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-rw-r--r--drivers/tty/serial/Kconfig2
-rw-r--r--drivers/tty/serial/sh-sci.c30
-rw-r--r--drivers/tty/serial/sh-sci.h103
3 files changed, 14 insertions, 121 deletions
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 636144cea932..1c0cd2d26d37 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -974,7 +974,7 @@ config SERIAL_IP22_ZILOG_CONSOLE
974 974
975config SERIAL_SH_SCI 975config SERIAL_SH_SCI
976 tristate "SuperH SCI(F) serial port support" 976 tristate "SuperH SCI(F) serial port support"
977 depends on HAVE_CLK && (SUPERH || H8300 || ARCH_SHMOBILE) 977 depends on HAVE_CLK && (SUPERH || ARCH_SHMOBILE)
978 select SERIAL_CORE 978 select SERIAL_CORE
979 979
980config SERIAL_SH_SCI_NR_UARTS 980config SERIAL_SH_SCI_NR_UARTS
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index ebd8629c108d..280c02af0eae 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -54,10 +54,6 @@
54#include <asm/sh_bios.h> 54#include <asm/sh_bios.h>
55#endif 55#endif
56 56
57#ifdef CONFIG_H8300
58#include <asm/gpio.h>
59#endif
60
61#include "sh-sci.h" 57#include "sh-sci.h"
62 58
63struct sci_port { 59struct sci_port {
@@ -164,23 +160,7 @@ static void sci_poll_put_char(struct uart_port *port, unsigned char c)
164} 160}
165#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 161#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
166 162
167#if defined(__H8300H__) || defined(__H8300S__) 163#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
168static void sci_init_pins(struct uart_port *port, unsigned int cflag)
169{
170 int ch = (port->mapbase - SMR0) >> 3;
171
172 /* set DDR regs */
173 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
174 h8300_sci_pins[ch].rx,
175 H8300_GPIO_INPUT);
176 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
177 h8300_sci_pins[ch].tx,
178 H8300_GPIO_OUTPUT);
179
180 /* tx mark output*/
181 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
182}
183#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
184static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) 164static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
185{ 165{
186 if (port->mapbase == 0xA4400000) { 166 if (port->mapbase == 0xA4400000) {
@@ -1863,14 +1843,8 @@ static int __devinit serial_console_setup(struct console *co, char *options)
1863 if (options) 1843 if (options)
1864 uart_parse_options(options, &baud, &parity, &bits, &flow); 1844 uart_parse_options(options, &baud, &parity, &bits, &flow);
1865 1845
1866 ret = uart_set_options(port, co, baud, parity, bits, flow);
1867#if defined(__H8300H__) || defined(__H8300S__)
1868 /* disable rx interrupt */
1869 if (ret == 0)
1870 sci_stop_rx(port);
1871#endif
1872 /* TODO: disable clock */ 1846 /* TODO: disable clock */
1873 return ret; 1847 return uart_set_options(port, co, baud, parity, bits, flow);
1874} 1848}
1875 1849
1876static struct console serial_console = { 1850static struct console serial_console = {
diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
index b04d937c9110..4dc249ecc59f 100644
--- a/drivers/tty/serial/sh-sci.h
+++ b/drivers/tty/serial/sh-sci.h
@@ -2,13 +2,6 @@
2#include <linux/io.h> 2#include <linux/io.h>
3#include <linux/gpio.h> 3#include <linux/gpio.h>
4 4
5#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6#include <asm/regs306x.h>
7#endif
8#if defined(CONFIG_H8S2678)
9#include <asm/regs267x.h>
10#endif
11
12#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 5#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 6 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \ 7 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
@@ -72,10 +65,6 @@
72#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 65#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
73# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 66# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
74# define SCIF_ORER 0x0001 /* overrun error bit */ 67# define SCIF_ORER 0x0001 /* overrun error bit */
75#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
76# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
77#elif defined(CONFIG_H8S2678)
78# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
79#elif defined(CONFIG_CPU_SUBTYPE_SH7757) 68#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
80# define SCSPTR0 0xfe4b0020 69# define SCSPTR0 0xfe4b0020
81# define SCIF_ORER 0x0001 70# define SCIF_ORER 0x0001
@@ -223,17 +212,6 @@
223 } \ 212 } \
224 } 213 }
225 214
226#ifdef CONFIG_H8300
227/* h8300 don't have SCIF */
228#define CPU_SCIF_FNS(name) \
229 static inline unsigned int sci_##name##_in(struct uart_port *port) \
230 { \
231 return 0; \
232 } \
233 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
234 { \
235 }
236#else
237#define CPU_SCIF_FNS(name, scif_offset, scif_size) \ 215#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
238 static inline unsigned int sci_##name##_in(struct uart_port *port) \ 216 static inline unsigned int sci_##name##_in(struct uart_port *port) \
239 { \ 217 { \
@@ -243,7 +221,6 @@
243 { \ 221 { \
244 SCI_OUT(scif_size, scif_offset, value); \ 222 SCI_OUT(scif_size, scif_offset, value); \
245 } 223 }
246#endif
247 224
248#define CPU_SCI_FNS(name, sci_offset, sci_size) \ 225#define CPU_SCI_FNS(name, sci_offset, sci_size) \
249 static inline unsigned int sci_##name##_in(struct uart_port* port) \ 226 static inline unsigned int sci_##name##_in(struct uart_port* port) \
@@ -262,8 +239,7 @@
262 defined(CONFIG_ARCH_SH7372) 239 defined(CONFIG_ARCH_SH7372)
263#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 240#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
264#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 241#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
265 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 242 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
266 h8_sci_offset, h8_sci_size) \
267 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) 243 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
268#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 244#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
269 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 245 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
@@ -282,19 +258,11 @@
282 CPU_SCIF_FNS(name, scif_offset, scif_size) 258 CPU_SCIF_FNS(name, scif_offset, scif_size)
283#else 259#else
284#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 260#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
285 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 261 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
286 h8_sci_offset, h8_sci_size) \
287 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size) 262 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
288#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 263#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
289 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) 264 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
290#endif 265#endif
291#elif defined(__H8300H__) || defined(__H8300S__)
292#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
293 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
294 h8_sci_offset, h8_sci_size) \
295 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
296#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
297 CPU_SCIF_FNS(name)
298#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ 266#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
299 defined(CONFIG_CPU_SUBTYPE_SH7724) 267 defined(CONFIG_CPU_SUBTYPE_SH7724)
300 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \ 268 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
@@ -303,8 +271,7 @@
303 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 271 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
304#else 272#else
305#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 273#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
306 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 274 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
307 h8_sci_offset, h8_sci_size) \
308 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) 275 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
309#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 276#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
310 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 277 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
@@ -353,14 +320,14 @@ SCIF_FNS(SCFCR, 0x18, 16)
353SCIF_FNS(SCFDR, 0x1c, 16) 320SCIF_FNS(SCFDR, 0x1c, 16)
354SCIF_FNS(SCLSR, 0x24, 16) 321SCIF_FNS(SCLSR, 0x24, 16)
355#else 322#else
356/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ 323/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 */
357/* name off sz off sz off sz off sz off sz*/ 324/* name off sz off sz off sz off sz */
358SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) 325SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16)
359SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) 326SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8)
360SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) 327SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16)
361SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) 328SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8)
362SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) 329SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16)
363SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) 330SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8)
364SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) 331SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
365#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ 332#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
366 defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 333 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
@@ -390,48 +357,6 @@ SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
390#define sci_in(port, reg) sci_##reg##_in(port) 357#define sci_in(port, reg) sci_##reg##_in(port)
391#define sci_out(port, reg, value) sci_##reg##_out(port, value) 358#define sci_out(port, reg, value) sci_##reg##_out(port, value)
392 359
393/* H8/300 series SCI pins assignment */
394#if defined(__H8300H__) || defined(__H8300S__)
395static const struct __attribute__((packed)) {
396 int port; /* GPIO port no */
397 unsigned short rx,tx; /* GPIO bit no */
398} h8300_sci_pins[] = {
399#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
400 { /* SCI0 */
401 .port = H8300_GPIO_P9,
402 .rx = H8300_GPIO_B2,
403 .tx = H8300_GPIO_B0,
404 },
405 { /* SCI1 */
406 .port = H8300_GPIO_P9,
407 .rx = H8300_GPIO_B3,
408 .tx = H8300_GPIO_B1,
409 },
410 { /* SCI2 */
411 .port = H8300_GPIO_PB,
412 .rx = H8300_GPIO_B7,
413 .tx = H8300_GPIO_B6,
414 }
415#elif defined(CONFIG_H8S2678)
416 { /* SCI0 */
417 .port = H8300_GPIO_P3,
418 .rx = H8300_GPIO_B2,
419 .tx = H8300_GPIO_B0,
420 },
421 { /* SCI1 */
422 .port = H8300_GPIO_P3,
423 .rx = H8300_GPIO_B3,
424 .tx = H8300_GPIO_B1,
425 },
426 { /* SCI2 */
427 .port = H8300_GPIO_P5,
428 .rx = H8300_GPIO_B1,
429 .tx = H8300_GPIO_B0,
430 }
431#endif
432};
433#endif
434
435#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 360#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
436 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 361 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
437 defined(CONFIG_CPU_SUBTYPE_SH7708) || \ 362 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
@@ -454,12 +379,6 @@ static inline int sci_rxd_in(struct uart_port *port)
454 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ 379 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
455 return 1; 380 return 1;
456} 381}
457#elif defined(__H8300H__) || defined(__H8300S__)
458static inline int sci_rxd_in(struct uart_port *port)
459{
460 int ch = (port->mapbase - SMR0) >> 3;
461 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
462}
463#else /* default case for non-SCI processors */ 382#else /* default case for non-SCI processors */
464static inline int sci_rxd_in(struct uart_port *port) 383static inline int sci_rxd_in(struct uart_port *port)
465{ 384{