3 files changed, 29 insertions, 27 deletions

diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
index c07455d1695f..bffcf455c857 100644
--- a/arch/x86/kernel/pci-gart_64.c
+++ b/arch/x86/kernel/pci-gart_64.c
@@ -598,13 +598,13 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
                 dev = k8_northbridges[i];
                 gatt_reg = __pa(gatt) >> 12;
                 gatt_reg <<= 4;
-                pci_write_config_dword(dev, 0x98, gatt_reg);
-                pci_read_config_dword(dev, 0x90, &ctl);
+                pci_write_config_dword(dev, AMD64_GARTTABLEBASE, gatt_reg);
+                pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
 
-                ctl |= 1;
-                ctl &= ~((1<<4) | (1<<5));
+                ctl |= GARTEN;
+                ctl &= ~(DISGARTCPU | DISGARTIO);
 
-                pci_write_config_dword(dev, 0x90, ctl);
+                pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
         }
         flush_gart();
 
diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c
index d8200ac8f8cb..25d64224cdbb 100644
--- a/drivers/char/agp/amd64-agp.c
+++ b/drivers/char/agp/amd64-agp.c
@@ -16,28 +16,9 @@
 #include <asm/page.h>           /* PAGE_SIZE */
 #include <asm/e820.h>
 #include <asm/k8.h>
+#include <asm/gart.h>
 #include "agp.h"
 
-/* PTE bits. */
-#define GPTE_VALID      1
-#define GPTE_COHERENT   2
-
-/* Aperture control register bits. */
-#define GARTEN          (1<<0)
-#define DISGARTCPU      (1<<4)
-#define DISGARTIO       (1<<5)
-
-/* GART cache control register bits. */
-#define INVGART         (1<<0)
-#define GARTPTEERR      (1<<1)
-
-/* K8 On-cpu GART registers */
-#define AMD64_GARTAPERTURECTL   0x90
-#define AMD64_GARTAPERTUREBASE  0x94
-#define AMD64_GARTTABLEBASE     0x98
-#define AMD64_GARTCACHECTL      0x9c
-#define AMD64_GARTEN            (1<<0)
-
 /* NVIDIA K8 registers */
 #define NVIDIA_X86_64_0_APBASE          0x10
 #define NVIDIA_X86_64_1_APBASE1         0x50
@@ -165,7 +146,7 @@ static int amd64_fetch_size(void)
  * In a multiprocessor x86-64 system, this function gets
  * called once for each CPU.
  */
-static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table)
+static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
 {
         u64 aperturebase;
         u32 tmp;
@@ -181,7 +162,7 @@ static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table)
         addr >>= 12;
         tmp = (u32) addr<<4;
         tmp &= ~0xf;
-        pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp);
+        pci_write_config_dword(hammer, AMD64_GARTTABLEBASE, tmp);
 
         /* Enable GART translation for this hammer. */
         pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp);
diff --git a/include/asm-x86/gart.h b/include/asm-x86/gart.h
index 90958ed993fa..248e5778e928 100644
--- a/include/asm-x86/gart.h
+++ b/include/asm-x86/gart.h
@@ -5,6 +5,7 @@ extern void pci_iommu_shutdown(void);
 extern void no_iommu_init(void);
 extern int force_iommu, no_iommu;
 extern int iommu_detected;
+extern int agp_amd64_init(void);
 #ifdef CONFIG_GART_IOMMU
 extern void gart_iommu_init(void);
 extern void gart_iommu_shutdown(void);
@@ -31,4 +32,24 @@ static inline void gart_iommu_shutdown(void)
 
 #endif
 
+/* PTE bits. */
+#define GPTE_VALID      1
+#define GPTE_COHERENT   2
+
+/* Aperture control register bits. */
+#define GARTEN          (1<<0)
+#define DISGARTCPU      (1<<4)
+#define DISGARTIO       (1<<5)
+
+/* GART cache control register bits. */
+#define INVGART         (1<<0)
+#define GARTPTEERR      (1<<1)
+
+/* K8 On-cpu GART registers */
+#define AMD64_GARTAPERTURECTL   0x90
+#define AMD64_GARTAPERTUREBASE  0x94
+#define AMD64_GARTTABLEBASE     0x98
+#define AMD64_GARTCACHECTL      0x9c
+#define AMD64_GARTEN            (1<<0)
+
 #endif