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-rw-r--r--MAINTAINERS28
-rw-r--r--arch/arm/common/sa1111.c2
-rw-r--r--arch/arm/mach-pxa/clock.c30
-rw-r--r--arch/arm/mach-pxa/clock.h9
-rw-r--r--arch/arm/mach-pxa/cm-x270-pci.c27
-rw-r--r--arch/arm/mach-pxa/cm-x270-pci.h14
-rw-r--r--arch/arm/mach-pxa/cm-x270.c403
-rw-r--r--arch/arm/mach-pxa/em-x270.c371
-rw-r--r--arch/arm/mach-pxa/pxa25x.c59
-rw-r--r--arch/arm/mach-sa1100/clock.c2
-rw-r--r--drivers/mtd/nand/cmx270_nand.c79
-rw-r--r--drivers/pcmcia/pxa2xx_cm_x270.c93
-rw-r--r--include/asm-arm/arch-pxa/cm-x270.h50
-rw-r--r--include/asm-arm/arch-pxa/hardware.h12
14 files changed, 767 insertions, 412 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 8a5ffef66976..3b228e2d12e6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -475,28 +475,34 @@ M: kernel@wantstofly.org
475L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) 475L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
476S: Maintained 476S: Maintained
477 477
478ARM/COMPULAB CM-X270/EM-X270 MACHINE SUPPORT
479P: Mike Rapoport
480M: mike@compulab.co.il
481L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
482S: Maintained
483
478ARM/CORGI MACHINE SUPPORT 484ARM/CORGI MACHINE SUPPORT
479P: Richard Purdie 485P: Richard Purdie
480M: rpurdie@rpsys.net 486M: rpurdie@rpsys.net
481S: Maintained 487S: Maintained
482 488
489ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6)
490P: Daniel Ribeiro
491M: drwyrm@gmail.com
492P: Stefan Schmidt
493M: stefan@openezx.org
494P: Harald Welte
495M: laforge@openezx.org
496L: openezx-devel@lists.openezx.org (subscribers-only)
497W: http://www.openezx.org/
498S: Maintained
499
483ARM/GLOMATION GESBC9312SX MACHINE SUPPORT 500ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
484P: Lennert Buytenhek 501P: Lennert Buytenhek
485M: kernel@wantstofly.org 502M: kernel@wantstofly.org
486L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) 503L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
487S: Maintained 504S: Maintained
488 505
489ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6)
490P: Daniel Ribeiro
491M: drwyrm@gmail.com
492P: Stefan Schmidt
493M: stefan@openezx.org
494P: Harald Welte
495M: laforge@openezx.org
496L: openezx-devel@lists.openezx.org (subscribers-only)
497W: http://www.openezx.org/
498S: Maintained
499
500ARM/GUMSTIX MACHINE SUPPORT 506ARM/GUMSTIX MACHINE SUPPORT
501P: Steve Sakoman 507P: Steve Sakoman
502M: sakoman@gmail.com 508M: sakoman@gmail.com
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index eb06d0b2cb74..79fa71d990b5 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -627,7 +627,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
627 if (!sachip) 627 if (!sachip)
628 return -ENOMEM; 628 return -ENOMEM;
629 629
630 sachip->clk = clk_get(me, "GPIO27_CLK"); 630 sachip->clk = clk_get(me, "SA1111_CLK");
631 if (!sachip->clk) { 631 if (!sachip->clk) {
632 ret = PTR_ERR(sachip->clk); 632 ret = PTR_ERR(sachip->clk);
633 goto err_free; 633 goto err_free;
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index b4d04955dcb0..630063ffa6fc 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -101,21 +101,6 @@ unsigned long clk_get_rate(struct clk *clk)
101EXPORT_SYMBOL(clk_get_rate); 101EXPORT_SYMBOL(clk_get_rate);
102 102
103 103
104static void clk_gpio27_enable(struct clk *clk)
105{
106 pxa_gpio_mode(GPIO11_3_6MHz_MD);
107}
108
109static void clk_gpio27_disable(struct clk *clk)
110{
111}
112
113static const struct clkops clk_gpio27_ops = {
114 .enable = clk_gpio27_enable,
115 .disable = clk_gpio27_disable,
116};
117
118
119void clk_cken_enable(struct clk *clk) 104void clk_cken_enable(struct clk *clk)
120{ 105{
121 CKEN |= 1 << clk->cken; 106 CKEN |= 1 << clk->cken;
@@ -131,14 +116,6 @@ const struct clkops clk_cken_ops = {
131 .disable = clk_cken_disable, 116 .disable = clk_cken_disable,
132}; 117};
133 118
134static struct clk common_clks[] = {
135 {
136 .name = "GPIO27_CLK",
137 .ops = &clk_gpio27_ops,
138 .rate = 3686400,
139 },
140};
141
142void clks_register(struct clk *clks, size_t num) 119void clks_register(struct clk *clks, size_t num)
143{ 120{
144 int i; 121 int i;
@@ -148,10 +125,3 @@ void clks_register(struct clk *clks, size_t num)
148 list_add(&clks[i].node, &clocks); 125 list_add(&clks[i].node, &clocks);
149 mutex_unlock(&clocks_mutex); 126 mutex_unlock(&clocks_mutex);
150} 127}
151
152static int __init clk_init(void)
153{
154 clks_register(common_clks, ARRAY_SIZE(common_clks));
155 return 0;
156}
157arch_initcall(clk_init);
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index 83cbfaba485d..32d0c074b351 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -47,6 +47,15 @@ struct clk {
47 .other = _other, \ 47 .other = _other, \
48 } 48 }
49 49
50#define INIT_CLK(_name, _ops, _rate, _delay, _dev) \
51 { \
52 .name = _name, \
53 .dev = _dev, \
54 .ops = _ops, \
55 .rate = _rate, \
56 .delay = _delay, \
57 }
58
50extern const struct clkops clk_cken_ops; 59extern const struct clkops clk_cken_ops;
51 60
52void clk_cken_enable(struct clk *clk); 61void clk_cken_enable(struct clk *clk);
diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c
index 319c9ff3ab9a..bcf0cde6ccc9 100644
--- a/arch/arm/mach-pxa/cm-x270-pci.c
+++ b/arch/arm/mach-pxa/cm-x270-pci.c
@@ -5,7 +5,7 @@
5 * 5 *
6 * Bits taken from various places. 6 * Bits taken from various places.
7 * 7 *
8 * Copyright (C) 2007 Compulab, Ltd. 8 * Copyright (C) 2007, 2008 Compulab, Ltd.
9 * Mike Rapoport <mike@compulab.co.il> 9 * Mike Rapoport <mike@compulab.co.il>
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
@@ -19,16 +19,16 @@
19#include <linux/device.h> 19#include <linux/device.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/irq.h> 21#include <linux/irq.h>
22#include <linux/gpio.h>
22 23
23#include <asm/mach/pci.h> 24#include <asm/mach/pci.h>
24#include <asm/arch/cm-x270.h>
25#include <asm/arch/pxa-regs.h> 25#include <asm/arch/pxa-regs.h>
26#include <asm/arch/pxa2xx-gpio.h>
27#include <asm/mach-types.h> 26#include <asm/mach-types.h>
28 27
29#include <asm/hardware/it8152.h> 28#include <asm/hardware/it8152.h>
30 29
31unsigned long it8152_base_address = CMX270_IT8152_VIRT; 30unsigned long it8152_base_address;
31static int cmx270_it8152_irq_gpio;
32 32
33/* 33/*
34 * Only first 64MB of memory can be accessed via PCI. 34 * Only first 64MB of memory can be accessed via PCI.
@@ -42,7 +42,7 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
42 unsigned int sz = SZ_64M >> PAGE_SHIFT; 42 unsigned int sz = SZ_64M >> PAGE_SHIFT;
43 43
44 if (machine_is_armcore()) { 44 if (machine_is_armcore()) {
45 pr_info("Adjusting zones for CM-x270\n"); 45 pr_info("Adjusting zones for CM-X270\n");
46 46
47 /* 47 /*
48 * Only adjust if > 64M on current system 48 * Only adjust if > 64M on current system
@@ -60,19 +60,20 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
60static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) 60static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
61{ 61{
62 /* clear our parent irq */ 62 /* clear our parent irq */
63 GEDR(GPIO_IT8152_IRQ) = GPIO_bit(GPIO_IT8152_IRQ); 63 GEDR(cmx270_it8152_irq_gpio) = GPIO_bit(cmx270_it8152_irq_gpio);
64 64
65 it8152_irq_demux(irq, desc); 65 it8152_irq_demux(irq, desc);
66} 66}
67 67
68void __cmx270_pci_init_irq(void) 68void __cmx270_pci_init_irq(int irq_gpio)
69{ 69{
70 it8152_init_irq(); 70 it8152_init_irq();
71 pxa_gpio_mode(IRQ_TO_GPIO(GPIO_IT8152_IRQ));
72 set_irq_type(IRQ_GPIO(GPIO_IT8152_IRQ), IRQT_RISING);
73 71
74 set_irq_chained_handler(IRQ_GPIO(GPIO_IT8152_IRQ), 72 cmx270_it8152_irq_gpio = irq_gpio;
75 cmx270_it8152_irq_demux); 73
74 set_irq_type(gpio_to_irq(irq_gpio), IRQT_RISING);
75
76 set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx270_it8152_irq_demux);
76} 77}
77 78
78#ifdef CONFIG_PM 79#ifdef CONFIG_PM
@@ -115,8 +116,8 @@ static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
115 116
116 /* 117 /*
117 Here comes the ugly part. The routing is baseboard specific, 118 Here comes the ugly part. The routing is baseboard specific,
118 but defining a platform for each possible base of CM-x270 is 119 but defining a platform for each possible base of CM-X270 is
119 unrealistic. Here we keep mapping for ATXBase and SB-x270. 120 unrealistic. Here we keep mapping for ATXBase and SB-X270.
120 */ 121 */
121 /* ATXBASE PCI slot */ 122 /* ATXBASE PCI slot */
122 if (slot == 7) 123 if (slot == 7)
diff --git a/arch/arm/mach-pxa/cm-x270-pci.h b/arch/arm/mach-pxa/cm-x270-pci.h
index ffe37b66f9a0..48f532f4cb51 100644
--- a/arch/arm/mach-pxa/cm-x270-pci.h
+++ b/arch/arm/mach-pxa/cm-x270-pci.h
@@ -1,13 +1,13 @@
1extern void __cmx270_pci_init_irq(void); 1extern void __cmx270_pci_init_irq(int irq_gpio);
2extern void __cmx270_pci_suspend(void); 2extern void __cmx270_pci_suspend(void);
3extern void __cmx270_pci_resume(void); 3extern void __cmx270_pci_resume(void);
4 4
5#ifdef CONFIG_PCI 5#ifdef CONFIG_PCI
6#define cmx270_pci_init_irq __cmx270_pci_init_irq 6#define cmx270_pci_init_irq(x) __cmx270_pci_init_irq(x)
7#define cmx270_pci_suspend __cmx270_pci_suspend 7#define cmx270_pci_suspend(x) __cmx270_pci_suspend(x)
8#define cmx270_pci_resume __cmx270_pci_resume 8#define cmx270_pci_resume(x) __cmx270_pci_resume(x)
9#else 9#else
10#define cmx270_pci_init_irq() do {} while (0) 10#define cmx270_pci_init_irq(x) do {} while (0)
11#define cmx270_pci_suspend() do {} while (0) 11#define cmx270_pci_suspend(x) do {} while (0)
12#define cmx270_pci_resume() do {} while (0) 12#define cmx270_pci_resume(x) do {} while (0)
13#endif 13#endif
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index 01b9964acec1..402e807eae54 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/mach-pxa/cm-x270.c 2 * linux/arch/arm/mach-pxa/cm-x270.c
3 * 3 *
4 * Copyright (C) 2007 CompuLab, Ltd. 4 * Copyright (C) 2007, 2008 CompuLab, Ltd.
5 * Mike Rapoport <mike@compulab.co.il> 5 * Mike Rapoport <mike@compulab.co.il>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
@@ -9,44 +9,156 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include <linux/types.h>
13#include <linux/pm.h>
14#include <linux/fb.h>
15#include <linux/platform_device.h> 12#include <linux/platform_device.h>
16#include <linux/irq.h>
17#include <linux/sysdev.h> 13#include <linux/sysdev.h>
18#include <linux/io.h> 14#include <linux/irq.h>
19#include <linux/delay.h> 15#include <linux/gpio.h>
20 16
21#include <linux/dm9000.h> 17#include <linux/dm9000.h>
22#include <linux/rtc-v3020.h> 18#include <linux/rtc-v3020.h>
23#include <linux/serial_8250.h>
24
25#include <video/mbxfb.h> 19#include <video/mbxfb.h>
20#include <linux/leds.h>
26 21
27#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
28#include <asm/mach-types.h> 23#include <asm/mach-types.h>
29#include <asm/mach/map.h> 24#include <asm/mach/map.h>
30 25
31#include <asm/arch/pxa-regs.h>
32#include <asm/arch/pxa2xx-regs.h> 26#include <asm/arch/pxa2xx-regs.h>
33#include <asm/arch/pxa2xx-gpio.h> 27#include <asm/arch/mfp-pxa27x.h>
28#include <asm/arch/pxa-regs.h>
34#include <asm/arch/audio.h> 29#include <asm/arch/audio.h>
35#include <asm/arch/pxafb.h> 30#include <asm/arch/pxafb.h>
36#include <asm/arch/ohci.h> 31#include <asm/arch/ohci.h>
37#include <asm/arch/mmc.h> 32#include <asm/arch/mmc.h>
38#include <asm/arch/bitfield.h> 33#include <asm/arch/bitfield.h>
39#include <asm/arch/cm-x270.h>
40 34
41#include <asm/hardware/it8152.h> 35#include <asm/hardware/it8152.h>
42 36
43#include "generic.h" 37#include "generic.h"
44#include "cm-x270-pci.h" 38#include "cm-x270-pci.h"
45 39
40/* virtual addresses for statically mapped regions */
41#define CMX270_VIRT_BASE (0xe8000000)
42#define CMX270_IT8152_VIRT (CMX270_VIRT_BASE)
43
46#define RTC_PHYS_BASE (PXA_CS1_PHYS + (5 << 22)) 44#define RTC_PHYS_BASE (PXA_CS1_PHYS + (5 << 22))
47#define DM9000_PHYS_BASE (PXA_CS1_PHYS + (6 << 22)) 45#define DM9000_PHYS_BASE (PXA_CS1_PHYS + (6 << 22))
48 46
49static struct resource cmx270_dm9k_resource[] = { 47/* GPIO IRQ usage */
48#define GPIO10_ETHIRQ (10)
49#define GPIO22_IT8152_IRQ (22)
50#define GPIO83_MMC_IRQ (83)
51#define GPIO95_GFXIRQ (95)
52
53#define CMX270_ETHIRQ IRQ_GPIO(GPIO10_ETHIRQ)
54#define CMX270_IT8152_IRQ IRQ_GPIO(GPIO22_IT8152_IRQ)
55#define CMX270_MMC_IRQ IRQ_GPIO(GPIO83_MMC_IRQ)
56#define CMX270_GFXIRQ IRQ_GPIO(GPIO95_GFXIRQ)
57
58/* MMC power enable */
59#define GPIO105_MMC_POWER (105)
60
61static unsigned long cmx270_pin_config[] = {
62 /* AC'97 */
63 GPIO28_AC97_BITCLK,
64 GPIO29_AC97_SDATA_IN_0,
65 GPIO30_AC97_SDATA_OUT,
66 GPIO31_AC97_SYNC,
67 GPIO98_AC97_SYSCLK,
68 GPIO113_AC97_nRESET,
69
70 /* BTUART */
71 GPIO42_BTUART_RXD,
72 GPIO43_BTUART_TXD,
73 GPIO44_BTUART_CTS,
74 GPIO45_BTUART_RTS,
75
76 /* STUART */
77 GPIO46_STUART_RXD,
78 GPIO47_STUART_TXD,
79
80 /* MCI controller */
81 GPIO32_MMC_CLK,
82 GPIO112_MMC_CMD,
83 GPIO92_MMC_DAT_0,
84 GPIO109_MMC_DAT_1,
85 GPIO110_MMC_DAT_2,
86 GPIO111_MMC_DAT_3,
87
88 /* LCD */
89 GPIO58_LCD_LDD_0,
90 GPIO59_LCD_LDD_1,
91 GPIO60_LCD_LDD_2,
92 GPIO61_LCD_LDD_3,
93 GPIO62_LCD_LDD_4,
94 GPIO63_LCD_LDD_5,
95 GPIO64_LCD_LDD_6,
96 GPIO65_LCD_LDD_7,
97 GPIO66_LCD_LDD_8,
98 GPIO67_LCD_LDD_9,
99 GPIO68_LCD_LDD_10,
100 GPIO69_LCD_LDD_11,
101 GPIO70_LCD_LDD_12,
102 GPIO71_LCD_LDD_13,
103 GPIO72_LCD_LDD_14,
104 GPIO73_LCD_LDD_15,
105 GPIO74_LCD_FCLK,
106 GPIO75_LCD_LCLK,
107 GPIO76_LCD_PCLK,
108 GPIO77_LCD_BIAS,
109
110 /* I2C */
111 GPIO117_I2C_SCL,
112 GPIO118_I2C_SDA,
113
114 /* SSP1 */
115 GPIO23_SSP1_SCLK,
116 GPIO24_SSP1_SFRM,
117 GPIO25_SSP1_TXD,
118 GPIO26_SSP1_RXD,
119
120 /* SSP2 */
121 GPIO19_SSP2_SCLK,
122 GPIO14_SSP2_SFRM,
123 GPIO87_SSP2_TXD,
124 GPIO88_SSP2_RXD,
125
126 /* PC Card */
127 GPIO48_nPOE,
128 GPIO49_nPWE,
129 GPIO50_nPIOR,
130 GPIO51_nPIOW,
131 GPIO85_nPCE_1,
132 GPIO54_nPCE_2,
133 GPIO55_nPREG,
134 GPIO56_nPWAIT,
135 GPIO57_nIOIS16,
136
137 /* SDRAM and local bus */
138 GPIO15_nCS_1,
139 GPIO78_nCS_2,
140 GPIO79_nCS_3,
141 GPIO80_nCS_4,
142 GPIO33_nCS_5,
143 GPIO49_nPWE,
144 GPIO18_RDY,
145
146 /* GPIO */
147 GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH,
148 GPIO105_GPIO | MFP_LPM_DRIVE_HIGH, /* MMC/SD power */
149 GPIO53_GPIO, /* PC card reset */
150
151 /* NAND controls */
152 GPIO11_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */
153 GPIO89_GPIO, /* NAND Ready/Busy */
154
155 /* interrupts */
156 GPIO10_GPIO, /* DM9000 interrupt */
157 GPIO83_GPIO, /* MMC card detect */
158};
159
160#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
161static struct resource cmx270_dm9000_resource[] = {
50 [0] = { 162 [0] = {
51 .start = DM9000_PHYS_BASE, 163 .start = DM9000_PHYS_BASE,
52 .end = DM9000_PHYS_BASE + 4, 164 .end = DM9000_PHYS_BASE + 4,
@@ -64,31 +176,45 @@ static struct resource cmx270_dm9k_resource[] = {
64 } 176 }
65}; 177};
66 178
67/* for the moment we limit ourselves to 32bit IO until some 179static struct dm9000_plat_data cmx270_dm9000_platdata = {
68 * better IO routines can be written and tested
69 */
70static struct dm9000_plat_data cmx270_dm9k_platdata = {
71 .flags = DM9000_PLATF_32BITONLY, 180 .flags = DM9000_PLATF_32BITONLY,
72}; 181};
73 182
74/* Ethernet device */ 183static struct platform_device cmx270_dm9000_device = {
75static struct platform_device cmx270_device_dm9k = {
76 .name = "dm9000", 184 .name = "dm9000",
77 .id = 0, 185 .id = 0,
78 .num_resources = ARRAY_SIZE(cmx270_dm9k_resource), 186 .num_resources = ARRAY_SIZE(cmx270_dm9000_resource),
79 .resource = cmx270_dm9k_resource, 187 .resource = cmx270_dm9000_resource,
80 .dev = { 188 .dev = {
81 .platform_data = &cmx270_dm9k_platdata, 189 .platform_data = &cmx270_dm9000_platdata,
82 } 190 }
83}; 191};
84 192
85/* touchscreen controller */ 193static void __init cmx270_init_dm9000(void)
194{
195 platform_device_register(&cmx270_dm9000_device);
196}
197#else
198static inline void cmx270_init_dm9000(void) {}
199#endif
200
201/* UCB1400 touchscreen controller */
202#if defined(CONFIG_TOUCHSCREEN_UCB1400) || defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
86static struct platform_device cmx270_ts_device = { 203static struct platform_device cmx270_ts_device = {
87 .name = "ucb1400_ts", 204 .name = "ucb1400_ts",
88 .id = -1, 205 .id = -1,
89}; 206};
90 207
91/* RTC */ 208static void __init cmx270_init_touchscreen(void)
209{
210 platform_device_register(&cmx270_ts_device);
211}
212#else
213static inline void cmx270_init_touchscreen(void) {}
214#endif
215
216/* V3020 RTC */
217#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
92static struct resource cmx270_v3020_resource[] = { 218static struct resource cmx270_v3020_resource[] = {
93 [0] = { 219 [0] = {
94 .start = RTC_PHYS_BASE, 220 .start = RTC_PHYS_BASE,
@@ -111,28 +237,67 @@ static struct platform_device cmx270_rtc_device = {
111 } 237 }
112}; 238};
113 239
114/* 240static void __init cmx270_init_rtc(void)
115 * CM-X270 LEDs 241{
116 */ 242 platform_device_register(&cmx270_rtc_device);
243}
244#else
245static inline void cmx270_init_rtc(void) {}
246#endif
247
248/* CM-X270 LEDs */
249#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
250static struct gpio_led cmx270_leds[] = {
251 [0] = {
252 .name = "cm-x270:red",
253 .default_trigger = "nand-disk",
254 .gpio = 93,
255 .active_low = 1,
256 },
257 [1] = {
258 .name = "cm-x270:green",
259 .default_trigger = "heartbeat",
260 .gpio = 94,
261 .active_low = 1,
262 },
263};
264
265static struct gpio_led_platform_data cmx270_gpio_led_pdata = {
266 .num_leds = ARRAY_SIZE(cmx270_leds),
267 .leds = cmx270_leds,
268};
269
117static struct platform_device cmx270_led_device = { 270static struct platform_device cmx270_led_device = {
118 .name = "cm-x270-led", 271 .name = "leds-gpio",
119 .id = -1, 272 .id = -1,
273 .dev = {
274 .platform_data = &cmx270_gpio_led_pdata,
275 },
120}; 276};
121 277
278static void __init cmx270_init_leds(void)
279{
280 platform_device_register(&cmx270_led_device);
281}
282#else
283static inline void cmx270_init_leds(void) {}
284#endif
285
122/* 2700G graphics */ 286/* 2700G graphics */
287#if defined(CONFIG_FB_MBX) || defined(CONFIG_FB_MBX_MODULE)
123static u64 fb_dma_mask = ~(u64)0; 288static u64 fb_dma_mask = ~(u64)0;
124 289
125static struct resource cmx270_2700G_resource[] = { 290static struct resource cmx270_2700G_resource[] = {
126 /* frame buffer memory including ODFB and External SDRAM */ 291 /* frame buffer memory including ODFB and External SDRAM */
127 [0] = { 292 [0] = {
128 .start = MARATHON_PHYS, 293 .start = PXA_CS2_PHYS,
129 .end = MARATHON_PHYS + 0x02000000, 294 .end = PXA_CS2_PHYS + 0x01ffffff,
130 .flags = IORESOURCE_MEM, 295 .flags = IORESOURCE_MEM,
131 }, 296 },
132 /* Marathon registers */ 297 /* Marathon registers */
133 [1] = { 298 [1] = {
134 .start = MARATHON_PHYS + 0x03fe0000, 299 .start = PXA_CS2_PHYS + 0x03fe0000,
135 .end = MARATHON_PHYS + 0x03ffffff, 300 .end = PXA_CS2_PHYS + 0x03ffffff,
136 .flags = IORESOURCE_MEM, 301 .flags = IORESOURCE_MEM,
137 }, 302 },
138}; 303};
@@ -200,43 +365,15 @@ static struct platform_device cmx270_2700G = {
200 .id = -1, 365 .id = -1,
201}; 366};
202 367
203static u64 ata_dma_mask = ~(u64)0; 368static void __init cmx270_init_2700G(void)
204 369{
205static struct platform_device cmx270_ata = { 370 platform_device_register(&cmx270_2700G);
206 .name = "pata_cm_x270", 371}
207 .id = -1, 372#else
208 .dev = { 373static inline void cmx270_init_2700G(void) {}
209 .dma_mask = &ata_dma_mask, 374#endif
210 .coherent_dma_mask = 0xffffffff,
211 },
212};
213
214/* platform devices */
215static struct platform_device *platform_devices[] __initdata = {
216 &cmx270_device_dm9k,
217 &cmx270_rtc_device,
218 &cmx270_2700G,
219 &cmx270_led_device,
220 &cmx270_ts_device,
221 &cmx270_ata,
222};
223
224/* Map PCI companion and IDE/General Purpose CS statically */
225static struct map_desc cmx270_io_desc[] __initdata = {
226 [0] = { /* IDE/general purpose space */
227 .virtual = CMX270_IDE104_VIRT,
228 .pfn = __phys_to_pfn(CMX270_IDE104_PHYS),
229 .length = SZ_64M - SZ_8M,
230 .type = MT_DEVICE
231 },
232 [1] = { /* PCI bridge */
233 .virtual = CMX270_IT8152_VIRT,
234 .pfn = __phys_to_pfn(CMX270_IT8152_PHYS),
235 .length = SZ_64M,
236 .type = MT_DEVICE
237 },
238};
239 375
376#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
240/* 377/*
241 Display definitions 378 Display definitions
242 keep these for backwards compatibility, although symbolic names (as 379 keep these for backwards compatibility, although symbolic names (as
@@ -446,7 +583,16 @@ static int __init cmx270_set_display(char *str)
446*/ 583*/
447__setup("monitor=", cmx270_set_display); 584__setup("monitor=", cmx270_set_display);
448 585
586static void __init cmx270_init_display(void)
587{
588 set_pxa_fb_info(cmx270_display);
589}
590#else
591static inline void cmx270_init_display(void) {}
592#endif
593
449/* PXA27x OHCI controller setup */ 594/* PXA27x OHCI controller setup */
595#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
450static int cmx270_ohci_init(struct device *dev) 596static int cmx270_ohci_init(struct device *dev)
451{ 597{
452 /* Set the Power Control Polarity Low */ 598 /* Set the Power Control Polarity Low */
@@ -461,35 +607,37 @@ static struct pxaohci_platform_data cmx270_ohci_platform_data = {
461 .init = cmx270_ohci_init, 607 .init = cmx270_ohci_init,
462}; 608};
463 609
610static void __init cmx270_init_ohci(void)
611{
612 pxa_set_ohci_info(&cmx270_ohci_platform_data);
613}
614#else
615static inline void cmx270_init_ohci(void) {}
616#endif
464 617
618#if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
465static int cmx270_mci_init(struct device *dev, 619static int cmx270_mci_init(struct device *dev,
466 irq_handler_t cmx270_detect_int, 620 irq_handler_t cmx270_detect_int,
467 void *data) 621 void *data)
468{ 622{
469 int err; 623 int err;
470 624
471 /* 625 err = gpio_request(GPIO105_MMC_POWER, "MMC/SD power");
472 * setup GPIO for PXA27x MMC controller 626 if (err) {
473 */ 627 dev_warn(dev, "power gpio unavailable\n");
474 pxa_gpio_mode(GPIO32_MMCCLK_MD); 628 return err;
475 pxa_gpio_mode(GPIO112_MMCCMD_MD); 629 }
476 pxa_gpio_mode(GPIO92_MMCDAT0_MD);
477 pxa_gpio_mode(GPIO109_MMCDAT1_MD);
478 pxa_gpio_mode(GPIO110_MMCDAT2_MD);
479 pxa_gpio_mode(GPIO111_MMCDAT3_MD);
480
481 /* SB-X270 uses GPIO105 as SD power enable */
482 pxa_gpio_mode(105 | GPIO_OUT);
483 630
484 /* card detect IRQ on GPIO 83 */ 631 gpio_direction_output(GPIO105_MMC_POWER, 0);
485 pxa_gpio_mode(IRQ_TO_GPIO(CMX270_MMC_IRQ));
486 632
487 err = request_irq(CMX270_MMC_IRQ, cmx270_detect_int, 633 err = request_irq(CMX270_MMC_IRQ, cmx270_detect_int,
488 IRQF_DISABLED | IRQF_TRIGGER_FALLING, 634 IRQF_DISABLED | IRQF_TRIGGER_FALLING,
489 "MMC card detect", data); 635 "MMC card detect", data);
490 if (err) 636 if (err) {
491 printk(KERN_ERR "cmx270_mci_init: MMC/SD: can't" 637 gpio_free(GPIO105_MMC_POWER);
492 " request MMC card detect IRQ\n"); 638 dev_err(dev, "cmx270_mci_init: MMC/SD: can't"
639 " request MMC card detect IRQ\n");
640 }
493 641
494 return err; 642 return err;
495} 643}
@@ -499,17 +647,18 @@ static void cmx270_mci_setpower(struct device *dev, unsigned int vdd)
499 struct pxamci_platform_data *p_d = dev->platform_data; 647 struct pxamci_platform_data *p_d = dev->platform_data;
500 648
501 if ((1 << vdd) & p_d->ocr_mask) { 649 if ((1 << vdd) & p_d->ocr_mask) {
502 printk(KERN_DEBUG "%s: on\n", __func__); 650 dev_dbg(dev, "power on\n");
503 GPCR(105) = GPIO_bit(105); 651 gpio_set_value(GPIO105_MMC_POWER, 0);
504 } else { 652 } else {
505 GPSR(105) = GPIO_bit(105); 653 gpio_set_value(GPIO105_MMC_POWER, 1);
506 printk(KERN_DEBUG "%s: off\n", __func__); 654 dev_dbg(dev, "power off\n");
507 } 655 }
508} 656}
509 657
510static void cmx270_mci_exit(struct device *dev, void *data) 658static void cmx270_mci_exit(struct device *dev, void *data)
511{ 659{
512 free_irq(CMX270_MMC_IRQ, data); 660 free_irq(CMX270_MMC_IRQ, data);
661 gpio_free(GPIO105_MMC_POWER);
513} 662}
514 663
515static struct pxamci_platform_data cmx270_mci_platform_data = { 664static struct pxamci_platform_data cmx270_mci_platform_data = {
@@ -519,6 +668,14 @@ static struct pxamci_platform_data cmx270_mci_platform_data = {
519 .exit = cmx270_mci_exit, 668 .exit = cmx270_mci_exit,
520}; 669};
521 670
671static void __init cmx270_init_mmc(void)
672{
673 pxa_set_mci_info(&cmx270_mci_platform_data);
674}
675#else
676static inline void cmx270_init_mmc(void) {}
677#endif
678
522#ifdef CONFIG_PM 679#ifdef CONFIG_PM
523static unsigned long sleep_save_msc[10]; 680static unsigned long sleep_save_msc[10];
524 681
@@ -580,53 +737,63 @@ static int __init cmx270_pm_init(void)
580static int __init cmx270_pm_init(void) { return 0; } 737static int __init cmx270_pm_init(void) { return 0; }
581#endif 738#endif
582 739
583static void __init cmx270_init(void) 740#if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE)
741static void __init cmx270_init_ac97(void)
584{ 742{
585 cmx270_pm_init();
586
587 set_pxa_fb_info(cmx270_display);
588
589 /* register CM-X270 platform devices */
590 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
591 pxa_set_ac97_info(NULL); 743 pxa_set_ac97_info(NULL);
744}
745#else
746static inline void cmx270_init_ac97(void) {}
747#endif
592 748
593 /* set MCI and OHCI platform parameters */ 749static void __init cmx270_init(void)
594 pxa_set_mci_info(&cmx270_mci_platform_data); 750{
595 pxa_set_ohci_info(&cmx270_ohci_platform_data); 751 cmx270_pm_init();
596
597 /* This enables the STUART */
598 pxa_gpio_mode(GPIO46_STRXD_MD);
599 pxa_gpio_mode(GPIO47_STTXD_MD);
600 752
601 /* This enables the BTUART */ 753 pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx270_pin_config));
602 pxa_gpio_mode(GPIO42_BTRXD_MD); 754
603 pxa_gpio_mode(GPIO43_BTTXD_MD); 755 cmx270_init_dm9000();
604 pxa_gpio_mode(GPIO44_BTCTS_MD); 756 cmx270_init_rtc();
605 pxa_gpio_mode(GPIO45_BTRTS_MD); 757 cmx270_init_display();
758 cmx270_init_mmc();
759 cmx270_init_ohci();
760 cmx270_init_ac97();
761 cmx270_init_touchscreen();
762 cmx270_init_leds();
763 cmx270_init_2700G();
606} 764}
607 765
608static void __init cmx270_init_irq(void) 766static void __init cmx270_init_irq(void)
609{ 767{
610 pxa27x_init_irq(); 768 pxa27x_init_irq();
611 769
770 cmx270_pci_init_irq(GPIO22_IT8152_IRQ);
771}
612 772
613 cmx270_pci_init_irq(); 773#ifdef CONFIG_PCI
774/* Map PCI companion statically */
775static struct map_desc cmx270_io_desc[] __initdata = {
776 [0] = { /* PCI bridge */
777 .virtual = CMX270_IT8152_VIRT,
778 .pfn = __phys_to_pfn(PXA_CS4_PHYS),
779 .length = SZ_64M,
780 .type = MT_DEVICE
781 },
782};
614 783
615 /* Setup interrupt for dm9000 */ 784static void __init cmx270_map_io(void)
616 pxa_gpio_mode(IRQ_TO_GPIO(CMX270_ETHIRQ)); 785{
617 set_irq_type(CMX270_ETHIRQ, IRQT_RISING); 786 pxa_map_io();
787 iotable_init(cmx270_io_desc, ARRAY_SIZE(cmx270_io_desc));
618 788
619 /* Setup interrupt for 2700G */ 789 it8152_base_address = CMX270_IT8152_VIRT;
620 pxa_gpio_mode(IRQ_TO_GPIO(CMX270_GFXIRQ));
621 set_irq_type(CMX270_GFXIRQ, IRQT_FALLING);
622} 790}
623 791#else
624static void __init cmx270_map_io(void) 792static void __init cmx270_map_io(void)
625{ 793{
626 pxa_map_io(); 794 pxa_map_io();
627 iotable_init(cmx270_io_desc, ARRAY_SIZE(cmx270_io_desc));
628} 795}
629 796#endif
630 797
631MACHINE_START(ARMCORE, "Compulab CM-x270") 798MACHINE_START(ARMCORE, "Compulab CM-x270")
632 .boot_params = 0xa0000100, 799 .boot_params = 0xa0000100,
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 1bf680749928..e5cc6ca63c75 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Support for CompuLab EM-x270 platform 2 * Support for CompuLab EM-X270 platform
3 * 3 *
4 * Copyright (C) 2007 CompuLab, Ltd. 4 * Copyright (C) 2007, 2008 CompuLab, Ltd.
5 * Author: Mike Rapoport <mike@compulab.co.il> 5 * Author: Mike Rapoport <mike@compulab.co.il>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
@@ -14,31 +14,159 @@
14 14
15#include <linux/dm9000.h> 15#include <linux/dm9000.h>
16#include <linux/rtc-v3020.h> 16#include <linux/rtc-v3020.h>
17
18#include <linux/mtd/nand.h> 17#include <linux/mtd/nand.h>
19#include <linux/mtd/partitions.h> 18#include <linux/mtd/partitions.h>
19#include <linux/input.h>
20#include <linux/gpio_keys.h>
21#include <linux/gpio.h>
20 22
21#include <asm/mach-types.h> 23#include <asm/mach-types.h>
22
23#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
24 25
26#include <asm/arch/mfp-pxa27x.h>
25#include <asm/arch/pxa-regs.h> 27#include <asm/arch/pxa-regs.h>
26#include <asm/arch/pxa2xx-gpio.h>
27#include <asm/arch/pxa27x-udc.h> 28#include <asm/arch/pxa27x-udc.h>
28#include <asm/arch/audio.h> 29#include <asm/arch/audio.h>
29#include <asm/arch/pxafb.h> 30#include <asm/arch/pxafb.h>
30#include <asm/arch/ohci.h> 31#include <asm/arch/ohci.h>
31#include <asm/arch/mmc.h> 32#include <asm/arch/mmc.h>
32#include <asm/arch/bitfield.h> 33#include <asm/arch/pxa27x_keypad.h>
33 34
34#include "generic.h" 35#include "generic.h"
35 36
36/* GPIO IRQ usage */ 37/* GPIO IRQ usage */
37#define EM_X270_MMC_PD (105) 38#define GPIO41_ETHIRQ (41)
38#define EM_X270_ETHIRQ IRQ_GPIO(41) 39#define GPIO13_MMC_CD (13)
39#define EM_X270_MMC_IRQ IRQ_GPIO(13) 40#define EM_X270_ETHIRQ IRQ_GPIO(GPIO41_ETHIRQ)
41#define EM_X270_MMC_CD IRQ_GPIO(GPIO13_MMC_CD)
42
43/* NAND control GPIOs */
44#define GPIO11_NAND_CS (11)
45#define GPIO56_NAND_RB (56)
46
47static unsigned long em_x270_pin_config[] = {
48 /* AC'97 */
49 GPIO28_AC97_BITCLK,
50 GPIO29_AC97_SDATA_IN_0,
51 GPIO30_AC97_SDATA_OUT,
52 GPIO31_AC97_SYNC,
53 GPIO98_AC97_SYSCLK,
54 GPIO113_AC97_nRESET,
55
56 /* BTUART */
57 GPIO42_BTUART_RXD,
58 GPIO43_BTUART_TXD,
59 GPIO44_BTUART_CTS,
60 GPIO45_BTUART_RTS,
61
62 /* STUART */
63 GPIO46_STUART_RXD,
64 GPIO47_STUART_TXD,
65
66 /* MCI controller */
67 GPIO32_MMC_CLK,
68 GPIO112_MMC_CMD,
69 GPIO92_MMC_DAT_0,
70 GPIO109_MMC_DAT_1,
71 GPIO110_MMC_DAT_2,
72 GPIO111_MMC_DAT_3,
73
74 /* LCD */
75 GPIO58_LCD_LDD_0,
76 GPIO59_LCD_LDD_1,
77 GPIO60_LCD_LDD_2,
78 GPIO61_LCD_LDD_3,
79 GPIO62_LCD_LDD_4,
80 GPIO63_LCD_LDD_5,
81 GPIO64_LCD_LDD_6,
82 GPIO65_LCD_LDD_7,
83 GPIO66_LCD_LDD_8,
84 GPIO67_LCD_LDD_9,
85 GPIO68_LCD_LDD_10,
86 GPIO69_LCD_LDD_11,
87 GPIO70_LCD_LDD_12,
88 GPIO71_LCD_LDD_13,
89 GPIO72_LCD_LDD_14,
90 GPIO73_LCD_LDD_15,
91 GPIO74_LCD_FCLK,
92 GPIO75_LCD_LCLK,
93 GPIO76_LCD_PCLK,
94 GPIO77_LCD_BIAS,
95
96 /* QCI */
97 GPIO84_CIF_FV,
98 GPIO25_CIF_LV,
99 GPIO53_CIF_MCLK,
100 GPIO54_CIF_PCLK,
101 GPIO81_CIF_DD_0,
102 GPIO55_CIF_DD_1,
103 GPIO51_CIF_DD_2,
104 GPIO50_CIF_DD_3,
105 GPIO52_CIF_DD_4,
106 GPIO48_CIF_DD_5,
107 GPIO17_CIF_DD_6,
108 GPIO12_CIF_DD_7,
109
110 /* I2C */
111 GPIO117_I2C_SCL,
112 GPIO118_I2C_SDA,
113
114 /* Keypad */
115 GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
116 GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
117 GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
118 GPIO34_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
119 GPIO39_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
120 GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH,
121 GPIO91_KP_MKIN_6 | WAKEUP_ON_LEVEL_HIGH,
122 GPIO36_KP_MKIN_7 | WAKEUP_ON_LEVEL_HIGH,
123 GPIO103_KP_MKOUT_0,
124 GPIO104_KP_MKOUT_1,
125 GPIO105_KP_MKOUT_2,
126 GPIO106_KP_MKOUT_3,
127 GPIO107_KP_MKOUT_4,
128 GPIO108_KP_MKOUT_5,
129 GPIO96_KP_MKOUT_6,
130 GPIO22_KP_MKOUT_7,
131
132 /* SSP1 */
133 GPIO26_SSP1_RXD,
134 GPIO23_SSP1_SCLK,
135 GPIO24_SSP1_SFRM,
136 GPIO57_SSP1_TXD,
137
138 /* SSP2 */
139 GPIO19_SSP2_SCLK,
140 GPIO14_SSP2_SFRM,
141 GPIO89_SSP2_TXD,
142 GPIO88_SSP2_RXD,
143
144 /* SDRAM and local bus */
145 GPIO15_nCS_1,
146 GPIO78_nCS_2,
147 GPIO79_nCS_3,
148 GPIO80_nCS_4,
149 GPIO49_nPWE,
150 GPIO18_RDY,
151
152 /* GPIO */
153 GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
154
155 /* power controls */
156 GPIO20_GPIO | MFP_LPM_DRIVE_LOW, /* GPRS_PWEN */
157 GPIO115_GPIO | MFP_LPM_DRIVE_LOW, /* WLAN_PWEN */
158
159 /* NAND controls */
160 GPIO11_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */
161 GPIO56_GPIO, /* NAND Ready/Busy */
162
163 /* interrupts */
164 GPIO13_GPIO, /* MMC card detect */
165 GPIO41_GPIO, /* DM9000 interrupt */
166};
40 167
41static struct resource em_x270_dm9k_resource[] = { 168#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
169static struct resource em_x270_dm9000_resource[] = {
42 [0] = { 170 [0] = {
43 .start = PXA_CS2_PHYS, 171 .start = PXA_CS2_PHYS,
44 .end = PXA_CS2_PHYS + 3, 172 .end = PXA_CS2_PHYS + 3,
@@ -56,32 +184,30 @@ static struct resource em_x270_dm9k_resource[] = {
56 } 184 }
57}; 185};
58 186
59/* for the moment we limit ourselves to 32bit IO until some 187static struct dm9000_plat_data em_x270_dm9000_platdata = {
60 * better IO routines can be written and tested
61 */
62static struct dm9000_plat_data em_x270_dm9k_platdata = {
63 .flags = DM9000_PLATF_32BITONLY, 188 .flags = DM9000_PLATF_32BITONLY,
64}; 189};
65 190
66/* Ethernet device */ 191static struct platform_device em_x270_dm9000 = {
67static struct platform_device em_x270_dm9k = {
68 .name = "dm9000", 192 .name = "dm9000",
69 .id = 0, 193 .id = 0,
70 .num_resources = ARRAY_SIZE(em_x270_dm9k_resource), 194 .num_resources = ARRAY_SIZE(em_x270_dm9000_resource),
71 .resource = em_x270_dm9k_resource, 195 .resource = em_x270_dm9000_resource,
72 .dev = { 196 .dev = {
73 .platform_data = &em_x270_dm9k_platdata, 197 .platform_data = &em_x270_dm9000_platdata,
74 } 198 }
75}; 199};
76 200
77/* WM9712 touchscreen controller. Hopefully the driver will make it to 201static void __init em_x270_init_dm9000(void)
78 * the mainstream sometime */ 202{
79static struct platform_device em_x270_ts = { 203 platform_device_register(&em_x270_dm9000);
80 .name = "wm97xx-ts", 204}
81 .id = -1, 205#else
82}; 206static inline void em_x270_init_dm9000(void) {}
207#endif
83 208
84/* RTC */ 209/* V3020 RTC */
210#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
85static struct resource em_x270_v3020_resource[] = { 211static struct resource em_x270_v3020_resource[] = {
86 [0] = { 212 [0] = {
87 .start = PXA_CS4_PHYS, 213 .start = PXA_CS4_PHYS,
@@ -104,20 +230,26 @@ static struct platform_device em_x270_rtc = {
104 } 230 }
105}; 231};
106 232
107/* NAND flash */ 233static void __init em_x270_init_rtc(void)
108#define GPIO_NAND_CS (11) 234{
109#define GPIO_NAND_RB (56) 235 platform_device_register(&em_x270_rtc);
236}
237#else
238static inline void em_x270_init_rtc(void) {}
239#endif
110 240
241/* NAND flash */
242#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
111static inline void nand_cs_on(void) 243static inline void nand_cs_on(void)
112{ 244{
113 GPCR(GPIO_NAND_CS) = GPIO_bit(GPIO_NAND_CS); 245 gpio_set_value(GPIO11_NAND_CS, 0);
114} 246}
115 247
116static void nand_cs_off(void) 248static void nand_cs_off(void)
117{ 249{
118 dsb(); 250 dsb();
119 251
120 GPSR(GPIO_NAND_CS) = GPIO_bit(GPIO_NAND_CS); 252 gpio_set_value(GPIO11_NAND_CS, 1);
121} 253}
122 254
123/* hardware specific access to control-lines */ 255/* hardware specific access to control-lines */
@@ -157,7 +289,7 @@ static int em_x270_nand_device_ready(struct mtd_info *mtd)
157{ 289{
158 dsb(); 290 dsb();
159 291
160 return GPLR(GPIO_NAND_RB) & GPIO_bit(GPIO_NAND_RB); 292 return gpio_get_value(GPIO56_NAND_RB);
161} 293}
162 294
163static struct mtd_partition em_x270_partition_info[] = { 295static struct mtd_partition em_x270_partition_info[] = {
@@ -210,16 +342,35 @@ static struct platform_device em_x270_nand = {
210 } 342 }
211}; 343};
212 344
213/* platform devices */ 345static void __init em_x270_init_nand(void)
214static struct platform_device *platform_devices[] __initdata = { 346{
215 &em_x270_dm9k, 347 int err;
216 &em_x270_ts,
217 &em_x270_rtc,
218 &em_x270_nand,
219};
220 348
349 err = gpio_request(GPIO11_NAND_CS, "NAND CS");
350 if (err) {
351 pr_warning("EM-X270: failed to request NAND CS gpio\n");
352 return;
353 }
354
355 gpio_direction_output(GPIO11_NAND_CS, 1);
356
357 err = gpio_request(GPIO56_NAND_RB, "NAND R/B");
358 if (err) {
359 pr_warning("EM-X270: failed to request NAND R/B gpio\n");
360 gpio_free(GPIO11_NAND_CS);
361 return;
362 }
363
364 gpio_direction_input(GPIO56_NAND_RB);
365
366 platform_device_register(&em_x270_nand);
367}
368#else
369static inline void em_x270_init_nand(void) {}
370#endif
221 371
222/* PXA27x OHCI controller setup */ 372/* PXA27x OHCI controller setup */
373#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
223static int em_x270_ohci_init(struct device *dev) 374static int em_x270_ohci_init(struct device *dev)
224{ 375{
225 /* Set the Power Control Polarity Low */ 376 /* Set the Power Control Polarity Low */
@@ -237,27 +388,23 @@ static struct pxaohci_platform_data em_x270_ohci_platform_data = {
237 .init = em_x270_ohci_init, 388 .init = em_x270_ohci_init,
238}; 389};
239 390
391static void __init em_x270_init_ohci(void)
392{
393 pxa_set_ohci_info(&em_x270_ohci_platform_data);
394}
395#else
396static inline void em_x270_init_ohci(void) {}
397#endif
240 398
399/* MCI controller setup */
400#if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
241static int em_x270_mci_init(struct device *dev, 401static int em_x270_mci_init(struct device *dev,
242 irq_handler_t em_x270_detect_int, 402 irq_handler_t em_x270_detect_int,
243 void *data) 403 void *data)
244{ 404{
245 int err; 405 int err = request_irq(EM_X270_MMC_CD, em_x270_detect_int,
246 406 IRQF_DISABLED | IRQF_TRIGGER_FALLING,
247 /* setup GPIO for PXA27x MMC controller */ 407 "MMC card detect", data);
248 pxa_gpio_mode(GPIO32_MMCCLK_MD);
249 pxa_gpio_mode(GPIO112_MMCCMD_MD);
250 pxa_gpio_mode(GPIO92_MMCDAT0_MD);
251 pxa_gpio_mode(GPIO109_MMCDAT1_MD);
252 pxa_gpio_mode(GPIO110_MMCDAT2_MD);
253 pxa_gpio_mode(GPIO111_MMCDAT3_MD);
254
255 /* EM-X270 uses GPIO13 as SD power enable */
256 pxa_gpio_mode(EM_X270_MMC_PD | GPIO_OUT);
257
258 err = request_irq(EM_X270_MMC_IRQ, em_x270_detect_int,
259 IRQF_DISABLED | IRQF_TRIGGER_FALLING,
260 "MMC card detect", data);
261 if (err) { 408 if (err) {
262 printk(KERN_ERR "%s: can't request MMC card detect IRQ: %d\n", 409 printk(KERN_ERR "%s: can't request MMC card detect IRQ: %d\n",
263 __func__, err); 410 __func__, err);
@@ -279,7 +426,8 @@ static void em_x270_mci_setpower(struct device *dev, unsigned int vdd)
279 426
280static void em_x270_mci_exit(struct device *dev, void *data) 427static void em_x270_mci_exit(struct device *dev, void *data)
281{ 428{
282 free_irq(EM_X270_MMC_IRQ, data); 429 int irq = gpio_to_irq(GPIO13_MMC_CD);
430 free_irq(irq, data);
283} 431}
284 432
285static struct pxamci_platform_data em_x270_mci_platform_data = { 433static struct pxamci_platform_data em_x270_mci_platform_data = {
@@ -289,7 +437,16 @@ static struct pxamci_platform_data em_x270_mci_platform_data = {
289 .exit = em_x270_mci_exit, 437 .exit = em_x270_mci_exit,
290}; 438};
291 439
440static void __init em_x270_init_mmc(void)
441{
442 pxa_set_mci_info(&em_x270_mci_platform_data);
443}
444#else
445static inline void em_x270_init_mmc(void) {}
446#endif
447
292/* LCD 480x640 */ 448/* LCD 480x640 */
449#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
293static struct pxafb_mode_info em_x270_lcd_mode = { 450static struct pxafb_mode_info em_x270_lcd_mode = {
294 .pixclock = 50000, 451 .pixclock = 50000,
295 .bpp = 16, 452 .bpp = 16,
@@ -307,40 +464,96 @@ static struct pxafb_mode_info em_x270_lcd_mode = {
307static struct pxafb_mach_info em_x270_lcd = { 464static struct pxafb_mach_info em_x270_lcd = {
308 .modes = &em_x270_lcd_mode, 465 .modes = &em_x270_lcd_mode,
309 .num_modes = 1, 466 .num_modes = 1,
310 .cmap_inverse = 0, 467 .lcd_conn = LCD_COLOR_TFT_16BPP,
311 .cmap_static = 0,
312 .lccr0 = LCCR0_PAS,
313 .lccr3 = LCCR3_PixClkDiv(0x01) | LCCR3_Acb(0xff),
314}; 468};
315 469static void __init em_x270_init_lcd(void)
316static void __init em_x270_init(void)
317{ 470{
318 /* setup LCD */
319 set_pxa_fb_info(&em_x270_lcd); 471 set_pxa_fb_info(&em_x270_lcd);
472}
473#else
474static inline void em_x270_init_lcd(void) {}
475#endif
320 476
321 /* register EM-X270 platform devices */ 477#if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE)
322 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 478static void __init em_x270_init_ac97(void)
479{
323 pxa_set_ac97_info(NULL); 480 pxa_set_ac97_info(NULL);
481}
482#else
483static inline void em_x270_init_ac97(void) {}
484#endif
485
486#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
487static unsigned int em_x270_matrix_keys[] = {
488 KEY(0, 0, KEY_A), KEY(1, 0, KEY_UP), KEY(2, 1, KEY_B),
489 KEY(0, 2, KEY_LEFT), KEY(1, 1, KEY_ENTER), KEY(2, 0, KEY_RIGHT),
490 KEY(0, 1, KEY_C), KEY(1, 2, KEY_DOWN), KEY(2, 2, KEY_D),
491};
324 492
325 /* set MCI and OHCI platform parameters */ 493struct pxa27x_keypad_platform_data em_x270_keypad_info = {
326 pxa_set_mci_info(&em_x270_mci_platform_data); 494 /* code map for the matrix keys */
327 pxa_set_ohci_info(&em_x270_ohci_platform_data); 495 .matrix_key_rows = 3,
496 .matrix_key_cols = 3,
497 .matrix_key_map = em_x270_matrix_keys,
498 .matrix_key_map_size = ARRAY_SIZE(em_x270_matrix_keys),
499};
500
501static void __init em_x270_init_keypad(void)
502{
503 pxa_set_keypad_info(&em_x270_keypad_info);
504}
505#else
506static inline void em_x270_init_keypad(void) {}
507#endif
328 508
329 /* setup STUART GPIOs */ 509#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
330 pxa_gpio_mode(GPIO46_STRXD_MD); 510static struct gpio_keys_button gpio_keys_button[] = {
331 pxa_gpio_mode(GPIO47_STTXD_MD); 511 [0] = {
512 .desc = "sleep/wakeup",
513 .code = KEY_SUSPEND,
514 .type = EV_PWR,
515 .gpio = 1,
516 .wakeup = 1,
517 },
518};
332 519
333 /* setup BTUART GPIOs */ 520static struct gpio_keys_platform_data em_x270_gpio_keys_data = {
334 pxa_gpio_mode(GPIO42_BTRXD_MD); 521 .buttons = gpio_keys_button,
335 pxa_gpio_mode(GPIO43_BTTXD_MD); 522 .nbuttons = 1,
336 pxa_gpio_mode(GPIO44_BTCTS_MD); 523};
337 pxa_gpio_mode(GPIO45_BTRTS_MD);
338 524
339 /* Setup interrupt for dm9000 */ 525static struct platform_device em_x270_gpio_keys = {
340 set_irq_type(EM_X270_ETHIRQ, IRQT_RISING); 526 .name = "gpio-keys",
527 .id = -1,
528 .dev = {
529 .platform_data = &em_x270_gpio_keys_data,
530 },
531};
532
533static void __init em_x270_init_gpio_keys(void)
534{
535 platform_device_register(&em_x270_gpio_keys);
536}
537#else
538static inline void em_x270_init_gpio_keys(void) {}
539#endif
540
541static void __init em_x270_init(void)
542{
543 pxa2xx_mfp_config(ARRAY_AND_SIZE(em_x270_pin_config));
544
545 em_x270_init_dm9000();
546 em_x270_init_rtc();
547 em_x270_init_nand();
548 em_x270_init_lcd();
549 em_x270_init_mmc();
550 em_x270_init_ohci();
551 em_x270_init_keypad();
552 em_x270_init_gpio_keys();
553 em_x270_init_ac97();
341} 554}
342 555
343MACHINE_START(EM_X270, "Compulab EM-x270") 556MACHINE_START(EM_X270, "Compulab EM-X270")
344 .boot_params = 0xa0000100, 557 .boot_params = 0xa0000100,
345 .phys_io = 0x40000000, 558 .phys_io = 0x40000000,
346 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, 559 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 4cd50e3005e9..c5b845b935bb 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -109,6 +109,52 @@ static const struct clkops clk_pxa25x_lcd_ops = {
109 .getrate = clk_pxa25x_lcd_getrate, 109 .getrate = clk_pxa25x_lcd_getrate,
110}; 110};
111 111
112static unsigned long gpio12_config_32k[] = {
113 GPIO12_32KHz,
114};
115
116static unsigned long gpio12_config_gpio[] = {
117 GPIO12_GPIO,
118};
119
120static void clk_gpio12_enable(struct clk *clk)
121{
122 pxa2xx_mfp_config(gpio12_config_32k, 1);
123}
124
125static void clk_gpio12_disable(struct clk *clk)
126{
127 pxa2xx_mfp_config(gpio12_config_gpio, 1);
128}
129
130static const struct clkops clk_pxa25x_gpio12_ops = {
131 .enable = clk_gpio12_enable,
132 .disable = clk_gpio12_disable,
133};
134
135static unsigned long gpio11_config_3m6[] = {
136 GPIO11_3_6MHz,
137};
138
139static unsigned long gpio11_config_gpio[] = {
140 GPIO11_GPIO,
141};
142
143static void clk_gpio11_enable(struct clk *clk)
144{
145 pxa2xx_mfp_config(gpio11_config_3m6, 1);
146}
147
148static void clk_gpio11_disable(struct clk *clk)
149{
150 pxa2xx_mfp_config(gpio11_config_gpio, 1);
151}
152
153static const struct clkops clk_pxa25x_gpio11_ops = {
154 .enable = clk_gpio11_enable,
155 .disable = clk_gpio11_disable,
156};
157
112/* 158/*
113 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz) 159 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
114 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz 160 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
@@ -128,6 +174,8 @@ static struct clk pxa25x_clks[] = {
128 INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), 174 INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
129 INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL), 175 INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
130 INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa25x_device_udc.dev), 176 INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa25x_device_udc.dev),
177 INIT_CLK("GPIO11_CLK", &clk_pxa25x_gpio11_ops, 3686400, 0, NULL),
178 INIT_CLK("GPIO12_CLK", &clk_pxa25x_gpio12_ops, 32768, 0, NULL),
131 INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), 179 INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
132 INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), 180 INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
133 181
@@ -145,7 +193,10 @@ static struct clk pxa25x_clks[] = {
145 INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), 193 INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
146}; 194};
147 195
148static struct clk gpio7_clk = INIT_CKOTHER("GPIO7_CK", &pxa25x_clks[4], NULL); 196static struct clk pxa2xx_clk_aliases[] = {
197 INIT_CKOTHER("GPIO7_CLK", &pxa25x_clks[4], NULL),
198 INIT_CKOTHER("SA1111_CLK", &pxa25x_clks[5], NULL),
199};
149 200
150#ifdef CONFIG_PM 201#ifdef CONFIG_PM
151 202
@@ -293,7 +344,7 @@ static int __init pxa25x_init(void)
293 int i, ret = 0; 344 int i, ret = 0;
294 345
295 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ 346 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
296 if (cpu_is_pxa25x()) 347 if (cpu_is_pxa255())
297 clks_register(&pxa25x_hwuart_clk, 1); 348 clks_register(&pxa25x_hwuart_clk, 1);
298 349
299 if (cpu_is_pxa21x() || cpu_is_pxa25x()) { 350 if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
@@ -317,10 +368,10 @@ static int __init pxa25x_init(void)
317 } 368 }
318 369
319 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ 370 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
320 if (cpu_is_pxa25x()) 371 if (cpu_is_pxa255())
321 ret = platform_device_register(&pxa_device_hwuart); 372 ret = platform_device_register(&pxa_device_hwuart);
322 373
323 clks_register(&gpio7_clk, 1); 374 clks_register(pxa2xx_clk_aliases, ARRAY_SIZE(pxa2xx_clk_aliases));
324 375
325 return ret; 376 return ret;
326} 377}
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
index fc97fe57ee6f..b5809c51d13f 100644
--- a/arch/arm/mach-sa1100/clock.c
+++ b/arch/arm/mach-sa1100/clock.c
@@ -103,7 +103,7 @@ static void clk_gpio27_disable(void)
103} 103}
104 104
105static struct clk clk_gpio27 = { 105static struct clk clk_gpio27 = {
106 .name = "GPIO27_CLK", 106 .name = "SA1111_CLK",
107 .rate = 3686400, 107 .rate = 3686400,
108 .enable = clk_gpio27_enable, 108 .enable = clk_gpio27_enable,
109 .disable = clk_gpio27_disable, 109 .disable = clk_gpio27_disable,
diff --git a/drivers/mtd/nand/cmx270_nand.c b/drivers/mtd/nand/cmx270_nand.c
index cb663ef245d5..fc8529bedfdf 100644
--- a/drivers/mtd/nand/cmx270_nand.c
+++ b/drivers/mtd/nand/cmx270_nand.c
@@ -20,9 +20,11 @@
20 20
21#include <linux/mtd/nand.h> 21#include <linux/mtd/nand.h>
22#include <linux/mtd/partitions.h> 22#include <linux/mtd/partitions.h>
23#include <linux/gpio.h>
23 24
24#include <asm/io.h> 25#include <asm/io.h>
25#include <asm/irq.h> 26#include <asm/irq.h>
27#include <asm/mach-types.h>
26 28
27#include <asm/arch/hardware.h> 29#include <asm/arch/hardware.h>
28#include <asm/arch/pxa-regs.h> 30#include <asm/arch/pxa-regs.h>
@@ -30,20 +32,6 @@
30#define GPIO_NAND_CS (11) 32#define GPIO_NAND_CS (11)
31#define GPIO_NAND_RB (89) 33#define GPIO_NAND_RB (89)
32 34
33/* This macro needed to ensure in-order operation of GPIO and local
34 * bus. Without both asm command and dummy uncached read there're
35 * states when NAND access is broken. I've looked for such macro(s) in
36 * include/asm-arm but found nothing approptiate.
37 * dmac_clean_range is close, but is makes cache invalidation
38 * unnecessary here and it cannot be used in module
39 */
40#define DRAIN_WB() \
41 do { \
42 unsigned char dummy; \
43 asm volatile ("mcr p15, 0, r0, c7, c10, 4":::"r0"); \
44 dummy=*((unsigned char*)UNCACHED_ADDR); \
45 } while(0)
46
47/* MTD structure for CM-X270 board */ 35/* MTD structure for CM-X270 board */
48static struct mtd_info *cmx270_nand_mtd; 36static struct mtd_info *cmx270_nand_mtd;
49 37
@@ -103,14 +91,14 @@ static int cmx270_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
103 91
104static inline void nand_cs_on(void) 92static inline void nand_cs_on(void)
105{ 93{
106 GPCR(GPIO_NAND_CS) = GPIO_bit(GPIO_NAND_CS); 94 gpio_set_value(GPIO_NAND_CS, 0);
107} 95}
108 96
109static void nand_cs_off(void) 97static void nand_cs_off(void)
110{ 98{
111 DRAIN_WB(); 99 dsb();
112 100
113 GPSR(GPIO_NAND_CS) = GPIO_bit(GPIO_NAND_CS); 101 gpio_set_value(GPIO_NAND_CS, 1);
114} 102}
115 103
116/* 104/*
@@ -122,7 +110,7 @@ static void cmx270_hwcontrol(struct mtd_info *mtd, int dat,
122 struct nand_chip* this = mtd->priv; 110 struct nand_chip* this = mtd->priv;
123 unsigned int nandaddr = (unsigned int)this->IO_ADDR_W; 111 unsigned int nandaddr = (unsigned int)this->IO_ADDR_W;
124 112
125 DRAIN_WB(); 113 dsb();
126 114
127 if (ctrl & NAND_CTRL_CHANGE) { 115 if (ctrl & NAND_CTRL_CHANGE) {
128 if ( ctrl & NAND_ALE ) 116 if ( ctrl & NAND_ALE )
@@ -139,12 +127,12 @@ static void cmx270_hwcontrol(struct mtd_info *mtd, int dat,
139 nand_cs_off(); 127 nand_cs_off();
140 } 128 }
141 129
142 DRAIN_WB(); 130 dsb();
143 this->IO_ADDR_W = (void __iomem*)nandaddr; 131 this->IO_ADDR_W = (void __iomem*)nandaddr;
144 if (dat != NAND_CMD_NONE) 132 if (dat != NAND_CMD_NONE)
145 writel((dat << 16), this->IO_ADDR_W); 133 writel((dat << 16), this->IO_ADDR_W);
146 134
147 DRAIN_WB(); 135 dsb();
148} 136}
149 137
150/* 138/*
@@ -152,9 +140,9 @@ static void cmx270_hwcontrol(struct mtd_info *mtd, int dat,
152 */ 140 */
153static int cmx270_device_ready(struct mtd_info *mtd) 141static int cmx270_device_ready(struct mtd_info *mtd)
154{ 142{
155 DRAIN_WB(); 143 dsb();
156 144
157 return (GPLR(GPIO_NAND_RB) & GPIO_bit(GPIO_NAND_RB)); 145 return (gpio_get_value(GPIO_NAND_RB));
158} 146}
159 147
160/* 148/*
@@ -168,20 +156,40 @@ static int cmx270_init(void)
168 int mtd_parts_nb = 0; 156 int mtd_parts_nb = 0;
169 int ret; 157 int ret;
170 158
159 if (!machine_is_armcore())
160 return -ENODEV;
161
162 ret = gpio_request(GPIO_NAND_CS, "NAND CS");
163 if (ret) {
164 pr_warning("CM-X270: failed to request NAND CS gpio\n");
165 return ret;
166 }
167
168 gpio_direction_output(GPIO_NAND_CS, 1);
169
170 ret = gpio_request(GPIO_NAND_RB, "NAND R/B");
171 if (ret) {
172 pr_warning("CM-X270: failed to request NAND R/B gpio\n");
173 goto err_gpio_request;
174 }
175
176 gpio_direction_input(GPIO_NAND_RB);
177
171 /* Allocate memory for MTD device structure and private data */ 178 /* Allocate memory for MTD device structure and private data */
172 cmx270_nand_mtd = kzalloc(sizeof(struct mtd_info) + 179 cmx270_nand_mtd = kzalloc(sizeof(struct mtd_info) +
173 sizeof(struct nand_chip), 180 sizeof(struct nand_chip),
174 GFP_KERNEL); 181 GFP_KERNEL);
175 if (!cmx270_nand_mtd) { 182 if (!cmx270_nand_mtd) {
176 printk("Unable to allocate CM-X270 NAND MTD device structure.\n"); 183 pr_debug("Unable to allocate CM-X270 NAND MTD device structure.\n");
177 return -ENOMEM; 184 ret = -ENOMEM;
185 goto err_kzalloc;
178 } 186 }
179 187
180 cmx270_nand_io = ioremap(PXA_CS1_PHYS, 12); 188 cmx270_nand_io = ioremap(PXA_CS1_PHYS, 12);
181 if (!cmx270_nand_io) { 189 if (!cmx270_nand_io) {
182 printk("Unable to ioremap NAND device\n"); 190 pr_debug("Unable to ioremap NAND device\n");
183 ret = -EINVAL; 191 ret = -EINVAL;
184 goto err1; 192 goto err_ioremap;
185 } 193 }
186 194
187 /* Get pointer to private data */ 195 /* Get pointer to private data */
@@ -209,9 +217,9 @@ static int cmx270_init(void)
209 217
210 /* Scan to find existence of the device */ 218 /* Scan to find existence of the device */
211 if (nand_scan (cmx270_nand_mtd, 1)) { 219 if (nand_scan (cmx270_nand_mtd, 1)) {
212 printk(KERN_NOTICE "No NAND device\n"); 220 pr_notice("No NAND device\n");
213 ret = -ENXIO; 221 ret = -ENXIO;
214 goto err2; 222 goto err_scan;
215 } 223 }
216 224
217#ifdef CONFIG_MTD_CMDLINE_PARTS 225#ifdef CONFIG_MTD_CMDLINE_PARTS
@@ -229,18 +237,22 @@ static int cmx270_init(void)
229 } 237 }
230 238
231 /* Register the partitions */ 239 /* Register the partitions */
232 printk(KERN_NOTICE "Using %s partition definition\n", part_type); 240 pr_notice("Using %s partition definition\n", part_type);
233 ret = add_mtd_partitions(cmx270_nand_mtd, mtd_parts, mtd_parts_nb); 241 ret = add_mtd_partitions(cmx270_nand_mtd, mtd_parts, mtd_parts_nb);
234 if (ret) 242 if (ret)
235 goto err2; 243 goto err_scan;
236 244
237 /* Return happy */ 245 /* Return happy */
238 return 0; 246 return 0;
239 247
240err2: 248err_scan:
241 iounmap(cmx270_nand_io); 249 iounmap(cmx270_nand_io);
242err1: 250err_ioremap:
243 kfree(cmx270_nand_mtd); 251 kfree(cmx270_nand_mtd);
252err_kzalloc:
253 gpio_free(GPIO_NAND_RB);
254err_gpio_request:
255 gpio_free(GPIO_NAND_CS);
244 256
245 return ret; 257 return ret;
246 258
@@ -255,6 +267,9 @@ static void cmx270_cleanup(void)
255 /* Release resources, unregister device */ 267 /* Release resources, unregister device */
256 nand_release(cmx270_nand_mtd); 268 nand_release(cmx270_nand_mtd);
257 269
270 gpio_free(GPIO_NAND_RB);
271 gpio_free(GPIO_NAND_CS);
272
258 iounmap(cmx270_nand_io); 273 iounmap(cmx270_nand_io);
259 274
260 /* Free the MTD device structure */ 275 /* Free the MTD device structure */
diff --git a/drivers/pcmcia/pxa2xx_cm_x270.c b/drivers/pcmcia/pxa2xx_cm_x270.c
index f123fce65f2e..bb95db7d2b76 100644
--- a/drivers/pcmcia/pxa2xx_cm_x270.c
+++ b/drivers/pcmcia/pxa2xx_cm_x270.c
@@ -5,83 +5,60 @@
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 * 7 *
8 * Compulab Ltd., 2003, 2007 8 * Compulab Ltd., 2003, 2007, 2008
9 * Mike Rapoport <mike@compulab.co.il> 9 * Mike Rapoport <mike@compulab.co.il>
10 * 10 *
11 */ 11 */
12 12
13#include <linux/kernel.h>
14#include <linux/sched.h>
15#include <linux/platform_device.h> 13#include <linux/platform_device.h>
16#include <linux/irq.h> 14#include <linux/irq.h>
17#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/gpio.h>
18 17
19#include <pcmcia/ss.h>
20#include <asm/hardware.h>
21#include <asm/mach-types.h> 18#include <asm/mach-types.h>
22
23#include <asm/arch/pxa-regs.h> 19#include <asm/arch/pxa-regs.h>
24#include <asm/arch/pxa2xx-gpio.h>
25#include <asm/arch/cm-x270.h>
26 20
27#include "soc_common.h" 21#include "soc_common.h"
28 22
23#define GPIO_PCMCIA_S0_CD_VALID (84)
24#define GPIO_PCMCIA_S0_RDYINT (82)
25#define GPIO_PCMCIA_RESET (53)
26
27#define PCMCIA_S0_CD_VALID IRQ_GPIO(GPIO_PCMCIA_S0_CD_VALID)
28#define PCMCIA_S0_RDYINT IRQ_GPIO(GPIO_PCMCIA_S0_RDYINT)
29
30
29static struct pcmcia_irqs irqs[] = { 31static struct pcmcia_irqs irqs[] = {
30 { 0, PCMCIA_S0_CD_VALID, "PCMCIA0 CD" }, 32 { 0, PCMCIA_S0_CD_VALID, "PCMCIA0 CD" },
31 { 1, PCMCIA_S1_CD_VALID, "PCMCIA1 CD" },
32}; 33};
33 34
34static int cmx270_pcmcia_hw_init(struct soc_pcmcia_socket *skt) 35static int cmx270_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
35{ 36{
36 GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) | 37 int ret = gpio_request(GPIO_PCMCIA_RESET, "PCCard reset");
37 GPIO_bit(GPIO49_nPWE) | 38 if (ret)
38 GPIO_bit(GPIO50_nPIOR) | 39 return ret;
39 GPIO_bit(GPIO51_nPIOW) | 40 gpio_direction_output(GPIO_PCMCIA_RESET, 0);
40 GPIO_bit(GPIO85_nPCE_1) | 41
41 GPIO_bit(GPIO54_nPCE_2); 42 skt->irq = PCMCIA_S0_RDYINT;
42 43 ret = soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
43 pxa_gpio_mode(GPIO48_nPOE_MD); 44 if (!ret)
44 pxa_gpio_mode(GPIO49_nPWE_MD); 45 gpio_free(GPIO_PCMCIA_RESET);
45 pxa_gpio_mode(GPIO50_nPIOR_MD); 46
46 pxa_gpio_mode(GPIO51_nPIOW_MD); 47 return ret;
47 pxa_gpio_mode(GPIO85_nPCE_1_MD);
48 pxa_gpio_mode(GPIO54_nPCE_2_MD);
49 pxa_gpio_mode(GPIO55_nPREG_MD);
50 pxa_gpio_mode(GPIO56_nPWAIT_MD);
51 pxa_gpio_mode(GPIO57_nIOIS16_MD);
52
53 /* Reset signal */
54 pxa_gpio_mode(GPIO53_nPCE_2 | GPIO_OUT);
55 GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
56
57 set_irq_type(PCMCIA_S0_CD_VALID, IRQ_TYPE_EDGE_BOTH);
58 set_irq_type(PCMCIA_S1_CD_VALID, IRQ_TYPE_EDGE_BOTH);
59
60 /* irq's for slots: */
61 set_irq_type(PCMCIA_S0_RDYINT, IRQ_TYPE_EDGE_FALLING);
62 set_irq_type(PCMCIA_S1_RDYINT, IRQ_TYPE_EDGE_FALLING);
63
64 skt->irq = (skt->nr == 0) ? PCMCIA_S0_RDYINT : PCMCIA_S1_RDYINT;
65 return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
66} 48}
67 49
68static void cmx270_pcmcia_shutdown(struct soc_pcmcia_socket *skt) 50static void cmx270_pcmcia_shutdown(struct soc_pcmcia_socket *skt)
69{ 51{
70 soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs)); 52 soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs));
71 53 gpio_free(GPIO_PCMCIA_RESET);
72 set_irq_type(IRQ_TO_GPIO(PCMCIA_S0_CD_VALID), IRQ_TYPE_NONE);
73 set_irq_type(IRQ_TO_GPIO(PCMCIA_S1_CD_VALID), IRQ_TYPE_NONE);
74
75 set_irq_type(IRQ_TO_GPIO(PCMCIA_S0_RDYINT), IRQ_TYPE_NONE);
76 set_irq_type(IRQ_TO_GPIO(PCMCIA_S1_RDYINT), IRQ_TYPE_NONE);
77} 54}
78 55
79 56
80static void cmx270_pcmcia_socket_state(struct soc_pcmcia_socket *skt, 57static void cmx270_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
81 struct pcmcia_state *state) 58 struct pcmcia_state *state)
82{ 59{
83 state->detect = (PCC_DETECT(skt->nr) == 0) ? 1 : 0; 60 state->detect = (gpio_get_value(GPIO_PCMCIA_S0_CD_VALID) == 0) ? 1 : 0;
84 state->ready = (PCC_READY(skt->nr) == 0) ? 0 : 1; 61 state->ready = (gpio_get_value(GPIO_PCMCIA_S0_RDYINT) == 0) ? 0 : 1;
85 state->bvd1 = 1; 62 state->bvd1 = 1;
86 state->bvd2 = 1; 63 state->bvd2 = 1;
87 state->vs_3v = 0; 64 state->vs_3v = 0;
@@ -93,32 +70,16 @@ static void cmx270_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
93static int cmx270_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, 70static int cmx270_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
94 const socket_state_t *state) 71 const socket_state_t *state)
95{ 72{
96 GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
97 pxa_gpio_mode(GPIO49_nPWE | GPIO_OUT);
98
99 switch (skt->nr) { 73 switch (skt->nr) {
100 case 0: 74 case 0:
101 if (state->flags & SS_RESET) { 75 if (state->flags & SS_RESET) {
102 GPCR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE); 76 gpio_set_value(GPIO_PCMCIA_RESET, 1);
103 GPSR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
104 udelay(10);
105 GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
106 GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
107 }
108 break;
109 case 1:
110 if (state->flags & SS_RESET) {
111 GPCR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
112 GPSR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
113 udelay(10); 77 udelay(10);
114 GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2); 78 gpio_set_value(GPIO_PCMCIA_RESET, 0);
115 GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
116 } 79 }
117 break; 80 break;
118 } 81 }
119 82
120 pxa_gpio_mode(GPIO49_nPWE_MD);
121
122 return 0; 83 return 0;
123} 84}
124 85
@@ -139,7 +100,7 @@ static struct pcmcia_low_level cmx270_pcmcia_ops __initdata = {
139 .configure_socket = cmx270_pcmcia_configure_socket, 100 .configure_socket = cmx270_pcmcia_configure_socket,
140 .socket_init = cmx270_pcmcia_socket_init, 101 .socket_init = cmx270_pcmcia_socket_init,
141 .socket_suspend = cmx270_pcmcia_socket_suspend, 102 .socket_suspend = cmx270_pcmcia_socket_suspend,
142 .nr = 2, 103 .nr = 1,
143}; 104};
144 105
145static struct platform_device *cmx270_pcmcia_device; 106static struct platform_device *cmx270_pcmcia_device;
diff --git a/include/asm-arm/arch-pxa/cm-x270.h b/include/asm-arm/arch-pxa/cm-x270.h
deleted file mode 100644
index f8fac9e18009..000000000000
--- a/include/asm-arm/arch-pxa/cm-x270.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * linux/include/asm/arch-pxa/cm-x270.h
3 *
4 * Copyright Compulab Ltd., 2003, 2007
5 * Mike Rapoport <mike@compulab.co.il>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12
13/* CM-x270 device physical addresses */
14#define CMX270_CS1_PHYS (PXA_CS1_PHYS)
15#define MARATHON_PHYS (PXA_CS2_PHYS)
16#define CMX270_IDE104_PHYS (PXA_CS3_PHYS)
17#define CMX270_IT8152_PHYS (PXA_CS4_PHYS)
18
19/* Statically mapped regions */
20#define CMX270_VIRT_BASE (0xe8000000)
21#define CMX270_IT8152_VIRT (CMX270_VIRT_BASE)
22#define CMX270_IDE104_VIRT (CMX270_IT8152_VIRT + SZ_64M)
23
24/* GPIO related definitions */
25#define GPIO_IT8152_IRQ (22)
26
27#define IRQ_GPIO_IT8152_IRQ IRQ_GPIO(GPIO_IT8152_IRQ)
28#define PME_IRQ IRQ_GPIO(0)
29#define CMX270_IDE_IRQ IRQ_GPIO(100)
30#define CMX270_GPIRQ1 IRQ_GPIO(101)
31#define CMX270_TOUCHIRQ IRQ_GPIO(96)
32#define CMX270_ETHIRQ IRQ_GPIO(10)
33#define CMX270_GFXIRQ IRQ_GPIO(95)
34#define CMX270_NANDIRQ IRQ_GPIO(89)
35#define CMX270_MMC_IRQ IRQ_GPIO(83)
36
37/* PCMCIA related definitions */
38#define PCC_DETECT(x) (GPLR(84 - (x)) & GPIO_bit(84 - (x)))
39#define PCC_READY(x) (GPLR(82 - (x)) & GPIO_bit(82 - (x)))
40
41#define PCMCIA_S0_CD_VALID IRQ_GPIO(84)
42#define PCMCIA_S0_CD_VALID_EDGE GPIO_BOTH_EDGES
43
44#define PCMCIA_S1_CD_VALID IRQ_GPIO(83)
45#define PCMCIA_S1_CD_VALID_EDGE GPIO_BOTH_EDGES
46
47#define PCMCIA_S0_RDYINT IRQ_GPIO(82)
48#define PCMCIA_S1_RDYINT IRQ_GPIO(81)
49
50#define PCMCIA_RESET_GPIO 53
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index d9af6dabc899..b6a8317c2ec4 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -69,6 +69,12 @@
69 _id == 0x212; \ 69 _id == 0x212; \
70 }) 70 })
71 71
72#define __cpu_is_pxa255(id) \
73 ({ \
74 unsigned int _id = (id) >> 4 & 0xfff; \
75 _id == 0x2d0; \
76 })
77
72#define __cpu_is_pxa25x(id) \ 78#define __cpu_is_pxa25x(id) \
73 ({ \ 79 ({ \
74 unsigned int _id = (id) >> 4 & 0xfff; \ 80 unsigned int _id = (id) >> 4 & 0xfff; \
@@ -76,6 +82,7 @@
76 }) 82 })
77#else 83#else
78#define __cpu_is_pxa21x(id) (0) 84#define __cpu_is_pxa21x(id) (0)
85#define __cpu_is_pxa255(id) (0)
79#define __cpu_is_pxa25x(id) (0) 86#define __cpu_is_pxa25x(id) (0)
80#endif 87#endif
81 88
@@ -124,6 +131,11 @@
124 __cpu_is_pxa21x(read_cpuid_id()); \ 131 __cpu_is_pxa21x(read_cpuid_id()); \
125 }) 132 })
126 133
134#define cpu_is_pxa255() \
135 ({ \
136 __cpu_is_pxa255(read_cpuid_id()); \
137 })
138
127#define cpu_is_pxa25x() \ 139#define cpu_is_pxa25x() \
128 ({ \ 140 ({ \
129 __cpu_is_pxa25x(read_cpuid_id()); \ 141 __cpu_is_pxa25x(read_cpuid_id()); \
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 09:33:33 -0500