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-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h67
-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/mx21.h9
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h13
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h9
-rw-r--r--arch/arm/plat-mxc/include/mach/mx2x.h36
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h16
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h17
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h65
-rw-r--r--arch/arm/plat-mxc/include/mach/mx51.h38
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc91231.h22
11 files changed, 89 insertions, 208 deletions
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 409cec6223df..dde777c10176 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -32,6 +32,73 @@
32 (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \ 32 (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \
33 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0) 33 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
34 34
35/*
36 * This is rather complicated for humans and ugly to verify, but for a machine
37 * it's OK. Still more as it is usually only applied to constants. The upsides
38 * on using this approach are:
39 *
40 * - same mapping on all i.MX machines
41 * - works for assembler, too
42 * - no need to nurture #defines for virtual addresses
43 *
44 * The downside it, it's hard to verify (but I have a script for that).
45 *
46 * Obviously this needs to be injective for each SoC. In general it maps the
47 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
48 * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
49 *
50 * It applies the following mappings for the different SoCs:
51 *
52 * mx1:
53 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
54 * mx21:
55 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
56 * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000
57 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
58 * mx25:
59 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
60 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
61 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
62 * mx27:
63 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
64 * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000
65 * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000
66 * mx31:
67 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
68 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
69 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
70 * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
71 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
72 * mx35:
73 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
74 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
75 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
76 * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
77 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
78 * mx51:
79 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
80 * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000
81 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
82 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
83 * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000
84 * mxc91231:
85 * L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000
86 * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
87 * ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000
88 * AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000
89 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
90 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
91 * SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000
92 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
93 */
94#define IMX_IO_P2V(x) ( \
95 0xf4000000 + \
96 (((x) & 0x50000000) >> 6) + \
97 (((x) & 0x0b000000) >> 4) + \
98 (((x) & 0x000fffff)))
99
100#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
101
35#ifdef CONFIG_ARCH_MX5 102#ifdef CONFIG_ARCH_MX5
36#include <mach/mx51.h> 103#include <mach/mx51.h>
37#endif 104#endif
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index b41c2887f65c..b786ae783d1b 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -19,7 +19,6 @@
19 */ 19 */
20#define MX1_IO_BASE_ADDR 0x00200000 20#define MX1_IO_BASE_ADDR 0x00200000
21#define MX1_IO_SIZE SZ_1M 21#define MX1_IO_SIZE SZ_1M
22#define MX1_IO_BASE_ADDR_VIRT VMALLOC_END
23 22
24#define MX1_CS0_PHYS 0x10000000 23#define MX1_CS0_PHYS 0x10000000
25#define MX1_CS0_SIZE 0x02000000 24#define MX1_CS0_SIZE 0x02000000
@@ -73,8 +72,7 @@
73#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) 72#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
74 73
75/* macro to get at IO space when running virtually */ 74/* macro to get at IO space when running virtually */
76#define MX1_IO_P2V(x) ( \ 75#define MX1_IO_P2V(x) IMX_IO_P2V(x)
77 IMX_IO_P2V_MODULE(x, MX1_IO))
78#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x)) 76#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
79 77
80/* fixed interrput numbers */ 78/* fixed interrput numbers */
@@ -171,7 +169,6 @@
171/* these should go away */ 169/* these should go away */
172#define IMX_IO_PHYS MX1_IO_BASE_ADDR 170#define IMX_IO_PHYS MX1_IO_BASE_ADDR
173#define IMX_IO_SIZE MX1_IO_SIZE 171#define IMX_IO_SIZE MX1_IO_SIZE
174#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT
175#define IMX_CS0_PHYS MX1_CS0_PHYS 172#define IMX_CS0_PHYS MX1_CS0_PHYS
176#define IMX_CS0_SIZE MX1_CS0_SIZE 173#define IMX_CS0_SIZE MX1_CS0_SIZE
177#define IMX_CS1_PHYS MX1_CS1_PHYS 174#define IMX_CS1_PHYS MX1_CS1_PHYS
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index aed0277ebc93..b417e32072f9 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -26,7 +26,6 @@
26#define __MACH_MX21_H__ 26#define __MACH_MX21_H__
27 27
28#define MX21_AIPI_BASE_ADDR 0x10000000 28#define MX21_AIPI_BASE_ADDR 0x10000000
29#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000
30#define MX21_AIPI_SIZE SZ_1M 29#define MX21_AIPI_SIZE SZ_1M
31#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) 30#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
32#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) 31#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
@@ -64,7 +63,6 @@
64#define MX21_AVIC_BASE_ADDR 0x10040000 63#define MX21_AVIC_BASE_ADDR 0x10040000
65 64
66#define MX21_SAHB1_BASE_ADDR 0x80000000 65#define MX21_SAHB1_BASE_ADDR 0x80000000
67#define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000
68#define MX21_SAHB1_SIZE SZ_1M 66#define MX21_SAHB1_SIZE SZ_1M
69#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) 67#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
70 68
@@ -82,7 +80,6 @@
82 80
83/* NAND, SDRAM, WEIM etc controllers */ 81/* NAND, SDRAM, WEIM etc controllers */
84#define MX21_X_MEMC_BASE_ADDR 0xdf000000 82#define MX21_X_MEMC_BASE_ADDR 0xdf000000
85#define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000
86#define MX21_X_MEMC_SIZE SZ_256K 83#define MX21_X_MEMC_SIZE SZ_256K
87 84
88#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) 85#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
@@ -92,10 +89,7 @@
92 89
93#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ 90#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
94 91
95#define MX21_IO_P2V(x) ( \ 92#define MX21_IO_P2V(x) IMX_IO_P2V(x)
96 IMX_IO_P2V_MODULE(x, MX21_AIPI) ?: \
97 IMX_IO_P2V_MODULE(x, MX21_SAHB1) ?: \
98 IMX_IO_P2V_MODULE(x, MX21_X_MEMC))
99#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) 93#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
100 94
101/* fixed interrupt numbers */ 95/* fixed interrupt numbers */
@@ -197,7 +191,6 @@
197#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR 191#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
198#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR 192#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
199#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR 193#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
200#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT
201#define X_MEMC_SIZE MX21_X_MEMC_SIZE 194#define X_MEMC_SIZE MX21_X_MEMC_SIZE
202#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR 195#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
203#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR 196#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 08b5a3af9432..aac6a9c2b306 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -2,13 +2,11 @@
2#define __MACH_MX25_H__ 2#define __MACH_MX25_H__
3 3
4#define MX25_AIPS1_BASE_ADDR 0x43f00000 4#define MX25_AIPS1_BASE_ADDR 0x43f00000
5#define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000 5#define MX25_AIPS1_BASE_ADDR_VIRT 0xf5300000
6#define MX25_AIPS1_SIZE SZ_1M 6#define MX25_AIPS1_SIZE SZ_1M
7#define MX25_AIPS2_BASE_ADDR 0x53f00000 7#define MX25_AIPS2_BASE_ADDR 0x53f00000
8#define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000
9#define MX25_AIPS2_SIZE SZ_1M 8#define MX25_AIPS2_SIZE SZ_1M
10#define MX25_AVIC_BASE_ADDR 0x68000000 9#define MX25_AVIC_BASE_ADDR 0x68000000
11#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000
12#define MX25_AVIC_SIZE SZ_1M 10#define MX25_AVIC_SIZE SZ_1M
13 11
14#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) 12#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
@@ -27,12 +25,6 @@
27#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) 25#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
28#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) 26#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
29 27
30#define MX25_IO_P2V(x) ( \
31 IMX_IO_P2V_MODULE(x, MX25_AIPS1) ?: \
32 IMX_IO_P2V_MODULE(x, MX25_AIPS2) ?: \
33 IMX_IO_P2V_MODULE(x, MX25_AVIC))
34#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
35
36#define MX25_AIPS1_IO_ADDRESS(x) \ 28#define MX25_AIPS1_IO_ADDRESS(x) \
37 (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) 29 (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
38 30
@@ -58,6 +50,9 @@
58#define MX25_OTG_BASE_ADDR 0x53ff4000 50#define MX25_OTG_BASE_ADDR 0x53ff4000
59#define MX25_CSI_BASE_ADDR 0x53ff8000 51#define MX25_CSI_BASE_ADDR 0x53ff8000
60 52
53#define MX25_IO_P2V(x) IMX_IO_P2V(x)
54#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
55
61#define MX25_INT_CSPI3 0 56#define MX25_INT_CSPI3 0
62#define MX25_INT_I2C1 3 57#define MX25_INT_I2C1 3
63#define MX25_INT_I2C2 4 58#define MX25_INT_I2C2 4
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index c769cc8c0e86..e81728921686 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -29,7 +29,6 @@
29#endif 29#endif
30 30
31#define MX27_AIPI_BASE_ADDR 0x10000000 31#define MX27_AIPI_BASE_ADDR 0x10000000
32#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000
33#define MX27_AIPI_SIZE SZ_1M 32#define MX27_AIPI_SIZE SZ_1M
34#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) 33#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
35#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) 34#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
@@ -87,7 +86,6 @@
87#define MX27_ROMP_BASE_ADDR 0x10041000 86#define MX27_ROMP_BASE_ADDR 0x10041000
88 87
89#define MX27_SAHB1_BASE_ADDR 0x80000000 88#define MX27_SAHB1_BASE_ADDR 0x80000000
90#define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000
91#define MX27_SAHB1_SIZE SZ_1M 89#define MX27_SAHB1_SIZE SZ_1M
92#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) 90#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
93#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) 91#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
@@ -105,7 +103,6 @@
105 103
106/* NAND, SDRAM, WEIM, M3IF, EMI controllers */ 104/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
107#define MX27_X_MEMC_BASE_ADDR 0xd8000000 105#define MX27_X_MEMC_BASE_ADDR 0xd8000000
108#define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000
109#define MX27_X_MEMC_SIZE SZ_1M 106#define MX27_X_MEMC_SIZE SZ_1M
110#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) 107#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
111#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) 108#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
@@ -123,10 +120,7 @@
123/* IRAM */ 120/* IRAM */
124#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ 121#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
125 122
126#define MX27_IO_P2V(x) ( \ 123#define MX27_IO_P2V(x) IMX_IO_P2V(x)
127 IMX_IO_P2V_MODULE(x, MX27_AIPI) ?: \
128 IMX_IO_P2V_MODULE(x, MX27_SAHB1) ?: \
129 IMX_IO_P2V_MODULE(x, MX27_X_MEMC))
130#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) 124#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
131 125
132#ifndef __ASSEMBLER__ 126#ifndef __ASSEMBLER__
@@ -280,7 +274,6 @@ extern int mx27_revision(void);
280#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR 274#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR
281#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR 275#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR
282#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR 276#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR
283#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT
284#define X_MEMC_SIZE MX27_X_MEMC_SIZE 277#define X_MEMC_SIZE MX27_X_MEMC_SIZE
285#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR 278#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR
286#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR 279#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index afb895a0b5b8..46eeeb21533d 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -27,7 +27,7 @@
27 27
28/* Register offsets */ 28/* Register offsets */
29#define MX2x_AIPI_BASE_ADDR 0x10000000 29#define MX2x_AIPI_BASE_ADDR 0x10000000
30#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000 30#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4400000
31#define MX2x_AIPI_SIZE SZ_1M 31#define MX2x_AIPI_SIZE SZ_1M
32#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) 32#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
33#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) 33#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
@@ -65,43 +65,12 @@
65#define MX2x_AVIC_BASE_ADDR 0x10040000 65#define MX2x_AVIC_BASE_ADDR 0x10040000
66 66
67#define MX2x_SAHB1_BASE_ADDR 0x80000000 67#define MX2x_SAHB1_BASE_ADDR 0x80000000
68#define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000
69#define MX2x_SAHB1_SIZE SZ_1M 68#define MX2x_SAHB1_SIZE SZ_1M
70#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) 69#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
71 70
72/* 71#define AIPI_IO_ADDRESS(x) \
73 * This macro defines the physical to virtual address mapping for all the
74 * peripheral modules. It is used by passing in the physical address as x
75 * and returning the virtual address. If the physical address is not mapped,
76 * it returns 0xDEADBEEF
77 */
78#define IO_ADDRESS(x) \
79 (void __force __iomem *) \
80 (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
81 AIPI_IO_ADDRESS(x) : \
82 ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
83 SAHB1_IO_ADDRESS(x) : \
84 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
85 X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
86
87/* define the address mapping macros: in physical address order */
88#define AIPI_IO_ADDRESS(x) \
89 (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT) 72 (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
90 73
91#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
92
93#define SAHB1_IO_ADDRESS(x) \
94 (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
95
96#define CS4_IO_ADDRESS(x) \
97 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
98
99#define X_MEMC_IO_ADDRESS(x) \
100 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
101
102#define PCMCIA_IO_ADDRESS(x) \
103 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
104
105/* fixed interrupt numbers */ 74/* fixed interrupt numbers */
106#define MX2x_INT_CSPI3 6 75#define MX2x_INT_CSPI3 6
107#define MX2x_INT_GPIO 8 76#define MX2x_INT_GPIO 8
@@ -215,7 +184,6 @@
215#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR 184#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
216#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR 185#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
217#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR 186#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
218#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT
219#define SAHB1_SIZE MX2x_SAHB1_SIZE 187#define SAHB1_SIZE MX2x_SAHB1_SIZE
220#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR 188#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
221#define MXC_INT_CSPI3 MX2x_INT_CSPI3 189#define MXC_INT_CSPI3 MX2x_INT_CSPI3
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index eb4a28dc2686..9ed9975bc9be 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -15,7 +15,6 @@
15#define MX31_L2CC_SIZE SZ_1M 15#define MX31_L2CC_SIZE SZ_1M
16 16
17#define MX31_AIPS1_BASE_ADDR 0x43f00000 17#define MX31_AIPS1_BASE_ADDR 0x43f00000
18#define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000
19#define MX31_AIPS1_SIZE SZ_1M 18#define MX31_AIPS1_SIZE SZ_1M
20#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) 19#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
21#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) 20#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
@@ -41,7 +40,6 @@
41#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) 40#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
42 41
43#define MX31_SPBA0_BASE_ADDR 0x50000000 42#define MX31_SPBA0_BASE_ADDR 0x50000000
44#define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000
45#define MX31_SPBA0_SIZE SZ_1M 43#define MX31_SPBA0_SIZE SZ_1M
46#define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) 44#define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
47#define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) 45#define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
@@ -55,7 +53,6 @@
55#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) 53#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
56 54
57#define MX31_AIPS2_BASE_ADDR 0x53f00000 55#define MX31_AIPS2_BASE_ADDR 0x53f00000
58#define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000
59#define MX31_AIPS2_SIZE SZ_1M 56#define MX31_AIPS2_SIZE SZ_1M
60#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) 57#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
61#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) 58#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
@@ -84,7 +81,6 @@
84#define MX31_ROMP_SIZE SZ_1M 81#define MX31_ROMP_SIZE SZ_1M
85 82
86#define MX31_AVIC_BASE_ADDR 0x68000000 83#define MX31_AVIC_BASE_ADDR 0x68000000
87#define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000
88#define MX31_AVIC_SIZE SZ_1M 84#define MX31_AVIC_SIZE SZ_1M
89 85
90#define MX31_IPU_MEM_BASE_ADDR 0x70000000 86#define MX31_IPU_MEM_BASE_ADDR 0x70000000
@@ -97,15 +93,14 @@
97#define MX31_CS3_BASE_ADDR 0xb2000000 93#define MX31_CS3_BASE_ADDR 0xb2000000
98 94
99#define MX31_CS4_BASE_ADDR 0xb4000000 95#define MX31_CS4_BASE_ADDR 0xb4000000
100#define MX31_CS4_BASE_ADDR_VIRT 0xf4000000 96#define MX31_CS4_BASE_ADDR_VIRT 0xf6000000
101#define MX31_CS4_SIZE SZ_32M 97#define MX31_CS4_SIZE SZ_32M
102 98
103#define MX31_CS5_BASE_ADDR 0xb6000000 99#define MX31_CS5_BASE_ADDR 0xb6000000
104#define MX31_CS5_BASE_ADDR_VIRT 0xf6000000 100#define MX31_CS5_BASE_ADDR_VIRT 0xf8000000
105#define MX31_CS5_SIZE SZ_32M 101#define MX31_CS5_SIZE SZ_32M
106 102
107#define MX31_X_MEMC_BASE_ADDR 0xb8000000 103#define MX31_X_MEMC_BASE_ADDR 0xb8000000
108#define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000
109#define MX31_X_MEMC_SIZE SZ_64K 104#define MX31_X_MEMC_SIZE SZ_64K
110#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) 105#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
111#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) 106#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
@@ -121,12 +116,7 @@
121 116
122#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 117#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
123 118
124#define MX31_IO_P2V(x) ( \ 119#define MX31_IO_P2V(x) IMX_IO_P2V(x)
125 IMX_IO_P2V_MODULE(x, MX31_AIPS1) ?: \
126 IMX_IO_P2V_MODULE(x, MX31_AIPS2) ?: \
127 IMX_IO_P2V_MODULE(x, MX31_AVIC) ?: \
128 IMX_IO_P2V_MODULE(x, MX31_X_MEMC) ?: \
129 IMX_IO_P2V_MODULE(x, MX31_SPBA0))
130#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) 120#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
131 121
132#ifndef __ASSEMBLER__ 122#ifndef __ASSEMBLER__
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index ce1a24b09337..3678ca3f920a 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -11,7 +11,6 @@
11#define MX35_L2CC_SIZE SZ_1M 11#define MX35_L2CC_SIZE SZ_1M
12 12
13#define MX35_AIPS1_BASE_ADDR 0x43f00000 13#define MX35_AIPS1_BASE_ADDR 0x43f00000
14#define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000
15#define MX35_AIPS1_SIZE SZ_1M 14#define MX35_AIPS1_SIZE SZ_1M
16#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) 15#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
17#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) 16#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
@@ -33,7 +32,6 @@
33#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) 32#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
34 33
35#define MX35_SPBA0_BASE_ADDR 0x50000000 34#define MX35_SPBA0_BASE_ADDR 0x50000000
36#define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000
37#define MX35_SPBA0_SIZE SZ_1M 35#define MX35_SPBA0_SIZE SZ_1M
38#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) 36#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
39#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) 37#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
@@ -44,7 +42,6 @@
44#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) 42#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
45 43
46#define MX35_AIPS2_BASE_ADDR 0x53f00000 44#define MX35_AIPS2_BASE_ADDR 0x53f00000
47#define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000
48#define MX35_AIPS2_SIZE SZ_1M 45#define MX35_AIPS2_SIZE SZ_1M
49#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) 46#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
50#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) 47#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
@@ -72,11 +69,9 @@
72#define MX35_OTG_BASE_ADDR 0x53ff4000 69#define MX35_OTG_BASE_ADDR 0x53ff4000
73 70
74#define MX35_ROMP_BASE_ADDR 0x60000000 71#define MX35_ROMP_BASE_ADDR 0x60000000
75#define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000
76#define MX35_ROMP_SIZE SZ_1M 72#define MX35_ROMP_SIZE SZ_1M
77 73
78#define MX35_AVIC_BASE_ADDR 0x68000000 74#define MX35_AVIC_BASE_ADDR 0x68000000
79#define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000
80#define MX35_AVIC_SIZE SZ_1M 75#define MX35_AVIC_SIZE SZ_1M
81 76
82/* 77/*
@@ -92,18 +87,17 @@
92#define MX35_CS3_BASE_ADDR 0xb2000000 87#define MX35_CS3_BASE_ADDR 0xb2000000
93 88
94#define MX35_CS4_BASE_ADDR 0xb4000000 89#define MX35_CS4_BASE_ADDR 0xb4000000
95#define MX35_CS4_BASE_ADDR_VIRT 0xf4000000 90#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000
96#define MX35_CS4_SIZE SZ_32M 91#define MX35_CS4_SIZE SZ_32M
97 92
98#define MX35_CS5_BASE_ADDR 0xb6000000 93#define MX35_CS5_BASE_ADDR 0xb6000000
99#define MX35_CS5_BASE_ADDR_VIRT 0xf6000000 94#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000
100#define MX35_CS5_SIZE SZ_32M 95#define MX35_CS5_SIZE SZ_32M
101 96
102/* 97/*
103 * NAND, SDRAM, WEIM, M3IF, EMI controllers 98 * NAND, SDRAM, WEIM, M3IF, EMI controllers
104 */ 99 */
105#define MX35_X_MEMC_BASE_ADDR 0xb8000000 100#define MX35_X_MEMC_BASE_ADDR 0xb8000000
106#define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000
107#define MX35_X_MEMC_SIZE SZ_64K 101#define MX35_X_MEMC_SIZE SZ_64K
108#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) 102#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
109#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) 103#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
@@ -114,12 +108,7 @@
114#define MX35_NFC_BASE_ADDR 0xbb000000 108#define MX35_NFC_BASE_ADDR 0xbb000000
115#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 109#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
116 110
117#define MX35_IO_P2V(x) ( \ 111#define MX35_IO_P2V(x) IMX_IO_P2V(x)
118 IMX_IO_P2V_MODULE(x, MX35_AIPS1) ?: \
119 IMX_IO_P2V_MODULE(x, MX35_AIPS2) ?: \
120 IMX_IO_P2V_MODULE(x, MX35_AVIC) ?: \
121 IMX_IO_P2V_MODULE(x, MX35_X_MEMC) ?: \
122 IMX_IO_P2V_MODULE(x, MX35_SPBA0))
123#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x)) 112#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x))
124 113
125/* 114/*
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index d1bd26d7b8a6..da22cd481829 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -44,7 +44,7 @@
44 * AIPS 1 44 * AIPS 1
45 */ 45 */
46#define MX3x_AIPS1_BASE_ADDR 0x43f00000 46#define MX3x_AIPS1_BASE_ADDR 0x43f00000
47#define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000 47#define MX3x_AIPS1_BASE_ADDR_VIRT 0xf5300000
48#define MX3x_AIPS1_SIZE SZ_1M 48#define MX3x_AIPS1_SIZE SZ_1M
49#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) 49#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
50#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) 50#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
@@ -69,7 +69,6 @@
69 * SPBA global module enabled #0 69 * SPBA global module enabled #0
70 */ 70 */
71#define MX3x_SPBA0_BASE_ADDR 0x50000000 71#define MX3x_SPBA0_BASE_ADDR 0x50000000
72#define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000
73#define MX3x_SPBA0_SIZE SZ_1M 72#define MX3x_SPBA0_SIZE SZ_1M
74#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) 73#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000)
75#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) 74#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000)
@@ -82,7 +81,6 @@
82 * AIPS 2 81 * AIPS 2
83 */ 82 */
84#define MX3x_AIPS2_BASE_ADDR 0x53f00000 83#define MX3x_AIPS2_BASE_ADDR 0x53f00000
85#define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000
86#define MX3x_AIPS2_SIZE SZ_1M 84#define MX3x_AIPS2_SIZE SZ_1M
87#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) 85#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000)
88#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) 86#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000)
@@ -105,11 +103,9 @@
105 * ROMP and AVIC 103 * ROMP and AVIC
106 */ 104 */
107#define MX3x_ROMP_BASE_ADDR 0x60000000 105#define MX3x_ROMP_BASE_ADDR 0x60000000
108#define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000
109#define MX3x_ROMP_SIZE SZ_1M 106#define MX3x_ROMP_SIZE SZ_1M
110 107
111#define MX3x_AVIC_BASE_ADDR 0x68000000 108#define MX3x_AVIC_BASE_ADDR 0x68000000
112#define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000
113#define MX3x_AVIC_SIZE SZ_1M 109#define MX3x_AVIC_SIZE SZ_1M
114 110
115/* 111/*
@@ -125,18 +121,17 @@
125#define MX3x_CS3_BASE_ADDR 0xb2000000 121#define MX3x_CS3_BASE_ADDR 0xb2000000
126 122
127#define MX3x_CS4_BASE_ADDR 0xb4000000 123#define MX3x_CS4_BASE_ADDR 0xb4000000
128#define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000 124#define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000
129#define MX3x_CS4_SIZE SZ_32M 125#define MX3x_CS4_SIZE SZ_32M
130 126
131#define MX3x_CS5_BASE_ADDR 0xb6000000 127#define MX3x_CS5_BASE_ADDR 0xb6000000
132#define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000 128#define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000
133#define MX3x_CS5_SIZE SZ_32M 129#define MX3x_CS5_SIZE SZ_32M
134 130
135/* 131/*
136 * NAND, SDRAM, WEIM, M3IF, EMI controllers 132 * NAND, SDRAM, WEIM, M3IF, EMI controllers
137 */ 133 */
138#define MX3x_X_MEMC_BASE_ADDR 0xb8000000 134#define MX3x_X_MEMC_BASE_ADDR 0xb8000000
139#define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000
140#define MX3x_X_MEMC_SIZE SZ_64K 135#define MX3x_X_MEMC_SIZE SZ_64K
141#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) 136#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000)
142#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) 137#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000)
@@ -146,56 +141,9 @@
146 141
147#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 142#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000
148 143
149/*!
150 * This macro defines the physical to virtual address mapping for all the
151 * peripheral modules. It is used by passing in the physical address as x
152 * and returning the virtual address. If the physical address is not mapped,
153 * it returns 0xDEADBEEF
154 */
155#define IO_ADDRESS(x) \
156 (void __force __iomem *) \
157 (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
158 ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
159 ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
160 ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
161 ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
162 ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
163 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
164 0xDEADBEEF)
165
166/*
167 * define the address mapping macros: in physical address order
168 */
169#define L2CC_IO_ADDRESS(x) \
170 (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
171
172#define AIPS1_IO_ADDRESS(x) \ 144#define AIPS1_IO_ADDRESS(x) \
173 (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) 145 (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
174 146
175#define SPBA0_IO_ADDRESS(x) \
176 (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
177
178#define AIPS2_IO_ADDRESS(x) \
179 (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
180
181#define ROMP_IO_ADDRESS(x) \
182 (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
183
184#define AVIC_IO_ADDRESS(x) \
185 (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
186
187#define CS4_IO_ADDRESS(x) \
188 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
189
190#define CS5_IO_ADDRESS(x) \
191 (((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT)
192
193#define X_MEMC_IO_ADDRESS(x) \
194 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
195
196#define PCMCIA_IO_ADDRESS(x) \
197 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
198
199/* 147/*
200 * Interrupt numbers 148 * Interrupt numbers
201 */ 149 */
@@ -303,7 +251,6 @@ static inline int mx35_revision(void)
303#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR 251#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR
304#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR 252#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR
305#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR 253#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR
306#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT
307#define SPBA0_SIZE MX3x_SPBA0_SIZE 254#define SPBA0_SIZE MX3x_SPBA0_SIZE
308#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR 255#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR
309#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR 256#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR
@@ -312,7 +259,6 @@ static inline int mx35_revision(void)
312#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR 259#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR
313#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR 260#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR
314#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR 261#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR
315#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT
316#define AIPS2_SIZE MX3x_AIPS2_SIZE 262#define AIPS2_SIZE MX3x_AIPS2_SIZE
317#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR 263#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR
318#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR 264#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR
@@ -331,10 +277,8 @@ static inline int mx35_revision(void)
331#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR 277#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR
332#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR 278#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR
333#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR 279#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR
334#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT
335#define ROMP_SIZE MX3x_ROMP_SIZE 280#define ROMP_SIZE MX3x_ROMP_SIZE
336#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR 281#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR
337#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT
338#define AVIC_SIZE MX3x_AVIC_SIZE 282#define AVIC_SIZE MX3x_AVIC_SIZE
339#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR 283#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR
340#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR 284#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR
@@ -344,13 +288,10 @@ static inline int mx35_revision(void)
344#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR 288#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR
345#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR 289#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR
346#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR 290#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR
347#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT
348#define CS4_SIZE MX3x_CS4_SIZE 291#define CS4_SIZE MX3x_CS4_SIZE
349#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR 292#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR
350#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT
351#define CS5_SIZE MX3x_CS5_SIZE 293#define CS5_SIZE MX3x_CS5_SIZE
352#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR 294#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR
353#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT
354#define X_MEMC_SIZE MX3x_X_MEMC_SIZE 295#define X_MEMC_SIZE MX3x_X_MEMC_SIZE
355#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR 296#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR
356#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR 297#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index e93cf5be90a4..1b8715f28477 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -2,31 +2,6 @@
2#define __MACH_MX51_H__ 2#define __MACH_MX51_H__
3 3
4/* 4/*
5 * MX51 memory map:
6 *
7 *
8 * Virt Phys Size What
9 * ---------------------------------------------------------------------------
10 * fa3e0000 1ffe0000 128K IRAM (SCCv2 RAM)
11 * 30000000 256M GPU
12 * 40000000 512M IPU
13 * fa200000 60000000 1M DEBUG
14 * fb100000 70000000 1M SPBA 0
15 * fb000000 73f00000 1M AIPS 1
16 * fb200000 83f00000 1M AIPS 2
17 * 8fffc000 16K TZIC (interrupt controller)
18 * 90000000 256M CSD0 SDRAM/DDR
19 * a0000000 256M CSD1 SDRAM/DDR
20 * b0000000 128M CS0 Flash
21 * b8000000 128M CS1 Flash
22 * c0000000 128M CS2 Flash
23 * c8000000 64M CS3 Flash
24 * cc000000 32M CS4 SRAM
25 * ce000000 32M CS5 SRAM
26 * cfff0000 64K NFC (NAND Flash AXI)
27 */
28
29/*
30 * IROM 5 * IROM
31 */ 6 */
32#define MX51_IROM_BASE_ADDR 0x0 7#define MX51_IROM_BASE_ADDR 0x0
@@ -36,7 +11,6 @@
36 * IRAM 11 * IRAM
37 */ 12 */
38#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ 13#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */
39#define MX51_IRAM_BASE_ADDR_VIRT 0xfa3e0000
40#define MX51_IRAM_PARTITIONS 16 14#define MX51_IRAM_PARTITIONS 16
41#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ 15#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
42 16
@@ -45,7 +19,6 @@
45#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 19#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
46 20
47#define MX51_DEBUG_BASE_ADDR 0x60000000 21#define MX51_DEBUG_BASE_ADDR 0x60000000
48#define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000
49#define MX51_DEBUG_SIZE SZ_1M 22#define MX51_DEBUG_SIZE SZ_1M
50 23
51#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) 24#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000)
@@ -61,7 +34,6 @@
61 * SPBA global module enabled #0 34 * SPBA global module enabled #0
62 */ 35 */
63#define MX51_SPBA0_BASE_ADDR 0x70000000 36#define MX51_SPBA0_BASE_ADDR 0x70000000
64#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000
65#define MX51_SPBA0_SIZE SZ_1M 37#define MX51_SPBA0_SIZE SZ_1M
66 38
67#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) 39#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
@@ -81,7 +53,7 @@
81 * AIPS 1 53 * AIPS 1
82 */ 54 */
83#define MX51_AIPS1_BASE_ADDR 0x73f00000 55#define MX51_AIPS1_BASE_ADDR 0x73f00000
84#define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000 56#define MX51_AIPS1_BASE_ADDR_VIRT 0xf5700000
85#define MX51_AIPS1_SIZE SZ_1M 57#define MX51_AIPS1_SIZE SZ_1M
86 58
87#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) 59#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000)
@@ -109,7 +81,6 @@
109 * AIPS 2 81 * AIPS 2
110 */ 82 */
111#define MX51_AIPS2_BASE_ADDR 0x83f00000 83#define MX51_AIPS2_BASE_ADDR 0x83f00000
112#define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000
113#define MX51_AIPS2_SIZE SZ_1M 84#define MX51_AIPS2_SIZE SZ_1M
114 85
115#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) 86#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000)
@@ -163,12 +134,7 @@
163#define MX51_GPU2D_BASE_ADDR 0xd0000000 134#define MX51_GPU2D_BASE_ADDR 0xd0000000
164#define MX51_TZIC_BASE_ADDR 0xe0000000 135#define MX51_TZIC_BASE_ADDR 0xe0000000
165 136
166#define MX51_IO_P2V(x) ( \ 137#define MX51_IO_P2V(x) IMX_IO_P2V(x)
167 IMX_IO_P2V_MODULE(x, MX51_IRAM) ?: \
168 IMX_IO_P2V_MODULE(x, MX51_DEBUG) ?: \
169 IMX_IO_P2V_MODULE(x, MX51_SPBA0) ?: \
170 IMX_IO_P2V_MODULE(x, MX51_AIPS1) ?: \
171 IMX_IO_P2V_MODULE(x, MX51_AIPS2))
172#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) 138#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x))
173 139
174/* This is currently used in <mach/debug-macro.S>, but should go away */ 140/* This is currently used in <mach/debug-macro.S>, but should go away */
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
index 49e5e25000fc..765190fe6332 100644
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -21,14 +21,12 @@
21 * L2CC 21 * L2CC
22 */ 22 */
23#define MXC91231_L2CC_BASE_ADDR 0x30000000 23#define MXC91231_L2CC_BASE_ADDR 0x30000000
24#define MXC91231_L2CC_BASE_ADDR_VIRT 0xF9000000
25#define MXC91231_L2CC_SIZE SZ_64K 24#define MXC91231_L2CC_SIZE SZ_64K
26 25
27/* 26/*
28 * AIPS 1 27 * AIPS 1
29 */ 28 */
30#define MXC91231_AIPS1_BASE_ADDR 0x43F00000 29#define MXC91231_AIPS1_BASE_ADDR 0x43F00000
31#define MXC91231_AIPS1_BASE_ADDR_VIRT 0xFC000000
32#define MXC91231_AIPS1_SIZE SZ_1M 30#define MXC91231_AIPS1_SIZE SZ_1M
33 31
34#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR 32#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR
@@ -53,7 +51,6 @@
53 * AIPS 2 51 * AIPS 2
54 */ 52 */
55#define MXC91231_AIPS2_BASE_ADDR 0x53F00000 53#define MXC91231_AIPS2_BASE_ADDR 0x53F00000
56#define MXC91231_AIPS2_BASE_ADDR_VIRT 0xFC100000
57#define MXC91231_AIPS2_SIZE SZ_1M 54#define MXC91231_AIPS2_SIZE SZ_1M
58 55
59#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) 56#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
@@ -79,7 +76,6 @@
79 * SPBA global module 0 76 * SPBA global module 0
80 */ 77 */
81#define MXC91231_SPBA0_BASE_ADDR 0x50000000 78#define MXC91231_SPBA0_BASE_ADDR 0x50000000
82#define MXC91231_SPBA0_BASE_ADDR_VIRT 0xFC200000
83#define MXC91231_SPBA0_SIZE SZ_1M 79#define MXC91231_SPBA0_SIZE SZ_1M
84 80
85#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) 81#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000)
@@ -109,7 +105,6 @@
109 * SPBA global module 1 105 * SPBA global module 1
110 */ 106 */
111#define MXC91231_SPBA1_BASE_ADDR 0x52000000 107#define MXC91231_SPBA1_BASE_ADDR 0x52000000
112#define MXC91231_SPBA1_BASE_ADDR_VIRT 0xFC300000
113#define MXC91231_SPBA1_SIZE SZ_1M 108#define MXC91231_SPBA1_SIZE SZ_1M
114 109
115#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) 110#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000)
@@ -144,18 +139,15 @@
144 * ROMP and AVIC 139 * ROMP and AVIC
145 */ 140 */
146#define MXC91231_ROMP_BASE_ADDR 0x60000000 141#define MXC91231_ROMP_BASE_ADDR 0x60000000
147#define MXC91231_ROMP_BASE_ADDR_VIRT 0xFC400000
148#define MXC91231_ROMP_SIZE SZ_64K 142#define MXC91231_ROMP_SIZE SZ_64K
149 143
150#define MXC91231_AVIC_BASE_ADDR 0x68000000 144#define MXC91231_AVIC_BASE_ADDR 0x68000000
151#define MXC91231_AVIC_BASE_ADDR_VIRT 0xFC410000
152#define MXC91231_AVIC_SIZE SZ_64K 145#define MXC91231_AVIC_SIZE SZ_64K
153 146
154/* 147/*
155 * NAND, SDRAM, WEIM, M3IF, EMI controllers 148 * NAND, SDRAM, WEIM, M3IF, EMI controllers
156 */ 149 */
157#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 150#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000
158#define MXC91231_X_MEMC_BASE_ADDR_VIRT 0xFC420000
159#define MXC91231_X_MEMC_SIZE SZ_64K 151#define MXC91231_X_MEMC_SIZE SZ_64K
160 152
161#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) 153#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
@@ -183,19 +175,9 @@
183/* 175/*
184 * This macro defines the physical to virtual address mapping for all the 176 * This macro defines the physical to virtual address mapping for all the
185 * peripheral modules. It is used by passing in the physical address as x 177 * peripheral modules. It is used by passing in the physical address as x
186 * and returning the virtual address. If the physical address is not mapped, 178 * and returning the virtual address.
187 * it returns 0.
188 */ 179 */
189 180#define MXC91231_IO_P2V(x) IMX_IO_P2V(x)
190#define MXC91231_IO_P2V(x) ( \
191 IMX_IO_P2V_MODULE(x, MXC91231_L2CC) ?: \
192 IMX_IO_P2V_MODULE(x, MXC91231_X_MEMC) ?: \
193 IMX_IO_P2V_MODULE(x, MXC91231_ROMP) ?: \
194 IMX_IO_P2V_MODULE(x, MXC91231_AVIC) ?: \
195 IMX_IO_P2V_MODULE(x, MXC91231_AIPS1) ?: \
196 IMX_IO_P2V_MODULE(x, MXC91231_SPBA0) ?: \
197 IMX_IO_P2V_MODULE(x, MXC91231_SPBA1) ?: \
198 IMX_IO_P2V_MODULE(x, MXC91231_AIPS2))
199#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x)) 181#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x))
200 182
201/* 183/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 12:16:05 -0500