diff options
-rw-r--r-- | drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c | 4 | ||||
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-cherryview.c | 44 | ||||
-rw-r--r-- | drivers/pinctrl/meson/pinctrl-meson.c | 2 | ||||
-rw-r--r-- | drivers/pinctrl/meson/pinctrl-meson8b.c | 4 |
4 files changed, 50 insertions, 4 deletions
diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c index 4ad5c1a996e3..e406e3d8c1c7 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c | |||
@@ -643,7 +643,9 @@ static const struct cygnus_gpio_pin_range cygnus_gpio_pintable[] = { | |||
643 | CYGNUS_PINRANGE(87, 104, 12), | 643 | CYGNUS_PINRANGE(87, 104, 12), |
644 | CYGNUS_PINRANGE(99, 102, 2), | 644 | CYGNUS_PINRANGE(99, 102, 2), |
645 | CYGNUS_PINRANGE(101, 90, 4), | 645 | CYGNUS_PINRANGE(101, 90, 4), |
646 | CYGNUS_PINRANGE(105, 116, 10), | 646 | CYGNUS_PINRANGE(105, 116, 6), |
647 | CYGNUS_PINRANGE(111, 100, 2), | ||
648 | CYGNUS_PINRANGE(113, 122, 4), | ||
647 | CYGNUS_PINRANGE(123, 11, 1), | 649 | CYGNUS_PINRANGE(123, 11, 1), |
648 | CYGNUS_PINRANGE(124, 38, 4), | 650 | CYGNUS_PINRANGE(124, 38, 4), |
649 | CYGNUS_PINRANGE(128, 43, 1), | 651 | CYGNUS_PINRANGE(128, 43, 1), |
diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 82f691eeeec4..732ff757a95f 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c | |||
@@ -1292,6 +1292,49 @@ static void chv_gpio_irq_unmask(struct irq_data *d) | |||
1292 | chv_gpio_irq_mask_unmask(d, false); | 1292 | chv_gpio_irq_mask_unmask(d, false); |
1293 | } | 1293 | } |
1294 | 1294 | ||
1295 | static unsigned chv_gpio_irq_startup(struct irq_data *d) | ||
1296 | { | ||
1297 | /* | ||
1298 | * Check if the interrupt has been requested with 0 as triggering | ||
1299 | * type. In that case it is assumed that the current values | ||
1300 | * programmed to the hardware are used (e.g BIOS configured | ||
1301 | * defaults). | ||
1302 | * | ||
1303 | * In that case ->irq_set_type() will never be called so we need to | ||
1304 | * read back the values from hardware now, set correct flow handler | ||
1305 | * and update mappings before the interrupt is being used. | ||
1306 | */ | ||
1307 | if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { | ||
1308 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | ||
1309 | struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); | ||
1310 | unsigned offset = irqd_to_hwirq(d); | ||
1311 | int pin = chv_gpio_offset_to_pin(pctrl, offset); | ||
1312 | irq_flow_handler_t handler; | ||
1313 | unsigned long flags; | ||
1314 | u32 intsel, value; | ||
1315 | |||
1316 | intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); | ||
1317 | intsel &= CHV_PADCTRL0_INTSEL_MASK; | ||
1318 | intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; | ||
1319 | |||
1320 | value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); | ||
1321 | if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) | ||
1322 | handler = handle_level_irq; | ||
1323 | else | ||
1324 | handler = handle_edge_irq; | ||
1325 | |||
1326 | spin_lock_irqsave(&pctrl->lock, flags); | ||
1327 | if (!pctrl->intr_lines[intsel]) { | ||
1328 | __irq_set_handler_locked(d->irq, handler); | ||
1329 | pctrl->intr_lines[intsel] = offset; | ||
1330 | } | ||
1331 | spin_unlock_irqrestore(&pctrl->lock, flags); | ||
1332 | } | ||
1333 | |||
1334 | chv_gpio_irq_unmask(d); | ||
1335 | return 0; | ||
1336 | } | ||
1337 | |||
1295 | static int chv_gpio_irq_type(struct irq_data *d, unsigned type) | 1338 | static int chv_gpio_irq_type(struct irq_data *d, unsigned type) |
1296 | { | 1339 | { |
1297 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | 1340 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
@@ -1357,6 +1400,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned type) | |||
1357 | 1400 | ||
1358 | static struct irq_chip chv_gpio_irqchip = { | 1401 | static struct irq_chip chv_gpio_irqchip = { |
1359 | .name = "chv-gpio", | 1402 | .name = "chv-gpio", |
1403 | .irq_startup = chv_gpio_irq_startup, | ||
1360 | .irq_ack = chv_gpio_irq_ack, | 1404 | .irq_ack = chv_gpio_irq_ack, |
1361 | .irq_mask = chv_gpio_irq_mask, | 1405 | .irq_mask = chv_gpio_irq_mask, |
1362 | .irq_unmask = chv_gpio_irq_unmask, | 1406 | .irq_unmask = chv_gpio_irq_unmask, |
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index edcd140e0899..a70a5fe79d44 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c | |||
@@ -569,7 +569,7 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc) | |||
569 | domain->chip.direction_output = meson_gpio_direction_output; | 569 | domain->chip.direction_output = meson_gpio_direction_output; |
570 | domain->chip.get = meson_gpio_get; | 570 | domain->chip.get = meson_gpio_get; |
571 | domain->chip.set = meson_gpio_set; | 571 | domain->chip.set = meson_gpio_set; |
572 | domain->chip.base = -1; | 572 | domain->chip.base = domain->data->pin_base; |
573 | domain->chip.ngpio = domain->data->num_pins; | 573 | domain->chip.ngpio = domain->data->num_pins; |
574 | domain->chip.can_sleep = false; | 574 | domain->chip.can_sleep = false; |
575 | domain->chip.of_node = domain->of_node; | 575 | domain->chip.of_node = domain->of_node; |
diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c index 2f7ea6229880..9677807db364 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8b.c +++ b/drivers/pinctrl/meson/pinctrl-meson8b.c | |||
@@ -876,13 +876,13 @@ static struct meson_domain_data meson8b_domain_data[] = { | |||
876 | .banks = meson8b_banks, | 876 | .banks = meson8b_banks, |
877 | .num_banks = ARRAY_SIZE(meson8b_banks), | 877 | .num_banks = ARRAY_SIZE(meson8b_banks), |
878 | .pin_base = 0, | 878 | .pin_base = 0, |
879 | .num_pins = 83, | 879 | .num_pins = 130, |
880 | }, | 880 | }, |
881 | { | 881 | { |
882 | .name = "ao-bank", | 882 | .name = "ao-bank", |
883 | .banks = meson8b_ao_banks, | 883 | .banks = meson8b_ao_banks, |
884 | .num_banks = ARRAY_SIZE(meson8b_ao_banks), | 884 | .num_banks = ARRAY_SIZE(meson8b_ao_banks), |
885 | .pin_base = 83, | 885 | .pin_base = 130, |
886 | .num_pins = 16, | 886 | .num_pins = 16, |
887 | }, | 887 | }, |
888 | }; | 888 | }; |