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-rw-r--r--drivers/net/ethernet/amd/7990.c836
-rw-r--r--drivers/net/ethernet/amd/7990.h268
-rw-r--r--drivers/net/ethernet/amd/hplance.c96
-rw-r--r--drivers/net/ethernet/amd/mvme147.c36
4 files changed, 619 insertions, 617 deletions
diff --git a/drivers/net/ethernet/amd/7990.c b/drivers/net/ethernet/amd/7990.c
index 65926a956575..72cfff7d23a5 100644
--- a/drivers/net/ethernet/amd/7990.c
+++ b/drivers/net/ethernet/amd/7990.c
@@ -42,9 +42,9 @@
42 42
43#include "7990.h" 43#include "7990.h"
44 44
45#define WRITERAP(lp,x) out_be16(lp->base + LANCE_RAP, (x)) 45#define WRITERAP(lp, x) out_be16(lp->base + LANCE_RAP, (x))
46#define WRITERDP(lp,x) out_be16(lp->base + LANCE_RDP, (x)) 46#define WRITERDP(lp, x) out_be16(lp->base + LANCE_RDP, (x))
47#define READRDP(lp) in_be16(lp->base + LANCE_RDP) 47#define READRDP(lp) in_be16(lp->base + LANCE_RDP)
48 48
49#if defined(CONFIG_HPLANCE) || defined(CONFIG_HPLANCE_MODULE) 49#if defined(CONFIG_HPLANCE) || defined(CONFIG_HPLANCE_MODULE)
50#include "hplance.h" 50#include "hplance.h"
@@ -56,9 +56,9 @@
56#if defined(CONFIG_MVME147_NET) || defined(CONFIG_MVME147_NET_MODULE) 56#if defined(CONFIG_MVME147_NET) || defined(CONFIG_MVME147_NET_MODULE)
57 57
58/* Lossage Factor Nine, Mr Sulu. */ 58/* Lossage Factor Nine, Mr Sulu. */
59#define WRITERAP(lp,x) (lp->writerap(lp,x)) 59#define WRITERAP(lp, x) (lp->writerap(lp, x))
60#define WRITERDP(lp,x) (lp->writerdp(lp,x)) 60#define WRITERDP(lp, x) (lp->writerdp(lp, x))
61#define READRDP(lp) (lp->readrdp(lp)) 61#define READRDP(lp) (lp->readrdp(lp))
62 62
63#else 63#else
64 64
@@ -94,428 +94,436 @@ static inline __u16 READRDP(struct lance_private *lp)
94#ifdef UNDEF 94#ifdef UNDEF
95#define PRINT_RINGS() \ 95#define PRINT_RINGS() \
96do { \ 96do { \
97 int t; \ 97 int t; \
98 for (t=0; t < RX_RING_SIZE; t++) { \ 98 for (t = 0; t < RX_RING_SIZE; t++) { \
99 printk("R%d: @(%02X %04X) len %04X, mblen %04X, bits %02X\n",\ 99 printk("R%d: @(%02X %04X) len %04X, mblen %04X, bits %02X\n", \
100 t, ib->brx_ring[t].rmd1_hadr, ib->brx_ring[t].rmd0,\ 100 t, ib->brx_ring[t].rmd1_hadr, ib->brx_ring[t].rmd0, \
101 ib->brx_ring[t].length,\ 101 ib->brx_ring[t].length, \
102 ib->brx_ring[t].mblength, ib->brx_ring[t].rmd1_bits);\ 102 ib->brx_ring[t].mblength, ib->brx_ring[t].rmd1_bits); \
103 }\ 103 } \
104 for (t=0; t < TX_RING_SIZE; t++) { \ 104 for (t = 0; t < TX_RING_SIZE; t++) { \
105 printk("T%d: @(%02X %04X) len %04X, misc %04X, bits %02X\n",\ 105 printk("T%d: @(%02X %04X) len %04X, misc %04X, bits %02X\n", \
106 t, ib->btx_ring[t].tmd1_hadr, ib->btx_ring[t].tmd0,\ 106 t, ib->btx_ring[t].tmd1_hadr, ib->btx_ring[t].tmd0, \
107 ib->btx_ring[t].length,\ 107 ib->btx_ring[t].length, \
108 ib->btx_ring[t].misc, ib->btx_ring[t].tmd1_bits);\ 108 ib->btx_ring[t].misc, ib->btx_ring[t].tmd1_bits); \
109 }\ 109 } \
110} while (0) 110} while (0)
111#else 111#else
112#define PRINT_RINGS() 112#define PRINT_RINGS()
113#endif 113#endif
114 114
115/* Load the CSR registers. The LANCE has to be STOPped when we do this! */ 115/* Load the CSR registers. The LANCE has to be STOPped when we do this! */
116static void load_csrs (struct lance_private *lp) 116static void load_csrs(struct lance_private *lp)
117{ 117{
118 volatile struct lance_init_block *aib = lp->lance_init_block; 118 volatile struct lance_init_block *aib = lp->lance_init_block;
119 int leptr; 119 int leptr;
120 120
121 leptr = LANCE_ADDR (aib); 121 leptr = LANCE_ADDR(aib);
122 122
123 WRITERAP(lp, LE_CSR1); /* load address of init block */ 123 WRITERAP(lp, LE_CSR1); /* load address of init block */
124 WRITERDP(lp, leptr & 0xFFFF); 124 WRITERDP(lp, leptr & 0xFFFF);
125 WRITERAP(lp, LE_CSR2); 125 WRITERAP(lp, LE_CSR2);
126 WRITERDP(lp, leptr >> 16); 126 WRITERDP(lp, leptr >> 16);
127 WRITERAP(lp, LE_CSR3); 127 WRITERAP(lp, LE_CSR3);
128 WRITERDP(lp, lp->busmaster_regval); /* set byteswap/ALEctrl/byte ctrl */ 128 WRITERDP(lp, lp->busmaster_regval); /* set byteswap/ALEctrl/byte ctrl */
129 129
130 /* Point back to csr0 */ 130 /* Point back to csr0 */
131 WRITERAP(lp, LE_CSR0); 131 WRITERAP(lp, LE_CSR0);
132} 132}
133 133
134/* #define to 0 or 1 appropriately */ 134/* #define to 0 or 1 appropriately */
135#define DEBUG_IRING 0 135#define DEBUG_IRING 0
136/* Set up the Lance Rx and Tx rings and the init block */ 136/* Set up the Lance Rx and Tx rings and the init block */
137static void lance_init_ring (struct net_device *dev) 137static void lance_init_ring(struct net_device *dev)
138{ 138{
139 struct lance_private *lp = netdev_priv(dev); 139 struct lance_private *lp = netdev_priv(dev);
140 volatile struct lance_init_block *ib = lp->init_block; 140 volatile struct lance_init_block *ib = lp->init_block;
141 volatile struct lance_init_block *aib; /* for LANCE_ADDR computations */ 141 volatile struct lance_init_block *aib; /* for LANCE_ADDR computations */
142 int leptr; 142 int leptr;
143 int i; 143 int i;
144 144
145 aib = lp->lance_init_block; 145 aib = lp->lance_init_block;
146 146
147 lp->rx_new = lp->tx_new = 0; 147 lp->rx_new = lp->tx_new = 0;
148 lp->rx_old = lp->tx_old = 0; 148 lp->rx_old = lp->tx_old = 0;
149 149
150 ib->mode = LE_MO_PROM; /* normal, enable Tx & Rx */ 150 ib->mode = LE_MO_PROM; /* normal, enable Tx & Rx */
151 151
152 /* Copy the ethernet address to the lance init block 152 /* Copy the ethernet address to the lance init block
153 * Notice that we do a byteswap if we're big endian. 153 * Notice that we do a byteswap if we're big endian.
154 * [I think this is the right criterion; at least, sunlance, 154 * [I think this is the right criterion; at least, sunlance,
155 * a2065 and atarilance do the byteswap and lance.c (PC) doesn't. 155 * a2065 and atarilance do the byteswap and lance.c (PC) doesn't.
156 * However, the datasheet says that the BSWAP bit doesn't affect 156 * However, the datasheet says that the BSWAP bit doesn't affect
157 * the init block, so surely it should be low byte first for 157 * the init block, so surely it should be low byte first for
158 * everybody? Um.] 158 * everybody? Um.]
159 * We could define the ib->physaddr as three 16bit values and 159 * We could define the ib->physaddr as three 16bit values and
160 * use (addr[1] << 8) | addr[0] & co, but this is more efficient. 160 * use (addr[1] << 8) | addr[0] & co, but this is more efficient.
161 */ 161 */
162#ifdef __BIG_ENDIAN 162#ifdef __BIG_ENDIAN
163 ib->phys_addr [0] = dev->dev_addr [1]; 163 ib->phys_addr[0] = dev->dev_addr[1];
164 ib->phys_addr [1] = dev->dev_addr [0]; 164 ib->phys_addr[1] = dev->dev_addr[0];
165 ib->phys_addr [2] = dev->dev_addr [3]; 165 ib->phys_addr[2] = dev->dev_addr[3];
166 ib->phys_addr [3] = dev->dev_addr [2]; 166 ib->phys_addr[3] = dev->dev_addr[2];
167 ib->phys_addr [4] = dev->dev_addr [5]; 167 ib->phys_addr[4] = dev->dev_addr[5];
168 ib->phys_addr [5] = dev->dev_addr [4]; 168 ib->phys_addr[5] = dev->dev_addr[4];
169#else 169#else
170 for (i=0; i<6; i++) 170 for (i = 0; i < 6; i++)
171 ib->phys_addr[i] = dev->dev_addr[i]; 171 ib->phys_addr[i] = dev->dev_addr[i];
172#endif 172#endif
173 173
174 if (DEBUG_IRING) 174 if (DEBUG_IRING)
175 printk ("TX rings:\n"); 175 printk("TX rings:\n");
176 176
177 lp->tx_full = 0; 177 lp->tx_full = 0;
178 /* Setup the Tx ring entries */ 178 /* Setup the Tx ring entries */
179 for (i = 0; i < (1<<lp->lance_log_tx_bufs); i++) { 179 for (i = 0; i < (1 << lp->lance_log_tx_bufs); i++) {
180 leptr = LANCE_ADDR(&aib->tx_buf[i][0]); 180 leptr = LANCE_ADDR(&aib->tx_buf[i][0]);
181 ib->btx_ring [i].tmd0 = leptr; 181 ib->btx_ring[i].tmd0 = leptr;
182 ib->btx_ring [i].tmd1_hadr = leptr >> 16; 182 ib->btx_ring[i].tmd1_hadr = leptr >> 16;
183 ib->btx_ring [i].tmd1_bits = 0; 183 ib->btx_ring[i].tmd1_bits = 0;
184 ib->btx_ring [i].length = 0xf000; /* The ones required by tmd2 */ 184 ib->btx_ring[i].length = 0xf000; /* The ones required by tmd2 */
185 ib->btx_ring [i].misc = 0; 185 ib->btx_ring[i].misc = 0;
186 if (DEBUG_IRING) 186 if (DEBUG_IRING)
187 printk ("%d: 0x%8.8x\n", i, leptr); 187 printk("%d: 0x%8.8x\n", i, leptr);
188 } 188 }
189 189
190 /* Setup the Rx ring entries */ 190 /* Setup the Rx ring entries */
191 if (DEBUG_IRING) 191 if (DEBUG_IRING)
192 printk ("RX rings:\n"); 192 printk("RX rings:\n");
193 for (i = 0; i < (1<<lp->lance_log_rx_bufs); i++) { 193 for (i = 0; i < (1 << lp->lance_log_rx_bufs); i++) {
194 leptr = LANCE_ADDR(&aib->rx_buf[i][0]); 194 leptr = LANCE_ADDR(&aib->rx_buf[i][0]);
195 195
196 ib->brx_ring [i].rmd0 = leptr; 196 ib->brx_ring[i].rmd0 = leptr;
197 ib->brx_ring [i].rmd1_hadr = leptr >> 16; 197 ib->brx_ring[i].rmd1_hadr = leptr >> 16;
198 ib->brx_ring [i].rmd1_bits = LE_R1_OWN; 198 ib->brx_ring[i].rmd1_bits = LE_R1_OWN;
199 /* 0xf000 == bits that must be one (reserved, presumably) */ 199 /* 0xf000 == bits that must be one (reserved, presumably) */
200 ib->brx_ring [i].length = -RX_BUFF_SIZE | 0xf000; 200 ib->brx_ring[i].length = -RX_BUFF_SIZE | 0xf000;
201 ib->brx_ring [i].mblength = 0; 201 ib->brx_ring[i].mblength = 0;
202 if (DEBUG_IRING) 202 if (DEBUG_IRING)
203 printk ("%d: 0x%8.8x\n", i, leptr); 203 printk("%d: 0x%8.8x\n", i, leptr);
204 } 204 }
205 205
206 /* Setup the initialization block */ 206 /* Setup the initialization block */
207 207
208 /* Setup rx descriptor pointer */ 208 /* Setup rx descriptor pointer */
209 leptr = LANCE_ADDR(&aib->brx_ring); 209 leptr = LANCE_ADDR(&aib->brx_ring);
210 ib->rx_len = (lp->lance_log_rx_bufs << 13) | (leptr >> 16); 210 ib->rx_len = (lp->lance_log_rx_bufs << 13) | (leptr >> 16);
211 ib->rx_ptr = leptr; 211 ib->rx_ptr = leptr;
212 if (DEBUG_IRING) 212 if (DEBUG_IRING)
213 printk ("RX ptr: %8.8x\n", leptr); 213 printk("RX ptr: %8.8x\n", leptr);
214 214
215 /* Setup tx descriptor pointer */ 215 /* Setup tx descriptor pointer */
216 leptr = LANCE_ADDR(&aib->btx_ring); 216 leptr = LANCE_ADDR(&aib->btx_ring);
217 ib->tx_len = (lp->lance_log_tx_bufs << 13) | (leptr >> 16); 217 ib->tx_len = (lp->lance_log_tx_bufs << 13) | (leptr >> 16);
218 ib->tx_ptr = leptr; 218 ib->tx_ptr = leptr;
219 if (DEBUG_IRING) 219 if (DEBUG_IRING)
220 printk ("TX ptr: %8.8x\n", leptr); 220 printk("TX ptr: %8.8x\n", leptr);
221 221
222 /* Clear the multicast filter */ 222 /* Clear the multicast filter */
223 ib->filter [0] = 0; 223 ib->filter[0] = 0;
224 ib->filter [1] = 0; 224 ib->filter[1] = 0;
225 PRINT_RINGS(); 225 PRINT_RINGS();
226} 226}
227 227
228/* LANCE must be STOPped before we do this, too... */ 228/* LANCE must be STOPped before we do this, too... */
229static int init_restart_lance (struct lance_private *lp) 229static int init_restart_lance(struct lance_private *lp)
230{ 230{
231 int i; 231 int i;
232 232
233 WRITERAP(lp, LE_CSR0); 233 WRITERAP(lp, LE_CSR0);
234 WRITERDP(lp, LE_C0_INIT); 234 WRITERDP(lp, LE_C0_INIT);
235 235
236 /* Need a hook here for sunlance ledma stuff */ 236 /* Need a hook here for sunlance ledma stuff */
237 237
238 /* Wait for the lance to complete initialization */ 238 /* Wait for the lance to complete initialization */
239 for (i = 0; (i < 100) && !(READRDP(lp) & (LE_C0_ERR | LE_C0_IDON)); i++) 239 for (i = 0; (i < 100) && !(READRDP(lp) & (LE_C0_ERR | LE_C0_IDON)); i++)
240 barrier(); 240 barrier();
241 if ((i == 100) || (READRDP(lp) & LE_C0_ERR)) { 241 if ((i == 100) || (READRDP(lp) & LE_C0_ERR)) {
242 printk ("LANCE unopened after %d ticks, csr0=%4.4x.\n", i, READRDP(lp)); 242 printk("LANCE unopened after %d ticks, csr0=%4.4x.\n", i, READRDP(lp));
243 return -1; 243 return -1;
244 } 244 }
245 245
246 /* Clear IDON by writing a "1", enable interrupts and start lance */ 246 /* Clear IDON by writing a "1", enable interrupts and start lance */
247 WRITERDP(lp, LE_C0_IDON); 247 WRITERDP(lp, LE_C0_IDON);
248 WRITERDP(lp, LE_C0_INEA | LE_C0_STRT); 248 WRITERDP(lp, LE_C0_INEA | LE_C0_STRT);
249 249
250 return 0; 250 return 0;
251} 251}
252 252
253static int lance_reset (struct net_device *dev) 253static int lance_reset(struct net_device *dev)
254{ 254{
255 struct lance_private *lp = netdev_priv(dev); 255 struct lance_private *lp = netdev_priv(dev);
256 int status; 256 int status;
257 257
258 /* Stop the lance */ 258 /* Stop the lance */
259 WRITERAP(lp, LE_CSR0); 259 WRITERAP(lp, LE_CSR0);
260 WRITERDP(lp, LE_C0_STOP); 260 WRITERDP(lp, LE_C0_STOP);
261 261
262 load_csrs (lp); 262 load_csrs(lp);
263 lance_init_ring (dev); 263 lance_init_ring(dev);
264 dev->trans_start = jiffies; /* prevent tx timeout */ 264 dev->trans_start = jiffies; /* prevent tx timeout */
265 status = init_restart_lance (lp); 265 status = init_restart_lance(lp);
266#ifdef DEBUG_DRIVER 266#ifdef DEBUG_DRIVER
267 printk ("Lance restart=%d\n", status); 267 printk("Lance restart=%d\n", status);
268#endif 268#endif
269 return status; 269 return status;
270} 270}
271 271
272static int lance_rx (struct net_device *dev) 272static int lance_rx(struct net_device *dev)
273{ 273{
274 struct lance_private *lp = netdev_priv(dev); 274 struct lance_private *lp = netdev_priv(dev);
275 volatile struct lance_init_block *ib = lp->init_block; 275 volatile struct lance_init_block *ib = lp->init_block;
276 volatile struct lance_rx_desc *rd; 276 volatile struct lance_rx_desc *rd;
277 unsigned char bits; 277 unsigned char bits;
278#ifdef TEST_HITS 278#ifdef TEST_HITS
279 int i; 279 int i;
280#endif 280#endif
281 281
282#ifdef TEST_HITS 282#ifdef TEST_HITS
283 printk ("["); 283 printk("[");
284 for (i = 0; i < RX_RING_SIZE; i++) { 284 for (i = 0; i < RX_RING_SIZE; i++) {
285 if (i == lp->rx_new) 285 if (i == lp->rx_new)
286 printk ("%s", 286 printk("%s",
287 ib->brx_ring [i].rmd1_bits & LE_R1_OWN ? "_" : "X"); 287 ib->brx_ring[i].rmd1_bits & LE_R1_OWN ? "_" : "X");
288 else 288 else
289 printk ("%s", 289 printk("%s",
290 ib->brx_ring [i].rmd1_bits & LE_R1_OWN ? "." : "1"); 290 ib->brx_ring[i].rmd1_bits & LE_R1_OWN ? "." : "1");
291 } 291 }
292 printk ("]"); 292 printk("]");
293#endif 293#endif
294#ifdef CONFIG_HP300 294#ifdef CONFIG_HP300
295 blinken_leds(0x40, 0); 295 blinken_leds(0x40, 0);
296#endif 296#endif
297 WRITERDP(lp, LE_C0_RINT | LE_C0_INEA); /* ack Rx int, reenable ints */ 297 WRITERDP(lp, LE_C0_RINT | LE_C0_INEA); /* ack Rx int, reenable ints */
298 for (rd = &ib->brx_ring [lp->rx_new]; /* For each Rx ring we own... */ 298 for (rd = &ib->brx_ring[lp->rx_new]; /* For each Rx ring we own... */
299 !((bits = rd->rmd1_bits) & LE_R1_OWN); 299 !((bits = rd->rmd1_bits) & LE_R1_OWN);
300 rd = &ib->brx_ring [lp->rx_new]) { 300 rd = &ib->brx_ring[lp->rx_new]) {
301 301
302 /* We got an incomplete frame? */ 302 /* We got an incomplete frame? */
303 if ((bits & LE_R1_POK) != LE_R1_POK) { 303 if ((bits & LE_R1_POK) != LE_R1_POK) {
304 dev->stats.rx_over_errors++; 304 dev->stats.rx_over_errors++;
305 dev->stats.rx_errors++; 305 dev->stats.rx_errors++;
306 continue; 306 continue;
307 } else if (bits & LE_R1_ERR) { 307 } else if (bits & LE_R1_ERR) {
308 /* Count only the end frame as a rx error, 308 /* Count only the end frame as a rx error,
309 * not the beginning 309 * not the beginning
310 */ 310 */
311 if (bits & LE_R1_BUF) dev->stats.rx_fifo_errors++; 311 if (bits & LE_R1_BUF)
312 if (bits & LE_R1_CRC) dev->stats.rx_crc_errors++; 312 dev->stats.rx_fifo_errors++;
313 if (bits & LE_R1_OFL) dev->stats.rx_over_errors++; 313 if (bits & LE_R1_CRC)
314 if (bits & LE_R1_FRA) dev->stats.rx_frame_errors++; 314 dev->stats.rx_crc_errors++;
315 if (bits & LE_R1_EOP) dev->stats.rx_errors++; 315 if (bits & LE_R1_OFL)
316 } else { 316 dev->stats.rx_over_errors++;
317 if (bits & LE_R1_FRA)
318 dev->stats.rx_frame_errors++;
319 if (bits & LE_R1_EOP)
320 dev->stats.rx_errors++;
321 } else {
317 int len = (rd->mblength & 0xfff) - 4; 322 int len = (rd->mblength & 0xfff) - 4;
318 struct sk_buff *skb = netdev_alloc_skb(dev, len + 2); 323 struct sk_buff *skb = netdev_alloc_skb(dev, len + 2);
319 324
320 if (!skb) { 325 if (!skb) {
321 dev->stats.rx_dropped++; 326 dev->stats.rx_dropped++;
322 rd->mblength = 0; 327 rd->mblength = 0;
323 rd->rmd1_bits = LE_R1_OWN; 328 rd->rmd1_bits = LE_R1_OWN;
324 lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask; 329 lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
325 return 0; 330 return 0;
326 } 331 }
327 332
328 skb_reserve (skb, 2); /* 16 byte align */ 333 skb_reserve(skb, 2); /* 16 byte align */
329 skb_put (skb, len); /* make room */ 334 skb_put(skb, len); /* make room */
330 skb_copy_to_linear_data(skb, 335 skb_copy_to_linear_data(skb,
331 (unsigned char *)&(ib->rx_buf [lp->rx_new][0]), 336 (unsigned char *)&(ib->rx_buf[lp->rx_new][0]),
332 len); 337 len);
333 skb->protocol = eth_type_trans (skb, dev); 338 skb->protocol = eth_type_trans(skb, dev);
334 netif_rx (skb); 339 netif_rx(skb);
335 dev->stats.rx_packets++; 340 dev->stats.rx_packets++;
336 dev->stats.rx_bytes += len; 341 dev->stats.rx_bytes += len;
337 } 342 }
338 343
339 /* Return the packet to the pool */ 344 /* Return the packet to the pool */
340 rd->mblength = 0; 345 rd->mblength = 0;
341 rd->rmd1_bits = LE_R1_OWN; 346 rd->rmd1_bits = LE_R1_OWN;
342 lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask; 347 lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
343 } 348 }
344 return 0; 349 return 0;
345} 350}
346 351
347static int lance_tx (struct net_device *dev) 352static int lance_tx(struct net_device *dev)
348{ 353{
349 struct lance_private *lp = netdev_priv(dev); 354 struct lance_private *lp = netdev_priv(dev);
350 volatile struct lance_init_block *ib = lp->init_block; 355 volatile struct lance_init_block *ib = lp->init_block;
351 volatile struct lance_tx_desc *td; 356 volatile struct lance_tx_desc *td;
352 int i, j; 357 int i, j;
353 int status; 358 int status;
354 359
355#ifdef CONFIG_HP300 360#ifdef CONFIG_HP300
356 blinken_leds(0x80, 0); 361 blinken_leds(0x80, 0);
357#endif 362#endif
358 /* csr0 is 2f3 */ 363 /* csr0 is 2f3 */
359 WRITERDP(lp, LE_C0_TINT | LE_C0_INEA); 364 WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
360 /* csr0 is 73 */ 365 /* csr0 is 73 */
361 366
362 j = lp->tx_old; 367 j = lp->tx_old;
363 for (i = j; i != lp->tx_new; i = j) { 368 for (i = j; i != lp->tx_new; i = j) {
364 td = &ib->btx_ring [i]; 369 td = &ib->btx_ring[i];
365 370
366 /* If we hit a packet not owned by us, stop */ 371 /* If we hit a packet not owned by us, stop */
367 if (td->tmd1_bits & LE_T1_OWN) 372 if (td->tmd1_bits & LE_T1_OWN)
368 break; 373 break;
369 374
370 if (td->tmd1_bits & LE_T1_ERR) { 375 if (td->tmd1_bits & LE_T1_ERR) {
371 status = td->misc; 376 status = td->misc;
372 377
373 dev->stats.tx_errors++; 378 dev->stats.tx_errors++;
374 if (status & LE_T3_RTY) dev->stats.tx_aborted_errors++; 379 if (status & LE_T3_RTY)
375 if (status & LE_T3_LCOL) dev->stats.tx_window_errors++; 380 dev->stats.tx_aborted_errors++;
376 381 if (status & LE_T3_LCOL)
377 if (status & LE_T3_CLOS) { 382 dev->stats.tx_window_errors++;
378 dev->stats.tx_carrier_errors++; 383
379 if (lp->auto_select) { 384 if (status & LE_T3_CLOS) {
380 lp->tpe = 1 - lp->tpe; 385 dev->stats.tx_carrier_errors++;
381 printk("%s: Carrier Lost, trying %s\n", 386 if (lp->auto_select) {
382 dev->name, lp->tpe?"TPE":"AUI"); 387 lp->tpe = 1 - lp->tpe;
383 /* Stop the lance */ 388 printk("%s: Carrier Lost, trying %s\n",
384 WRITERAP(lp, LE_CSR0); 389 dev->name,
385 WRITERDP(lp, LE_C0_STOP); 390 lp->tpe ? "TPE" : "AUI");
386 lance_init_ring (dev); 391 /* Stop the lance */
387 load_csrs (lp); 392 WRITERAP(lp, LE_CSR0);
388 init_restart_lance (lp); 393 WRITERDP(lp, LE_C0_STOP);
389 return 0; 394 lance_init_ring(dev);
390 } 395 load_csrs(lp);
391 } 396 init_restart_lance(lp);
392 397 return 0;
393 /* buffer errors and underflows turn off the transmitter */ 398 }
394 /* Restart the adapter */ 399 }
395 if (status & (LE_T3_BUF|LE_T3_UFL)) { 400
396 dev->stats.tx_fifo_errors++; 401 /* buffer errors and underflows turn off the transmitter */
397 402 /* Restart the adapter */
398 printk ("%s: Tx: ERR_BUF|ERR_UFL, restarting\n", 403 if (status & (LE_T3_BUF|LE_T3_UFL)) {
399 dev->name); 404 dev->stats.tx_fifo_errors++;
400 /* Stop the lance */ 405
401 WRITERAP(lp, LE_CSR0); 406 printk("%s: Tx: ERR_BUF|ERR_UFL, restarting\n",
402 WRITERDP(lp, LE_C0_STOP); 407 dev->name);
403 lance_init_ring (dev); 408 /* Stop the lance */
404 load_csrs (lp); 409 WRITERAP(lp, LE_CSR0);
405 init_restart_lance (lp); 410 WRITERDP(lp, LE_C0_STOP);
406 return 0; 411 lance_init_ring(dev);
407 } 412 load_csrs(lp);
408 } else if ((td->tmd1_bits & LE_T1_POK) == LE_T1_POK) { 413 init_restart_lance(lp);
409 /* 414 return 0;
410 * So we don't count the packet more than once. 415 }
411 */ 416 } else if ((td->tmd1_bits & LE_T1_POK) == LE_T1_POK) {
412 td->tmd1_bits &= ~(LE_T1_POK); 417 /*
413 418 * So we don't count the packet more than once.
414 /* One collision before packet was sent. */ 419 */
415 if (td->tmd1_bits & LE_T1_EONE) 420 td->tmd1_bits &= ~(LE_T1_POK);
416 dev->stats.collisions++; 421
417 422 /* One collision before packet was sent. */
418 /* More than one collision, be optimistic. */ 423 if (td->tmd1_bits & LE_T1_EONE)
419 if (td->tmd1_bits & LE_T1_EMORE) 424 dev->stats.collisions++;
420 dev->stats.collisions += 2; 425
421 426 /* More than one collision, be optimistic. */
422 dev->stats.tx_packets++; 427 if (td->tmd1_bits & LE_T1_EMORE)
423 } 428 dev->stats.collisions += 2;
424 429
425 j = (j + 1) & lp->tx_ring_mod_mask; 430 dev->stats.tx_packets++;
426 } 431 }
427 lp->tx_old = j; 432
428 WRITERDP(lp, LE_C0_TINT | LE_C0_INEA); 433 j = (j + 1) & lp->tx_ring_mod_mask;
429 return 0; 434 }
435 lp->tx_old = j;
436 WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
437 return 0;
430} 438}
431 439
432static irqreturn_t 440static irqreturn_t
433lance_interrupt (int irq, void *dev_id) 441lance_interrupt(int irq, void *dev_id)
434{ 442{
435 struct net_device *dev = (struct net_device *)dev_id; 443 struct net_device *dev = (struct net_device *)dev_id;
436 struct lance_private *lp = netdev_priv(dev); 444 struct lance_private *lp = netdev_priv(dev);
437 int csr0; 445 int csr0;
438 446
439 spin_lock (&lp->devlock); 447 spin_lock(&lp->devlock);
440 448
441 WRITERAP(lp, LE_CSR0); /* LANCE Controller Status */ 449 WRITERAP(lp, LE_CSR0); /* LANCE Controller Status */
442 csr0 = READRDP(lp); 450 csr0 = READRDP(lp);
443 451
444 PRINT_RINGS(); 452 PRINT_RINGS();
445 453
446 if (!(csr0 & LE_C0_INTR)) { /* Check if any interrupt has */ 454 if (!(csr0 & LE_C0_INTR)) { /* Check if any interrupt has */
447 spin_unlock (&lp->devlock); 455 spin_unlock(&lp->devlock);
448 return IRQ_NONE; /* been generated by the Lance. */ 456 return IRQ_NONE; /* been generated by the Lance. */
449 } 457 }
450 458
451 /* Acknowledge all the interrupt sources ASAP */ 459 /* Acknowledge all the interrupt sources ASAP */
452 WRITERDP(lp, csr0 & ~(LE_C0_INEA|LE_C0_TDMD|LE_C0_STOP|LE_C0_STRT|LE_C0_INIT)); 460 WRITERDP(lp, csr0 & ~(LE_C0_INEA|LE_C0_TDMD|LE_C0_STOP|LE_C0_STRT|LE_C0_INIT));
453 461
454 if ((csr0 & LE_C0_ERR)) { 462 if ((csr0 & LE_C0_ERR)) {
455 /* Clear the error condition */ 463 /* Clear the error condition */
456 WRITERDP(lp, LE_C0_BABL|LE_C0_ERR|LE_C0_MISS|LE_C0_INEA); 464 WRITERDP(lp, LE_C0_BABL|LE_C0_ERR|LE_C0_MISS|LE_C0_INEA);
457 } 465 }
458 466
459 if (csr0 & LE_C0_RINT) 467 if (csr0 & LE_C0_RINT)
460 lance_rx (dev); 468 lance_rx(dev);
461 469
462 if (csr0 & LE_C0_TINT) 470 if (csr0 & LE_C0_TINT)
463 lance_tx (dev); 471 lance_tx(dev);
464 472
465 /* Log misc errors. */ 473 /* Log misc errors. */
466 if (csr0 & LE_C0_BABL) 474 if (csr0 & LE_C0_BABL)
467 dev->stats.tx_errors++; /* Tx babble. */ 475 dev->stats.tx_errors++; /* Tx babble. */
468 if (csr0 & LE_C0_MISS) 476 if (csr0 & LE_C0_MISS)
469 dev->stats.rx_errors++; /* Missed a Rx frame. */ 477 dev->stats.rx_errors++; /* Missed a Rx frame. */
470 if (csr0 & LE_C0_MERR) { 478 if (csr0 & LE_C0_MERR) {
471 printk("%s: Bus master arbitration failure, status %4.4x.\n", 479 printk("%s: Bus master arbitration failure, status %4.4x.\n",
472 dev->name, csr0); 480 dev->name, csr0);
473 /* Restart the chip. */ 481 /* Restart the chip. */
474 WRITERDP(lp, LE_C0_STRT); 482 WRITERDP(lp, LE_C0_STRT);
475 } 483 }
476 484
477 if (lp->tx_full && netif_queue_stopped(dev) && (TX_BUFFS_AVAIL >= 0)) { 485 if (lp->tx_full && netif_queue_stopped(dev) && (TX_BUFFS_AVAIL >= 0)) {
478 lp->tx_full = 0; 486 lp->tx_full = 0;
479 netif_wake_queue (dev); 487 netif_wake_queue(dev);
480 } 488 }
481 489
482 WRITERAP(lp, LE_CSR0); 490 WRITERAP(lp, LE_CSR0);
483 WRITERDP(lp, LE_C0_BABL|LE_C0_CERR|LE_C0_MISS|LE_C0_MERR|LE_C0_IDON|LE_C0_INEA); 491 WRITERDP(lp, LE_C0_BABL|LE_C0_CERR|LE_C0_MISS|LE_C0_MERR|LE_C0_IDON|LE_C0_INEA);
484 492
485 spin_unlock (&lp->devlock); 493 spin_unlock(&lp->devlock);
486 return IRQ_HANDLED; 494 return IRQ_HANDLED;
487} 495}
488 496
489int lance_open (struct net_device *dev) 497int lance_open(struct net_device *dev)
490{ 498{
491 struct lance_private *lp = netdev_priv(dev); 499 struct lance_private *lp = netdev_priv(dev);
492 int res; 500 int res;
493 501
494 /* Install the Interrupt handler. Or we could shunt this out to specific drivers? */ 502 /* Install the Interrupt handler. Or we could shunt this out to specific drivers? */
495 if (request_irq(lp->irq, lance_interrupt, IRQF_SHARED, lp->name, dev)) 503 if (request_irq(lp->irq, lance_interrupt, IRQF_SHARED, lp->name, dev))
496 return -EAGAIN; 504 return -EAGAIN;
497 505
498 res = lance_reset(dev); 506 res = lance_reset(dev);
499 spin_lock_init(&lp->devlock); 507 spin_lock_init(&lp->devlock);
500 netif_start_queue (dev); 508 netif_start_queue(dev);
501 509
502 return res; 510 return res;
503} 511}
504EXPORT_SYMBOL_GPL(lance_open); 512EXPORT_SYMBOL_GPL(lance_open);
505 513
506int lance_close (struct net_device *dev) 514int lance_close(struct net_device *dev)
507{ 515{
508 struct lance_private *lp = netdev_priv(dev); 516 struct lance_private *lp = netdev_priv(dev);
509 517
510 netif_stop_queue (dev); 518 netif_stop_queue(dev);
511 519
512 /* Stop the LANCE */ 520 /* Stop the LANCE */
513 WRITERAP(lp, LE_CSR0); 521 WRITERAP(lp, LE_CSR0);
514 WRITERDP(lp, LE_C0_STOP); 522 WRITERDP(lp, LE_C0_STOP);
515 523
516 free_irq(lp->irq, dev); 524 free_irq(lp->irq, dev);
517 525
518 return 0; 526 return 0;
519} 527}
520EXPORT_SYMBOL_GPL(lance_close); 528EXPORT_SYMBOL_GPL(lance_close);
521 529
@@ -524,122 +532,122 @@ void lance_tx_timeout(struct net_device *dev)
524 printk("lance_tx_timeout\n"); 532 printk("lance_tx_timeout\n");
525 lance_reset(dev); 533 lance_reset(dev);
526 dev->trans_start = jiffies; /* prevent tx timeout */ 534 dev->trans_start = jiffies; /* prevent tx timeout */
527 netif_wake_queue (dev); 535 netif_wake_queue(dev);
528} 536}
529EXPORT_SYMBOL_GPL(lance_tx_timeout); 537EXPORT_SYMBOL_GPL(lance_tx_timeout);
530 538
531int lance_start_xmit (struct sk_buff *skb, struct net_device *dev) 539int lance_start_xmit(struct sk_buff *skb, struct net_device *dev)
532{ 540{
533 struct lance_private *lp = netdev_priv(dev); 541 struct lance_private *lp = netdev_priv(dev);
534 volatile struct lance_init_block *ib = lp->init_block; 542 volatile struct lance_init_block *ib = lp->init_block;
535 int entry, skblen, len; 543 int entry, skblen, len;
536 static int outs; 544 static int outs;
537 unsigned long flags; 545 unsigned long flags;
538 546
539 if (!TX_BUFFS_AVAIL) 547 if (!TX_BUFFS_AVAIL)
540 return NETDEV_TX_LOCKED; 548 return NETDEV_TX_LOCKED;
541 549
542 netif_stop_queue (dev); 550 netif_stop_queue(dev);
543 551
544 skblen = skb->len; 552 skblen = skb->len;
545 553
546#ifdef DEBUG_DRIVER 554#ifdef DEBUG_DRIVER
547 /* dump the packet */ 555 /* dump the packet */
548 { 556 {
549 int i; 557 int i;
550 558
551 for (i = 0; i < 64; i++) { 559 for (i = 0; i < 64; i++) {
552 if ((i % 16) == 0) 560 if ((i % 16) == 0)
553 printk ("\n"); 561 printk("\n");
554 printk ("%2.2x ", skb->data [i]); 562 printk("%2.2x ", skb->data[i]);
555 } 563 }
556 } 564 }
557#endif 565#endif
558 len = (skblen <= ETH_ZLEN) ? ETH_ZLEN : skblen; 566 len = (skblen <= ETH_ZLEN) ? ETH_ZLEN : skblen;
559 entry = lp->tx_new & lp->tx_ring_mod_mask; 567 entry = lp->tx_new & lp->tx_ring_mod_mask;
560 ib->btx_ring [entry].length = (-len) | 0xf000; 568 ib->btx_ring[entry].length = (-len) | 0xf000;
561 ib->btx_ring [entry].misc = 0; 569 ib->btx_ring[entry].misc = 0;
562 570
563 if (skb->len < ETH_ZLEN) 571 if (skb->len < ETH_ZLEN)
564 memset((void *)&ib->tx_buf[entry][0], 0, ETH_ZLEN); 572 memset((void *)&ib->tx_buf[entry][0], 0, ETH_ZLEN);
565 skb_copy_from_linear_data(skb, (void *)&ib->tx_buf[entry][0], skblen); 573 skb_copy_from_linear_data(skb, (void *)&ib->tx_buf[entry][0], skblen);
566 574
567 /* Now, give the packet to the lance */ 575 /* Now, give the packet to the lance */
568 ib->btx_ring [entry].tmd1_bits = (LE_T1_POK|LE_T1_OWN); 576 ib->btx_ring[entry].tmd1_bits = (LE_T1_POK|LE_T1_OWN);
569 lp->tx_new = (lp->tx_new+1) & lp->tx_ring_mod_mask; 577 lp->tx_new = (lp->tx_new + 1) & lp->tx_ring_mod_mask;
570 578
571 outs++; 579 outs++;
572 /* Kick the lance: transmit now */ 580 /* Kick the lance: transmit now */
573 WRITERDP(lp, LE_C0_INEA | LE_C0_TDMD); 581 WRITERDP(lp, LE_C0_INEA | LE_C0_TDMD);
574 dev_kfree_skb (skb); 582 dev_kfree_skb(skb);
575 583
576 spin_lock_irqsave (&lp->devlock, flags); 584 spin_lock_irqsave(&lp->devlock, flags);
577 if (TX_BUFFS_AVAIL) 585 if (TX_BUFFS_AVAIL)
578 netif_start_queue (dev); 586 netif_start_queue(dev);
579 else 587 else
580 lp->tx_full = 1; 588 lp->tx_full = 1;
581 spin_unlock_irqrestore (&lp->devlock, flags); 589 spin_unlock_irqrestore(&lp->devlock, flags);
582 590
583 return NETDEV_TX_OK; 591 return NETDEV_TX_OK;
584} 592}
585EXPORT_SYMBOL_GPL(lance_start_xmit); 593EXPORT_SYMBOL_GPL(lance_start_xmit);
586 594
587/* taken from the depca driver via a2065.c */ 595/* taken from the depca driver via a2065.c */
588static void lance_load_multicast (struct net_device *dev) 596static void lance_load_multicast(struct net_device *dev)
589{ 597{
590 struct lance_private *lp = netdev_priv(dev); 598 struct lance_private *lp = netdev_priv(dev);
591 volatile struct lance_init_block *ib = lp->init_block; 599 volatile struct lance_init_block *ib = lp->init_block;
592 volatile u16 *mcast_table = (u16 *)&ib->filter; 600 volatile u16 *mcast_table = (u16 *)&ib->filter;
593 struct netdev_hw_addr *ha; 601 struct netdev_hw_addr *ha;
594 u32 crc; 602 u32 crc;
595 603
596 /* set all multicast bits */ 604 /* set all multicast bits */
597 if (dev->flags & IFF_ALLMULTI){ 605 if (dev->flags & IFF_ALLMULTI) {
598 ib->filter [0] = 0xffffffff; 606 ib->filter[0] = 0xffffffff;
599 ib->filter [1] = 0xffffffff; 607 ib->filter[1] = 0xffffffff;
600 return; 608 return;
601 } 609 }
602 /* clear the multicast filter */ 610 /* clear the multicast filter */
603 ib->filter [0] = 0; 611 ib->filter[0] = 0;
604 ib->filter [1] = 0; 612 ib->filter[1] = 0;
605 613
606 /* Add addresses */ 614 /* Add addresses */
607 netdev_for_each_mc_addr(ha, dev) { 615 netdev_for_each_mc_addr(ha, dev) {
608 crc = ether_crc_le(6, ha->addr); 616 crc = ether_crc_le(6, ha->addr);
609 crc = crc >> 26; 617 crc = crc >> 26;
610 mcast_table [crc >> 4] |= 1 << (crc & 0xf); 618 mcast_table[crc >> 4] |= 1 << (crc & 0xf);
611 } 619 }
612} 620}
613 621
614 622
615void lance_set_multicast (struct net_device *dev) 623void lance_set_multicast(struct net_device *dev)
616{ 624{
617 struct lance_private *lp = netdev_priv(dev); 625 struct lance_private *lp = netdev_priv(dev);
618 volatile struct lance_init_block *ib = lp->init_block; 626 volatile struct lance_init_block *ib = lp->init_block;
619 int stopped; 627 int stopped;
620 628
621 stopped = netif_queue_stopped(dev); 629 stopped = netif_queue_stopped(dev);
622 if (!stopped) 630 if (!stopped)
623 netif_stop_queue (dev); 631 netif_stop_queue(dev);
624
625 while (lp->tx_old != lp->tx_new)
626 schedule();
627 632
628 WRITERAP(lp, LE_CSR0); 633 while (lp->tx_old != lp->tx_new)
629 WRITERDP(lp, LE_C0_STOP); 634 schedule();
630 lance_init_ring (dev);
631 635
632 if (dev->flags & IFF_PROMISC) { 636 WRITERAP(lp, LE_CSR0);
633 ib->mode |= LE_MO_PROM; 637 WRITERDP(lp, LE_C0_STOP);
634 } else { 638 lance_init_ring(dev);
635 ib->mode &= ~LE_MO_PROM; 639
636 lance_load_multicast (dev); 640 if (dev->flags & IFF_PROMISC) {
637 } 641 ib->mode |= LE_MO_PROM;
638 load_csrs (lp); 642 } else {
639 init_restart_lance (lp); 643 ib->mode &= ~LE_MO_PROM;
644 lance_load_multicast(dev);
645 }
646 load_csrs(lp);
647 init_restart_lance(lp);
640 648
641 if (!stopped) 649 if (!stopped)
642 netif_start_queue (dev); 650 netif_start_queue(dev);
643} 651}
644EXPORT_SYMBOL_GPL(lance_set_multicast); 652EXPORT_SYMBOL_GPL(lance_set_multicast);
645 653
@@ -648,10 +656,10 @@ void lance_poll(struct net_device *dev)
648{ 656{
649 struct lance_private *lp = netdev_priv(dev); 657 struct lance_private *lp = netdev_priv(dev);
650 658
651 spin_lock (&lp->devlock); 659 spin_lock(&lp->devlock);
652 WRITERAP(lp, LE_CSR0); 660 WRITERAP(lp, LE_CSR0);
653 WRITERDP(lp, LE_C0_STRT); 661 WRITERDP(lp, LE_C0_STRT);
654 spin_unlock (&lp->devlock); 662 spin_unlock(&lp->devlock);
655 lance_interrupt(dev->irq, dev); 663 lance_interrupt(dev->irq, dev);
656} 664}
657#endif 665#endif
diff --git a/drivers/net/ethernet/amd/7990.h b/drivers/net/ethernet/amd/7990.h
index ae33a99bf476..6cf566c3d249 100644
--- a/drivers/net/ethernet/amd/7990.h
+++ b/drivers/net/ethernet/amd/7990.h
@@ -35,33 +35,32 @@
35#define LANCE_LOG_RX_BUFFERS 3 35#define LANCE_LOG_RX_BUFFERS 3
36#endif 36#endif
37 37
38#define TX_RING_SIZE (1<<LANCE_LOG_TX_BUFFERS) 38#define TX_RING_SIZE (1 << LANCE_LOG_TX_BUFFERS)
39#define RX_RING_SIZE (1<<LANCE_LOG_RX_BUFFERS) 39#define RX_RING_SIZE (1 << LANCE_LOG_RX_BUFFERS)
40#define TX_RING_MOD_MASK (TX_RING_SIZE - 1) 40#define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
41#define RX_RING_MOD_MASK (RX_RING_SIZE - 1) 41#define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
42#define TX_RING_LEN_BITS ((LANCE_LOG_TX_BUFFERS) << 29) 42#define TX_RING_LEN_BITS ((LANCE_LOG_TX_BUFFERS) << 29)
43#define RX_RING_LEN_BITS ((LANCE_LOG_RX_BUFFERS) << 29) 43#define RX_RING_LEN_BITS ((LANCE_LOG_RX_BUFFERS) << 29)
44#define PKT_BUFF_SIZE (1544) 44#define PKT_BUFF_SIZE (1544)
45#define RX_BUFF_SIZE PKT_BUFF_SIZE 45#define RX_BUFF_SIZE PKT_BUFF_SIZE
46#define TX_BUFF_SIZE PKT_BUFF_SIZE 46#define TX_BUFF_SIZE PKT_BUFF_SIZE
47 47
48/* Each receive buffer is described by a receive message descriptor (RMD) */ 48/* Each receive buffer is described by a receive message descriptor (RMD) */
49struct lance_rx_desc { 49struct lance_rx_desc {
50 volatile unsigned short rmd0; /* low address of packet */ 50 volatile unsigned short rmd0; /* low address of packet */
51 volatile unsigned char rmd1_bits; /* descriptor bits */ 51 volatile unsigned char rmd1_bits; /* descriptor bits */
52 volatile unsigned char rmd1_hadr; /* high address of packet */ 52 volatile unsigned char rmd1_hadr; /* high address of packet */
53 volatile short length; /* This length is 2s complement (negative)! 53 volatile short length; /* This length is 2s complement (negative)!
54 * Buffer length 54 * Buffer length */
55 */ 55 volatile unsigned short mblength; /* Actual number of bytes received */
56 volatile unsigned short mblength; /* Actual number of bytes received */
57}; 56};
58 57
59/* Ditto for TMD: */ 58/* Ditto for TMD: */
60struct lance_tx_desc { 59struct lance_tx_desc {
61 volatile unsigned short tmd0; /* low address of packet */ 60 volatile unsigned short tmd0; /* low address of packet */
62 volatile unsigned char tmd1_bits; /* descriptor bits */ 61 volatile unsigned char tmd1_bits; /* descriptor bits */
63 volatile unsigned char tmd1_hadr; /* high address of packet */ 62 volatile unsigned char tmd1_hadr; /* high address of packet */
64 volatile short length; /* Length is 2s complement (negative)! */ 63 volatile short length; /* Length is 2s complement (negative)! */
65 volatile unsigned short misc; 64 volatile unsigned short misc;
66}; 65};
67 66
@@ -71,181 +70,178 @@ struct lance_tx_desc {
71 * init block,the Tx and Rx rings and the buffers together in memory: 70 * init block,the Tx and Rx rings and the buffers together in memory:
72 */ 71 */
73struct lance_init_block { 72struct lance_init_block {
74 volatile unsigned short mode; /* Pre-set mode (reg. 15) */ 73 volatile unsigned short mode; /* Pre-set mode (reg. 15) */
75 volatile unsigned char phys_addr[6]; /* Physical ethernet address */ 74 volatile unsigned char phys_addr[6]; /* Physical ethernet address */
76 volatile unsigned filter[2]; /* Multicast filter (64 bits) */ 75 volatile unsigned filter[2]; /* Multicast filter (64 bits) */
77 76
78 /* Receive and transmit ring base, along with extra bits. */ 77 /* Receive and transmit ring base, along with extra bits. */
79 volatile unsigned short rx_ptr; /* receive descriptor addr */ 78 volatile unsigned short rx_ptr; /* receive descriptor addr */
80 volatile unsigned short rx_len; /* receive len and high addr */ 79 volatile unsigned short rx_len; /* receive len and high addr */
81 volatile unsigned short tx_ptr; /* transmit descriptor addr */ 80 volatile unsigned short tx_ptr; /* transmit descriptor addr */
82 volatile unsigned short tx_len; /* transmit len and high addr */ 81 volatile unsigned short tx_len; /* transmit len and high addr */
83 82
84 /* The Tx and Rx ring entries must be aligned on 8-byte boundaries. 83 /* The Tx and Rx ring entries must be aligned on 8-byte boundaries.
85 * This will be true if this whole struct is 8-byte aligned. 84 * This will be true if this whole struct is 8-byte aligned.
86 */ 85 */
87 volatile struct lance_tx_desc btx_ring[TX_RING_SIZE]; 86 volatile struct lance_tx_desc btx_ring[TX_RING_SIZE];
88 volatile struct lance_rx_desc brx_ring[RX_RING_SIZE]; 87 volatile struct lance_rx_desc brx_ring[RX_RING_SIZE];
89 88
90 volatile char tx_buf [TX_RING_SIZE][TX_BUFF_SIZE]; 89 volatile char tx_buf[TX_RING_SIZE][TX_BUFF_SIZE];
91 volatile char rx_buf [RX_RING_SIZE][RX_BUFF_SIZE]; 90 volatile char rx_buf[RX_RING_SIZE][RX_BUFF_SIZE];
92 /* we use this just to make the struct big enough that we can move its startaddr 91 /* we use this just to make the struct big enough that we can move its startaddr
93 * in order to force alignment to an eight byte boundary. 92 * in order to force alignment to an eight byte boundary.
94 */ 93 */
95}; 94};
96 95
97/* This is where we keep all the stuff the driver needs to know about. 96/* This is where we keep all the stuff the driver needs to know about.
98 * I'm definitely unhappy about the mechanism for allowing specific 97 * I'm definitely unhappy about the mechanism for allowing specific
99 * drivers to add things... 98 * drivers to add things...
100 */ 99 */
101struct lance_private 100struct lance_private {
102{ 101 char *name;
103 char *name;
104 unsigned long base; 102 unsigned long base;
105 volatile struct lance_init_block *init_block; /* CPU address of RAM */ 103 volatile struct lance_init_block *init_block; /* CPU address of RAM */
106 volatile struct lance_init_block *lance_init_block; /* LANCE address of RAM */ 104 volatile struct lance_init_block *lance_init_block; /* LANCE address of RAM */
107 105
108 int rx_new, tx_new; 106 int rx_new, tx_new;
109 int rx_old, tx_old; 107 int rx_old, tx_old;
110 108
111 int lance_log_rx_bufs, lance_log_tx_bufs; 109 int lance_log_rx_bufs, lance_log_tx_bufs;
112 int rx_ring_mod_mask, tx_ring_mod_mask; 110 int rx_ring_mod_mask, tx_ring_mod_mask;
113 111
114 int tpe; /* TPE is selected */ 112 int tpe; /* TPE is selected */
115 int auto_select; /* cable-selection is by carrier */ 113 int auto_select; /* cable-selection is by carrier */
116 unsigned short busmaster_regval; 114 unsigned short busmaster_regval;
117 115
118 unsigned int irq; /* IRQ to register */ 116 unsigned int irq; /* IRQ to register */
119 117
120 /* This is because the HP LANCE is disgusting and you have to check 118 /* This is because the HP LANCE is disgusting and you have to check
121 * a DIO-specific register every time you read/write the LANCE regs :-< 119 * a DIO-specific register every time you read/write the LANCE regs :-<
122 * [could we get away with making these some sort of macro?] 120 * [could we get away with making these some sort of macro?]
123 */ 121 */
124 void (*writerap)(void *, unsigned short); 122 void (*writerap)(void *, unsigned short);
125 void (*writerdp)(void *, unsigned short); 123 void (*writerdp)(void *, unsigned short);
126 unsigned short (*readrdp)(void *); 124 unsigned short (*readrdp)(void *);
127 spinlock_t devlock; 125 spinlock_t devlock;
128 char tx_full; 126 char tx_full;
129}; 127};
130 128
131/* 129/*
132 * Am7990 Control and Status Registers 130 * Am7990 Control and Status Registers
133 */ 131 */
134#define LE_CSR0 0x0000 /* LANCE Controller Status */ 132#define LE_CSR0 0x0000 /* LANCE Controller Status */
135#define LE_CSR1 0x0001 /* IADR[15:0] (bit0==0 ie word aligned) */ 133#define LE_CSR1 0x0001 /* IADR[15:0] (bit0==0 ie word aligned) */
136#define LE_CSR2 0x0002 /* IADR[23:16] (high bits reserved) */ 134#define LE_CSR2 0x0002 /* IADR[23:16] (high bits reserved) */
137#define LE_CSR3 0x0003 /* Misc */ 135#define LE_CSR3 0x0003 /* Misc */
138 136
139/* 137/*
140 * Bit definitions for CSR0 (LANCE Controller Status) 138 * Bit definitions for CSR0 (LANCE Controller Status)
141 */ 139 */
142#define LE_C0_ERR 0x8000 /* Error = BABL | CERR | MISS | MERR */ 140#define LE_C0_ERR 0x8000 /* Error = BABL | CERR | MISS | MERR */
143#define LE_C0_BABL 0x4000 /* Babble: Transmitted too many bits */ 141#define LE_C0_BABL 0x4000 /* Babble: Transmitted too many bits */
144#define LE_C0_CERR 0x2000 /* No Heartbeat (10BASE-T) */ 142#define LE_C0_CERR 0x2000 /* No Heartbeat (10BASE-T) */
145#define LE_C0_MISS 0x1000 /* Missed Frame (no rx buffer to put it in) */ 143#define LE_C0_MISS 0x1000 /* Missed Frame (no rx buffer to put it in) */
146#define LE_C0_MERR 0x0800 /* Memory Error */ 144#define LE_C0_MERR 0x0800 /* Memory Error */
147#define LE_C0_RINT 0x0400 /* Receive Interrupt */ 145#define LE_C0_RINT 0x0400 /* Receive Interrupt */
148#define LE_C0_TINT 0x0200 /* Transmit Interrupt */ 146#define LE_C0_TINT 0x0200 /* Transmit Interrupt */
149#define LE_C0_IDON 0x0100 /* Initialization Done */ 147#define LE_C0_IDON 0x0100 /* Initialization Done */
150#define LE_C0_INTR 0x0080 /* Interrupt Flag 148#define LE_C0_INTR 0x0080 /* Interrupt Flag
151 = BABL | MISS | MERR | RINT | TINT | IDON */ 149 = BABL | MISS | MERR | RINT | TINT | IDON */
152#define LE_C0_INEA 0x0040 /* Interrupt Enable */ 150#define LE_C0_INEA 0x0040 /* Interrupt Enable */
153#define LE_C0_RXON 0x0020 /* Receive On */ 151#define LE_C0_RXON 0x0020 /* Receive On */
154#define LE_C0_TXON 0x0010 /* Transmit On */ 152#define LE_C0_TXON 0x0010 /* Transmit On */
155#define LE_C0_TDMD 0x0008 /* Transmit Demand */ 153#define LE_C0_TDMD 0x0008 /* Transmit Demand */
156#define LE_C0_STOP 0x0004 /* Stop */ 154#define LE_C0_STOP 0x0004 /* Stop */
157#define LE_C0_STRT 0x0002 /* Start */ 155#define LE_C0_STRT 0x0002 /* Start */
158#define LE_C0_INIT 0x0001 /* Initialize */ 156#define LE_C0_INIT 0x0001 /* Initialize */
159 157
160 158
161/* 159/*
162 * Bit definitions for CSR3 160 * Bit definitions for CSR3
163 */ 161 */
164#define LE_C3_BSWP 0x0004 /* Byte Swap 162#define LE_C3_BSWP 0x0004 /* Byte Swap (on for big endian byte order) */
165 (on for big endian byte order) */ 163#define LE_C3_ACON 0x0002 /* ALE Control (on for active low ALE) */
166#define LE_C3_ACON 0x0002 /* ALE Control 164#define LE_C3_BCON 0x0001 /* Byte Control */
167 (on for active low ALE) */
168#define LE_C3_BCON 0x0001 /* Byte Control */
169 165
170 166
171/* 167/*
172 * Mode Flags 168 * Mode Flags
173 */ 169 */
174#define LE_MO_PROM 0x8000 /* Promiscuous Mode */ 170#define LE_MO_PROM 0x8000 /* Promiscuous Mode */
175/* these next ones 0x4000 -- 0x0080 are not available on the LANCE 7990, 171/* these next ones 0x4000 -- 0x0080 are not available on the LANCE 7990,
176 * but they are in NetBSD's am7990.h, presumably for backwards-compatible chips 172 * but they are in NetBSD's am7990.h, presumably for backwards-compatible chips
177 */ 173 */
178#define LE_MO_DRCVBC 0x4000 /* disable receive broadcast */ 174#define LE_MO_DRCVBC 0x4000 /* disable receive broadcast */
179#define LE_MO_DRCVPA 0x2000 /* disable physical address detection */ 175#define LE_MO_DRCVPA 0x2000 /* disable physical address detection */
180#define LE_MO_DLNKTST 0x1000 /* disable link status */ 176#define LE_MO_DLNKTST 0x1000 /* disable link status */
181#define LE_MO_DAPC 0x0800 /* disable automatic polarity correction */ 177#define LE_MO_DAPC 0x0800 /* disable automatic polarity correction */
182#define LE_MO_MENDECL 0x0400 /* MENDEC loopback mode */ 178#define LE_MO_MENDECL 0x0400 /* MENDEC loopback mode */
183#define LE_MO_LRTTSEL 0x0200 /* lower RX threshold / TX mode selection */ 179#define LE_MO_LRTTSEL 0x0200 /* lower RX threshold / TX mode selection */
184#define LE_MO_PSEL1 0x0100 /* port selection bit1 */ 180#define LE_MO_PSEL1 0x0100 /* port selection bit1 */
185#define LE_MO_PSEL0 0x0080 /* port selection bit0 */ 181#define LE_MO_PSEL0 0x0080 /* port selection bit0 */
186/* and this one is from the C-LANCE data sheet... */ 182/* and this one is from the C-LANCE data sheet... */
187#define LE_MO_EMBA 0x0080 /* Enable Modified Backoff Algorithm 183#define LE_MO_EMBA 0x0080 /* Enable Modified Backoff Algorithm
188 (C-LANCE, not original LANCE) */ 184 (C-LANCE, not original LANCE) */
189#define LE_MO_INTL 0x0040 /* Internal Loopback */ 185#define LE_MO_INTL 0x0040 /* Internal Loopback */
190#define LE_MO_DRTY 0x0020 /* Disable Retry */ 186#define LE_MO_DRTY 0x0020 /* Disable Retry */
191#define LE_MO_FCOLL 0x0010 /* Force Collision */ 187#define LE_MO_FCOLL 0x0010 /* Force Collision */
192#define LE_MO_DXMTFCS 0x0008 /* Disable Transmit CRC */ 188#define LE_MO_DXMTFCS 0x0008 /* Disable Transmit CRC */
193#define LE_MO_LOOP 0x0004 /* Loopback Enable */ 189#define LE_MO_LOOP 0x0004 /* Loopback Enable */
194#define LE_MO_DTX 0x0002 /* Disable Transmitter */ 190#define LE_MO_DTX 0x0002 /* Disable Transmitter */
195#define LE_MO_DRX 0x0001 /* Disable Receiver */ 191#define LE_MO_DRX 0x0001 /* Disable Receiver */
196 192
197 193
198/* 194/*
199 * Receive Flags 195 * Receive Flags
200 */ 196 */
201#define LE_R1_OWN 0x80 /* LANCE owns the descriptor */ 197#define LE_R1_OWN 0x80 /* LANCE owns the descriptor */
202#define LE_R1_ERR 0x40 /* Error */ 198#define LE_R1_ERR 0x40 /* Error */
203#define LE_R1_FRA 0x20 /* Framing Error */ 199#define LE_R1_FRA 0x20 /* Framing Error */
204#define LE_R1_OFL 0x10 /* Overflow Error */ 200#define LE_R1_OFL 0x10 /* Overflow Error */
205#define LE_R1_CRC 0x08 /* CRC Error */ 201#define LE_R1_CRC 0x08 /* CRC Error */
206#define LE_R1_BUF 0x04 /* Buffer Error */ 202#define LE_R1_BUF 0x04 /* Buffer Error */
207#define LE_R1_SOP 0x02 /* Start of Packet */ 203#define LE_R1_SOP 0x02 /* Start of Packet */
208#define LE_R1_EOP 0x01 /* End of Packet */ 204#define LE_R1_EOP 0x01 /* End of Packet */
209#define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */ 205#define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */
210 206
211 207
212/* 208/*
213 * Transmit Flags 209 * Transmit Flags
214 */ 210 */
215#define LE_T1_OWN 0x80 /* LANCE owns the descriptor */ 211#define LE_T1_OWN 0x80 /* LANCE owns the descriptor */
216#define LE_T1_ERR 0x40 /* Error */ 212#define LE_T1_ERR 0x40 /* Error */
217#define LE_T1_RES 0x20 /* Reserved, LANCE writes this with a zero */ 213#define LE_T1_RES 0x20 /* Reserved, LANCE writes this with a zero */
218#define LE_T1_EMORE 0x10 /* More than one retry needed */ 214#define LE_T1_EMORE 0x10 /* More than one retry needed */
219#define LE_T1_EONE 0x08 /* One retry needed */ 215#define LE_T1_EONE 0x08 /* One retry needed */
220#define LE_T1_EDEF 0x04 /* Deferred */ 216#define LE_T1_EDEF 0x04 /* Deferred */
221#define LE_T1_SOP 0x02 /* Start of Packet */ 217#define LE_T1_SOP 0x02 /* Start of Packet */
222#define LE_T1_EOP 0x01 /* End of Packet */ 218#define LE_T1_EOP 0x01 /* End of Packet */
223#define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */ 219#define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */
224 220
225/* 221/*
226 * Error Flags 222 * Error Flags
227 */ 223 */
228#define LE_T3_BUF 0x8000 /* Buffer Error */ 224#define LE_T3_BUF 0x8000 /* Buffer Error */
229#define LE_T3_UFL 0x4000 /* Underflow Error */ 225#define LE_T3_UFL 0x4000 /* Underflow Error */
230#define LE_T3_LCOL 0x1000 /* Late Collision */ 226#define LE_T3_LCOL 0x1000 /* Late Collision */
231#define LE_T3_CLOS 0x0800 /* Loss of Carrier */ 227#define LE_T3_CLOS 0x0800 /* Loss of Carrier */
232#define LE_T3_RTY 0x0400 /* Retry Error */ 228#define LE_T3_RTY 0x0400 /* Retry Error */
233#define LE_T3_TDR 0x03ff /* Time Domain Reflectometry */ 229#define LE_T3_TDR 0x03ff /* Time Domain Reflectometry */
234 230
235/* Miscellaneous useful macros */ 231/* Miscellaneous useful macros */
236 232
237#define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\ 233#define TX_BUFFS_AVAIL ((lp->tx_old <= lp->tx_new) ? \
238 lp->tx_old+lp->tx_ring_mod_mask-lp->tx_new:\ 234 lp->tx_old + lp->tx_ring_mod_mask - lp->tx_new : \
239 lp->tx_old - lp->tx_new-1) 235 lp->tx_old - lp->tx_new - 1)
240 236
241/* The LANCE only uses 24 bit addresses. This does the obvious thing. */ 237/* The LANCE only uses 24 bit addresses. This does the obvious thing. */
242#define LANCE_ADDR(x) ((int)(x) & ~0xff000000) 238#define LANCE_ADDR(x) ((int)(x) & ~0xff000000)
243 239
244/* Now the prototypes we export */ 240/* Now the prototypes we export */
245int lance_open(struct net_device *dev); 241int lance_open(struct net_device *dev);
246int lance_close (struct net_device *dev); 242int lance_close(struct net_device *dev);
247int lance_start_xmit (struct sk_buff *skb, struct net_device *dev); 243int lance_start_xmit(struct sk_buff *skb, struct net_device *dev);
248void lance_set_multicast (struct net_device *dev); 244void lance_set_multicast(struct net_device *dev);
249void lance_tx_timeout(struct net_device *dev); 245void lance_tx_timeout(struct net_device *dev);
250#ifdef CONFIG_NET_POLL_CONTROLLER 246#ifdef CONFIG_NET_POLL_CONTROLLER
251void lance_poll(struct net_device *dev); 247void lance_poll(struct net_device *dev);
diff --git a/drivers/net/ethernet/amd/hplance.c b/drivers/net/ethernet/amd/hplance.c
index 0c61fd50d882..88a81a18374d 100644
--- a/drivers/net/ethernet/amd/hplance.c
+++ b/drivers/net/ethernet/amd/hplance.c
@@ -127,41 +127,41 @@ static void hplance_remove_one(struct dio_dev *d)
127/* Initialise a single lance board at the given DIO device */ 127/* Initialise a single lance board at the given DIO device */
128static void hplance_init(struct net_device *dev, struct dio_dev *d) 128static void hplance_init(struct net_device *dev, struct dio_dev *d)
129{ 129{
130 unsigned long va = (d->resource.start + DIO_VIRADDRBASE); 130 unsigned long va = (d->resource.start + DIO_VIRADDRBASE);
131 struct hplance_private *lp; 131 struct hplance_private *lp;
132 int i; 132 int i;
133 133
134 /* reset the board */ 134 /* reset the board */
135 out_8(va+DIO_IDOFF, 0xff); 135 out_8(va + DIO_IDOFF, 0xff);
136 udelay(100); /* ariba! ariba! udelay! udelay! */ 136 udelay(100); /* ariba! ariba! udelay! udelay! */
137 137
138 /* Fill the dev fields */ 138 /* Fill the dev fields */
139 dev->base_addr = va; 139 dev->base_addr = va;
140 dev->netdev_ops = &hplance_netdev_ops; 140 dev->netdev_ops = &hplance_netdev_ops;
141 dev->dma = 0; 141 dev->dma = 0;
142 142
143 for (i=0; i<6; i++) { 143 for (i = 0; i < 6; i++) {
144 /* The NVRAM holds our ethernet address, one nibble per byte, 144 /* The NVRAM holds our ethernet address, one nibble per byte,
145 * at bytes NVRAMOFF+1,3,5,7,9... 145 * at bytes NVRAMOFF+1,3,5,7,9...
146 */ 146 */
147 dev->dev_addr[i] = ((in_8(va + HPLANCE_NVRAMOFF + i*4 + 1) & 0xF) << 4) 147 dev->dev_addr[i] = ((in_8(va + HPLANCE_NVRAMOFF + i*4 + 1) & 0xF) << 4)
148 | (in_8(va + HPLANCE_NVRAMOFF + i*4 + 3) & 0xF); 148 | (in_8(va + HPLANCE_NVRAMOFF + i*4 + 3) & 0xF);
149 } 149 }
150 150
151 lp = netdev_priv(dev); 151 lp = netdev_priv(dev);
152 lp->lance.name = (char*)d->name; /* discards const, shut up gcc */ 152 lp->lance.name = (char *)d->name; /* discards const, shut up gcc */
153 lp->lance.base = va; 153 lp->lance.base = va;
154 lp->lance.init_block = (struct lance_init_block *)(va + HPLANCE_MEMOFF); /* CPU addr */ 154 lp->lance.init_block = (struct lance_init_block *)(va + HPLANCE_MEMOFF); /* CPU addr */
155 lp->lance.lance_init_block = NULL; /* LANCE addr of same RAM */ 155 lp->lance.lance_init_block = NULL; /* LANCE addr of same RAM */
156 lp->lance.busmaster_regval = LE_C3_BSWP; /* we're bigendian */ 156 lp->lance.busmaster_regval = LE_C3_BSWP; /* we're bigendian */
157 lp->lance.irq = d->ipl; 157 lp->lance.irq = d->ipl;
158 lp->lance.writerap = hplance_writerap; 158 lp->lance.writerap = hplance_writerap;
159 lp->lance.writerdp = hplance_writerdp; 159 lp->lance.writerdp = hplance_writerdp;
160 lp->lance.readrdp = hplance_readrdp; 160 lp->lance.readrdp = hplance_readrdp;
161 lp->lance.lance_log_rx_bufs = LANCE_LOG_RX_BUFFERS; 161 lp->lance.lance_log_rx_bufs = LANCE_LOG_RX_BUFFERS;
162 lp->lance.lance_log_tx_bufs = LANCE_LOG_TX_BUFFERS; 162 lp->lance.lance_log_tx_bufs = LANCE_LOG_TX_BUFFERS;
163 lp->lance.rx_ring_mod_mask = RX_RING_MOD_MASK; 163 lp->lance.rx_ring_mod_mask = RX_RING_MOD_MASK;
164 lp->lance.tx_ring_mod_mask = TX_RING_MOD_MASK; 164 lp->lance.tx_ring_mod_mask = TX_RING_MOD_MASK;
165} 165}
166 166
167/* This is disgusting. We have to check the DIO status register for ack every 167/* This is disgusting. We have to check the DIO status register for ack every
@@ -195,25 +195,25 @@ static unsigned short hplance_readrdp(void *priv)
195 195
196static int hplance_open(struct net_device *dev) 196static int hplance_open(struct net_device *dev)
197{ 197{
198 int status; 198 int status;
199 struct lance_private *lp = netdev_priv(dev); 199 struct lance_private *lp = netdev_priv(dev);
200 200
201 status = lance_open(dev); /* call generic lance open code */ 201 status = lance_open(dev); /* call generic lance open code */
202 if (status) 202 if (status)
203 return status; 203 return status;
204 /* enable interrupts at board level. */ 204 /* enable interrupts at board level. */
205 out_8(lp->base + HPLANCE_STATUS, LE_IE); 205 out_8(lp->base + HPLANCE_STATUS, LE_IE);
206 206
207 return 0; 207 return 0;
208} 208}
209 209
210static int hplance_close(struct net_device *dev) 210static int hplance_close(struct net_device *dev)
211{ 211{
212 struct lance_private *lp = netdev_priv(dev); 212 struct lance_private *lp = netdev_priv(dev);
213 213
214 out_8(lp->base + HPLANCE_STATUS, 0); /* disable interrupts at boardlevel */ 214 out_8(lp->base + HPLANCE_STATUS, 0); /* disable interrupts at boardlevel */
215 lance_close(dev); 215 lance_close(dev);
216 return 0; 216 return 0;
217} 217}
218 218
219static int __init hplance_init_module(void) 219static int __init hplance_init_module(void)
@@ -223,7 +223,7 @@ static int __init hplance_init_module(void)
223 223
224static void __exit hplance_cleanup_module(void) 224static void __exit hplance_cleanup_module(void)
225{ 225{
226 dio_unregister_driver(&hplance_driver); 226 dio_unregister_driver(&hplance_driver);
227} 227}
228 228
229module_init(hplance_init_module); 229module_init(hplance_init_module);
diff --git a/drivers/net/ethernet/amd/mvme147.c b/drivers/net/ethernet/amd/mvme147.c
index e108e911da05..15a5e366af29 100644
--- a/drivers/net/ethernet/amd/mvme147.c
+++ b/drivers/net/ethernet/amd/mvme147.c
@@ -94,33 +94,31 @@ struct net_device * __init mvme147lance_probe(int unit)
94 dev->netdev_ops = &lance_netdev_ops; 94 dev->netdev_ops = &lance_netdev_ops;
95 dev->dma = 0; 95 dev->dma = 0;
96 96
97 addr=(u_long *)ETHERNET_ADDRESS; 97 addr = (u_long *)ETHERNET_ADDRESS;
98 address = *addr; 98 address = *addr;
99 dev->dev_addr[0]=0x08; 99 dev->dev_addr[0] = 0x08;
100 dev->dev_addr[1]=0x00; 100 dev->dev_addr[1] = 0x00;
101 dev->dev_addr[2]=0x3e; 101 dev->dev_addr[2] = 0x3e;
102 address=address>>8; 102 address = address >> 8;
103 dev->dev_addr[5]=address&0xff; 103 dev->dev_addr[5] = address&0xff;
104 address=address>>8; 104 address = address >> 8;
105 dev->dev_addr[4]=address&0xff; 105 dev->dev_addr[4] = address&0xff;
106 address=address>>8; 106 address = address >> 8;
107 dev->dev_addr[3]=address&0xff; 107 dev->dev_addr[3] = address&0xff;
108 108
109 printk("%s: MVME147 at 0x%08lx, irq %d, " 109 printk("%s: MVME147 at 0x%08lx, irq %d, Hardware Address %pM\n",
110 "Hardware Address %pM\n",
111 dev->name, dev->base_addr, MVME147_LANCE_IRQ, 110 dev->name, dev->base_addr, MVME147_LANCE_IRQ,
112 dev->dev_addr); 111 dev->dev_addr);
113 112
114 lp = netdev_priv(dev); 113 lp = netdev_priv(dev);
115 lp->ram = __get_dma_pages(GFP_ATOMIC, 3); /* 16K */ 114 lp->ram = __get_dma_pages(GFP_ATOMIC, 3); /* 16K */
116 if (!lp->ram) 115 if (!lp->ram) {
117 {
118 printk("%s: No memory for LANCE buffers\n", dev->name); 116 printk("%s: No memory for LANCE buffers\n", dev->name);
119 free_netdev(dev); 117 free_netdev(dev);
120 return ERR_PTR(-ENOMEM); 118 return ERR_PTR(-ENOMEM);
121 } 119 }
122 120
123 lp->lance.name = (char*)name; /* discards const, shut up gcc */ 121 lp->lance.name = (char *)name; /* discards const, shut up gcc */
124 lp->lance.base = dev->base_addr; 122 lp->lance.base = dev->base_addr;
125 lp->lance.init_block = (struct lance_init_block *)(lp->ram); /* CPU addr */ 123 lp->lance.init_block = (struct lance_init_block *)(lp->ram); /* CPU addr */
126 lp->lance.lance_init_block = (struct lance_init_block *)(lp->ram); /* LANCE addr of same RAM */ 124 lp->lance.lance_init_block = (struct lance_init_block *)(lp->ram); /* LANCE addr of same RAM */
@@ -167,8 +165,8 @@ static int m147lance_open(struct net_device *dev)
167 if (status) 165 if (status)
168 return status; 166 return status;
169 /* enable interrupts at board level. */ 167 /* enable interrupts at board level. */
170 m147_pcc->lan_cntrl=0; /* clear the interrupts (if any) */ 168 m147_pcc->lan_cntrl = 0; /* clear the interrupts (if any) */
171 m147_pcc->lan_cntrl=0x08 | 0x04; /* Enable irq 4 */ 169 m147_pcc->lan_cntrl = 0x08 | 0x04; /* Enable irq 4 */
172 170
173 return 0; 171 return 0;
174} 172}
@@ -176,7 +174,7 @@ static int m147lance_open(struct net_device *dev)
176static int m147lance_close(struct net_device *dev) 174static int m147lance_close(struct net_device *dev)
177{ 175{
178 /* disable interrupts at boardlevel */ 176 /* disable interrupts at boardlevel */
179 m147_pcc->lan_cntrl=0x0; /* disable interrupts */ 177 m147_pcc->lan_cntrl = 0x0; /* disable interrupts */
180 lance_close(dev); 178 lance_close(dev);
181 return 0; 179 return 0;
182} 180}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 20:03:05 -0500