aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--arch/mips/alchemy/common/sleeper.S6
-rw-r--r--arch/mips/include/asm/asm.h4
-rw-r--r--arch/mips/include/asm/atomic.h40
-rw-r--r--arch/mips/include/asm/bitops.h28
-rw-r--r--arch/mips/include/asm/cmpxchg.h20
-rw-r--r--arch/mips/include/asm/futex.h16
-rw-r--r--arch/mips/include/asm/io.h4
-rw-r--r--arch/mips/include/asm/local.h8
-rw-r--r--arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h12
-rw-r--r--arch/mips/include/asm/r4kcache.h4
-rw-r--r--arch/mips/include/asm/stackframe.h2
-rw-r--r--arch/mips/kernel/bmips_vec.S2
-rw-r--r--arch/mips/kernel/genex.S6
-rw-r--r--arch/mips/kernel/idle.c6
-rw-r--r--arch/mips/kernel/r4k_fpu.S2
-rw-r--r--arch/mips/kernel/r4k_switch.S2
-rw-r--r--arch/mips/kernel/syscall.c4
-rw-r--r--arch/mips/pmcs-msp71xx/msp_setup.c2
18 files changed, 84 insertions, 84 deletions
diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index 706d933e0085..c73d81270b42 100644
--- a/arch/mips/alchemy/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -95,7 +95,7 @@ LEAF(alchemy_sleep_au1000)
95 95
96 /* cache following instructions, as memory gets put to sleep */ 96 /* cache following instructions, as memory gets put to sleep */
97 la t0, 1f 97 la t0, 1f
98 .set mips3 98 .set arch=r4000
99 cache 0x14, 0(t0) 99 cache 0x14, 0(t0)
100 cache 0x14, 32(t0) 100 cache 0x14, 32(t0)
101 cache 0x14, 64(t0) 101 cache 0x14, 64(t0)
@@ -121,7 +121,7 @@ LEAF(alchemy_sleep_au1550)
121 121
122 /* cache following instructions, as memory gets put to sleep */ 122 /* cache following instructions, as memory gets put to sleep */
123 la t0, 1f 123 la t0, 1f
124 .set mips3 124 .set arch=r4000
125 cache 0x14, 0(t0) 125 cache 0x14, 0(t0)
126 cache 0x14, 32(t0) 126 cache 0x14, 32(t0)
127 cache 0x14, 64(t0) 127 cache 0x14, 64(t0)
@@ -163,7 +163,7 @@ LEAF(alchemy_sleep_au1300)
163 la t1, 4f 163 la t1, 4f
164 subu t2, t1, t0 164 subu t2, t1, t0
165 165
166 .set mips3 166 .set arch=r4000
167 167
1681: cache 0x14, 0(t0) 1681: cache 0x14, 0(t0)
169 subu t2, t2, 32 169 subu t2, t2, 32
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index b153e7991a9d..7c26b28bf252 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -146,7 +146,7 @@ symbol = value
146 146
147#define PREF(hint,addr) \ 147#define PREF(hint,addr) \
148 .set push; \ 148 .set push; \
149 .set mips4; \ 149 .set arch=r5000; \
150 pref hint, addr; \ 150 pref hint, addr; \
151 .set pop 151 .set pop
152 152
@@ -159,7 +159,7 @@ symbol = value
159 159
160#define PREFX(hint,addr) \ 160#define PREFX(hint,addr) \
161 .set push; \ 161 .set push; \
162 .set mips4; \ 162 .set arch=r5000; \
163 prefx hint, addr; \ 163 prefx hint, addr; \
164 .set pop 164 .set pop
165 165
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 7eed2f261710..e8eb3d53a241 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -53,7 +53,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
53 int temp; 53 int temp;
54 54
55 __asm__ __volatile__( 55 __asm__ __volatile__(
56 " .set mips3 \n" 56 " .set arch=r4000 \n"
57 "1: ll %0, %1 # atomic_add \n" 57 "1: ll %0, %1 # atomic_add \n"
58 " addu %0, %2 \n" 58 " addu %0, %2 \n"
59 " sc %0, %1 \n" 59 " sc %0, %1 \n"
@@ -66,7 +66,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
66 66
67 do { 67 do {
68 __asm__ __volatile__( 68 __asm__ __volatile__(
69 " .set mips3 \n" 69 " .set arch=r4000 \n"
70 " ll %0, %1 # atomic_add \n" 70 " ll %0, %1 # atomic_add \n"
71 " addu %0, %2 \n" 71 " addu %0, %2 \n"
72 " sc %0, %1 \n" 72 " sc %0, %1 \n"
@@ -96,7 +96,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
96 int temp; 96 int temp;
97 97
98 __asm__ __volatile__( 98 __asm__ __volatile__(
99 " .set mips3 \n" 99 " .set arch=r4000 \n"
100 "1: ll %0, %1 # atomic_sub \n" 100 "1: ll %0, %1 # atomic_sub \n"
101 " subu %0, %2 \n" 101 " subu %0, %2 \n"
102 " sc %0, %1 \n" 102 " sc %0, %1 \n"
@@ -109,7 +109,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
109 109
110 do { 110 do {
111 __asm__ __volatile__( 111 __asm__ __volatile__(
112 " .set mips3 \n" 112 " .set arch=r4000 \n"
113 " ll %0, %1 # atomic_sub \n" 113 " ll %0, %1 # atomic_sub \n"
114 " subu %0, %2 \n" 114 " subu %0, %2 \n"
115 " sc %0, %1 \n" 115 " sc %0, %1 \n"
@@ -139,7 +139,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
139 int temp; 139 int temp;
140 140
141 __asm__ __volatile__( 141 __asm__ __volatile__(
142 " .set mips3 \n" 142 " .set arch=r4000 \n"
143 "1: ll %1, %2 # atomic_add_return \n" 143 "1: ll %1, %2 # atomic_add_return \n"
144 " addu %0, %1, %3 \n" 144 " addu %0, %1, %3 \n"
145 " sc %0, %2 \n" 145 " sc %0, %2 \n"
@@ -153,7 +153,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
153 153
154 do { 154 do {
155 __asm__ __volatile__( 155 __asm__ __volatile__(
156 " .set mips3 \n" 156 " .set arch=r4000 \n"
157 " ll %1, %2 # atomic_add_return \n" 157 " ll %1, %2 # atomic_add_return \n"
158 " addu %0, %1, %3 \n" 158 " addu %0, %1, %3 \n"
159 " sc %0, %2 \n" 159 " sc %0, %2 \n"
@@ -188,7 +188,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
188 int temp; 188 int temp;
189 189
190 __asm__ __volatile__( 190 __asm__ __volatile__(
191 " .set mips3 \n" 191 " .set arch=r4000 \n"
192 "1: ll %1, %2 # atomic_sub_return \n" 192 "1: ll %1, %2 # atomic_sub_return \n"
193 " subu %0, %1, %3 \n" 193 " subu %0, %1, %3 \n"
194 " sc %0, %2 \n" 194 " sc %0, %2 \n"
@@ -205,7 +205,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
205 205
206 do { 206 do {
207 __asm__ __volatile__( 207 __asm__ __volatile__(
208 " .set mips3 \n" 208 " .set arch=r4000 \n"
209 " ll %1, %2 # atomic_sub_return \n" 209 " ll %1, %2 # atomic_sub_return \n"
210 " subu %0, %1, %3 \n" 210 " subu %0, %1, %3 \n"
211 " sc %0, %2 \n" 211 " sc %0, %2 \n"
@@ -248,7 +248,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
248 int temp; 248 int temp;
249 249
250 __asm__ __volatile__( 250 __asm__ __volatile__(
251 " .set mips3 \n" 251 " .set arch=r4000 \n"