diff options
-rw-r--r-- | drivers/clk/at91/clk-usb.c | 35 | ||||
-rw-r--r-- | drivers/clk/clk-divider.c | 18 | ||||
-rw-r--r-- | drivers/clk/pxa/clk-pxa27x.c | 4 | ||||
-rw-r--r-- | drivers/clk/qcom/mmcc-apq8084.c | 2 | ||||
-rw-r--r-- | drivers/clk/rockchip/clk.c | 4 | ||||
-rw-r--r-- | include/dt-bindings/clock/qcom,mmcc-apq8084.h | 2 | ||||
-rw-r--r-- | include/linux/clk-provider.h | 1 |
7 files changed, 32 insertions, 34 deletions
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c index 24b5b020753a..a23ac0c724f0 100644 --- a/drivers/clk/at91/clk-usb.c +++ b/drivers/clk/at91/clk-usb.c | |||
@@ -52,29 +52,26 @@ static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw, | |||
52 | 52 | ||
53 | tmp = pmc_read(pmc, AT91_PMC_USB); | 53 | tmp = pmc_read(pmc, AT91_PMC_USB); |
54 | usbdiv = (tmp & AT91_PMC_OHCIUSBDIV) >> SAM9X5_USB_DIV_SHIFT; | 54 | usbdiv = (tmp & AT91_PMC_OHCIUSBDIV) >> SAM9X5_USB_DIV_SHIFT; |
55 | return parent_rate / (usbdiv + 1); | 55 | |
56 | return DIV_ROUND_CLOSEST(parent_rate, (usbdiv + 1)); | ||
56 | } | 57 | } |
57 | 58 | ||
58 | static long at91sam9x5_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate, | 59 | static long at91sam9x5_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate, |
59 | unsigned long *parent_rate) | 60 | unsigned long *parent_rate) |
60 | { | 61 | { |
61 | unsigned long div; | 62 | unsigned long div; |
62 | unsigned long bestrate; | 63 | |
63 | unsigned long tmp; | 64 | if (!rate) |
65 | return -EINVAL; | ||
64 | 66 | ||
65 | if (rate >= *parent_rate) | 67 | if (rate >= *parent_rate) |
66 | return *parent_rate; | 68 | return *parent_rate; |
67 | 69 | ||
68 | div = *parent_rate / rate; | 70 | div = DIV_ROUND_CLOSEST(*parent_rate, rate); |
69 | if (div >= SAM9X5_USB_MAX_DIV) | 71 | if (div > SAM9X5_USB_MAX_DIV + 1) |
70 | return *parent_rate / (SAM9X5_USB_MAX_DIV + 1); | 72 | div = SAM9X5_USB_MAX_DIV + 1; |
71 | |||
72 | bestrate = *parent_rate / div; | ||
73 | tmp = *parent_rate / (div + 1); | ||
74 | if (bestrate - rate > rate - tmp) | ||
75 | bestrate = tmp; | ||
76 | 73 | ||
77 | return bestrate; | 74 | return DIV_ROUND_CLOSEST(*parent_rate, div); |
78 | } | 75 | } |
79 | 76 | ||
80 | static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index) | 77 | static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index) |
@@ -106,9 +103,13 @@ static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, | |||
106 | u32 tmp; | 103 | u32 tmp; |
107 | struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); | 104 | struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); |
108 | struct at91_pmc *pmc = usb->pmc; | 105 | struct at91_pmc *pmc = usb->pmc; |
109 | unsigned long div = parent_rate / rate; | 106 | unsigned long div; |
107 | |||
108 | if (!rate) | ||
109 | return -EINVAL; | ||
110 | 110 | ||
111 | if (parent_rate % rate || div < 1 || div >= SAM9X5_USB_MAX_DIV) | 111 | div = DIV_ROUND_CLOSEST(parent_rate, rate); |
112 | if (div > SAM9X5_USB_MAX_DIV + 1 || !div) | ||
112 | return -EINVAL; | 113 | return -EINVAL; |
113 | 114 | ||
114 | tmp = pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_OHCIUSBDIV; | 115 | tmp = pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_OHCIUSBDIV; |
@@ -253,7 +254,7 @@ static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate, | |||
253 | 254 | ||
254 | tmp_parent_rate = rate * usb->divisors[i]; | 255 | tmp_parent_rate = rate * usb->divisors[i]; |
255 | tmp_parent_rate = __clk_round_rate(parent, tmp_parent_rate); | 256 | tmp_parent_rate = __clk_round_rate(parent, tmp_parent_rate); |
256 | tmprate = tmp_parent_rate / usb->divisors[i]; | 257 | tmprate = DIV_ROUND_CLOSEST(tmp_parent_rate, usb->divisors[i]); |
257 | if (tmprate < rate) | 258 | if (tmprate < rate) |
258 | tmpdiff = rate - tmprate; | 259 | tmpdiff = rate - tmprate; |
259 | else | 260 | else |
@@ -281,10 +282,10 @@ static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, | |||
281 | struct at91_pmc *pmc = usb->pmc; | 282 | struct at91_pmc *pmc = usb->pmc; |
282 | unsigned long div; | 283 | unsigned long div; |
283 | 284 | ||
284 | if (!rate || parent_rate % rate) | 285 | if (!rate) |
285 | return -EINVAL; | 286 | return -EINVAL; |
286 | 287 | ||
287 | div = parent_rate / rate; | 288 | div = DIV_ROUND_CLOSEST(parent_rate, rate); |
288 | 289 | ||
289 | for (i = 0; i < RM9200_USB_DIV_TAB_SIZE; i++) { | 290 | for (i = 0; i < RM9200_USB_DIV_TAB_SIZE; i++) { |
290 | if (usb->divisors[i] == div) { | 291 | if (usb->divisors[i] == div) { |
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 18a9de29df0e..c0a842b335c5 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c | |||
@@ -263,6 +263,14 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, | |||
263 | if (!rate) | 263 | if (!rate) |
264 | rate = 1; | 264 | rate = 1; |
265 | 265 | ||
266 | /* if read only, just return current value */ | ||
267 | if (divider->flags & CLK_DIVIDER_READ_ONLY) { | ||
268 | bestdiv = readl(divider->reg) >> divider->shift; | ||
269 | bestdiv &= div_mask(divider); | ||
270 | bestdiv = _get_div(divider, bestdiv); | ||
271 | return bestdiv; | ||
272 | } | ||
273 | |||
266 | maxdiv = _get_maxdiv(divider); | 274 | maxdiv = _get_maxdiv(divider); |
267 | 275 | ||
268 | if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) { | 276 | if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) { |
@@ -361,11 +369,6 @@ const struct clk_ops clk_divider_ops = { | |||
361 | }; | 369 | }; |
362 | EXPORT_SYMBOL_GPL(clk_divider_ops); | 370 | EXPORT_SYMBOL_GPL(clk_divider_ops); |
363 | 371 | ||
364 | const struct clk_ops clk_divider_ro_ops = { | ||
365 | .recalc_rate = clk_divider_recalc_rate, | ||
366 | }; | ||
367 | EXPORT_SYMBOL_GPL(clk_divider_ro_ops); | ||
368 | |||
369 | static struct clk *_register_divider(struct device *dev, const char *name, | 372 | static struct clk *_register_divider(struct device *dev, const char *name, |
370 | const char *parent_name, unsigned long flags, | 373 | const char *parent_name, unsigned long flags, |
371 | void __iomem *reg, u8 shift, u8 width, | 374 | void __iomem *reg, u8 shift, u8 width, |
@@ -391,10 +394,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, | |||
391 | } | 394 | } |
392 | 395 | ||
393 | init.name = name; | 396 | init.name = name; |
394 | if (clk_divider_flags & CLK_DIVIDER_READ_ONLY) | 397 | init.ops = &clk_divider_ops; |
395 | init.ops = &clk_divider_ro_ops; | ||
396 | else | ||
397 | init.ops = &clk_divider_ops; | ||
398 | init.flags = flags | CLK_IS_BASIC; | 398 | init.flags = flags | CLK_IS_BASIC; |
399 | init.parent_names = (parent_name ? &parent_name: NULL); | 399 | init.parent_names = (parent_name ? &parent_name: NULL); |
400 | init.num_parents = (parent_name ? 1 : 0); | 400 | init.num_parents = (parent_name ? 1 : 0); |
diff --git a/drivers/clk/pxa/clk-pxa27x.c b/drivers/clk/pxa/clk-pxa27x.c index b345cc791e5d..88b9fe13fa44 100644 --- a/drivers/clk/pxa/clk-pxa27x.c +++ b/drivers/clk/pxa/clk-pxa27x.c | |||
@@ -322,7 +322,7 @@ static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw, | |||
322 | unsigned long ccsr = CCSR; | 322 | unsigned long ccsr = CCSR; |
323 | 323 | ||
324 | osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); | 324 | osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); |
325 | a = cccr & CCCR_A_BIT; | 325 | a = cccr & (1 << CCCR_A_BIT); |
326 | l = ccsr & CCSR_L_MASK; | 326 | l = ccsr & CCSR_L_MASK; |
327 | 327 | ||
328 | if (osc_forced || a) | 328 | if (osc_forced || a) |
@@ -341,7 +341,7 @@ static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw) | |||
341 | unsigned long ccsr = CCSR; | 341 | unsigned long ccsr = CCSR; |
342 | 342 | ||
343 | osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); | 343 | osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); |
344 | a = cccr & CCCR_A_BIT; | 344 | a = cccr & (1 << CCCR_A_BIT); |
345 | if (osc_forced) | 345 | if (osc_forced) |
346 | return PXA_MEM_13Mhz; | 346 | return PXA_MEM_13Mhz; |
347 | if (a) | 347 | if (a) |
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c index dab988ab8cf1..157139a5c1ca 100644 --- a/drivers/clk/qcom/mmcc-apq8084.c +++ b/drivers/clk/qcom/mmcc-apq8084.c | |||
@@ -3122,7 +3122,7 @@ static struct clk_regmap *mmcc_apq8084_clocks[] = { | |||
3122 | [ESC1_CLK_SRC] = &esc1_clk_src.clkr, | 3122 | [ESC1_CLK_SRC] = &esc1_clk_src.clkr, |
3123 | [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, | 3123 | [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, |
3124 | [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, | 3124 | [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, |
3125 | [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, | 3125 | [MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, |
3126 | [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, | 3126 | [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, |
3127 | [MAPLE_CLK_SRC] = &maple_clk_src.clkr, | 3127 | [MAPLE_CLK_SRC] = &maple_clk_src.clkr, |
3128 | [VDP_CLK_SRC] = &vdp_clk_src.clkr, | 3128 | [VDP_CLK_SRC] = &vdp_clk_src.clkr, |
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 1e68bff481b8..880a266f0143 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c | |||
@@ -90,9 +90,7 @@ static struct clk *rockchip_clk_register_branch(const char *name, | |||
90 | div->width = div_width; | 90 | div->width = div_width; |
91 | div->lock = lock; | 91 | div->lock = lock; |
92 | div->table = div_table; | 92 | div->table = div_table; |
93 | div_ops = (div_flags & CLK_DIVIDER_READ_ONLY) | 93 | div_ops = &clk_divider_ops; |
94 | ? &clk_divider_ro_ops | ||
95 | : &clk_divider_ops; | ||
96 | } | 94 | } |
97 | 95 | ||
98 | clk = clk_register_composite(NULL, name, parent_names, num_parents, | 96 | clk = clk_register_composite(NULL, name, parent_names, num_parents, |
diff --git a/include/dt-bindings/clock/qcom,mmcc-apq8084.h b/include/dt-bindings/clock/qcom,mmcc-apq8084.h index a929f86d0ddd..d72b5b35f15e 100644 --- a/include/dt-bindings/clock/qcom,mmcc-apq8084.h +++ b/include/dt-bindings/clock/qcom,mmcc-apq8084.h | |||
@@ -60,7 +60,7 @@ | |||
60 | #define ESC1_CLK_SRC 43 | 60 | #define ESC1_CLK_SRC 43 |
61 | #define HDMI_CLK_SRC 44 | 61 | #define HDMI_CLK_SRC 44 |
62 | #define VSYNC_CLK_SRC 45 | 62 | #define VSYNC_CLK_SRC 45 |
63 | #define RBCPR_CLK_SRC 46 | 63 | #define MMSS_RBCPR_CLK_SRC 46 |
64 | #define RBBMTIMER_CLK_SRC 47 | 64 | #define RBBMTIMER_CLK_SRC 47 |
65 | #define MAPLE_CLK_SRC 48 | 65 | #define MAPLE_CLK_SRC 48 |
66 | #define VDP_CLK_SRC 49 | 66 | #define VDP_CLK_SRC 49 |
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index be21af149f11..2839c639f092 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h | |||
@@ -352,7 +352,6 @@ struct clk_divider { | |||
352 | #define CLK_DIVIDER_READ_ONLY BIT(5) | 352 | #define CLK_DIVIDER_READ_ONLY BIT(5) |
353 | 353 | ||
354 | extern const struct clk_ops clk_divider_ops; | 354 | extern const struct clk_ops clk_divider_ops; |
355 | extern const struct clk_ops clk_divider_ro_ops; | ||
356 | struct clk *clk_register_divider(struct device *dev, const char *name, | 355 | struct clk *clk_register_divider(struct device *dev, const char *name, |
357 | const char *parent_name, unsigned long flags, | 356 | const char *parent_name, unsigned long flags, |
358 | void __iomem *reg, u8 shift, u8 width, | 357 | void __iomem *reg, u8 shift, u8 width, |