diff options
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index f4af1ca0fb62..6ddc5677ea2f 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c | |||
| @@ -1253,21 +1253,21 @@ hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) | |||
| 1253 | 1253 | ||
| 1254 | #define __i915_read(x, y) \ | 1254 | #define __i915_read(x, y) \ |
| 1255 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | 1255 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
| 1256 | unsigned long irqflags; \ | ||
| 1256 | u##x val = 0; \ | 1257 | u##x val = 0; \ |
| 1258 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ | ||
| 1257 | if (IS_GEN5(dev_priv->dev)) \ | 1259 | if (IS_GEN5(dev_priv->dev)) \ |
| 1258 | ilk_dummy_write(dev_priv); \ | 1260 | ilk_dummy_write(dev_priv); \ |
| 1259 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | 1261 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 1260 | unsigned long irqflags; \ | ||
| 1261 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ | ||
| 1262 | if (dev_priv->forcewake_count == 0) \ | 1262 | if (dev_priv->forcewake_count == 0) \ |
| 1263 | dev_priv->gt.force_wake_get(dev_priv); \ | 1263 | dev_priv->gt.force_wake_get(dev_priv); \ |
| 1264 | val = read##y(dev_priv->regs + reg); \ | 1264 | val = read##y(dev_priv->regs + reg); \ |
| 1265 | if (dev_priv->forcewake_count == 0) \ | 1265 | if (dev_priv->forcewake_count == 0) \ |
| 1266 | dev_priv->gt.force_wake_put(dev_priv); \ | 1266 | dev_priv->gt.force_wake_put(dev_priv); \ |
| 1267 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ | ||
| 1268 | } else { \ | 1267 | } else { \ |
| 1269 | val = read##y(dev_priv->regs + reg); \ | 1268 | val = read##y(dev_priv->regs + reg); \ |
| 1270 | } \ | 1269 | } \ |
| 1270 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ | ||
| 1271 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ | 1271 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ |
| 1272 | return val; \ | 1272 | return val; \ |
| 1273 | } | 1273 | } |
| @@ -1280,8 +1280,10 @@ __i915_read(64, q) | |||
| 1280 | 1280 | ||
| 1281 | #define __i915_write(x, y) \ | 1281 | #define __i915_write(x, y) \ |
| 1282 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | 1282 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
| 1283 | unsigned long irqflags; \ | ||
| 1283 | u32 __fifo_ret = 0; \ | 1284 | u32 __fifo_ret = 0; \ |
| 1284 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ | 1285 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
| 1286 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ | ||
| 1285 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | 1287 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 1286 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ | 1288 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
| 1287 | } \ | 1289 | } \ |
| @@ -1293,6 +1295,7 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | |||
| 1293 | gen6_gt_check_fifodbg(dev_priv); \ | 1295 | gen6_gt_check_fifodbg(dev_priv); \ |
| 1294 | } \ | 1296 | } \ |
| 1295 | hsw_unclaimed_reg_check(dev_priv, reg); \ | 1297 | hsw_unclaimed_reg_check(dev_priv, reg); \ |
| 1298 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ | ||
| 1296 | } | 1299 | } |
| 1297 | __i915_write(8, b) | 1300 | __i915_write(8, b) |
| 1298 | __i915_write(16, w) | 1301 | __i915_write(16, w) |
