diff options
263 files changed, 2919 insertions, 6559 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt index 7f9fb85f5456..e7f4dc14eff2 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt | |||
@@ -2,7 +2,7 @@ Allwinner Sunxi Interrupt Controller | |||
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | 4 | ||
5 | - compatible : should be "allwinner,sunxi-ic" | 5 | - compatible : should be "allwinner,sun4i-ic" |
6 | - reg : Specifies base physical address and size of the registers. | 6 | - reg : Specifies base physical address and size of the registers. |
7 | - interrupt-controller : Identifies the node as an interrupt controller | 7 | - interrupt-controller : Identifies the node as an interrupt controller |
8 | - #interrupt-cells : Specifies the number of cells needed to encode an | 8 | - #interrupt-cells : Specifies the number of cells needed to encode an |
@@ -97,7 +97,7 @@ The interrupt sources are as follows: | |||
97 | Example: | 97 | Example: |
98 | 98 | ||
99 | intc: interrupt-controller { | 99 | intc: interrupt-controller { |
100 | compatible = "allwinner,sunxi-ic"; | 100 | compatible = "allwinner,sun4i-ic"; |
101 | reg = <0x01c20400 0x400>; | 101 | reg = <0x01c20400 0x400>; |
102 | interrupt-controller; | 102 | interrupt-controller; |
103 | #interrupt-cells = <2>; | 103 | #interrupt-cells = <2>; |
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt index 0c7b64e95a61..48aeb7884ed3 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt +++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt | |||
@@ -2,7 +2,7 @@ Allwinner A1X SoCs Timer Controller | |||
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | 4 | ||
5 | - compatible : should be "allwinner,sunxi-timer" | 5 | - compatible : should be "allwinner,sun4i-timer" |
6 | - reg : Specifies base physical address and size of the registers. | 6 | - reg : Specifies base physical address and size of the registers. |
7 | - interrupts : The interrupt of the first timer | 7 | - interrupts : The interrupt of the first timer |
8 | - clocks: phandle to the source clock (usually a 24 MHz fixed clock) | 8 | - clocks: phandle to the source clock (usually a 24 MHz fixed clock) |
@@ -10,7 +10,7 @@ Required properties: | |||
10 | Example: | 10 | Example: |
11 | 11 | ||
12 | timer { | 12 | timer { |
13 | compatible = "allwinner,sunxi-timer"; | 13 | compatible = "allwinner,sun4i-timer"; |
14 | reg = <0x01c20c00 0x400>; | 14 | reg = <0x01c20c00 0x400>; |
15 | interrupts = <22>; | 15 | interrupts = <22>; |
16 | clocks = <&osc>; | 16 | clocks = <&osc>; |
diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sun4i-wdt.txt index 0b2717775600..ecd650adff31 100644 --- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/sun4i-wdt.txt | |||
@@ -1,13 +1,13 @@ | |||
1 | Allwinner sunXi Watchdog timer | 1 | Allwinner sun4i Watchdog timer |
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | 4 | ||
5 | - compatible : should be "allwinner,sunxi-wdt" | 5 | - compatible : should be "allwinner,sun4i-wdt" |
6 | - reg : Specifies base physical address and size of the registers. | 6 | - reg : Specifies base physical address and size of the registers. |
7 | 7 | ||
8 | Example: | 8 | Example: |
9 | 9 | ||
10 | wdt: watchdog@01c20c90 { | 10 | wdt: watchdog@01c20c90 { |
11 | compatible = "allwinner,sunxi-wdt"; | 11 | compatible = "allwinner,sun4i-wdt"; |
12 | reg = <0x01c20c90 0x10>; | 12 | reg = <0x01c20c90 0x10>; |
13 | }; | 13 | }; |
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 006f9838dd43..7af7d1368942 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -411,6 +411,7 @@ config ARCH_GEMINI | |||
411 | bool "Cortina Systems Gemini" | 411 | bool "Cortina Systems Gemini" |
412 | select ARCH_REQUIRE_GPIOLIB | 412 | select ARCH_REQUIRE_GPIOLIB |
413 | select ARCH_USES_GETTIMEOFFSET | 413 | select ARCH_USES_GETTIMEOFFSET |
414 | select NEED_MACH_GPIO_H | ||
414 | select CPU_FA526 | 415 | select CPU_FA526 |
415 | help | 416 | help |
416 | Support for the Cortina Systems Gemini family SoCs | 417 | Support for the Cortina Systems Gemini family SoCs |
@@ -474,12 +475,14 @@ config ARCH_MXS | |||
474 | select ARCH_REQUIRE_GPIOLIB | 475 | select ARCH_REQUIRE_GPIOLIB |
475 | select CLKDEV_LOOKUP | 476 | select CLKDEV_LOOKUP |
476 | select CLKSRC_MMIO | 477 | select CLKSRC_MMIO |
478 | select CLKSRC_OF | ||
477 | select COMMON_CLK | 479 | select COMMON_CLK |
478 | select GENERIC_CLOCKEVENTS | 480 | select GENERIC_CLOCKEVENTS |
479 | select HAVE_CLK_PREPARE | 481 | select HAVE_CLK_PREPARE |
480 | select MULTI_IRQ_HANDLER | 482 | select MULTI_IRQ_HANDLER |
481 | select PINCTRL | 483 | select PINCTRL |
482 | select SPARSE_IRQ | 484 | select SPARSE_IRQ |
485 | select STMP_DEVICE | ||
483 | select USE_OF | 486 | select USE_OF |
484 | help | 487 | help |
485 | Support for Freescale MXS-based family of processors | 488 | Support for Freescale MXS-based family of processors |
@@ -493,14 +496,6 @@ config ARCH_NETX | |||
493 | help | 496 | help |
494 | This enables support for systems based on the Hilscher NetX Soc | 497 | This enables support for systems based on the Hilscher NetX Soc |
495 | 498 | ||
496 | config ARCH_H720X | ||
497 | bool "Hynix HMS720x-based" | ||
498 | select ARCH_USES_GETTIMEOFFSET | ||
499 | select CPU_ARM720T | ||
500 | select ISA_DMA_API | ||
501 | help | ||
502 | This enables support for systems based on the Hynix HMS720x | ||
503 | |||
504 | config ARCH_IOP13XX | 499 | config ARCH_IOP13XX |
505 | bool "IOP13xx-based" | 500 | bool "IOP13xx-based" |
506 | depends on MMU | 501 | depends on MMU |
@@ -1054,8 +1049,6 @@ source "arch/arm/mach-footbridge/Kconfig" | |||
1054 | 1049 | ||
1055 | source "arch/arm/mach-gemini/Kconfig" | 1050 | source "arch/arm/mach-gemini/Kconfig" |
1056 | 1051 | ||
1057 | source "arch/arm/mach-h720x/Kconfig" | ||
1058 | |||
1059 | source "arch/arm/mach-highbank/Kconfig" | 1052 | source "arch/arm/mach-highbank/Kconfig" |
1060 | 1053 | ||
1061 | source "arch/arm/mach-integrator/Kconfig" | 1054 | source "arch/arm/mach-integrator/Kconfig" |
@@ -1176,7 +1169,6 @@ config PLAT_VERSATILE | |||
1176 | config ARM_TIMER_SP804 | 1169 | config ARM_TIMER_SP804 |
1177 | bool | 1170 | bool |
1178 | select CLKSRC_MMIO | 1171 | select CLKSRC_MMIO |
1179 | select HAVE_SCHED_CLOCK | ||
1180 | 1172 | ||
1181 | source arch/arm/mm/Kconfig | 1173 | source arch/arm/mm/Kconfig |
1182 | 1174 | ||
@@ -1606,6 +1598,7 @@ config HAVE_ARM_ARCH_TIMER | |||
1606 | config HAVE_ARM_TWD | 1598 | config HAVE_ARM_TWD |
1607 | bool | 1599 | bool |
1608 | depends on SMP | 1600 | depends on SMP |
1601 | select CLKSRC_OF if OF | ||
1609 | help | 1602 | help |
1610 | This options enables support for the ARM timer and watchdog unit | 1603 | This options enables support for the ARM timer and watchdog unit |
1611 | 1604 | ||
@@ -2165,13 +2158,6 @@ menu "CPU Power Management" | |||
2165 | if ARCH_HAS_CPUFREQ | 2158 | if ARCH_HAS_CPUFREQ |
2166 | source "drivers/cpufreq/Kconfig" | 2159 | source "drivers/cpufreq/Kconfig" |
2167 | 2160 | ||
2168 | config CPU_FREQ_IMX | ||
2169 | tristate "CPUfreq driver for i.MX CPUs" | ||
2170 | depends on ARCH_MXC && CPU_FREQ | ||
2171 | select CPU_FREQ_TABLE | ||
2172 | help | ||
2173 | This enables the CPUfreq driver for i.MX CPUs. | ||
2174 | |||
2175 | config CPU_FREQ_S3C | 2161 | config CPU_FREQ_S3C |
2176 | bool | 2162 | bool |
2177 | help | 2163 | help |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ee4605f400b0..e4d1d23916b0 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
@@ -147,7 +147,6 @@ machine-$(CONFIG_ARCH_DOVE) += dove | |||
147 | machine-$(CONFIG_ARCH_EBSA110) += ebsa110 | 147 | machine-$(CONFIG_ARCH_EBSA110) += ebsa110 |
148 | machine-$(CONFIG_ARCH_EP93XX) += ep93xx | 148 | machine-$(CONFIG_ARCH_EP93XX) += ep93xx |
149 | machine-$(CONFIG_ARCH_GEMINI) += gemini | 149 | machine-$(CONFIG_ARCH_GEMINI) += gemini |
150 | machine-$(CONFIG_ARCH_H720X) += h720x | ||
151 | machine-$(CONFIG_ARCH_HIGHBANK) += highbank | 150 | machine-$(CONFIG_ARCH_HIGHBANK) += highbank |
152 | machine-$(CONFIG_ARCH_INTEGRATOR) += integrator | 151 | machine-$(CONFIG_ARCH_INTEGRATOR) += integrator |
153 | machine-$(CONFIG_ARCH_IOP13XX) += iop13xx | 152 | machine-$(CONFIG_ARCH_IOP13XX) += iop13xx |
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 56afcf41aae0..ad2d79324cd3 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi | |||
@@ -295,6 +295,7 @@ | |||
295 | }; | 295 | }; |
296 | 296 | ||
297 | digctl@8001c000 { | 297 | digctl@8001c000 { |
298 | compatible = "fsl,imx23-digctl"; | ||
298 | reg = <0x8001c000 2000>; | 299 | reg = <0x8001c000 2000>; |
299 | status = "disabled"; | 300 | status = "disabled"; |
300 | }; | 301 | }; |
@@ -321,6 +322,7 @@ | |||
321 | }; | 322 | }; |
322 | 323 | ||
323 | ocotp@8002c000 { | 324 | ocotp@8002c000 { |
325 | compatible = "fsl,ocotp"; | ||
324 | reg = <0x8002c000 0x2000>; | 326 | reg = <0x8002c000 0x2000>; |
325 | status = "disabled"; | 327 | status = "disabled"; |
326 | }; | 328 | }; |
@@ -360,7 +362,7 @@ | |||
360 | ranges; | 362 | ranges; |
361 | 363 | ||
362 | clks: clkctrl@80040000 { | 364 | clks: clkctrl@80040000 { |
363 | compatible = "fsl,imx23-clkctrl"; | 365 | compatible = "fsl,imx23-clkctrl", "fsl,clkctrl"; |
364 | reg = <0x80040000 0x2000>; | 366 | reg = <0x80040000 0x2000>; |
365 | #clock-cells = <1>; | 367 | #clock-cells = <1>; |
366 | }; | 368 | }; |
@@ -426,6 +428,7 @@ | |||
426 | compatible = "fsl,imx23-timrot", "fsl,timrot"; | 428 | compatible = "fsl,imx23-timrot", "fsl,timrot"; |
427 | reg = <0x80068000 0x2000>; | 429 | reg = <0x80068000 0x2000>; |
428 | interrupts = <28 29 30 31>; | 430 | interrupts = <28 29 30 31>; |
431 | clocks = <&clks 28>; | ||
429 | }; | 432 | }; |
430 | 433 | ||
431 | auart0: serial@8006c000 { | 434 | auart0: serial@8006c000 { |
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 7ba49662b9bc..64af2381c1b0 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi | |||
@@ -647,6 +647,7 @@ | |||
647 | }; | 647 | }; |
648 | 648 | ||
649 | digctl@8001c000 { | 649 | digctl@8001c000 { |
650 | compatible = "fsl,imx28-digctl"; | ||
650 | reg = <0x8001c000 0x2000>; | 651 | reg = <0x8001c000 0x2000>; |
651 | interrupts = <89>; | 652 | interrupts = <89>; |
652 | status = "disabled"; | 653 | status = "disabled"; |
@@ -676,6 +677,7 @@ | |||
676 | }; | 677 | }; |
677 | 678 | ||
678 | ocotp@8002c000 { | 679 | ocotp@8002c000 { |
680 | compatible = "fsl,ocotp"; | ||
679 | reg = <0x8002c000 0x2000>; | 681 | reg = <0x8002c000 0x2000>; |
680 | status = "disabled"; | 682 | status = "disabled"; |
681 | }; | 683 | }; |
@@ -755,7 +757,7 @@ | |||
755 | ranges; | 757 | ranges; |
756 | 758 | ||
757 | clks: clkctrl@80040000 { | 759 | clks: clkctrl@80040000 { |
758 | compatible = "fsl,imx28-clkctrl"; | 760 | compatible = "fsl,imx28-clkctrl", "fsl,clkctrl"; |
759 | reg = <0x80040000 0x2000>; | 761 | reg = <0x80040000 0x2000>; |
760 | #clock-cells = <1>; | 762 | #clock-cells = <1>; |
761 | }; | 763 | }; |
@@ -838,6 +840,7 @@ | |||
838 | compatible = "fsl,imx28-timrot", "fsl,timrot"; | 840 | compatible = "fsl,imx28-timrot", "fsl,timrot"; |
839 | reg = <0x80068000 0x2000>; | 841 | reg = <0x80068000 0x2000>; |
840 | interrupts = <48 49 50 51>; | 842 | interrupts = <48 49 50 51>; |
843 | clocks = <&clks 26>; | ||
841 | }; | 844 | }; |
842 | 845 | ||
843 | auart0: serial@8006a000 { | 846 | auart0: serial@8006a000 { |
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 1dfaf2874c57..e4ddeddcd437 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi | |||
@@ -99,7 +99,7 @@ | |||
99 | }; | 99 | }; |
100 | 100 | ||
101 | pmc { | 101 | pmc { |
102 | compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc"; | 102 | compatible = "nvidia,tegra114-pmc"; |
103 | reg = <0x7000e400 0x400>; | 103 | reg = <0x7000e400 0x400>; |
104 | }; | 104 | }; |
105 | 105 | ||
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 3d3f64d2111a..ad64c8cc9da7 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi | |||
@@ -145,6 +145,7 @@ | |||
145 | 0 1 0x04 | 145 | 0 1 0x04 |
146 | 0 41 0x04 | 146 | 0 41 0x04 |
147 | 0 42 0x04>; | 147 | 0 42 0x04>; |
148 | clocks = <&tegra_car 5>; | ||
148 | }; | 149 | }; |
149 | 150 | ||
150 | tegra_car: clock { | 151 | tegra_car: clock { |
@@ -304,6 +305,7 @@ | |||
304 | compatible = "nvidia,tegra20-rtc"; | 305 | compatible = "nvidia,tegra20-rtc"; |
305 | reg = <0x7000e000 0x100>; | 306 | reg = <0x7000e000 0x100>; |
306 | interrupts = <0 2 0x04>; | 307 | interrupts = <0 2 0x04>; |
308 | clocks = <&tegra_car 4>; | ||
307 | }; | 309 | }; |
308 | 310 | ||
309 | i2c@7000c000 { | 311 | i2c@7000c000 { |
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index dbf46c272562..9491edf1a067 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi | |||
@@ -148,6 +148,7 @@ | |||
148 | 0 42 0x04 | 148 | 0 42 0x04 |
149 | 0 121 0x04 | 149 | 0 121 0x04 |
150 | 0 122 0x04>; | 150 | 0 122 0x04>; |
151 | clocks = <&tegra_car 5>; | ||
151 | }; | 152 | }; |
152 | 153 | ||
153 | tegra_car: clock { | 154 | tegra_car: clock { |
@@ -291,6 +292,7 @@ | |||
291 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; | 292 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; |
292 | reg = <0x7000e000 0x100>; | 293 | reg = <0x7000e000 0x100>; |
293 | interrupts = <0 2 0x04>; | 294 | interrupts = <0 2 0x04>; |
295 | clocks = <&tegra_car 4>; | ||
294 | }; | 296 | }; |
295 | 297 | ||
296 | i2c@7000c000 { | 298 | i2c@7000c000 { |
@@ -423,7 +425,7 @@ | |||
423 | }; | 425 | }; |
424 | 426 | ||
425 | pmc { | 427 | pmc { |
426 | compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; | 428 | compatible = "nvidia,tegra30-pmc"; |
427 | reg = <0x7000e400 0x400>; | 429 | reg = <0x7000e400 0x400>; |
428 | }; | 430 | }; |
429 | 431 | ||
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 1ea959019fcd..047f2a415309 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig | |||
@@ -20,7 +20,7 @@ CONFIG_SOC_AT91SAM9263=y | |||
20 | CONFIG_SOC_AT91SAM9G45=y | 20 | CONFIG_SOC_AT91SAM9G45=y |
21 | CONFIG_SOC_AT91SAM9X5=y | 21 | CONFIG_SOC_AT91SAM9X5=y |
22 | CONFIG_SOC_AT91SAM9N12=y | 22 | CONFIG_SOC_AT91SAM9N12=y |
23 | CONFIG_MACH_AT91SAM_DT=y | 23 | CONFIG_MACH_AT91SAM9_DT=y |
24 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | 24 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y |
25 | CONFIG_AT91_TIMER_HZ=128 | 25 | CONFIG_AT91_TIMER_HZ=128 |
26 | CONFIG_AEABI=y | 26 | CONFIG_AEABI=y |
diff --git a/arch/arm/configs/at91sam9260_defconfig b/arch/arm/configs/at91sam9260_defconfig index 0ea5d2c97fc4..05618eb694f8 100644 --- a/arch/arm/configs/at91sam9260_defconfig +++ b/arch/arm/configs/at91sam9260_defconfig | |||
@@ -22,7 +22,7 @@ CONFIG_MACH_QIL_A9260=y | |||
22 | CONFIG_MACH_CPU9260=y | 22 | CONFIG_MACH_CPU9260=y |
23 | CONFIG_MACH_FLEXIBITY=y | 23 | CONFIG_MACH_FLEXIBITY=y |
24 | CONFIG_MACH_SNAPPER_9260=y | 24 | CONFIG_MACH_SNAPPER_9260=y |
25 | CONFIG_MACH_AT91SAM_DT=y | 25 | CONFIG_MACH_AT91SAM9_DT=y |
26 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | 26 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y |
27 | # CONFIG_ARM_THUMB is not set | 27 | # CONFIG_ARM_THUMB is not set |
28 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 28 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9g20_defconfig index 3b1881033ad8..892e8287ed73 100644 --- a/arch/arm/configs/at91sam9g20_defconfig +++ b/arch/arm/configs/at91sam9g20_defconfig | |||
@@ -22,7 +22,7 @@ CONFIG_MACH_PCONTROL_G20=y | |||
22 | CONFIG_MACH_GSIA18S=y | 22 | CONFIG_MACH_GSIA18S=y |
23 | CONFIG_MACH_USB_A9G20=y | 23 | CONFIG_MACH_USB_A9G20=y |
24 | CONFIG_MACH_SNAPPER_9260=y | 24 | CONFIG_MACH_SNAPPER_9260=y |
25 | CONFIG_MACH_AT91SAM_DT=y | 25 | CONFIG_MACH_AT91SAM9_DT=y |
26 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | 26 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y |
27 | # CONFIG_ARM_THUMB is not set | 27 | # CONFIG_ARM_THUMB is not set |
28 | CONFIG_AEABI=y | 28 | CONFIG_AEABI=y |
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig index 606d48f3b8f8..5f551b76cb65 100644 --- a/arch/arm/configs/at91sam9g45_defconfig +++ b/arch/arm/configs/at91sam9g45_defconfig | |||
@@ -18,7 +18,7 @@ CONFIG_MODULE_UNLOAD=y | |||
18 | CONFIG_ARCH_AT91=y | 18 | CONFIG_ARCH_AT91=y |
19 | CONFIG_ARCH_AT91SAM9G45=y | 19 | CONFIG_ARCH_AT91SAM9G45=y |
20 | CONFIG_MACH_AT91SAM9M10G45EK=y | 20 | CONFIG_MACH_AT91SAM9M10G45EK=y |
21 | CONFIG_MACH_AT91SAM_DT=y | 21 | CONFIG_MACH_AT91SAM9_DT=y |
22 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | 22 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y |
23 | CONFIG_AT91_SLOW_CLOCK=y | 23 | CONFIG_AT91_SLOW_CLOCK=y |
24 | CONFIG_AEABI=y | 24 | CONFIG_AEABI=y |
diff --git a/arch/arm/configs/h7201_defconfig b/arch/arm/configs/h7201_defconfig deleted file mode 100644 index bee94d29655e..000000000000 --- a/arch/arm/configs/h7201_defconfig +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | CONFIG_EXPERIMENTAL=y | ||
2 | CONFIG_SYSVIPC=y | ||
3 | CONFIG_LOG_BUF_SHIFT=14 | ||
4 | CONFIG_BLK_DEV_INITRD=y | ||
5 | CONFIG_MODULES=y | ||
6 | CONFIG_ARCH_H720X=y | ||
7 | CONFIG_ARCH_H7201=y | ||
8 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
9 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
10 | CONFIG_FPE_NWFPE=y | ||
11 | CONFIG_MTD=y | ||
12 | CONFIG_MTD_DEBUG=y | ||
13 | CONFIG_MTD_PARTITIONS=y | ||
14 | CONFIG_MTD_CHAR=y | ||
15 | CONFIG_MTD_BLOCK=y | ||
16 | CONFIG_MTD_CFI=y | ||
17 | CONFIG_MTD_CFI_ADV_OPTIONS=y | ||
18 | CONFIG_MTD_CFI_INTELEXT=y | ||
19 | CONFIG_BLK_DEV_RAM=y | ||
20 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
21 | # CONFIG_INPUT_KEYBOARD is not set | ||
22 | # CONFIG_INPUT_MOUSE is not set | ||
23 | # CONFIG_VGA_CONSOLE is not set | ||
24 | CONFIG_SOUND=m | ||
25 | CONFIG_EXT2_FS=y | ||
26 | CONFIG_JFFS2_FS=y | ||
27 | CONFIG_DEBUG_USER=y | ||
diff --git a/arch/arm/configs/h7202_defconfig b/arch/arm/configs/h7202_defconfig deleted file mode 100644 index e16d3f372e2a..000000000000 --- a/arch/arm/configs/h7202_defconfig +++ /dev/null | |||
@@ -1,47 +0,0 @@ | |||
1 | CONFIG_EXPERIMENTAL=y | ||
2 | CONFIG_SYSVIPC=y | ||
3 | CONFIG_LOG_BUF_SHIFT=14 | ||
4 | CONFIG_MODULES=y | ||
5 | CONFIG_ARCH_H720X=y | ||
6 | CONFIG_ARCH_H7202=y | ||
7 | # CONFIG_ARM_THUMB is not set | ||
8 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
9 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
10 | CONFIG_CMDLINE="console=ttyS0,19200" | ||
11 | CONFIG_FPE_NWFPE=y | ||
12 | CONFIG_FPE_NWFPE_XP=y | ||
13 | CONFIG_NET=y | ||
14 | CONFIG_UNIX=y | ||
15 | CONFIG_INET=y | ||
16 | CONFIG_IP_PNP=y | ||
17 | CONFIG_IP_PNP_BOOTP=y | ||
18 | # CONFIG_IPV6 is not set | ||
19 | CONFIG_MTD=y | ||
20 | CONFIG_MTD_PARTITIONS=y | ||
21 | CONFIG_MTD_CMDLINE_PARTS=y | ||
22 | CONFIG_MTD_CHAR=y | ||
23 | CONFIG_MTD_BLOCK=y | ||
24 | CONFIG_MTD_CFI=y | ||
25 | CONFIG_MTD_CFI_INTELEXT=y | ||
26 | CONFIG_MTD_H720X=y | ||
27 | CONFIG_NETDEVICES=y | ||
28 | CONFIG_NET_ETHERNET=y | ||
29 | CONFIG_SERIAL_8250=y | ||
30 | CONFIG_SERIAL_8250_CONSOLE=y | ||
31 | CONFIG_FB=y | ||
32 | CONFIG_FB_MODE_HELPERS=y | ||
33 | # CONFIG_VGA_CONSOLE is not set | ||
34 | CONFIG_USB_GADGET=m | ||
35 | CONFIG_USB_ZERO=m | ||
36 | CONFIG_USB_GADGETFS=m | ||
37 | CONFIG_USB_MASS_STORAGE=m | ||
38 | CONFIG_USB_G_SERIAL=m | ||
39 | CONFIG_EXT2_FS=y | ||
40 | CONFIG_TMPFS=y | ||
41 | CONFIG_JFFS2_FS=y | ||
42 | CONFIG_NFS_FS=y | ||
43 | CONFIG_NFS_V3=y | ||
44 | CONFIG_MAGIC_SYSRQ=y | ||
45 | CONFIG_DEBUG_KERNEL=y | ||
46 | CONFIG_DEBUG_INFO=y | ||
47 | CONFIG_DEBUG_USER=y | ||
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h index 35c21c375d81..53c15dec7af6 100644 --- a/arch/arm/include/asm/irq.h +++ b/arch/arm/include/asm/irq.h | |||
@@ -30,6 +30,11 @@ extern void asm_do_IRQ(unsigned int, struct pt_regs *); | |||
30 | void handle_IRQ(unsigned int, struct pt_regs *); | 30 | void handle_IRQ(unsigned int, struct pt_regs *); |
31 | void init_IRQ(void); | 31 | void init_IRQ(void); |
32 | 32 | ||
33 | #ifdef CONFIG_MULTI_IRQ_HANDLER | ||
34 | extern void (*handle_arch_irq)(struct pt_regs *); | ||
35 | extern void set_handle_irq(void (*handle_irq)(struct pt_regs *)); | ||
36 | #endif | ||
37 | |||
33 | #endif | 38 | #endif |
34 | 39 | ||
35 | #endif | 40 | #endif |
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h index 18c883023339..2092ee1e1300 100644 --- a/arch/arm/include/asm/mach/irq.h +++ b/arch/arm/include/asm/mach/irq.h | |||
@@ -20,11 +20,6 @@ struct seq_file; | |||
20 | extern void init_FIQ(int); | 20 | extern void init_FIQ(int); |
21 | extern int show_fiq_list(struct seq_file *, int); | 21 | extern int show_fiq_list(struct seq_file *, int); |
22 | 22 | ||
23 | #ifdef CONFIG_MULTI_IRQ_HANDLER | ||
24 | extern void (*handle_arch_irq)(struct pt_regs *); | ||
25 | extern void set_handle_irq(void (*handle_irq)(struct pt_regs *)); | ||
26 | #endif | ||
27 | |||
28 | /* | 23 | /* |
29 | * This is for easy migration, but should be changed in the source | 24 | * This is for easy migration, but should be changed in the source |
30 | */ | 25 | */ |
@@ -35,35 +30,4 @@ do { \ | |||
35 | raw_spin_unlock(&desc->lock); \ | 30 | raw_spin_unlock(&desc->lock); \ |
36 | } while(0) | 31 | } while(0) |
37 | 32 | ||
38 | #ifndef __ASSEMBLY__ | ||
39 | /* | ||
40 | * Entry/exit functions for chained handlers where the primary IRQ chip | ||
41 | * may implement either fasteoi or level-trigger flow control. | ||
42 | */ | ||
43 | static inline void chained_irq_enter(struct irq_chip *chip, | ||
44 | struct irq_desc *desc) | ||
45 | { | ||
46 | /* FastEOI controllers require no action on entry. */ | ||
47 | if (chip->irq_eoi) | ||
48 | return; | ||
49 | |||
50 | if (chip->irq_mask_ack) { | ||
51 | chip->irq_mask_ack(&desc->irq_data); | ||
52 | } else { | ||
53 | chip->irq_mask(&desc->irq_data); | ||
54 | if (chip->irq_ack) | ||
55 | chip->irq_ack(&desc->irq_data); | ||
56 | } | ||
57 | } | ||
58 | |||
59 | static inline void chained_irq_exit(struct irq_chip *chip, | ||
60 | struct irq_desc *desc) | ||
61 | { | ||
62 | if (chip->irq_eoi) | ||
63 | chip->irq_eoi(&desc->irq_data); | ||
64 | else | ||
65 | chip->irq_unmask(&desc->irq_data); | ||
66 | } | ||
67 | #endif | ||
68 | |||
69 | #endif | 33 | #endif |
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h index 0f01f4677bd2..7b2899c2f7fc 100644 --- a/arch/arm/include/asm/smp_twd.h +++ b/arch/arm/include/asm/smp_twd.h | |||
@@ -34,12 +34,4 @@ struct twd_local_timer name __initdata = { \ | |||
34 | 34 | ||
35 | int twd_local_timer_register(struct twd_local_timer *); | 35 | int twd_local_timer_register(struct twd_local_timer *); |
36 | 36 | ||
37 | #ifdef CONFIG_HAVE_ARM_TWD | ||
38 | void twd_local_timer_of_register(void); | ||
39 | #else | ||
40 | static inline void twd_local_timer_of_register(void) | ||
41 | { | ||
42 | } | ||
43 | #endif | ||
44 | |||
45 | #endif | 37 | #endif |
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 8e4ef4c83a74..9723d17b8f38 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <linux/ioport.h> | 26 | #include <linux/ioport.h> |
27 | #include <linux/interrupt.h> | 27 | #include <linux/interrupt.h> |
28 | #include <linux/irq.h> | 28 | #include <linux/irq.h> |
29 | #include <linux/irqchip.h> | ||
29 | #include <linux/random.h> | 30 | #include <linux/random.h> |
30 | #include <linux/smp.h> | 31 | #include <linux/smp.h> |
31 | #include <linux/init.h> | 32 | #include <linux/init.h> |
@@ -114,7 +115,10 @@ EXPORT_SYMBOL_GPL(set_irq_flags); | |||
114 | 115 | ||
115 | void __init init_IRQ(void) | 116 | void __init init_IRQ(void) |
116 | { | 117 | { |
117 | machine_desc->init_irq(); | 118 | if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq) |
119 | irqchip_init(); | ||
120 | else | ||
121 | machine_desc->init_irq(); | ||
118 | } | 122 | } |
119 | 123 | ||
120 | #ifdef CONFIG_MULTI_IRQ_HANDLER | 124 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 3f2565037480..90525d9d290b 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c | |||
@@ -362,25 +362,13 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt) | |||
362 | } | 362 | } |
363 | 363 | ||
364 | #ifdef CONFIG_OF | 364 | #ifdef CONFIG_OF |
365 | const static struct of_device_id twd_of_match[] __initconst = { | 365 | static void __init twd_local_timer_of_register(struct device_node *np) |
366 | { .compatible = "arm,cortex-a9-twd-timer", }, | ||
367 | { .compatible = "arm,cortex-a5-twd-timer", }, | ||
368 | { .compatible = "arm,arm11mp-twd-timer", }, | ||
369 | { }, | ||
370 | }; | ||
371 | |||
372 | void __init twd_local_timer_of_register(void) | ||
373 | { | 366 | { |
374 | struct device_node *np; | ||
375 | int err; | 367 | int err; |
376 | 368 | ||
377 | if (!is_smp() || !setup_max_cpus) | 369 | if (!is_smp() || !setup_max_cpus) |
378 | return; | 370 | return; |
379 | 371 | ||
380 | np = of_find_matching_node(NULL, twd_of_match); | ||
381 | if (!np) | ||
382 | return; | ||
383 | |||
384 | twd_ppi = irq_of_parse_and_map(np, 0); | 372 | twd_ppi = irq_of_parse_and_map(np, 0); |
385 | if (!twd_ppi) { | 373 | if (!twd_ppi) { |
386 | err = -EINVAL; | 374 | err = -EINVAL; |
@@ -398,4 +386,7 @@ void __init twd_local_timer_of_register(void) | |||
398 | out: | 386 | out: |
399 | WARN(err, "twd_local_timer_of_register failed (%d)\n", err); | 387 | WARN(err, "twd_local_timer_of_register failed (%d)\n", err); |
400 | } | 388 | } |
389 | CLOCKSOURCE_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register); | ||
390 | CLOCKSOURCE_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register); | ||
391 | CLOCKSOURCE_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register); | ||
401 | #endif | 392 | #endif |
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 6071f4c3d654..440682b708f3 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig | |||
@@ -1,8 +1,5 @@ | |||
1 | if ARCH_AT91 | 1 | if ARCH_AT91 |
2 | 2 | ||
3 | config HAVE_AT91_DATAFLASH_CARD | ||
4 | bool | ||
5 | |||
6 | config HAVE_AT91_DBGU0 | 3 | config HAVE_AT91_DBGU0 |
7 | bool | 4 | bool |
8 | 5 | ||
@@ -93,394 +90,13 @@ config SOC_AT91SAM9N12 | |||
93 | help | 90 | help |
94 | Select this if you are using Atmel's AT91SAM9N12 SoC. | 91 | Select this if you are using Atmel's AT91SAM9N12 SoC. |
95 | 92 | ||
96 | choice | ||
97 | prompt "Atmel AT91 Processor Devices for non DT boards" | ||
98 | |||
99 | config ARCH_AT91_NONE | ||
100 | bool "None" | ||
101 | |||
102 | config ARCH_AT91RM9200 | ||
103 | bool "AT91RM9200" | ||
104 | select SOC_AT91RM9200 | ||
105 | |||
106 | config ARCH_AT91SAM9260 | ||
107 | bool "AT91SAM9260 or AT91SAM9XE" | ||
108 | select SOC_AT91SAM9260 | ||
109 | |||
110 | config ARCH_AT91SAM9261 | ||
111 | bool "AT91SAM9261" | ||
112 | select SOC_AT91SAM9261 | ||
113 | |||
114 | config ARCH_AT91SAM9G10 | ||
115 | bool "AT91SAM9G10" | ||
116 | select SOC_AT91SAM9261 | ||
117 | |||
118 | config ARCH_AT91SAM9263 | ||
119 | bool "AT91SAM9263" | ||
120 | select SOC_AT91SAM9263 | ||
121 | |||
122 | config ARCH_AT91SAM9RL | ||
123 | bool "AT91SAM9RL" | ||
124 | select SOC_AT91SAM9RL | ||
125 | |||
126 | config ARCH_AT91SAM9G20 | ||
127 | bool "AT91SAM9G20" | ||
128 | select SOC_AT91SAM9260 | ||
129 | |||
130 | config ARCH_AT91SAM9G45 | ||
131 | bool "AT91SAM9G45" | ||
132 | select SOC_AT91SAM9G45 | ||
133 | |||
134 | config ARCH_AT91X40 | ||
135 | bool "AT91x40" | ||
136 | depends on !MMU | ||
137 | select ARCH_USES_GETTIMEOFFSET | ||
138 | select MULTI_IRQ_HANDLER | ||
139 | select SPARSE_IRQ | ||
140 | |||
141 | endchoice | ||
142 | |||
143 | config AT91_PMC_UNIT | 93 | config AT91_PMC_UNIT |
144 | bool | 94 | bool |
145 | default !ARCH_AT91X40 | 95 | default !ARCH_AT91X40 |
146 | 96 | ||
147 | # ---------------------------------------------------------- | 97 | # ---------------------------------------------------------- |
148 | 98 | ||
149 | if ARCH_AT91RM9200 | 99 | source arch/arm/mach-at91/Kconfig.non_dt |
150 | |||
151 | comment "AT91RM9200 Board Type" | ||
152 | |||
153 | config MACH_ONEARM | ||
154 | bool "Ajeco 1ARM Single Board Computer" | ||
155 | help | ||
156 | Select this if you are using Ajeco's 1ARM Single Board Computer. | ||
157 | <http://www.ajeco.fi/> | ||
158 | |||
159 | config ARCH_AT91RM9200DK | ||
160 | bool "Atmel AT91RM9200-DK Development board" | ||
161 | select HAVE_AT91_DATAFLASH_CARD | ||
162 | help | ||
163 | Select this if you are using Atmel's AT91RM9200-DK Development board. | ||
164 | (Discontinued) | ||
165 | |||
166 | config MACH_AT91RM9200EK | ||
167 | bool "Atmel AT91RM9200-EK Evaluation Kit" | ||
168 | select HAVE_AT91_DATAFLASH_CARD | ||
169 | help | ||
170 | Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit. | ||
171 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507> | ||
172 | |||
173 | config MACH_CSB337 | ||
174 | bool "Cogent CSB337" | ||
175 | help | ||
176 | Select this if you are using Cogent's CSB337 board. | ||
177 | <http://www.cogcomp.com/csb_csb337.htm> | ||
178 | |||
179 | config MACH_CSB637 | ||
180 | bool "Cogent CSB637" | ||
181 | help | ||
182 | Select this if you are using Cogent's CSB637 board. | ||
183 | <http://www.cogcomp.com/csb_csb637.htm> | ||
184 | |||
185 | config MACH_CARMEVA | ||
186 | bool "Conitec ARM&EVA" | ||
187 | help | ||
188 | Select this if you are using Conitec's AT91RM9200-MCU-Module. | ||
189 | <http://www.conitec.net/english/linuxboard.php> | ||
190 | |||
191 | config MACH_ATEB9200 | ||
192 | bool "Embest ATEB9200" | ||
193 | help | ||
194 | Select this if you are using Embest's ATEB9200 board. | ||
195 | <http://www.embedinfo.com/english/product/ATEB9200.asp> | ||
196 | |||
197 | config MACH_KB9200 | ||
198 | bool "KwikByte KB920x" | ||
199 | help | ||
200 | Select this if you are using KwikByte's KB920x board. | ||
201 | <http://www.kwikbyte.com/KB9202.html> | ||
202 | |||
203 | config MACH_PICOTUX2XX | ||
204 | bool "picotux 200" | ||
205 | help | ||
206 | Select this if you are using a picotux 200. | ||
207 | <http://www.picotux.com/> | ||
208 | |||
209 | config MACH_KAFA | ||
210 | bool "Sperry-Sun KAFA board" | ||
211 | help | ||
212 | Select this if you are using Sperry-Sun's KAFA board. | ||
213 | |||
214 | config MACH_ECBAT91 | ||
215 | bool "emQbit ECB_AT91 SBC" | ||
216 | select HAVE_AT91_DATAFLASH_CARD | ||
217 | help | ||
218 | Select this if you are using emQbit's ECB_AT91 board. | ||
219 | <http://wiki.emqbit.com/free-ecb-at91> | ||
220 | |||
221 | config MACH_YL9200 | ||
222 | bool "ucDragon YL-9200" | ||
223 | help | ||
224 | Select this if you are using the ucDragon YL-9200 board. | ||
225 | |||
226 | config MACH_CPUAT91 | ||
227 | bool "Eukrea CPUAT91" | ||
228 | help | ||
229 | Select this if you are using the Eukrea Electromatique's | ||
230 | CPUAT91 board <http://www.eukrea.com/>. | ||
231 | |||
232 | config MACH_ECO920 | ||
233 | bool "eco920" | ||
234 | help | ||
235 | Select this if you are using the eco920 board | ||
236 | |||
237 | config MACH_RSI_EWS | ||
238 | bool "RSI Embedded Webserver" | ||
239 | depends on ARCH_AT91RM9200 | ||
240 | help | ||
241 | Select this if you are using RSIs EWS board. | ||
242 | endif | ||
243 | |||
244 | # ---------------------------------------------------------- | ||
245 | |||
246 | if ARCH_AT91SAM9260 | ||
247 | |||
248 | comment "AT91SAM9260 Variants" | ||
249 | |||
250 | comment "AT91SAM9260 / AT91SAM9XE Board Type" | ||
251 | |||
252 | config MACH_AT91SAM9260EK | ||
253 | bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit" | ||
254 | select HAVE_AT91_DATAFLASH_CARD | ||
255 | help | ||
256 | Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit | ||
257 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933> | ||
258 | |||
259 | config MACH_CAM60 | ||
260 | bool "KwikByte KB9260 (CAM60) board" | ||
261 | help | ||
262 | Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260. | ||
263 | <http://www.kwikbyte.com/KB9260.html> | ||
264 | |||
265 | config MACH_SAM9_L9260 | ||
266 | bool "Olimex SAM9-L9260 board" | ||
267 | select HAVE_AT91_DATAFLASH_CARD | ||
268 | help | ||
269 | Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260. | ||
270 | <http://www.olimex.com/dev/sam9-L9260.html> | ||
271 | |||
272 | config MACH_AFEB9260 | ||
273 | bool "Custom afeb9260 board v1" | ||
274 | help | ||
275 | Select this if you are using custom afeb9260 board based on | ||
276 | open hardware design. Select this for revision 1 of the board. | ||
277 | <svn://194.85.238.22/home/users/george/svn/arm9eb> | ||
278 | <http://groups.google.com/group/arm9fpga-evolution-board> | ||
279 | |||
280 | config MACH_USB_A9260 | ||
281 | bool "CALAO USB-A9260" | ||
282 | help | ||
283 | Select this if you are using a Calao Systems USB-A9260. | ||
284 | <http://www.calao-systems.com> | ||
285 | |||
286 | config MACH_QIL_A9260 | ||
287 | bool "CALAO QIL-A9260 board" | ||
288 | help | ||
289 | Select this if you are using a Calao Systems QIL-A9260 Board. | ||
290 | <http://www.calao-systems.com> | ||
291 | |||
292 | config MACH_CPU9260 | ||
293 | bool "Eukrea CPU9260 board" | ||
294 | help | ||
295 | Select this if you are using a Eukrea Electromatique's | ||
296 | CPU9260 Board <http://www.eukrea.com/> | ||
297 | |||
298 | config MACH_FLEXIBITY | ||
299 | bool "Flexibity Connect board" | ||
300 | help | ||
301 | Select this if you are using Flexibity Connect board | ||
302 | <http://www.flexibity.com> | ||
303 | |||
304 | endif | ||
305 | |||
306 | # ---------------------------------------------------------- | ||
307 | |||
308 | if ARCH_AT91SAM9261 | ||
309 | |||
310 | comment "AT91SAM9261 Board Type" | ||
311 | |||
312 | config MACH_AT91SAM9261EK | ||
313 | bool "Atmel AT91SAM9261-EK Evaluation Kit" | ||
314 | select HAVE_AT91_DATAFLASH_CARD | ||
315 | help | ||
316 | Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. | ||
317 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820> | ||
318 | |||
319 | endif | ||
320 | |||
321 | # ---------------------------------------------------------- | ||
322 | |||
323 | if ARCH_AT91SAM9G10 | ||
324 | |||
325 | comment "AT91SAM9G10 Board Type" | ||
326 | |||
327 | config MACH_AT91SAM9G10EK | ||
328 | bool "Atmel AT91SAM9G10-EK Evaluation Kit" | ||
329 | select HAVE_AT91_DATAFLASH_CARD | ||
330 | help | ||
331 | Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. | ||
332 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588> | ||
333 | |||
334 | endif | ||
335 | |||
336 | # ---------------------------------------------------------- | ||
337 | |||
338 | if ARCH_AT91SAM9263 | ||
339 | |||
340 | comment "AT91SAM9263 Board Type" | ||
341 | |||
342 | config MACH_AT91SAM9263EK | ||
343 | bool "Atmel AT91SAM9263-EK Evaluation Kit" | ||
344 | select HAVE_AT91_DATAFLASH_CARD | ||
345 | help | ||
346 | Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. | ||
347 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057> | ||
348 | |||
349 | config MACH_USB_A9263 | ||
350 | bool "CALAO USB-A9263" | ||
351 | help | ||
352 | Select this if you are using a Calao Systems USB-A9263. | ||
353 | <http://www.calao-systems.com> | ||
354 | |||
355 | endif | ||
356 | |||
357 | # ---------------------------------------------------------- | ||
358 | |||
359 | if ARCH_AT91SAM9RL | ||
360 | |||
361 | comment "AT91SAM9RL Board Type" | ||
362 | |||
363 | config MACH_AT91SAM9RLEK | ||
364 | bool "Atmel AT91SAM9RL-EK Evaluation Kit" | ||
365 | help | ||
366 | Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit. | ||
367 | |||
368 | endif | ||
369 | |||
370 | # ---------------------------------------------------------- | ||
371 | |||
372 | if ARCH_AT91SAM9G20 | ||
373 | |||
374 | comment "AT91SAM9G20 Board Type" | ||
375 | |||
376 | config MACH_AT91SAM9G20EK | ||
377 | bool "Atmel AT91SAM9G20-EK Evaluation Kit" | ||
378 | select HAVE_AT91_DATAFLASH_CARD | ||
379 | help | ||
380 | Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit | ||
381 | that embeds only one SD/MMC slot. | ||
382 | |||
383 | config MACH_AT91SAM9G20EK_2MMC | ||
384 | depends on MACH_AT91SAM9G20EK | ||
385 | bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots" | ||
386 | help | ||
387 | Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit | ||
388 | with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and | ||
389 | onwards. | ||
390 | <http://www.atmel.com/tools/SAM9G20-EK.aspx> | ||
391 | |||
392 | config MACH_CPU9G20 | ||
393 | bool "Eukrea CPU9G20 board" | ||
394 | help | ||
395 | Select this if you are using a Eukrea Electromatique's | ||
396 | CPU9G20 Board <http://www.eukrea.com/> | ||
397 | |||
398 | config MACH_ACMENETUSFOXG20 | ||
399 | bool "Acme Systems srl FOX Board G20" | ||
400 | help | ||
401 | Select this if you are using Acme Systems | ||
402 | FOX Board G20 <http://www.acmesystems.it> | ||
403 | |||
404 | config MACH_PORTUXG20 | ||
405 | bool "taskit PortuxG20" | ||
406 | help | ||
407 | Select this if you are using taskit's PortuxG20. | ||
408 | <http://www.taskit.de/en/> | ||
409 | |||
410 | config MACH_STAMP9G20 | ||
411 | bool "taskit Stamp9G20 CPU module" | ||
412 | help | ||
413 | Select this if you are using taskit's Stamp9G20 CPU module on its | ||
414 | evaluation board. | ||
415 | <http://www.taskit.de/en/> | ||
416 | |||
417 | config MACH_PCONTROL_G20 | ||
418 | bool "PControl G20 CPU module" | ||
419 | help | ||
420 | Select this if you are using taskit's Stamp9G20 CPU module on this | ||
421 | carrier board, beeing the decentralized unit of a building automation | ||
422 | system; featuring nvram, eth-switch, iso-rs485, display, io | ||
423 | |||
424 | config MACH_GSIA18S | ||
425 | bool "GS_IA18_S board" | ||
426 | help | ||
427 | This enables support for the GS_IA18_S board | ||
428 | produced by GeoSIG Ltd company. This is an internet accelerograph. | ||
429 | <http://www.geosig.com> | ||
430 | |||
431 | config MACH_USB_A9G20 | ||
432 | bool "CALAO USB-A9G20" | ||
433 | depends on ARCH_AT91SAM9G20 | ||
434 | help | ||
435 | Select this if you are using a Calao Systems USB-A9G20. | ||
436 | <http://www.calao-systems.com> | ||
437 | |||
438 | endif | ||
439 | |||
440 | if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) | ||
441 | comment "AT91SAM9260/AT91SAM9G20 boards" | ||
442 | |||
443 | config MACH_SNAPPER_9260 | ||
444 | bool "Bluewater Systems Snapper 9260/9G20 module" | ||
445 | help | ||
446 | Select this if you are using the Bluewater Systems Snapper 9260 or | ||
447 | Snapper 9G20 modules. | ||
448 | <http://www.bluewatersys.com/> | ||
449 | endif | ||
450 | |||
451 | # ---------------------------------------------------------- | ||
452 | |||
453 | if ARCH_AT91SAM9G45 | ||
454 | |||
455 | comment "AT91SAM9G45 Board Type" | ||
456 | |||
457 | config MACH_AT91SAM9M10G45EK | ||
458 | bool "Atmel AT91SAM9M10G45-EK Evaluation Kits" | ||
459 | help | ||
460 | Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit. | ||
461 | Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10 | ||
462 | families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. | ||
463 | <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx> | ||
464 | |||
465 | endif | ||
466 | |||
467 | # ---------------------------------------------------------- | ||
468 | |||
469 | if ARCH_AT91X40 | ||
470 | |||
471 | comment "AT91X40 Board Type" | ||
472 | |||
473 | config MACH_AT91EB01 | ||
474 | bool "Atmel AT91EB01 Evaluation Kit" | ||
475 | help | ||
476 | Select this if you are using Atmel's AT91EB01 Evaluation Kit. | ||
477 | It is also a popular target for simulators such as GDB's | ||
478 | ARM simulator (commonly known as the ARMulator) and the | ||
479 | Skyeye simulator. | ||
480 | |||
481 | endif | ||
482 | |||
483 | # ---------------------------------------------------------- | ||
484 | 100 | ||
485 | comment "Generic Board Type" | 101 | comment "Generic Board Type" |
486 | 102 | ||
@@ -492,7 +108,7 @@ config MACH_AT91RM9200_DT | |||
492 | Select this if you want to experiment device-tree with | 108 | Select this if you want to experiment device-tree with |
493 | an Atmel RM9200 Evaluation Kit. | 109 | an Atmel RM9200 Evaluation Kit. |
494 | 110 | ||
495 | config MACH_AT91SAM_DT | 111 | config MACH_AT91SAM9_DT |
496 | bool "Atmel AT91SAM Evaluation Kits with device-tree support" | 112 | bool "Atmel AT91SAM Evaluation Kits with device-tree support" |
497 | depends on SOC_AT91SAM9 | 113 | depends on SOC_AT91SAM9 |
498 | select USE_OF | 114 | select USE_OF |
@@ -502,16 +118,6 @@ config MACH_AT91SAM_DT | |||
502 | 118 | ||
503 | # ---------------------------------------------------------- | 119 | # ---------------------------------------------------------- |
504 | 120 | ||
505 | comment "AT91 Board Options" | ||
506 | |||
507 | config MTD_AT91_DATAFLASH_CARD | ||
508 | bool "Enable DataFlash Card support" | ||
509 | depends on HAVE_AT91_DATAFLASH_CARD | ||
510 | help | ||
511 | Enable support for the DataFlash card. | ||
512 | |||
513 | # ---------------------------------------------------------- | ||
514 | |||
515 | comment "AT91 Feature Selections" | 121 | comment "AT91 Feature Selections" |
516 | 122 | ||
517 | config AT91_PROGRAMMABLE_CLOCKS | 123 | config AT91_PROGRAMMABLE_CLOCKS |
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt new file mode 100644 index 000000000000..6c24985515a2 --- /dev/null +++ b/arch/arm/mach-at91/Kconfig.non_dt | |||
@@ -0,0 +1,399 @@ | |||
1 | menu "Atmel Non-DT world" | ||
2 | |||
3 | config HAVE_AT91_DATAFLASH_CARD | ||
4 | bool | ||
5 | |||
6 | choice | ||
7 | prompt "Atmel AT91 Processor Devices for non DT boards" | ||
8 | |||
9 | config ARCH_AT91_NONE | ||
10 | bool "None" | ||
11 | |||
12 | config ARCH_AT91RM9200 | ||
13 | bool "AT91RM9200" | ||
14 | select SOC_AT91RM9200 | ||
15 | |||
16 | config ARCH_AT91SAM9260 | ||
17 | bool "AT91SAM9260 or AT91SAM9XE" | ||
18 | select SOC_AT91SAM9260 | ||
19 | |||
20 | config ARCH_AT91SAM9261 | ||
21 | bool "AT91SAM9261" | ||
22 | select SOC_AT91SAM9261 | ||
23 | |||
24 | config ARCH_AT91SAM9G10 | ||
25 | bool "AT91SAM9G10" | ||
26 | select SOC_AT91SAM9261 | ||
27 | |||
28 | config ARCH_AT91SAM9263 | ||
29 | bool "AT91SAM9263" | ||
30 | select SOC_AT91SAM9263 | ||
31 | |||
32 | config ARCH_AT91SAM9RL | ||
33 | bool "AT91SAM9RL" | ||
34 | select SOC_AT91SAM9RL | ||
35 | |||
36 | config ARCH_AT91SAM9G20 | ||
37 | bool "AT91SAM9G20" | ||
38 | select SOC_AT91SAM9260 | ||
39 | |||
40 | config ARCH_AT91SAM9G45 | ||
41 | bool "AT91SAM9G45" | ||
42 | select SOC_AT91SAM9G45 | ||
43 | |||
44 | config ARCH_AT91X40 | ||
45 | bool "AT91x40" | ||
46 | depends on !MMU | ||
47 | select ARCH_USES_GETTIMEOFFSET | ||
48 | select MULTI_IRQ_HANDLER | ||
49 | select SPARSE_IRQ | ||
50 | |||
51 | endchoice | ||
52 | |||
53 | # ---------------------------------------------------------- | ||
54 | |||
55 | if ARCH_AT91RM9200 | ||
56 | |||
57 | comment "AT91RM9200 Board Type" | ||
58 | |||
59 | config MACH_ONEARM | ||
60 | bool "Ajeco 1ARM Single Board Computer" | ||
61 | help | ||
62 | Select this if you are using Ajeco's 1ARM Single Board Computer. | ||
63 | <http://www.ajeco.fi/> | ||
64 | |||
65 | config ARCH_AT91RM9200DK | ||
66 | bool "Atmel AT91RM9200-DK Development board" | ||
67 | select HAVE_AT91_DATAFLASH_CARD | ||
68 | help | ||
69 | Select this if you are using Atmel's AT91RM9200-DK Development board. | ||
70 | (Discontinued) | ||
71 | |||
72 | config MACH_AT91RM9200EK | ||
73 | bool "Atmel AT91RM9200-EK Evaluation Kit" | ||
74 | select HAVE_AT91_DATAFLASH_CARD | ||
75 | help | ||
76 | Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit. | ||
77 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507> | ||
78 | |||
79 | config MACH_CSB337 | ||
80 | bool "Cogent CSB337" | ||
81 | help | ||
82 | Select this if you are using Cogent's CSB337 board. | ||
83 | <http://www.cogcomp.com/csb_csb337.htm> | ||
84 | |||
85 | config MACH_CSB637 | ||
86 | bool "Cogent CSB637" | ||
87 | help | ||
88 | Select this if you are using Cogent's CSB637 board. | ||
89 | <http://www.cogcomp.com/csb_csb637.htm> | ||
90 | |||
91 | config MACH_CARMEVA | ||
92 | bool "Conitec ARM&EVA" | ||
93 | help | ||
94 | Select this if you are using Conitec's AT91RM9200-MCU-Module. | ||
95 | <http://www.conitec.net/english/linuxboard.php> | ||
96 | |||
97 | config MACH_ATEB9200 | ||
98 | bool "Embest ATEB9200" | ||
99 | help | ||
100 | Select this if you are using Embest's ATEB9200 board. | ||
101 | <http://www.embedinfo.com/english/product/ATEB9200.asp> | ||
102 | |||
103 | config MACH_KB9200 | ||
104 | bool "KwikByte KB920x" | ||
105 | help | ||
106 | Select this if you are using KwikByte's KB920x board. | ||
107 | <http://www.kwikbyte.com/KB9202.html> | ||
108 | |||
109 | config MACH_PICOTUX2XX | ||
110 | bool "picotux 200" | ||
111 | help | ||
112 | Select this if you are using a picotux 200. | ||
113 | <http://www.picotux.com/> | ||
114 | |||
115 | config MACH_KAFA | ||
116 | bool "Sperry-Sun KAFA board" | ||
117 | help | ||
118 | Select this if you are using Sperry-Sun's KAFA board. | ||
119 | |||
120 | config MACH_ECBAT91 | ||
121 | bool "emQbit ECB_AT91 SBC" | ||
122 | select HAVE_AT91_DATAFLASH_CARD | ||
123 | help | ||
124 | Select this if you are using emQbit's ECB_AT91 board. | ||
125 | <http://wiki.emqbit.com/free-ecb-at91> | ||
126 | |||
127 | config MACH_YL9200 | ||
128 | bool "ucDragon YL-9200" | ||
129 | help | ||
130 | Select this if you are using the ucDragon YL-9200 board. | ||
131 | |||
132 | config MACH_CPUAT91 | ||
133 | bool "Eukrea CPUAT91" | ||
134 | help | ||
135 | Select this if you are using the Eukrea Electromatique's | ||
136 | CPUAT91 board <http://www.eukrea.com/>. | ||
137 | |||
138 | config MACH_ECO920 | ||
139 | bool "eco920" | ||
140 | help | ||
141 | Select this if you are using the eco920 board | ||
142 | |||
143 | config MACH_RSI_EWS | ||
144 | bool "RSI Embedded Webserver" | ||
145 | depends on ARCH_AT91RM9200 | ||
146 | help | ||
147 | Select this if you are using RSIs EWS board. | ||
148 | endif | ||
149 | |||
150 | # ---------------------------------------------------------- | ||
151 | |||
152 | if ARCH_AT91SAM9260 | ||
153 | |||
154 | comment "AT91SAM9260 Variants" | ||
155 | |||
156 | comment "AT91SAM9260 / AT91SAM9XE Board Type" | ||
157 | |||
158 | config MACH_AT91SAM9260EK | ||
159 | bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit" | ||
160 | select HAVE_AT91_DATAFLASH_CARD | ||
161 | help | ||
162 | Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit | ||
163 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933> | ||
164 | |||
165 | config MACH_CAM60 | ||
166 | bool "KwikByte KB9260 (CAM60) board" | ||
167 | help | ||
168 | Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260. | ||
169 | <http://www.kwikbyte.com/KB9260.html> | ||
170 | |||
171 | config MACH_SAM9_L9260 | ||
172 | bool "Olimex SAM9-L9260 board" | ||
173 | select HAVE_AT91_DATAFLASH_CARD | ||
174 | help | ||
175 | Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260. | ||
176 | <http://www.olimex.com/dev/sam9-L9260.html> | ||
177 | |||
178 | config MACH_AFEB9260 | ||
179 | bool "Custom afeb9260 board v1" | ||
180 | help | ||
181 | Select this if you are using custom afeb9260 board based on | ||
182 | open hardware design. Select this for revision 1 of the board. | ||
183 | <svn://194.85.238.22/home/users/george/svn/arm9eb> | ||
184 | <http://groups.google.com/group/arm9fpga-evolution-board> | ||
185 | |||
186 | config MACH_USB_A9260 | ||
187 | bool "CALAO USB-A9260" | ||
188 | help | ||
189 | Select this if you are using a Calao Systems USB-A9260. | ||
190 | <http://www.calao-systems.com> | ||
191 | |||
192 | config MACH_QIL_A9260 | ||
193 | bool "CALAO QIL-A9260 board" | ||
194 | help | ||
195 | Select this if you are using a Calao Systems QIL-A9260 Board. | ||
196 | <http://www.calao-systems.com> | ||
197 | |||
198 | config MACH_CPU9260 | ||
199 | bool "Eukrea CPU9260 board" | ||
200 | help | ||
201 | Select this if you are using a Eukrea Electromatique's | ||
202 | CPU9260 Board <http://www.eukrea.com/> | ||
203 | |||
204 | config MACH_FLEXIBITY | ||
205 | bool "Flexibity Connect board" | ||
206 | help | ||
207 | Select this if you are using Flexibity Connect board | ||
208 | <http://www.flexibity.com> | ||
209 | |||
210 | endif | ||
211 | |||
212 | # ---------------------------------------------------------- | ||
213 | |||
214 | if ARCH_AT91SAM9261 | ||
215 | |||
216 | comment "AT91SAM9261 Board Type" | ||
217 | |||
218 | config MACH_AT91SAM9261EK | ||
219 | bool "Atmel AT91SAM9261-EK Evaluation Kit" | ||
220 | select HAVE_AT91_DATAFLASH_CARD | ||
221 | help | ||
222 | Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. | ||
223 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820> | ||
224 | |||
225 | endif | ||
226 | |||
227 | # ---------------------------------------------------------- | ||
228 | |||
229 | if ARCH_AT91SAM9G10 | ||
230 | |||
231 | comment "AT91SAM9G10 Board Type" | ||
232 | |||
233 | config MACH_AT91SAM9G10EK | ||
234 | bool "Atmel AT91SAM9G10-EK Evaluation Kit" | ||
235 | select HAVE_AT91_DATAFLASH_CARD | ||
236 | help | ||
237 | Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. | ||
238 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588> | ||
239 | |||
240 | endif | ||
241 | |||
242 | # ---------------------------------------------------------- | ||
243 | |||
244 | if ARCH_AT91SAM9263 | ||
245 | |||
246 | comment "AT91SAM9263 Board Type" | ||
247 | |||
248 | config MACH_AT91SAM9263EK | ||
249 | bool "Atmel AT91SAM9263-EK Evaluation Kit" | ||
250 | select HAVE_AT91_DATAFLASH_CARD | ||
251 | help | ||
252 | Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. | ||
253 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057> | ||
254 | |||
255 | config MACH_USB_A9263 | ||
256 | bool "CALAO USB-A9263" | ||
257 | help | ||
258 | Select this if you are using a Calao Systems USB-A9263. | ||
259 | <http://www.calao-systems.com> | ||
260 | |||
261 | endif | ||
262 | |||
263 | # ---------------------------------------------------------- | ||
264 | |||
265 | if ARCH_AT91SAM9RL | ||
266 | |||
267 | comment "AT91SAM9RL Board Type" | ||
268 | |||
269 | config MACH_AT91SAM9RLEK | ||
270 | bool "Atmel AT91SAM9RL-EK Evaluation Kit" | ||
271 | help | ||
272 | Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit. | ||
273 | |||
274 | endif | ||
275 | |||
276 | # ---------------------------------------------------------- | ||
277 | |||
278 | if ARCH_AT91SAM9G20 | ||
279 | |||
280 | comment "AT91SAM9G20 Board Type" | ||
281 | |||
282 | config MACH_AT91SAM9G20EK | ||
283 | bool "Atmel AT91SAM9G20-EK Evaluation Kit" | ||
284 | select HAVE_AT91_DATAFLASH_CARD | ||
285 | help | ||
286 | Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit | ||
287 | that embeds only one SD/MMC slot. | ||
288 | |||
289 | config MACH_AT91SAM9G20EK_2MMC | ||
290 | depends on MACH_AT91SAM9G20EK | ||
291 | bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots" | ||
292 | help | ||
293 | Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit | ||
294 | with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and | ||
295 | onwards. | ||
296 | <http://www.atmel.com/tools/SAM9G20-EK.aspx> | ||
297 | |||
298 | config MACH_CPU9G20 | ||
299 | bool "Eukrea CPU9G20 board" | ||
300 | help | ||
301 | Select this if you are using a Eukrea Electromatique's | ||
302 | CPU9G20 Board <http://www.eukrea.com/> | ||
303 | |||
304 | config MACH_ACMENETUSFOXG20 | ||
305 | bool "Acme Systems srl FOX Board G20" | ||
306 | help | ||
307 | Select this if you are using Acme Systems | ||
308 | FOX Board G20 <http://www.acmesystems.it> | ||
309 | |||
310 | config MACH_PORTUXG20 | ||
311 | bool "taskit PortuxG20" | ||
312 | help | ||
313 | Select this if you are using taskit's PortuxG20. | ||
314 | <http://www.taskit.de/en/> | ||
315 | |||
316 | config MACH_STAMP9G20 | ||
317 | bool "taskit Stamp9G20 CPU module" | ||
318 | help | ||
319 | Select this if you are using taskit's Stamp9G20 CPU module on its | ||
320 | evaluation board. | ||
321 | <http://www.taskit.de/en/> | ||
322 | |||
323 | config MACH_PCONTROL_G20 | ||
324 | bool "PControl G20 CPU module" | ||
325 | help | ||
326 | Select this if you are using taskit's Stamp9G20 CPU module on this | ||
327 | carrier board, beeing the decentralized unit of a building automation | ||
328 | system; featuring nvram, eth-switch, iso-rs485, display, io | ||
329 | |||
330 | config MACH_GSIA18S | ||
331 | bool "GS_IA18_S board" | ||
332 | help | ||
333 | This enables support for the GS_IA18_S board | ||
334 | produced by GeoSIG Ltd company. This is an internet accelerograph. | ||
335 | <http://www.geosig.com> | ||
336 | |||
337 | config MACH_USB_A9G20 | ||
338 | bool "CALAO USB-A9G20" | ||
339 | depends on ARCH_AT91SAM9G20 | ||
340 | help | ||
341 | Select this if you are using a Calao Systems USB-A9G20. | ||
342 | <http://www.calao-systems.com> | ||
343 | |||
344 | endif | ||
345 | |||
346 | if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) | ||
347 | comment "AT91SAM9260/AT91SAM9G20 boards" | ||
348 | |||
349 | config MACH_SNAPPER_9260 | ||
350 | bool "Bluewater Systems Snapper 9260/9G20 module" | ||
351 | help | ||
352 | Select this if you are using the Bluewater Systems Snapper 9260 or | ||
353 | Snapper 9G20 modules. | ||
354 | <http://www.bluewatersys.com/> | ||
355 | endif | ||
356 | |||
357 | # ---------------------------------------------------------- | ||
358 | |||
359 | if ARCH_AT91SAM9G45 | ||
360 | |||
361 | comment "AT91SAM9G45 Board Type" | ||
362 | |||
363 | config MACH_AT91SAM9M10G45EK | ||
364 | bool "Atmel AT91SAM9M10G45-EK Evaluation Kits" | ||
365 | help | ||
366 | Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit. | ||
367 | Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10 | ||
368 | families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. | ||
369 | <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx> | ||
370 | |||
371 | endif | ||
372 | |||
373 | # ---------------------------------------------------------- | ||
374 | |||
375 | if ARCH_AT91X40 | ||
376 | |||
377 | comment "AT91X40 Board Type" | ||
378 | |||
379 | config MACH_AT91EB01 | ||
380 | bool "Atmel AT91EB01 Evaluation Kit" | ||
381 | help | ||
382 | Select this if you are using Atmel's AT91EB01 Evaluation Kit. | ||
383 | It is also a popular target for simulators such as GDB's | ||
384 | ARM simulator (commonly known as the ARMulator) and the | ||
385 | Skyeye simulator. | ||
386 | |||
387 | endif | ||
388 | |||
389 | # ---------------------------------------------------------- | ||
390 | |||
391 | comment "AT91 Board Options" | ||
392 | |||
393 | config MTD_AT91_DATAFLASH_CARD | ||
394 | bool "Enable DataFlash Card support" | ||
395 | depends on HAVE_AT91_DATAFLASH_CARD | ||
396 | help | ||
397 | Enable support for the DataFlash card. | ||
398 | |||
399 | endmenu | ||
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 39218ca6d8e8..505fed961eb0 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile | |||
@@ -87,8 +87,8 @@ obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o | |||
87 | obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o | 87 | obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o |
88 | 88 | ||
89 | # AT91SAM board with device-tree | 89 | # AT91SAM board with device-tree |
90 | obj-$(CONFIG_MACH_AT91RM9200_DT) += board-rm9200-dt.o | 90 | obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o |
91 | obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o | 91 | obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o |
92 | 92 | ||
93 | # AT91X40 board-specific support | 93 | # AT91X40 board-specific support |
94 | obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o | 94 | obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o |
diff --git a/arch/arm/mach-at91/at91_rstc.h b/arch/arm/mach-at91/at91_rstc.h index 875fa336800b..a600e6992920 100644 --- a/arch/arm/mach-at91/at91_rstc.h +++ b/arch/arm/mach-at91/at91_rstc.h | |||
@@ -23,7 +23,7 @@ extern void __iomem *at91_rstc_base; | |||
23 | __raw_readl(at91_rstc_base + field) | 23 | __raw_readl(at91_rstc_base + field) |
24 | 24 | ||
25 | #define at91_rstc_write(field, value) \ | 25 | #define at91_rstc_write(field, value) \ |
26 | __raw_writel(value, at91_rstc_base + field); | 26 | __raw_writel(value, at91_rstc_base + field) |
27 | #else | 27 | #else |
28 | .extern at91_rstc_base | 28 | .extern at91_rstc_base |
29 | #endif | 29 | #endif |
diff --git a/arch/arm/mach-at91/at91_shdwc.h b/arch/arm/mach-at91/at91_shdwc.h index 60478ea8bd46..9e29f31ec9a6 100644 --- a/arch/arm/mach-at91/at91_shdwc.h +++ b/arch/arm/mach-at91/at91_shdwc.h | |||
@@ -23,7 +23,7 @@ extern void __iomem *at91_shdwc_base; | |||
23 | __raw_readl(at91_shdwc_base + field) | 23 | __raw_readl(at91_shdwc_base + field) |
24 | 24 | ||
25 | #define at91_shdwc_write(field, value) \ | 25 | #define at91_shdwc_write(field, value) \ |
26 | __raw_writel(value, at91_shdwc_base + field); | 26 | __raw_writel(value, at91_shdwc_base + field) |
27 | #endif | 27 | #endif |
28 | 28 | ||
29 | #define AT91_SHDW_CR 0x00 /* Shut Down Control Register */ | 29 | #define AT91_SHDW_CR 0x00 /* Shut Down Control Register */ |
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c index 0c07a4459cb2..2919eba41ff4 100644 --- a/arch/arm/mach-at91/at91x40_time.c +++ b/arch/arm/mach-at91/at91x40_time.c | |||
@@ -33,7 +33,7 @@ | |||
33 | __raw_readl(AT91_IO_P2V(AT91_TC) + field) | 33 | __raw_readl(AT91_IO_P2V(AT91_TC) + field) |
34 | 34 | ||
35 | #define at91_tc_write(field, value) \ | 35 | #define at91_tc_write(field, value) \ |
36 | __raw_writel(value, AT91_IO_P2V(AT91_TC) + field); | 36 | __raw_writel(value, AT91_IO_P2V(AT91_TC) + field) |
37 | 37 | ||
38 | /* | 38 | /* |
39 | * 3 counter/timer units present. | 39 | * 3 counter/timer units present. |
diff --git a/arch/arm/mach-at91/board-rm9200-dt.c b/arch/arm/mach-at91/board-dt-rm9200.c index 3fcb6623a33e..3fcb6623a33e 100644 --- a/arch/arm/mach-at91/board-rm9200-dt.c +++ b/arch/arm/mach-at91/board-dt-rm9200.c | |||
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt-sam9.c index 8db30132abed..8db30132abed 100644 --- a/arch/arm/mach-at91/board-dt.c +++ b/arch/arm/mach-at91/board-dt-sam9.c | |||
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index c5d7e1e9d757..a5afcf76550e 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c | |||
@@ -22,10 +22,9 @@ | |||
22 | #include <linux/module.h> | 22 | #include <linux/module.h> |
23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | #include <linux/irqdomain.h> | 24 | #include <linux/irqdomain.h> |
25 | #include <linux/irqchip/chained_irq.h> | ||
25 | #include <linux/of_address.h> | 26 | #include <linux/of_address.h> |
26 | 27 | ||
27 | #include <asm/mach/irq.h> | ||
28 | |||
29 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
30 | #include <mach/at91_pio.h> | 29 | #include <mach/at91_pio.h> |
31 | 30 | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h index 2aa0c5e13495..3b5948566e52 100644 --- a/arch/arm/mach-at91/include/mach/at91_dbgu.h +++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h | |||
@@ -16,9 +16,6 @@ | |||
16 | #ifndef AT91_DBGU_H | 16 | #ifndef AT91_DBGU_H |
17 | #define AT91_DBGU_H | 17 | #define AT91_DBGU_H |
18 | 18 | ||
19 | #define dbgu_readl(dbgu, field) \ | ||
20 | __raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field) | ||
21 | |||
22 | #if !defined(CONFIG_ARCH_AT91X40) | 19 | #if !defined(CONFIG_ARCH_AT91X40) |
23 | #define AT91_DBGU_CR (0x00) /* Control Register */ | 20 | #define AT91_DBGU_CR (0x00) /* Control Register */ |
24 | #define AT91_DBGU_MR (0x04) /* Mode Register */ | 21 | #define AT91_DBGU_MR (0x04) /* Mode Register */ |
diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h index 02fae9de746b..f8996c954131 100644 --- a/arch/arm/mach-at91/include/mach/at91_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91_matrix.h | |||
@@ -14,7 +14,7 @@ extern void __iomem *at91_matrix_base; | |||
14 | __raw_readl(at91_matrix_base + field) | 14 | __raw_readl(at91_matrix_base + field) |
15 | 15 | ||
16 | #define at91_matrix_write(field, value) \ | 16 | #define at91_matrix_write(field, value) \ |
17 | __raw_writel(value, at91_matrix_base + field); | 17 | __raw_writel(value, at91_matrix_base + field) |
18 | 18 | ||
19 | #else | 19 | #else |
20 | .extern at91_matrix_base | 20 | .extern at91_matrix_base |
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h index 969aac27109f..67fdbd13c3ed 100644 --- a/arch/arm/mach-at91/include/mach/at91_st.h +++ b/arch/arm/mach-at91/include/mach/at91_st.h | |||
@@ -23,7 +23,7 @@ extern void __iomem *at91_st_base; | |||
23 | __raw_readl(at91_st_base + field) | 23 | __raw_readl(at91_st_base + field) |
24 | 24 | ||
25 | #define at91_st_write(field, value) \ | 25 | #define at91_st_write(field, value) \ |
26 | __raw_writel(value, at91_st_base + field); | 26 | __raw_writel(value, at91_st_base + field) |
27 | #else | 27 | #else |
28 | .extern at91_st_base | 28 | .extern at91_st_base |
29 | #endif | 29 | #endif |
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index 4b678478cf95..9e7c1e1528e5 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c | |||
@@ -333,7 +333,7 @@ static void at91_dt_rstc(void) | |||
333 | 333 | ||
334 | of_id = of_match_node(rstc_ids, np); | 334 | of_id = of_match_node(rstc_ids, np); |
335 | if (!of_id) | 335 | if (!of_id) |
336 | panic("AT91: rtsc no restart function availlable\n"); | 336 | panic("AT91: rtsc no restart function available\n"); |
337 | 337 | ||
338 | arm_pm_restart = of_id->data; | 338 | arm_pm_restart = of_id->data; |
339 | 339 | ||
@@ -353,7 +353,7 @@ static void at91_dt_ramc(void) | |||
353 | 353 | ||
354 | np = of_find_matching_node(NULL, ramc_ids); | 354 | np = of_find_matching_node(NULL, ramc_ids); |
355 | if (!np) | 355 | if (!np) |
356 | panic("unable to find compatible ram conroller node in dtb\n"); | 356 | panic("unable to find compatible ram controller node in dtb\n"); |
357 | 357 | ||
358 | at91_ramc_base[0] = of_iomap(np, 0); | 358 | at91_ramc_base[0] = of_iomap(np, 0); |
359 | if (!at91_ramc_base[0]) | 359 | if (!at91_ramc_base[0]) |
@@ -403,7 +403,7 @@ static void at91_dt_shdwc(void) | |||
403 | 403 | ||
404 | np = of_find_matching_node(NULL, shdwc_ids); | 404 | np = of_find_matching_node(NULL, shdwc_ids); |
405 | if (!np) { | 405 | if (!np) { |
406 | pr_debug("AT91: unable to find compatible shutdown (shdwc) conroller node in dtb\n"); | 406 | pr_debug("AT91: unable to find compatible shutdown (shdwc) controller node in dtb\n"); |
407 | return; | 407 | return; |
408 | } | 408 | } |
409 | 409 | ||
@@ -419,7 +419,7 @@ static void at91_dt_shdwc(void) | |||
419 | 419 | ||
420 | if (!of_property_read_u32(np, "atmel,wakeup-counter", ®)) { | 420 | if (!of_property_read_u32(np, "atmel,wakeup-counter", ®)) { |
421 | if (reg > AT91_SHDW_CPTWK0_MAX) { | 421 | if (reg > AT91_SHDW_CPTWK0_MAX) { |
422 | pr_warn("AT91: shdwc wakeup conter 0x%x > 0x%x reduce it to 0x%x\n", | 422 | pr_warn("AT91: shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n", |
423 | reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX); | 423 | reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX); |
424 | reg = AT91_SHDW_CPTWK0_MAX; | 424 | reg = AT91_SHDW_CPTWK0_MAX; |
425 | } | 425 | } |
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index d5dde0727339..42378fb90167 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig | |||
@@ -97,11 +97,6 @@ config EXYNOS4_DEV_AHCI | |||
97 | help | 97 | help |
98 | Compile in platform device definitions for AHCI | 98 | Compile in platform device definitions for AHCI |
99 | 99 | ||
100 | config EXYNOS_DEV_DRM | ||
101 | bool | ||
102 | help | ||
103 | Compile in platform device definitions for core DRM device | ||
104 | |||
105 | config EXYNOS4_SETUP_FIMD0 | 100 | config EXYNOS4_SETUP_FIMD0 |
106 | bool | 101 | bool |
107 | help | 102 | help |
@@ -201,7 +196,6 @@ config MACH_SMDKV310 | |||
201 | select EXYNOS4_SETUP_SDHCI | 196 | select EXYNOS4_SETUP_SDHCI |
202 | select EXYNOS4_SETUP_USB_PHY | 197 | select EXYNOS4_SETUP_USB_PHY |
203 | select EXYNOS_DEV_DMA | 198 | select EXYNOS_DEV_DMA |
204 | select EXYNOS_DEV_DRM | ||
205 | select EXYNOS_DEV_SYSMMU | 199 | select EXYNOS_DEV_SYSMMU |
206 | select S3C24XX_PWM | 200 | select S3C24XX_PWM |
207 | select S3C_DEV_HSMMC | 201 | select S3C_DEV_HSMMC |
@@ -255,9 +249,7 @@ config MACH_UNIVERSAL_C210 | |||
255 | select EXYNOS4_SETUP_SDHCI | 249 | select EXYNOS4_SETUP_SDHCI |
256 | select EXYNOS4_SETUP_USB_PHY | 250 | select EXYNOS4_SETUP_USB_PHY |
257 | select EXYNOS_DEV_DMA | 251 | select EXYNOS_DEV_DMA |
258 | select EXYNOS_DEV_DRM | ||
259 | select EXYNOS_DEV_SYSMMU | 252 | select EXYNOS_DEV_SYSMMU |
260 | select HAVE_SCHED_CLOCK | ||
261 | select S3C_DEV_HSMMC | 253 | select S3C_DEV_HSMMC |
262 | select S3C_DEV_HSMMC2 | 254 | select S3C_DEV_HSMMC2 |
263 | select S3C_DEV_HSMMC3 | 255 | select S3C_DEV_HSMMC3 |
@@ -296,7 +288,6 @@ config MACH_NURI | |||
296 | select EXYNOS4_SETUP_SDHCI | 288 | select EXYNOS4_SETUP_SDHCI |
297 | select EXYNOS4_SETUP_USB_PHY | 289 | select EXYNOS4_SETUP_USB_PHY |
298 | select EXYNOS_DEV_DMA | 290 | select EXYNOS_DEV_DMA |
299 | select EXYNOS_DEV_DRM | ||
300 | select S3C_DEV_HSMMC | 291 | select S3C_DEV_HSMMC |
301 | select S3C_DEV_HSMMC2 | 292 | select S3C_DEV_HSMMC2 |
302 | select S3C_DEV_HSMMC3 | 293 | select S3C_DEV_HSMMC3 |
@@ -332,7 +323,6 @@ config MACH_ORIGEN | |||
332 | select EXYNOS4_SETUP_SDHCI | 323 | select EXYNOS4_SETUP_SDHCI |
333 | select EXYNOS4_SETUP_USB_PHY | 324 | select EXYNOS4_SETUP_USB_PHY |
334 | select EXYNOS_DEV_DMA | 325 | select EXYNOS_DEV_DMA |
335 | select EXYNOS_DEV_DRM | ||
336 | select EXYNOS_DEV_SYSMMU | 326 | select EXYNOS_DEV_SYSMMU |
337 | select S3C24XX_PWM | 327 | select S3C24XX_PWM |
338 | select S3C_DEV_HSMMC | 328 | select S3C_DEV_HSMMC |
@@ -368,7 +358,6 @@ config MACH_SMDK4212 | |||
368 | select EXYNOS4_SETUP_SDHCI | 358 | select EXYNOS4_SETUP_SDHCI |
369 | select EXYNOS4_SETUP_USB_PHY | 359 | select EXYNOS4_SETUP_USB_PHY |
370 | select EXYNOS_DEV_DMA | 360 | select EXYNOS_DEV_DMA |
371 | select EXYNOS_DEV_DRM | ||
372 | select EXYNOS_DEV_SYSMMU | 361 | select EXYNOS_DEV_SYSMMU |
373 | select S3C24XX_PWM | 362 | select S3C24XX_PWM |
374 | select S3C_DEV_HSMMC2 | 363 | select S3C_DEV_HSMMC2 |
@@ -409,7 +398,7 @@ config MACH_EXYNOS4_DT | |||
409 | depends on ARCH_EXYNOS4 | 398 | depends on ARCH_EXYNOS4 |
410 | select ARM_AMBA | 399 | select ARM_AMBA |
411 | select CPU_EXYNOS4210 | 400 | select CPU_EXYNOS4210 |
412 | select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD | 401 | select KEYBOARD_SAMSUNG if INPUT_KEYBOARD |
413 | select PINCTRL | 402 | select PINCTRL |
414 | select PINCTRL_EXYNOS | 403 | select PINCTRL_EXYNOS |
415 | select USE_OF | 404 | select USE_OF |
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index d63d399c7bae..1b0fa7afc7f8 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c | |||
@@ -23,9 +23,9 @@ | |||
23 | #include <linux/of_irq.h> | 23 | #include <linux/of_irq.h> |
24 | #include <linux/export.h> | 24 | #include <linux/export.h> |
25 | #include <linux/irqdomain.h> | 25 | #include <linux/irqdomain.h> |
26 | #include <linux/irqchip.h> | ||
27 | #include <linux/of_address.h> | 26 | #include <linux/of_address.h> |
28 | #include <linux/irqchip/arm-gic.h> | 27 | #include <linux/irqchip/arm-gic.h> |
28 | #include <linux/irqchip/chained_irq.h> | ||
29 | 29 | ||
30 | #include <asm/proc-fns.h> | 30 | #include <asm/proc-fns.h> |
31 | #include <asm/exception.h> | 31 | #include <asm/exception.h> |
diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c index 4244d02dafbd..d5bc129e6bb7 100644 --- a/arch/arm/mach-exynos/dev-ohci.c +++ b/arch/arm/mach-exynos/dev-ohci.c | |||
@@ -12,7 +12,7 @@ | |||
12 | 12 | ||
13 | #include <linux/dma-mapping.h> | 13 | #include <linux/dma-mapping.h> |
14 | #include <linux/platform_device.h> | 14 | #include <linux/platform_device.h> |
15 | #include <linux/platform_data/usb-exynos.h> | 15 | #include <linux/platform_data/usb-ohci-exynos.h> |
16 | 16 | ||
17 | #include <mach/irqs.h> | 17 | #include <mach/irqs.h> |
18 | #include <mach/map.h> | 18 | #include <mach/map.h> |
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index 579d2d171daa..bf946931ab32 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c | |||
@@ -26,7 +26,7 @@ | |||
26 | #include <linux/platform_data/i2c-s3c2410.h> | 26 | #include <linux/platform_data/i2c-s3c2410.h> |
27 | #include <linux/platform_data/s3c-hsotg.h> | 27 | #include <linux/platform_data/s3c-hsotg.h> |
28 | #include <linux/platform_data/usb-ehci-s5p.h> | 28 | #include <linux/platform_data/usb-ehci-s5p.h> |
29 | #include <linux/platform_data/usb-exynos.h> | 29 | #include <linux/platform_data/usb-ohci-exynos.h> |
30 | 30 | ||
31 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
32 | #include <asm/mach-types.h> | 32 | #include <asm/mach-types.h> |
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c index d71672922b19..8270929d7b44 100644 --- a/arch/arm/mach-exynos/mach-smdkv310.c +++ b/arch/arm/mach-exynos/mach-smdkv310.c | |||
@@ -23,7 +23,7 @@ | |||
23 | #include <linux/platform_data/i2c-s3c2410.h> | 23 | #include <linux/platform_data/i2c-s3c2410.h> |
24 | #include <linux/platform_data/s3c-hsotg.h> | 24 | #include <linux/platform_data/s3c-hsotg.h> |
25 | #include <linux/platform_data/usb-ehci-s5p.h> | 25 | #include <linux/platform_data/usb-ehci-s5p.h> |
26 | #include <linux/platform_data/usb-exynos.h> | 26 | #include <linux/platform_data/usb-ohci-exynos.h> |
27 | 27 | ||
28 | #include <asm/mach/arch.h> | 28 | #include <asm/mach/arch.h> |
29 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 60f7c5be057d..95e04bd5813f 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c | |||
@@ -20,7 +20,6 @@ | |||
20 | #include <linux/jiffies.h> | 20 | #include <linux/jiffies.h> |
21 | #include <linux/smp.h> | 21 | #include <linux/smp.h> |
22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
23 | #include <linux/irqchip/arm-gic.h> | ||
24 | 23 | ||
25 | #include <asm/cacheflush.h> | 24 | #include <asm/cacheflush.h> |
26 | #include <asm/smp_plat.h> | 25 | #include <asm/smp_plat.h> |
@@ -76,13 +75,6 @@ static DEFINE_SPINLOCK(boot_lock); | |||
76 | static void __cpuinit exynos_secondary_init(unsigned int cpu) | 75 | static void __cpuinit exynos_secondary_init(unsigned int cpu) |
77 | { | 76 | { |
78 | /* | 77 | /* |
79 | * if any interrupts are already enabled for the primary | ||
80 | * core (e.g. timer irq), then they will not have been enabled | ||
81 | * for us: do so | ||
82 | */ | ||
83 | gic_secondary_init(0); | ||
84 | |||
85 | /* | ||
86 | * let the primary processor know we're out of the | 78 | * let the primary processor know we're out of the |
87 | * pen, then head off into the C entry point | 79 | * pen, then head off into the C entry point |
88 | */ | 80 | */ |
diff --git a/arch/arm/mach-gemini/Makefile b/arch/arm/mach-gemini/Makefile index 7355c0bbcb5e..7963a77be637 100644 --- a/arch/arm/mach-gemini/Makefile +++ b/arch/arm/mach-gemini/Makefile | |||
@@ -4,7 +4,7 @@ | |||
4 | 4 | ||
5 | # Object file lists. | 5 | # Object file lists. |
6 | 6 | ||
7 | obj-y := irq.o mm.o time.o devices.o gpio.o idle.o | 7 | obj-y := irq.o mm.o time.o devices.o gpio.o idle.o reset.o |
8 | 8 | ||
9 | # Board-specific support | 9 | # Board-specific support |
10 | obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o | 10 | obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o |
diff --git a/arch/arm/mach-gemini/board-nas4220b.c b/arch/arm/mach-gemini/board-nas4220b.c index 08bd650c42f3..ca8a25bb3521 100644 --- a/arch/arm/mach-gemini/board-nas4220b.c +++ b/arch/arm/mach-gemini/board-nas4220b.c | |||
@@ -103,4 +103,5 @@ MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B") | |||
103 | .init_irq = gemini_init_irq, | 103 | .init_irq = gemini_init_irq, |
104 | .init_time = gemini_timer_init, | 104 | .init_time = gemini_timer_init, |
105 | .init_machine = ib4220b_init, | 105 | .init_machine = ib4220b_init, |
106 | .restart = gemini_restart, | ||
106 | MACHINE_END | 107 | MACHINE_END |
diff --git a/arch/arm/mach-gemini/board-rut1xx.c b/arch/arm/mach-gemini/board-rut1xx.c index fa0a36337f4d..7a675f88ffd6 100644 --- a/arch/arm/mach-gemini/board-rut1xx.c +++ b/arch/arm/mach-gemini/board-rut1xx.c | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <linux/leds.h> | 14 | #include <linux/leds.h> |
15 | #include <linux/input.h> | 15 | #include <linux/input.h> |
16 | #include <linux/gpio_keys.h> | 16 | #include <linux/gpio_keys.h> |
17 | #include <linux/sizes.h> | ||
17 | 18 | ||
18 | #include <asm/mach-types.h> | 19 | #include <asm/mach-types.h> |
19 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
@@ -87,4 +88,5 @@ MACHINE_START(RUT100, "Teltonika RUT100") | |||
87 | .init_irq = gemini_init_irq, | 88 | .init_irq = gemini_init_irq, |
88 | .init_time = gemini_timer_init, | 89 | .init_time = gemini_timer_init, |
89 | .init_machine = rut1xx_init, | 90 | .init_machine = rut1xx_init, |
91 | .restart = gemini_restart, | ||
90 | MACHINE_END | 92 | MACHINE_END |
diff --git a/arch/arm/mach-gemini/board-wbd111.c b/arch/arm/mach-gemini/board-wbd111.c index 3321cd6cc1f3..418188cd1712 100644 --- a/arch/arm/mach-gemini/board-wbd111.c +++ b/arch/arm/mach-gemini/board-wbd111.c | |||
@@ -130,4 +130,5 @@ MACHINE_START(WBD111, "Wiliboard WBD-111") | |||
130 | .init_irq = gemini_init_irq, | 130 | .init_irq = gemini_init_irq, |
131 | .init_time = gemini_timer_init, | 131 | .init_time = gemini_timer_init, |
132 | .init_machine = wbd111_init, | 132 | .init_machine = wbd111_init, |
133 | .restart = gemini_restart, | ||
133 | MACHINE_END | 134 | MACHINE_END |
diff --git a/arch/arm/mach-gemini/board-wbd222.c b/arch/arm/mach-gemini/board-wbd222.c index fe33c825fdaf..266b265090cd 100644 --- a/arch/arm/mach-gemini/board-wbd222.c +++ b/arch/arm/mach-gemini/board-wbd222.c | |||
@@ -130,4 +130,5 @@ MACHINE_START(WBD222, "Wiliboard WBD-222") | |||
130 | .init_irq = gemini_init_irq, | 130 | .init_irq = gemini_init_irq, |
131 | .init_time = gemini_timer_init, | 131 | .init_time = gemini_timer_init, |
132 | .init_machine = wbd222_init, | 132 | .init_machine = wbd222_init, |
133 | .restart = gemini_restart, | ||
133 | MACHINE_END | 134 | MACHINE_END |
diff --git a/arch/arm/mach-gemini/common.h b/arch/arm/mach-gemini/common.h index 7670c39acb2f..38a45260a7c8 100644 --- a/arch/arm/mach-gemini/common.h +++ b/arch/arm/mach-gemini/common.h | |||
@@ -26,4 +26,6 @@ extern int platform_register_pflash(unsigned int size, | |||
26 | struct mtd_partition *parts, | 26 | struct mtd_partition *parts, |
27 | unsigned int nr_parts); | 27 | unsigned int nr_parts); |
28 | 28 | ||
29 | extern void gemini_restart(char mode, const char *cmd); | ||
30 | |||
29 | #endif /* __GEMINI_COMMON_H__ */ | 31 | #endif /* __GEMINI_COMMON_H__ */ |
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c index fdc7ef1391d3..70bfa571b24b 100644 --- a/arch/arm/mach-gemini/gpio.c +++ b/arch/arm/mach-gemini/gpio.c | |||
@@ -21,6 +21,7 @@ | |||
21 | 21 | ||
22 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
23 | #include <mach/irqs.h> | 23 | #include <mach/irqs.h> |
24 | #include <mach/gpio.h> | ||
24 | 25 | ||
25 | #define GPIO_BASE(x) IO_ADDRESS(GEMINI_GPIO_BASE(x)) | 26 | #define GPIO_BASE(x) IO_ADDRESS(GEMINI_GPIO_BASE(x)) |
26 | 27 | ||
@@ -44,7 +45,7 @@ | |||
44 | 45 | ||
45 | #define GPIO_PORT_NUM 3 | 46 | #define GPIO_PORT_NUM 3 |
46 | 47 | ||
47 | static void _set_gpio_irqenable(unsigned int base, unsigned int index, | 48 | static void _set_gpio_irqenable(void __iomem *base, unsigned int index, |
48 | int enable) | 49 | int enable) |
49 | { | 50 | { |
50 | unsigned int reg; | 51 | unsigned int reg; |
@@ -57,7 +58,7 @@ static void _set_gpio_irqenable(unsigned int base, unsigned int index, | |||
57 | static void gpio_ack_irq(struct irq_data *d) | 58 | static void gpio_ack_irq(struct irq_data *d) |
58 | { | 59 | { |
59 | unsigned int gpio = irq_to_gpio(d->irq); | 60 | unsigned int gpio = irq_to_gpio(d->irq); |
60 | unsigned int base = GPIO_BASE(gpio / 32); | 61 | void __iomem *base = GPIO_BASE(gpio / 32); |
61 | 62 | ||
62 | __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR); | 63 | __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR); |
63 | } | 64 | } |
@@ -65,7 +66,7 @@ static void gpio_ack_irq(struct irq_data *d) | |||
65 | static void gpio_mask_irq(struct irq_data *d) | 66 | static void gpio_mask_irq(struct irq_data *d) |
66 | { | 67 | { |
67 | unsigned int gpio = irq_to_gpio(d->irq); | 68 | unsigned int gpio = irq_to_gpio(d->irq); |
68 | unsigned int base = GPIO_BASE(gpio / 32); | 69 | void __iomem *base = GPIO_BASE(gpio / 32); |
69 | 70 | ||
70 | _set_gpio_irqenable(base, gpio % 32, 0); | 71 | _set_gpio_irqenable(base, gpio % 32, 0); |
71 | } | 72 | } |
@@ -73,7 +74,7 @@ static void gpio_mask_irq(struct irq_data *d) | |||
73 | static void gpio_unmask_irq(struct irq_data *d) | 74 | static void gpio_unmask_irq(struct irq_data *d) |
74 | { | 75 | { |
75 | unsigned int gpio = irq_to_gpio(d->irq); | 76 | unsigned int gpio = irq_to_gpio(d->irq); |
76 | unsigned int base = GPIO_BASE(gpio / 32); | 77 | void __iomem *base = GPIO_BASE(gpio / 32); |
77 | 78 | ||
78 | _set_gpio_irqenable(base, gpio % 32, 1); | 79 | _set_gpio_irqenable(base, gpio % 32, 1); |
79 | } | 80 | } |
@@ -82,7 +83,7 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type) | |||
82 | { | 83 | { |
83 | unsigned int gpio = irq_to_gpio(d->irq); | 84 | unsigned int gpio = irq_to_gpio(d->irq); |
84 | unsigned int gpio_mask = 1 << (gpio % 32); | 85 | unsigned int gpio_mask = 1 << (gpio % 32); |
85 | unsigned int base = GPIO_BASE(gpio / 32); | 86 | void __iomem *base = GPIO_BASE(gpio / 32); |
86 | unsigned int reg_both, reg_level, reg_type; | 87 | unsigned int reg_both, reg_level, reg_type; |
87 | 88 | ||
88 | reg_type = __raw_readl(base + GPIO_INT_TYPE); | 89 | reg_type = __raw_readl(base + GPIO_INT_TYPE); |
@@ -120,7 +121,7 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type) | |||
120 | __raw_writel(reg_level, base + GPIO_INT_LEVEL); | 121 | __raw_writel(reg_level, base + GPIO_INT_LEVEL); |
121 | __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE); | 122 | __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE); |
122 | 123 | ||
123 | gpio_ack_irq(d->irq); | 124 | gpio_ack_irq(d); |
124 | 125 | ||
125 | return 0; | 126 | return 0; |
126 | } | 127 | } |
@@ -153,7 +154,7 @@ static struct irq_chip gpio_irq_chip = { | |||
153 | static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, | 154 | static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, |
154 | int dir) | 155 | int dir) |
155 | { | 156 | { |
156 | unsigned int base = GPIO_BASE(offset / 32); | 157 | void __iomem *base = GPIO_BASE(offset / 32); |
157 | unsigned int reg; | 158 | unsigned int reg; |
158 | 159 | ||
159 | reg = __raw_readl(base + GPIO_DIR); | 160 | reg = __raw_readl(base + GPIO_DIR); |
@@ -166,7 +167,7 @@ static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, | |||
166 | 167 | ||
167 | static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | 168 | static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
168 | { | 169 | { |
169 | unsigned int base = GPIO_BASE(offset / 32); | 170 | void __iomem *base = GPIO_BASE(offset / 32); |
170 | 171 | ||
171 | if (value) | 172 | if (value) |
172 | __raw_writel(1 << (offset % 32), base + GPIO_DATA_SET); | 173 | __raw_writel(1 << (offset % 32), base + GPIO_DATA_SET); |
@@ -176,7 +177,7 @@ static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |||
176 | 177 | ||
177 | static int gemini_gpio_get(struct gpio_chip *chip, unsigned offset) | 178 | static int gemini_gpio_get(struct gpio_chip *chip, unsigned offset) |
178 | { | 179 | { |
179 | unsigned int base = GPIO_BASE(offset / 32); | 180 | void __iomem *base = GPIO_BASE(offset / 32); |
180 | 181 | ||
181 | return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1; | 182 | return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1; |
182 | } | 183 | } |
diff --git a/arch/arm/mach-gemini/include/mach/hardware.h b/arch/arm/mach-gemini/include/mach/hardware.h index 8c950e1d06be..98e7b0f286bf 100644 --- a/arch/arm/mach-gemini/include/mach/hardware.h +++ b/arch/arm/mach-gemini/include/mach/hardware.h | |||
@@ -69,6 +69,6 @@ | |||
69 | /* | 69 | /* |
70 | * macro to get at IO space when running virtually | 70 | * macro to get at IO space when running virtually |
71 | */ | 71 | */ |
72 | #define IO_ADDRESS(x) ((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000) | 72 | #define IO_ADDRESS(x) IOMEM((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000) |
73 | 73 | ||
74 | #endif | 74 | #endif |
diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c index 6d8f6d1669ff..44f50dcb616d 100644 --- a/arch/arm/mach-gemini/irq.c +++ b/arch/arm/mach-gemini/irq.c | |||
@@ -67,8 +67,8 @@ static struct irq_chip gemini_irq_chip = { | |||
67 | 67 | ||
68 | static struct resource irq_resource = { | 68 | static struct resource irq_resource = { |
69 | .name = "irq_handler", | 69 | .name = "irq_handler", |
70 | .start = IO_ADDRESS(GEMINI_INTERRUPT_BASE), | 70 | .start = GEMINI_INTERRUPT_BASE, |
71 | .end = IO_ADDRESS(FIQ_STATUS(GEMINI_INTERRUPT_BASE)) + 4, | 71 | .end = FIQ_STATUS(GEMINI_INTERRUPT_BASE) + 4, |
72 | }; | 72 | }; |
73 | 73 | ||
74 | void __init gemini_init_irq(void) | 74 | void __init gemini_init_irq(void) |
diff --git a/arch/arm/mach-gemini/mm.c b/arch/arm/mach-gemini/mm.c index 51948242ec09..2c2cd284bb6a 100644 --- a/arch/arm/mach-gemini/mm.c +++ b/arch/arm/mach-gemini/mm.c | |||
@@ -19,57 +19,57 @@ | |||
19 | /* Page table mapping for I/O region */ | 19 | /* Page table mapping for I/O region */ |
20 | static struct map_desc gemini_io_desc[] __initdata = { | 20 | static struct map_desc gemini_io_desc[] __initdata = { |
21 | { | 21 | { |
22 | .virtual = IO_ADDRESS(GEMINI_GLOBAL_BASE), | 22 | .virtual = (unsigned long)IO_ADDRESS(GEMINI_GLOBAL_BASE), |
23 | .pfn =__phys_to_pfn(GEMINI_GLOBAL_BASE), | 23 | .pfn =__phys_to_pfn(GEMINI_GLOBAL_BASE), |
24 | .length = SZ_512K, | 24 | .length = SZ_512K, |
25 | .type = MT_DEVICE, | 25 | .type = MT_DEVICE, |
26 | }, { | 26 | }, { |
27 | .virtual = IO_ADDRESS(GEMINI_UART_BASE), | 27 | .virtual = (unsigned long)IO_ADDRESS(GEMINI_UART_BASE), |
28 | .pfn = __phys_to_pfn(GEMINI_UART_BASE), | 28 | .pfn = __phys_to_pfn(GEMINI_UART_BASE), |
29 | .length = SZ_512K, | 29 | .length = SZ_512K, |
30 | .type = MT_DEVICE, | 30 | .type = MT_DEVICE, |
31 | }, { | 31 | }, { |
32 | .virtual = IO_ADDRESS(GEMINI_TIMER_BASE), | 32 | .virtual = (unsigned long)IO_ADDRESS(GEMINI_TIMER_BASE), |
33 | .pfn = __phys_to_pfn(GEMINI_TIMER_BASE), | 33 | .pfn = __phys_to_pfn(GEMINI_TIMER_BASE), |
34 | .length = SZ_512K, | 34 | .length = SZ_512K, |
35 | .type = MT_DEVICE, | 35 | .type = MT_DEVICE, |
36 | }, { | 36 | }, { |
37 | .virtual = IO_ADDRESS(GEMINI_INTERRUPT_BASE), | 37 | .virtual = (unsigned long)IO_ADDRESS(GEMINI_INTERRUPT_BASE), |
38 | .pfn = __phys_to_pfn(GEMINI_INTERRUPT_BASE), | 38 | .pfn = __phys_to_pfn(GEMINI_INTERRUPT_BASE), |
39 | .length = SZ_512K, | 39 | .length = SZ_512K, |
40 | .type = MT_DEVICE, | 40 | .type = MT_DEVICE, |
41 | }, { | 41 | }, { |
42 | .virtual = IO_ADDRESS(GEMINI_POWER_CTRL_BASE), | 42 | .virtual = (unsigned long)IO_ADDRESS(GEMINI_POWER_CTRL_BASE), |
43 | .pfn = __phys_to_pfn(GEMINI_POWER_CTRL_BASE), | 43 | .pfn = __phys_to_pfn(GEMINI_POWER_CTRL_BASE), |
44 | .length = SZ_512K, | 44 | .length = SZ_512K, |
45 | .type = MT_DEVICE, | 45 | .type = MT_DEVICE, |
46 | }, { | 46 | }, { |
47 | .virtual = IO_ADDRESS(GEMINI_GPIO_BASE(0)), | 47 | .virtual = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(0)), |
48 | .pfn = __phys_to_pfn(GEMINI_GPIO_BASE(0)), | 48 | .pfn = __phys_to_pfn(GEMINI_GPIO_BASE(0)), |
49 | .length = SZ_512K, | 49 | .length = SZ_512K, |
50 | .type = MT_DEVICE, | 50 | .type = MT_DEVICE, |
51 | }, { | 51 | }, { |
52 | .virtual = IO_ADDRESS(GEMINI_GPIO_BASE(1)), | 52 | .virtual = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(1)), |
53 | .pfn = __phys_to_pfn(GEMINI_GPIO_BASE(1)), | 53 | .pfn = __phys_to_pfn(GEMINI_GPIO_BASE(1)), |
54 | .length = SZ_512K, | 54 | .length = SZ_512K, |
55 | .type = MT_DEVICE, | 55 | .type = MT_DEVICE, |
56 | }, { | 56 | }, { |
57 | .virtual = IO_ADDRESS(GEMINI_GPIO_BASE(2)), | 57 | .virtual = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(2)), |
58 | .pfn = __phys_to_pfn(GEMINI_GPIO_BASE(2)), | 58 | .pfn = __phys_to_pfn(GEMINI_GPIO_BASE(2)), |
59 | .length = SZ_512K, | 59 | .length = SZ_512K, |
60 | .type = MT_DEVICE, | 60 | .type = MT_DEVICE, |
61 | }, { | 61 | }, { |
62 | .virtual = IO_ADDRESS(GEMINI_FLASH_CTRL_BASE), | 62 | .virtual = (unsigned long)IO_ADDRESS(GEMINI_FLASH_CTRL_BASE), |
63 | .pfn = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE), | 63 | .pfn = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE), |
64 | .length = SZ_512K, | 64 | .length = SZ_512K, |
65 | .type = MT_DEVICE, | 65 | .type = MT_DEVICE, |
66 | }, { | 66 | }, { |
67 | .virtual = IO_ADDRESS(GEMINI_DRAM_CTRL_BASE), | 67 | .virtual = (unsigned long)IO_ADDRESS(GEMINI_DRAM_CTRL_BASE), |
68 | .pfn = __phys_to_pfn(GEMINI_DRAM_CTRL_BASE), | 68 | .pfn = __phys_to_pfn(GEMINI_DRAM_CTRL_BASE), |
69 | .length = SZ_512K, | 69 | .length = SZ_512K, |
70 | .type = MT_DEVICE, | 70 | .type = MT_DEVICE, |
71 | }, { | 71 | }, { |
72 | .virtual = IO_ADDRESS(GEMINI_GENERAL_DMA_BASE), | 72 | .virtual = (unsigned long)IO_ADDRESS(GEMINI_GENERAL_DMA_BASE), |
73 | .pfn = __phys_to_pfn(GEMINI_GENERAL_DMA_BASE), | 73 | .pfn = __phys_to_pfn(GEMINI_GENERAL_DMA_BASE), |
74 | .length = SZ_512K, | 74 | .length = SZ_512K, |
75 | .type = MT_DEVICE, | 75 | .type = MT_DEVICE, |
diff --git a/arch/arm/mach-gemini/include/mach/system.h b/arch/arm/mach-gemini/reset.c index a33b5a1f8ab4..b26659759e27 100644 --- a/arch/arm/mach-gemini/include/mach/system.h +++ b/arch/arm/mach-gemini/reset.c | |||
@@ -14,7 +14,7 @@ | |||
14 | #include <mach/hardware.h> | 14 | #include <mach/hardware.h> |
15 | #include <mach/global_reg.h> | 15 | #include <mach/global_reg.h> |
16 | 16 | ||
17 | static inline void arch_reset(char mode, const char *cmd) | 17 | void gemini_restart(char mode, const char *cmd) |
18 | { | 18 | { |
19 | __raw_writel(RESET_GLOBAL | RESET_CPU1, | 19 | __raw_writel(RESET_GLOBAL | RESET_CPU1, |
20 | IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET); | 20 | IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET); |
diff --git a/arch/arm/mach-h720x/Kconfig b/arch/arm/mach-h720x/Kconfig deleted file mode 100644 index 6bb755bcb6f5..000000000000 --- a/arch/arm/mach-h720x/Kconfig +++ /dev/null | |||
@@ -1,40 +0,0 @@ | |||
1 | if ARCH_H720X | ||
2 | |||
3 | menu "h720x Implementations" | ||
4 | |||
5 | config ARCH_H7201 | ||
6 | bool "gms30c7201" | ||
7 | depends on ARCH_H720X | ||
8 | select CPU_H7201 | ||
9 | select ZONE_DMA | ||
10 | help | ||
11 | Say Y here if you are using the Hynix GMS30C7201 Reference Board | ||
12 | |||
13 | config ARCH_H7202 | ||
14 | bool "hms30c7202" | ||
15 | depends on ARCH_H720X | ||
16 | select CPU_H7202 | ||
17 | select ZONE_DMA | ||
18 | help | ||
19 | Say Y here if you are using the Hynix HMS30C7202 Reference Board | ||
20 | |||
21 | endmenu | ||
22 | |||
23 | config CPU_H7201 | ||
24 | bool | ||
25 | help | ||
26 | Select code specific to h7201 variants | ||
27 | |||
28 | config CPU_H7202 | ||
29 | bool | ||
30 | help | ||
31 | Select code specific to h7202 variants | ||
32 | config H7202_SERIAL23 | ||
33 | depends on CPU_H7202 | ||
34 | bool "Use serial ports 2+3" | ||
35 | help | ||
36 | Say Y here if you wish to use serial ports 2+3. They share their | ||
37 | pins with the keyboard matrix controller, so you have to decide. | ||
38 | |||
39 | |||
40 | endif | ||
diff --git a/arch/arm/mach-h720x/Makefile b/arch/arm/mach-h720x/Makefile deleted file mode 100644 index e4cf728948eb..000000000000 --- a/arch/arm/mach-h720x/Makefile +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | # | ||
2 | # Makefile for the linux kernel. | ||
3 | # | ||
4 | |||
5 | # Common support | ||
6 | obj-y := common.o | ||
7 | obj-m := | ||
8 | obj-n := | ||
9 | obj- := | ||
10 | |||
11 | # Specific board support | ||
12 | |||
13 | obj-$(CONFIG_ARCH_H7201) += h7201-eval.o | ||
14 | obj-$(CONFIG_ARCH_H7202) += h7202-eval.o | ||
15 | obj-$(CONFIG_CPU_H7201) += cpu-h7201.o | ||
16 | obj-$(CONFIG_CPU_H7202) += cpu-h7202.o | ||
diff --git a/arch/arm/mach-h720x/Makefile.boot b/arch/arm/mach-h720x/Makefile.boot deleted file mode 100644 index d875a7094dfe..000000000000 --- a/arch/arm/mach-h720x/Makefile.boot +++ /dev/null | |||
@@ -1,2 +0,0 @@ | |||
1 | zreladdr-$(CONFIG_ARCH_H720X) += 0x40008000 | ||
2 | |||
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c deleted file mode 100644 index 17ef91fa3d56..000000000000 --- a/arch/arm/mach-h720x/common.c +++ /dev/null | |||
@@ -1,268 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-h720x/common.c | ||
3 | * | ||
4 | * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de> | ||
5 | * 2003 Robert Schwebel <r.schwebel@pengutronix.de> | ||
6 | * 2004 Sascha Hauer <s.hauer@pengutronix.de> | ||
7 | * | ||
8 | * common stuff for Hynix h720x processors | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #include <linux/sched.h> | ||
17 | #include <linux/mman.h> | ||
18 | #include <linux/init.h> | ||
19 | #include <linux/interrupt.h> | ||
20 | #include <linux/io.h> | ||
21 | |||
22 | #include <asm/page.h> | ||
23 | #include <asm/pgtable.h> | ||
24 | #include <asm/dma.h> | ||
25 | #include <mach/hardware.h> | ||
26 | #include <asm/irq.h> | ||
27 | #include <asm/system_misc.h> | ||
28 | #include <asm/mach/irq.h> | ||
29 | #include <asm/mach/map.h> | ||
30 | #include <mach/irqs.h> | ||
31 | |||
32 | #include <asm/mach/dma.h> | ||
33 | |||
34 | #if 0 | ||
35 | #define IRQDBG(args...) printk(args) | ||
36 | #else | ||
37 | #define IRQDBG(args...) do {} while(0) | ||
38 | #endif | ||
39 | |||
40 | void __init arch_dma_init(dma_t *dma) | ||
41 | { | ||
42 | } | ||
43 | |||
44 | /* | ||
45 | * Return nsecs since last timer reload | ||
46 | * (timercount * (usecs perjiffie)) / (ticks per jiffie) | ||
47 | */ | ||
48 | u32 h720x_gettimeoffset(void) | ||
49 | { | ||
50 | return ((CPU_REG(TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH) * 1000; | ||
51 | } | ||
52 | |||
53 | /* | ||
54 | * mask Global irq's | ||
55 | */ | ||
56 | static void mask_global_irq(struct irq_data *d) | ||
57 | { | ||
58 | CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << d->irq); | ||
59 | } | ||
60 | |||
61 | /* | ||
62 | * unmask Global irq's | ||
63 | */ | ||
64 | static void unmask_global_irq(struct irq_data *d) | ||
65 | { | ||
66 | CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << d->irq); | ||
67 | } | ||
68 | |||
69 | |||
70 | /* | ||
71 | * ack GPIO irq's | ||
72 | * Ack only for edge triggered int's valid | ||
73 | */ | ||
74 | static void inline ack_gpio_irq(struct irq_data *d) | ||
75 | { | ||
76 | u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq)); | ||
77 | u32 bit = IRQ_TO_BIT(d->irq); | ||
78 | if ( (CPU_REG (reg_base, GPIO_EDGE) & bit)) | ||
79 | CPU_REG (reg_base, GPIO_CLR) = bit; | ||
80 | } | ||
81 | |||
82 | /* | ||
83 | * mask GPIO irq's | ||
84 | */ | ||
85 | static void inline mask_gpio_irq(struct irq_data *d) | ||
86 | { | ||
87 | u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq)); | ||
88 | u32 bit = IRQ_TO_BIT(d->irq); | ||
89 | CPU_REG (reg_base, GPIO_MASK) &= ~bit; | ||
90 | } | ||
91 | |||
92 | /* | ||
93 | * unmask GPIO irq's | ||
94 | */ | ||
95 | static void inline unmask_gpio_irq(struct irq_data *d) | ||
96 | { | ||
97 | u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq)); | ||
98 | u32 bit = IRQ_TO_BIT(d->irq); | ||
99 | CPU_REG (reg_base, GPIO_MASK) |= bit; | ||
100 | } | ||
101 | |||
102 | static void | ||
103 | h720x_gpio_handler(unsigned int mask, unsigned int irq, | ||
104 | struct irq_desc *desc) | ||
105 | { | ||
106 | IRQDBG("%s irq: %d\n", __func__, irq); | ||
107 | while (mask) { | ||
108 | if (mask & 1) { | ||
109 | IRQDBG("handling irq %d\n", irq); | ||
110 | generic_handle_irq(irq); | ||
111 | } | ||
112 | irq++; | ||
113 | mask >>= 1; | ||
114 | } | ||
115 | } | ||
116 | |||
117 | static void | ||
118 | h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc) | ||
119 | { | ||
120 | unsigned int mask, irq; | ||
121 | |||
122 | mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT); | ||
123 | irq = IRQ_CHAINED_GPIOA(0); | ||
124 | IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq); | ||
125 | h720x_gpio_handler(mask, irq, desc); | ||
126 | } | ||
127 | |||
128 | static void | ||
129 | h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc) | ||
130 | { | ||
131 | unsigned int mask, irq; | ||
132 | mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT); | ||
133 | irq = IRQ_CHAINED_GPIOB(0); | ||
134 | IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq); | ||
135 | h720x_gpio_handler(mask, irq, desc); | ||
136 | } | ||
137 | |||
138 | static void | ||
139 | h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc) | ||
140 | { | ||
141 | unsigned int mask, irq; | ||
142 | |||
143 | mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT); | ||
144 | irq = IRQ_CHAINED_GPIOC(0); | ||
145 | IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq); | ||
146 | h720x_gpio_handler(mask, irq, desc); | ||
147 | } | ||
148 | |||
149 | static void | ||
150 | h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc) | ||
151 | { | ||
152 | unsigned int mask, irq; | ||
153 | |||
154 | mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT); | ||
155 | irq = IRQ_CHAINED_GPIOD(0); | ||
156 | IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq); | ||
157 | h720x_gpio_handler(mask, irq, desc); | ||
158 | } | ||
159 | |||
160 | #ifdef CONFIG_CPU_H7202 | ||
161 | static void | ||
162 | h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc) | ||
163 | { | ||
164 | unsigned int mask, irq; | ||
165 | |||
166 | mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT); | ||
167 | irq = IRQ_CHAINED_GPIOE(0); | ||
168 | IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq); | ||
169 | h720x_gpio_handler(mask, irq, desc); | ||
170 | } | ||
171 | #endif | ||
172 | |||
173 | static struct irq_chip h720x_global_chip = { | ||
174 | .irq_ack = mask_global_irq, | ||
175 | .irq_mask = mask_global_irq, | ||
176 | .irq_unmask = unmask_global_irq, | ||
177 | }; | ||
178 | |||
179 | static struct irq_chip h720x_gpio_chip = { | ||
180 | .irq_ack = ack_gpio_irq, | ||
181 | .irq_mask = mask_gpio_irq, | ||
182 | .irq_unmask = unmask_gpio_irq, | ||
183 | }; | ||
184 | |||
185 | /* | ||
186 | * Initialize IRQ's, mask all, enable multiplexed irq's | ||
187 | */ | ||
188 | void __init h720x_init_irq (void) | ||
189 | { | ||
190 | int irq; | ||
191 | |||
192 | /* Mask global irq's */ | ||
193 | CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0; | ||
194 | |||
195 | /* Mask all multiplexed irq's */ | ||
196 | CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0; | ||
197 | CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0; | ||
198 | CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0; | ||
199 | CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0; | ||
200 | |||
201 | /* Initialize global IRQ's, fast path */ | ||
202 | for (irq = 0; irq < NR_GLBL_IRQS; irq++) { | ||
203 | irq_set_chip_and_handler(irq, &h720x_global_chip, | ||
204 | handle_level_irq); | ||
205 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
206 | } | ||
207 | |||
208 | /* Initialize multiplexed IRQ's, slow path */ | ||
209 | for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { | ||
210 | irq_set_chip_and_handler(irq, &h720x_gpio_chip, | ||
211 | handle_edge_irq); | ||
212 | set_irq_flags(irq, IRQF_VALID ); | ||
213 | } | ||
214 | irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); | ||
215 | irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); | ||
216 | irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); | ||
217 | irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); | ||
218 | |||
219 | #ifdef CONFIG_CPU_H7202 | ||
220 | for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { | ||
221 | irq_set_chip_and_handler(irq, &h720x_gpio_chip, | ||
222 | handle_edge_irq); | ||
223 | set_irq_flags(irq, IRQF_VALID ); | ||
224 | } | ||
225 | irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); | ||
226 | #endif | ||
227 | |||
228 | /* Enable multiplexed irq's */ | ||
229 | CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX; | ||
230 | } | ||
231 | |||
232 | static struct map_desc h720x_io_desc[] __initdata = { | ||
233 | { | ||
234 | .virtual = IO_VIRT, | ||
235 | .pfn = __phys_to_pfn(IO_PHYS), | ||
236 | .length = IO_SIZE, | ||
237 | .type = MT_DEVICE | ||
238 | }, | ||
239 | }; | ||
240 | |||
241 | /* Initialize io tables */ | ||
242 | void __init h720x_map_io(void) | ||
243 | { | ||
244 | iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc)); | ||
245 | } | ||
246 | |||
247 | void h720x_restart(char mode, const char *cmd) | ||
248 | { | ||
249 | CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET; | ||
250 | } | ||
251 | |||
252 | static void h720x__idle(void) | ||
253 | { | ||
254 | CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE; | ||
255 | nop(); | ||
256 | nop(); | ||
257 | CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN; | ||
258 | nop(); | ||
259 | nop(); | ||
260 | } | ||
261 | |||
262 | static int __init h720x_idle_init(void) | ||
263 | { | ||
264 | arm_pm_idle = h720x__idle; | ||
265 | return 0; | ||
266 | } | ||
267 | |||
268 | arch_initcall(h720x_idle_init); | ||
diff --git a/arch/arm/mach-h720x/common.h b/arch/arm/mach-h720x/common.h deleted file mode 100644 index 7e738410ca93..000000000000 --- a/arch/arm/mach-h720x/common.h +++ /dev/null | |||
@@ -1,30 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-h720x/common.h | ||
3 | * | ||
4 | * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de> | ||
5 | * 2003 Robert Schwebel <r.schwebel@pengutronix.de> | ||
6 | * 2004 Sascha Hauer <s.hauer@pengutronix.de> | ||
7 | * | ||
8 | * Architecture specific stuff for Hynix GMS30C7201 development board | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | extern u32 h720x_gettimeoffset(void); | ||
17 | extern void __init h720x_init_irq(void); | ||
18 | extern void __init h720x_map_io(void); | ||
19 | extern void h720x_restart(char, const char *); | ||
20 | |||
21 | #ifdef CONFIG_ARCH_H7202 | ||
22 | extern void h7202_timer_init(void); | ||
23 | extern void __init init_hw_h7202(void); | ||
24 | extern void __init h7202_init_irq(void); | ||
25 | extern void __init h7202_init_time(void); | ||
26 | #endif | ||
27 | |||
28 | #ifdef CONFIG_ARCH_H7201 | ||
29 | extern void h7201_timer_init(void); | ||
30 | #endif | ||
diff --git a/arch/arm/mach-h720x/cpu-h7201.c b/arch/arm/mach-h720x/cpu-h7201.c deleted file mode 100644 index 13c741215387..000000000000 --- a/arch/arm/mach-h720x/cpu-h7201.c +++ /dev/null | |||
@@ -1,57 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-h720x/cpu-h7201.c | ||
3 | * | ||
4 | * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de> | ||
5 | * 2003 Robert Schwebel <r.schwebel@pengutronix.de> | ||
6 | * 2004 Sascha Hauer <s.hauer@pengutronix.de> | ||
7 | * | ||
8 | * processor specific stuff for the Hynix h7201 | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #include <linux/init.h> | ||
17 | #include <linux/interrupt.h> | ||
18 | #include <linux/module.h> | ||
19 | #include <asm/types.h> | ||
20 | #include <mach/hardware.h> | ||
21 | #include <asm/irq.h> | ||
22 | #include <mach/irqs.h> | ||
23 | #include <asm/mach/irq.h> | ||
24 | #include <asm/mach/time.h> | ||
25 | #include "common.h" | ||
26 | /* | ||
27 | * Timer interrupt handler | ||
28 | */ | ||
29 | static irqreturn_t | ||
30 | h7201_timer_interrupt(int irq, void *dev_id) | ||
31 | { | ||
32 | CPU_REG (TIMER_VIRT, TIMER_TOPSTAT); | ||
33 | timer_tick(); | ||
34 | |||
35 | return IRQ_HANDLED; | ||
36 | } | ||
37 | |||
38 | static struct irqaction h7201_timer_irq = { | ||
39 | .name = "h7201 Timer Tick", | ||
40 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
41 | .handler = h7201_timer_interrupt, | ||
42 | }; | ||
43 | |||
44 | /* | ||
45 | * Setup TIMER0 as system timer | ||
46 | */ | ||
47 | void __init h7201_timer_init(void) | ||
48 | { | ||
49 | arch_gettimeoffset = h720x_gettimeoffset; | ||
50 | |||
51 | CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH; | ||
52 | CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET; | ||
53 | CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START; | ||
54 | CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT; | ||
55 | |||
56 | setup_irq(IRQ_TIMER0, &h7201_timer_irq); | ||
57 | } | ||
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c deleted file mode 100644 index e2ae7e898f9d..000000000000 --- a/arch/arm/mach-h720x/cpu-h7202.c +++ /dev/null | |||
@@ -1,225 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-h720x/cpu-h7202.c | ||
3 | * | ||
4 | * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de> | ||
5 | * 2003 Robert Schwebel <r.schwebel@pengutronix.de> | ||
6 | * 2004 Sascha Hauer <s.hauer@pengutronix.de> | ||
7 | * | ||
8 | * processor specific stuff for the Hynix h7202 | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #include <linux/init.h> | ||
17 | #include <linux/interrupt.h> | ||
18 | #include <linux/module.h> | ||
19 | #include <asm/types.h> | ||
20 | #include <mach/hardware.h> | ||
21 | #include <asm/irq.h> | ||
22 | #include <mach/irqs.h> | ||
23 | #include <asm/mach/irq.h> | ||
24 | #include <asm/mach/time.h> | ||
25 | #include <linux/device.h> | ||
26 | #include <linux/serial_8250.h> | ||
27 | #include "common.h" | ||
28 | |||
29 | static struct resource h7202ps2_resources[] = { | ||
30 | [0] = { | ||
31 | .start = 0x8002c000, | ||
32 | .end = 0x8002c040, | ||
33 | .flags = IORESOURCE_MEM, | ||
34 | }, | ||
35 | [1] = { | ||
36 | .start = IRQ_PS2, | ||
37 | .end = IRQ_PS2, | ||
38 | .flags = IORESOURCE_IRQ, | ||
39 | }, | ||
40 | }; | ||
41 | |||
42 | static struct platform_device h7202ps2_device = { | ||
43 | .name = "h7202ps2", | ||
44 | .id = -1, | ||
45 | .num_resources = ARRAY_SIZE(h7202ps2_resources), | ||
46 | .resource = h7202ps2_resources, | ||
47 | }; | ||
48 | |||
49 | static struct plat_serial8250_port serial_platform_data[] = { | ||
50 | { | ||
51 | .membase = (void*)SERIAL0_VIRT, | ||
52 | .mapbase = SERIAL0_BASE, | ||
53 | .irq = IRQ_UART0, | ||
54 | .uartclk = 2*1843200, | ||
55 | .regshift = 2, | ||
56 | .iotype = UPIO_MEM, | ||
57 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | ||
58 | }, | ||
59 | { | ||
60 | .membase = (void*)SERIAL1_VIRT, | ||
61 | .mapbase = SERIAL1_BASE, | ||
62 | .irq = IRQ_UART1, | ||
63 | .uartclk = 2*1843200, | ||
64 | .regshift = 2, | ||
65 | .iotype = UPIO_MEM, | ||
66 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | ||
67 | }, | ||
68 | #ifdef CONFIG_H7202_SERIAL23 | ||
69 | { | ||
70 | .membase = (void*)SERIAL2_VIRT, | ||
71 | .mapbase = SERIAL2_BASE, | ||
72 | .irq = IRQ_UART2, | ||
73 | .uartclk = 2*1843200, | ||
74 | .regshift = 2, | ||
75 | .iotype = UPIO_MEM, | ||
76 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | ||
77 | }, | ||
78 | { | ||
79 | .membase = (void*)SERIAL3_VIRT, | ||
80 | .mapbase = SERIAL3_BASE, | ||
81 | .irq = IRQ_UART3, | ||
82 | .uartclk = 2*1843200, | ||
83 | .regshift = 2, | ||
84 | .iotype = UPIO_MEM, | ||
85 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | ||
86 | }, | ||
87 | #endif | ||
88 | { }, | ||
89 | }; | ||
90 | |||
91 | static struct platform_device serial_device = { | ||
92 | .name = "serial8250", | ||
93 | .id = PLAT8250_DEV_PLATFORM, | ||
94 | .dev = { | ||
95 | .platform_data = serial_platform_data, | ||
96 | }, | ||
97 | }; | ||
98 | |||
99 | static struct platform_device *devices[] __initdata = { | ||
100 | &h7202ps2_device, | ||
101 | &serial_device, | ||
102 | }; | ||
103 | |||
104 | /* Although we have two interrupt lines for the timers, we only have one | ||
105 | * status register which clears all pending timer interrupts on reading. So | ||
106 | * we have to handle all timer interrupts in one place. | ||
107 | */ | ||
108 | static void | ||
109 | h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc) | ||
110 | { | ||
111 | unsigned int mask, irq; | ||
112 | |||
113 | mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT); | ||
114 | |||
115 | if ( mask & TSTAT_T0INT ) { | ||
116 | timer_tick(); | ||
117 | if( mask == TSTAT_T0INT ) | ||
118 | return; | ||
119 | } | ||
120 | |||
121 | mask >>= 1; | ||
122 | irq = IRQ_TIMER1; | ||
123 | while (mask) { | ||
124 | if (mask & 1) | ||
125 | generic_handle_irq(irq); | ||
126 | irq++; | ||
127 | mask >>= 1; | ||
128 | } | ||
129 | } | ||
130 | |||
131 | /* | ||
132 | * Timer interrupt handler | ||
133 | */ | ||
134 | static irqreturn_t | ||
135 | h7202_timer_interrupt(int irq, void *dev_id) | ||
136 | { | ||
137 | h7202_timerx_demux_handler(0, NULL); | ||
138 | return IRQ_HANDLED; | ||
139 | } | ||
140 | |||
141 | /* | ||
142 | * mask multiplexed timer IRQs | ||
143 | */ | ||
144 | static void inline __mask_timerx_irq(unsigned int irq) | ||
145 | { | ||
146 | unsigned int bit; | ||
147 | bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1)); | ||
148 | CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit; | ||
149 | } | ||
150 | |||
151 | static void inline mask_timerx_irq(struct irq_data *d) | ||
152 | { | ||
153 | __mask_timerx_irq(d->irq); | ||
154 | } | ||
155 | |||
156 | /* | ||
157 | * unmask multiplexed timer IRQs | ||
158 | */ | ||
159 | static void inline unmask_timerx_irq(struct irq_data *d) | ||
160 | { | ||
161 | unsigned int bit; | ||
162 | bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1)); | ||
163 | CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit; | ||
164 | } | ||
165 | |||
166 | static struct irq_chip h7202_timerx_chip = { | ||
167 | .irq_ack = mask_timerx_irq, | ||
168 | .irq_mask = mask_timerx_irq, | ||
169 | .irq_unmask = unmask_timerx_irq, | ||
170 | }; | ||
171 | |||
172 | static struct irqaction h7202_timer_irq = { | ||
173 | .name = "h7202 Timer Tick", | ||
174 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
175 | .handler = h7202_timer_interrupt, | ||
176 | }; | ||
177 | |||
178 | /* | ||
179 | * Setup TIMER0 as system timer | ||
180 | */ | ||
181 | void __init h7202_timer_init(void) | ||
182 | { | ||
183 | arch_gettimeoffset = h720x_gettimeoffset; | ||
184 | |||
185 | CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH; | ||
186 | CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET; | ||
187 | CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START; | ||
188 | CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT; | ||
189 | |||
190 | setup_irq(IRQ_TIMER0, &h7202_timer_irq); | ||
191 | } | ||
192 | |||
193 | void __init h7202_init_irq (void) | ||
194 | { | ||
195 | int irq; | ||
196 | |||
197 | CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0; | ||
198 | |||
199 | for (irq = IRQ_TIMER1; | ||
200 | irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) { | ||
201 | __mask_timerx_irq(irq); | ||
202 | irq_set_chip_and_handler(irq, &h7202_timerx_chip, | ||
203 | handle_edge_irq); | ||
204 | set_irq_flags(irq, IRQF_VALID ); | ||
205 | } | ||
206 | irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); | ||
207 | |||
208 | h720x_init_irq(); | ||
209 | } | ||
210 | |||
211 | void __init init_hw_h7202(void) | ||
212 | { | ||
213 | /* Enable clocks */ | ||
214 | CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE; | ||
215 | |||
216 | CPU_REG (SERIAL0_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN; | ||
217 | CPU_REG (SERIAL1_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN; | ||
218 | #ifdef CONFIG_H7202_SERIAL23 | ||
219 | CPU_REG (SERIAL2_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN; | ||
220 | CPU_REG (SERIAL3_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN; | ||
221 | CPU_IO (GPIO_AMULSEL) = AMULSEL_USIN2 | AMULSEL_USOUT2 | | ||
222 | AMULSEL_USIN3 | AMULSEL_USOUT3; | ||
223 | #endif | ||
224 | (void) platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
225 | } | ||
diff --git a/arch/arm/mach-h720x/h7201-eval.c b/arch/arm/mach-h720x/h7201-eval.c deleted file mode 100644 index 4fdeb686c0a9..000000000000 --- a/arch/arm/mach-h720x/h7201-eval.c +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-h720x/h7201-eval.c | ||
3 | * | ||
4 | * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de> | ||
5 | * 2003 Robert Schwebel <r.schwebel@pengutronix.de> | ||
6 | * 2004 Sascha Hauer <s.hauer@pengutronix.de> | ||
7 | * | ||
8 | * Architecture specific stuff for Hynix GMS30C7201 development board | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #include <linux/init.h> | ||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/types.h> | ||
19 | #include <linux/string.h> | ||
20 | #include <linux/device.h> | ||
21 | |||
22 | #include <asm/setup.h> | ||
23 | #include <asm/types.h> | ||
24 | #include <asm/mach-types.h> | ||
25 | #include <asm/page.h> | ||
26 | #include <asm/mach/arch.h> | ||
27 | #include <mach/hardware.h> | ||
28 | #include "common.h" | ||
29 | |||
30 | MACHINE_START(H7201, "Hynix GMS30C7201") | ||
31 | /* Maintainer: Robert Schwebel, Pengutronix */ | ||
32 | .atag_offset = 0x1000, | ||
33 | .map_io = h720x_map_io, | ||
34 | .init_irq = h720x_init_irq, | ||
35 | .init_time = h7201_timer_init, | ||
36 | .dma_zone_size = SZ_256M, | ||
37 | .restart = h720x_restart, | ||
38 | MACHINE_END | ||
diff --git a/arch/arm/mach-h720x/h7202-eval.c b/arch/arm/mach-h720x/h7202-eval.c deleted file mode 100644 index f68e967a2062..000000000000 --- a/arch/arm/mach-h720x/h7202-eval.c +++ /dev/null | |||
@@ -1,81 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-h720x/h7202-eval.c | ||
3 | * | ||
4 | * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de> | ||
5 | * 2003 Robert Schwebel <r.schwebel@pengutronix.de> | ||
6 | * 2004 Sascha Hauer <s.hauer@pengutronix.de> | ||
7 | * | ||
8 | * Architecture specific stuff for Hynix HMS30C7202 development board | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #include <linux/init.h> | ||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/types.h> | ||
19 | #include <linux/string.h> | ||
20 | #include <linux/platform_device.h> | ||
21 | |||
22 | #include <asm/setup.h> | ||
23 | #include <asm/types.h> | ||
24 | #include <asm/mach-types.h> | ||
25 | #include <asm/page.h> | ||
26 | #include <asm/mach/arch.h> | ||
27 | #include <mach/irqs.h> | ||
28 | #include <mach/hardware.h> | ||
29 | #include "common.h" | ||
30 | |||
31 | static struct resource cirrus_resources[] = { | ||
32 | [0] = { | ||
33 | .start = ETH0_PHYS + 0x300, | ||
34 | .end = ETH0_PHYS + 0x300 + 0x10, | ||
35 | .flags = IORESOURCE_MEM, | ||
36 | }, | ||
37 | [1] = { | ||
38 | .start = IRQ_CHAINED_GPIOB(8), | ||
39 | .end = IRQ_CHAINED_GPIOB(8), | ||
40 | .flags = IORESOURCE_IRQ, | ||
41 | }, | ||
42 | }; | ||
43 | |||
44 | static struct platform_device cirrus_device = { | ||
45 | .name = "cirrus-cs89x0", | ||
46 | .id = -1, | ||
47 | .num_resources = ARRAY_SIZE(cirrus_resources), | ||
48 | .resource = cirrus_resources, | ||
49 | }; | ||
50 | |||
51 | static struct platform_device *devices[] __initdata = { | ||
52 | &cirrus_device, | ||
53 | }; | ||
54 | |||
55 | /* | ||
56 | * Hardware init. This is called early in initcalls | ||
57 | * Place pin inits here. So you avoid adding ugly | ||
58 | * #ifdef stuff to common drivers. | ||
59 | * Use this only, if your bootloader is not able | ||
60 | * to initialize the pins proper. | ||
61 | */ | ||
62 | static void __init init_eval_h7202(void) | ||
63 | { | ||
64 | init_hw_h7202(); | ||
65 | (void) platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
66 | |||
67 | /* Enable interrupt on portb bit 8 (ethernet) */ | ||
68 | CPU_REG (GPIO_B_VIRT, GPIO_POL) &= ~(1 << 8); | ||
69 | CPU_REG (GPIO_B_VIRT, GPIO_EN) |= (1 << 8); | ||
70 | } | ||
71 | |||
72 | MACHINE_START(H7202, "Hynix HMS30C7202") | ||
73 | /* Maintainer: Robert Schwebel, Pengutronix */ | ||
74 | .atag_offset = 0x100, | ||
75 | .map_io = h720x_map_io, | ||
76 | .init_irq = h7202_init_irq, | ||
77 | .init_time = h7202_timer_init, | ||
78 | .init_machine = init_eval_h7202, | ||
79 | .dma_zone_size = SZ_256M, | ||
80 | .restart = h720x_restart, | ||
81 | MACHINE_END | ||
diff --git a/arch/arm/mach-h720x/include/mach/boards.h b/arch/arm/mach-h720x/include/mach/boards.h deleted file mode 100644 index 38b8e0d61fbf..000000000000 --- a/arch/arm/mach-h720x/include/mach/boards.h +++ /dev/null | |||
@@ -1,53 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-h720x/include/mach/boards.h | ||
3 | * | ||
4 | * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de> | ||
5 | * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> | ||
6 | * | ||
7 | * This file contains the board specific defines for various devices | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_HARDWARE_INCMACH_H | ||
15 | #error Do not include this file directly. Include asm/hardware.h instead ! | ||
16 | #endif | ||
17 | |||
18 | /* Hynix H7202 developer board specific device defines */ | ||
19 | #ifdef CONFIG_ARCH_H7202 | ||
20 | |||
21 | /* FLASH */ | ||
22 | #define H720X_FLASH_VIRT 0xd0000000 | ||
23 | #define H720X_FLASH_PHYS 0x00000000 | ||
24 | #define H720X_FLASH_SIZE 0x02000000 | ||
25 | |||
26 | /* onboard LAN controller */ | ||
27 | # define ETH0_PHYS 0x08000000 | ||
28 | |||
29 | /* Touch screen defines */ | ||
30 | /* GPIO Port */ | ||
31 | #define PEN_GPIO GPIO_B_VIRT | ||
32 | /* Bitmask for pen down interrupt */ | ||
33 | #define PEN_INT_BIT (1<<7) | ||
34 | /* Bitmask for pen up interrupt */ | ||
35 | #define PEN_ENA_BIT (1<<6) | ||
36 | /* pen up interrupt */ | ||
37 | #define IRQ_PEN IRQ_MUX_GPIOB(7) | ||
38 | |||
39 | #endif | ||
40 | |||
41 | /* Hynix H7201 developer board specific device defines */ | ||
42 | #if defined (CONFIG_ARCH_H7201) | ||
43 | /* ROM DISK SPACE */ | ||
44 | #define ROM_DISK_BASE 0xc1800000 | ||
45 | #define ROM_DISK_START 0x41800000 | ||
46 | #define ROM_DISK_SIZE 0x00700000 | ||
47 | |||
48 | /* SRAM DISK SPACE */ | ||
49 | #define SRAM_DISK_BASE 0xf1000000 | ||
50 | #define SRAM_DISK_START 0x04000000 | ||
51 | #define SRAM_DISK_SIZE 0x00400000 | ||
52 | #endif | ||
53 | |||
diff --git a/arch/arm/mach-h720x/include/mach/debug-macro.S b/arch/arm/mach-h720x/include/mach/debug-macro.S deleted file mode 100644 index 8a46157b0582..000000000000 --- a/arch/arm/mach-h720x/include/mach/debug-macro.S +++ /dev/null | |||
@@ -1,40 +0,0 @@ | |||
1 | /* arch/arm/mach-h720x/include/mach/debug-macro.S | ||
2 | * | ||
3 | * Debugging macro include header | ||
4 | * | ||
5 | * Copyright (C) 1994-1999 Russell King | ||
6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <mach/hardware.h> | ||
15 | |||
16 | .equ io_virt, IO_VIRT | ||
17 | .equ io_phys, IO_PHYS | ||
18 | |||
19 | .macro addruart, rp, rv, tmp | ||
20 | mov \rp, #0x00020000 @ UART1 | ||
21 | add \rv, \rp, #io_virt @ virtual address | ||
22 | add \rp, \rp, #io_phys @ physical base address | ||
23 | .endm | ||
24 | |||
25 | .macro senduart,rd,rx | ||
26 | str \rd, [\rx, #0x0] @ UARTDR | ||
27 | |||
28 | .endm | ||
29 | |||
30 | .macro waituart,rd,rx | ||
31 | 1001: ldr \rd, [\rx, #0x18] @ UARTFLG | ||
32 | tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full | ||
33 | bne 1001b | ||
34 | .endm | ||
35 | |||
36 | .macro busyuart,rd,rx | ||
37 | 1001: ldr \rd, [\rx, #0x18] @ UARTFLG | ||
38 | tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy | ||
39 | bne 1001b | ||
40 | .endm | ||
diff --git a/arch/arm/mach-h720x/include/mach/entry-macro.S b/arch/arm/mach-h720x/include/mach/entry-macro.S deleted file mode 100644 index 75267fad7012..000000000000 --- a/arch/arm/mach-h720x/include/mach/entry-macro.S +++ /dev/null | |||
@@ -1,57 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-h720x/include/mach/entry-macro.S | ||
3 | * | ||
4 | * Low-level IRQ helper macros for Hynix HMS720x based platforms | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public | ||
7 | * License version 2. This program is licensed "as is" without any | ||
8 | * warranty of any kind, whether express or implied. | ||
9 | */ | ||
10 | |||
11 | .macro get_irqnr_preamble, base, tmp | ||
12 | .endm | ||
13 | |||
14 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
15 | #if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202) | ||
16 | @ we could use the id register on H7202, but this is not | ||
17 | @ properly updated when we come back from asm_do_irq | ||
18 | @ without a previous return from interrupt | ||
19 | @ (see loops below in irq_svc, irq_usr) | ||
20 | @ We see unmasked pending ints only, as the masked pending ints | ||
21 | @ are not visible here | ||
22 | |||
23 | mov \base, #0xf0000000 @ base register | ||
24 | orr \base, \base, #0x24000 @ irqbase | ||
25 | ldr \irqstat, [\base, #0x04] @ get interrupt status | ||
26 | #if defined (CONFIG_CPU_H7201) | ||
27 | ldr \tmp, =0x001fffff | ||
28 | #else | ||
29 | mvn \tmp, #0xc0000000 | ||
30 | #endif | ||
31 | and \irqstat, \irqstat, \tmp @ mask out unused ints | ||
32 | mov \irqnr, #0 | ||
33 | |||
34 | mov \tmp, #0xff00 | ||
35 | orr \tmp, \tmp, #0xff | ||
36 | tst \irqstat, \tmp | ||
37 | addeq \irqnr, \irqnr, #16 | ||
38 | moveq \irqstat, \irqstat, lsr #16 | ||
39 | tst \irqstat, #255 | ||
40 | addeq \irqnr, \irqnr, #8 | ||
41 | moveq \irqstat, \irqstat, lsr #8 | ||
42 | tst \irqstat, #15 | ||
43 | addeq \irqnr, \irqnr, #4 | ||
44 | moveq \irqstat, \irqstat, lsr #4 | ||
45 | tst \irqstat, #3 | ||
46 | addeq \irqnr, \irqnr, #2 | ||
47 | moveq \irqstat, \irqstat, lsr #2 | ||
48 | tst \irqstat, #1 | ||
49 | addeq \irqnr, \irqnr, #1 | ||
50 | moveq \irqstat, \irqstat, lsr #1 | ||
51 | tst \irqstat, #1 @ bit 0 should be set | ||
52 | .endm | ||
53 | |||
54 | #else | ||
55 | #error hynix processor selection missmatch | ||
56 | #endif | ||
57 | |||
diff --git a/arch/arm/mach-h720x/include/mach/h7201-regs.h b/arch/arm/mach-h720x/include/mach/h7201-regs.h deleted file mode 100644 index 611b4947ccfc..000000000000 --- a/arch/arm/mach-h720x/include/mach/h7201-regs.h +++ /dev/null | |||
@@ -1,67 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-h720x/include/mach/h7201-regs.h | ||
3 | * | ||
4 | * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc. | ||
5 | * (C) 2003 Thomas Gleixner <tglx@linutronix.de> | ||
6 | * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> | ||
7 | * (C) 2004 Sascha Hauer <s.hauer@pengutronix.de> | ||
8 | * | ||
9 | * This file contains the hardware definitions of the h720x processors | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | * | ||
15 | * Do not add implementations specific defines here. This files contains | ||
16 | * only defines of the onchip peripherals. Add those defines to boards.h, | ||
17 | * which is included by this file. | ||
18 | */ | ||
19 | |||
20 | #define SERIAL2_VIRT (IO_VIRT + 0x50100) | ||
21 | #define SERIAL3_VIRT (IO_VIRT + 0x50200) | ||
22 | |||
23 | /* | ||
24 | * PCMCIA | ||
25 | */ | ||
26 | #define PCMCIA0_ATT_BASE 0xe5000000 | ||
27 | #define PCMCIA0_ATT_SIZE 0x00200000 | ||
28 | #define PCMCIA0_ATT_START 0x20000000 | ||
29 | #define PCMCIA0_MEM_BASE 0xe5200000 | ||
30 | #define PCMCIA0_MEM_SIZE 0x00200000 | ||
31 | #define PCMCIA0_MEM_START 0x24000000 | ||
32 | #define PCMCIA0_IO_BASE 0xe5400000 | ||
33 | #define PCMCIA0_IO_SIZE 0x00200000 | ||
34 | #define PCMCIA0_IO_START 0x28000000 | ||
35 | |||
36 | #define PCMCIA1_ATT_BASE 0xe5600000 | ||
37 | #define PCMCIA1_ATT_SIZE 0x00200000 | ||
38 | #define PCMCIA1_ATT_START 0x30000000 | ||
39 | #define PCMCIA1_MEM_BASE 0xe5800000 | ||
40 | #define PCMCIA1_MEM_SIZE 0x00200000 | ||
41 | #define PCMCIA1_MEM_START 0x34000000 | ||
42 | #define PCMCIA1_IO_BASE 0xe5a00000 | ||
43 | #define PCMCIA1_IO_SIZE 0x00200000 | ||
44 | #define PCMCIA1_IO_START 0x38000000 | ||
45 | |||
46 | #define PRIME3C_BASE 0xf0050000 | ||
47 | #define PRIME3C_SIZE 0x00001000 | ||
48 | #define PRIME3C_START 0x10000000 | ||
49 | |||
50 | /* VGA Controller */ | ||
51 | #define VGA_RAMBASE 0x50 | ||
52 | #define VGA_TIMING0 0x60 | ||
53 | #define VGA_TIMING1 0x64 | ||
54 | #define VGA_TIMING2 0x68 | ||
55 | #define VGA_TIMING3 0x6c | ||
56 | |||
57 | #define LCD_CTRL_VGA_ENABLE 0x00000100 | ||
58 | #define LCD_CTRL_VGA_BPP_MASK 0x00000600 | ||
59 | #define LCD_CTRL_VGA_4BPP 0x00000000 | ||
60 | #define LCD_CTRL_VGA_8BPP 0x00000200 | ||
61 | #define LCD_CTRL_VGA_16BPP 0x00000300 | ||
62 | #define LCD_CTRL_SHARE_DMA 0x00000800 | ||
63 | #define LCD_CTRL_VDE 0x00100000 | ||
64 | #define LCD_CTRL_LPE 0x00400000 /* LCD Power enable */ | ||
65 | #define LCD_CTRL_BLE 0x00800000 /* LCD backlight enable */ | ||
66 | |||
67 | #define VGA_PALETTE_BASE (IO_VIRT + 0x10800) | ||
diff --git a/arch/arm/mach-h720x/include/mach/h7202-regs.h b/arch/arm/mach-h720x/include/mach/h7202-regs.h deleted file mode 100644 index 17c12eb34995..000000000000 --- a/arch/arm/mach-h720x/include/mach/h7202-regs.h +++ /dev/null | |||
@@ -1,155 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-h720x/include/mach/h7202-regs.h | ||
3 | * | ||
4 | * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc. | ||
5 | * (C) 2003 Thomas Gleixner <tglx@linutronix.de> | ||
6 | * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> | ||
7 | * (C) 2004 Sascha Hauer <s.hauer@pengutronix.de> | ||
8 | * | ||
9 | * This file contains the hardware definitions of the h720x processors | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | * | ||
15 | * Do not add implementations specific defines here. This files contains | ||
16 | * only defines of the onchip peripherals. Add those defines to boards.h, | ||
17 | * which is included by this file. | ||
18 | */ | ||
19 | |||
20 | #define SERIAL2_OFS 0x2d000 | ||
21 | #define SERIAL2_BASE (IO_PHYS + SERIAL2_OFS) | ||
22 | #define SERIAL2_VIRT (IO_VIRT + SERIAL2_OFS) | ||
23 | #define SERIAL3_OFS 0x2e000 | ||
24 | #define SERIAL3_BASE (IO_PHYS + SERIAL3_OFS) | ||
25 | #define SERIAL3_VIRT (IO_VIRT + SERIAL3_OFS) | ||
26 | |||
27 | /* Matrix Keyboard Controller */ | ||
28 | #define KBD_VIRT (IO_VIRT + 0x22000) | ||
29 | #define KBD_KBCR 0x00 | ||
30 | #define KBD_KBSC 0x04 | ||
31 | #define KBD_KBTR 0x08 | ||
32 | #define KBD_KBVR0 0x0C | ||
33 | #define KBD_KBVR1 0x10 | ||
34 | #define KBD_KBSR 0x18 | ||
35 | |||
36 | #define KBD_KBCR_SCANENABLE (1 << 7) | ||
37 | #define KBD_KBCR_NPOWERDOWN (1 << 2) | ||
38 | #define KBD_KBCR_CLKSEL_MASK (3) | ||
39 | #define KBD_KBCR_CLKSEL_PCLK2 0x0 | ||
40 | #define KBD_KBCR_CLKSEL_PCLK128 0x1 | ||
41 | #define KBD_KBCR_CLKSEL_PCLK256 0x2 | ||
42 | #define KBD_KBCR_CLKSEL_PCLK512 0x3 | ||
43 | |||
44 | #define KBD_KBSR_INTR (1 << 0) | ||
45 | #define KBD_KBSR_WAKEUP (1 << 1) | ||
46 | |||
47 | /* USB device controller */ | ||
48 | |||
49 | #define USBD_BASE (IO_VIRT + 0x12000) | ||
50 | #define USBD_LENGTH 0x3C | ||
51 | |||
52 | #define USBD_GCTRL 0x00 | ||
53 | #define USBD_EPCTRL 0x04 | ||
54 | #define USBD_INTMASK 0x08 | ||
55 | #define USBD_INTSTAT 0x0C | ||
56 | #define USBD_PWR 0x10 | ||
57 | #define USBD_DMARXTX 0x14 | ||
58 | #define USBD_DEVID 0x18 | ||
59 | #define USBD_DEVCLASS 0x1C | ||
60 | #define USBD_INTCLASS 0x20 | ||
61 | #define USBD_SETUP0 0x24 | ||
62 | #define USBD_SETUP1 0x28 | ||
63 | #define USBD_ENDP0RD 0x2C | ||
64 | #define USBD_ENDP0WT 0x30 | ||
65 | #define USBD_ENDP1RD 0x34 | ||
66 | #define USBD_ENDP2WT 0x38 | ||
67 | |||
68 | /* PS/2 port */ | ||
69 | #define PSDATA 0x00 | ||
70 | #define PSSTAT 0x04 | ||
71 | #define PSSTAT_TXEMPTY (1<<0) | ||
72 | #define PSSTAT_TXBUSY (1<<1) | ||
73 | #define PSSTAT_RXFULL (1<<2) | ||
74 | #define PSSTAT_RXBUSY (1<<3) | ||
75 | #define PSSTAT_CLKIN (1<<4) | ||
76 | #define PSSTAT_DATAIN (1<<5) | ||
77 | #define PSSTAT_PARITY (1<<6) | ||
78 | |||
79 | #define PSCONF 0x08 | ||
80 | #define PSCONF_ENABLE (1<<0) | ||
81 | #define PSCONF_TXINTEN (1<<2) | ||
82 | #define PSCONF_RXINTEN (1<<3) | ||
83 | #define PSCONF_FORCECLKLOW (1<<4) | ||
84 | #define PSCONF_FORCEDATLOW (1<<5) | ||
85 | #define PSCONF_LCE (1<<6) | ||
86 | |||
87 | #define PSINTR 0x0C | ||
88 | #define PSINTR_TXINT (1<<0) | ||
89 | #define PSINTR_RXINT (1<<1) | ||
90 | #define PSINTR_PAR (1<<2) | ||
91 | #define PSINTR_RXTO (1<<3) | ||
92 | #define PSINTR_TXTO (1<<4) | ||
93 | |||
94 | #define PSTDLO 0x10 /* clk low before start transmission */ | ||
95 | #define PSTPRI 0x14 /* PRI clock */ | ||
96 | #define PSTXMT 0x18 /* maximum transmission time */ | ||
97 | #define PSTREC 0x20 /* maximum receive time */ | ||
98 | #define PSPWDN 0x3c | ||
99 | |||
100 | /* ADC converter */ | ||
101 | #define ADC_BASE (IO_VIRT + 0x29000) | ||
102 | #define ADC_CR 0x00 | ||
103 | #define ADC_TSCTRL 0x04 | ||
104 | #define ADC_BT_CTRL 0x08 | ||
105 | #define ADC_MC_CTRL 0x0C | ||
106 | #define ADC_STATUS 0x10 | ||
107 | |||
108 | /* ADC control register bits */ | ||
109 | #define ADC_CR_PW_CTRL 0x80 | ||
110 | #define ADC_CR_DIRECTC 0x04 | ||
111 | #define ADC_CR_CONTIME_NO 0x00 | ||
112 | #define ADC_CR_CONTIME_2 0x04 | ||
113 | #define ADC_CR_CONTIME_4 0x08 | ||
114 | #define ADC_CR_CONTIME_ADE 0x0c | ||
115 | #define ADC_CR_LONGCALTIME 0x01 | ||
116 | |||
117 | /* ADC touch panel register bits */ | ||
118 | #define ADC_TSCTRL_ENABLE 0x80 | ||
119 | #define ADC_TSCTRL_INTR 0x40 | ||
120 | #define ADC_TSCTRL_SWBYPSS 0x20 | ||
121 | #define ADC_TSCTRL_SWINVT 0x10 | ||
122 | #define ADC_TSCTRL_S400 0x03 | ||
123 | #define ADC_TSCTRL_S200 0x02 | ||
124 | #define ADC_TSCTRL_S100 0x01 | ||
125 | #define ADC_TSCTRL_S50 0x00 | ||
126 | |||
127 | /* ADC Interrupt Status Register bits */ | ||
128 | #define ADC_STATUS_TS_BIT 0x80 | ||
129 | #define ADC_STATUS_MBT_BIT 0x40 | ||
130 | #define ADC_STATUS_BBT_BIT 0x20 | ||
131 | #define ADC_STATUS_MIC_BIT 0x10 | ||
132 | |||
133 | /* Touch data registers */ | ||
134 | #define ADC_TS_X0X1 0x30 | ||
135 | #define ADC_TS_X2X3 0x34 | ||
136 | #define ADC_TS_Y0Y1 0x38 | ||
137 | #define ADC_TS_Y2Y3 0x3c | ||
138 | #define ADC_TS_X4X5 0x40 | ||
139 | #define ADC_TS_X6X7 0x44 | ||
140 | #define ADC_TS_Y4Y5 0x48 | ||
141 | #define ADC_TS_Y6Y7 0x50 | ||
142 | |||
143 | /* battery data */ | ||
144 | #define ADC_MB_DATA 0x54 | ||
145 | #define ADC_BB_DATA 0x58 | ||
146 | |||
147 | /* Sound data register */ | ||
148 | #define ADC_SD_DAT0 0x60 | ||
149 | #define ADC_SD_DAT1 0x64 | ||
150 | #define ADC_SD_DAT2 0x68 | ||
151 | #define ADC_SD_DAT3 0x6c | ||
152 | #define ADC_SD_DAT4 0x70 | ||
153 | #define ADC_SD_DAT5 0x74 | ||
154 | #define ADC_SD_DAT6 0x78 | ||
155 | #define ADC_SD_DAT7 0x7c | ||
diff --git a/arch/arm/mach-h720x/include/mach/hardware.h b/arch/arm/mach-h720x/include/mach/hardware.h deleted file mode 100644 index c55a52c6541d..000000000000 --- a/arch/arm/mach-h720x/include/mach/hardware.h +++ /dev/null | |||
@@ -1,190 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-h720x/include/mach/hardware.h | ||
3 | * | ||
4 | * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc. | ||
5 | * (C) 2003 Thomas Gleixner <tglx@linutronix.de> | ||
6 | * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> | ||
7 | * | ||
8 | * This file contains the hardware definitions of the h720x processors | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | * | ||
14 | * Do not add implementations specific defines here. This files contains | ||
15 | * only defines of the onchip peripherals. Add those defines to boards.h, | ||
16 | * which is included by this file. | ||
17 | */ | ||
18 | |||
19 | #ifndef __ASM_ARCH_HARDWARE_H | ||
20 | #define __ASM_ARCH_HARDWARE_H | ||
21 | |||
22 | #define IOCLK (3686400L) | ||
23 | |||
24 | /* Onchip peripherals */ | ||
25 | |||
26 | #define IO_VIRT 0xf0000000 /* IO peripherals */ | ||
27 | #define IO_PHYS 0x80000000 | ||
28 | #define IO_SIZE 0x00050000 | ||
29 | |||
30 | #ifdef CONFIG_CPU_H7202 | ||
31 | #include "h7202-regs.h" | ||
32 | #elif defined CONFIG_CPU_H7201 | ||
33 | #include "h7201-regs.h" | ||
34 | #else | ||
35 | #error machine definition mismatch | ||
36 | #endif | ||
37 | |||
38 | /* Macro to access the CPU IO */ | ||
39 | #define CPU_IO(x) (*(volatile u32*)(x)) | ||
40 | |||
41 | /* Macro to access general purpose regs (base, offset) */ | ||
42 | #define CPU_REG(x,y) CPU_IO(x+y) | ||
43 | |||
44 | /* Macro to access irq related regs */ | ||
45 | #define IRQ_REG(x) CPU_REG(IRQC_VIRT,x) | ||
46 | |||
47 | /* CPU registers */ | ||
48 | /* general purpose I/O */ | ||
49 | #define GPIO_VIRT(x) (IO_VIRT + 0x23000 + ((x)<<5)) | ||
50 | #define GPIO_A_VIRT (GPIO_VIRT(0)) | ||
51 | #define GPIO_B_VIRT (GPIO_VIRT(1)) | ||
52 | #define GPIO_C_VIRT (GPIO_VIRT(2)) | ||
53 | #define GPIO_D_VIRT (GPIO_VIRT(3)) | ||
54 | #define GPIO_E_VIRT (GPIO_VIRT(4)) | ||
55 | #define GPIO_AMULSEL (GPIO_VIRT(0) + 0xA4) | ||
56 | |||
57 | #define AMULSEL_USIN2 (1<<5) | ||
58 | #define AMULSEL_USOUT2 (1<<6) | ||
59 | #define AMULSEL_USIN3 (1<<13) | ||
60 | #define AMULSEL_USOUT3 (1<<14) | ||
61 | #define AMULSEL_IRDIN (1<<15) | ||
62 | #define AMULSEL_IRDOUT (1<<7) | ||
63 | |||
64 | /* Register offsets general purpose I/O */ | ||
65 | #define GPIO_DATA 0x00 | ||
66 | #define GPIO_DIR 0x04 | ||
67 | #define GPIO_MASK 0x08 | ||
68 | #define GPIO_STAT 0x0C | ||
69 | #define GPIO_EDGE 0x10 | ||
70 | #define GPIO_CLR 0x14 | ||
71 | #define GPIO_POL 0x18 | ||
72 | #define GPIO_EN 0x1C | ||
73 | |||
74 | /*interrupt controller */ | ||
75 | #define IRQC_VIRT (IO_VIRT + 0x24000) | ||
76 | /* register offset interrupt controller */ | ||
77 | #define IRQC_IER 0x00 | ||
78 | #define IRQC_ISR 0x04 | ||
79 | |||
80 | /* timer unit */ | ||
81 | #define TIMER_VIRT (IO_VIRT + 0x25000) | ||
82 | /* Register offsets timer unit */ | ||
83 | #define TM0_PERIOD 0x00 | ||
84 | #define TM0_COUNT 0x08 | ||
85 | #define TM0_CTRL 0x10 | ||
86 | #define TM1_PERIOD 0x20 | ||
87 | #define TM1_COUNT 0x28 | ||
88 | #define TM1_CTRL 0x30 | ||
89 | #define TM2_PERIOD 0x40 | ||
90 | #define TM2_COUNT 0x48 | ||
91 | #define TM2_CTRL 0x50 | ||
92 | #define TIMER_TOPCTRL 0x60 | ||
93 | #define TIMER_TOPSTAT 0x64 | ||
94 | #define T64_COUNTL 0x80 | ||
95 | #define T64_COUNTH 0x84 | ||
96 | #define T64_CTRL 0x88 | ||
97 | #define T64_BASEL 0x94 | ||
98 | #define T64_BASEH 0x98 | ||
99 | /* Bitmaks timer unit TOPSTAT reg */ | ||
100 | #define TSTAT_T0INT 0x1 | ||
101 | #define TSTAT_T1INT 0x2 | ||
102 | #define TSTAT_T2INT 0x4 | ||
103 | #define TSTAT_T3INT 0x8 | ||
104 | /* Bit description of TMx_CTRL register */ | ||
105 | #define TM_START 0x1 | ||
106 | #define TM_REPEAT 0x2 | ||
107 | #define TM_RESET 0x4 | ||
108 | /* Bit description of TIMER_CTRL register */ | ||
109 | #define ENABLE_TM0_INTR 0x1 | ||
110 | #define ENABLE_TM1_INTR 0x2 | ||
111 | #define ENABLE_TM2_INTR 0x4 | ||
112 | #define TIMER_ENABLE_BIT 0x8 | ||
113 | #define ENABLE_TIMER64 0x10 | ||
114 | #define ENABLE_TIMER64_INT 0x20 | ||
115 | |||
116 | /* PMU & PLL */ | ||
117 | #define PMU_BASE (IO_VIRT + 0x1000) | ||
118 | #define PMU_MODE 0x00 | ||
119 | #define PMU_STAT 0x20 | ||
120 | #define PMU_PLL_CTRL 0x28 | ||
121 | |||
122 | /* PMU Mode bits */ | ||
123 | #define PMU_MODE_SLOW 0x00 | ||
124 | #define PMU_MODE_RUN 0x01 | ||
125 | #define PMU_MODE_IDLE 0x02 | ||
126 | #define PMU_MODE_SLEEP 0x03 | ||
127 | #define PMU_MODE_INIT 0x04 | ||
128 | #define PMU_MODE_DEEPSLEEP 0x07 | ||
129 | #define PMU_MODE_WAKEUP 0x08 | ||
130 | |||
131 | /* PMU ... */ | ||
132 | #define PLL_2_EN 0x8000 | ||
133 | #define PLL_1_EN 0x4000 | ||
134 | #define PLL_3_MUTE 0x0080 | ||
135 | |||
136 | /* Control bits for PMU/ PLL */ | ||
137 | #define PMU_WARMRESET 0x00010000 | ||
138 | #define PLL_CTRL_MASK23 0x000080ff | ||
139 | |||
140 | /* LCD Controller */ | ||
141 | #define LCD_BASE (IO_VIRT + 0x10000) | ||
142 | #define LCD_CTRL 0x00 | ||
143 | #define LCD_STATUS 0x04 | ||
144 | #define LCD_STATUS_M 0x08 | ||
145 | #define LCD_INTERRUPT 0x0C | ||
146 | #define LCD_DBAR 0x10 | ||
147 | #define LCD_DCAR 0x14 | ||
148 | #define LCD_TIMING0 0x20 | ||
149 | #define LCD_TIMING1 0x24 | ||
150 | #define LCD_TIMING2 0x28 | ||
151 | #define LCD_TEST 0x40 | ||
152 | |||
153 | /* LCD Control Bits */ | ||
154 | #define LCD_CTRL_LCD_ENABLE 0x00000001 | ||
155 | /* Bits per pixel */ | ||
156 | #define LCD_CTRL_LCD_BPP_MASK 0x00000006 | ||
157 | #define LCD_CTRL_LCD_4BPP 0x00000000 | ||
158 | #define LCD_CTRL_LCD_8BPP 0x00000002 | ||
159 | #define LCD_CTRL_LCD_16BPP 0x00000004 | ||
160 | #define LCD_CTRL_LCD_BW 0x00000008 | ||
161 | #define LCD_CTRL_LCD_TFT 0x00000010 | ||
162 | #define LCD_CTRL_BGR 0x00001000 | ||
163 | #define LCD_CTRL_LCD_VCOMP 0x00080000 | ||
164 | #define LCD_CTRL_LCD_MONO8 0x00200000 | ||
165 | #define LCD_CTRL_LCD_PWR 0x00400000 | ||
166 | #define LCD_CTRL_LCD_BLE 0x00800000 | ||
167 | #define LCD_CTRL_LDBUSEN 0x01000000 | ||
168 | |||
169 | /* Palette */ | ||
170 | #define LCD_PALETTE_BASE (IO_VIRT + 0x10400) | ||
171 | |||
172 | /* Serial ports */ | ||
173 | #define SERIAL0_OFS 0x20000 | ||
174 | #define SERIAL0_VIRT (IO_VIRT + SERIAL0_OFS) | ||
175 | #define SERIAL0_BASE (IO_PHYS + SERIAL0_OFS) | ||
176 | |||
177 | #define SERIAL1_OFS 0x21000 | ||
178 | #define SERIAL1_VIRT (IO_VIRT + SERIAL1_OFS) | ||
179 | #define SERIAL1_BASE (IO_PHYS + SERIAL1_OFS) | ||
180 | |||
181 | #define SERIAL_ENABLE 0x30 | ||
182 | #define SERIAL_ENABLE_EN (1<<0) | ||
183 | |||
184 | /* General defines to pacify gcc */ | ||
185 | |||
186 | #define __ASM_ARCH_HARDWARE_INCMACH_H | ||
187 | #include "boards.h" | ||
188 | #undef __ASM_ARCH_HARDWARE_INCMACH_H | ||
189 | |||
190 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
diff --git a/arch/arm/mach-h720x/include/mach/irqs.h b/arch/arm/mach-h720x/include/mach/irqs.h deleted file mode 100644 index 430a92b492f1..000000000000 --- a/arch/arm/mach-h720x/include/mach/irqs.h +++ /dev/null | |||
@@ -1,116 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-h720x/include/mach/irqs.h | ||
3 | * | ||
4 | * Copyright (C) 2000 Jungjun Kim | ||
5 | * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> | ||
6 | * (C) 2003 Thomas Gleixner <tglx@linutronix.de> | ||
7 | * | ||
8 | */ | ||
9 | |||
10 | #ifndef __ASM_ARCH_IRQS_H | ||
11 | #define __ASM_ARCH_IRQS_H | ||
12 | |||
13 | #if defined (CONFIG_CPU_H7201) | ||
14 | |||
15 | #define IRQ_PMU 0 /* 0x000001 */ | ||
16 | #define IRQ_DMA 1 /* 0x000002 */ | ||
17 | #define IRQ_LCD 2 /* 0x000004 */ | ||
18 | #define IRQ_VGA 3 /* 0x000008 */ | ||
19 | #define IRQ_PCMCIA1 4 /* 0x000010 */ | ||
20 | #define IRQ_PCMCIA2 5 /* 0x000020 */ | ||
21 | #define IRQ_AFE 6 /* 0x000040 */ | ||
22 | #define IRQ_AIC 7 /* 0x000080 */ | ||
23 | #define IRQ_KEYBOARD 8 /* 0x000100 */ | ||
24 | #define IRQ_TIMER0 9 /* 0x000200 */ | ||
25 | #define IRQ_RTC 10 /* 0x000400 */ | ||
26 | #define IRQ_SOUND 11 /* 0x000800 */ | ||
27 | #define IRQ_USB 12 /* 0x001000 */ | ||
28 | #define IRQ_IrDA 13 /* 0x002000 */ | ||
29 | #define IRQ_UART0 14 /* 0x004000 */ | ||
30 | #define IRQ_UART1 15 /* 0x008000 */ | ||
31 | #define IRQ_SPI 16 /* 0x010000 */ | ||
32 | #define IRQ_GPIOA 17 /* 0x020000 */ | ||
33 | #define IRQ_GPIOB 18 /* 0x040000 */ | ||
34 | #define IRQ_GPIOC 19 /* 0x080000 */ | ||
35 | #define IRQ_GPIOD 20 /* 0x100000 */ | ||
36 | #define IRQ_CommRX 21 /* 0x200000 */ | ||
37 | #define IRQ_CommTX 22 /* 0x400000 */ | ||
38 | #define IRQ_Soft 23 /* 0x800000 */ | ||
39 | |||
40 | #define NR_GLBL_IRQS 24 | ||
41 | |||
42 | #define IRQ_CHAINED_GPIOA(x) (NR_GLBL_IRQS + x) | ||
43 | #define IRQ_CHAINED_GPIOB(x) (IRQ_CHAINED_GPIOA(32) + x) | ||
44 | #define IRQ_CHAINED_GPIOC(x) (IRQ_CHAINED_GPIOB(32) + x) | ||
45 | #define IRQ_CHAINED_GPIOD(x) (IRQ_CHAINED_GPIOC(32) + x) | ||
46 | #define NR_IRQS IRQ_CHAINED_GPIOD(32) | ||
47 | |||
48 | /* Enable mask for multiplexed interrupts */ | ||
49 | #define IRQ_ENA_MUX (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) \ | ||
50 | | (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD) | ||
51 | |||
52 | |||
53 | #elif defined (CONFIG_CPU_H7202) | ||
54 | |||
55 | #define IRQ_PMU 0 /* 0x00000001 */ | ||
56 | #define IRQ_DMA 1 /* 0x00000002 */ | ||
57 | #define IRQ_LCD 2 /* 0x00000004 */ | ||
58 | #define IRQ_SOUND 3 /* 0x00000008 */ | ||
59 | #define IRQ_I2S 4 /* 0x00000010 */ | ||
60 | #define IRQ_USB 5 /* 0x00000020 */ | ||
61 | #define IRQ_MMC 6 /* 0x00000040 */ | ||
62 | #define IRQ_RTC 7 /* 0x00000080 */ | ||
63 | #define IRQ_UART0 8 /* 0x00000100 */ | ||
64 | #define IRQ_UART1 9 /* 0x00000200 */ | ||
65 | #define IRQ_UART2 10 /* 0x00000400 */ | ||
66 | #define IRQ_UART3 11 /* 0x00000800 */ | ||
67 | #define IRQ_KBD 12 /* 0x00001000 */ | ||
68 | #define IRQ_PS2 13 /* 0x00002000 */ | ||
69 | #define IRQ_AIC 14 /* 0x00004000 */ | ||
70 | #define IRQ_TIMER0 15 /* 0x00008000 */ | ||
71 | #define IRQ_TIMERX 16 /* 0x00010000 */ | ||
72 | #define IRQ_WDT 17 /* 0x00020000 */ | ||
73 | #define IRQ_CAN0 18 /* 0x00040000 */ | ||
74 | #define IRQ_CAN1 19 /* 0x00080000 */ | ||
75 | #define IRQ_EXT0 20 /* 0x00100000 */ | ||
76 | #define IRQ_EXT1 21 /* 0x00200000 */ | ||
77 | #define IRQ_GPIOA 22 /* 0x00400000 */ | ||
78 | #define IRQ_GPIOB 23 /* 0x00800000 */ | ||
79 | #define IRQ_GPIOC 24 /* 0x01000000 */ | ||
80 | #define IRQ_GPIOD 25 /* 0x02000000 */ | ||
81 | #define IRQ_GPIOE 26 /* 0x04000000 */ | ||
82 | #define IRQ_COMMRX 27 /* 0x08000000 */ | ||
83 | #define IRQ_COMMTX 28 /* 0x10000000 */ | ||
84 | #define IRQ_SMC 29 /* 0x20000000 */ | ||
85 | #define IRQ_Soft 30 /* 0x40000000 */ | ||
86 | #define IRQ_RESERVED1 31 /* 0x80000000 */ | ||
87 | #define NR_GLBL_IRQS 32 | ||
88 | |||
89 | #define NR_TIMERX_IRQS 3 | ||
90 | |||
91 | #define IRQ_CHAINED_GPIOA(x) (NR_GLBL_IRQS + x) | ||
92 | #define IRQ_CHAINED_GPIOB(x) (IRQ_CHAINED_GPIOA(32) + x) | ||
93 | #define IRQ_CHAINED_GPIOC(x) (IRQ_CHAINED_GPIOB(32) + x) | ||
94 | #define IRQ_CHAINED_GPIOD(x) (IRQ_CHAINED_GPIOC(32) + x) | ||
95 | #define IRQ_CHAINED_GPIOE(x) (IRQ_CHAINED_GPIOD(32) + x) | ||
96 | #define IRQ_CHAINED_TIMERX(x) (IRQ_CHAINED_GPIOE(32) + x) | ||
97 | #define IRQ_TIMER1 (IRQ_CHAINED_TIMERX(0)) | ||
98 | #define IRQ_TIMER2 (IRQ_CHAINED_TIMERX(1)) | ||
99 | #define IRQ_TIMER64B (IRQ_CHAINED_TIMERX(2)) | ||
100 | |||
101 | #define NR_IRQS (IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS)) | ||
102 | |||
103 | /* Enable mask for multiplexed interrupts */ | ||
104 | #define IRQ_ENA_MUX (1<<IRQ_TIMERX) | (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) | \ | ||
105 | (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD) | (1<<IRQ_GPIOE) | \ | ||
106 | (1<<IRQ_TIMERX) | ||
107 | |||
108 | #else | ||
109 | #error cpu definition mismatch | ||
110 | #endif | ||
111 | |||
112 | /* decode irq number to register number */ | ||
113 | #define IRQ_TO_REGNO(irq) ((irq - NR_GLBL_IRQS) >> 5) | ||
114 | #define IRQ_TO_BIT(irq) (1 << ((irq - NR_GLBL_IRQS) % 32)) | ||
115 | |||
116 | #endif | ||
diff --git a/arch/arm/mach-h720x/include/mach/isa-dma.h b/arch/arm/mach-h720x/include/mach/isa-dma.h deleted file mode 100644 index 3eafb3f163c0..000000000000 --- a/arch/arm/mach-h720x/include/mach/isa-dma.h +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-h720x/include/mach/isa-dma.h | ||
3 | * | ||
4 | * Architecture DMA routes | ||
5 | * | ||
6 | * Copyright (C) 1997.1998 Russell King | ||
7 | */ | ||
8 | #ifndef __ASM_ARCH_DMA_H | ||
9 | #define __ASM_ARCH_DMA_H | ||
10 | |||
11 | #if defined (CONFIG_CPU_H7201) | ||
12 | #define MAX_DMA_CHANNELS 3 | ||
13 | #elif defined (CONFIG_CPU_H7202) | ||
14 | #define MAX_DMA_CHANNELS 4 | ||
15 | #else | ||
16 | #error processor definition missmatch | ||
17 | #endif | ||
18 | |||
19 | #endif /* __ASM_ARCH_DMA_H */ | ||
diff --git a/arch/arm/mach-h720x/include/mach/uncompress.h b/arch/arm/mach-h720x/include/mach/uncompress.h deleted file mode 100644 index 43e343c4b50a..000000000000 --- a/arch/arm/mach-h720x/include/mach/uncompress.h +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-h720x/include/mach/uncompress.h | ||
3 | * | ||
4 | * Copyright (C) 2001-2002 Jungjun Kim | ||
5 | */ | ||
6 | |||
7 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
8 | #define __ASM_ARCH_UNCOMPRESS_H | ||
9 | |||
10 | #include <mach/hardware.h> | ||
11 | |||
12 | #define LSR 0x14 | ||
13 | #define TEMPTY 0x40 | ||
14 | |||
15 | static inline void putc(int c) | ||
16 | { | ||
17 | volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000); | ||
18 | |||
19 | /* wait until transmit buffer is empty */ | ||
20 | while((p[LSR] & TEMPTY) == 0x0) | ||
21 | barrier(); | ||
22 | |||
23 | /* write next character */ | ||
24 | *p = c; | ||
25 | } | ||
26 | |||
27 | static inline void flush(void) | ||
28 | { | ||
29 | } | ||
30 | |||
31 | /* | ||
32 | * nothing to do | ||
33 | */ | ||
34 | #define arch_decomp_setup() | ||
35 | |||
36 | #endif | ||
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index a4f9f50247d4..76c1170b3528 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c | |||
@@ -32,7 +32,6 @@ | |||
32 | #include <asm/cacheflush.h> | 32 | #include <asm/cacheflush.h> |
33 | #include <asm/cputype.h> | 33 | #include <asm/cputype.h> |
34 | #include <asm/smp_plat.h> | 34 | #include <asm/smp_plat.h> |
35 | #include <asm/smp_twd.h> | ||
36 | #include <asm/hardware/arm_timer.h> | 35 | #include <asm/hardware/arm_timer.h> |
37 | #include <asm/hardware/timer-sp.h> | 36 | #include <asm/hardware/timer-sp.h> |
38 | #include <asm/hardware/cache-l2x0.h> | 37 | #include <asm/hardware/cache-l2x0.h> |
@@ -119,10 +118,10 @@ static void __init highbank_timer_init(void) | |||
119 | sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1"); | 118 | sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1"); |
120 | sp804_clockevents_init(timer_base, irq, "timer0"); | 119 | sp804_clockevents_init(timer_base, irq, "timer0"); |
121 | 120 | ||
122 | twd_local_timer_of_register(); | ||
123 | |||
124 | arch_timer_of_register(); | 121 | arch_timer_of_register(); |
125 | arch_timer_sched_clock_init(); | 122 | arch_timer_sched_clock_init(); |
123 | |||
124 | clocksource_of_init(); | ||
126 | } | 125 | } |
127 | 126 | ||
128 | static void highbank_power_off(void) | 127 | static void highbank_power_off(void) |
diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c index 8797a7001720..a984573e0d02 100644 --- a/arch/arm/mach-highbank/platsmp.c +++ b/arch/arm/mach-highbank/platsmp.c | |||
@@ -17,7 +17,6 @@ | |||
17 | #include <linux/init.h> | 17 | #include <linux/init.h> |
18 | #include <linux/smp.h> | 18 | #include <linux/smp.h> |
19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
20 | #include <linux/irqchip/arm-gic.h> | ||
21 | 20 | ||
22 | #include <asm/smp_scu.h> | 21 | #include <asm/smp_scu.h> |
23 | 22 | ||
@@ -25,11 +24,6 @@ | |||
25 | 24 | ||
26 | extern void secondary_startup(void); | 25 | extern void secondary_startup(void); |
27 | 26 | ||
28 | static void __cpuinit highbank_secondary_init(unsigned int cpu) | ||
29 | { | ||
30 | gic_secondary_init(0); | ||
31 | } | ||
32 | |||
33 | static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle) | 27 | static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle) |
34 | { | 28 | { |
35 | highbank_set_cpu_jump(cpu, secondary_startup); | 29 | highbank_set_cpu_jump(cpu, secondary_startup); |
@@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus) | |||
67 | struct smp_operations highbank_smp_ops __initdata = { | 61 | struct smp_operations highbank_smp_ops __initdata = { |
68 | .smp_init_cpus = highbank_smp_init_cpus, | 62 | .smp_init_cpus = highbank_smp_init_cpus, |
69 | .smp_prepare_cpus = highbank_smp_prepare_cpus, | 63 | .smp_prepare_cpus = highbank_smp_prepare_cpus, |
70 | .smp_secondary_init = highbank_secondary_init, | ||
71 | .smp_boot_secondary = highbank_boot_secondary, | 64 | .smp_boot_secondary = highbank_boot_secondary, |
72 | #ifdef CONFIG_HOTPLUG_CPU | 65 | #ifdef CONFIG_HOTPLUG_CPU |
73 | .cpu_die = highbank_cpu_die, | 66 | .cpu_die = highbank_cpu_die, |
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 4c9c6f9d2c55..6575e4ebe26e 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig | |||
@@ -83,24 +83,12 @@ config ARCH_MXC_IOMUX_V3 | |||
83 | config ARCH_MX1 | 83 | config ARCH_MX1 |
84 | bool | 84 | bool |
85 | 85 | ||
86 | config MACH_MX21 | ||
87 | bool | ||
88 | |||
89 | config ARCH_MX25 | 86 | config ARCH_MX25 |
90 | bool | 87 | bool |
91 | 88 | ||
92 | config MACH_MX27 | 89 | config MACH_MX27 |
93 | bool | 90 | bool |
94 | 91 | ||
95 | config ARCH_MX5 | ||
96 | bool | ||
97 | |||
98 | config ARCH_MX51 | ||
99 | bool | ||
100 | |||
101 | config ARCH_MX53 | ||
102 | bool | ||
103 | |||
104 | config SOC_IMX1 | 92 | config SOC_IMX1 |
105 | bool | 93 | bool |
106 | select ARCH_MX1 | 94 | select ARCH_MX1 |
@@ -114,7 +102,6 @@ config SOC_IMX21 | |||
114 | select COMMON_CLK | 102 | select COMMON_CLK |
115 | select CPU_ARM926T | 103 | select CPU_ARM926T |
116 | select IMX_HAVE_IOMUX_V1 | 104 | select IMX_HAVE_IOMUX_V1 |
117 | select MACH_MX21 | ||
118 | select MXC_AVIC | 105 | select MXC_AVIC |
119 | 106 | ||
120 | config SOC_IMX25 | 107 | config SOC_IMX25 |
@@ -155,7 +142,6 @@ config SOC_IMX35 | |||
155 | config SOC_IMX5 | 142 | config SOC_IMX5 |
156 | bool | 143 | bool |
157 | select ARCH_HAS_CPUFREQ | 144 | select ARCH_HAS_CPUFREQ |
158 | select ARCH_MX5 | ||
159 | select ARCH_MXC_IOMUX_V3 | 145 | select ARCH_MXC_IOMUX_V3 |
160 | select COMMON_CLK | 146 | select COMMON_CLK |
161 | select CPU_V7 | 147 | select CPU_V7 |
@@ -163,8 +149,6 @@ config SOC_IMX5 | |||
163 | 149 | ||
164 | config SOC_IMX51 | 150 | config SOC_IMX51 |
165 | bool | 151 | bool |
166 | select ARCH_MX5 | ||
167 | select ARCH_MX51 | ||
168 | select PINCTRL | 152 | select PINCTRL |
169 | select PINCTRL_IMX51 | 153 | select PINCTRL_IMX51 |
170 | select SOC_IMX5 | 154 | select SOC_IMX5 |
@@ -789,8 +773,6 @@ comment "Device tree only" | |||
789 | 773 | ||
790 | config SOC_IMX53 | 774 | config SOC_IMX53 |
791 | bool "i.MX53 support" | 775 | bool "i.MX53 support" |
792 | select ARCH_MX5 | ||
793 | select ARCH_MX53 | ||
794 | select HAVE_CAN_FLEXCAN if CAN | 776 | select HAVE_CAN_FLEXCAN if CAN |
795 | select IMX_HAVE_PLATFORM_IMX2_WDT | 777 | select IMX_HAVE_PLATFORM_IMX2_WDT |
796 | select PINCTRL | 778 | select PINCTRL |
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index cb70961b6239..fbe60a145344 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile | |||
@@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci- | |||
12 | obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o | 12 | obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o |
13 | 13 | ||
14 | imx5-pm-$(CONFIG_PM) += pm-imx5.o | 14 | imx5-pm-$(CONFIG_PM) += pm-imx5.o |
15 | obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o | 15 | obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) |
16 | 16 | ||
17 | obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ | 17 | obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ |
18 | clk-pfd.o clk-busy.o clk.o | 18 | clk-pfd.o clk-busy.o clk.o |
@@ -27,7 +27,6 @@ obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o | |||
27 | obj-$(CONFIG_MXC_ULPI) += ulpi.o | 27 | obj-$(CONFIG_MXC_ULPI) += ulpi.o |
28 | obj-$(CONFIG_MXC_USE_EPIT) += epit.o | 28 | obj-$(CONFIG_MXC_USE_EPIT) += epit.o |
29 | obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o | 29 | obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o |
30 | obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o | ||
31 | 30 | ||
32 | ifeq ($(CONFIG_CPU_IDLE),y) | 31 | ifeq ($(CONFIG_CPU_IDLE),y) |
33 | obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o | 32 | obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o |
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot deleted file mode 100644 index 41ba1bb0437b..000000000000 --- a/arch/arm/mach-imx/Makefile.boot +++ /dev/null | |||
@@ -1,35 +0,0 @@ | |||
1 | zreladdr-$(CONFIG_SOC_IMX1) += 0x08008000 | ||
2 | params_phys-$(CONFIG_SOC_IMX1) := 0x08000100 | ||
3 | initrd_phys-$(CONFIG_SOC_IMX1) := 0x08800000 | ||
4 | |||
5 | zreladdr-$(CONFIG_SOC_IMX21) += 0xC0008000 | ||
6 | params_phys-$(CONFIG_SOC_IMX21) := 0xC0000100 | ||
7 | initrd_phys-$(CONFIG_SOC_IMX21) := 0xC0800000 | ||
8 | |||
9 | zreladdr-$(CONFIG_SOC_IMX25) += 0x80008000 | ||
10 | params_phys-$(CONFIG_SOC_IMX25) := 0x80000100 | ||
11 | initrd_phys-$(CONFIG_SOC_IMX25) := 0x80800000 | ||
12 | |||
13 | zreladdr-$(CONFIG_SOC_IMX27) += 0xA0008000 | ||
14 | params_phys-$(CONFIG_SOC_IMX27) := 0xA0000100 | ||
15 | initrd_phys-$(CONFIG_SOC_IMX27) := 0xA0800000 | ||
16 | |||
17 | zreladdr-$(CONFIG_SOC_IMX31) += 0x80008000 | ||
18 | params_phys-$(CONFIG_SOC_IMX31) := 0x80000100 | ||
19 | initrd_phys-$(CONFIG_SOC_IMX31) := 0x80800000 | ||
20 | |||
21 | zreladdr-$(CONFIG_SOC_IMX35) += 0x80008000 | ||
22 | params_phys-$(CONFIG_SOC_IMX35) := 0x80000100 | ||
23 | initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000 | ||
24 | |||
25 | zreladdr-$(CONFIG_SOC_IMX51) += 0x90008000 | ||
26 | params_phys-$(CONFIG_SOC_IMX51) := 0x90000100 | ||
27 | initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000 | ||
28 | |||
29 | zreladdr-$(CONFIG_SOC_IMX53) += 0x70008000 | ||
30 | params_phys-$(CONFIG_SOC_IMX53) := 0x70000100 | ||
31 | initrd_phys-$(CONFIG_SOC_IMX53) := 0x70800000 | ||
32 | |||
33 | zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000 | ||
34 | params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100 | ||
35 | initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000 | ||
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c index 9c3e014705b1..e163ec7a8441 100644 --- a/arch/arm/mach-imx/avic.c +++ b/arch/arm/mach-imx/avic.c | |||
@@ -54,8 +54,6 @@ | |||
54 | static void __iomem *avic_base; | 54 | static void __iomem *avic_base; |
55 | static struct irq_domain *domain; | 55 | static struct irq_domain *domain; |
56 | 56 | ||
57 | static u32 avic_saved_mask_reg[2]; | ||
58 | |||
59 | #ifdef CONFIG_MXC_IRQ_PRIOR | 57 | #ifdef CONFIG_MXC_IRQ_PRIOR |
60 | static int avic_irq_set_priority(unsigned char irq, unsigned char prio) | 58 | static int avic_irq_set_priority(unsigned char irq, unsigned char prio) |
61 | { | 59 | { |
@@ -113,6 +111,8 @@ static struct mxc_extra_irq avic_extra_irq = { | |||
113 | }; | 111 | }; |
114 | 112 | ||
115 | #ifdef CONFIG_PM | 113 | #ifdef CONFIG_PM |
114 | static u32 avic_saved_mask_reg[2]; | ||
115 | |||
116 | static void avic_irq_suspend(struct irq_data *d) | 116 | static void avic_irq_suspend(struct irq_data *d) |
117 | { | 117 | { |
118 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | 118 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index 30b3242a7d49..8e3b65719106 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c | |||
@@ -278,8 +278,6 @@ int __init mx27_clocks_init(unsigned long fref) | |||
278 | clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL); | 278 | clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL); |
279 | clk_register_clkdev(clk[cpu_div], "cpu", NULL); | 279 | clk_register_clkdev(clk[cpu_div], "cpu", NULL); |
280 | clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL); | 280 | clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL); |
281 | clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0"); | ||
282 | clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1"); | ||
283 | 281 | ||
284 | mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); | 282 | mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); |
285 | 283 | ||
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 5bf4a97ab241..9fea2522d7a3 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h | |||
@@ -113,7 +113,6 @@ extern void imx_set_cpu_jump(int cpu, void *jump_addr); | |||
113 | extern u32 imx_get_cpu_arg(int cpu); | 113 | extern u32 imx_get_cpu_arg(int cpu); |
114 | extern void imx_set_cpu_arg(int cpu, u32 arg); | 114 | extern void imx_set_cpu_arg(int cpu, u32 arg); |
115 | extern void v7_cpu_resume(void); | 115 | extern void v7_cpu_resume(void); |
116 | extern u32 *pl310_get_save_ptr(void); | ||
117 | #ifdef CONFIG_SMP | 116 | #ifdef CONFIG_SMP |
118 | extern void v7_secondary_startup(void); | 117 | extern void v7_secondary_startup(void); |
119 | extern void imx_scu_map_io(void); | 118 | extern void imx_scu_map_io(void); |
@@ -124,8 +123,6 @@ static inline void imx_scu_map_io(void) {} | |||
124 | static inline void imx_smp_prepare(void) {} | 123 | static inline void imx_smp_prepare(void) {} |
125 | static inline void imx_scu_standby_enable(void) {} | 124 | static inline void imx_scu_standby_enable(void) {} |
126 | #endif | 125 | #endif |
127 | extern void imx_enable_cpu(int cpu, bool enable); | ||
128 | extern void imx_set_cpu_jump(int cpu, void *jump_addr); | ||
129 | extern void imx_src_init(void); | 126 | extern void imx_src_init(void); |
130 | extern void imx_src_prepare_restart(void); | 127 | extern void imx_src_prepare_restart(void); |
131 | extern void imx_gpc_init(void); | 128 | extern void imx_gpc_init(void); |
diff --git a/arch/arm/mach-imx/cpu_op-mx51.c b/arch/arm/mach-imx/cpu_op-mx51.c deleted file mode 100644 index b9ef692b61a2..000000000000 --- a/arch/arm/mach-imx/cpu_op-mx51.c +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | */ | ||
4 | |||
5 | /* | ||
6 | * The code contained herein is licensed under the GNU General Public | ||
7 | * License. You may obtain a copy of the GNU General Public License | ||
8 | * Version 2 or later at the following locations: | ||
9 | * | ||
10 | * http://www.opensource.org/licenses/gpl-license.html | ||
11 | * http://www.gnu.org/copyleft/gpl.html | ||
12 | */ | ||
13 | |||
14 | #include <linux/bug.h> | ||
15 | #include <linux/types.h> | ||
16 | #include <linux/kernel.h> | ||
17 | |||
18 | #include "hardware.h" | ||
19 | |||
20 | static struct cpu_op mx51_cpu_op[] = { | ||
21 | { | ||
22 | .cpu_rate = 160000000,}, | ||
23 | { | ||
24 | .cpu_rate = 800000000,}, | ||
25 | }; | ||
26 | |||
27 | struct cpu_op *mx51_get_cpu_op(int *op) | ||
28 | { | ||
29 | *op = ARRAY_SIZE(mx51_cpu_op); | ||
30 | return mx51_cpu_op; | ||
31 | } | ||
diff --git a/arch/arm/mach-imx/cpu_op-mx51.h b/arch/arm/mach-imx/cpu_op-mx51.h deleted file mode 100644 index 97477fecb469..000000000000 --- a/arch/arm/mach-imx/cpu_op-mx51.h +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | */ | ||
4 | |||
5 | /* | ||
6 | * The code contained herein is licensed under the GNU General Public | ||
7 | * License. You may obtain a copy of the GNU General Public License | ||
8 | * Version 2 or later at the following locations: | ||
9 | * | ||
10 | * http://www.opensource.org/licenses/gpl-license.html | ||
11 | * http://www.gnu.org/copyleft/gpl.html | ||
12 | */ | ||
13 | |||
14 | extern struct cpu_op *mx51_get_cpu_op(int *op); | ||
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c deleted file mode 100644 index 387dc4cceca2..000000000000 --- a/arch/arm/mach-imx/cpufreq.c +++ /dev/null | |||
@@ -1,202 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | */ | ||
4 | |||
5 | /* | ||
6 | * The code contained herein is licensed under the GNU General Public | ||
7 | * License. You may obtain a copy of the GNU General Public License | ||
8 | * Version 2 or later at the following locations: | ||
9 | * | ||
10 | * http://www.opensource.org/licenses/gpl-license.html | ||
11 | * http://www.gnu.org/copyleft/gpl.html | ||
12 | */ | ||
13 | |||
14 | /* | ||
15 | * A driver for the Freescale Semiconductor i.MXC CPUfreq module. | ||
16 | * The CPUFREQ driver is for controlling CPU frequency. It allows you to change | ||
17 | * the CPU clock speed on the fly. | ||
18 | */ | ||
19 | |||
20 | #include <linux/module.h> | ||
21 | #include <linux/cpufreq.h> | ||
22 | #include <linux/clk.h> | ||
23 | #include <linux/err.h> | ||
24 | #include <linux/slab.h> | ||
25 | |||
26 | #include "hardware.h" | ||
27 | |||
28 | #define CLK32_FREQ 32768 | ||
29 | #define NANOSECOND (1000 * 1000 * 1000) | ||
30 | |||
31 | struct cpu_op *(*get_cpu_op)(int *op); | ||
32 | |||
33 | static int cpu_freq_khz_min; | ||
34 | static int cpu_freq_khz_max; | ||
35 | |||
36 | static struct clk *cpu_clk; | ||
37 | static struct cpufreq_frequency_table *imx_freq_table; | ||
38 | |||
39 | static int cpu_op_nr; | ||
40 | static struct cpu_op *cpu_op_tbl; | ||
41 | |||
42 | static int set_cpu_freq(int freq) | ||
43 | { | ||
44 | int ret = 0; | ||
45 | int org_cpu_rate; | ||
46 | |||
47 | org_cpu_rate = clk_get_rate(cpu_clk); | ||
48 | if (org_cpu_rate == freq) | ||
49 | return ret; | ||
50 | |||
51 | ret = clk_set_rate(cpu_clk, freq); | ||
52 | if (ret != 0) { | ||
53 | printk(KERN_DEBUG "cannot set CPU clock rate\n"); | ||
54 | return ret; | ||
55 | } | ||
56 | |||
57 | return ret; | ||
58 | } | ||
59 | |||
60 | static int mxc_verify_speed(struct cpufreq_policy *policy) | ||
61 | { | ||
62 | if (policy->cpu != 0) | ||
63 | return -EINVAL; | ||
64 | |||
65 | return cpufreq_frequency_table_verify(policy, imx_freq_table); | ||
66 | } | ||
67 | |||
68 | static unsigned int mxc_get_speed(unsigned int cpu) | ||
69 | { | ||
70 | if (cpu) | ||
71 | return 0; | ||
72 | |||
73 | return clk_get_rate(cpu_clk) / 1000; | ||
74 | } | ||
75 | |||
76 | static int mxc_set_target(struct cpufreq_policy *policy, | ||
77 | unsigned int target_freq, unsigned int relation) | ||
78 | { | ||
79 | struct cpufreq_freqs freqs; | ||
80 | int freq_Hz; | ||
81 | int ret = 0; | ||
82 | unsigned int index; | ||
83 | |||
84 | cpufreq_frequency_table_target(policy, imx_freq_table, | ||
85 | target_freq, relation, &index); | ||
86 | freq_Hz = imx_freq_table[index].frequency * 1000; | ||
87 | |||
88 | freqs.old = clk_get_rate(cpu_clk) / 1000; | ||
89 | freqs.new = freq_Hz / 1000; | ||
90 | freqs.flags = 0; | ||
91 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); | ||
92 | |||
93 | ret = set_cpu_freq(freq_Hz); | ||
94 | |||
95 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); | ||
96 | |||
97 | return ret; | ||
98 | } | ||
99 | |||
100 | static int mxc_cpufreq_init(struct cpufreq_policy *policy) | ||
101 | { | ||
102 | int ret; | ||
103 | int i; | ||
104 | |||
105 | printk(KERN_INFO "i.MXC CPU frequency driver\n"); | ||
106 | |||
107 | if (policy->cpu != 0) | ||
108 | return -EINVAL; | ||
109 | |||
110 | if (!get_cpu_op) | ||
111 | return -EINVAL; | ||
112 | |||
113 | cpu_clk = clk_get(NULL, "cpu_clk"); | ||
114 | if (IS_ERR(cpu_clk)) { | ||
115 | printk(KERN_ERR "%s: failed to get cpu clock\n", __func__); | ||
116 | return PTR_ERR(cpu_clk); | ||
117 | } | ||
118 | |||
119 | cpu_op_tbl = get_cpu_op(&cpu_op_nr); | ||
120 | |||
121 | cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000; | ||
122 | cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000; | ||
123 | |||
124 | imx_freq_table = kmalloc( | ||
125 | sizeof(struct cpufreq_frequency_table) * (cpu_op_nr + 1), | ||
126 | GFP_KERNEL); | ||
127 | if (!imx_freq_table) { | ||
128 | ret = -ENOMEM; | ||
129 | goto err1; | ||
130 | } | ||
131 | |||
132 | for (i = 0; i < cpu_op_nr; i++) { | ||
133 | imx_freq_table[i].index = i; | ||
134 | imx_freq_table[i].frequency = cpu_op_tbl[i].cpu_rate / 1000; | ||
135 | |||
136 | if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min) | ||
137 | cpu_freq_khz_min = cpu_op_tbl[i].cpu_rate / 1000; | ||
138 | |||
139 | if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max) | ||
140 | cpu_freq_khz_max = cpu_op_tbl[i].cpu_rate / 1000; | ||
141 | } | ||
142 | |||
143 | imx_freq_table[i].index = i; | ||
144 | imx_freq_table[i].frequency = CPUFREQ_TABLE_END; | ||
145 | |||
146 | policy->cur = clk_get_rate(cpu_clk) / 1000; | ||
147 | |||
148 | /* Manual states, that PLL stabilizes in two CLK32 periods */ | ||
149 | policy->cpuinfo.transition_latency = 2 * NANOSECOND / CLK32_FREQ; | ||
150 | |||
151 | ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table); | ||
152 | if (ret < 0) { | ||
153 | printk(KERN_ERR "%s: failed to register i.MXC CPUfreq with error code %d\n", | ||
154 | __func__, ret); | ||
155 | goto err; | ||
156 | } | ||
157 | |||
158 | cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu); | ||
159 | return 0; | ||
160 | err: | ||
161 | kfree(imx_freq_table); | ||
162 | err1: | ||
163 | clk_put(cpu_clk); | ||
164 | return ret; | ||
165 | } | ||
166 | |||
167 | static int mxc_cpufreq_exit(struct cpufreq_policy *policy) | ||
168 | { | ||
169 | cpufreq_frequency_table_put_attr(policy->cpu); | ||
170 | |||
171 | set_cpu_freq(cpu_freq_khz_max * 1000); | ||
172 | clk_put(cpu_clk); | ||
173 | kfree(imx_freq_table); | ||
174 | return 0; | ||
175 | } | ||
176 | |||
177 | static struct cpufreq_driver mxc_driver = { | ||
178 | .flags = CPUFREQ_STICKY, | ||
179 | .verify = mxc_verify_speed, | ||
180 | .target = mxc_set_target, | ||
181 | .get = mxc_get_speed, | ||
182 | .init = mxc_cpufreq_init, | ||
183 | .exit = mxc_cpufreq_exit, | ||
184 | .name = "imx", | ||
185 | }; | ||
186 | |||
187 | static int mxc_cpufreq_driver_init(void) | ||
188 | { | ||
189 | return cpufreq_register_driver(&mxc_driver); | ||
190 | } | ||
191 | |||
192 | static void mxc_cpufreq_driver_exit(void) | ||
193 | { | ||
194 | cpufreq_unregister_driver(&mxc_driver); | ||
195 | } | ||
196 | |||
197 | module_init(mxc_cpufreq_driver_init); | ||
198 | module_exit(mxc_cpufreq_driver_exit); | ||
199 | |||
200 | MODULE_AUTHOR("Freescale Semiconductor Inc. Yong Shen <yong.shen@linaro.org>"); | ||
201 | MODULE_DESCRIPTION("CPUfreq driver for i.MX"); | ||
202 | MODULE_LICENSE("GPL"); | ||
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig index 9b9ba1f4ffe1..3dd2b1b041d1 100644 --- a/arch/arm/mach-imx/devices/Kconfig +++ b/arch/arm/mach-imx/devices/Kconfig | |||
@@ -86,7 +86,3 @@ config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | |||
86 | 86 | ||
87 | config IMX_HAVE_PLATFORM_SPI_IMX | 87 | config IMX_HAVE_PLATFORM_SPI_IMX |
88 | bool | 88 | bool |
89 | |||
90 | config IMX_HAVE_PLATFORM_AHCI | ||
91 | bool | ||
92 | default y if ARCH_MX53 | ||
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile index 6acf37e0c119..67416fb1dc69 100644 --- a/arch/arm/mach-imx/devices/Makefile +++ b/arch/arm/mach-imx/devices/Makefile | |||
@@ -29,5 +29,4 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o | |||
29 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o | 29 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o |
30 | obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o | 30 | obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o |
31 | obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o | 31 | obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o |
32 | obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) += platform-ahci-imx.o | ||
33 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_EMMA) += platform-mx2-emma.o | 32 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_EMMA) += platform-mx2-emma.o |
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h index 9bd5777ff0e7..453e20bc2657 100644 --- a/arch/arm/mach-imx/devices/devices-common.h +++ b/arch/arm/mach-imx/devices/devices-common.h | |||
@@ -344,13 +344,3 @@ struct platform_device *imx_add_imx_dma(char *name, resource_size_t iobase, | |||
344 | int irq, int irq_err); | 344 | int irq, int irq_err); |
345 | struct platform_device *imx_add_imx_sdma(char *name, | 345 | struct platform_device *imx_add_imx_sdma(char *name, |
346 | resource_size_t iobase, int irq, struct sdma_platform_data *pdata); | 346 | resource_size_t iobase, int irq, struct sdma_platform_data *pdata); |
347 | |||
348 | #include <linux/ahci_platform.h> | ||
349 | struct imx_ahci_imx_data { | ||
350 | const char *devid; | ||
351 | resource_size_t iobase; | ||
352 | resource_size_t irq; | ||
353 | }; | ||
354 | struct platform_device *__init imx_add_ahci_imx( | ||
355 | const struct imx_ahci_imx_data *data, | ||
356 | const struct ahci_platform_data *pdata); | ||
diff --git a/arch/arm/mach-imx/devices/platform-ahci-imx.c b/arch/arm/mach-imx/devices/platform-ahci-imx.c deleted file mode 100644 index 3d87dd9c284a..000000000000 --- a/arch/arm/mach-imx/devices/platform-ahci-imx.c +++ /dev/null | |||
@@ -1,157 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | */ | ||
4 | |||
5 | /* | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | |||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | |||
16 | * You should have received a copy of the GNU General Public License along | ||
17 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
19 | */ | ||
20 | |||
21 | #include <linux/io.h> | ||
22 | #include <linux/clk.h> | ||
23 | #include <linux/err.h> | ||
24 | #include <linux/device.h> | ||
25 | #include <linux/dma-mapping.h> | ||
26 | #include <asm/sizes.h> | ||
27 | |||
28 | #include "../hardware.h" | ||
29 | #include "devices-common.h" | ||
30 | |||
31 | #define imx_ahci_imx_data_entry_single(soc, _devid) \ | ||
32 | { \ | ||
33 | .devid = _devid, \ | ||
34 | .iobase = soc ## _SATA_BASE_ADDR, \ | ||
35 | .irq = soc ## _INT_SATA, \ | ||
36 | } | ||
37 | |||
38 | #ifdef CONFIG_SOC_IMX53 | ||
39 | const struct imx_ahci_imx_data imx53_ahci_imx_data __initconst = | ||
40 | imx_ahci_imx_data_entry_single(MX53, "imx53-ahci"); | ||
41 | #endif | ||
42 | |||
43 | enum { | ||
44 | HOST_CAP = 0x00, | ||
45 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ | ||
46 | HOST_PORTS_IMPL = 0x0c, | ||
47 | HOST_TIMER1MS = 0xe0, /* Timer 1-ms */ | ||
48 | }; | ||
49 | |||
50 | static struct clk *sata_clk, *sata_ref_clk; | ||
51 | |||
52 | /* AHCI module Initialization, if return 0, initialization is successful. */ | ||
53 | static int imx_sata_init(struct device *dev, void __iomem *addr) | ||
54 | { | ||
55 | u32 tmpdata; | ||
56 | int ret = 0; | ||
57 | struct clk *clk; | ||
58 | |||
59 | sata_clk = clk_get(dev, "ahci"); | ||
60 | if (IS_ERR(sata_clk)) { | ||
61 | dev_err(dev, "no sata clock.\n"); | ||
62 | return PTR_ERR(sata_clk); | ||
63 | } | ||
64 | ret = clk_prepare_enable(sata_clk); | ||
65 | if (ret) { | ||
66 | dev_err(dev, "can't prepare/enable sata clock.\n"); | ||
67 | goto put_sata_clk; | ||
68 | } | ||
69 | |||
70 | /* Get the AHCI SATA PHY CLK */ | ||
71 | sata_ref_clk = clk_get(dev, "ahci_phy"); | ||
72 | if (IS_ERR(sata_ref_clk)) { | ||
73 | dev_err(dev, "no sata ref clock.\n"); | ||
74 | ret = PTR_ERR(sata_ref_clk); | ||
75 | goto release_sata_clk; | ||
76 | } | ||
77 | ret = clk_prepare_enable(sata_ref_clk); | ||
78 | if (ret) { | ||
79 | dev_err(dev, "can't prepare/enable sata ref clock.\n"); | ||
80 | goto put_sata_ref_clk; | ||
81 | } | ||
82 | |||
83 | /* Get the AHB clock rate, and configure the TIMER1MS reg later */ | ||
84 | clk = clk_get(dev, "ahci_dma"); | ||
85 | if (IS_ERR(clk)) { | ||
86 | dev_err(dev, "no dma clock.\n"); | ||
87 | ret = PTR_ERR(clk); | ||
88 | goto release_sata_ref_clk; | ||
89 | } | ||
90 | tmpdata = clk_get_rate(clk) / 1000; | ||
91 | clk_put(clk); | ||
92 | |||
93 | writel(tmpdata, addr + HOST_TIMER1MS); | ||
94 | |||
95 | tmpdata = readl(addr + HOST_CAP); | ||
96 | if (!(tmpdata & HOST_CAP_SSS)) { | ||
97 | tmpdata |= HOST_CAP_SSS; | ||
98 | writel(tmpdata, addr + HOST_CAP); | ||
99 | } | ||
100 | |||
101 | if (!(readl(addr + HOST_PORTS_IMPL) & 0x1)) | ||
102 | writel((readl(addr + HOST_PORTS_IMPL) | 0x1), | ||
103 | addr + HOST_PORTS_IMPL); | ||
104 | |||
105 | return 0; | ||
106 | |||
107 | release_sata_ref_clk: | ||
108 | clk_disable_unprepare(sata_ref_clk); | ||
109 | put_sata_ref_clk: | ||
110 | clk_put(sata_ref_clk); | ||
111 | release_sata_clk: | ||
112 | clk_disable_unprepare(sata_clk); | ||
113 | put_sata_clk: | ||
114 | clk_put(sata_clk); | ||
115 | |||
116 | return ret; | ||
117 | } | ||
118 | |||
119 | static void imx_sata_exit(struct device *dev) | ||
120 | { | ||
121 | clk_disable_unprepare(sata_ref_clk); | ||
122 | clk_put(sata_ref_clk); | ||
123 | |||
124 | clk_disable_unprepare(sata_clk); | ||
125 | clk_put(sata_clk); | ||
126 | |||
127 | } | ||
128 | struct platform_device *__init imx_add_ahci_imx( | ||
129 | const struct imx_ahci_imx_data *data, | ||
130 | const struct ahci_platform_data *pdata) | ||
131 | { | ||
132 | struct resource res[] = { | ||
133 | { | ||
134 | .start = data->iobase, | ||
135 | .end = data->iobase + SZ_4K - 1, | ||
136 | .flags = IORESOURCE_MEM, | ||
137 | }, { | ||
138 | .start = data->irq, | ||
139 | .end = data->irq, | ||
140 | .flags = IORESOURCE_IRQ, | ||
141 | }, | ||
142 | }; | ||
143 | |||
144 | return imx_add_platform_device_dmamask(data->devid, 0, | ||
145 | res, ARRAY_SIZE(res), | ||
146 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
147 | } | ||
148 | |||
149 | struct platform_device *__init imx53_add_ahci_imx(void) | ||
150 | { | ||
151 | struct ahci_platform_data pdata = { | ||
152 | .init = imx_sata_init, | ||
153 | .exit = imx_sata_exit, | ||
154 | }; | ||
155 | |||
156 | return imx_add_ahci_imx(&imx53_ahci_imx_data, &pdata); | ||
157 | } | ||
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h index 911e9b31b03f..356131f7b591 100644 --- a/arch/arm/mach-imx/hardware.h +++ b/arch/arm/mach-imx/hardware.h | |||
@@ -102,7 +102,6 @@ | |||
102 | 102 | ||
103 | #include "mxc.h" | 103 | #include "mxc.h" |
104 | 104 | ||
105 | #include "mx6q.h" | ||
106 | #include "mx51.h" | 105 | #include "mx51.h" |
107 | #include "mx53.h" | 106 | #include "mx53.h" |
108 | #include "mx3x.h" | 107 | #include "mx3x.h" |
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c index 9b7393234f6f..9b5ddf5bbd33 100644 --- a/arch/arm/mach-imx/mach-cpuimx51sd.c +++ b/arch/arm/mach-imx/mach-cpuimx51sd.c | |||
@@ -33,7 +33,6 @@ | |||
33 | 33 | ||
34 | #include "common.h" | 34 | #include "common.h" |
35 | #include "devices-imx51.h" | 35 | #include "devices-imx51.h" |
36 | #include "cpu_op-mx51.h" | ||
37 | #include "eukrea-baseboards.h" | 36 | #include "eukrea-baseboards.h" |
38 | #include "hardware.h" | 37 | #include "hardware.h" |
39 | #include "iomux-mx51.h" | 38 | #include "iomux-mx51.h" |
@@ -285,10 +284,6 @@ static void __init eukrea_cpuimx51sd_init(void) | |||
285 | mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads, | 284 | mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads, |
286 | ARRAY_SIZE(eukrea_cpuimx51sd_pads)); | 285 | ARRAY_SIZE(eukrea_cpuimx51sd_pads)); |
287 | 286 | ||
288 | #if defined(CONFIG_CPU_FREQ_IMX) | ||
289 | get_cpu_op = mx51_get_cpu_op; | ||
290 | #endif | ||
291 | |||
292 | imx51_add_imx_uart(0, &uart_pdata); | 287 | imx51_add_imx_uart(0, &uart_pdata); |
293 | imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info); | 288 | imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info); |
294 | imx51_add_imx2_wdt(0); | 289 | imx51_add_imx2_wdt(0); |
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index fe1b7aafabdc..99502eeefdf7 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c | |||
@@ -12,6 +12,7 @@ | |||
12 | 12 | ||
13 | #include <linux/clk.h> | 13 | #include <linux/clk.h> |
14 | #include <linux/clkdev.h> | 14 | #include <linux/clkdev.h> |
15 | #include <linux/clocksource.h> | ||
15 | #include <linux/cpu.h> | 16 | #include <linux/cpu.h> |
16 | #include <linux/delay.h> | 17 | #include <linux/delay.h> |
17 | #include <linux/export.h> | 18 | #include <linux/export.h> |
@@ -28,11 +29,9 @@ | |||
28 | #include <linux/regmap.h> | 29 | #include <linux/regmap.h> |
29 | #include <linux/micrel_phy.h> | 30 | #include <linux/micrel_phy.h> |
30 | #include <linux/mfd/syscon.h> | 31 | #include <linux/mfd/syscon.h> |
31 | #include <asm/smp_twd.h> | ||
32 | #include <asm/hardware/cache-l2x0.h> | 32 | #include <asm/hardware/cache-l2x0.h> |
33 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
34 | #include <asm/mach/map.h> | 34 | #include <asm/mach/map.h> |
35 | #include <asm/mach/time.h> | ||
36 | #include <asm/system_misc.h> | 35 | #include <asm/system_misc.h> |
37 | 36 | ||
38 | #include "common.h" | 37 | #include "common.h" |
@@ -292,7 +291,7 @@ static void __init imx6q_init_irq(void) | |||
292 | static void __init imx6q_timer_init(void) | 291 | static void __init imx6q_timer_init(void) |
293 | { | 292 | { |
294 | mx6q_clocks_init(); | 293 | mx6q_clocks_init(); |
295 | twd_local_timer_of_register(); | 294 | clocksource_of_init(); |
296 | imx_print_silicon_rev("i.MX6Q", imx6q_revision()); | 295 | imx_print_silicon_rev("i.MX6Q", imx6q_revision()); |
297 | } | 296 | } |
298 | 297 | ||
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c index 6c4d7feb4520..f3d264a636fa 100644 --- a/arch/arm/mach-imx/mach-mx51_babbage.c +++ b/arch/arm/mach-imx/mach-mx51_babbage.c | |||
@@ -27,7 +27,6 @@ | |||
27 | 27 | ||
28 | #include "common.h" | 28 | #include "common.h" |
29 | #include "devices-imx51.h" | 29 | #include "devices-imx51.h" |
30 | #include "cpu_op-mx51.h" | ||
31 | #include "hardware.h" | 30 | #include "hardware.h" |
32 | #include "iomux-mx51.h" | 31 | #include "iomux-mx51.h" |
33 | 32 | ||
@@ -371,9 +370,6 @@ static void __init mx51_babbage_init(void) | |||
371 | 370 | ||
372 | imx51_soc_init(); | 371 | imx51_soc_init(); |
373 | 372 | ||
374 | #if defined(CONFIG_CPU_FREQ_IMX) | ||
375 | get_cpu_op = mx51_get_cpu_op; | ||
376 | #endif | ||
377 | imx51_babbage_common_init(); | 373 | imx51_babbage_common_init(); |
378 | 374 | ||
379 | imx51_add_imx_uart(0, &uart_pdata); | 375 | imx51_add_imx_uart(0, &uart_pdata); |
diff --git a/arch/arm/mach-imx/mx6q.h b/arch/arm/mach-imx/mx6q.h deleted file mode 100644 index 19d3f54db5af..000000000000 --- a/arch/arm/mach-imx/mx6q.h +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | * Copyright 2011 Linaro Ltd. | ||
4 | * | ||
5 | * The code contained herein is licensed under the GNU General Public | ||
6 | * License. You may obtain a copy of the GNU General Public License | ||
7 | * Version 2 or later at the following locations: | ||
8 | * | ||
9 | * http://www.opensource.org/licenses/gpl-license.html | ||
10 | * http://www.gnu.org/copyleft/gpl.html | ||
11 | */ | ||
12 | |||
13 | #ifndef __MACH_MX6Q_H__ | ||
14 | #define __MACH_MX6Q_H__ | ||
15 | |||
16 | #define MX6Q_IO_P2V(x) IMX_IO_P2V(x) | ||
17 | #define MX6Q_IO_ADDRESS(x) IOMEM(MX6Q_IO_P2V(x)) | ||
18 | |||
19 | /* | ||
20 | * The following are the blocks that need to be statically mapped. | ||
21 | * For other blocks, the base address really should be retrieved from | ||
22 | * device tree. | ||
23 | */ | ||
24 | #define MX6Q_SCU_BASE_ADDR 0x00a00000 | ||
25 | #define MX6Q_SCU_SIZE 0x1000 | ||
26 | #define MX6Q_CCM_BASE_ADDR 0x020c4000 | ||
27 | #define MX6Q_CCM_SIZE 0x4000 | ||
28 | #define MX6Q_ANATOP_BASE_ADDR 0x020c8000 | ||
29 | #define MX6Q_ANATOP_SIZE 0x1000 | ||
30 | |||
31 | #endif /* __MACH_MX6Q_H__ */ | ||
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c index 7c0b03f67b05..77e9a25ed0f6 100644 --- a/arch/arm/mach-imx/platsmp.c +++ b/arch/arm/mach-imx/platsmp.c | |||
@@ -12,7 +12,6 @@ | |||
12 | 12 | ||
13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
14 | #include <linux/smp.h> | 14 | #include <linux/smp.h> |
15 | #include <linux/irqchip/arm-gic.h> | ||
16 | #include <asm/page.h> | 15 | #include <asm/page.h> |
17 | #include <asm/smp_scu.h> | 16 | #include <asm/smp_scu.h> |
18 | #include <asm/mach/map.h> | 17 | #include <asm/mach/map.h> |
@@ -52,16 +51,6 @@ void imx_scu_standby_enable(void) | |||
52 | writel_relaxed(val, scu_base); | 51 | writel_relaxed(val, scu_base); |
53 | } | 52 | } |
54 | 53 | ||
55 | static void __cpuinit imx_secondary_init(unsigned int cpu) | ||
56 | { | ||
57 | /* | ||
58 | * if any interrupts are already enabled for the primary | ||
59 | * core (e.g. timer irq), then they will not have been enabled | ||
60 | * for us: do so | ||
61 | */ | ||
62 | gic_secondary_init(0); | ||
63 | } | ||
64 | |||
65 | static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle) | 54 | static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle) |
66 | { | 55 | { |
67 | imx_set_cpu_jump(cpu, v7_secondary_startup); | 56 | imx_set_cpu_jump(cpu, v7_secondary_startup); |
@@ -96,7 +85,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus) | |||
96 | struct smp_operations imx_smp_ops __initdata = { | 85 | struct smp_operations imx_smp_ops __initdata = { |
97 | .smp_init_cpus = imx_smp_init_cpus, | 86 | .smp_init_cpus = imx_smp_init_cpus, |
98 | .smp_prepare_cpus = imx_smp_prepare_cpus, | 87 | .smp_prepare_cpus = imx_smp_prepare_cpus, |
99 | .smp_secondary_init = imx_secondary_init, | ||
100 | .smp_boot_secondary = imx_boot_secondary, | 88 | .smp_boot_secondary = imx_boot_secondary, |
101 | #ifdef CONFIG_HOTPLUG_CPU | 89 | #ifdef CONFIG_HOTPLUG_CPU |
102 | .cpu_die = imx_cpu_die, | 90 | .cpu_die = imx_cpu_die, |
diff --git a/arch/arm/mach-l7200/include/mach/debug-macro.S b/arch/arm/mach-l7200/include/mach/debug-macro.S deleted file mode 100644 index 0b4e760159b9..000000000000 --- a/arch/arm/mach-l7200/include/mach/debug-macro.S +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | /* arch/arm/mach-l7200/include/mach/debug-macro.S | ||
2 | * | ||
3 | * Debugging macro include header | ||
4 | * | ||
5 | * Copyright (C) 1994-1999 Russell King | ||
6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | .equ io_virt, IO_BASE | ||
15 | .equ io_phys, IO_START | ||
16 | |||
17 | .macro addruart, rp, rv, tmp | ||
18 | mov \rp, #0x00044000 @ UART1 | ||
19 | @ mov \rp, #0x00045000 @ UART2 | ||
20 | add \rv, \rp, #io_virt @ virtual address | ||
21 | add \rp, \rp, #io_phys @ physical base address | ||
22 | .endm | ||
23 | |||
24 | .macro senduart,rd,rx | ||
25 | str \rd, [\rx, #0x0] @ UARTDR | ||
26 | .endm | ||
27 | |||
28 | .macro waituart,rd,rx | ||
29 | 1001: ldr \rd, [\rx, #0x18] @ UARTFLG | ||
30 | tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full | ||
31 | bne 1001b | ||
32 | .endm | ||
33 | |||
34 | .macro busyuart,rd,rx | ||
35 | 1001: ldr \rd, [\rx, #0x18] @ UARTFLG | ||
36 | tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy | ||
37 | bne 1001b | ||
38 | .endm | ||
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c index 84d720af34ab..82eaf88d2026 100644 --- a/arch/arm/mach-msm/board-halibut.c +++ b/arch/arm/mach-msm/board-halibut.c | |||
@@ -59,6 +59,7 @@ static struct platform_device smc91x_device = { | |||
59 | }; | 59 | }; |
60 | 60 | ||
61 | static struct platform_device *devices[] __initdata = { | 61 | static struct platform_device *devices[] __initdata = { |
62 | &msm_device_gpio_7201, | ||
62 | &msm_device_uart3, | 63 | &msm_device_uart3, |
63 | &msm_device_smd, | 64 | &msm_device_smd, |
64 | &msm_device_nand, | 65 | &msm_device_nand, |
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index 7bc3f82e3ec9..520c141acd03 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c | |||
@@ -89,6 +89,7 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { | |||
89 | }; | 89 | }; |
90 | 90 | ||
91 | static struct platform_device *devices[] __initdata = { | 91 | static struct platform_device *devices[] __initdata = { |
92 | &msm_device_gpio_7x30, | ||
92 | #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER) | 93 | #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER) |
93 | &msm_device_uart2, | 94 | &msm_device_uart2, |
94 | #endif | 95 | #endif |
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index 686e7949a73a..38a532d6937c 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c | |||
@@ -89,6 +89,7 @@ static struct msm_otg_platform_data msm_otg_pdata = { | |||
89 | }; | 89 | }; |
90 | 90 | ||
91 | static struct platform_device *devices[] __initdata = { | 91 | static struct platform_device *devices[] __initdata = { |
92 | &msm_device_gpio_8x50, | ||
92 | &msm_device_uart3, | 93 | &msm_device_uart3, |
93 | &msm_device_smd, | 94 | &msm_device_smd, |
94 | &msm_device_otg, | 95 | &msm_device_otg, |
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c index 919bfa32871a..80fe1c5ff5c1 100644 --- a/arch/arm/mach-msm/board-trout.c +++ b/arch/arm/mach-msm/board-trout.c | |||
@@ -36,6 +36,7 @@ | |||
36 | extern int trout_init_mmc(unsigned int); | 36 | extern int trout_init_mmc(unsigned int); |
37 | 37 | ||
38 | static struct platform_device *devices[] __initdata = { | 38 | static struct platform_device *devices[] __initdata = { |
39 | &msm_device_gpio_7201, | ||
39 | &msm_device_uart3, | 40 | &msm_device_uart3, |
40 | &msm_device_smd, | 41 | &msm_device_smd, |
41 | &msm_device_nand, | 42 | &msm_device_nand, |
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c index f66ee6ea8720..1a0a2306b115 100644 --- a/arch/arm/mach-msm/devices-msm7x00.c +++ b/arch/arm/mach-msm/devices-msm7x00.c | |||
@@ -29,6 +29,37 @@ | |||
29 | #include "clock-pcom.h" | 29 | #include "clock-pcom.h" |
30 | #include <linux/platform_data/mmc-msm_sdcc.h> | 30 | #include <linux/platform_data/mmc-msm_sdcc.h> |
31 | 31 | ||
32 | static struct resource msm_gpio_resources[] = { | ||
33 | { | ||
34 | .start = 32 + 0, | ||
35 | .end = 32 + 0, | ||
36 | .flags = IORESOURCE_IRQ, | ||
37 | }, | ||
38 | { | ||
39 | .start = 32 + 1, | ||
40 | .end = 32 + 1, | ||
41 | .flags = IORESOURCE_IRQ, | ||
42 | }, | ||
43 | { | ||
44 | .start = 0xa9200800, | ||
45 | .end = 0xa9200800 + SZ_4K - 1, | ||
46 | .flags = IORESOURCE_MEM, | ||
47 | .name = "gpio1" | ||
48 | }, | ||
49 | { | ||
50 | .start = 0xa9300C00, | ||
51 | .end = 0xa9300C00 + SZ_4K - 1, | ||
52 | .flags = IORESOURCE_MEM, | ||
53 | .name = "gpio2" | ||
54 | }, | ||
55 | }; | ||
56 | |||
57 | struct platform_device msm_device_gpio_7201 = { | ||
58 | .name = "gpio-msm-7201", | ||
59 | .num_resources = ARRAY_SIZE(msm_gpio_resources), | ||
60 | .resource = msm_gpio_resources, | ||
61 | }; | ||
62 | |||
32 | static struct resource resources_uart1[] = { | 63 | static struct resource resources_uart1[] = { |
33 | { | 64 | { |
34 | .start = INT_UART1, | 65 | .start = INT_UART1, |
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c index e90ab5938c5f..12f482c07740 100644 --- a/arch/arm/mach-msm/devices-msm7x30.c +++ b/arch/arm/mach-msm/devices-msm7x30.c | |||
@@ -33,6 +33,37 @@ | |||
33 | 33 | ||
34 | #include <linux/platform_data/mmc-msm_sdcc.h> | 34 | #include <linux/platform_data/mmc-msm_sdcc.h> |
35 | 35 | ||
36 | static struct resource msm_gpio_resources[] = { | ||
37 | { | ||
38 | .start = 32 + 18, | ||
39 | .end = 32 + 18, | ||
40 | .flags = IORESOURCE_IRQ, | ||
41 | }, | ||
42 | { | ||
43 | .start = 32 + 19, | ||
44 | .end = 32 + 19, | ||
45 | .flags = IORESOURCE_IRQ, | ||
46 | }, | ||
47 | { | ||
48 | .start = 0xac001000, | ||
49 | .end = 0xac001000 + SZ_4K - 1, | ||
50 | .flags = IORESOURCE_MEM, | ||
51 | .name = "gpio1" | ||
52 | }, | ||
53 | { | ||
54 | .start = 0xac101400, | ||
55 | .end = 0xac101400 + SZ_4K - 1, | ||
56 | .flags = IORESOURCE_MEM, | ||
57 | .name = "gpio2" | ||
58 | }, | ||
59 | }; | ||
60 | |||
61 | struct platform_device msm_device_gpio_7x30 = { | ||
62 | .name = "gpio-msm-7x30", | ||
63 | .num_resources = ARRAY_SIZE(msm_gpio_resources), | ||
64 | .resource = msm_gpio_resources, | ||
65 | }; | ||
66 | |||
36 | static struct resource resources_uart2[] = { | 67 | static struct resource resources_uart2[] = { |
37 | { | 68 | { |
38 | .start = INT_UART2, | 69 | .start = INT_UART2, |
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c index 4db61d5fe317..2e1b3ec9dfc7 100644 --- a/arch/arm/mach-msm/devices-qsd8x50.c +++ b/arch/arm/mach-msm/devices-qsd8x50.c | |||
@@ -30,6 +30,37 @@ | |||
30 | #include <linux/platform_data/mmc-msm_sdcc.h> | 30 | #include <linux/platform_data/mmc-msm_sdcc.h> |
31 | #include "clock-pcom.h" | 31 | #include "clock-pcom.h" |
32 | 32 | ||
33 | static struct resource msm_gpio_resources[] = { | ||
34 | { | ||
35 | .start = 64 + 165 + 9, | ||
36 | .end = 64 + 165 + 9, | ||
37 | .flags = IORESOURCE_IRQ, | ||
38 | }, | ||
39 | { | ||
40 | .start = 64 + 165 + 10, | ||
41 | .end = 64 + 165 + 10, | ||
42 | .flags = IORESOURCE_IRQ, | ||
43 | }, | ||
44 | { | ||
45 | .start = 0xa9000800, | ||
46 | .end = 0xa9000800 + SZ_4K - 1, | ||
47 | .flags = IORESOURCE_MEM, | ||
48 | .name = "gpio1" | ||
49 | }, | ||
50 | { | ||
51 | .start = 0xa9100C00, | ||
52 | .end = 0xa9100C00 + SZ_4K - 1, | ||
53 | .flags = IORESOURCE_MEM, | ||
54 | .name = "gpio2" | ||
55 | }, | ||
56 | }; | ||
57 | |||
58 | struct platform_device msm_device_gpio_8x50 = { | ||
59 | .name = "gpio-msm-8x50", | ||
60 | .num_resources = ARRAY_SIZE(msm_gpio_resources), | ||
61 | .resource = msm_gpio_resources, | ||
62 | }; | ||
63 | |||
33 | static struct resource resources_uart3[] = { | 64 | static struct resource resources_uart3[] = { |
34 | { | 65 | { |
35 | .start = INT_UART3, | 66 | .start = INT_UART3, |
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h index 9545c196c6e8..da902cf51161 100644 --- a/arch/arm/mach-msm/devices.h +++ b/arch/arm/mach-msm/devices.h | |||
@@ -20,6 +20,10 @@ | |||
20 | 20 | ||
21 | #include "clock.h" | 21 | #include "clock.h" |
22 | 22 | ||
23 | extern struct platform_device msm_device_gpio_7201; | ||
24 | extern struct platform_device msm_device_gpio_7x30; | ||
25 | extern struct platform_device msm_device_gpio_8x50; | ||
26 | |||
23 | extern struct platform_device msm_device_uart1; | 27 | extern struct platform_device msm_device_uart1; |
24 | extern struct platform_device msm_device_uart2; | 28 | extern struct platform_device msm_device_uart2; |
25 | extern struct platform_device msm_device_uart3; | 29 | extern struct platform_device msm_device_uart3; |
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c index 354b91d4c3ac..b279fd8a31b1 100644 --- a/arch/arm/mach-msm/dma.c +++ b/arch/arm/mach-msm/dma.c | |||
@@ -19,9 +19,35 @@ | |||
19 | #include <linux/interrupt.h> | 19 | #include <linux/interrupt.h> |
20 | #include <linux/completion.h> | 20 | #include <linux/completion.h> |
21 | #include <mach/dma.h> | 21 | #include <mach/dma.h> |
22 | #include <mach/msm_iomap.h> | ||
22 | 23 | ||
23 | #define MSM_DMOV_CHANNEL_COUNT 16 | 24 | #define MSM_DMOV_CHANNEL_COUNT 16 |
24 | 25 | ||
26 | #define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2)) | ||
27 | #define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2)) | ||
28 | #define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2)) | ||
29 | #define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2)) | ||
30 | |||
31 | #if defined(CONFIG_ARCH_MSM7X30) | ||
32 | #define DMOV_SD_AARM DMOV_SD2 | ||
33 | #else | ||
34 | #define DMOV_SD_AARM DMOV_SD3 | ||
35 | #endif | ||
36 | |||
37 | #define DMOV_CMD_PTR(ch) DMOV_SD_AARM(0x000, ch) | ||
38 | #define DMOV_RSLT(ch) DMOV_SD_AARM(0x040, ch) | ||
39 | #define DMOV_FLUSH0(ch) DMOV_SD_AARM(0x080, ch) | ||
40 | #define DMOV_FLUSH1(ch) DMOV_SD_AARM(0x0C0, ch) | ||
41 | #define DMOV_FLUSH2(ch) DMOV_SD_AARM(0x100, ch) | ||
42 | #define DMOV_FLUSH3(ch) DMOV_SD_AARM(0x140, ch) | ||
43 | #define DMOV_FLUSH4(ch) DMOV_SD_AARM(0x180, ch) | ||
44 | #define DMOV_FLUSH5(ch) DMOV_SD_AARM(0x1C0, ch) | ||
45 | |||
46 | #define DMOV_STATUS(ch) DMOV_SD_AARM(0x200, ch) | ||
47 | #define DMOV_ISR DMOV_SD_AARM(0x380, 0) | ||
48 | |||
49 | #define DMOV_CONFIG(ch) DMOV_SD_AARM(0x300, ch) | ||
50 | |||
25 | enum { | 51 | enum { |
26 | MSM_DMOV_PRINT_ERRORS = 1, | 52 | MSM_DMOV_PRINT_ERRORS = 1, |
27 | MSM_DMOV_PRINT_IO = 2, | 53 | MSM_DMOV_PRINT_IO = 2, |
diff --git a/arch/arm/mach-msm/include/mach/cpu.h b/arch/arm/mach-msm/include/mach/cpu.h deleted file mode 100644 index a9481b08d5c7..000000000000 --- a/arch/arm/mach-msm/include/mach/cpu.h +++ /dev/null | |||
@@ -1,54 +0,0 @@ | |||
1 | /* Copyright (c) 2011, Code Aurora Forum. All rights reserved. | ||
2 | * | ||
3 | * This program is free software; you can redistribute it and/or modify | ||
4 | * it under the terms of the GNU General Public License version 2 and | ||
5 | * only version 2 as published by the Free Software Foundation. | ||
6 | * | ||
7 | * This program is distributed in the hope that it will be useful, | ||
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | * GNU General Public License for more details. | ||
11 | * | ||
12 | * You should have received a copy of the GNU General Public License | ||
13 | * along with this program; if not, write to the Free Software | ||
14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
15 | * 02110-1301, USA. | ||
16 | */ | ||
17 | |||
18 | #ifndef __ARCH_ARM_MACH_MSM_CPU_H__ | ||
19 | #define __ARCH_ARM_MACH_MSM_CPU_H__ | ||
20 | |||
21 | /* TODO: For now, only one CPU can be compiled at a time. */ | ||
22 | |||
23 | #define cpu_is_msm7x01() 0 | ||
24 | #define cpu_is_msm7x30() 0 | ||
25 | #define cpu_is_qsd8x50() 0 | ||
26 | #define cpu_is_msm8x60() 0 | ||
27 | #define cpu_is_msm8960() 0 | ||
28 | |||
29 | #ifdef CONFIG_ARCH_MSM7X00A | ||
30 | # undef cpu_is_msm7x01 | ||
31 | # define cpu_is_msm7x01() 1 | ||
32 | #endif | ||
33 | |||
34 | #ifdef CONFIG_ARCH_MSM7X30 | ||
35 | # undef cpu_is_msm7x30 | ||
36 | # define cpu_is_msm7x30() 1 | ||
37 | #endif | ||
38 | |||
39 | #ifdef CONFIG_ARCH_QSD8X50 | ||
40 | # undef cpu_is_qsd8x50 | ||
41 | # define cpu_is_qsd8x50() 1 | ||
42 | #endif | ||
43 | |||
44 | #ifdef CONFIG_ARCH_MSM8X60 | ||
45 | # undef cpu_is_msm8x60 | ||
46 | # define cpu_is_msm8x60() 1 | ||
47 | #endif | ||
48 | |||
49 | #ifdef CONFIG_ARCH_MSM8960 | ||
50 | # undef cpu_is_msm8960 | ||
51 | # define cpu_is_msm8960() 1 | ||
52 | #endif | ||
53 | |||
54 | #endif | ||
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h index 05583f569524..a72d48d42342 100644 --- a/arch/arm/mach-msm/include/mach/dma.h +++ b/arch/arm/mach-msm/include/mach/dma.h | |||
@@ -16,7 +16,6 @@ | |||
16 | #ifndef __ASM_ARCH_MSM_DMA_H | 16 | #ifndef __ASM_ARCH_MSM_DMA_H |
17 | 17 | ||
18 | #include <linux/list.h> | 18 | #include <linux/list.h> |
19 | #include <mach/msm_iomap.h> | ||
20 | 19 | ||
21 | struct msm_dmov_errdata { | 20 | struct msm_dmov_errdata { |
22 | uint32_t flush[6]; | 21 | uint32_t flush[6]; |
@@ -45,48 +44,23 @@ static inline | |||
45 | int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { return -EIO; } | 44 | int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { return -EIO; } |
46 | #endif | 45 | #endif |
47 | 46 | ||
48 | |||
49 | #define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2)) | ||
50 | #define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2)) | ||
51 | #define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2)) | ||
52 | #define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2)) | ||
53 | |||
54 | #if defined(CONFIG_ARCH_MSM7X30) | ||
55 | #define DMOV_SD_AARM DMOV_SD2 | ||
56 | #else | ||
57 | #define DMOV_SD_AARM DMOV_SD3 | ||
58 | #endif | ||
59 | |||
60 | #define DMOV_CMD_PTR(ch) DMOV_SD_AARM(0x000, ch) | ||
61 | #define DMOV_CMD_LIST (0 << 29) /* does not work */ | 47 | #define DMOV_CMD_LIST (0 << 29) /* does not work */ |
62 | #define DMOV_CMD_PTR_LIST (1 << 29) /* works */ | 48 | #define DMOV_CMD_PTR_LIST (1 << 29) /* works */ |
63 | #define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */ | 49 | #define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */ |
64 | #define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */ | 50 | #define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */ |
65 | #define DMOV_CMD_ADDR(addr) ((addr) >> 3) | 51 | #define DMOV_CMD_ADDR(addr) ((addr) >> 3) |
66 | 52 | ||
67 | #define DMOV_RSLT(ch) DMOV_SD_AARM(0x040, ch) | ||
68 | #define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */ | 53 | #define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */ |
69 | #define DMOV_RSLT_ERROR (1 << 3) | 54 | #define DMOV_RSLT_ERROR (1 << 3) |
70 | #define DMOV_RSLT_FLUSH (1 << 2) | 55 | #define DMOV_RSLT_FLUSH (1 << 2) |
71 | #define DMOV_RSLT_DONE (1 << 1) /* top pointer done */ | 56 | #define DMOV_RSLT_DONE (1 << 1) /* top pointer done */ |
72 | #define DMOV_RSLT_USER (1 << 0) /* command with FR force result */ | 57 | #define DMOV_RSLT_USER (1 << 0) /* command with FR force result */ |
73 | 58 | ||
74 | #define DMOV_FLUSH0(ch) DMOV_SD_AARM(0x080, ch) | ||
75 | #define DMOV_FLUSH1(ch) DMOV_SD_AARM(0x0C0, ch) | ||
76 | #define DMOV_FLUSH2(ch) DMOV_SD_AARM(0x100, ch) | ||
77 | #define DMOV_FLUSH3(ch) DMOV_SD_AARM(0x140, ch) | ||
78 | #define DMOV_FLUSH4(ch) DMOV_SD_AARM(0x180, ch) | ||
79 | #define DMOV_FLUSH5(ch) DMOV_SD_AARM(0x1C0, ch) | ||
80 | |||
81 | #define DMOV_STATUS(ch) DMOV_SD_AARM(0x200, ch) | ||
82 | #define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29)) | 59 | #define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29)) |
83 | #define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3) | 60 | #define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3) |
84 | #define DMOV_STATUS_RSLT_VALID (1 << 1) | 61 | #define DMOV_STATUS_RSLT_VALID (1 << 1) |
85 | #define DMOV_STATUS_CMD_PTR_RDY (1 << 0) | 62 | #define DMOV_STATUS_CMD_PTR_RDY (1 << 0) |
86 | 63 | ||
87 | #define DMOV_ISR DMOV_SD_AARM(0x380, 0) | ||
88 | |||
89 | #define DMOV_CONFIG(ch) DMOV_SD_AARM(0x300, ch) | ||
90 | #define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2) | 64 | #define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2) |
91 | #define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1) | 65 | #define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1) |
92 | #define DMOV_CONFIG_IRQ_EN (1 << 0) | 66 | #define DMOV_CONFIG_IRQ_EN (1 << 0) |
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index 42932865416a..00cdb0a5dac8 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c | |||
@@ -15,7 +15,6 @@ | |||
15 | #include <linux/jiffies.h> | 15 | #include <linux/jiffies.h> |
16 | #include <linux/smp.h> | 16 | #include <linux/smp.h> |
17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
18 | #include <linux/irqchip/arm-gic.h> | ||
19 | 18 | ||
20 | #include <asm/cacheflush.h> | 19 | #include <asm/cacheflush.h> |
21 | #include <asm/cputype.h> | 20 | #include <asm/cputype.h> |
@@ -42,13 +41,6 @@ static inline int get_core_count(void) | |||
42 | static void __cpuinit msm_secondary_init(unsigned int cpu) | 41 | static void __cpuinit msm_secondary_init(unsigned int cpu) |
43 | { | 42 | { |
44 | /* | 43 | /* |
45 | * if any interrupts are already enabled for the primary | ||
46 | * core (e.g. timer irq), then they will not have been enabled | ||
47 | * for us: do so | ||
48 | */ | ||
49 | gic_secondary_init(0); | ||
50 | |||
51 | /* | ||
52 | * let the primary processor know we're out of the | 44 | * let the primary processor know we're out of the |
53 | * pen, then head off into the C entry point | 45 | * pen, then head off into the C entry point |
54 | */ | 46 | */ |
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index 3d3c8a973062..80db7269760e 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile | |||
@@ -1,6 +1,2 @@ | |||
1 | # Common support | ||
2 | obj-y := icoll.o ocotp.o system.o timer.o mm.o | ||
3 | |||
4 | obj-$(CONFIG_PM) += pm.o | 1 | obj-$(CONFIG_PM) += pm.o |
5 | |||
6 | obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o | 2 | obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o |
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h deleted file mode 100644 index be5a9c93cb2a..000000000000 --- a/arch/arm/mach-mxs/include/mach/common.h +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | */ | ||
4 | |||
5 | /* | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __MACH_MXS_COMMON_H__ | ||
12 | #define __MACH_MXS_COMMON_H__ | ||
13 | |||
14 | extern const u32 *mxs_get_ocotp(void); | ||
15 | extern int mxs_reset_block(void __iomem *); | ||
16 | extern void mxs_timer_init(void); | ||
17 | extern void mxs_restart(char, const char *); | ||
18 | extern int mxs_saif_clkmux_select(unsigned int clkmux); | ||
19 | |||
20 | extern int mx23_clocks_init(void); | ||
21 | extern void mx23_map_io(void); | ||
22 | |||
23 | extern int mx28_clocks_init(void); | ||
24 | extern void mx28_map_io(void); | ||
25 | |||
26 | extern void icoll_init_irq(void); | ||
27 | extern void icoll_handle_irq(struct pt_regs *); | ||
28 | |||
29 | #endif /* __MACH_MXS_COMMON_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/debug-macro.S b/arch/arm/mach-mxs/include/mach/debug-macro.S index 90c6b7836ad3..d86951551ca1 100644 --- a/arch/arm/mach-mxs/include/mach/debug-macro.S +++ b/arch/arm/mach-mxs/include/mach/debug-macro.S | |||
@@ -11,16 +11,13 @@ | |||
11 | * | 11 | * |
12 | */ | 12 | */ |
13 | 13 | ||
14 | #include <mach/mx23.h> | ||
15 | #include <mach/mx28.h> | ||
16 | |||
17 | #ifdef CONFIG_DEBUG_IMX23_UART | 14 | #ifdef CONFIG_DEBUG_IMX23_UART |
18 | #define UART_PADDR MX23_DUART_BASE_ADDR | 15 | #define UART_PADDR 0x80070000 |
19 | #elif defined (CONFIG_DEBUG_IMX28_UART) | 16 | #elif defined (CONFIG_DEBUG_IMX28_UART) |
20 | #define UART_PADDR MX28_DUART_BASE_ADDR | 17 | #define UART_PADDR 0x80074000 |
21 | #endif | 18 | #endif |
22 | 19 | ||
23 | #define UART_VADDR MXS_IO_ADDRESS(UART_PADDR) | 20 | #define UART_VADDR 0xfe100000 |
24 | 21 | ||
25 | .macro addruart, rp, rv, tmp | 22 | .macro addruart, rp, rv, tmp |
26 | ldr \rp, =UART_PADDR @ physical | 23 | ldr \rp, =UART_PADDR @ physical |
diff --git a/arch/arm/mach-mxs/include/mach/digctl.h b/arch/arm/mach-mxs/include/mach/digctl.h deleted file mode 100644 index 17964066303f..000000000000 --- a/arch/arm/mach-mxs/include/mach/digctl.h +++ /dev/null | |||
@@ -1,22 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | |||
9 | #ifndef __MACH_DIGCTL_H__ | ||
10 | #define __MACH_DIGCTL_H__ | ||
11 | |||
12 | /* MXS DIGCTL SAIF CLKMUX */ | ||
13 | #define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0 | ||
14 | #define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1 | ||
15 | #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2 | ||
16 | #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3 | ||
17 | |||
18 | #define HW_DIGCTL_CTRL 0x0 | ||
19 | #define BP_DIGCTL_CTRL_SAIF_CLKMUX 10 | ||
20 | #define BM_DIGCTL_CTRL_SAIF_CLKMUX (0x3 << 10) | ||
21 | #define HW_DIGCTL_CHIPID 0x310 | ||
22 | #endif | ||
diff --git a/arch/arm/mach-mxs/include/mach/hardware.h b/arch/arm/mach-mxs/include/mach/hardware.h deleted file mode 100644 index 4c0e8a64d8c7..000000000000 --- a/arch/arm/mach-mxs/include/mach/hardware.h +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * as published by the Free Software Foundation; either version 2 | ||
8 | * of the License, or (at your option) any later version. | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
17 | * MA 02110-1301, USA. | ||
18 | */ | ||
19 | |||
20 | #ifndef __MACH_MXS_HARDWARE_H__ | ||
21 | #define __MACH_MXS_HARDWARE_H__ | ||
22 | |||
23 | #endif /* __MACH_MXS_HARDWARE_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h deleted file mode 100644 index 599094bc99de..000000000000 --- a/arch/arm/mach-mxs/include/mach/mx23.h +++ /dev/null | |||
@@ -1,169 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License along | ||
15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
17 | */ | ||
18 | |||
19 | #ifndef __MACH_MX23_H__ | ||
20 | #define __MACH_MX23_H__ | ||
21 | |||
22 | #include <mach/mxs.h> | ||
23 | |||
24 | /* | ||
25 | * OCRAM | ||
26 | */ | ||
27 | #define MX23_OCRAM_BASE_ADDR 0x00000000 | ||
28 | #define MX23_OCRAM_SIZE SZ_32K | ||
29 | |||
30 | /* | ||
31 | * IO | ||
32 | */ | ||
33 | #define MX23_IO_BASE_ADDR 0x80000000 | ||
34 | #define MX23_IO_SIZE SZ_1M | ||
35 | |||
36 | #define MX23_ICOLL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x000000) | ||
37 | #define MX23_APBH_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x004000) | ||
38 | #define MX23_BCH_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00a000) | ||
39 | #define MX23_GPMI_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00c000) | ||
40 | #define MX23_SSP1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x010000) | ||
41 | #define MX23_PINCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x018000) | ||
42 | #define MX23_DIGCTL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x01c000) | ||
43 | #define MX23_ETM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x020000) | ||
44 | #define MX23_APBX_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x024000) | ||
45 | #define MX23_DCP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x028000) | ||
46 | #define MX23_PXP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02a000) | ||
47 | #define MX23_OCOTP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02c000) | ||
48 | #define MX23_AXI_AHB0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02e000) | ||
49 | #define MX23_LCDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x030000) | ||
50 | #define MX23_SSP2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x034000) | ||
51 | #define MX23_TVENC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x038000) | ||
52 | #define MX23_CLKCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x040000) | ||
53 | #define MX23_SAIF0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x042000) | ||
54 | #define MX23_POWER_BASE_ADDR (MX23_IO_BASE_ADDR + 0x044000) | ||
55 | #define MX23_SAIF1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x046000) | ||
56 | #define MX23_AUDIOOUT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x048000) | ||
57 | #define MX23_AUDIOIN_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04c000) | ||
58 | #define MX23_LRADC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x050000) | ||
59 | #define MX23_SPDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x054000) | ||
60 | #define MX23_I2C_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000) | ||
61 | #define MX23_RTC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05c000) | ||
62 | #define MX23_PWM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x064000) | ||
63 | #define MX23_TIMROT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x068000) | ||
64 | #define MX23_AUART1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06c000) | ||
65 | #define MX23_AUART2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06e000) | ||
66 | #define MX23_DUART_BASE_ADDR (MX23_IO_BASE_ADDR + 0x070000) | ||
67 | #define MX23_USBPHY_BASE_ADDR (MX23_IO_BASE_ADDR + 0x07c000) | ||
68 | #define MX23_USBCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x080000) | ||
69 | #define MX23_DRAM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x0e0000) | ||
70 | |||
71 | #define MX23_IO_P2V(x) MXS_IO_P2V(x) | ||
72 | #define MX23_IO_ADDRESS(x) IOMEM(MX23_IO_P2V(x)) | ||
73 | |||
74 | /* | ||
75 | * IRQ | ||
76 | */ | ||
77 | #define MX23_INT_DUART 0 | ||
78 | #define MX23_INT_COMMS_RX 1 | ||
79 | #define MX23_INT_COMMS_TX 1 | ||
80 | #define MX23_INT_SSP2_ERROR 2 | ||
81 | #define MX23_INT_VDD5V 3 | ||
82 | #define MX23_INT_HEADPHONE_SHORT 4 | ||
83 | #define MX23_INT_DAC_DMA 5 | ||
84 | #define MX23_INT_DAC_ERROR 6 | ||
85 | #define MX23_INT_ADC_DMA 7 | ||
86 | #define MX23_INT_ADC_ERROR 8 | ||
87 | #define MX23_INT_SPDIF_DMA 9 | ||
88 | #define MX23_INT_SAIF2_DMA 9 | ||
89 | #define MX23_INT_SPDIF_ERROR 10 | ||
90 | #define MX23_INT_SAIF1_IRQ 10 | ||
91 | #define MX23_INT_SAIF2_IRQ 10 | ||
92 | #define MX23_INT_USB_CTRL 11 | ||
93 | #define MX23_INT_USB_WAKEUP 12 | ||
94 | #define MX23_INT_GPMI_DMA 13 | ||
95 | #define MX23_INT_SSP1_DMA 14 | ||
96 | #define MX23_INT_SSP1_ERROR 15 | ||
97 | #define MX23_INT_GPIO0 16 | ||
98 | #define MX23_INT_GPIO1 17 | ||
99 | #define MX23_INT_GPIO2 18 | ||
100 | #define MX23_INT_SAIF1_DMA 19 | ||
101 | #define MX23_INT_SSP2_DMA 20 | ||
102 | #define MX23_INT_ECC8_IRQ 21 | ||
103 | #define MX23_INT_RTC_ALARM 22 | ||
104 | #define MX23_INT_AUART1_TX_DMA 23 | ||
105 | #define MX23_INT_AUART1 24 | ||
106 | #define MX23_INT_AUART1_RX_DMA 25 | ||
107 | #define MX23_INT_I2C_DMA 26 | ||
108 | #define MX23_INT_I2C_ERROR 27 | ||
109 | #define MX23_INT_TIMER0 28 | ||
110 | #define MX23_INT_TIMER1 29 | ||
111 | #define MX23_INT_TIMER2 30 | ||
112 | #define MX23_INT_TIMER3 31 | ||
113 | #define MX23_INT_BATT_BRNOUT 32 | ||
114 | #define MX23_INT_VDDD_BRNOUT 33 | ||
115 | #define MX23_INT_VDDIO_BRNOUT 34 | ||
116 | #define MX23_INT_VDD18_BRNOUT 35 | ||
117 | #define MX23_INT_TOUCH_DETECT 36 | ||
118 | #define MX23_INT_LRADC_CH0 37 | ||
119 | #define MX23_INT_LRADC_CH1 38 | ||
120 | #define MX23_INT_LRADC_CH2 39 | ||
121 | #define MX23_INT_LRADC_CH3 40 | ||
122 | #define MX23_INT_LRADC_CH4 41 | ||
123 | #define MX23_INT_LRADC_CH5 42 | ||
124 | #define MX23_INT_LRADC_CH6 43 | ||
125 | #define MX23_INT_LRADC_CH7 44 | ||
126 | #define MX23_INT_LCDIF_DMA 45 | ||
127 | #define MX23_INT_LCDIF_ERROR 46 | ||
128 | #define MX23_INT_DIGCTL_DEBUG_TRAP 47 | ||
129 | #define MX23_INT_RTC_1MSEC 48 | ||
130 | #define MX23_INT_DRI_DMA 49 | ||
131 | #define MX23_INT_DRI_ATTENTION 50 | ||
132 | #define MX23_INT_GPMI_ATTENTION 51 | ||
133 | #define MX23_INT_IR 52 | ||
134 | #define MX23_INT_DCP_VMI 53 | ||
135 | #define MX23_INT_DCP 54 | ||
136 | #define MX23_INT_BCH 56 | ||
137 | #define MX23_INT_PXP 57 | ||
138 | #define MX23_INT_AUART2_TX_DMA 58 | ||
139 | #define MX23_INT_AUART2 59 | ||
140 | #define MX23_INT_AUART2_RX_DMA 60 | ||
141 | #define MX23_INT_VDAC_DETECT 61 | ||
142 | #define MX23_INT_VDD5V_DROOP 64 | ||
143 | #define MX23_INT_DCDC4P2_BO 65 | ||
144 | |||
145 | /* | ||
146 | * APBH DMA | ||
147 | */ | ||
148 | #define MX23_DMA_SSP1 1 | ||
149 | #define MX23_DMA_SSP2 2 | ||
150 | #define MX23_DMA_GPMI0 4 | ||
151 | #define MX23_DMA_GPMI1 5 | ||
152 | #define MX23_DMA_GPMI2 6 | ||
153 | #define MX23_DMA_GPMI3 7 | ||
154 | |||
155 | /* | ||
156 | * APBX DMA | ||
157 | */ | ||
158 | #define MX23_DMA_ADC 0 | ||
159 | #define MX23_DMA_DAC 1 | ||
160 | #define MX23_DMA_SPDIF 2 | ||
161 | #define MX23_DMA_I2C 3 | ||
162 | #define MX23_DMA_SAIF0 4 | ||
163 | #define MX23_DMA_UART0_RX 6 | ||
164 | #define MX23_DMA_UART0_TX 7 | ||
165 | #define MX23_DMA_UART1_RX 8 | ||
166 | #define MX23_DMA_UART1_TX 9 | ||
167 | #define MX23_DMA_SAIF1 10 | ||
168 | |||
169 | #endif /* __MACH_MX23_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h deleted file mode 100644 index 30c7990f3c01..000000000000 --- a/arch/arm/mach-mxs/include/mach/mx28.h +++ /dev/null | |||
@@ -1,225 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License along | ||
15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
17 | */ | ||
18 | |||
19 | #ifndef __MACH_MX28_H__ | ||
20 | #define __MACH_MX28_H__ | ||
21 | |||
22 | #include <mach/mxs.h> | ||
23 | |||
24 | /* | ||
25 | * OCRAM | ||
26 | */ | ||
27 | #define MX28_OCRAM_BASE_ADDR 0x00000000 | ||
28 | #define MX28_OCRAM_SIZE SZ_128K | ||
29 | |||
30 | /* | ||
31 | * IO | ||
32 | */ | ||
33 | #define MX28_IO_BASE_ADDR 0x80000000 | ||
34 | #define MX28_IO_SIZE SZ_1M | ||
35 | |||
36 | #define MX28_ICOLL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x000000) | ||
37 | #define MX28_HSADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x002000) | ||
38 | #define MX28_APBH_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x004000) | ||
39 | #define MX28_PERFMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x006000) | ||
40 | #define MX28_BCH_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00a000) | ||
41 | #define MX28_GPMI_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00c000) | ||
42 | #define MX28_SSP0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x010000) | ||
43 | #define MX28_SSP1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x012000) | ||
44 | #define MX28_SSP2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x014000) | ||
45 | #define MX28_SSP3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x016000) | ||
46 | #define MX28_PINCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x018000) | ||
47 | #define MX28_DIGCTL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x01c000) | ||
48 | #define MX28_ETM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x022000) | ||
49 | #define MX28_APBX_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x024000) | ||
50 | #define MX28_DCP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x028000) | ||
51 | #define MX28_PXP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02a000) | ||
52 | #define MX28_OCOTP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02c000) | ||
53 | #define MX28_AXI_AHB0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02e000) | ||
54 | #define MX28_LCDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x030000) | ||
55 | #define MX28_CAN0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x032000) | ||
56 | #define MX28_CAN1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x034000) | ||
57 | #define MX28_SIMDBG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c000) | ||
58 | #define MX28_SIMGPMISEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c200) | ||
59 | #define MX28_SIMSSPSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c300) | ||
60 | #define MX28_SIMMEMSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c400) | ||
61 | #define MX28_GPIOMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c500) | ||
62 | #define MX28_SIMENET_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c700) | ||
63 | #define MX28_ARMJTAG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c800) | ||
64 | #define MX28_CLKCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x040000) | ||
65 | #define MX28_SAIF0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x042000) | ||
66 | #define MX28_POWER_BASE_ADDR (MX28_IO_BASE_ADDR + 0x044000) | ||
67 | #define MX28_SAIF1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x046000) | ||
68 | #define MX28_LRADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x050000) | ||
69 | #define MX28_SPDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x054000) | ||
70 | #define MX28_RTC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x056000) | ||
71 | #define MX28_I2C0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x058000) | ||
72 | #define MX28_I2C1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x05a000) | ||
73 | #define MX28_PWM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x064000) | ||
74 | #define MX28_TIMROT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x068000) | ||
75 | #define MX28_AUART0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06a000) | ||
76 | #define MX28_AUART1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06c000) | ||
77 | #define MX28_AUART2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06e000) | ||
78 | #define MX28_AUART3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x070000) | ||
79 | #define MX28_AUART4_BASE_ADDR (MX28_IO_BASE_ADDR + 0x072000) | ||
80 | #define MX28_DUART_BASE_ADDR (MX28_IO_BASE_ADDR + 0x074000) | ||
81 | #define MX28_USBPHY0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07C000) | ||
82 | #define MX28_USBPHY1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07e000) | ||
83 | #define MX28_USBCTRL0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x080000) | ||
84 | #define MX28_USBCTRL1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x090000) | ||
85 | #define MX28_DFLPT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0c0000) | ||
86 | #define MX28_DRAM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0e0000) | ||
87 | #define MX28_ENET_MAC0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f0000) | ||
88 | #define MX28_ENET_MAC1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f4000) | ||
89 | |||
90 | #define MX28_IO_P2V(x) MXS_IO_P2V(x) | ||
91 | #define MX28_IO_ADDRESS(x) IOMEM(MX28_IO_P2V(x)) | ||
92 | |||
93 | /* | ||
94 | * IRQ | ||
95 | */ | ||
96 | #define MX28_INT_BATT_BRNOUT 0 | ||
97 | #define MX28_INT_VDDD_BRNOUT 1 | ||
98 | #define MX28_INT_VDDIO_BRNOUT 2 | ||
99 | #define MX28_INT_VDDA_BRNOUT 3 | ||
100 | #define MX28_INT_VDD5V_DROOP 4 | ||
101 | #define MX28_INT_DCDC4P2_BRNOUT 5 | ||
102 | #define MX28_INT_VDD5V 6 | ||
103 | #define MX28_INT_CAN0 8 | ||
104 | #define MX28_INT_CAN1 9 | ||
105 | #define MX28_INT_LRADC_TOUCH 10 | ||
106 | #define MX28_INT_HSADC 13 | ||
107 | #define MX28_INT_LRADC_THRESH0 14 | ||
108 | #define MX28_INT_LRADC_THRESH1 15 | ||
109 | #define MX28_INT_LRADC_CH0 16 | ||
110 | #define MX28_INT_LRADC_CH1 17 | ||
111 | #define MX28_INT_LRADC_CH2 18 | ||
112 | #define MX28_INT_LRADC_CH3 19 | ||
113 | #define MX28_INT_LRADC_CH4 20 | ||
114 | #define MX28_INT_LRADC_CH5 21 | ||
115 | #define MX28_INT_LRADC_CH6 22 | ||
116 | #define MX28_INT_LRADC_CH7 23 | ||
117 | #define MX28_INT_LRADC_BUTTON0 24 | ||
118 | #define MX28_INT_LRADC_BUTTON1 25 | ||
119 | #define MX28_INT_PERFMON 27 | ||
120 | #define MX28_INT_RTC_1MSEC 28 | ||
121 | #define MX28_INT_RTC_ALARM 29 | ||
122 | #define MX28_INT_COMMS 31 | ||
123 | #define MX28_INT_EMI_ERR 32 | ||
124 | #define MX28_INT_LCDIF 38 | ||
125 | #define MX28_INT_PXP 39 | ||
126 | #define MX28_INT_BCH 41 | ||
127 | #define MX28_INT_GPMI 42 | ||
128 | #define MX28_INT_SPDIF_ERROR 45 | ||
129 | #define MX28_INT_DUART 47 | ||
130 | #define MX28_INT_TIMER0 48 | ||
131 | #define MX28_INT_TIMER1 49 | ||
132 | #define MX28_INT_TIMER2 50 | ||
133 | #define MX28_INT_TIMER3 51 | ||
134 | #define MX28_INT_DCP_VMI 52 | ||
135 | #define MX28_INT_DCP 53 | ||
136 | #define MX28_INT_DCP_SECURE 54 | ||
137 | #define MX28_INT_SAIF1 58 | ||
138 | #define MX28_INT_SAIF0 59 | ||
139 | #define MX28_INT_SPDIF_DMA 66 | ||
140 | #define MX28_INT_I2C0_DMA 68 | ||
141 | #define MX28_INT_I2C1_DMA 69 | ||
142 | #define MX28_INT_AUART0_RX_DMA 70 | ||
143 | #define MX28_INT_AUART0_TX_DMA 71 | ||
144 | #define MX28_INT_AUART1_RX_DMA 72 | ||
145 | #define MX28_INT_AUART1_TX_DMA 73 | ||
146 | #define MX28_INT_AUART2_RX_DMA 74 | ||
147 | #define MX28_INT_AUART2_TX_DMA 75 | ||
148 | #define MX28_INT_AUART3_RX_DMA 76 | ||
149 | #define MX28_INT_AUART3_TX_DMA 77 | ||
150 | #define MX28_INT_AUART4_RX_DMA 78 | ||
151 | #define MX28_INT_AUART4_TX_DMA 79 | ||
152 | #define MX28_INT_SAIF0_DMA 80 | ||
153 | #define MX28_INT_SAIF1_DMA 81 | ||
154 | #define MX28_INT_SSP0_DMA 82 | ||
155 | #define MX28_INT_SSP1_DMA 83 | ||
156 | #define MX28_INT_SSP2_DMA 84 | ||
157 | #define MX28_INT_SSP3_DMA 85 | ||
158 | #define MX28_INT_LCDIF_DMA 86 | ||
159 | #define MX28_INT_HSADC_DMA 87 | ||
160 | #define MX28_INT_GPMI_DMA 88 | ||
161 | #define MX28_INT_DIGCTL_DEBUG_TRAP 89 | ||
162 | #define MX28_INT_USB1 92 | ||
163 | #define MX28_INT_USB0 93 | ||
164 | #define MX28_INT_USB1_WAKEUP 94 | ||
165 | #define MX28_INT_USB0_WAKEUP 95 | ||
166 | #define MX28_INT_SSP0_ERROR 96 | ||
167 | #define MX28_INT_SSP1_ERROR 97 | ||
168 | #define MX28_INT_SSP2_ERROR 98 | ||
169 | #define MX28_INT_SSP3_ERROR 99 | ||
170 | #define MX28_INT_ENET_SWI 100 | ||
171 | #define MX28_INT_ENET_MAC0 101 | ||
172 | #define MX28_INT_ENET_MAC1 102 | ||
173 | #define MX28_INT_ENET_MAC0_1588 103 | ||
174 | #define MX28_INT_ENET_MAC1_1588 104 | ||
175 | #define MX28_INT_I2C1_ERROR 110 | ||
176 | #define MX28_INT_I2C0_ERROR 111 | ||
177 | #define MX28_INT_AUART0 112 | ||
178 | #define MX28_INT_AUART1 113 | ||
179 | #define MX28_INT_AUART2 114 | ||
180 | #define MX28_INT_AUART3 115 | ||
181 | #define MX28_INT_AUART4 116 | ||
182 | #define MX28_INT_GPIO4 123 | ||
183 | #define MX28_INT_GPIO3 124 | ||
184 | #define MX28_INT_GPIO2 125 | ||
185 | #define MX28_INT_GPIO1 126 | ||
186 | #define MX28_INT_GPIO0 127 | ||
187 | |||
188 | /* | ||
189 | * APBH DMA | ||
190 | */ | ||
191 | #define MX28_DMA_SSP0 0 | ||
192 | #define MX28_DMA_SSP1 1 | ||
193 | #define MX28_DMA_SSP2 2 | ||
194 | #define MX28_DMA_SSP3 3 | ||
195 | #define MX28_DMA_GPMI0 4 | ||
196 | #define MX28_DMA_GPMI1 5 | ||
197 | #define MX28_DMA_GPMI2 6 | ||
198 | #define MX28_DMA_GPMI3 7 | ||
199 | #define MX28_DMA_GPMI4 8 | ||
200 | #define MX28_DMA_GPMI5 9 | ||
201 | #define MX28_DMA_GPMI6 10 | ||
202 | #define MX28_DMA_GPMI7 11 | ||
203 | #define MX28_DMA_HSADC 12 | ||
204 | #define MX28_DMA_LCDIF 13 | ||
205 | |||
206 | /* | ||
207 | * APBX DMA | ||
208 | */ | ||
209 | #define MX28_DMA_AUART4_RX 0 | ||
210 | #define MX28_DMA_AUART4_TX 1 | ||
211 | #define MX28_DMA_SPDIF_TX 2 | ||
212 | #define MX28_DMA_SAIF0 4 | ||
213 | #define MX28_DMA_SAIF1 5 | ||
214 | #define MX28_DMA_I2C0 6 | ||
215 | #define MX28_DMA_I2C1 7 | ||
216 | #define MX28_DMA_AUART0_RX 8 | ||
217 | #define MX28_DMA_AUART0_TX 9 | ||
218 | #define MX28_DMA_AUART1_RX 10 | ||
219 | #define MX28_DMA_AUART1_TX 11 | ||
220 | #define MX28_DMA_AUART2_RX 12 | ||
221 | #define MX28_DMA_AUART2_TX 13 | ||
222 | #define MX28_DMA_AUART3_RX 14 | ||
223 | #define MX28_DMA_AUART3_TX 15 | ||
224 | |||
225 | #endif /* __MACH_MX28_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h deleted file mode 100644 index 7d4fb6d0afda..000000000000 --- a/arch/arm/mach-mxs/include/mach/mxs.h +++ /dev/null | |||
@@ -1,117 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License along | ||
15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
17 | */ | ||
18 | |||
19 | #ifndef __MACH_MXS_H__ | ||
20 | #define __MACH_MXS_H__ | ||
21 | |||
22 | #ifndef __ASSEMBLER__ | ||
23 | #include <linux/io.h> | ||
24 | #endif | ||
25 | #include <asm/mach-types.h> | ||
26 | #include <mach/digctl.h> | ||
27 | #include <mach/hardware.h> | ||
28 | |||
29 | /* | ||
30 | * IO addresses common to MXS-based | ||
31 | */ | ||
32 | #define MXS_IO_BASE_ADDR 0x80000000 | ||
33 | #define MXS_IO_SIZE SZ_1M | ||
34 | |||
35 | #define MXS_ICOLL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x000000) | ||
36 | #define MXS_APBH_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x004000) | ||
37 | #define MXS_BCH_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00a000) | ||
38 | #define MXS_GPMI_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00c000) | ||
39 | #define MXS_PINCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x018000) | ||
40 | #define MXS_DIGCTL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x01c000) | ||
41 | #define MXS_APBX_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x024000) | ||
42 | #define MXS_DCP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x028000) | ||
43 | #define MXS_PXP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02a000) | ||
44 | #define MXS_OCOTP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02c000) | ||
45 | #define MXS_AXI_AHB0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02e000) | ||
46 | #define MXS_LCDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x030000) | ||
47 | #define MXS_CLKCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x040000) | ||
48 | #define MXS_SAIF0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x042000) | ||
49 | #define MXS_POWER_BASE_ADDR (MXS_IO_BASE_ADDR + 0x044000) | ||
50 | #define MXS_SAIF1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x046000) | ||
51 | #define MXS_LRADC_BASE_ADDR (MXS_IO_BASE_ADDR + 0x050000) | ||
52 | #define MXS_SPDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x054000) | ||
53 | #define MXS_I2C0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x058000) | ||
54 | #define MXS_PWM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x064000) | ||
55 | #define MXS_TIMROT_BASE_ADDR (MXS_IO_BASE_ADDR + 0x068000) | ||
56 | #define MXS_AUART1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06c000) | ||
57 | #define MXS_AUART2_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06e000) | ||
58 | #define MXS_DRAM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x0e0000) | ||
59 | |||
60 | /* | ||
61 | * It maps the whole address space to [0xf4000000, 0xf50fffff]. | ||
62 | * | ||
63 | * OCRAM 0x00000000+0x020000 -> 0xf4000000+0x020000 | ||
64 | * IO 0x80000000+0x100000 -> 0xf5000000+0x100000 | ||
65 | */ | ||
66 | #define MXS_IO_P2V(x) (0xf4000000 + \ | ||
67 | (((x) & 0x80000000) >> 7) + \ | ||
68 | (((x) & 0x000fffff))) | ||
69 | |||
70 | #define MXS_IO_ADDRESS(x) IOMEM(MXS_IO_P2V(x)) | ||
71 | |||
72 | #define mxs_map_entry(soc, name, _type) { \ | ||
73 | .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ | ||
74 | .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ | ||
75 | .length = soc ## _ ## name ## _SIZE, \ | ||
76 | .type = _type, \ | ||
77 | } | ||
78 | |||
79 | #define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) | ||
80 | |||
81 | #define MXS_SET_ADDR 0x4 | ||
82 | #define MXS_CLR_ADDR 0x8 | ||
83 | #define MXS_TOG_ADDR 0xc | ||
84 | |||
85 | #ifndef __ASSEMBLER__ | ||
86 | static inline void __mxs_setl(u32 mask, void __iomem *reg) | ||
87 | { | ||
88 | __raw_writel(mask, reg + MXS_SET_ADDR); | ||
89 | } | ||
90 | |||
91 | static inline void __mxs_clrl(u32 mask, void __iomem *reg) | ||
92 | { | ||
93 | __raw_writel(mask, reg + MXS_CLR_ADDR); | ||
94 | } | ||
95 | |||
96 | static inline void __mxs_togl(u32 mask, void __iomem *reg) | ||
97 | { | ||
98 | __raw_writel(mask, reg + MXS_TOG_ADDR); | ||
99 | } | ||
100 | |||
101 | /* | ||
102 | * MXS CPU types | ||
103 | */ | ||
104 | #define MXS_CHIPID (MXS_IO_ADDRESS(MXS_DIGCTL_BASE_ADDR) + HW_DIGCTL_CHIPID) | ||
105 | |||
106 | static inline int cpu_is_mx23(void) | ||
107 | { | ||
108 | return ((__raw_readl(MXS_CHIPID) >> 16) == 0x3780); | ||
109 | } | ||
110 | |||
111 | static inline int cpu_is_mx28(void) | ||
112 | { | ||
113 | return ((__raw_readl(MXS_CHIPID) >> 16) == 0x2800); | ||
114 | } | ||
115 | #endif | ||
116 | |||
117 | #endif /* __MACH_MXS_H__ */ | ||
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index e7b781d3788f..16870bf853b8 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c | |||
@@ -11,22 +11,53 @@ | |||
11 | */ | 11 | */ |
12 | 12 | ||
13 | #include <linux/clk.h> | 13 | #include <linux/clk.h> |
14 | #include <linux/clk/mxs.h> | ||
14 | #include <linux/clkdev.h> | 15 | #include <linux/clkdev.h> |
16 | #include <linux/clocksource.h> | ||
15 | #include <linux/can/platform/flexcan.h> | 17 | #include <linux/can/platform/flexcan.h> |
16 | #include <linux/delay.h> | 18 | #include <linux/delay.h> |
17 | #include <linux/err.h> | 19 | #include <linux/err.h> |
18 | #include <linux/gpio.h> | 20 | #include <linux/gpio.h> |
19 | #include <linux/init.h> | 21 | #include <linux/init.h> |
22 | #include <linux/irqchip.h> | ||
23 | #include <linux/irqchip/mxs.h> | ||
20 | #include <linux/micrel_phy.h> | 24 | #include <linux/micrel_phy.h> |
21 | #include <linux/mxsfb.h> | 25 | #include <linux/mxsfb.h> |
26 | #include <linux/of_address.h> | ||
22 | #include <linux/of_platform.h> | 27 | #include <linux/of_platform.h> |
23 | #include <linux/phy.h> | 28 | #include <linux/phy.h> |
24 | #include <linux/pinctrl/consumer.h> | 29 | #include <linux/pinctrl/consumer.h> |
25 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
31 | #include <asm/mach/map.h> | ||
26 | #include <asm/mach/time.h> | 32 | #include <asm/mach/time.h> |
27 | #include <mach/common.h> | 33 | #include <asm/system_misc.h> |
28 | #include <mach/digctl.h> | 34 | |
29 | #include <mach/mxs.h> | 35 | /* MXS DIGCTL SAIF CLKMUX */ |
36 | #define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0 | ||
37 | #define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1 | ||
38 | #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2 | ||
39 | #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3 | ||
40 | |||
41 | #define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) | ||
42 | |||
43 | #define MXS_SET_ADDR 0x4 | ||
44 | #define MXS_CLR_ADDR 0x8 | ||
45 | #define MXS_TOG_ADDR 0xc | ||
46 | |||
47 | static inline void __mxs_setl(u32 mask, void __iomem *reg) | ||
48 | { | ||
49 | __raw_writel(mask, reg + MXS_SET_ADDR); | ||
50 | } | ||
51 | |||
52 | static inline void __mxs_clrl(u32 mask, void __iomem *reg) | ||
53 | { | ||
54 | __raw_writel(mask, reg + MXS_CLR_ADDR); | ||
55 | } | ||
56 | |||
57 | static inline void __mxs_togl(u32 mask, void __iomem *reg) | ||
58 | { | ||
59 | __raw_writel(mask, reg + MXS_TOG_ADDR); | ||
60 | } | ||
30 | 61 | ||
31 | static struct fb_videomode mx23evk_video_modes[] = { | 62 | static struct fb_videomode mx23evk_video_modes[] = { |
32 | { | 63 | { |
@@ -165,14 +196,80 @@ static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = { | |||
165 | { /* sentinel */ } | 196 | { /* sentinel */ } |
166 | }; | 197 | }; |
167 | 198 | ||
168 | static void __init imx23_timer_init(void) | 199 | #define OCOTP_WORD_OFFSET 0x20 |
169 | { | 200 | #define OCOTP_WORD_COUNT 0x20 |
170 | mx23_clocks_init(); | 201 | |
171 | } | 202 | #define BM_OCOTP_CTRL_BUSY (1 << 8) |
203 | #define BM_OCOTP_CTRL_ERROR (1 << 9) | ||
204 | #define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12) | ||
172 | 205 | ||
173 | static void __init imx28_timer_init(void) | 206 | static DEFINE_MUTEX(ocotp_mutex); |
207 | static u32 ocotp_words[OCOTP_WORD_COUNT]; | ||
208 | |||
209 | static const u32 *mxs_get_ocotp(void) | ||
174 | { | 210 | { |
175 | mx28_clocks_init(); | 211 | struct device_node *np; |
212 | void __iomem *ocotp_base; | ||
213 | int timeout = 0x400; | ||
214 | size_t i; | ||
215 | static int once; | ||
216 | |||
217 | if (once) | ||
218 | return ocotp_words; | ||
219 | |||
220 | np = of_find_compatible_node(NULL, NULL, "fsl,ocotp"); | ||
221 | ocotp_base = of_iomap(np, 0); | ||
222 | WARN_ON(!ocotp_base); | ||
223 | |||
224 | mutex_lock(&ocotp_mutex); | ||
225 | |||
226 | /* | ||
227 | * clk_enable(hbus_clk) for ocotp can be skipped | ||
228 | * as it must be on when system is running. | ||
229 | */ | ||
230 | |||
231 | /* try to clear ERROR bit */ | ||
232 | __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base); | ||
233 | |||
234 | /* check both BUSY and ERROR cleared */ | ||
235 | while ((__raw_readl(ocotp_base) & | ||
236 | (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout) | ||
237 | cpu_relax(); | ||
238 | |||
239 | if (unlikely(!timeout)) | ||
240 | goto error_unlock; | ||
241 | |||
242 | /* open OCOTP banks for read */ | ||
243 | __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base); | ||
244 | |||
245 | /* approximately wait 32 hclk cycles */ | ||
246 | udelay(1); | ||
247 | |||
248 | /* poll BUSY bit becoming cleared */ | ||
249 | timeout = 0x400; | ||
250 | while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout) | ||
251 | cpu_relax(); | ||
252 | |||
253 | if (unlikely(!timeout)) | ||
254 | goto error_unlock; | ||
255 | |||
256 | for (i = 0; i < OCOTP_WORD_COUNT; i++) | ||
257 | ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET + | ||
258 | i * 0x10); | ||
259 | |||
260 | /* close banks for power saving */ | ||
261 | __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base); | ||
262 | |||
263 | once = 1; | ||
264 | |||
265 | mutex_unlock(&ocotp_mutex); | ||
266 | |||
267 | return ocotp_words; | ||
268 | |||
269 | error_unlock: | ||
270 | mutex_unlock(&ocotp_mutex); | ||
271 | pr_err("%s: timeout in reading OCOTP\n", __func__); | ||
272 | return NULL; | ||
176 | } | 273 | } |
177 | 274 | ||
178 | enum mac_oui { | 275 | enum mac_oui { |
@@ -454,32 +551,62 @@ static void __init mxs_machine_init(void) | |||
454 | imx28_evk_post_init(); | 551 | imx28_evk_post_init(); |
455 | } | 552 | } |
456 | 553 | ||
457 | static const char *imx23_dt_compat[] __initdata = { | 554 | #define MX23_CLKCTRL_RESET_OFFSET 0x120 |
458 | "fsl,imx23", | 555 | #define MX28_CLKCTRL_RESET_OFFSET 0x1e0 |
459 | NULL, | 556 | #define MXS_CLKCTRL_RESET_CHIP (1 << 1) |
460 | }; | 557 | |
558 | /* | ||
559 | * Reset the system. It is called by machine_restart(). | ||
560 | */ | ||
561 | static void mxs_restart(char mode, const char *cmd) | ||
562 | { | ||
563 | struct device_node *np; | ||
564 | void __iomem *reset_addr; | ||
565 | |||
566 | np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl"); | ||
567 | reset_addr = of_iomap(np, 0); | ||
568 | if (!reset_addr) | ||
569 | goto soft; | ||
570 | |||
571 | if (of_device_is_compatible(np, "fsl,imx23-clkctrl")) | ||
572 | reset_addr += MX23_CLKCTRL_RESET_OFFSET; | ||
573 | else | ||
574 | reset_addr += MX28_CLKCTRL_RESET_OFFSET; | ||
461 | 575 | ||
462 | static const char *imx28_dt_compat[] __initdata = { | 576 | /* reset the chip */ |
577 | __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr); | ||
578 | |||
579 | pr_err("Failed to assert the chip reset\n"); | ||
580 | |||
581 | /* Delay to allow the serial port to show the message */ | ||
582 | mdelay(50); | ||
583 | |||
584 | soft: | ||
585 | /* We'll take a jump through zero as a poor second */ | ||
586 | soft_restart(0); | ||
587 | } | ||
588 | |||
589 | static void __init mxs_timer_init(void) | ||
590 | { | ||
591 | if (of_machine_is_compatible("fsl,imx23")) | ||
592 | mx23_clocks_init(); | ||
593 | else | ||
594 | mx28_clocks_init(); | ||
595 | clocksource_of_init(); | ||
596 | } | ||
597 | |||
598 | static const char *mxs_dt_compat[] __initdata = { | ||
463 | "fsl,imx28", | 599 | "fsl,imx28", |
600 | "fsl,imx23", | ||
464 | NULL, | 601 | NULL, |
465 | }; | 602 | }; |
466 | 603 | ||
467 | DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)") | 604 | DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)") |
468 | .map_io = mx23_map_io, | 605 | .map_io = debug_ll_io_init, |
469 | .init_irq = icoll_init_irq, | 606 | .init_irq = irqchip_init, |
470 | .handle_irq = icoll_handle_irq, | ||
471 | .init_time = imx23_timer_init, | ||
472 | .init_machine = mxs_machine_init, | ||
473 | .dt_compat = imx23_dt_compat, | ||
474 | .restart = mxs_restart, | ||
475 | MACHINE_END | ||
476 | |||
477 | DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)") | ||
478 | .map_io = mx28_map_io, | ||
479 | .init_irq = icoll_init_irq, | ||
480 | .handle_irq = icoll_handle_irq, | 607 | .handle_irq = icoll_handle_irq, |
481 | .init_time = imx28_timer_init, | 608 | .init_time = mxs_timer_init, |
482 | .init_machine = mxs_machine_init, | 609 | .init_machine = mxs_machine_init, |
483 | .dt_compat = imx28_dt_compat, | 610 | .dt_compat = mxs_dt_compat, |
484 | .restart = mxs_restart, | 611 | .restart = mxs_restart, |
485 | MACHINE_END | 612 | MACHINE_END |
diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c deleted file mode 100644 index e63b7d87acbd..000000000000 --- a/arch/arm/mach-mxs/mm.c +++ /dev/null | |||
@@ -1,52 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | * | ||
4 | * The code contained herein is licensed under the GNU General Public | ||
5 | * License. You may obtain a copy of the GNU General Public License | ||
6 | * Version 2 or later at the following locations: | ||
7 | * | ||
8 | * http://www.opensource.org/licenses/gpl-license.html | ||
9 | * http://www.gnu.org/copyleft/gpl.html | ||
10 | * | ||
11 | * Create static mapping between physical to virtual memory. | ||
12 | */ | ||
13 | |||
14 | #include <linux/mm.h> | ||
15 | #include <linux/init.h> | ||
16 | |||
17 | #include <asm/mach/map.h> | ||
18 | |||
19 | #include <mach/mx23.h> | ||
20 | #include <mach/mx28.h> | ||
21 | #include <mach/common.h> | ||
22 | |||
23 | /* | ||
24 | * Define the MX23 memory map. | ||
25 | */ | ||
26 | static struct map_desc mx23_io_desc[] __initdata = { | ||
27 | mxs_map_entry(MX23, OCRAM, MT_DEVICE), | ||
28 | mxs_map_entry(MX23, IO, MT_DEVICE), | ||
29 | }; | ||
30 | |||
31 | /* | ||
32 | * Define the MX28 memory map. | ||
33 | */ | ||
34 | static struct map_desc mx28_io_desc[] __initdata = { | ||
35 | mxs_map_entry(MX28, OCRAM, MT_DEVICE), | ||
36 | mxs_map_entry(MX28, IO, MT_DEVICE), | ||
37 | }; | ||
38 | |||
39 | /* | ||
40 | * This function initializes the memory map. It is called during the | ||
41 | * system startup to create static physical to virtual memory mappings | ||
42 | * for the IO modules. | ||
43 | */ | ||
44 | void __init mx23_map_io(void) | ||
45 | { | ||
46 | iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc)); | ||
47 | } | ||
48 | |||
49 | void __init mx28_map_io(void) | ||
50 | { | ||
51 | iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); | ||
52 | } | ||
diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c deleted file mode 100644 index 1dff46703753..000000000000 --- a/arch/arm/mach-mxs/ocotp.c +++ /dev/null | |||
@@ -1,93 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | */ | ||
14 | |||
15 | #include <linux/delay.h> | ||
16 | #include <linux/err.h> | ||
17 | #include <linux/mutex.h> | ||
18 | |||
19 | #include <asm/processor.h> /* for cpu_relax() */ | ||
20 | |||
21 | #include <mach/mxs.h> | ||
22 | #include <mach/common.h> | ||
23 | |||
24 | #define OCOTP_WORD_OFFSET 0x20 | ||
25 | #define OCOTP_WORD_COUNT 0x20 | ||
26 | |||
27 | #define BM_OCOTP_CTRL_BUSY (1 << 8) | ||
28 | #define BM_OCOTP_CTRL_ERROR (1 << 9) | ||
29 | #define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12) | ||
30 | |||
31 | static DEFINE_MUTEX(ocotp_mutex); | ||
32 | static u32 ocotp_words[OCOTP_WORD_COUNT]; | ||
33 | |||
34 | const u32 *mxs_get_ocotp(void) | ||
35 | { | ||
36 | void __iomem *ocotp_base = MXS_IO_ADDRESS(MXS_OCOTP_BASE_ADDR); | ||
37 | int timeout = 0x400; | ||
38 | size_t i; | ||
39 | static int once = 0; | ||
40 | |||
41 | if (once) | ||
42 | return ocotp_words; | ||
43 | |||
44 | mutex_lock(&ocotp_mutex); | ||
45 | |||
46 | /* | ||
47 | * clk_enable(hbus_clk) for ocotp can be skipped | ||
48 | * as it must be on when system is running. | ||
49 | */ | ||
50 | |||
51 | /* try to clear ERROR bit */ | ||
52 | __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base); | ||
53 | |||
54 | /* check both BUSY and ERROR cleared */ | ||
55 | while ((__raw_readl(ocotp_base) & | ||
56 | (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout) | ||
57 | cpu_relax(); | ||
58 | |||
59 | if (unlikely(!timeout)) | ||
60 | goto error_unlock; | ||
61 | |||
62 | /* open OCOTP banks for read */ | ||
63 | __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base); | ||
64 | |||
65 | /* approximately wait 32 hclk cycles */ | ||
66 | udelay(1); | ||
67 | |||
68 | /* poll BUSY bit becoming cleared */ | ||
69 | timeout = 0x400; | ||
70 | while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout) | ||
71 | cpu_relax(); | ||
72 | |||
73 | if (unlikely(!timeout)) | ||
74 | goto error_unlock; | ||
75 | |||
76 | for (i = 0; i < OCOTP_WORD_COUNT; i++) | ||
77 | ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET + | ||
78 | i * 0x10); | ||
79 | |||
80 | /* close banks for power saving */ | ||
81 | __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base); | ||
82 | |||
83 | once = 1; | ||
84 | |||
85 | mutex_unlock(&ocotp_mutex); | ||
86 | |||
87 | return ocotp_words; | ||
88 | |||
89 | error_unlock: | ||
90 | mutex_unlock(&ocotp_mutex); | ||
91 | pr_err("%s: timeout in reading OCOTP\n", __func__); | ||
92 | return NULL; | ||
93 | } | ||
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c deleted file mode 100644 index 30042e23bfa7..000000000000 --- a/arch/arm/mach-mxs/system.c +++ /dev/null | |||
@@ -1,139 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 1999 ARM Limited | ||
3 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
4 | * Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
5 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
6 | * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | */ | ||
18 | |||
19 | #include <linux/kernel.h> | ||
20 | #include <linux/clk.h> | ||
21 | #include <linux/io.h> | ||
22 | #include <linux/err.h> | ||
23 | #include <linux/delay.h> | ||
24 | #include <linux/init.h> | ||
25 | #include <linux/module.h> | ||
26 | |||
27 | #include <asm/proc-fns.h> | ||
28 | #include <asm/system_misc.h> | ||
29 | |||
30 | #include <mach/mxs.h> | ||
31 | #include <mach/common.h> | ||
32 | |||
33 | #define MX23_CLKCTRL_RESET_OFFSET 0x120 | ||
34 | #define MX28_CLKCTRL_RESET_OFFSET 0x1e0 | ||
35 | #define MXS_CLKCTRL_RESET_CHIP (1 << 1) | ||
36 | |||
37 | #define MXS_MODULE_CLKGATE (1 << 30) | ||
38 | #define MXS_MODULE_SFTRST (1 << 31) | ||
39 | |||
40 | static void __iomem *mxs_clkctrl_reset_addr; | ||
41 | |||
42 | /* | ||
43 | * Reset the system. It is called by machine_restart(). | ||
44 | */ | ||
45 | void mxs_restart(char mode, const char *cmd) | ||
46 | { | ||
47 | /* reset the chip */ | ||
48 | __mxs_setl(MXS_CLKCTRL_RESET_CHIP, mxs_clkctrl_reset_addr); | ||
49 | |||
50 | pr_err("Failed to assert the chip reset\n"); | ||
51 | |||
52 | /* Delay to allow the serial port to show the message */ | ||
53 | mdelay(50); | ||
54 | |||
55 | /* We'll take a jump through zero as a poor second */ | ||
56 | soft_restart(0); | ||
57 | } | ||
58 | |||
59 | static int __init mxs_arch_reset_init(void) | ||
60 | { | ||
61 | struct clk *clk; | ||
62 | |||
63 | mxs_clkctrl_reset_addr = MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR) + | ||
64 | (cpu_is_mx23() ? MX23_CLKCTRL_RESET_OFFSET : | ||
65 | MX28_CLKCTRL_RESET_OFFSET); | ||
66 | |||
67 | clk = clk_get_sys("rtc", NULL); | ||
68 | if (!IS_ERR(clk)) | ||
69 | clk_prepare_enable(clk); | ||
70 | |||
71 | return 0; | ||
72 | } | ||
73 | core_initcall(mxs_arch_reset_init); | ||
74 | |||
75 | /* | ||
76 | * Clear the bit and poll it cleared. This is usually called with | ||
77 | * a reset address and mask being either SFTRST(bit 31) or CLKGATE | ||
78 | * (bit 30). | ||
79 | */ | ||
80 | static int clear_poll_bit(void __iomem *addr, u32 mask) | ||
81 | { | ||
82 | int timeout = 0x400; | ||
83 | |||
84 | /* clear the bit */ | ||
85 | __mxs_clrl(mask, addr); | ||
86 | |||
87 | /* | ||
88 | * SFTRST needs 3 GPMI clocks to settle, the reference manual | ||
89 | * recommends to wait 1us. | ||
90 | */ | ||
91 | udelay(1); | ||
92 | |||
93 | /* poll the bit becoming clear */ | ||
94 | while ((__raw_readl(addr) & mask) && --timeout) | ||
95 | /* nothing */; | ||
96 | |||
97 | return !timeout; | ||
98 | } | ||
99 | |||
100 | int mxs_reset_block(void __iomem *reset_addr) | ||
101 | { | ||
102 | int ret; | ||
103 | int timeout = 0x400; | ||
104 | |||
105 | /* clear and poll SFTRST */ | ||
106 | ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST); | ||
107 | if (unlikely(ret)) | ||
108 | goto error; | ||
109 | |||
110 | /* clear CLKGATE */ | ||
111 | __mxs_clrl(MXS_MODULE_CLKGATE, reset_addr); | ||
112 | |||
113 | /* set SFTRST to reset the block */ | ||
114 | __mxs_setl(MXS_MODULE_SFTRST, reset_addr); | ||
115 | udelay(1); | ||
116 | |||
117 | /* poll CLKGATE becoming set */ | ||
118 | while ((!(__raw_readl(reset_addr) & MXS_MODULE_CLKGATE)) && --timeout) | ||
119 | /* nothing */; | ||
120 | if (unlikely(!timeout)) | ||
121 | goto error; | ||
122 | |||
123 | /* clear and poll SFTRST */ | ||
124 | ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST); | ||
125 | if (unlikely(ret)) | ||
126 | goto error; | ||
127 | |||
128 | /* clear and poll CLKGATE */ | ||
129 | ret = clear_poll_bit(reset_addr, MXS_MODULE_CLKGATE); | ||
130 | if (unlikely(ret)) | ||
131 | goto error; | ||
132 | |||
133 | return 0; | ||
134 | |||
135 | error: | ||
136 | pr_err("%s(%p): module reset timeout\n", __func__, reset_addr); | ||
137 | return -ETIMEDOUT; | ||
138 | } | ||
139 | EXPORT_SYMBOL(mxs_reset_block); | ||
diff --git a/arch/arm/mach-omap1/dma.h b/arch/arm/mach-omap1/dma.h index da6345dab03f..d05909c96715 100644 --- a/arch/arm/mach-omap1/dma.h +++ b/arch/arm/mach-omap1/dma.h | |||
@@ -21,21 +21,10 @@ | |||
21 | 21 | ||
22 | /* DMA channels for omap1 */ | 22 | /* DMA channels for omap1 */ |
23 | #define OMAP_DMA_NO_DEVICE 0 | 23 | #define OMAP_DMA_NO_DEVICE 0 |
24 | #define OMAP_DMA_MCSI1_TX 1 | ||
25 | #define OMAP_DMA_MCSI1_RX 2 | ||
26 | #define OMAP_DMA_I2C_RX 3 | ||
27 | #define OMAP_DMA_I2C_TX 4 | ||
28 | #define OMAP_DMA_EXT_NDMA_REQ 5 | ||
29 | #define OMAP_DMA_EXT_NDMA_REQ2 6 | ||
30 | #define OMAP_DMA_UWIRE_TX 7 | ||
31 | #define OMAP_DMA_MCBSP1_TX 8 | 24 | #define OMAP_DMA_MCBSP1_TX 8 |
32 | #define OMAP_DMA_MCBSP1_RX 9 | 25 | #define OMAP_DMA_MCBSP1_RX 9 |
33 | #define OMAP_DMA_MCBSP3_TX 10 | 26 | #define OMAP_DMA_MCBSP3_TX 10 |
34 | #define OMAP_DMA_MCBSP3_RX 11 | 27 | #define OMAP_DMA_MCBSP3_RX 11 |
35 | #define OMAP_DMA_UART1_TX 12 | ||
36 | #define OMAP_DMA_UART1_RX 13 | ||
37 | #define OMAP_DMA_UART2_TX 14 | ||
38 | #define OMAP_DMA_UART2_RX 15 | ||
39 | #define OMAP_DMA_MCBSP2_TX 16 | 28 | #define OMAP_DMA_MCBSP2_TX 16 |
40 | #define OMAP_DMA_MCBSP2_RX 17 | 29 | #define OMAP_DMA_MCBSP2_RX 17 |
41 | #define OMAP_DMA_UART3_TX 18 | 30 | #define OMAP_DMA_UART3_TX 18 |
@@ -43,41 +32,11 @@ | |||
43 | #define OMAP_DMA_CAMERA_IF_RX 20 | 32 | #define OMAP_DMA_CAMERA_IF_RX 20 |
44 | #define OMAP_DMA_MMC_TX 21 | 33 | #define OMAP_DMA_MMC_TX 21 |
45 | #define OMAP_DMA_MMC_RX 22 | 34 | #define OMAP_DMA_MMC_RX 22 |
46 | #define OMAP_DMA_NAND 23 | ||
47 | #define OMAP_DMA_IRQ_LCD_LINE 24 | ||
48 | #define OMAP_DMA_MEMORY_STICK 25 | ||
49 | #define OMAP_DMA_USB_W2FC_RX0 26 | 35 | #define OMAP_DMA_USB_W2FC_RX0 26 |
50 | #define OMAP_DMA_USB_W2FC_RX1 27 | ||
51 | #define OMAP_DMA_USB_W2FC_RX2 28 | ||
52 | #define OMAP_DMA_USB_W2FC_TX0 29 | 36 | #define OMAP_DMA_USB_W2FC_TX0 29 |
53 | #define OMAP_DMA_USB_W2FC_TX1 30 | ||
54 | #define OMAP_DMA_USB_W2FC_TX2 31 | ||
55 | 37 | ||
56 | /* These are only for 1610 */ | 38 | /* These are only for 1610 */ |
57 | #define OMAP_DMA_CRYPTO_DES_IN 32 | ||
58 | #define OMAP_DMA_SPI_TX 33 | ||
59 | #define OMAP_DMA_SPI_RX 34 | ||
60 | #define OMAP_DMA_CRYPTO_HASH 35 | ||
61 | #define OMAP_DMA_CCP_ATTN 36 | ||
62 | #define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 | ||
63 | #define OMAP_DMA_CMT_APE_TX_CHAN_0 38 | ||
64 | #define OMAP_DMA_CMT_APE_RV_CHAN_0 39 | ||
65 | #define OMAP_DMA_CMT_APE_TX_CHAN_1 40 | ||
66 | #define OMAP_DMA_CMT_APE_RV_CHAN_1 41 | ||
67 | #define OMAP_DMA_CMT_APE_TX_CHAN_2 42 | ||
68 | #define OMAP_DMA_CMT_APE_RV_CHAN_2 43 | ||
69 | #define OMAP_DMA_CMT_APE_TX_CHAN_3 44 | ||
70 | #define OMAP_DMA_CMT_APE_RV_CHAN_3 45 | ||
71 | #define OMAP_DMA_CMT_APE_TX_CHAN_4 46 | ||
72 | #define OMAP_DMA_CMT_APE_RV_CHAN_4 47 | ||
73 | #define OMAP_DMA_CMT_APE_TX_CHAN_5 48 | ||
74 | #define OMAP_DMA_CMT_APE_RV_CHAN_5 49 | ||
75 | #define OMAP_DMA_CMT_APE_TX_CHAN_6 50 | ||
76 | #define OMAP_DMA_CMT_APE_RV_CHAN_6 51 | ||
77 | #define OMAP_DMA_CMT_APE_TX_CHAN_7 52 | ||
78 | #define OMAP_DMA_CMT_APE_RV_CHAN_7 53 | ||
79 | #define OMAP_DMA_MMC2_TX 54 | 39 | #define OMAP_DMA_MMC2_TX 54 |
80 | #define OMAP_DMA_MMC2_RX 55 | 40 | #define OMAP_DMA_MMC2_RX 55 |
81 | #define OMAP_DMA_CRYPTO_DES_OUT 56 | ||
82 | 41 | ||
83 | #endif /* __OMAP1_DMA_CHANNEL_H */ | 42 | #endif /* __OMAP1_DMA_CHANNEL_H */ |
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c index 0f0a97c1fcc0..3662f4d4c8ea 100644 --- a/arch/arm/mach-omap2/cclock2420_data.c +++ b/arch/arm/mach-omap2/cclock2420_data.c | |||
@@ -1739,153 +1739,153 @@ DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); | |||
1739 | 1739 | ||
1740 | static struct omap_clk omap2420_clks[] = { | 1740 | static struct omap_clk omap2420_clks[] = { |
1741 | /* external root sources */ | 1741 | /* external root sources */ |
1742 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X), | 1742 | CLK(NULL, "func_32k_ck", &func_32k_ck), |
1743 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X), | 1743 | CLK(NULL, "secure_32k_ck", &secure_32k_ck), |
1744 | CLK(NULL, "osc_ck", &osc_ck, CK_242X), | 1744 | CLK(NULL, "osc_ck", &osc_ck), |
1745 | CLK(NULL, "sys_ck", &sys_ck, CK_242X), | 1745 | CLK(NULL, "sys_ck", &sys_ck), |
1746 | CLK(NULL, "alt_ck", &alt_ck, CK_242X), | 1746 | CLK(NULL, "alt_ck", &alt_ck), |
1747 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), | 1747 | CLK(NULL, "mcbsp_clks", &mcbsp_clks), |
1748 | /* internal analog sources */ | 1748 | /* internal analog sources */ |
1749 | CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), | 1749 | CLK(NULL, "dpll_ck", &dpll_ck), |
1750 | CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), | 1750 | CLK(NULL, "apll96_ck", &apll96_ck), |
1751 | CLK(NULL, "apll54_ck", &apll54_ck, CK_242X), | 1751 | CLK(NULL, "apll54_ck", &apll54_ck), |
1752 | /* internal prcm root sources */ | 1752 | /* internal prcm root sources */ |
1753 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), | 1753 | CLK(NULL, "func_54m_ck", &func_54m_ck), |
1754 | CLK(NULL, "core_ck", &core_ck, CK_242X), | 1754 | CLK(NULL, "core_ck", &core_ck), |
1755 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), | 1755 | CLK(NULL, "func_96m_ck", &func_96m_ck), |
1756 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), | 1756 | CLK(NULL, "func_48m_ck", &func_48m_ck), |
1757 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), | 1757 | CLK(NULL, "func_12m_ck", &func_12m_ck), |
1758 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), | 1758 | CLK(NULL, "sys_clkout_src", &sys_clkout_src), |
1759 | CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), | 1759 | CLK(NULL, "sys_clkout", &sys_clkout), |
1760 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), | 1760 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src), |
1761 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), | 1761 | CLK(NULL, "sys_clkout2", &sys_clkout2), |
1762 | CLK(NULL, "emul_ck", &emul_ck, CK_242X), | 1762 | CLK(NULL, "emul_ck", &emul_ck), |
1763 | /* mpu domain clocks */ | 1763 | /* mpu domain clocks */ |
1764 | CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), | 1764 | CLK(NULL, "mpu_ck", &mpu_ck), |
1765 | /* dsp domain clocks */ | 1765 | /* dsp domain clocks */ |
1766 | CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), | 1766 | CLK(NULL, "dsp_fck", &dsp_fck), |
1767 | CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), | 1767 | CLK(NULL, "dsp_ick", &dsp_ick), |
1768 | CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), | 1768 | CLK(NULL, "iva1_ifck", &iva1_ifck), |
1769 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), | 1769 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck), |
1770 | /* GFX domain clocks */ | 1770 | /* GFX domain clocks */ |
1771 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X), | 1771 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck), |
1772 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), | 1772 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck), |
1773 | CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), | 1773 | CLK(NULL, "gfx_ick", &gfx_ick), |
1774 | /* DSS domain clocks */ | 1774 | /* DSS domain clocks */ |
1775 | CLK("omapdss_dss", "ick", &dss_ick, CK_242X), | 1775 | CLK("omapdss_dss", "ick", &dss_ick), |
1776 | CLK(NULL, "dss_ick", &dss_ick, CK_242X), | 1776 | CLK(NULL, "dss_ick", &dss_ick), |
1777 | CLK(NULL, "dss1_fck", &dss1_fck, CK_242X), | 1777 | CLK(NULL, "dss1_fck", &dss1_fck), |
1778 | CLK(NULL, "dss2_fck", &dss2_fck, CK_242X), | 1778 | CLK(NULL, "dss2_fck", &dss2_fck), |
1779 | CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X), | 1779 | CLK(NULL, "dss_54m_fck", &dss_54m_fck), |
1780 | /* L3 domain clocks */ | 1780 | /* L3 domain clocks */ |
1781 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), | 1781 | CLK(NULL, "core_l3_ck", &core_l3_ck), |
1782 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), | 1782 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck), |
1783 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X), | 1783 | CLK(NULL, "usb_l4_ick", &usb_l4_ick), |
1784 | /* L4 domain clocks */ | 1784 | /* L4 domain clocks */ |
1785 | CLK(NULL, "l4_ck", &l4_ck, CK_242X), | 1785 | CLK(NULL, "l4_ck", &l4_ck), |
1786 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), | 1786 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick), |
1787 | /* virtual meta-group clock */ | 1787 | /* virtual meta-group clock */ |
1788 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), | 1788 | CLK(NULL, "virt_prcm_set", &virt_prcm_set), |
1789 | /* general l4 interface ck, multi-parent functional clk */ | 1789 | /* general l4 interface ck, multi-parent functional clk */ |
1790 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X), | 1790 | CLK(NULL, "gpt1_ick", &gpt1_ick), |
1791 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X), | 1791 | CLK(NULL, "gpt1_fck", &gpt1_fck), |
1792 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X), | 1792 | CLK(NULL, "gpt2_ick", &gpt2_ick), |
1793 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X), | 1793 | CLK(NULL, "gpt2_fck", &gpt2_fck), |
1794 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X), | 1794 | CLK(NULL, "gpt3_ick", &gpt3_ick), |
1795 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X), | 1795 | CLK(NULL, "gpt3_fck", &gpt3_fck), |
1796 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X), | 1796 | CLK(NULL, "gpt4_ick", &gpt4_ick), |
1797 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X), | 1797 | CLK(NULL, "gpt4_fck", &gpt4_fck), |
1798 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X), | 1798 | CLK(NULL, "gpt5_ick", &gpt5_ick), |
1799 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X), | 1799 | CLK(NULL, "gpt5_fck", &gpt5_fck), |
1800 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X), | 1800 | CLK(NULL, "gpt6_ick", &gpt6_ick), |
1801 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X), | 1801 | CLK(NULL, "gpt6_fck", &gpt6_fck), |
1802 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X), | 1802 | CLK(NULL, "gpt7_ick", &gpt7_ick), |
1803 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X), | 1803 | CLK(NULL, "gpt7_fck", &gpt7_fck), |
1804 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X), | 1804 | CLK(NULL, "gpt8_ick", &gpt8_ick), |
1805 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X), | 1805 | CLK(NULL, "gpt8_fck", &gpt8_fck), |
1806 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X), | 1806 | CLK(NULL, "gpt9_ick", &gpt9_ick), |
1807 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X), | 1807 | CLK(NULL, "gpt9_fck", &gpt9_fck), |
1808 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X), | 1808 | CLK(NULL, "gpt10_ick", &gpt10_ick), |
1809 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X), | 1809 | CLK(NULL, "gpt10_fck", &gpt10_fck), |
1810 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X), | 1810 | CLK(NULL, "gpt11_ick", &gpt11_ick), |
1811 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X), | 1811 | CLK(NULL, "gpt11_fck", &gpt11_fck), |
1812 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), | 1812 | CLK(NULL, "gpt12_ick", &gpt12_ick), |
1813 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), | 1813 | CLK(NULL, "gpt12_fck", &gpt12_fck), |
1814 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), | 1814 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick), |
1815 | CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X), | 1815 | CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), |
1816 | CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X), | 1816 | CLK(NULL, "mcbsp1_fck", &mcbsp1_fck), |
1817 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), | 1817 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick), |
1818 | CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X), | 1818 | CLK(NULL, "mcbsp2_ick", &mcbsp2_ick), |
1819 | CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X), | 1819 | CLK(NULL, "mcbsp2_fck", &mcbsp2_fck), |
1820 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), | 1820 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick), |
1821 | CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X), | 1821 | CLK(NULL, "mcspi1_ick", &mcspi1_ick), |
1822 | CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X), | 1822 | CLK(NULL, "mcspi1_fck", &mcspi1_fck), |
1823 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), | 1823 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick), |
1824 | CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X), | 1824 | CLK(NULL, "mcspi2_ick", &mcspi2_ick), |
1825 | CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X), | 1825 | CLK(NULL, "mcspi2_fck", &mcspi2_fck), |
1826 | CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), | 1826 | CLK(NULL, "uart1_ick", &uart1_ick), |
1827 | CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), | 1827 | CLK(NULL, "uart1_fck", &uart1_fck), |
1828 | CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), | 1828 | CLK(NULL, "uart2_ick", &uart2_ick), |
1829 | CLK(NULL, "uart2_fck", &uart2_fck, CK_242X), | 1829 | CLK(NULL, "uart2_fck", &uart2_fck), |
1830 | CLK(NULL, "uart3_ick", &uart3_ick, CK_242X), | 1830 | CLK(NULL, "uart3_ick", &uart3_ick), |
1831 | CLK(NULL, "uart3_fck", &uart3_fck, CK_242X), | 1831 | CLK(NULL, "uart3_fck", &uart3_fck), |
1832 | CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), | 1832 | CLK(NULL, "gpios_ick", &gpios_ick), |
1833 | CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), | 1833 | CLK(NULL, "gpios_fck", &gpios_fck), |
1834 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), | 1834 | CLK("omap_wdt", "ick", &mpu_wdt_ick), |
1835 | CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X), | 1835 | CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick), |
1836 | CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X), | 1836 | CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck), |
1837 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), | 1837 | CLK(NULL, "sync_32k_ick", &sync_32k_ick), |
1838 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), | 1838 | CLK(NULL, "wdt1_ick", &wdt1_ick), |
1839 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), | 1839 | CLK(NULL, "omapctrl_ick", &omapctrl_ick), |
1840 | CLK("omap24xxcam", "fck", &cam_fck, CK_242X), | 1840 | CLK("omap24xxcam", "fck", &cam_fck), |
1841 | CLK(NULL, "cam_fck", &cam_fck, CK_242X), | 1841 | CLK(NULL, "cam_fck", &cam_fck), |
1842 | CLK("omap24xxcam", "ick", &cam_ick, CK_242X), | 1842 | CLK("omap24xxcam", "ick", &cam_ick), |
1843 | CLK(NULL, "cam_ick", &cam_ick, CK_242X), | 1843 | CLK(NULL, "cam_ick", &cam_ick), |
1844 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), | 1844 | CLK(NULL, "mailboxes_ick", &mailboxes_ick), |
1845 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), | 1845 | CLK(NULL, "wdt4_ick", &wdt4_ick), |
1846 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), | 1846 | CLK(NULL, "wdt4_fck", &wdt4_fck), |
1847 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), | 1847 | CLK(NULL, "wdt3_ick", &wdt3_ick), |
1848 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), | 1848 | CLK(NULL, "wdt3_fck", &wdt3_fck), |
1849 | CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), | 1849 | CLK(NULL, "mspro_ick", &mspro_ick), |
1850 | CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), | 1850 | CLK(NULL, "mspro_fck", &mspro_fck), |
1851 | CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), | 1851 | CLK("mmci-omap.0", "ick", &mmc_ick), |
1852 | CLK(NULL, "mmc_ick", &mmc_ick, CK_242X), | 1852 | CLK(NULL, "mmc_ick", &mmc_ick), |
1853 | CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), | 1853 | CLK("mmci-omap.0", "fck", &mmc_fck), |
1854 | CLK(NULL, "mmc_fck", &mmc_fck, CK_242X), | 1854 | CLK(NULL, "mmc_fck", &mmc_fck), |
1855 | CLK(NULL, "fac_ick", &fac_ick, CK_242X), | 1855 | CLK(NULL, "fac_ick", &fac_ick), |
1856 | CLK(NULL, "fac_fck", &fac_fck, CK_242X), | 1856 | CLK(NULL, "fac_fck", &fac_fck), |
1857 | CLK(NULL, "eac_ick", &eac_ick, CK_242X), | 1857 | CLK(NULL, "eac_ick", &eac_ick), |
1858 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), | 1858 | CLK(NULL, "eac_fck", &eac_fck), |
1859 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), | 1859 | CLK("omap_hdq.0", "ick", &hdq_ick), |
1860 | CLK(NULL, "hdq_ick", &hdq_ick, CK_242X), | 1860 | CLK(NULL, "hdq_ick", &hdq_ick), |
1861 | CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X), | 1861 | CLK("omap_hdq.0", "fck", &hdq_fck), |
1862 | CLK(NULL, "hdq_fck", &hdq_fck, CK_242X), | 1862 | CLK(NULL, "hdq_fck", &hdq_fck), |
1863 | CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), | 1863 | CLK("omap_i2c.1", "ick", &i2c1_ick), |
1864 | CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X), | 1864 | CLK(NULL, "i2c1_ick", &i2c1_ick), |
1865 | CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X), | 1865 | CLK(NULL, "i2c1_fck", &i2c1_fck), |
1866 | CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), | 1866 | CLK("omap_i2c.2", "ick", &i2c2_ick), |
1867 | CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X), | 1867 | CLK(NULL, "i2c2_ick", &i2c2_ick), |
1868 | CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X), | 1868 | CLK(NULL, "i2c2_fck", &i2c2_fck), |
1869 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), | 1869 | CLK(NULL, "gpmc_fck", &gpmc_fck), |
1870 | CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), | 1870 | CLK(NULL, "sdma_fck", &sdma_fck), |
1871 | CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), | 1871 | CLK(NULL, "sdma_ick", &sdma_ick), |
1872 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X), | 1872 | CLK(NULL, "sdrc_ick", &sdrc_ick), |
1873 | CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), | 1873 | CLK(NULL, "vlynq_ick", &vlynq_ick), |
1874 | CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), | 1874 | CLK(NULL, "vlynq_fck", &vlynq_fck), |
1875 | CLK(NULL, "des_ick", &des_ick, CK_242X), | 1875 | CLK(NULL, "des_ick", &des_ick), |
1876 | CLK("omap-sham", "ick", &sha_ick, CK_242X), | 1876 | CLK("omap-sham", "ick", &sha_ick), |
1877 | CLK(NULL, "sha_ick", &sha_ick, CK_242X), | 1877 | CLK(NULL, "sha_ick", &sha_ick), |
1878 | CLK("omap_rng", "ick", &rng_ick, CK_242X), | 1878 | CLK("omap_rng", "ick", &rng_ick), |
1879 | CLK(NULL, "rng_ick", &rng_ick, CK_242X), | 1879 | CLK(NULL, "rng_ick", &rng_ick), |
1880 | CLK("omap-aes", "ick", &aes_ick, CK_242X), | 1880 | CLK("omap-aes", "ick", &aes_ick), |
1881 | CLK(NULL, "aes_ick", &aes_ick, CK_242X), | 1881 | CLK(NULL, "aes_ick", &aes_ick), |
1882 | CLK(NULL, "pka_ick", &pka_ick, CK_242X), | 1882 | CLK(NULL, "pka_ick", &pka_ick), |
1883 | CLK(NULL, "usb_fck", &usb_fck, CK_242X), | 1883 | CLK(NULL, "usb_fck", &usb_fck), |
1884 | CLK("musb-hdrc", "fck", &osc_ck, CK_242X), | 1884 | CLK("musb-hdrc", "fck", &osc_ck), |
1885 | CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X), | 1885 | CLK(NULL, "timer_32k_ck", &func_32k_ck), |
1886 | CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X), | 1886 | CLK(NULL, "timer_sys_ck", &sys_ck), |
1887 | CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X), | 1887 | CLK(NULL, "timer_ext_ck", &alt_ck), |
1888 | CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X), | 1888 | CLK(NULL, "cpufreq_ck", &virt_prcm_set), |
1889 | }; | 1889 | }; |
1890 | 1890 | ||
1891 | 1891 | ||
@@ -1904,8 +1904,6 @@ static const char *enable_init_clks[] = { | |||
1904 | 1904 | ||
1905 | int __init omap2420_clk_init(void) | 1905 | int __init omap2420_clk_init(void) |
1906 | { | 1906 | { |
1907 | struct omap_clk *c; | ||
1908 | |||
1909 | prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; | 1907 | prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; |
1910 | cpu_mask = RATE_IN_242X; | 1908 | cpu_mask = RATE_IN_242X; |
1911 | rate_table = omap2420_rate_table; | 1909 | rate_table = omap2420_rate_table; |
@@ -1914,12 +1912,7 @@ int __init omap2420_clk_init(void) | |||
1914 | 1912 | ||
1915 | omap2xxx_clkt_vps_check_bootloader_rates(); | 1913 | omap2xxx_clkt_vps_check_bootloader_rates(); |
1916 | 1914 | ||
1917 | for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); | 1915 | omap_clocks_register(omap2420_clks, ARRAY_SIZE(omap2420_clks)); |
1918 | c++) { | ||
1919 | clkdev_add(&c->lk); | ||
1920 | if (!__clk_init(NULL, c->lk.clk)) | ||
1921 | omap2_init_clk_hw_omap_clocks(c->lk.clk); | ||
1922 | } | ||
1923 | 1916 | ||
1924 | omap2xxx_clkt_vps_late_init(); | 1917 | omap2xxx_clkt_vps_late_init(); |
1925 | 1918 | ||
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c index aed8f74ca076..bda353b2f7d9 100644 --- a/arch/arm/mach-omap2/cclock2430_data.c +++ b/arch/arm/mach-omap2/cclock2430_data.c | |||
@@ -1840,168 +1840,168 @@ DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); | |||
1840 | 1840 | ||
1841 | static struct omap_clk omap2430_clks[] = { | 1841 | static struct omap_clk omap2430_clks[] = { |
1842 | /* external root sources */ | 1842 | /* external root sources */ |
1843 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X), | 1843 | CLK(NULL, "func_32k_ck", &func_32k_ck), |
1844 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X), | 1844 | CLK(NULL, "secure_32k_ck", &secure_32k_ck), |
1845 | CLK(NULL, "osc_ck", &osc_ck, CK_243X), | 1845 | CLK(NULL, "osc_ck", &osc_ck), |
1846 | CLK("twl", "fck", &osc_ck, CK_243X), | 1846 | CLK("twl", "fck", &osc_ck), |
1847 | CLK(NULL, "sys_ck", &sys_ck, CK_243X), | 1847 | CLK(NULL, "sys_ck", &sys_ck), |
1848 | CLK(NULL, "alt_ck", &alt_ck, CK_243X), | 1848 | CLK(NULL, "alt_ck", &alt_ck), |
1849 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), | 1849 | CLK(NULL, "mcbsp_clks", &mcbsp_clks), |
1850 | /* internal analog sources */ | 1850 | /* internal analog sources */ |
1851 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), | 1851 | CLK(NULL, "dpll_ck", &dpll_ck), |
1852 | CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), | 1852 | CLK(NULL, "apll96_ck", &apll96_ck), |
1853 | CLK(NULL, "apll54_ck", &apll54_ck, CK_243X), | 1853 | CLK(NULL, "apll54_ck", &apll54_ck), |
1854 | /* internal prcm root sources */ | 1854 | /* internal prcm root sources */ |
1855 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), | 1855 | CLK(NULL, "func_54m_ck", &func_54m_ck), |
1856 | CLK(NULL, "core_ck", &core_ck, CK_243X), | 1856 | CLK(NULL, "core_ck", &core_ck), |
1857 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), | 1857 | CLK(NULL, "func_96m_ck", &func_96m_ck), |
1858 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), | 1858 | CLK(NULL, "func_48m_ck", &func_48m_ck), |
1859 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), | 1859 | CLK(NULL, "func_12m_ck", &func_12m_ck), |
1860 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X), | 1860 | CLK(NULL, "sys_clkout_src", &sys_clkout_src), |
1861 | CLK(NULL, "sys_clkout", &sys_clkout, CK_243X), | 1861 | CLK(NULL, "sys_clkout", &sys_clkout), |
1862 | CLK(NULL, "emul_ck", &emul_ck, CK_243X), | 1862 | CLK(NULL, "emul_ck", &emul_ck), |
1863 | /* mpu domain clocks */ | 1863 | /* mpu domain clocks */ |
1864 | CLK(NULL, "mpu_ck", &mpu_ck, CK_243X), | 1864 | CLK(NULL, "mpu_ck", &mpu_ck), |
1865 | /* dsp domain clocks */ | 1865 | /* dsp domain clocks */ |
1866 | CLK(NULL, "dsp_fck", &dsp_fck, CK_243X), | 1866 | CLK(NULL, "dsp_fck", &dsp_fck), |
1867 | CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), | 1867 | CLK(NULL, "iva2_1_ick", &iva2_1_ick), |
1868 | /* GFX domain clocks */ | 1868 | /* GFX domain clocks */ |
1869 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X), | 1869 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck), |
1870 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X), | 1870 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck), |
1871 | CLK(NULL, "gfx_ick", &gfx_ick, CK_243X), | 1871 | CLK(NULL, "gfx_ick", &gfx_ick), |
1872 | /* Modem domain clocks */ | 1872 | /* Modem domain clocks */ |
1873 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), | 1873 | CLK(NULL, "mdm_ick", &mdm_ick), |
1874 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), | 1874 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck), |
1875 | /* DSS domain clocks */ | 1875 | /* DSS domain clocks */ |
1876 | CLK("omapdss_dss", "ick", &dss_ick, CK_243X), | 1876 | CLK("omapdss_dss", "ick", &dss_ick), |
1877 | CLK(NULL, "dss_ick", &dss_ick, CK_243X), | 1877 | CLK(NULL, "dss_ick", &dss_ick), |
1878 | CLK(NULL, "dss1_fck", &dss1_fck, CK_243X), | 1878 | CLK(NULL, "dss1_fck", &dss1_fck), |
1879 | CLK(NULL, "dss2_fck", &dss2_fck, CK_243X), | 1879 | CLK(NULL, "dss2_fck", &dss2_fck), |
1880 | CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X), | 1880 | CLK(NULL, "dss_54m_fck", &dss_54m_fck), |
1881 | /* L3 domain clocks */ | 1881 | /* L3 domain clocks */ |
1882 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), | 1882 | CLK(NULL, "core_l3_ck", &core_l3_ck), |
1883 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), | 1883 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck), |
1884 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X), | 1884 | CLK(NULL, "usb_l4_ick", &usb_l4_ick), |
1885 | /* L4 domain clocks */ | 1885 | /* L4 domain clocks */ |
1886 | CLK(NULL, "l4_ck", &l4_ck, CK_243X), | 1886 | CLK(NULL, "l4_ck", &l4_ck), |
1887 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), | 1887 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick), |
1888 | /* virtual meta-group clock */ | 1888 | /* virtual meta-group clock */ |
1889 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), | 1889 | CLK(NULL, "virt_prcm_set", &virt_prcm_set), |
1890 | /* general l4 interface ck, multi-parent functional clk */ | 1890 | /* general l4 interface ck, multi-parent functional clk */ |
1891 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X), | 1891 | CLK(NULL, "gpt1_ick", &gpt1_ick), |
1892 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X), | 1892 | CLK(NULL, "gpt1_fck", &gpt1_fck), |
1893 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X), | 1893 | CLK(NULL, "gpt2_ick", &gpt2_ick), |
1894 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X), | 1894 | CLK(NULL, "gpt2_fck", &gpt2_fck), |
1895 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X), | 1895 | CLK(NULL, "gpt3_ick", &gpt3_ick), |
1896 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X), | 1896 | CLK(NULL, "gpt3_fck", &gpt3_fck), |
1897 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X), | 1897 | CLK(NULL, "gpt4_ick", &gpt4_ick), |
1898 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X), | 1898 | CLK(NULL, "gpt4_fck", &gpt4_fck), |
1899 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X), | 1899 | CLK(NULL, "gpt5_ick", &gpt5_ick), |
1900 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X), | 1900 | CLK(NULL, "gpt5_fck", &gpt5_fck), |
1901 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X), | 1901 | CLK(NULL, "gpt6_ick", &gpt6_ick), |
1902 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X), | 1902 | CLK(NULL, "gpt6_fck", &gpt6_fck), |
1903 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X), | 1903 | CLK(NULL, "gpt7_ick", &gpt7_ick), |
1904 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X), | 1904 | CLK(NULL, "gpt7_fck", &gpt7_fck), |
1905 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X), | 1905 | CLK(NULL, "gpt8_ick", &gpt8_ick), |
1906 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X), | 1906 | CLK(NULL, "gpt8_fck", &gpt8_fck), |
1907 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X), | 1907 | CLK(NULL, "gpt9_ick", &gpt9_ick), |
1908 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X), | 1908 | CLK(NULL, "gpt9_fck", &gpt9_fck), |
1909 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X), | 1909 | CLK(NULL, "gpt10_ick", &gpt10_ick), |
1910 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X), | 1910 | CLK(NULL, "gpt10_fck", &gpt10_fck), |
1911 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X), | 1911 | CLK(NULL, "gpt11_ick", &gpt11_ick), |
1912 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X), | 1912 | CLK(NULL, "gpt11_fck", &gpt11_fck), |
1913 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), | 1913 | CLK(NULL, "gpt12_ick", &gpt12_ick), |
1914 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), | 1914 | CLK(NULL, "gpt12_fck", &gpt12_fck), |
1915 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), | 1915 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick), |
1916 | CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X), | 1916 | CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), |
1917 | CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X), | 1917 | CLK(NULL, "mcbsp1_fck", &mcbsp1_fck), |
1918 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), | 1918 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick), |
1919 | CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X), | 1919 | CLK(NULL, "mcbsp2_ick", &mcbsp2_ick), |
1920 | CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X), | 1920 | CLK(NULL, "mcbsp2_fck", &mcbsp2_fck), |
1921 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), | 1921 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick), |
1922 | CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X), | 1922 | CLK(NULL, "mcbsp3_ick", &mcbsp3_ick), |
1923 | CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X), | 1923 | CLK(NULL, "mcbsp3_fck", &mcbsp3_fck), |
1924 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), | 1924 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick), |
1925 | CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X), | 1925 | CLK(NULL, "mcbsp4_ick", &mcbsp4_ick), |
1926 | CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X), | 1926 | CLK(NULL, "mcbsp4_fck", &mcbsp4_fck), |
1927 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), | 1927 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick), |
1928 | CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X), | 1928 | CLK(NULL, "mcbsp5_ick", &mcbsp5_ick), |
1929 | CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X), | 1929 | CLK(NULL, "mcbsp5_fck", &mcbsp5_fck), |
1930 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), | 1930 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick), |
1931 | CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X), | 1931 | CLK(NULL, "mcspi1_ick", &mcspi1_ick), |
1932 | CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X), | 1932 | CLK(NULL, "mcspi1_fck", &mcspi1_fck), |
1933 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), | 1933 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick), |
1934 | CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X), | 1934 | CLK(NULL, "mcspi2_ick", &mcspi2_ick), |
1935 | CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X), | 1935 | CLK(NULL, "mcspi2_fck", &mcspi2_fck), |
1936 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), | 1936 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick), |
1937 | CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X), | 1937 | CLK(NULL, "mcspi3_ick", &mcspi3_ick), |
1938 | CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X), | 1938 | CLK(NULL, "mcspi3_fck", &mcspi3_fck), |
1939 | CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), | 1939 | CLK(NULL, "uart1_ick", &uart1_ick), |
1940 | CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), | 1940 | CLK(NULL, "uart1_fck", &uart1_fck), |
1941 | CLK(NULL, "uart2_ick", &uart2_ick, CK_243X), | 1941 | CLK(NULL, "uart2_ick", &uart2_ick), |
1942 | CLK(NULL, "uart2_fck", &uart2_fck, CK_243X), | 1942 | CLK(NULL, "uart2_fck", &uart2_fck), |
1943 | CLK(NULL, "uart3_ick", &uart3_ick, CK_243X), | 1943 | CLK(NULL, "uart3_ick", &uart3_ick), |
1944 | CLK(NULL, "uart3_fck", &uart3_fck, CK_243X), | 1944 | CLK(NULL, "uart3_fck", &uart3_fck), |
1945 | CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), | 1945 | CLK(NULL, "gpios_ick", &gpios_ick), |
1946 | CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), | 1946 | CLK(NULL, "gpios_fck", &gpios_fck), |
1947 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), | 1947 | CLK("omap_wdt", "ick", &mpu_wdt_ick), |
1948 | CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X), | 1948 | CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick), |
1949 | CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X), | 1949 | CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck), |
1950 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), | 1950 | CLK(NULL, "sync_32k_ick", &sync_32k_ick), |
1951 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), | 1951 | CLK(NULL, "wdt1_ick", &wdt1_ick), |
1952 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), | 1952 | CLK(NULL, "omapctrl_ick", &omapctrl_ick), |
1953 | CLK(NULL, "icr_ick", &icr_ick, CK_243X), | 1953 | CLK(NULL, "icr_ick", &icr_ick), |
1954 | CLK("omap24xxcam", "fck", &cam_fck, CK_243X), | 1954 | CLK("omap24xxcam", "fck", &cam_fck), |
1955 | CLK(NULL, "cam_fck", &cam_fck, CK_243X), | 1955 | CLK(NULL, "cam_fck", &cam_fck), |
1956 | CLK("omap24xxcam", "ick", &cam_ick, CK_243X), | 1956 | CLK("omap24xxcam", "ick", &cam_ick), |
1957 | CLK(NULL, "cam_ick", &cam_ick, CK_243X), | 1957 | CLK(NULL, "cam_ick", &cam_ick), |
1958 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), | 1958 | CLK(NULL, "mailboxes_ick", &mailboxes_ick), |
1959 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), | 1959 | CLK(NULL, "wdt4_ick", &wdt4_ick), |
1960 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), | 1960 | CLK(NULL, "wdt4_fck", &wdt4_fck), |
1961 | CLK(NULL, "mspro_ick", &mspro_ick, CK_243X), | 1961 | CLK(NULL, "mspro_ick", &mspro_ick), |
1962 | CLK(NULL, "mspro_fck", &mspro_fck, CK_243X), | 1962 | CLK(NULL, "mspro_fck", &mspro_fck), |
1963 | CLK(NULL, "fac_ick", &fac_ick, CK_243X), | 1963 | CLK(NULL, "fac_ick", &fac_ick), |
1964 | CLK(NULL, "fac_fck", &fac_fck, CK_243X), | 1964 | CLK(NULL, "fac_fck", &fac_fck), |
1965 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), | 1965 | CLK("omap_hdq.0", "ick", &hdq_ick), |
1966 | CLK(NULL, "hdq_ick", &hdq_ick, CK_243X), | 1966 | CLK(NULL, "hdq_ick", &hdq_ick), |
1967 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), | 1967 | CLK("omap_hdq.1", "fck", &hdq_fck), |
1968 | CLK(NULL, "hdq_fck", &hdq_fck, CK_243X), | 1968 | CLK(NULL, "hdq_fck", &hdq_fck), |
1969 | CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), | 1969 | CLK("omap_i2c.1", "ick", &i2c1_ick), |
1970 | CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X), | 1970 | CLK(NULL, "i2c1_ick", &i2c1_ick), |
1971 | CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X), | 1971 | CLK(NULL, "i2chs1_fck", &i2chs1_fck), |
1972 | CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), | 1972 | CLK("omap_i2c.2", "ick", &i2c2_ick), |
1973 | CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X), | 1973 | CLK(NULL, "i2c2_ick", &i2c2_ick), |
1974 | CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X), | 1974 | CLK(NULL, "i2chs2_fck", &i2chs2_fck), |
1975 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), | 1975 | CLK(NULL, "gpmc_fck", &gpmc_fck), |
1976 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), | 1976 | CLK(NULL, "sdma_fck", &sdma_fck), |
1977 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), | 1977 | CLK(NULL, "sdma_ick", &sdma_ick), |
1978 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), | 1978 | CLK(NULL, "sdrc_ick", &sdrc_ick), |
1979 | CLK(NULL, "des_ick", &des_ick, CK_243X), | 1979 | CLK(NULL, "des_ick", &des_ick), |
1980 | CLK("omap-sham", "ick", &sha_ick, CK_243X), | 1980 | CLK("omap-sham", "ick", &sha_ick), |
1981 | CLK("omap_rng", "ick", &rng_ick, CK_243X), | 1981 | CLK("omap_rng", "ick", &rng_ick), |
1982 | CLK(NULL, "rng_ick", &rng_ick, CK_243X), | 1982 | CLK(NULL, "rng_ick", &rng_ick), |
1983 | CLK("omap-aes", "ick", &aes_ick, CK_243X), | 1983 | CLK("omap-aes", "ick", &aes_ick), |
1984 | CLK(NULL, "pka_ick", &pka_ick, CK_243X), | 1984 | CLK(NULL, "pka_ick", &pka_ick), |
1985 | CLK(NULL, "usb_fck", &usb_fck, CK_243X), | 1985 | CLK(NULL, "usb_fck", &usb_fck), |
1986 | CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), | 1986 | CLK("musb-omap2430", "ick", &usbhs_ick), |
1987 | CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), | 1987 | CLK(NULL, "usbhs_ick", &usbhs_ick), |
1988 | CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), | 1988 | CLK("omap_hsmmc.0", "ick", &mmchs1_ick), |
1989 | CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X), | 1989 | CLK(NULL, "mmchs1_ick", &mmchs1_ick), |
1990 | CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X), | 1990 | CLK(NULL, "mmchs1_fck", &mmchs1_fck), |
1991 | CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), | 1991 | CLK("omap_hsmmc.1", "ick", &mmchs2_ick), |
1992 | CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X), | 1992 | CLK(NULL, "mmchs2_ick", &mmchs2_ick), |
1993 | CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X), | 1993 | CLK(NULL, "mmchs2_fck", &mmchs2_fck), |
1994 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), | 1994 | CLK(NULL, "gpio5_ick", &gpio5_ick), |
1995 | CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), | 1995 | CLK(NULL, "gpio5_fck", &gpio5_fck), |
1996 | CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), | 1996 | CLK(NULL, "mdm_intc_ick", &mdm_intc_ick), |
1997 | CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), | 1997 | CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck), |
1998 | CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X), | 1998 | CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck), |
1999 | CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), | 1999 | CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck), |
2000 | CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X), | 2000 | CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck), |
2001 | CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), | 2001 | CLK(NULL, "timer_32k_ck", &func_32k_ck), |
2002 | CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), | 2002 | CLK(NULL, "timer_sys_ck", &sys_ck), |
2003 | CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), | 2003 | CLK(NULL, "timer_ext_ck", &alt_ck), |
2004 | CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X), | 2004 | CLK(NULL, "cpufreq_ck", &virt_prcm_set), |
2005 | }; | 2005 | }; |
2006 | 2006 | ||
2007 | static const char *enable_init_clks[] = { | 2007 | static const char *enable_init_clks[] = { |
@@ -2019,8 +2019,6 @@ static const char *enable_init_clks[] = { | |||
2019 | 2019 | ||
2020 | int __init omap2430_clk_init(void) | 2020 | int __init omap2430_clk_init(void) |
2021 | { | 2021 | { |
2022 | struct omap_clk *c; | ||
2023 | |||
2024 | prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; | 2022 | prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; |
2025 | cpu_mask = RATE_IN_243X; | 2023 | cpu_mask = RATE_IN_243X; |
2026 | rate_table = omap2430_rate_table; | 2024 | rate_table = omap2430_rate_table; |
@@ -2029,12 +2027,7 @@ int __init omap2430_clk_init(void) | |||
2029 | 2027 | ||
2030 | omap2xxx_clkt_vps_check_bootloader_rates(); | 2028 | omap2xxx_clkt_vps_check_bootloader_rates(); |
2031 | 2029 | ||
2032 | for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); | 2030 | omap_clocks_register(omap2430_clks, ARRAY_SIZE(omap2430_clks)); |
2033 | c++) { | ||
2034 | clkdev_add(&c->lk); | ||
2035 | if (!__clk_init(NULL, c->lk.clk)) | ||
2036 | omap2_init_clk_hw_omap_clocks(c->lk.clk); | ||
2037 | } | ||
2038 | 2031 | ||
2039 | omap2xxx_clkt_vps_late_init(); | 2032 | omap2xxx_clkt_vps_late_init(); |
2040 | 2033 | ||
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index 7f091c85384e..332c6d3e55a9 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c | |||
@@ -838,80 +838,80 @@ DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops); | |||
838 | * clkdev | 838 | * clkdev |
839 | */ | 839 | */ |
840 | static struct omap_clk am33xx_clks[] = { | 840 | static struct omap_clk am33xx_clks[] = { |
841 | CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX), | 841 | CLK(NULL, "clk_32768_ck", &clk_32768_ck), |
842 | CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX), | 842 | CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck), |
843 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX), | 843 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), |
844 | CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX), | 844 | CLK(NULL, "virt_24000000_ck", &virt_24000000_ck), |
845 | CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX), | 845 | CLK(NULL, "virt_25000000_ck", &virt_25000000_ck), |
846 | CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX), | 846 | CLK(NULL, "virt_26000000_ck", &virt_26000000_ck), |
847 | CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX), | 847 | CLK(NULL, "sys_clkin_ck", &sys_clkin_ck), |
848 | CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX), | 848 | CLK(NULL, "tclkin_ck", &tclkin_ck), |
849 | CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX), | 849 | CLK(NULL, "dpll_core_ck", &dpll_core_ck), |
850 | CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX), | 850 | CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck), |
851 | CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX), | 851 | CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck), |
852 | CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX), | 852 | CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck), |
853 | CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX), | 853 | CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck), |
854 | CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX), | 854 | CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck), |
855 | CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX), | 855 | CLK("cpu0", NULL, &dpll_mpu_ck), |
856 | CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX), | 856 | CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck), |
857 | CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX), | 857 | CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck), |
858 | CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX), | 858 | CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck), |
859 | CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX), | 859 | CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck), |
860 | CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX), | 860 | CLK(NULL, "dpll_disp_ck", &dpll_disp_ck), |
861 | CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX), | 861 | CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck), |
862 | CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX), | 862 | CLK(NULL, "dpll_per_ck", &dpll_per_ck), |
863 | CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX), | 863 | CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck), |
864 | CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX), | 864 | CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck), |
865 | CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX), | 865 | CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck), |
866 | CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX), | 866 | CLK(NULL, "adc_tsc_fck", &adc_tsc_fck), |
867 | CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX), | 867 | CLK(NULL, "cefuse_fck", &cefuse_fck), |
868 | CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck, CK_AM33XX), | 868 | CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck), |
869 | CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX), | 869 | CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick), |
870 | CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX), | 870 | CLK(NULL, "dcan0_fck", &dcan0_fck), |
871 | CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX), | 871 | CLK("481cc000.d_can", NULL, &dcan0_fck), |
872 | CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX), | 872 | CLK(NULL, "dcan1_fck", &dcan1_fck), |
873 | CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX), | 873 | CLK("481d0000.d_can", NULL, &dcan1_fck), |
874 | CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX), | 874 | CLK(NULL, "debugss_ick", &debugss_ick), |
875 | CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX), | 875 | CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk), |
876 | CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX), | 876 | CLK(NULL, "mcasp0_fck", &mcasp0_fck), |
877 | CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX), | 877 | CLK(NULL, "mcasp1_fck", &mcasp1_fck), |
878 | CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX), | 878 | CLK(NULL, "mmu_fck", &mmu_fck), |
879 | CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX), | 879 | CLK(NULL, "smartreflex0_fck", &smartreflex0_fck), |
880 | CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX), | 880 | CLK(NULL, "smartreflex1_fck", &smartreflex1_fck), |
881 | CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX), | 881 | CLK(NULL, "timer1_fck", &timer1_fck), |
882 | CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX), | 882 | CLK(NULL, "timer2_fck", &timer2_fck), |
883 | CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX), | 883 | CLK(NULL, "timer3_fck", &timer3_fck), |
884 | CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX), | 884 | CLK(NULL, "timer4_fck", &timer4_fck), |
885 | CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX), | 885 | CLK(NULL, "timer5_fck", &timer5_fck), |
886 | CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX), | 886 | CLK(NULL, "timer6_fck", &timer6_fck), |
887 | CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX), | 887 | CLK(NULL, "timer7_fck", &timer7_fck), |
888 | CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX), | 888 | CLK(NULL, "usbotg_fck", &usbotg_fck), |
889 | CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX), | 889 | CLK(NULL, "ieee5000_fck", &ieee5000_fck), |
890 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX), | 890 | CLK(NULL, "wdt1_fck", &wdt1_fck), |
891 | CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX), | 891 | CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk), |
892 | CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX), | 892 | CLK(NULL, "l3_gclk", &l3_gclk), |
893 | CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX), | 893 | CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck), |
894 | CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX), | 894 | CLK(NULL, "l4hs_gclk", &l4hs_gclk), |
895 | CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX), | 895 | CLK(NULL, "l3s_gclk", &l3s_gclk), |
896 | CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX), | 896 | CLK(NULL, "l4fw_gclk", &l4fw_gclk), |
897 | CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX), | 897 | CLK(NULL, "l4ls_gclk", &l4ls_gclk), |
898 | CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX), | 898 | CLK(NULL, "clk_24mhz", &clk_24mhz), |
899 | CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX), | 899 | CLK(NULL, "sysclk_div_ck", &sysclk_div_ck), |
900 | CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX), | 900 | CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk), |
901 | CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX), | 901 | CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk), |
902 | CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX), | 902 | CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck), |
903 | CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX), | 903 | CLK(NULL, "gpio0_dbclk", &gpio0_dbclk), |
904 | CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX), | 904 | CLK(NULL, "gpio1_dbclk", &gpio1_dbclk), |
905 | CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX), | 905 | CLK(NULL, "gpio2_dbclk", &gpio2_dbclk), |
906 | CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX), | 906 | CLK(NULL, "gpio3_dbclk", &gpio3_dbclk), |
907 | CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX), | 907 | CLK(NULL, "lcd_gclk", &lcd_gclk), |
908 | CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX), | 908 | CLK(NULL, "mmc_clk", &mmc_clk), |
909 | CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX), | 909 | CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck), |
910 | CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX), | 910 | CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck), |
911 | CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX), | 911 | CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck), |
912 | CLK(NULL, "clkout2_div_ck", &clkout2_div_ck, CK_AM33XX), | 912 | CLK(NULL, "clkout2_div_ck", &clkout2_div_ck), |
913 | CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX), | 913 | CLK(NULL, "timer_32k_ck", &clkdiv32k_ick), |
914 | CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX), | 914 | CLK(NULL, "timer_sys_ck", &sys_clkin_ck), |
915 | }; | 915 | }; |
916 | 916 | ||
917 | 917 | ||
@@ -926,21 +926,10 @@ static const char *enable_init_clks[] = { | |||
926 | 926 | ||
927 | int __init am33xx_clk_init(void) | 927 | int __init am33xx_clk_init(void) |
928 | { | 928 | { |
929 | struct omap_clk *c; | 929 | if (soc_is_am33xx()) |
930 | u32 cpu_clkflg; | ||
931 | |||
932 | if (soc_is_am33xx()) { | ||
933 | cpu_mask = RATE_IN_AM33XX; | 930 | cpu_mask = RATE_IN_AM33XX; |
934 | cpu_clkflg = CK_AM33XX; | 931 | |
935 | } | 932 | omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks)); |
936 | |||
937 | for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) { | ||
938 | if (c->cpu & cpu_clkflg) { | ||
939 | clkdev_add(&c->lk); | ||
940 | if (!__clk_init(NULL, c->lk.clk)) | ||
941 | omap2_init_clk_hw_omap_clocks(c->lk.clk); | ||
942 | } | ||
943 | } | ||
944 | 933 | ||
945 | omap2_clk_disable_autoidle_all(); | 934 | omap2_clk_disable_autoidle_all(); |
946 | 935 | ||
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c index 4579c3c5338f..438d13341e23 100644 --- a/arch/arm/mach-omap2/cclock3xxx_data.c +++ b/arch/arm/mach-omap2/cclock3xxx_data.c | |||
@@ -3219,289 +3219,325 @@ static struct clk_hw_omap wdt3_ick_hw = { | |||
3219 | DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops); | 3219 | DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops); |
3220 | 3220 | ||
3221 | /* | 3221 | /* |
3222 | * clkdev | 3222 | * clocks specific to omap3430es1 |
3223 | */ | ||
3224 | static struct omap_clk omap3430es1_clks[] = { | ||
3225 | CLK(NULL, "gfx_l3_ck", &gfx_l3_ck), | ||
3226 | CLK(NULL, "gfx_l3_fck", &gfx_l3_fck), | ||
3227 | CLK(NULL, "gfx_l3_ick", &gfx_l3_ick), | ||
3228 | CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck), | ||
3229 | CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck), | ||
3230 | CLK(NULL, "d2d_26m_fck", &d2d_26m_fck), | ||
3231 | CLK(NULL, "fshostusb_fck", &fshostusb_fck), | ||
3232 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1), | ||
3233 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1), | ||
3234 | CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1), | ||
3235 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1), | ||
3236 | CLK(NULL, "fac_ick", &fac_ick), | ||
3237 | CLK(NULL, "ssi_ick", &ssi_ick_3430es1), | ||
3238 | CLK(NULL, "usb_l4_ick", &usb_l4_ick), | ||
3239 | CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1), | ||
3240 | CLK("omapdss_dss", "ick", &dss_ick_3430es1), | ||
3241 | CLK(NULL, "dss_ick", &dss_ick_3430es1), | ||
3242 | }; | ||
3243 | |||
3244 | /* | ||
3245 | * clocks specific to am35xx | ||
3246 | */ | ||
3247 | static struct omap_clk am35xx_clks[] = { | ||
3248 | CLK(NULL, "ipss_ick", &ipss_ick), | ||
3249 | CLK(NULL, "rmii_ck", &rmii_ck), | ||
3250 | CLK(NULL, "pclk_ck", &pclk_ck), | ||
3251 | CLK(NULL, "emac_ick", &emac_ick), | ||
3252 | CLK(NULL, "emac_fck", &emac_fck), | ||
3253 | CLK("davinci_emac.0", NULL, &emac_ick), | ||
3254 | CLK("davinci_mdio.0", NULL, &emac_fck), | ||
3255 | CLK("vpfe-capture", "master", &vpfe_ick), | ||
3256 | CLK("vpfe-capture", "slave", &vpfe_fck), | ||
3257 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx), | ||
3258 | CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx), | ||
3259 | CLK(NULL, "hecc_ck", &hecc_ck), | ||
3260 | CLK(NULL, "uart4_ick", &uart4_ick_am35xx), | ||
3261 | CLK(NULL, "uart4_fck", &uart4_fck_am35xx), | ||
3262 | }; | ||
3263 | |||
3264 | /* | ||
3265 | * clocks specific to omap36xx | ||
3266 | */ | ||
3267 | static struct omap_clk omap36xx_clks[] = { | ||
3268 | CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck), | ||
3269 | CLK(NULL, "uart4_fck", &uart4_fck), | ||
3270 | }; | ||
3271 | |||
3272 | /* | ||
3273 | * clocks common to omap36xx omap34xx | ||
3274 | */ | ||
3275 | static struct omap_clk omap34xx_omap36xx_clks[] = { | ||
3276 | CLK(NULL, "aes1_ick", &aes1_ick), | ||
3277 | CLK("omap_rng", "ick", &rng_ick), | ||
3278 | CLK(NULL, "sha11_ick", &sha11_ick), | ||
3279 | CLK(NULL, "des1_ick", &des1_ick), | ||
3280 | CLK(NULL, "cam_mclk", &cam_mclk), | ||
3281 | CLK(NULL, "cam_ick", &cam_ick), | ||
3282 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck), | ||
3283 | CLK(NULL, "security_l3_ick", &security_l3_ick), | ||
3284 | CLK(NULL, "pka_ick", &pka_ick), | ||
3285 | CLK(NULL, "icr_ick", &icr_ick), | ||
3286 | CLK("omap-aes", "ick", &aes2_ick), | ||
3287 | CLK("omap-sham", "ick", &sha12_ick), | ||
3288 | CLK(NULL, "des2_ick", &des2_ick), | ||
3289 | CLK(NULL, "mspro_ick", &mspro_ick), | ||
3290 | CLK(NULL, "mailboxes_ick", &mailboxes_ick), | ||
3291 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick), | ||
3292 | CLK(NULL, "sr1_fck", &sr1_fck), | ||
3293 | CLK(NULL, "sr2_fck", &sr2_fck), | ||
3294 | CLK(NULL, "sr_l4_ick", &sr_l4_ick), | ||
3295 | CLK(NULL, "security_l4_ick2", &security_l4_ick2), | ||
3296 | CLK(NULL, "wkup_l4_ick", &wkup_l4_ick), | ||
3297 | CLK(NULL, "dpll2_fck", &dpll2_fck), | ||
3298 | CLK(NULL, "iva2_ck", &iva2_ck), | ||
3299 | CLK(NULL, "modem_fck", &modem_fck), | ||
3300 | CLK(NULL, "sad2d_ick", &sad2d_ick), | ||
3301 | CLK(NULL, "mad2d_ick", &mad2d_ick), | ||
3302 | CLK(NULL, "mspro_fck", &mspro_fck), | ||
3303 | CLK(NULL, "dpll2_ck", &dpll2_ck), | ||
3304 | CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck), | ||
3305 | }; | ||
3306 | |||
3307 | /* | ||
3308 | * clocks common to omap36xx and omap3430es2plus | ||
3309 | */ | ||
3310 | static struct omap_clk omap36xx_omap3430es2plus_clks[] = { | ||
3311 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2), | ||
3312 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2), | ||
3313 | CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2), | ||
3314 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2), | ||
3315 | CLK(NULL, "ssi_ick", &ssi_ick_3430es2), | ||
3316 | CLK(NULL, "usim_fck", &usim_fck), | ||
3317 | CLK(NULL, "usim_ick", &usim_ick), | ||
3318 | }; | ||
3319 | |||
3320 | /* | ||
3321 | * clocks common to am35xx omap36xx and omap3430es2plus | ||
3322 | */ | ||
3323 | static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = { | ||
3324 | CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck), | ||
3325 | CLK(NULL, "dpll5_ck", &dpll5_ck), | ||
3326 | CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck), | ||
3327 | CLK(NULL, "sgx_fck", &sgx_fck), | ||
3328 | CLK(NULL, "sgx_ick", &sgx_ick), | ||
3329 | CLK(NULL, "cpefuse_fck", &cpefuse_fck), | ||
3330 | CLK(NULL, "ts_fck", &ts_fck), | ||
3331 | CLK(NULL, "usbtll_fck", &usbtll_fck), | ||
3332 | CLK("usbhs_omap", "usbtll_fck", &usbtll_fck), | ||
3333 | CLK("usbhs_tll", "usbtll_fck", &usbtll_fck), | ||
3334 | CLK(NULL, "usbtll_ick", &usbtll_ick), | ||
3335 | CLK("usbhs_omap", "usbtll_ick", &usbtll_ick), | ||
3336 | CLK("usbhs_tll", "usbtll_ick", &usbtll_ick), | ||
3337 | CLK("omap_hsmmc.2", "ick", &mmchs3_ick), | ||
3338 | CLK(NULL, "mmchs3_ick", &mmchs3_ick), | ||
3339 | CLK(NULL, "mmchs3_fck", &mmchs3_fck), | ||
3340 | CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2), | ||
3341 | CLK("omapdss_dss", "ick", &dss_ick_3430es2), | ||
3342 | CLK(NULL, "dss_ick", &dss_ick_3430es2), | ||
3343 | CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck), | ||
3344 | CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck), | ||
3345 | CLK(NULL, "usbhost_ick", &usbhost_ick), | ||
3346 | CLK("usbhs_omap", "usbhost_ick", &usbhost_ick), | ||
3347 | }; | ||
3348 | |||
3349 | /* | ||
3350 | * common clocks | ||
3223 | */ | 3351 | */ |
3224 | static struct omap_clk omap3xxx_clks[] = { | 3352 | static struct omap_clk omap3xxx_clks[] = { |
3225 | CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX), | 3353 | CLK(NULL, "apb_pclk", &dummy_apb_pclk), |
3226 | CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), | 3354 | CLK(NULL, "omap_32k_fck", &omap_32k_fck), |
3227 | CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), | 3355 | CLK(NULL, "virt_12m_ck", &virt_12m_ck), |
3228 | CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), | 3356 | CLK(NULL, "virt_13m_ck", &virt_13m_ck), |
3229 | CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3357 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), |
3230 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_3XXX), | 3358 | CLK(NULL, "virt_26000000_ck", &virt_26000000_ck), |
3231 | CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX), | 3359 | CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck), |
3232 | CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), | 3360 | CLK(NULL, "osc_sys_ck", &osc_sys_ck), |
3233 | CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), | 3361 | CLK("twl", "fck", &osc_sys_ck), |
3234 | CLK("twl", "fck", &osc_sys_ck, CK_3XXX), | 3362 | CLK(NULL, "sys_ck", &sys_ck), |
3235 | CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), | 3363 | CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck), |
3236 | CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), | 3364 | CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck), |
3237 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), | 3365 | CLK(NULL, "sys_altclk", &sys_altclk), |
3238 | CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), | 3366 | CLK(NULL, "mcbsp_clks", &mcbsp_clks), |
3239 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), | 3367 | CLK(NULL, "sys_clkout1", &sys_clkout1), |
3240 | CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX), | 3368 | CLK(NULL, "dpll1_ck", &dpll1_ck), |
3241 | CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX), | 3369 | CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck), |
3242 | CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX), | 3370 | CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck), |
3243 | CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX), | 3371 | CLK(NULL, "dpll3_ck", &dpll3_ck), |
3244 | CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX), | 3372 | CLK(NULL, "core_ck", &core_ck), |
3245 | CLK(NULL, "core_ck", &core_ck, CK_3XXX), | 3373 | CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck), |
3246 | CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX), | 3374 | CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck), |
3247 | CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX), | 3375 | CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck), |
3248 | CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX), | 3376 | CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck), |
3249 | CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX), | 3377 | CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck), |
3250 | CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX), | 3378 | CLK(NULL, "dpll4_ck", &dpll4_ck), |
3251 | CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), | 3379 | CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck), |
3252 | CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX), | 3380 | CLK(NULL, "omap_96m_fck", &omap_96m_fck), |
3253 | CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX), | 3381 | CLK(NULL, "cm_96m_fck", &cm_96m_fck), |
3254 | CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX), | 3382 | CLK(NULL, "omap_54m_fck", &omap_54m_fck), |
3255 | CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX), | 3383 | CLK(NULL, "omap_48m_fck", &omap_48m_fck), |
3256 | CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX), | 3384 | CLK(NULL, "omap_12m_fck", &omap_12m_fck), |
3257 | CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX), | 3385 | CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck), |
3258 | CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX), | 3386 | CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck), |
3259 | CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX), | 3387 | CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck), |
3260 | CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX), | 3388 | CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck), |
3261 | CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX), | 3389 | CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck), |
3262 | CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX), | 3390 | CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck), |
3263 | CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX), | 3391 | CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck), |
3264 | CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX), | 3392 | CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck), |
3265 | CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX), | 3393 | CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck), |
3266 | CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX), | 3394 | CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck), |
3267 | CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX), | 3395 | CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck), |
3268 | CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX), | 3396 | CLK(NULL, "clkout2_src_ck", &clkout2_src_ck), |
3269 | CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), | 3397 | CLK(NULL, "sys_clkout2", &sys_clkout2), |
3270 | CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), | 3398 | CLK(NULL, "corex2_fck", &corex2_fck), |
3271 | CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), | 3399 | CLK(NULL, "dpll1_fck", &dpll1_fck), |
3272 | CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3400 | CLK(NULL, "mpu_ck", &mpu_ck), |
3273 | CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3401 | CLK(NULL, "arm_fck", &arm_fck), |
3274 | CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), | 3402 | CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck), |
3275 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), | 3403 | CLK(NULL, "l3_ick", &l3_ick), |
3276 | CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), | 3404 | CLK(NULL, "l4_ick", &l4_ick), |
3277 | CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX), | 3405 | CLK(NULL, "rm_ick", &rm_ick), |
3278 | CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), | 3406 | CLK(NULL, "gpt10_fck", &gpt10_fck), |
3279 | CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), | 3407 | CLK(NULL, "gpt11_fck", &gpt11_fck), |
3280 | CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), | 3408 | CLK(NULL, "core_96m_fck", &core_96m_fck), |
3281 | CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX), | 3409 | CLK(NULL, "mmchs2_fck", &mmchs2_fck), |
3282 | CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX), | 3410 | CLK(NULL, "mmchs1_fck", &mmchs1_fck), |
3283 | CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), | 3411 | CLK(NULL, "i2c3_fck", &i2c3_fck), |
3284 | CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), | 3412 | CLK(NULL, "i2c2_fck", &i2c2_fck), |
3285 | CLK(NULL, "rm_ick", &rm_ick, CK_3XXX), | 3413 | CLK(NULL, "i2c1_fck", &i2c1_fck), |
3286 | CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), | 3414 | CLK(NULL, "mcbsp5_fck", &mcbsp5_fck), |
3287 | CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), | 3415 | CLK(NULL, "mcbsp1_fck", &mcbsp1_fck), |
3288 | CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), | 3416 | CLK(NULL, "core_48m_fck", &core_48m_fck), |
3289 | CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), | 3417 | CLK(NULL, "mcspi4_fck", &mcspi4_fck), |
3290 | CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), | 3418 | CLK(NULL, "mcspi3_fck", &mcspi3_fck), |
3291 | CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3419 | CLK(NULL, "mcspi2_fck", &mcspi2_fck), |
3292 | CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3420 | CLK(NULL, "mcspi1_fck", &mcspi1_fck), |
3293 | CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), | 3421 | CLK(NULL, "uart2_fck", &uart2_fck), |
3294 | CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX), | 3422 | CLK(NULL, "uart1_fck", &uart1_fck), |
3295 | CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX), | 3423 | CLK(NULL, "core_12m_fck", &core_12m_fck), |
3296 | CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX), | 3424 | CLK("omap_hdq.0", "fck", &hdq_fck), |
3297 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), | 3425 | CLK(NULL, "hdq_fck", &hdq_fck), |
3298 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), | 3426 | CLK(NULL, "core_l3_ick", &core_l3_ick), |
3299 | CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3427 | CLK(NULL, "sdrc_ick", &sdrc_ick), |
3300 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3428 | CLK(NULL, "gpmc_fck", &gpmc_fck), |
3301 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3429 | CLK(NULL, "core_l4_ick", &core_l4_ick), |
3302 | CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3430 | CLK("omap_hsmmc.1", "ick", &mmchs2_ick), |
3303 | CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3431 | CLK("omap_hsmmc.0", "ick", &mmchs1_ick), |
3304 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), | 3432 | CLK(NULL, "mmchs2_ick", &mmchs2_ick), |
3305 | CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3433 | CLK(NULL, "mmchs1_ick", &mmchs1_ick), |
3306 | CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), | 3434 | CLK("omap_hdq.0", "ick", &hdq_ick), |
3307 | CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), | 3435 | CLK(NULL, "hdq_ick", &hdq_ick), |
3308 | CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX), | 3436 | CLK("omap2_mcspi.4", "ick", &mcspi4_ick), |
3309 | CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX), | 3437 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick), |
3310 | CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX), | 3438 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick), |
3311 | CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX), | 3439 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick), |
3312 | CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX), | 3440 | CLK(NULL, "mcspi4_ick", &mcspi4_ick), |
3313 | CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX), | 3441 | CLK(NULL, "mcspi3_ick", &mcspi3_ick), |
3314 | CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX), | 3442 | CLK(NULL, "mcspi2_ick", &mcspi2_ick), |
3315 | CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX), | 3443 | CLK(NULL, "mcspi1_ick", &mcspi1_ick), |
3316 | CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX), | 3444 | CLK("omap_i2c.3", "ick", &i2c3_ick), |
3317 | CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX), | 3445 | CLK("omap_i2c.2", "ick", &i2c2_ick), |
3318 | CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX), | 3446 | CLK("omap_i2c.1", "ick", &i2c1_ick), |
3319 | CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX), | 3447 | CLK(NULL, "i2c3_ick", &i2c3_ick), |
3320 | CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX), | 3448 | CLK(NULL, "i2c2_ick", &i2c2_ick), |
3321 | CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), | 3449 | CLK(NULL, "i2c1_ick", &i2c1_ick), |
3322 | CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), | 3450 | CLK(NULL, "uart2_ick", &uart2_ick), |
3323 | CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), | 3451 | CLK(NULL, "uart1_ick", &uart1_ick), |
3324 | CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX), | 3452 | CLK(NULL, "gpt11_ick", &gpt11_ick), |
3325 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), | 3453 | CLK(NULL, "gpt10_ick", &gpt10_ick), |
3326 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX), | 3454 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick), |
3327 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), | 3455 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick), |
3328 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX), | 3456 | CLK(NULL, "mcbsp5_ick", &mcbsp5_ick), |
3329 | CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), | 3457 | CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), |
3330 | CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), | 3458 | CLK(NULL, "omapctrl_ick", &omapctrl_ick), |
3331 | CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), | 3459 | CLK(NULL, "dss_tv_fck", &dss_tv_fck), |
3332 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1), | 3460 | CLK(NULL, "dss_96m_fck", &dss_96m_fck), |
3333 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), | 3461 | CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck), |
3334 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), | 3462 | CLK(NULL, "utmi_p1_gfclk", &dummy_ck), |
3335 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), | 3463 | CLK(NULL, "utmi_p2_gfclk", &dummy_ck), |
3336 | CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX), | 3464 | CLK(NULL, "xclk60mhsp1_ck", &dummy_ck), |
3337 | CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX), | 3465 | CLK(NULL, "xclk60mhsp2_ck", &dummy_ck), |
3338 | CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), | 3466 | CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck), |
3339 | CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3467 | CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck), |
3340 | CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3468 | CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck), |
3341 | CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3469 | CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck), |
3342 | CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3470 | CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck), |
3343 | CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3471 | CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck), |
3344 | CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), | 3472 | CLK(NULL, "init_60m_fclk", &dummy_ck), |
3345 | CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), | 3473 | CLK(NULL, "gpt1_fck", &gpt1_fck), |
3346 | CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), | 3474 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck), |
3347 | CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), | 3475 | CLK(NULL, "gpio1_dbck", &gpio1_dbck), |
3348 | CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX), | 3476 | CLK(NULL, "wdt2_fck", &wdt2_fck), |
3349 | CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX), | 3477 | CLK("omap_wdt", "ick", &wdt2_ick), |
3350 | CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX), | 3478 | CLK(NULL, "wdt2_ick", &wdt2_ick), |
3351 | CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX), | 3479 | CLK(NULL, "wdt1_ick", &wdt1_ick), |
3352 | CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), | 3480 | CLK(NULL, "gpio1_ick", &gpio1_ick), |
3353 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), | 3481 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick), |
3354 | CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX), | 3482 | CLK(NULL, "gpt12_ick", &gpt12_ick), |
3355 | CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), | 3483 | CLK(NULL, "gpt1_ick", &gpt1_ick), |
3356 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), | 3484 | CLK(NULL, "per_96m_fck", &per_96m_fck), |
3357 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), | 3485 | CLK(NULL, "per_48m_fck", &per_48m_fck), |
3358 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), | 3486 | CLK(NULL, "uart3_fck", &uart3_fck), |
3359 | CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX), | 3487 | CLK(NULL, "gpt2_fck", &gpt2_fck), |
3360 | CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX), | 3488 | CLK(NULL, "gpt3_fck", &gpt3_fck), |
3361 | CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX), | 3489 | CLK(NULL, "gpt4_fck", &gpt4_fck), |
3362 | CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX), | 3490 | CLK(NULL, "gpt5_fck", &gpt5_fck), |
3363 | CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX), | 3491 | CLK(NULL, "gpt6_fck", &gpt6_fck), |
3364 | CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX), | 3492 | CLK(NULL, "gpt7_fck", &gpt7_fck), |
3365 | CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX), | 3493 | CLK(NULL, "gpt8_fck", &gpt8_fck), |
3366 | CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX), | 3494 | CLK(NULL, "gpt9_fck", &gpt9_fck), |
3367 | CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX), | 3495 | CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck), |
3368 | CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX), | 3496 | CLK(NULL, "gpio6_dbck", &gpio6_dbck), |
3369 | CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), | 3497 | CLK(NULL, "gpio5_dbck", &gpio5_dbck), |
3370 | CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), | 3498 | CLK(NULL, "gpio4_dbck", &gpio4_dbck), |
3371 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), | 3499 | CLK(NULL, "gpio3_dbck", &gpio3_dbck), |
3372 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX), | 3500 | CLK(NULL, "gpio2_dbck", &gpio2_dbck), |
3373 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), | 3501 | CLK(NULL, "wdt3_fck", &wdt3_fck), |
3374 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), | 3502 | CLK(NULL, "per_l4_ick", &per_l4_ick), |
3375 | CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX), | 3503 | CLK(NULL, "gpio6_ick", &gpio6_ick), |
3376 | CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX), | 3504 | CLK(NULL, "gpio5_ick", &gpio5_ick), |
3377 | CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), | 3505 | CLK(NULL, "gpio4_ick", &gpio4_ick), |
3378 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX), | 3506 | CLK(NULL, "gpio3_ick", &gpio3_ick), |
3379 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), | 3507 | CLK(NULL, "gpio2_ick", &gpio2_ick), |
3380 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX), | 3508 | CLK(NULL, "wdt3_ick", &wdt3_ick), |
3381 | CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), | 3509 | CLK(NULL, "uart3_ick", &uart3_ick), |
3382 | CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX), | 3510 | CLK(NULL, "uart4_ick", &uart4_ick), |
3383 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), | 3511 | CLK(NULL, "gpt9_ick", &gpt9_ick), |
3384 | CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX), | 3512 | CLK(NULL, "gpt8_ick", &gpt8_ick), |
3385 | CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX), | 3513 | CLK(NULL, "gpt7_ick", &gpt7_ick), |
3386 | CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), | 3514 | CLK(NULL, "gpt6_ick", &gpt6_ick), |
3387 | CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), | 3515 | CLK(NULL, "gpt5_ick", &gpt5_ick), |
3388 | CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), | 3516 | CLK(NULL, "gpt4_ick", &gpt4_ick), |
3389 | CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), | 3517 | CLK(NULL, "gpt3_ick", &gpt3_ick), |
3390 | CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3518 | CLK(NULL, "gpt2_ick", &gpt2_ick), |
3391 | CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX), | 3519 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick), |
3392 | CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX), | 3520 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick), |
3393 | CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX), | 3521 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick), |
3394 | CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), | 3522 | CLK(NULL, "mcbsp4_ick", &mcbsp2_ick), |
3395 | CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1), | 3523 | CLK(NULL, "mcbsp3_ick", &mcbsp3_ick), |
3396 | CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3524 | CLK(NULL, "mcbsp2_ick", &mcbsp4_ick), |
3397 | CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3525 | CLK(NULL, "mcbsp2_fck", &mcbsp2_fck), |
3398 | CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), | 3526 | CLK(NULL, "mcbsp3_fck", &mcbsp3_fck), |
3399 | CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), | 3527 | CLK(NULL, "mcbsp4_fck", &mcbsp4_fck), |
3400 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), | 3528 | CLK("etb", "emu_src_ck", &emu_src_ck), |
3401 | CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3529 | CLK(NULL, "emu_src_ck", &emu_src_ck), |
3402 | CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3530 | CLK(NULL, "pclk_fck", &pclk_fck), |
3403 | CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3531 | CLK(NULL, "pclkx2_fck", &pclkx2_fck), |
3404 | CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3532 | CLK(NULL, "atclk_fck", &atclk_fck), |
3405 | CLK(NULL, "utmi_p1_gfclk", &dummy_ck, CK_3XXX), | 3533 | CLK(NULL, "traceclk_src_fck", &traceclk_src_fck), |
3406 | CLK(NULL, "utmi_p2_gfclk", &dummy_ck, CK_3XXX), | 3534 | CLK(NULL, "traceclk_fck", &traceclk_fck), |
3407 | CLK(NULL, "xclk60mhsp1_ck", &dummy_ck, CK_3XXX), | 3535 | CLK(NULL, "secure_32k_fck", &secure_32k_fck), |
3408 | CLK(NULL, "xclk60mhsp2_ck", &dummy_ck, CK_3XXX), | 3536 | CLK(NULL, "gpt12_fck", &gpt12_fck), |
3409 | CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX), | 3537 | CLK(NULL, "wdt1_fck", &wdt1_fck), |
3410 | CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX), | 3538 | CLK(NULL, "timer_32k_ck", &omap_32k_fck), |
3411 | CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), | 3539 | CLK(NULL, "timer_sys_ck", &sys_ck), |
3412 | CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), | 3540 | CLK(NULL, "cpufreq_ck", &dpll1_ck), |
3413 | CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), | ||
3414 | CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), | ||
3415 | CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX), | ||
3416 | CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX), | ||
3417 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), | ||
3418 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), | ||
3419 | CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), | ||
3420 | CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX), | ||
3421 | CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX), | ||
3422 | CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX), | ||
3423 | CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), | ||
3424 | CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX), | ||
3425 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), | ||
3426 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), | ||
3427 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), | ||
3428 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), | ||
3429 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), | ||
3430 | CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), | ||
3431 | CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), | ||
3432 | CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), | ||
3433 | CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX), | ||
3434 | CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX), | ||
3435 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), | ||
3436 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), | ||
3437 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), | ||
3438 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX), | ||
3439 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX), | ||
3440 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX), | ||
3441 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX), | ||
3442 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX), | ||
3443 | CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX), | ||
3444 | CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX), | ||
3445 | CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX), | ||
3446 | CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX), | ||
3447 | CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX), | ||
3448 | CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX), | ||
3449 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX), | ||
3450 | CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX), | ||
3451 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX), | ||
3452 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX), | ||
3453 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX), | ||
3454 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX), | ||
3455 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX), | ||
3456 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX), | ||
3457 | CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX), | ||
3458 | CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX), | ||
3459 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX), | ||
3460 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX), | ||
3461 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX), | ||
3462 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX), | ||
3463 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX), | ||
3464 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX), | ||
3465 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX), | ||
3466 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX), | ||
3467 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX), | ||
3468 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX), | ||
3469 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX), | ||
3470 | CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX), | ||
3471 | CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX), | ||
3472 | CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX), | ||
3473 | CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX), | ||
3474 | CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX), | ||
3475 | CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX), | ||
3476 | CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX), | ||
3477 | CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX), | ||
3478 | CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX), | ||
3479 | CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX), | ||
3480 | CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX), | ||
3481 | CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX), | ||
3482 | CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX), | ||
3483 | CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX), | ||
3484 | CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX), | ||
3485 | CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX), | ||
3486 | CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), | ||
3487 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), | ||
3488 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), | ||
3489 | CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), | ||
3490 | CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), | ||
3491 | CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), | ||
3492 | CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX), | ||
3493 | CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX), | ||
3494 | CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX), | ||
3495 | CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX), | ||
3496 | CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), | ||
3497 | CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), | ||
3498 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX), | ||
3499 | CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX), | ||
3500 | CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), | ||
3501 | CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), | ||
3502 | CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX), | ||
3503 | CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX), | ||
3504 | CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX), | ||
3505 | }; | 3541 | }; |
3506 | 3542 | ||
3507 | static const char *enable_init_clks[] = { | 3543 | static const char *enable_init_clks[] = { |
@@ -3512,8 +3548,27 @@ static const char *enable_init_clks[] = { | |||
3512 | 3548 | ||
3513 | int __init omap3xxx_clk_init(void) | 3549 | int __init omap3xxx_clk_init(void) |
3514 | { | 3550 | { |
3515 | struct omap_clk *c; | 3551 | if (omap3_has_192mhz_clk()) |
3516 | u32 cpu_clkflg = 0; | 3552 | omap_96m_alwon_fck = omap_96m_alwon_fck_3630; |
3553 | |||
3554 | if (cpu_is_omap3630()) { | ||
3555 | dpll3_m3x2_ck = dpll3_m3x2_ck_3630; | ||
3556 | dpll4_m2x2_ck = dpll4_m2x2_ck_3630; | ||
3557 | dpll4_m3x2_ck = dpll4_m3x2_ck_3630; | ||
3558 | dpll4_m4x2_ck = dpll4_m4x2_ck_3630; | ||
3559 | dpll4_m5x2_ck = dpll4_m5x2_ck_3630; | ||
3560 | dpll4_m6x2_ck = dpll4_m6x2_ck_3630; | ||
3561 | } | ||
3562 | |||
3563 | /* | ||
3564 | * XXX This type of dynamic rewriting of the clock tree is | ||
3565 | * deprecated and should be revised soon. | ||
3566 | */ | ||
3567 | if (cpu_is_omap3630()) | ||
3568 | dpll4_dd = dpll4_dd_3630; | ||
3569 | else | ||
3570 | dpll4_dd = dpll4_dd_34xx; | ||
3571 | |||
3517 | 3572 | ||
3518 | /* | 3573 | /* |
3519 | * 3505 must be tested before 3517, since 3517 returns true | 3574 | * 3505 must be tested before 3517, since 3517 returns true |
@@ -3523,13 +3578,20 @@ int __init omap3xxx_clk_init(void) | |||
3523 | */ | 3578 | */ |
3524 | if (soc_is_am35xx()) { | 3579 | if (soc_is_am35xx()) { |
3525 | cpu_mask = RATE_IN_34XX; | 3580 | cpu_mask = RATE_IN_34XX; |
3526 | cpu_clkflg = CK_AM35XX; | 3581 | omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks)); |
3582 | omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks, | ||
3583 | ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks)); | ||
3584 | omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks)); | ||
3527 | } else if (cpu_is_omap3630()) { | 3585 | } else if (cpu_is_omap3630()) { |
3528 | cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); | 3586 | cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); |
3529 | cpu_clkflg = CK_36XX; | 3587 | omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks)); |
3530 | } else if (cpu_is_ti816x()) { | 3588 | omap_clocks_register(omap36xx_omap3430es2plus_clks, |
3531 | cpu_mask = RATE_IN_TI816X; | 3589 | ARRAY_SIZE(omap36xx_omap3430es2plus_clks)); |
3532 | cpu_clkflg = CK_TI816X; | 3590 | omap_clocks_register(omap34xx_omap36xx_clks, |
3591 | ARRAY_SIZE(omap34xx_omap36xx_clks)); | ||
3592 | omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks, | ||
3593 | ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks)); | ||
3594 | omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks)); | ||
3533 | } else if (soc_is_am33xx()) { | 3595 | } else if (soc_is_am33xx()) { |
3534 | cpu_mask = RATE_IN_AM33XX; | 3596 | cpu_mask = RATE_IN_AM33XX; |
3535 | } else if (cpu_is_ti814x()) { | 3597 | } else if (cpu_is_ti814x()) { |
@@ -3537,49 +3599,32 @@ int __init omap3xxx_clk_init(void) | |||
3537 | } else if (cpu_is_omap34xx()) { | 3599 | } else if (cpu_is_omap34xx()) { |
3538 | if (omap_rev() == OMAP3430_REV_ES1_0) { | 3600 | if (omap_rev() == OMAP3430_REV_ES1_0) { |
3539 | cpu_mask = RATE_IN_3430ES1; | 3601 | cpu_mask = RATE_IN_3430ES1; |
3540 | cpu_clkflg = CK_3430ES1; | 3602 | omap_clocks_register(omap3430es1_clks, |
3603 | ARRAY_SIZE(omap3430es1_clks)); | ||
3604 | omap_clocks_register(omap34xx_omap36xx_clks, | ||
3605 | ARRAY_SIZE(omap34xx_omap36xx_clks)); | ||
3606 | omap_clocks_register(omap3xxx_clks, | ||
3607 | ARRAY_SIZE(omap3xxx_clks)); | ||
3541 | } else { | 3608 | } else { |
3542 | /* | 3609 | /* |
3543 | * Assume that anything that we haven't matched yet | 3610 | * Assume that anything that we haven't matched yet |
3544 | * has 3430ES2-type clocks. | 3611 | * has 3430ES2-type clocks. |
3545 | */ | 3612 | */ |
3546 | cpu_mask = RATE_IN_3430ES2PLUS; | 3613 | cpu_mask = RATE_IN_3430ES2PLUS; |
3547 | cpu_clkflg = CK_3430ES2PLUS; | 3614 | omap_clocks_register(omap34xx_omap36xx_clks, |
3615 | ARRAY_SIZE(omap34xx_omap36xx_clks)); | ||
3616 | omap_clocks_register(omap36xx_omap3430es2plus_clks, | ||
3617 | ARRAY_SIZE(omap36xx_omap3430es2plus_clks)); | ||
3618 | omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks, | ||
3619 | ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks)); | ||
3620 | omap_clocks_register(omap3xxx_clks, | ||
3621 | ARRAY_SIZE(omap3xxx_clks)); | ||
3548 | } | 3622 | } |
3549 | } else { | 3623 | } else { |
3550 | WARN(1, "clock: could not identify OMAP3 variant\n"); | 3624 | WARN(1, "clock: could not identify OMAP3 variant\n"); |
3551 | } | 3625 | } |
3552 | 3626 | ||
3553 | if (omap3_has_192mhz_clk()) | 3627 | omap2_clk_disable_autoidle_all(); |
3554 | omap_96m_alwon_fck = omap_96m_alwon_fck_3630; | ||
3555 | |||
3556 | if (cpu_is_omap3630()) { | ||
3557 | dpll3_m3x2_ck = dpll3_m3x2_ck_3630; | ||
3558 | dpll4_m2x2_ck = dpll4_m2x2_ck_3630; | ||
3559 | dpll4_m3x2_ck = dpll4_m3x2_ck_3630; | ||
3560 | dpll4_m4x2_ck = dpll4_m4x2_ck_3630; | ||
3561 | dpll4_m5x2_ck = dpll4_m5x2_ck_3630; | ||
3562 | dpll4_m6x2_ck = dpll4_m6x2_ck_3630; | ||
3563 | } | ||
3564 | |||
3565 | /* | ||
3566 | * XXX This type of dynamic rewriting of the clock tree is | ||
3567 | * deprecated and should be revised soon. | ||
3568 | */ | ||
3569 | if (cpu_is_omap3630()) | ||
3570 | dpll4_dd = dpll4_dd_3630; | ||
3571 | else | ||
3572 | dpll4_dd = dpll4_dd_34xx; | ||
3573 | |||
3574 | for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); | ||
3575 | c++) | ||
3576 | if (c->cpu & cpu_clkflg) { | ||
3577 | clkdev_add(&c->lk); | ||
3578 | if (!__clk_init(NULL, c->lk.clk)) | ||
3579 | omap2_init_clk_hw_omap_clocks(c->lk.clk); | ||
3580 | } | ||
3581 | |||
3582 | omap2_clk_disable_autoidle_all(); | ||
3583 | 3628 | ||
3584 | omap2_clk_enable_init_clocks(enable_init_clks, | 3629 | omap2_clk_enable_init_clocks(enable_init_clks, |
3585 | ARRAY_SIZE(enable_init_clks)); | 3630 | ARRAY_SIZE(enable_init_clks)); |
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c index 0c6834ae1fc4..88e37a474334 100644 --- a/arch/arm/mach-omap2/cclock44xx_data.c +++ b/arch/arm/mach-omap2/cclock44xx_data.c | |||
@@ -1424,284 +1424,285 @@ DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0, | |||
1424 | 0x0, NULL); | 1424 | 0x0, NULL); |
1425 | 1425 | ||
1426 | /* | 1426 | /* |
1427 | * clkdev | 1427 | * clocks specific to omap4460 |
1428 | */ | 1428 | */ |
1429 | static struct omap_clk omap446x_clks[] = { | ||
1430 | CLK(NULL, "div_ts_ck", &div_ts_ck), | ||
1431 | CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk), | ||
1432 | }; | ||
1433 | |||
1434 | /* | ||
1435 | * clocks specific to omap4430 | ||
1436 | */ | ||
1437 | static struct omap_clk omap443x_clks[] = { | ||
1438 | CLK(NULL, "bandgap_fclk", &bandgap_fclk), | ||
1439 | }; | ||
1429 | 1440 | ||
1441 | /* | ||
1442 | * clocks common to omap44xx | ||
1443 | */ | ||
1430 | static struct omap_clk omap44xx_clks[] = { | 1444 | static struct omap_clk omap44xx_clks[] = { |
1431 | CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), | 1445 | CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck), |
1432 | CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck, CK_443X), | 1446 | CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck), |
1433 | CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), | 1447 | CLK(NULL, "pad_clks_ck", &pad_clks_ck), |
1434 | CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), | 1448 | CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck), |
1435 | CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), | 1449 | CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck), |
1436 | CLK(NULL, "slimbus_src_clk", &slimbus_src_clk, CK_443X), | 1450 | CLK(NULL, "slimbus_src_clk", &slimbus_src_clk), |
1437 | CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), | 1451 | CLK(NULL, "slimbus_clk", &slimbus_clk), |
1438 | CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), | 1452 | CLK(NULL, "sys_32k_ck", &sys_32k_ck), |
1439 | CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), | 1453 | CLK(NULL, "virt_12000000_ck", &virt_12000000_ck), |
1440 | CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), | 1454 | CLK(NULL, "virt_13000000_ck", &virt_13000000_ck), |
1441 | CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), | 1455 | CLK(NULL, "virt_16800000_ck", &virt_16800000_ck), |
1442 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), | 1456 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), |
1443 | CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), | 1457 | CLK(NULL, "virt_26000000_ck", &virt_26000000_ck), |
1444 | CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), | 1458 | CLK(NULL, "virt_27000000_ck", &virt_27000000_ck), |
1445 | CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), | 1459 | CLK(NULL, "virt_38400000_ck", &virt_38400000_ck), |
1446 | CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), | 1460 | CLK(NULL, "sys_clkin_ck", &sys_clkin_ck), |
1447 | CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), | 1461 | CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck), |
1448 | CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), | 1462 | CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck), |
1449 | CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), | 1463 | CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck), |
1450 | CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), | 1464 | CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck), |
1451 | CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), | 1465 | CLK(NULL, "xclk60motg_ck", &xclk60motg_ck), |
1452 | CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), | 1466 | CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck), |
1453 | CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), | 1467 | CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck), |
1454 | CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), | 1468 | CLK(NULL, "dpll_abe_ck", &dpll_abe_ck), |
1455 | CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), | 1469 | CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck), |
1456 | CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), | 1470 | CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck), |
1457 | CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), | 1471 | CLK(NULL, "abe_24m_fclk", &abe_24m_fclk), |
1458 | CLK(NULL, "abe_clk", &abe_clk, CK_443X), | 1472 | CLK(NULL, "abe_clk", &abe_clk), |
1459 | CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), | 1473 | CLK(NULL, "aess_fclk", &aess_fclk), |
1460 | CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), | 1474 | CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck), |
1461 | CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), | 1475 | CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck), |
1462 | CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), | 1476 | CLK(NULL, "dpll_core_ck", &dpll_core_ck), |
1463 | CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), | 1477 | CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck), |
1464 | CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), | 1478 | CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck), |
1465 | CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), | 1479 | CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck), |
1466 | CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), | 1480 | CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck), |
1467 | CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), | 1481 | CLK(NULL, "ddrphy_ck", &ddrphy_ck), |
1468 | CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), | 1482 | CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck), |
1469 | CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), | 1483 | CLK(NULL, "div_core_ck", &div_core_ck), |
1470 | CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), | 1484 | CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk), |
1471 | CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), | 1485 | CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk), |
1472 | CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), | 1486 | CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck), |
1473 | CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), | 1487 | CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck), |
1474 | CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), | 1488 | CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck), |
1475 | CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), | 1489 | CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck), |
1476 | CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), | 1490 | CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck), |
1477 | CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), | 1491 | CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck), |
1478 | CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), | 1492 | CLK(NULL, "dpll_iva_ck", &dpll_iva_ck), |
1479 | CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), | 1493 | CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck), |
1480 | CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), | 1494 | CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck), |
1481 | CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), | 1495 | CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck), |
1482 | CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), | 1496 | CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck), |
1483 | CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), | 1497 | CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck), |
1484 | CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), | 1498 | CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck), |
1485 | CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), | 1499 | CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck), |
1486 | CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), | 1500 | CLK(NULL, "dpll_per_ck", &dpll_per_ck), |
1487 | CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), | 1501 | CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck), |
1488 | CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), | 1502 | CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck), |
1489 | CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), | 1503 | CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck), |
1490 | CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), | 1504 | CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck), |
1491 | CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), | 1505 | CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck), |
1492 | CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), | 1506 | CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck), |
1493 | CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), | 1507 | CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck), |
1494 | CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), | 1508 | CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck), |
1495 | CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), | 1509 | CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck), |
1496 | CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), | 1510 | CLK(NULL, "dpll_usb_ck", &dpll_usb_ck), |
1497 | CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), | 1511 | CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck), |
1498 | CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), | 1512 | CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck), |
1499 | CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), | 1513 | CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck), |
1500 | CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), | 1514 | CLK(NULL, "func_12m_fclk", &func_12m_fclk), |
1501 | CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), | 1515 | CLK(NULL, "func_24m_clk", &func_24m_clk), |
1502 | CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), | 1516 | CLK(NULL, "func_24mc_fclk", &func_24mc_fclk), |
1503 | CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), | 1517 | CLK(NULL, "func_48m_fclk", &func_48m_fclk), |
1504 | CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), | 1518 | CLK(NULL, "func_48mc_fclk", &func_48mc_fclk), |
1505 | CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), | 1519 | CLK(NULL, "func_64m_fclk", &func_64m_fclk), |
1506 | CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), | 1520 | CLK(NULL, "func_96m_fclk", &func_96m_fclk), |
1507 | CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), | 1521 | CLK(NULL, "init_60m_fclk", &init_60m_fclk), |
1508 | CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), | 1522 | CLK(NULL, "l3_div_ck", &l3_div_ck), |
1509 | CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), | 1523 | CLK(NULL, "l4_div_ck", &l4_div_ck), |
1510 | CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), | 1524 | CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck), |
1511 | CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), | 1525 | CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck), |
1512 | CLK("smp_twd", NULL, &mpu_periphclk, CK_443X), | 1526 | CLK("smp_twd", NULL, &mpu_periphclk), |
1513 | CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), | 1527 | CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk), |
1514 | CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), | 1528 | CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk), |
1515 | CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), | 1529 | CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk), |
1516 | CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), | 1530 | CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck), |
1517 | CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), | 1531 | CLK(NULL, "aes1_fck", &aes1_fck), |
1518 | CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), | 1532 | CLK(NULL, "aes2_fck", &aes2_fck), |
1519 | CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), | 1533 | CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck), |
1520 | CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), | 1534 | CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk), |
1521 | CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), | 1535 | CLK(NULL, "dss_sys_clk", &dss_sys_clk), |
1522 | CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), | 1536 | CLK(NULL, "dss_tv_clk", &dss_tv_clk), |
1523 | CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk, CK_443X), | 1537 | CLK(NULL, "dss_dss_clk", &dss_dss_clk), |
1524 | CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), | 1538 | CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk), |
1525 | CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), | 1539 | CLK(NULL, "dss_fck", &dss_fck), |
1526 | CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), | 1540 | CLK("omapdss_dss", "ick", &dss_fck), |
1527 | CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), | 1541 | CLK(NULL, "fdif_fck", &fdif_fck), |
1528 | CLK(NULL, "dss_fck", &dss_fck, CK_443X), | 1542 | CLK(NULL, "gpio1_dbclk", &gpio1_dbclk), |
1529 | CLK("omapdss_dss", "ick", &dss_fck, CK_443X), | 1543 | CLK(NULL, "gpio2_dbclk", &gpio2_dbclk), |
1530 | CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), | 1544 | CLK(NULL, "gpio3_dbclk", &gpio3_dbclk), |
1531 | CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), | 1545 | CLK(NULL, "gpio4_dbclk", &gpio4_dbclk), |
1532 | CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), | 1546 | CLK(NULL, "gpio5_dbclk", &gpio5_dbclk), |
1533 | CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), | 1547 | CLK(NULL, "gpio6_dbclk", &gpio6_dbclk), |
1534 | CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), | 1548 | CLK(NULL, "sgx_clk_mux", &sgx_clk_mux), |
1535 | CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), | 1549 | CLK(NULL, "hsi_fck", &hsi_fck), |
1536 | CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), | 1550 | CLK(NULL, "iss_ctrlclk", &iss_ctrlclk), |
1537 | CLK(NULL, "sgx_clk_mux", &sgx_clk_mux, CK_443X), | 1551 | CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck), |
1538 | CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), | 1552 | CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk), |
1539 | CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), | 1553 | CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck), |
1540 | CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), | 1554 | CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk), |
1541 | CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk, CK_443X), | 1555 | CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck), |
1542 | CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), | 1556 | CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk), |
1543 | CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk, CK_443X), | 1557 | CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck), |
1544 | CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), | 1558 | CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk), |
1545 | CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk, CK_443X), | 1559 | CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck), |
1546 | CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), | 1560 | CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk), |
1547 | CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk, CK_443X), | 1561 | CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk), |
1548 | CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), | 1562 | CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk), |
1549 | CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X), | 1563 | CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m), |
1550 | CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X), | 1564 | CLK(NULL, "sha2md5_fck", &sha2md5_fck), |
1551 | CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X), | 1565 | CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1), |
1552 | CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), | 1566 | CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0), |
1553 | CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), | 1567 | CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2), |
1554 | CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), | 1568 | CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk), |
1555 | CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), | 1569 | CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1), |
1556 | CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), | 1570 | CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0), |
1557 | CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), | 1571 | CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk), |
1558 | CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), | 1572 | CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck), |
1559 | CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), | 1573 | CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck), |
1560 | CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), | 1574 | CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck), |
1561 | CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), | 1575 | CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux), |
1562 | CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), | 1576 | CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux), |
1563 | CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), | 1577 | CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux), |
1564 | CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux, CK_443X), | 1578 | CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux), |
1565 | CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux, CK_443X), | 1579 | CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux), |
1566 | CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux, CK_443X), | 1580 | CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux), |
1567 | CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux, CK_443X), | 1581 | CLK(NULL, "timer5_sync_mux", &timer5_sync_mux), |
1568 | CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux, CK_443X), | 1582 | CLK(NULL, "timer6_sync_mux", &timer6_sync_mux), |
1569 | CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux, CK_443X), | 1583 | CLK(NULL, "timer7_sync_mux", &timer7_sync_mux), |
1570 | CLK(NULL, "timer5_sync_mux", &timer5_sync_mux, CK_443X), | 1584 | CLK(NULL, "timer8_sync_mux", &timer8_sync_mux), |
1571 | CLK(NULL, "timer6_sync_mux", &timer6_sync_mux, CK_443X), | 1585 | CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux), |
1572 | CLK(NULL, "timer7_sync_mux", &timer7_sync_mux, CK_443X), | 1586 | CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck), |
1573 | CLK(NULL, "timer8_sync_mux", &timer8_sync_mux, CK_443X), | 1587 | CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck), |
1574 | CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux, CK_443X), | 1588 | CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk), |
1575 | CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), | 1589 | CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk), |
1576 | CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), | 1590 | CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk), |
1577 | CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), | 1591 | CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk), |
1578 | CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), | 1592 | CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk), |
1579 | CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), | 1593 | CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk), |
1580 | CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), | 1594 | CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk), |
1581 | CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), | 1595 | CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk), |
1582 | CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), | 1596 | CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk), |
1583 | CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), | 1597 | CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk), |
1584 | CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), | 1598 | CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck), |
1585 | CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), | 1599 | CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck), |
1586 | CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), | 1600 | CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk), |
1587 | CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), | 1601 | CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk), |
1588 | CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X), | 1602 | CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick), |
1589 | CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), | 1603 | CLK("musb-omap2430", "ick", &usb_otg_hs_ick), |
1590 | CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), | 1604 | CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k), |
1591 | CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X), | 1605 | CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk), |
1592 | CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), | 1606 | CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk), |
1593 | CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), | 1607 | CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk), |
1594 | CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), | 1608 | CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick), |
1595 | CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), | 1609 | CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick), |
1596 | CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), | 1610 | CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick), |
1597 | CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), | 1611 | CLK(NULL, "usim_ck", &usim_ck), |
1598 | CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X), | 1612 | CLK(NULL, "usim_fclk", &usim_fclk), |
1599 | CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), | 1613 | CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck), |
1600 | CLK(NULL, "usim_ck", &usim_ck, CK_443X), | 1614 | CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck), |
1601 | CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), | 1615 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck), |
1602 | CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), | 1616 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck), |
1603 | CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), | 1617 | CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck), |
1604 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), | 1618 | CLK(NULL, "auxclk0_ck", &auxclk0_ck), |
1605 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), | 1619 | CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck), |
1606 | CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X), | 1620 | CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck), |
1607 | CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), | 1621 | CLK(NULL, "auxclk1_ck", &auxclk1_ck), |
1608 | CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), | 1622 | CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck), |
1609 | CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X), | 1623 | CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck), |
1610 | CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), | 1624 | CLK(NULL, "auxclk2_ck", &auxclk2_ck), |
1611 | CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), | 1625 | CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck), |
1612 | CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X), | 1626 | CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck), |
1613 | CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), | 1627 | CLK(NULL, "auxclk3_ck", &auxclk3_ck), |
1614 | CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), | 1628 | CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck), |
1615 | CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X), | 1629 | CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck), |
1616 | CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), | 1630 | CLK(NULL, "auxclk4_ck", &auxclk4_ck), |
1617 | CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), | 1631 | CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck), |
1618 | CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X), | 1632 | CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck), |
1619 | CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), | 1633 | CLK(NULL, "auxclk5_ck", &auxclk5_ck), |
1620 | CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), | 1634 | CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck), |
1621 | CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X), | 1635 | CLK("omap-gpmc", "fck", &dummy_ck), |
1622 | CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), | 1636 | CLK("omap_i2c.1", "ick", &dummy_ck), |
1623 | CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), | 1637 | CLK("omap_i2c.2", "ick", &dummy_ck), |
1624 | CLK("omap-gpmc", "fck", &dummy_ck, CK_443X), | 1638 | CLK("omap_i2c.3", "ick", &dummy_ck), |
1625 | CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), | 1639 | CLK("omap_i2c.4", "ick", &dummy_ck), |
1626 | CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), | 1640 | CLK(NULL, "mailboxes_ick", &dummy_ck), |
1627 | CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), | 1641 | CLK("omap_hsmmc.0", "ick", &dummy_ck), |
1628 | CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), | 1642 | CLK("omap_hsmmc.1", "ick", &dummy_ck), |
1629 | CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), | 1643 | CLK("omap_hsmmc.2", "ick", &dummy_ck), |
1630 | CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), | 1644 | CLK("omap_hsmmc.3", "ick", &dummy_ck), |
1631 | CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), | 1645 | CLK("omap_hsmmc.4", "ick", &dummy_ck), |
1632 | CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), | 1646 | CLK("omap-mcbsp.1", "ick", &dummy_ck), |
1633 | CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), | 1647 | CLK("omap-mcbsp.2", "ick", &dummy_ck), |
1634 | CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), | 1648 | CLK("omap-mcbsp.3", "ick", &dummy_ck), |
1635 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), | 1649 | CLK("omap-mcbsp.4", "ick", &dummy_ck), |
1636 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), | 1650 | CLK("omap2_mcspi.1", "ick", &dummy_ck), |
1637 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), | 1651 | CLK("omap2_mcspi.2", "ick", &dummy_ck), |
1638 | CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), | 1652 | CLK("omap2_mcspi.3", "ick", &dummy_ck), |
1639 | CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), | 1653 | CLK("omap2_mcspi.4", "ick", &dummy_ck), |
1640 | CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), | 1654 | CLK(NULL, "uart1_ick", &dummy_ck), |
1641 | CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), | 1655 | CLK(NULL, "uart2_ick", &dummy_ck), |
1642 | CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), | 1656 | CLK(NULL, "uart3_ick", &dummy_ck), |
1643 | CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), | 1657 | CLK(NULL, "uart4_ick", &dummy_ck), |
1644 | CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), | 1658 | CLK("usbhs_omap", "usbhost_ick", &dummy_ck), |
1645 | CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), | 1659 | CLK("usbhs_omap", "usbtll_fck", &dummy_ck), |
1646 | CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), | 1660 | CLK("usbhs_tll", "usbtll_fck", &dummy_ck), |
1647 | CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), | 1661 | CLK("omap_wdt", "ick", &dummy_ck), |
1648 | CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), | 1662 | CLK(NULL, "timer_32k_ck", &sys_32k_ck), |
1649 | CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X), | ||
1650 | CLK("omap_wdt", "ick", &dummy_ck, CK_443X), | ||
1651 | CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X), | ||
1652 | /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ | 1663 | /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ |
1653 | CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X), | 1664 | CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck), |
1654 | CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X), | 1665 | CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck), |
1655 | CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X), | 1666 | CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck), |
1656 | CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X), | 1667 | CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck), |
1657 | CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X), | 1668 | CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck), |
1658 | CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X), | 1669 | CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck), |
1659 | CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X), | 1670 | CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck), |
1660 | CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | 1671 | CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck), |
1661 | CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | 1672 | CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck), |
1662 | CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | 1673 | CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck), |
1663 | CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | 1674 | CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck), |
1664 | CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | 1675 | CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck), |
1665 | CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | 1676 | CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck), |
1666 | CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | 1677 | CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck), |
1667 | CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | 1678 | CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck), |
1668 | CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | 1679 | CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck), |
1669 | CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | 1680 | CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck), |
1670 | CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | 1681 | CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck), |
1671 | CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | 1682 | CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck), |
1672 | CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | 1683 | CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck), |
1673 | CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | 1684 | CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck), |
1674 | CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | 1685 | CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck), |
1675 | CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), | 1686 | CLK(NULL, "cpufreq_ck", &dpll_mpu_ck), |
1676 | }; | 1687 | }; |
1677 | 1688 | ||
1678 | int __init omap4xxx_clk_init(void) | 1689 | int __init omap4xxx_clk_init(void) |
1679 | { | 1690 | { |
1680 | u32 cpu_clkflg; | ||
1681 | struct omap_clk *c; | ||
1682 | int rc; | 1691 | int rc; |
1683 | 1692 | ||
1684 | if (cpu_is_omap443x()) { | 1693 | if (cpu_is_omap443x()) { |
1685 | cpu_mask = RATE_IN_4430; | 1694 | cpu_mask = RATE_IN_4430; |
1686 | cpu_clkflg = CK_443X; | 1695 | omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks)); |
1687 | } else if (cpu_is_omap446x() || cpu_is_omap447x()) { | 1696 | } else if (cpu_is_omap446x() || cpu_is_omap447x()) { |
1688 | cpu_mask = RATE_IN_4460 | RATE_IN_4430; | 1697 | cpu_mask = RATE_IN_4460 | RATE_IN_4430; |
1689 | cpu_clkflg = CK_446X | CK_443X; | 1698 | omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks)); |
1690 | |||
1691 | if (cpu_is_omap447x()) | 1699 | if (cpu_is_omap447x()) |
1692 | pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); | 1700 | pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); |
1693 | } else { | 1701 | } else { |
1694 | return 0; | 1702 | return 0; |
1695 | } | 1703 | } |
1696 | 1704 | ||
1697 | for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); | 1705 | omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks)); |
1698 | c++) { | ||
1699 | if (c->cpu & cpu_clkflg) { | ||
1700 | clkdev_add(&c->lk); | ||
1701 | if (!__clk_init(NULL, c->lk.clk)) | ||
1702 | omap2_init_clk_hw_omap_clocks(c->lk.clk); | ||
1703 | } | ||
1704 | } | ||
1705 | 1706 | ||
1706 | omap2_clk_disable_autoidle_all(); | 1707 | omap2_clk_disable_autoidle_all(); |
1707 | 1708 | ||
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index e4ec3a69ee2e..8474c7d228ee 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
@@ -23,7 +23,7 @@ | |||
23 | #include <linux/clk-provider.h> | 23 | #include <linux/clk-provider.h> |
24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
25 | #include <linux/bitops.h> | 25 | #include <linux/bitops.h> |
26 | 26 | #include <linux/clk-private.h> | |
27 | #include <asm/cpu.h> | 27 | #include <asm/cpu.h> |
28 | 28 | ||
29 | 29 | ||
@@ -569,6 +569,21 @@ const struct clk_hw_omap_ops clkhwops_wait = { | |||
569 | }; | 569 | }; |
570 | 570 | ||
571 | /** | 571 | /** |
572 | * omap_clocks_register - register an array of omap_clk | ||
573 | * @ocs: pointer to an array of omap_clk to register | ||
574 | */ | ||
575 | void __init omap_clocks_register(struct omap_clk oclks[], int cnt) | ||
576 | { | ||
577 | struct omap_clk *c; | ||
578 | |||
579 | for (c = oclks; c < oclks + cnt; c++) { | ||
580 | clkdev_add(&c->lk); | ||
581 | if (!__clk_init(NULL, c->lk.clk)) | ||
582 | omap2_init_clk_hw_omap_clocks(c->lk.clk); | ||
583 | } | ||
584 | } | ||
585 | |||
586 | /** | ||
572 | * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument | 587 | * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument |
573 | * @mpurate_ck_name: clk name of the clock to change rate | 588 | * @mpurate_ck_name: clk name of the clock to change rate |
574 | * | 589 | * |
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 60ddd8612b4d..7aa32cd292f9 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h | |||
@@ -27,9 +27,8 @@ struct omap_clk { | |||
27 | struct clk_lookup lk; | 27 | struct clk_lookup lk; |
28 | }; | 28 | }; |
29 | 29 | ||
30 | #define CLK(dev, con, ck, cp) \ | 30 | #define CLK(dev, con, ck) \ |
31 | { \ | 31 | { \ |
32 | .cpu = cp, \ | ||
33 | .lk = { \ | 32 | .lk = { \ |
34 | .dev_id = dev, \ | 33 | .dev_id = dev, \ |
35 | .con_id = con, \ | 34 | .con_id = con, \ |
@@ -37,22 +36,6 @@ struct omap_clk { | |||
37 | }, \ | 36 | }, \ |
38 | } | 37 | } |
39 | 38 | ||
40 | /* Platform flags for the clkdev-OMAP integration code */ | ||
41 | #define CK_242X (1 << 0) | ||
42 | #define CK_243X (1 << 1) /* 243x, 253x */ | ||
43 | #define CK_3430ES1 (1 << 2) /* 34xxES1 only */ | ||
44 | #define CK_3430ES2PLUS (1 << 3) /* 34xxES2, ES3, non-Sitara 35xx only */ | ||
45 | #define CK_AM35XX (1 << 4) /* Sitara AM35xx */ | ||
46 | #define CK_36XX (1 << 5) /* 36xx/37xx-specific clocks */ | ||
47 | #define CK_443X (1 << 6) | ||
48 | #define CK_TI816X (1 << 7) | ||
49 | #define CK_446X (1 << 8) | ||
50 | #define CK_AM33XX (1 << 9) /* AM33xx specific clocks */ | ||
51 | |||
52 | |||
53 | #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) | ||
54 | #define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) | ||
55 | |||
56 | struct clockdomain; | 39 | struct clockdomain; |
57 | #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) | 40 | #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) |
58 | 41 | ||
@@ -480,4 +463,5 @@ extern int am33xx_clk_init(void); | |||
480 | extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); | 463 | extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); |
481 | extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); | 464 | extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); |
482 | 465 | ||
466 | extern void omap_clocks_register(struct omap_clk *oclks, int cnt); | ||
483 | #endif | 467 | #endif |
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index cca045c95fbf..e18709d3b95d 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c | |||
@@ -112,8 +112,6 @@ static int omap3_enter_idle(struct cpuidle_device *dev, | |||
112 | { | 112 | { |
113 | struct omap3_idle_statedata *cx = &omap3_idle_data[index]; | 113 | struct omap3_idle_statedata *cx = &omap3_idle_data[index]; |
114 | 114 | ||
115 | local_fiq_disable(); | ||
116 | |||
117 | if (omap_irq_pending() || need_resched()) | 115 | if (omap_irq_pending() || need_resched()) |
118 | goto return_sleep_time; | 116 | goto return_sleep_time; |
119 | 117 | ||
@@ -148,7 +146,6 @@ static int omap3_enter_idle(struct cpuidle_device *dev, | |||
148 | clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]); | 146 | clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]); |
149 | 147 | ||
150 | return_sleep_time: | 148 | return_sleep_time: |
151 | local_fiq_enable(); | ||
152 | 149 | ||
153 | return index; | 150 | return index; |
154 | } | 151 | } |
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c index 5a286b56205e..c443f2e97e10 100644 --- a/arch/arm/mach-omap2/cpuidle44xx.c +++ b/arch/arm/mach-omap2/cpuidle44xx.c | |||
@@ -71,10 +71,7 @@ static int omap_enter_idle_simple(struct cpuidle_device *dev, | |||
71 | struct cpuidle_driver *drv, | 71 | struct cpuidle_driver *drv, |
72 | int index) | 72 | int index) |
73 | { | 73 | { |
74 | local_fiq_disable(); | ||
75 | omap_do_wfi(); | 74 | omap_do_wfi(); |
76 | local_fiq_enable(); | ||
77 | |||
78 | return index; | 75 | return index; |
79 | } | 76 | } |
80 | 77 | ||
@@ -84,8 +81,6 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, | |||
84 | { | 81 | { |
85 | struct idle_statedata *cx = state_ptr + index; | 82 | struct idle_statedata *cx = state_ptr + index; |
86 | 83 | ||
87 | local_fiq_disable(); | ||
88 | |||
89 | /* | 84 | /* |
90 | * CPU0 has to wait and stay ON until CPU1 is OFF state. | 85 | * CPU0 has to wait and stay ON until CPU1 is OFF state. |
91 | * This is necessary to honour hardware recommondation | 86 | * This is necessary to honour hardware recommondation |
@@ -134,6 +129,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, | |||
134 | /* Wakeup CPU1 only if it is not offlined */ | 129 | /* Wakeup CPU1 only if it is not offlined */ |
135 | if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) { | 130 | if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) { |
136 | clkdm_wakeup(cpu_clkdm[1]); | 131 | clkdm_wakeup(cpu_clkdm[1]); |
132 | omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON); | ||
137 | clkdm_allow_idle(cpu_clkdm[1]); | 133 | clkdm_allow_idle(cpu_clkdm[1]); |
138 | } | 134 | } |
139 | 135 | ||
@@ -155,8 +151,6 @@ fail: | |||
155 | cpuidle_coupled_parallel_barrier(dev, &abort_barrier); | 151 | cpuidle_coupled_parallel_barrier(dev, &abort_barrier); |
156 | cpu_done[dev->cpu] = false; | 152 | cpu_done[dev->cpu] = false; |
157 | 153 | ||
158 | local_fiq_enable(); | ||
159 | |||
160 | return index; | 154 | return index; |
161 | } | 155 | } |
162 | 156 | ||
diff --git a/arch/arm/mach-omap2/dma.h b/arch/arm/mach-omap2/dma.h index eba80dbc5218..65f80cacf178 100644 --- a/arch/arm/mach-omap2/dma.h +++ b/arch/arm/mach-omap2/dma.h | |||
@@ -22,69 +22,20 @@ | |||
22 | 22 | ||
23 | /* DMA channels for 24xx */ | 23 | /* DMA channels for 24xx */ |
24 | #define OMAP24XX_DMA_NO_DEVICE 0 | 24 | #define OMAP24XX_DMA_NO_DEVICE 0 |
25 | #define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */ | ||
26 | #define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */ | 25 | #define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */ |
27 | #define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */ | 26 | #define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */ |
28 | #define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ | 27 | #define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ |
29 | #define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ | ||
30 | #define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ | ||
31 | #define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */ | ||
32 | #define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */ | ||
33 | #define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */ | ||
34 | #define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ | 28 | #define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ |
35 | #define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ | 29 | #define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ |
36 | #define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ | ||
37 | #define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ | ||
38 | #define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ | ||
39 | #define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */ | ||
40 | #define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ | 30 | #define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ |
41 | #define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ | 31 | #define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ |
42 | #define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ | 32 | #define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ |
43 | #define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */ | ||
44 | #define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */ | ||
45 | #define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ | ||
46 | #define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */ | ||
47 | #define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */ | ||
48 | #define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */ | ||
49 | #define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */ | ||
50 | #define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */ | ||
51 | #define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */ | ||
52 | #define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */ | ||
53 | #define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */ | ||
54 | #define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */ | ||
55 | #define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */ | ||
56 | #define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */ | ||
57 | #define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */ | ||
58 | #define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */ | ||
59 | #define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */ | ||
60 | #define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */ | ||
61 | #define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */ | ||
62 | #define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */ | ||
63 | #define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */ | ||
64 | #define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */ | ||
65 | #define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */ | ||
66 | #define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */ | 33 | #define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */ |
67 | #define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */ | 34 | #define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */ |
68 | #define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ | 35 | #define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ |
69 | #define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ | 36 | #define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ |
70 | #define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ | 37 | #define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ |
71 | #define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ | 38 | #define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ |
72 | #define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */ | ||
73 | #define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */ | ||
74 | #define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */ | ||
75 | #define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */ | ||
76 | #define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */ | ||
77 | #define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */ | ||
78 | #define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */ | ||
79 | #define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */ | ||
80 | #define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */ | ||
81 | #define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */ | ||
82 | #define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */ | ||
83 | #define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */ | ||
84 | #define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */ | ||
85 | #define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */ | ||
86 | #define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */ | ||
87 | #define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */ | ||
88 | #define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */ | 39 | #define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */ |
89 | #define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */ | 40 | #define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */ |
90 | #define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */ | 41 | #define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */ |
@@ -93,33 +44,12 @@ | |||
93 | #define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */ | 44 | #define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */ |
94 | #define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */ | 45 | #define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */ |
95 | #define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */ | 46 | #define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */ |
96 | #define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */ | ||
97 | #define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */ | ||
98 | #define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */ | ||
99 | #define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */ | ||
100 | #define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */ | ||
101 | #define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */ | ||
102 | #define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */ | 47 | #define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */ |
103 | #define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */ | 48 | #define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */ |
104 | #define OMAP24XX_DMA_MS 63 /* S_DMA_62 */ | ||
105 | #define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ | 49 | #define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ |
106 | #define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */ | ||
107 | #define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */ | ||
108 | #define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */ | 50 | #define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */ |
109 | #define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */ | 51 | #define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */ |
110 | #define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */ | ||
111 | #define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */ | ||
112 | #define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */ | 52 | #define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */ |
113 | #define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */ | ||
114 | #define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */ | ||
115 | #define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */ | ||
116 | #define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */ | ||
117 | #define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */ | ||
118 | #define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */ | ||
119 | #define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */ | ||
120 | #define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */ | ||
121 | #define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ | ||
122 | #define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ | ||
123 | 53 | ||
124 | #define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */ | 54 | #define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */ |
125 | #define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */ | 55 | #define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */ |
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c index e712d1725a8b..458f72f9dc8f 100644 --- a/arch/arm/mach-omap2/omap-hotplug.c +++ b/arch/arm/mach-omap2/omap-hotplug.c | |||
@@ -19,11 +19,8 @@ | |||
19 | #include <linux/smp.h> | 19 | #include <linux/smp.h> |
20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
21 | 21 | ||
22 | #include <asm/cacheflush.h> | ||
23 | #include "omap-wakeupgen.h" | 22 | #include "omap-wakeupgen.h" |
24 | |||
25 | #include "common.h" | 23 | #include "common.h" |
26 | |||
27 | #include "powerdomain.h" | 24 | #include "powerdomain.h" |
28 | 25 | ||
29 | /* | 26 | /* |
@@ -35,9 +32,6 @@ void __ref omap4_cpu_die(unsigned int cpu) | |||
35 | unsigned int boot_cpu = 0; | 32 | unsigned int boot_cpu = 0; |
36 | void __iomem *base = omap_get_wakeupgen_base(); | 33 | void __iomem *base = omap_get_wakeupgen_base(); |
37 | 34 | ||
38 | flush_cache_all(); | ||
39 | dsb(); | ||
40 | |||
41 | /* | 35 | /* |
42 | * we're ready for shutdown now, so do it | 36 | * we're ready for shutdown now, so do it |
43 | */ | 37 | */ |
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index d9727218dd0a..61174b78dee6 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c | |||
@@ -21,7 +21,6 @@ | |||
21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
22 | #include <linux/irqchip/arm-gic.h> | 22 | #include <linux/irqchip/arm-gic.h> |
23 | 23 | ||
24 | #include <asm/cacheflush.h> | ||
25 | #include <asm/smp_scu.h> | 24 | #include <asm/smp_scu.h> |
26 | 25 | ||
27 | #include "omap-secure.h" | 26 | #include "omap-secure.h" |
@@ -67,13 +66,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu) | |||
67 | 4, 0, 0, 0, 0, 0); | 66 | 4, 0, 0, 0, 0, 0); |
68 | 67 | ||
69 | /* | 68 | /* |
70 | * If any interrupts are already enabled for the primary | ||
71 | * core (e.g. timer irq), then they will not have been enabled | ||
72 | * for us: do so | ||
73 | */ | ||
74 | gic_secondary_init(0); | ||
75 | |||
76 | /* | ||
77 | * Synchronise with the boot thread. | 69 | * Synchronise with the boot thread. |
78 | */ | 70 | */ |
79 | spin_lock(&boot_lock); | 71 | spin_lock(&boot_lock); |
@@ -84,6 +76,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * | |||
84 | { | 76 | { |
85 | static struct clockdomain *cpu1_clkdm; | 77 | static struct clockdomain *cpu1_clkdm; |
86 | static bool booted; | 78 | static bool booted; |
79 | static struct powerdomain *cpu1_pwrdm; | ||
87 | void __iomem *base = omap_get_wakeupgen_base(); | 80 | void __iomem *base = omap_get_wakeupgen_base(); |
88 | 81 | ||
89 | /* | 82 | /* |
@@ -103,11 +96,10 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * | |||
103 | else | 96 | else |
104 | __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0); | 97 | __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0); |
105 | 98 | ||
106 | flush_cache_all(); | 99 | if (!cpu1_clkdm && !cpu1_pwrdm) { |
107 | smp_wmb(); | ||
108 | |||
109 | if (!cpu1_clkdm) | ||
110 | cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); | 100 | cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); |
101 | cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm"); | ||
102 | } | ||
111 | 103 | ||
112 | /* | 104 | /* |
113 | * The SGI(Software Generated Interrupts) are not wakeup capable | 105 | * The SGI(Software Generated Interrupts) are not wakeup capable |
@@ -120,7 +112,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * | |||
120 | * Section : | 112 | * Section : |
121 | * 4.3.4.2 Power States of CPU0 and CPU1 | 113 | * 4.3.4.2 Power States of CPU0 and CPU1 |
122 | */ | 114 | */ |
123 | if (booted) { | 115 | if (booted && cpu1_pwrdm && cpu1_clkdm) { |
124 | /* | 116 | /* |
125 | * GIC distributor control register has changed between | 117 | * GIC distributor control register has changed between |
126 | * CortexA9 r1pX and r2pX. The Control Register secure | 118 | * CortexA9 r1pX and r2pX. The Control Register secure |
@@ -141,7 +133,12 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * | |||
141 | gic_dist_disable(); | 133 | gic_dist_disable(); |
142 | } | 134 | } |
143 | 135 | ||
136 | /* | ||
137 | * Ensure that CPU power state is set to ON to avoid CPU | ||
138 | * powerdomain transition on wfi | ||
139 | */ | ||
144 | clkdm_wakeup(cpu1_clkdm); | 140 | clkdm_wakeup(cpu1_clkdm); |
141 | omap_set_pwrdm_state(cpu1_pwrdm, PWRDM_POWER_ON); | ||
145 | clkdm_allow_idle(cpu1_clkdm); | 142 | clkdm_allow_idle(cpu1_clkdm); |
146 | 143 | ||
147 | if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) { | 144 | if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) { |
@@ -168,38 +165,6 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * | |||
168 | return 0; | 165 | return 0; |
169 | } | 166 | } |
170 | 167 | ||
171 | static void __init wakeup_secondary(void) | ||
172 | { | ||
173 | void *startup_addr = omap_secondary_startup; | ||
174 | void __iomem *base = omap_get_wakeupgen_base(); | ||
175 | |||
176 | if (cpu_is_omap446x()) { | ||
177 | startup_addr = omap_secondary_startup_4460; | ||
178 | pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; | ||
179 | } | ||
180 | |||
181 | /* | ||
182 | * Write the address of secondary startup routine into the | ||
183 | * AuxCoreBoot1 where ROM code will jump and start executing | ||
184 | * on secondary core once out of WFE | ||
185 | * A barrier is added to ensure that write buffer is drained | ||
186 | */ | ||
187 | if (omap_secure_apis_support()) | ||
188 | omap_auxcoreboot_addr(virt_to_phys(startup_addr)); | ||
189 | else | ||
190 | __raw_writel(virt_to_phys(omap5_secondary_startup), | ||
191 | base + OMAP_AUX_CORE_BOOT_1); | ||
192 | |||
193 | smp_wmb(); | ||
194 | |||
195 | /* | ||
196 | * Send a 'sev' to wake the secondary core from WFE. | ||
197 | * Drain the outstanding writes to memory | ||
198 | */ | ||
199 | dsb_sev(); | ||
200 | mb(); | ||
201 | } | ||
202 | |||
203 | /* | 168 | /* |
204 | * Initialise the CPU possible map early - this describes the CPUs | 169 | * Initialise the CPU possible map early - this describes the CPUs |
205 | * which may be present or become present in the system. | 170 | * which may be present or become present in the system. |
@@ -235,6 +200,8 @@ static void __init omap4_smp_init_cpus(void) | |||
235 | 200 | ||
236 | static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) | 201 | static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) |
237 | { | 202 | { |
203 | void *startup_addr = omap_secondary_startup; | ||
204 | void __iomem *base = omap_get_wakeupgen_base(); | ||
238 | 205 | ||
239 | /* | 206 | /* |
240 | * Initialise the SCU and wake up the secondary core using | 207 | * Initialise the SCU and wake up the secondary core using |
@@ -242,7 +209,24 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) | |||
242 | */ | 209 | */ |
243 | if (scu_base) | 210 | if (scu_base) |
244 | scu_enable(scu_base); | 211 | scu_enable(scu_base); |
245 | wakeup_secondary(); | 212 | |
213 | if (cpu_is_omap446x()) { | ||
214 | startup_addr = omap_secondary_startup_4460; | ||
215 | pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; | ||
216 | } | ||
217 | |||
218 | /* | ||
219 | * Write the address of secondary startup routine into the | ||
220 | * AuxCoreBoot1 where ROM code will jump and start executing | ||
221 | * on secondary core once out of WFE | ||
222 | * A barrier is added to ensure that write buffer is drained | ||
223 | */ | ||
224 | if (omap_secure_apis_support()) | ||
225 | omap_auxcoreboot_addr(virt_to_phys(startup_addr)); | ||
226 | else | ||
227 | __raw_writel(virt_to_phys(omap5_secondary_startup), | ||
228 | base + OMAP_AUX_CORE_BOOT_1); | ||
229 | |||
246 | } | 230 | } |
247 | 231 | ||
248 | struct smp_operations omap4_smp_ops __initdata = { | 232 | struct smp_operations omap4_smp_ops __initdata = { |
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 2aeb928efdfd..13b27ffaf45e 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <linux/of_platform.h> | 22 | #include <linux/of_platform.h> |
23 | #include <linux/export.h> | 23 | #include <linux/export.h> |
24 | #include <linux/irqchip/arm-gic.h> | 24 | #include <linux/irqchip/arm-gic.h> |
25 | #include <linux/of_address.h> | ||
25 | 26 | ||
26 | #include <asm/hardware/cache-l2x0.h> | 27 | #include <asm/hardware/cache-l2x0.h> |
27 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
@@ -264,6 +265,21 @@ omap_early_initcall(omap4_sar_ram_init); | |||
264 | 265 | ||
265 | void __init omap_gic_of_init(void) | 266 | void __init omap_gic_of_init(void) |
266 | { | 267 | { |
268 | struct device_node *np; | ||
269 | |||
270 | /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */ | ||
271 | if (!cpu_is_omap446x()) | ||
272 | goto skip_errata_init; | ||
273 | |||
274 | np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); | ||
275 | gic_dist_base_addr = of_iomap(np, 0); | ||
276 | WARN_ON(!gic_dist_base_addr); | ||
277 | |||
278 | np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer"); | ||
279 | twd_base = of_iomap(np, 0); | ||
280 | WARN_ON(!twd_base); | ||
281 | |||
282 | skip_errata_init: | ||
267 | omap_wakeupgen_init(); | 283 | omap_wakeupgen_init(); |
268 | irqchip_init(); | 284 | irqchip_init(); |
269 | } | 285 | } |
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h index 937417523b8e..792b1069f724 100644 --- a/arch/arm/mach-omap2/omap4-sar-layout.h +++ b/arch/arm/mach-omap2/omap4-sar-layout.h | |||
@@ -20,13 +20,13 @@ | |||
20 | #define SAR_BANK4_OFFSET 0x3000 | 20 | #define SAR_BANK4_OFFSET 0x3000 |
21 | 21 | ||
22 | /* Scratch pad memory offsets from SAR_BANK1 */ | 22 | /* Scratch pad memory offsets from SAR_BANK1 */ |
23 | #define SCU_OFFSET0 0xd00 | 23 | #define SCU_OFFSET0 0xfe4 |
24 | #define SCU_OFFSET1 0xd04 | 24 | #define SCU_OFFSET1 0xfe8 |
25 | #define OMAP_TYPE_OFFSET 0xd10 | 25 | #define OMAP_TYPE_OFFSET 0xfec |
26 | #define L2X0_SAVE_OFFSET0 0xd14 | 26 | #define L2X0_SAVE_OFFSET0 0xff0 |
27 | #define L2X0_SAVE_OFFSET1 0xd18 | 27 | #define L2X0_SAVE_OFFSET1 0xff4 |
28 | #define L2X0_AUXCTRL_OFFSET 0xd1c | 28 | #define L2X0_AUXCTRL_OFFSET 0xff8 |
29 | #define L2X0_PREFETCH_CTRL_OFFSET 0xd20 | 29 | #define L2X0_PREFETCH_CTRL_OFFSET 0xffc |
30 | 30 | ||
31 | /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */ | 31 | /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */ |
32 | #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04 | 32 | #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04 |
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index b59d93908341..ce956b0a7ba4 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c | |||
@@ -200,22 +200,17 @@ static int omap2_can_sleep(void) | |||
200 | 200 | ||
201 | static void omap2_pm_idle(void) | 201 | static void omap2_pm_idle(void) |
202 | { | 202 | { |
203 | local_fiq_disable(); | ||
204 | |||
205 | if (!omap2_can_sleep()) { | 203 | if (!omap2_can_sleep()) { |
206 | if (omap_irq_pending()) | 204 | if (omap_irq_pending()) |
207 | goto out; | 205 | return; |
208 | omap2_enter_mpu_retention(); | 206 | omap2_enter_mpu_retention(); |
209 | goto out; | 207 | return; |
210 | } | 208 | } |
211 | 209 | ||
212 | if (omap_irq_pending()) | 210 | if (omap_irq_pending()) |
213 | goto out; | 211 | return; |
214 | 212 | ||
215 | omap2_enter_full_retention(); | 213 | omap2_enter_full_retention(); |
216 | |||
217 | out: | ||
218 | local_fiq_enable(); | ||
219 | } | 214 | } |
220 | 215 | ||
221 | static void __init prcm_setup_regs(void) | 216 | static void __init prcm_setup_regs(void) |
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 2d93d8b23835..c01859398b54 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c | |||
@@ -346,19 +346,14 @@ void omap_sram_idle(void) | |||
346 | 346 | ||
347 | static void omap3_pm_idle(void) | 347 | static void omap3_pm_idle(void) |
348 | { | 348 | { |
349 | local_fiq_disable(); | ||
350 | |||
351 | if (omap_irq_pending()) | 349 | if (omap_irq_pending()) |
352 | goto out; | 350 | return; |
353 | 351 | ||
354 | trace_cpu_idle(1, smp_processor_id()); | 352 | trace_cpu_idle(1, smp_processor_id()); |
355 | 353 | ||
356 | omap_sram_idle(); | 354 | omap_sram_idle(); |
357 | 355 | ||
358 | trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); | 356 | trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); |
359 | |||
360 | out: | ||
361 | local_fiq_enable(); | ||
362 | } | 357 | } |
363 | 358 | ||
364 | #ifdef CONFIG_SUSPEND | 359 | #ifdef CONFIG_SUSPEND |
@@ -757,14 +752,12 @@ int __init omap3_pm_init(void) | |||
757 | pr_err("Memory allocation failed when allocating for secure sram context\n"); | 752 | pr_err("Memory allocation failed when allocating for secure sram context\n"); |
758 | 753 | ||
759 | local_irq_disable(); | 754 | local_irq_disable(); |
760 | local_fiq_disable(); | ||
761 | 755 | ||
762 | omap_dma_global_context_save(); | 756 | omap_dma_global_context_save(); |
763 | omap3_save_secure_ram_context(); | 757 | omap3_save_secure_ram_context(); |
764 | omap_dma_global_context_restore(); | 758 | omap_dma_global_context_restore(); |
765 | 759 | ||
766 | local_irq_enable(); | 760 | local_irq_enable(); |
767 | local_fiq_enable(); | ||
768 | } | 761 | } |
769 | 762 | ||
770 | omap3_save_scratchpad_contents(); | 763 | omap3_save_scratchpad_contents(); |
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index 152a10cf4f1d..a251f87fa2a2 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c | |||
@@ -131,11 +131,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) | |||
131 | */ | 131 | */ |
132 | static void omap_default_idle(void) | 132 | static void omap_default_idle(void) |
133 | { | 133 | { |
134 | local_fiq_disable(); | ||
135 | |||
136 | omap_do_wfi(); | 134 | omap_do_wfi(); |
137 | |||
138 | local_fiq_enable(); | ||
139 | } | 135 | } |
140 | 136 | ||
141 | /** | 137 | /** |
@@ -147,8 +143,8 @@ static void omap_default_idle(void) | |||
147 | int __init omap4_pm_init(void) | 143 | int __init omap4_pm_init(void) |
148 | { | 144 | { |
149 | int ret; | 145 | int ret; |
150 | struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup; | 146 | struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm; |
151 | struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm; | 147 | struct clockdomain *ducati_clkdm, *l3_2_clkdm; |
152 | 148 | ||
153 | if (omap_rev() == OMAP4430_REV_ES1_0) { | 149 | if (omap_rev() == OMAP4430_REV_ES1_0) { |
154 | WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); | 150 | WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); |
@@ -175,27 +171,19 @@ int __init omap4_pm_init(void) | |||
175 | * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as | 171 | * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as |
176 | * expected. The hardware recommendation is to enable static | 172 | * expected. The hardware recommendation is to enable static |
177 | * dependencies for these to avoid system lock ups or random crashes. | 173 | * dependencies for these to avoid system lock ups or random crashes. |
178 | * The L4 wakeup depedency is added to workaround the OCP sync hardware | ||
179 | * BUG with 32K synctimer which lead to incorrect timer value read | ||
180 | * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which | ||
181 | * are part of L4 wakeup clockdomain. | ||
182 | */ | 174 | */ |
183 | mpuss_clkdm = clkdm_lookup("mpuss_clkdm"); | 175 | mpuss_clkdm = clkdm_lookup("mpuss_clkdm"); |
184 | emif_clkdm = clkdm_lookup("l3_emif_clkdm"); | 176 | emif_clkdm = clkdm_lookup("l3_emif_clkdm"); |
185 | l3_1_clkdm = clkdm_lookup("l3_1_clkdm"); | 177 | l3_1_clkdm = clkdm_lookup("l3_1_clkdm"); |
186 | l3_2_clkdm = clkdm_lookup("l3_2_clkdm"); | 178 | l3_2_clkdm = clkdm_lookup("l3_2_clkdm"); |
187 | l4_per_clkdm = clkdm_lookup("l4_per_clkdm"); | ||
188 | l4wkup = clkdm_lookup("l4_wkup_clkdm"); | ||
189 | ducati_clkdm = clkdm_lookup("ducati_clkdm"); | 179 | ducati_clkdm = clkdm_lookup("ducati_clkdm"); |
190 | if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || (!l4wkup) || | 180 | if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || |
191 | (!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm)) | 181 | (!l3_2_clkdm) || (!ducati_clkdm)) |
192 | goto err2; | 182 | goto err2; |
193 | 183 | ||
194 | ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm); | 184 | ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm); |
195 | ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm); | 185 | ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm); |
196 | ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm); | 186 | ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm); |
197 | ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm); | ||
198 | ret |= clkdm_add_wkdep(mpuss_clkdm, l4wkup); | ||
199 | ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm); | 187 | ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm); |
200 | ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm); | 188 | ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm); |
201 | if (ret) { | 189 | if (ret) { |
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index d00d89c93f1c..ea6ea9aab092 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c | |||
@@ -602,7 +602,7 @@ void __init omap4_local_timer_init(void) | |||
602 | int err; | 602 | int err; |
603 | 603 | ||
604 | if (of_have_populated_dt()) { | 604 | if (of_have_populated_dt()) { |
605 | twd_local_timer_of_register(); | 605 | clocksource_of_init(); |
606 | return; | 606 | return; |
607 | } | 607 | } |
608 | 608 | ||
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index d9c7c3bf0d9c..973db98a3c27 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c | |||
@@ -402,8 +402,9 @@ static void __init orion5x_pci_master_slave_enable(void) | |||
402 | orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); | 402 | orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); |
403 | } | 403 | } |
404 | 404 | ||
405 | static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) | 405 | static void __init orion5x_setup_pci_wins(void) |
406 | { | 406 | { |
407 | const struct mbus_dram_target_info *dram = mv_mbus_dram_info(); | ||
407 | u32 win_enable; | 408 | u32 win_enable; |
408 | int bus; | 409 | int bus; |
409 | int i; | 410 | int i; |
@@ -420,7 +421,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) | |||
420 | bus = orion5x_pci_local_bus_nr(); | 421 | bus = orion5x_pci_local_bus_nr(); |
421 | 422 | ||
422 | for (i = 0; i < dram->num_cs; i++) { | 423 | for (i = 0; i < dram->num_cs; i++) { |
423 | struct mbus_dram_window *cs = dram->cs + i; | 424 | const struct mbus_dram_window *cs = dram->cs + i; |
424 | u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); | 425 | u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); |
425 | u32 reg; | 426 | u32 reg; |
426 | u32 val; | 427 | u32 val; |
@@ -467,7 +468,7 @@ static int __init pci_setup(struct pci_sys_data *sys) | |||
467 | /* | 468 | /* |
468 | * Point PCI unit MBUS decode windows to DRAM space. | 469 | * Point PCI unit MBUS decode windows to DRAM space. |
469 | */ | 470 | */ |
470 | orion5x_setup_pci_wins(&orion_mbus_dram_info); | 471 | orion5x_setup_pci_wins(); |
471 | 472 | ||
472 | /* | 473 | /* |
473 | * Master + Slave enable | 474 | * Master + Slave enable |
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c index 4b788310f6a6..c7c92e78f0cf 100644 --- a/arch/arm/mach-prima2/platsmp.c +++ b/arch/arm/mach-prima2/platsmp.c | |||
@@ -11,7 +11,6 @@ | |||
11 | #include <linux/delay.h> | 11 | #include <linux/delay.h> |
12 | #include <linux/of.h> | 12 | #include <linux/of.h> |
13 | #include <linux/of_address.h> | 13 | #include <linux/of_address.h> |
14 | #include <linux/irqchip/arm-gic.h> | ||
15 | #include <asm/page.h> | 14 | #include <asm/page.h> |
16 | #include <asm/mach/map.h> | 15 | #include <asm/mach/map.h> |
17 | #include <asm/smp_plat.h> | 16 | #include <asm/smp_plat.h> |
@@ -49,13 +48,6 @@ void __init sirfsoc_map_scu(void) | |||
49 | static void __cpuinit sirfsoc_secondary_init(unsigned int cpu) | 48 | static void __cpuinit sirfsoc_secondary_init(unsigned int cpu) |
50 | { | 49 | { |
51 | /* | 50 | /* |
52 | * if any interrupts are already enabled for the primary | ||
53 | * core (e.g. timer irq), then they will not have been enabled | ||
54 | * for us: do so | ||
55 | */ | ||
56 | gic_secondary_init(0); | ||
57 | |||
58 | /* | ||
59 | * let the primary processor know we're out of the | 51 | * let the primary processor know we're out of the |
60 | * pen, then head off into the C entry point | 52 | * pen, then head off into the C entry point |
61 | */ | 53 | */ |
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index 37f513d1588e..8d5fa6ece014 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig | |||
@@ -36,7 +36,6 @@ config CPU_S3C2410 | |||
36 | 36 | ||
37 | config CPU_S3C2412 | 37 | config CPU_S3C2412 |
38 | bool "SAMSUNG S3C2412" | 38 | bool "SAMSUNG S3C2412" |
39 | depends on ARCH_S3C24XX | ||
40 | select CPU_ARM926T | 39 | select CPU_ARM926T |
41 | select CPU_LLSERIAL_S3C2440 | 40 | select CPU_LLSERIAL_S3C2440 |
42 | select S3C2412_DMA if S3C24XX_DMA | 41 | select S3C2412_DMA if S3C24XX_DMA |
@@ -46,7 +45,6 @@ config CPU_S3C2412 | |||
46 | 45 | ||
47 | config CPU_S3C2416 | 46 | config CPU_S3C2416 |
48 | bool "SAMSUNG S3C2416/S3C2450" | 47 | bool "SAMSUNG S3C2416/S3C2450" |
49 | depends on ARCH_S3C24XX | ||
50 | select CPU_ARM926T | 48 | select CPU_ARM926T |
51 | select CPU_LLSERIAL_S3C2440 | 49 | select CPU_LLSERIAL_S3C2440 |
52 | select S3C2416_PM if PM | 50 | select S3C2416_PM if PM |
@@ -81,7 +79,6 @@ config CPU_S3C244X | |||
81 | 79 | ||
82 | config CPU_S3C2443 | 80 | config CPU_S3C2443 |
83 | bool "SAMSUNG S3C2443" | 81 | bool "SAMSUNG S3C2443" |
84 | depends on ARCH_S3C24XX | ||
85 | select CPU_ARM920T | 82 | select CPU_ARM920T |
86 | select CPU_LLSERIAL_S3C2440 | 83 | select CPU_LLSERIAL_S3C2440 |
87 | select S3C2443_COMMON | 84 | select S3C2443_COMMON |
@@ -133,7 +130,6 @@ config S3C24XX_SETUP_TS | |||
133 | 130 | ||
134 | config S3C24XX_DMA | 131 | config S3C24XX_DMA |
135 | bool "S3C2410 DMA support" | 132 | bool "S3C2410 DMA support" |
136 | depends on ARCH_S3C24XX | ||
137 | select S3C_DMA | 133 | select S3C_DMA |
138 | help | 134 | help |
139 | S3C2410 DMA support. This is needed for drivers like sound which | 135 | S3C2410 DMA support. This is needed for drivers like sound which |
@@ -142,7 +138,7 @@ config S3C24XX_DMA | |||
142 | 138 | ||
143 | config S3C2410_DMA_DEBUG | 139 | config S3C2410_DMA_DEBUG |
144 | bool "S3C2410 DMA support debug" | 140 | bool "S3C2410 DMA support debug" |
145 | depends on ARCH_S3C24XX && S3C2410_DMA | 141 | depends on S3C2410_DMA |
146 | help | 142 | help |
147 | Enable debugging output for the DMA code. This option sends info | 143 | Enable debugging output for the DMA code. This option sends info |
148 | to the kernel log, at priority KERN_DEBUG. | 144 | to the kernel log, at priority KERN_DEBUG. |
@@ -233,7 +229,7 @@ if CPU_S3C2410 | |||
233 | 229 | ||
234 | config S3C2410_CPUFREQ | 230 | config S3C2410_CPUFREQ |
235 | bool | 231 | bool |
236 | depends on CPU_FREQ_S3C24XX && CPU_S3C2410 | 232 | depends on CPU_FREQ_S3C24XX |
237 | select S3C2410_CPUFREQ_UTILS | 233 | select S3C2410_CPUFREQ_UTILS |
238 | help | 234 | help |
239 | CPU Frequency scaling support for S3C2410 | 235 | CPU Frequency scaling support for S3C2410 |
@@ -320,7 +316,6 @@ config PM_H1940 | |||
320 | 316 | ||
321 | config MACH_N30 | 317 | config MACH_N30 |
322 | bool "Acer N30 family" | 318 | bool "Acer N30 family" |
323 | select MACH_N35 | ||
324 | select S3C_DEV_NAND | 319 | select S3C_DEV_NAND |
325 | select S3C_DEV_USB_HOST | 320 | select S3C_DEV_USB_HOST |
326 | help | 321 | help |
@@ -380,14 +375,13 @@ if CPU_S3C2412 | |||
380 | 375 | ||
381 | config CPU_S3C2412_ONLY | 376 | config CPU_S3C2412_ONLY |
382 | bool | 377 | bool |
383 | depends on ARCH_S3C24XX && !CPU_S3C2410 && \ | 378 | depends on !CPU_S3C2410 && !CPU_S3C2416 && !CPU_S3C2440 && \ |
384 | !CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \ | 379 | !CPU_S3C2442 && !CPU_S3C2443 |
385 | !CPU_S3C2443 && CPU_S3C2412 | ||
386 | default y | 380 | default y |
387 | 381 | ||
388 | config S3C2412_CPUFREQ | 382 | config S3C2412_CPUFREQ |
389 | bool | 383 | bool |
390 | depends on CPU_FREQ_S3C24XX && CPU_S3C2412 | 384 | depends on CPU_FREQ_S3C24XX |
391 | default y | 385 | default y |
392 | select S3C2412_IOTIMING | 386 | select S3C2412_IOTIMING |
393 | help | 387 | help |
@@ -642,7 +636,6 @@ comment "S3C2442 Boards" | |||
642 | config MACH_NEO1973_GTA02 | 636 | config MACH_NEO1973_GTA02 |
643 | bool "Openmoko GTA02 / Freerunner phone" | 637 | bool "Openmoko GTA02 / Freerunner phone" |
644 | select I2C | 638 | select I2C |
645 | select MACH_NEO1973 | ||
646 | select MFD_PCF50633 | 639 | select MFD_PCF50633 |
647 | select PCF50633_GPIO | 640 | select PCF50633_GPIO |
648 | select POWER_SUPPLY | 641 | select POWER_SUPPLY |
@@ -663,10 +656,7 @@ config MACH_RX1950 | |||
663 | help | 656 | help |
664 | Say Y here if you're using HP iPAQ rx1950 | 657 | Say Y here if you're using HP iPAQ rx1950 |
665 | 658 | ||
666 | config SMDK2440_CPU2442 | 659 | endif # CPU_S3C2442 |
667 | bool "SMDM2440 with S3C2442 CPU module" | ||
668 | |||
669 | endif # CPU_S3C2440 | ||
670 | 660 | ||
671 | if CPU_S3C2443 || CPU_S3C2416 | 661 | if CPU_S3C2443 || CPU_S3C2416 |
672 | 662 | ||
diff --git a/arch/arm/mach-s3c24xx/bast-irq.c b/arch/arm/mach-s3c24xx/bast-irq.c index c0daa9590b4c..cb1b791954de 100644 --- a/arch/arm/mach-s3c24xx/bast-irq.c +++ b/arch/arm/mach-s3c24xx/bast-irq.c | |||
@@ -34,8 +34,6 @@ | |||
34 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
35 | #include <mach/regs-irq.h> | 35 | #include <mach/regs-irq.h> |
36 | 36 | ||
37 | #include <plat/irq.h> | ||
38 | |||
39 | #include "bast.h" | 37 | #include "bast.h" |
40 | 38 | ||
41 | #define irqdbf(x...) | 39 | #define irqdbf(x...) |
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2410.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c index 641266f3d152..34fffdf6fc1d 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2410.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2410.c | |||
@@ -40,7 +40,6 @@ | |||
40 | #include <mach/regs-clock.h> | 40 | #include <mach/regs-clock.h> |
41 | #include <mach/regs-gpio.h> | 41 | #include <mach/regs-gpio.h> |
42 | 42 | ||
43 | #include <plat/s3c2410.h> | ||
44 | #include <plat/clock.h> | 43 | #include <plat/clock.h> |
45 | #include <plat/cpu.h> | 44 | #include <plat/cpu.h> |
46 | 45 | ||
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c index d10b695a9066..2cc017da88fe 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2412.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2412.c | |||
@@ -41,7 +41,6 @@ | |||
41 | #include <mach/regs-clock.h> | 41 | #include <mach/regs-clock.h> |
42 | #include <mach/regs-gpio.h> | 42 | #include <mach/regs-gpio.h> |
43 | 43 | ||
44 | #include <plat/s3c2412.h> | ||
45 | #include <plat/clock.h> | 44 | #include <plat/clock.h> |
46 | #include <plat/cpu.h> | 45 | #include <plat/cpu.h> |
47 | 46 | ||
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c index 14a81c2317a4..036056cea57c 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2416.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c | |||
@@ -14,7 +14,6 @@ | |||
14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
15 | #include <linux/clk.h> | 15 | #include <linux/clk.h> |
16 | 16 | ||
17 | #include <plat/s3c2416.h> | ||
18 | #include <plat/clock.h> | 17 | #include <plat/clock.h> |
19 | #include <plat/clock-clksrc.h> | 18 | #include <plat/clock-clksrc.h> |
20 | #include <plat/cpu.h> | 19 | #include <plat/cpu.h> |
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c index bdaba59b42dc..0a53051b0787 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2443.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c | |||
@@ -41,7 +41,6 @@ | |||
41 | 41 | ||
42 | #include <plat/cpu-freq.h> | 42 | #include <plat/cpu-freq.h> |
43 | 43 | ||
44 | #include <plat/s3c2443.h> | ||
45 | #include <plat/clock.h> | 44 | #include <plat/clock.h> |
46 | #include <plat/clock-clksrc.h> | 45 | #include <plat/clock-clksrc.h> |
47 | #include <plat/cpu.h> | 46 | #include <plat/cpu.h> |
diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c index 3b2cf6db3634..404444dd3840 100644 --- a/arch/arm/mach-s3c24xx/common-smdk.c +++ b/arch/arm/mach-s3c24xx/common-smdk.c | |||
@@ -41,11 +41,12 @@ | |||
41 | 41 | ||
42 | #include <linux/platform_data/mtd-nand-s3c2410.h> | 42 | #include <linux/platform_data/mtd-nand-s3c2410.h> |
43 | 43 | ||
44 | #include <plat/common-smdk.h> | ||
45 | #include <plat/gpio-cfg.h> | 44 | #include <plat/gpio-cfg.h> |
46 | #include <plat/devs.h> | 45 | #include <plat/devs.h> |
47 | #include <plat/pm.h> | 46 | #include <plat/pm.h> |
48 | 47 | ||
48 | #include "common-smdk.h" | ||
49 | |||
49 | /* LED devices */ | 50 | /* LED devices */ |
50 | 51 | ||
51 | static struct s3c24xx_led_platdata smdk_pdata_led4 = { | 52 | static struct s3c24xx_led_platdata smdk_pdata_led4 = { |
diff --git a/arch/arm/plat-samsung/include/plat/common-smdk.h b/arch/arm/mach-s3c24xx/common-smdk.h index ba028f1ed30b..98f733e1cb42 100644 --- a/arch/arm/plat-samsung/include/plat/common-smdk.h +++ b/arch/arm/mach-s3c24xx/common-smdk.h | |||
@@ -1,5 +1,4 @@ | |||
1 | /* linux/arch/arm/plat-samsung/include/plat/common-smdk.h | 1 | /* |
2 | * | ||
3 | * Copyright (c) 2006 Simtec Electronics | 2 | * Copyright (c) 2006 Simtec Electronics |
4 | * Ben Dooks <ben@simtec.co.uk> | 3 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | 4 | * |
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c index 92e609440c57..c157103ed8eb 100644 --- a/arch/arm/mach-s3c24xx/common.c +++ b/arch/arm/mach-s3c24xx/common.c | |||
@@ -47,14 +47,11 @@ | |||
47 | #include <plat/cpu.h> | 47 | #include <plat/cpu.h> |
48 | #include <plat/devs.h> | 48 | #include <plat/devs.h> |
49 | #include <plat/clock.h> | 49 | #include <plat/clock.h> |
50 | #include <plat/s3c2410.h> | ||
51 | #include <plat/s3c2412.h> | ||
52 | #include <plat/s3c2416.h> | ||
53 | #include <plat/s3c244x.h> | ||
54 | #include <plat/s3c2443.h> | ||
55 | #include <plat/cpu-freq.h> | 50 | #include <plat/cpu-freq.h> |
56 | #include <plat/pll.h> | 51 | #include <plat/pll.h> |
57 | 52 | ||
53 | #include "common.h" | ||
54 | |||
58 | /* table of supported CPUs */ | 55 | /* table of supported CPUs */ |
59 | 56 | ||
60 | static const char name_s3c2410[] = "S3C2410"; | 57 | static const char name_s3c2410[] = "S3C2410"; |
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h index ed6276fcaa3b..8a2b4137ddb6 100644 --- a/arch/arm/mach-s3c24xx/common.h +++ b/arch/arm/mach-s3c24xx/common.h | |||
@@ -12,8 +12,94 @@ | |||
12 | #ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H | 12 | #ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H |
13 | #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__ | 13 | #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__ |
14 | 14 | ||
15 | void s3c2410_restart(char mode, const char *cmd); | 15 | struct s3c2410_uartcfg; |
16 | void s3c244x_restart(char mode, const char *cmd); | 16 | |
17 | #ifdef CONFIG_CPU_S3C2410 | ||
18 | extern int s3c2410_init(void); | ||
19 | extern int s3c2410a_init(void); | ||
20 | extern void s3c2410_map_io(void); | ||
21 | extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
22 | extern void s3c2410_init_clocks(int xtal); | ||
23 | extern void s3c2410_restart(char mode, const char *cmd); | ||
24 | #else | ||
25 | #define s3c2410_init_clocks NULL | ||
26 | #define s3c2410_init_uarts NULL | ||
27 | #define s3c2410_map_io NULL | ||
28 | #define s3c2410_init NULL | ||
29 | #define s3c2410a_init NULL | ||
30 | #endif | ||
31 | |||
32 | #ifdef CONFIG_CPU_S3C2412 | ||
33 | extern int s3c2412_init(void); | ||
34 | extern void s3c2412_map_io(void); | ||
35 | extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
36 | extern void s3c2412_init_clocks(int xtal); | ||
37 | extern int s3c2412_baseclk_add(void); | ||
38 | extern void s3c2412_restart(char mode, const char *cmd); | ||
39 | #else | ||
40 | #define s3c2412_init_clocks NULL | ||
41 | #define s3c2412_init_uarts NULL | ||
42 | #define s3c2412_map_io NULL | ||
43 | #define s3c2412_init NULL | ||
44 | #endif | ||
45 | |||
46 | #ifdef CONFIG_CPU_S3C2416 | ||
47 | extern int s3c2416_init(void); | ||
48 | extern void s3c2416_map_io(void); | ||
49 | extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
50 | extern void s3c2416_init_clocks(int xtal); | ||
51 | extern int s3c2416_baseclk_add(void); | ||
52 | extern void s3c2416_restart(char mode, const char *cmd); | ||
53 | extern void s3c2416_init_irq(void); | ||
54 | |||
55 | extern struct syscore_ops s3c2416_irq_syscore_ops; | ||
56 | #else | ||
57 | #define s3c2416_init_clocks NULL | ||
58 | #define s3c2416_init_uarts NULL | ||
59 | #define s3c2416_map_io NULL | ||
60 | #define s3c2416_init NULL | ||
61 | #endif | ||
62 | |||
63 | #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) | ||
64 | extern void s3c244x_map_io(void); | ||
65 | extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
66 | extern void s3c244x_init_clocks(int xtal); | ||
67 | extern void s3c244x_restart(char mode, const char *cmd); | ||
68 | #else | ||
69 | #define s3c244x_init_clocks NULL | ||
70 | #define s3c244x_init_uarts NULL | ||
71 | #endif | ||
72 | |||
73 | #ifdef CONFIG_CPU_S3C2440 | ||
74 | extern int s3c2440_init(void); | ||
75 | extern void s3c2440_map_io(void); | ||
76 | #else | ||
77 | #define s3c2440_init NULL | ||
78 | #define s3c2440_map_io NULL | ||
79 | #endif | ||
80 | |||
81 | #ifdef CONFIG_CPU_S3C2442 | ||
82 | extern int s3c2442_init(void); | ||
83 | extern void s3c2442_map_io(void); | ||
84 | #else | ||
85 | #define s3c2442_init NULL | ||
86 | #define s3c2442_map_io NULL | ||
87 | #endif | ||
88 | |||
89 | #ifdef CONFIG_CPU_S3C2443 | ||
90 | extern int s3c2443_init(void); | ||
91 | extern void s3c2443_map_io(void); | ||
92 | extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
93 | extern void s3c2443_init_clocks(int xtal); | ||
94 | extern int s3c2443_baseclk_add(void); | ||
95 | extern void s3c2443_restart(char mode, const char *cmd); | ||
96 | extern void s3c2443_init_irq(void); | ||
97 | #else | ||
98 | #define s3c2443_init_clocks NULL | ||
99 | #define s3c2443_init_uarts NULL | ||
100 | #define s3c2443_map_io NULL | ||
101 | #define s3c2443_init NULL | ||
102 | #endif | ||
17 | 103 | ||
18 | extern struct syscore_ops s3c24xx_irq_syscore_ops; | 104 | extern struct syscore_ops s3c24xx_irq_syscore_ops; |
19 | 105 | ||
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2410.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c index 25d085adc93c..a6c94b820954 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2410.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2410.c | |||
@@ -28,7 +28,6 @@ | |||
28 | #include <plat/regs-ac97.h> | 28 | #include <plat/regs-ac97.h> |
29 | #include <plat/regs-dma.h> | 29 | #include <plat/regs-dma.h> |
30 | #include <mach/regs-lcd.h> | 30 | #include <mach/regs-lcd.h> |
31 | #include <mach/regs-sdi.h> | ||
32 | #include <plat/regs-iis.h> | 31 | #include <plat/regs-iis.h> |
33 | #include <plat/regs-spi.h> | 32 | #include <plat/regs-spi.h> |
34 | 33 | ||
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c index d2408ba372cb..c0e8c3f5057e 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2412.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c | |||
@@ -28,7 +28,6 @@ | |||
28 | #include <plat/regs-ac97.h> | 28 | #include <plat/regs-ac97.h> |
29 | #include <plat/regs-dma.h> | 29 | #include <plat/regs-dma.h> |
30 | #include <mach/regs-lcd.h> | 30 | #include <mach/regs-lcd.h> |
31 | #include <mach/regs-sdi.h> | ||
32 | #include <plat/regs-iis.h> | 31 | #include <plat/regs-iis.h> |
33 | #include <plat/regs-spi.h> | 32 | #include <plat/regs-spi.h> |
34 | 33 | ||
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2440.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c index 0b86e74d104f..1c08eccd9425 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2440.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2440.c | |||
@@ -28,7 +28,6 @@ | |||
28 | #include <plat/regs-ac97.h> | 28 | #include <plat/regs-ac97.h> |
29 | #include <plat/regs-dma.h> | 29 | #include <plat/regs-dma.h> |
30 | #include <mach/regs-lcd.h> | 30 | #include <mach/regs-lcd.h> |
31 | #include <mach/regs-sdi.h> | ||
32 | #include <plat/regs-iis.h> | 31 | #include <plat/regs-iis.h> |
33 | #include <plat/regs-spi.h> | 32 | #include <plat/regs-spi.h> |
34 | 33 | ||
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c index 05536254a3f8..000e4c69fce9 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2443.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c | |||
@@ -28,7 +28,6 @@ | |||
28 | #include <plat/regs-ac97.h> | 28 | #include <plat/regs-ac97.h> |
29 | #include <plat/regs-dma.h> | 29 | #include <plat/regs-dma.h> |
30 | #include <mach/regs-lcd.h> | 30 | #include <mach/regs-lcd.h> |
31 | #include <mach/regs-sdi.h> | ||
32 | #include <plat/regs-iis.h> | 31 | #include <plat/regs-iis.h> |
33 | #include <plat/regs-spi.h> | 32 | #include <plat/regs-spi.h> |
34 | 33 | ||
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h index 6b72d5a4b377..b55da1d8cd8f 100644 --- a/arch/arm/mach-s3c24xx/include/mach/dma.h +++ b/arch/arm/mach-s3c24xx/include/mach/dma.h | |||
@@ -24,7 +24,6 @@ | |||
24 | */ | 24 | */ |
25 | 25 | ||
26 | enum dma_ch { | 26 | enum dma_ch { |
27 | DMACH_DT_PROP = -1, /* not yet supported, do not use */ | ||
28 | DMACH_XD0 = 0, | 27 | DMACH_XD0 = 0, |
29 | DMACH_XD1, | 28 | DMACH_XD1, |
30 | DMACH_SDI, | 29 | DMACH_SDI, |
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h b/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h deleted file mode 100644 index cbf2d8884e30..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h +++ /dev/null | |||
@@ -1,127 +0,0 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-sdi.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2410 MMC/SDIO register definitions | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARM_REGS_SDI | ||
14 | #define __ASM_ARM_REGS_SDI "regs-sdi.h" | ||
15 | |||
16 | #define S3C2410_SDICON (0x00) | ||
17 | #define S3C2410_SDIPRE (0x04) | ||
18 | #define S3C2410_SDICMDARG (0x08) | ||
19 | #define S3C2410_SDICMDCON (0x0C) | ||
20 | #define S3C2410_SDICMDSTAT (0x10) | ||
21 | #define S3C2410_SDIRSP0 (0x14) | ||
22 | #define S3C2410_SDIRSP1 (0x18) | ||
23 | #define S3C2410_SDIRSP2 (0x1C) | ||
24 | #define S3C2410_SDIRSP3 (0x20) | ||
25 | #define S3C2410_SDITIMER (0x24) | ||
26 | #define S3C2410_SDIBSIZE (0x28) | ||
27 | #define S3C2410_SDIDCON (0x2C) | ||
28 | #define S3C2410_SDIDCNT (0x30) | ||
29 | #define S3C2410_SDIDSTA (0x34) | ||
30 | #define S3C2410_SDIFSTA (0x38) | ||
31 | |||
32 | #define S3C2410_SDIDATA (0x3C) | ||
33 | #define S3C2410_SDIIMSK (0x40) | ||
34 | |||
35 | #define S3C2440_SDIDATA (0x40) | ||
36 | #define S3C2440_SDIIMSK (0x3C) | ||
37 | |||
38 | #define S3C2440_SDICON_SDRESET (1<<8) | ||
39 | #define S3C2440_SDICON_MMCCLOCK (1<<5) | ||
40 | #define S3C2410_SDICON_BYTEORDER (1<<4) | ||
41 | #define S3C2410_SDICON_SDIOIRQ (1<<3) | ||
42 | #define S3C2410_SDICON_RWAITEN (1<<2) | ||
43 | #define S3C2410_SDICON_FIFORESET (1<<1) | ||
44 | #define S3C2410_SDICON_CLOCKTYPE (1<<0) | ||
45 | |||
46 | #define S3C2410_SDICMDCON_ABORT (1<<12) | ||
47 | #define S3C2410_SDICMDCON_WITHDATA (1<<11) | ||
48 | #define S3C2410_SDICMDCON_LONGRSP (1<<10) | ||
49 | #define S3C2410_SDICMDCON_WAITRSP (1<<9) | ||
50 | #define S3C2410_SDICMDCON_CMDSTART (1<<8) | ||
51 | #define S3C2410_SDICMDCON_SENDERHOST (1<<6) | ||
52 | #define S3C2410_SDICMDCON_INDEX (0x3f) | ||
53 | |||
54 | #define S3C2410_SDICMDSTAT_CRCFAIL (1<<12) | ||
55 | #define S3C2410_SDICMDSTAT_CMDSENT (1<<11) | ||
56 | #define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10) | ||
57 | #define S3C2410_SDICMDSTAT_RSPFIN (1<<9) | ||
58 | #define S3C2410_SDICMDSTAT_XFERING (1<<8) | ||
59 | #define S3C2410_SDICMDSTAT_INDEX (0xff) | ||
60 | |||
61 | #define S3C2440_SDIDCON_DS_BYTE (0<<22) | ||
62 | #define S3C2440_SDIDCON_DS_HALFWORD (1<<22) | ||
63 | #define S3C2440_SDIDCON_DS_WORD (2<<22) | ||
64 | #define S3C2410_SDIDCON_IRQPERIOD (1<<21) | ||
65 | #define S3C2410_SDIDCON_TXAFTERRESP (1<<20) | ||
66 | #define S3C2410_SDIDCON_RXAFTERCMD (1<<19) | ||
67 | #define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18) | ||
68 | #define S3C2410_SDIDCON_BLOCKMODE (1<<17) | ||
69 | #define S3C2410_SDIDCON_WIDEBUS (1<<16) | ||
70 | #define S3C2410_SDIDCON_DMAEN (1<<15) | ||
71 | #define S3C2410_SDIDCON_STOP (1<<14) | ||
72 | #define S3C2440_SDIDCON_DATSTART (1<<14) | ||
73 | #define S3C2410_SDIDCON_DATMODE (3<<12) | ||
74 | #define S3C2410_SDIDCON_BLKNUM (0x7ff) | ||
75 | |||
76 | /* constants for S3C2410_SDIDCON_DATMODE */ | ||
77 | #define S3C2410_SDIDCON_XFER_READY (0<<12) | ||
78 | #define S3C2410_SDIDCON_XFER_CHKSTART (1<<12) | ||
79 | #define S3C2410_SDIDCON_XFER_RXSTART (2<<12) | ||
80 | #define S3C2410_SDIDCON_XFER_TXSTART (3<<12) | ||
81 | |||
82 | #define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF) | ||
83 | #define S3C2410_SDIDCNT_BLKNUM_SHIFT (12) | ||
84 | |||
85 | #define S3C2410_SDIDSTA_RDYWAITREQ (1<<10) | ||
86 | #define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9) | ||
87 | #define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */ | ||
88 | #define S3C2410_SDIDSTA_CRCFAIL (1<<7) | ||
89 | #define S3C2410_SDIDSTA_RXCRCFAIL (1<<6) | ||
90 | #define S3C2410_SDIDSTA_DATATIMEOUT (1<<5) | ||
91 | #define S3C2410_SDIDSTA_XFERFINISH (1<<4) | ||
92 | #define S3C2410_SDIDSTA_BUSYFINISH (1<<3) | ||
93 | #define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */ | ||
94 | #define S3C2410_SDIDSTA_TXDATAON (1<<1) | ||
95 | #define S3C2410_SDIDSTA_RXDATAON (1<<0) | ||
96 | |||
97 | #define S3C2440_SDIFSTA_FIFORESET (1<<16) | ||
98 | #define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */ | ||
99 | #define S3C2410_SDIFSTA_TFDET (1<<13) | ||
100 | #define S3C2410_SDIFSTA_RFDET (1<<12) | ||
101 | #define S3C2410_SDIFSTA_TFHALF (1<<11) | ||
102 | #define S3C2410_SDIFSTA_TFEMPTY (1<<10) | ||
103 | #define S3C2410_SDIFSTA_RFLAST (1<<9) | ||
104 | #define S3C2410_SDIFSTA_RFFULL (1<<8) | ||
105 | #define S3C2410_SDIFSTA_RFHALF (1<<7) | ||
106 | #define S3C2410_SDIFSTA_COUNTMASK (0x7f) | ||
107 | |||
108 | #define S3C2410_SDIIMSK_RESPONSECRC (1<<17) | ||
109 | #define S3C2410_SDIIMSK_CMDSENT (1<<16) | ||
110 | #define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15) | ||
111 | #define S3C2410_SDIIMSK_RESPONSEND (1<<14) | ||
112 | #define S3C2410_SDIIMSK_READWAIT (1<<13) | ||
113 | #define S3C2410_SDIIMSK_SDIOIRQ (1<<12) | ||
114 | #define S3C2410_SDIIMSK_FIFOFAIL (1<<11) | ||
115 | #define S3C2410_SDIIMSK_CRCSTATUS (1<<10) | ||
116 | #define S3C2410_SDIIMSK_DATACRC (1<<9) | ||
117 | #define S3C2410_SDIIMSK_DATATIMEOUT (1<<8) | ||
118 | #define S3C2410_SDIIMSK_DATAFINISH (1<<7) | ||
119 | #define S3C2410_SDIIMSK_BUSYFINISH (1<<6) | ||
120 | #define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */ | ||
121 | #define S3C2410_SDIIMSK_TXFIFOHALF (1<<4) | ||
122 | #define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3) | ||
123 | #define S3C2410_SDIIMSK_RXFIFOLAST (1<<2) | ||
124 | #define S3C2410_SDIIMSK_RXFIFOFULL (1<<1) | ||
125 | #define S3C2410_SDIIMSK_RXFIFOHALF (1<<0) | ||
126 | |||
127 | #endif /* __ASM_ARM_REGS_SDI */ | ||
diff --git a/arch/arm/mach-s3c24xx/irq-pm.c b/arch/arm/mach-s3c24xx/irq-pm.c index e1199599873e..b91341ef2b2e 100644 --- a/arch/arm/mach-s3c24xx/irq-pm.c +++ b/arch/arm/mach-s3c24xx/irq-pm.c | |||
@@ -16,10 +16,15 @@ | |||
16 | #include <linux/interrupt.h> | 16 | #include <linux/interrupt.h> |
17 | #include <linux/irq.h> | 17 | #include <linux/irq.h> |
18 | #include <linux/syscore_ops.h> | 18 | #include <linux/syscore_ops.h> |
19 | #include <linux/io.h> | ||
19 | 20 | ||
20 | #include <plat/cpu.h> | 21 | #include <plat/cpu.h> |
21 | #include <plat/pm.h> | 22 | #include <plat/pm.h> |
22 | #include <plat/irq.h> | 23 | #include <plat/map-base.h> |
24 | #include <plat/map-s3c.h> | ||
25 | |||
26 | #include <mach/regs-irq.h> | ||
27 | #include <mach/regs-gpio.h> | ||
23 | 28 | ||
24 | #include <asm/irq.h> | 29 | #include <asm/irq.h> |
25 | 30 | ||
diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c index d8ba9bee4c7e..b41c2cb7af4a 100644 --- a/arch/arm/mach-s3c24xx/irq.c +++ b/arch/arm/mach-s3c24xx/irq.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <linux/ioport.h> | 25 | #include <linux/ioport.h> |
26 | #include <linux/device.h> | 26 | #include <linux/device.h> |
27 | #include <linux/irqdomain.h> | 27 | #include <linux/irqdomain.h> |
28 | #include <linux/irqchip/chained_irq.h> | ||
28 | 29 | ||
29 | #include <asm/mach/irq.h> | 30 | #include <asm/mach/irq.h> |
30 | 31 | ||
@@ -34,7 +35,6 @@ | |||
34 | #include <plat/cpu.h> | 35 | #include <plat/cpu.h> |
35 | #include <plat/regs-irqtype.h> | 36 | #include <plat/regs-irqtype.h> |
36 | #include <plat/pm.h> | 37 | #include <plat/pm.h> |
37 | #include <plat/irq.h> | ||
38 | 38 | ||
39 | #define S3C_IRQTYPE_NONE 0 | 39 | #define S3C_IRQTYPE_NONE 0 |
40 | #define S3C_IRQTYPE_EINT 1 | 40 | #define S3C_IRQTYPE_EINT 1 |
@@ -175,8 +175,7 @@ static int s3c_irqext_type_set(void __iomem *gpcon_reg, | |||
175 | return 0; | 175 | return 0; |
176 | } | 176 | } |
177 | 177 | ||
178 | /* FIXME: make static when it's out of plat-samsung/irq.h */ | 178 | static int s3c_irqext_type(struct irq_data *data, unsigned int type) |
179 | int s3c_irqext_type(struct irq_data *data, unsigned int type) | ||
180 | { | 179 | { |
181 | void __iomem *extint_reg; | 180 | void __iomem *extint_reg; |
182 | void __iomem *gpcon_reg; | 181 | void __iomem *gpcon_reg; |
@@ -224,7 +223,7 @@ static int s3c_irqext0_type(struct irq_data *data, unsigned int type) | |||
224 | extint_offset, type); | 223 | extint_offset, type); |
225 | } | 224 | } |
226 | 225 | ||
227 | struct irq_chip s3c_irq_chip = { | 226 | static struct irq_chip s3c_irq_chip = { |
228 | .name = "s3c", | 227 | .name = "s3c", |
229 | .irq_ack = s3c_irq_ack, | 228 | .irq_ack = s3c_irq_ack, |
230 | .irq_mask = s3c_irq_mask, | 229 | .irq_mask = s3c_irq_mask, |
@@ -232,7 +231,7 @@ struct irq_chip s3c_irq_chip = { | |||
232 | .irq_set_wake = s3c_irq_wake | 231 | .irq_set_wake = s3c_irq_wake |
233 | }; | 232 | }; |
234 | 233 | ||
235 | struct irq_chip s3c_irq_level_chip = { | 234 | static struct irq_chip s3c_irq_level_chip = { |
236 | .name = "s3c-level", | 235 | .name = "s3c-level", |
237 | .irq_mask = s3c_irq_mask, | 236 | .irq_mask = s3c_irq_mask, |
238 | .irq_unmask = s3c_irq_unmask, | 237 | .irq_unmask = s3c_irq_unmask, |
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c index 54e83c1f780c..ca08d7df07f7 100644 --- a/arch/arm/mach-s3c24xx/mach-jive.c +++ b/arch/arm/mach-s3c24xx/mach-jive.c | |||
@@ -46,7 +46,6 @@ | |||
46 | #include <linux/mtd/nand_ecc.h> | 46 | #include <linux/mtd/nand_ecc.h> |
47 | #include <linux/mtd/partitions.h> | 47 | #include <linux/mtd/partitions.h> |
48 | 48 | ||
49 | #include <plat/s3c2412.h> | ||
50 | #include <plat/gpio-cfg.h> | 49 | #include <plat/gpio-cfg.h> |
51 | #include <plat/clock.h> | 50 | #include <plat/clock.h> |
52 | #include <plat/devs.h> | 51 | #include <plat/devs.h> |
@@ -54,6 +53,7 @@ | |||
54 | #include <plat/pm.h> | 53 | #include <plat/pm.h> |
55 | #include <linux/platform_data/usb-s3c2410_udc.h> | 54 | #include <linux/platform_data/usb-s3c2410_udc.h> |
56 | 55 | ||
56 | #include "common.h" | ||
57 | #include "s3c2412-power.h" | 57 | #include "s3c2412-power.h" |
58 | 58 | ||
59 | static struct map_desc jive_iodesc[] __initdata = { | 59 | static struct map_desc jive_iodesc[] __initdata = { |
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c index d9d04b240295..8017c0fc1729 100644 --- a/arch/arm/mach-s3c24xx/mach-n30.c +++ b/arch/arm/mach-s3c24xx/mach-n30.c | |||
@@ -48,7 +48,6 @@ | |||
48 | #include <plat/cpu.h> | 48 | #include <plat/cpu.h> |
49 | #include <plat/devs.h> | 49 | #include <plat/devs.h> |
50 | #include <linux/platform_data/mmc-s3cmci.h> | 50 | #include <linux/platform_data/mmc-s3cmci.h> |
51 | #include <plat/s3c2410.h> | ||
52 | #include <linux/platform_data/usb-s3c2410_udc.h> | 51 | #include <linux/platform_data/usb-s3c2410_udc.h> |
53 | 52 | ||
54 | #include "common.h" | 53 | #include "common.h" |
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c index a454e2461860..144b9f80c4a5 100644 --- a/arch/arm/mach-s3c24xx/mach-nexcoder.c +++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c | |||
@@ -41,8 +41,6 @@ | |||
41 | #include <linux/platform_data/i2c-s3c2410.h> | 41 | #include <linux/platform_data/i2c-s3c2410.h> |
42 | 42 | ||
43 | #include <plat/gpio-cfg.h> | 43 | #include <plat/gpio-cfg.h> |
44 | #include <plat/s3c2410.h> | ||
45 | #include <plat/s3c244x.h> | ||
46 | #include <plat/clock.h> | 44 | #include <plat/clock.h> |
47 | #include <plat/devs.h> | 45 | #include <plat/devs.h> |
48 | #include <plat/cpu.h> | 46 | #include <plat/cpu.h> |
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c index 40a47d6c6a85..deb0ace585b0 100644 --- a/arch/arm/mach-s3c24xx/mach-otom.c +++ b/arch/arm/mach-s3c24xx/mach-otom.c | |||
@@ -33,7 +33,6 @@ | |||
33 | #include <plat/cpu.h> | 33 | #include <plat/cpu.h> |
34 | #include <plat/devs.h> | 34 | #include <plat/devs.h> |
35 | #include <plat/regs-serial.h> | 35 | #include <plat/regs-serial.h> |
36 | #include <plat/s3c2410.h> | ||
37 | 36 | ||
38 | #include "common.h" | 37 | #include "common.h" |
39 | #include "otom.h" | 38 | #include "otom.h" |
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c index 56175f0941b1..84c541602661 100644 --- a/arch/arm/mach-s3c24xx/mach-qt2410.c +++ b/arch/arm/mach-s3c24xx/mach-qt2410.c | |||
@@ -55,13 +55,13 @@ | |||
55 | #include <linux/platform_data/usb-s3c2410_udc.h> | 55 | #include <linux/platform_data/usb-s3c2410_udc.h> |
56 | #include <linux/platform_data/i2c-s3c2410.h> | 56 | #include <linux/platform_data/i2c-s3c2410.h> |
57 | 57 | ||
58 | #include <plat/common-smdk.h> | ||
59 | #include <plat/gpio-cfg.h> | 58 | #include <plat/gpio-cfg.h> |
60 | #include <plat/devs.h> | 59 | #include <plat/devs.h> |
61 | #include <plat/cpu.h> | 60 | #include <plat/cpu.h> |
62 | #include <plat/pm.h> | 61 | #include <plat/pm.h> |
63 | 62 | ||
64 | #include "common.h" | 63 | #include "common.h" |
64 | #include "common-smdk.h" | ||
65 | 65 | ||
66 | static struct map_desc qt2410_iodesc[] __initdata = { | 66 | static struct map_desc qt2410_iodesc[] __initdata = { |
67 | { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE } | 67 | { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE } |
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c index e184bfa9613a..cd0b1635c47e 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2410.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c | |||
@@ -52,9 +52,8 @@ | |||
52 | #include <plat/devs.h> | 52 | #include <plat/devs.h> |
53 | #include <plat/cpu.h> | 53 | #include <plat/cpu.h> |
54 | 54 | ||
55 | #include <plat/common-smdk.h> | ||
56 | |||
57 | #include "common.h" | 55 | #include "common.h" |
56 | #include "common-smdk.h" | ||
58 | 57 | ||
59 | static struct map_desc smdk2410_iodesc[] __initdata = { | 58 | static struct map_desc smdk2410_iodesc[] __initdata = { |
60 | /* nothing here yet */ | 59 | /* nothing here yet */ |
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c index 86d7847c9d45..79485907950f 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2413.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c | |||
@@ -41,13 +41,12 @@ | |||
41 | #include <linux/platform_data/i2c-s3c2410.h> | 41 | #include <linux/platform_data/i2c-s3c2410.h> |
42 | #include <mach/fb.h> | 42 | #include <mach/fb.h> |
43 | 43 | ||
44 | #include <plat/s3c2410.h> | ||
45 | #include <plat/s3c2412.h> | ||
46 | #include <plat/clock.h> | 44 | #include <plat/clock.h> |
47 | #include <plat/devs.h> | 45 | #include <plat/devs.h> |
48 | #include <plat/cpu.h> | 46 | #include <plat/cpu.h> |
49 | 47 | ||
50 | #include <plat/common-smdk.h> | 48 | #include "common.h" |
49 | #include "common-smdk.h" | ||
51 | 50 | ||
52 | static struct map_desc smdk2413_iodesc[] __initdata = { | 51 | static struct map_desc smdk2413_iodesc[] __initdata = { |
53 | }; | 52 | }; |
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c index ebb2e61f3d07..037a5da343bd 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2416.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c | |||
@@ -42,7 +42,6 @@ | |||
42 | #include <linux/platform_data/leds-s3c24xx.h> | 42 | #include <linux/platform_data/leds-s3c24xx.h> |
43 | #include <linux/platform_data/i2c-s3c2410.h> | 43 | #include <linux/platform_data/i2c-s3c2410.h> |
44 | 44 | ||
45 | #include <plat/s3c2416.h> | ||
46 | #include <plat/gpio-cfg.h> | 45 | #include <plat/gpio-cfg.h> |
47 | #include <plat/clock.h> | 46 | #include <plat/clock.h> |
48 | #include <plat/devs.h> | 47 | #include <plat/devs.h> |
@@ -54,7 +53,8 @@ | |||
54 | 53 | ||
55 | #include <plat/fb.h> | 54 | #include <plat/fb.h> |
56 | 55 | ||
57 | #include <plat/common-smdk.h> | 56 | #include "common.h" |
57 | #include "common-smdk.h" | ||
58 | 58 | ||
59 | static struct map_desc smdk2416_iodesc[] __initdata = { | 59 | static struct map_desc smdk2416_iodesc[] __initdata = { |
60 | /* ISA IO Space map (memory space selected by A24) */ | 60 | /* ISA IO Space map (memory space selected by A24) */ |
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c index 08cc38c8a4ae..29d31314e23c 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2440.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c | |||
@@ -38,15 +38,12 @@ | |||
38 | #include <mach/fb.h> | 38 | #include <mach/fb.h> |
39 | #include <linux/platform_data/i2c-s3c2410.h> | 39 | #include <linux/platform_data/i2c-s3c2410.h> |
40 | 40 | ||
41 | #include <plat/s3c2410.h> | ||
42 | #include <plat/s3c244x.h> | ||
43 | #include <plat/clock.h> | 41 | #include <plat/clock.h> |
44 | #include <plat/devs.h> | 42 | #include <plat/devs.h> |
45 | #include <plat/cpu.h> | 43 | #include <plat/cpu.h> |
46 | 44 | ||
47 | #include <plat/common-smdk.h> | ||
48 | |||
49 | #include "common.h" | 45 | #include "common.h" |
46 | #include "common-smdk.h" | ||
50 | 47 | ||
51 | static struct map_desc smdk2440_iodesc[] __initdata = { | 48 | static struct map_desc smdk2440_iodesc[] __initdata = { |
52 | /* ISA IO Space map (memory space selected by A24) */ | 49 | /* ISA IO Space map (memory space selected by A24) */ |
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c index fc65d74d3c73..b3be4c4dc7bc 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2443.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c | |||
@@ -38,13 +38,12 @@ | |||
38 | #include <mach/fb.h> | 38 | #include <mach/fb.h> |
39 | #include <linux/platform_data/i2c-s3c2410.h> | 39 | #include <linux/platform_data/i2c-s3c2410.h> |
40 | 40 | ||
41 | #include <plat/s3c2410.h> | ||
42 | #include <plat/s3c2443.h> | ||
43 | #include <plat/clock.h> | 41 | #include <plat/clock.h> |
44 | #include <plat/devs.h> | 42 | #include <plat/devs.h> |
45 | #include <plat/cpu.h> | 43 | #include <plat/cpu.h> |
46 | 44 | ||
47 | #include <plat/common-smdk.h> | 45 | #include "common.h" |
46 | #include "common-smdk.h" | ||
48 | 47 | ||
49 | static struct map_desc smdk2443_iodesc[] __initdata = { | 48 | static struct map_desc smdk2443_iodesc[] __initdata = { |
50 | /* ISA IO Space map (memory space selected by A24) */ | 49 | /* ISA IO Space map (memory space selected by A24) */ |
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c index 3e2bfddc9df1..239129c2d8bc 100644 --- a/arch/arm/mach-s3c24xx/mach-vstms.c +++ b/arch/arm/mach-s3c24xx/mach-vstms.c | |||
@@ -41,12 +41,11 @@ | |||
41 | #include <linux/platform_data/i2c-s3c2410.h> | 41 | #include <linux/platform_data/i2c-s3c2410.h> |
42 | #include <linux/platform_data/mtd-nand-s3c2410.h> | 42 | #include <linux/platform_data/mtd-nand-s3c2410.h> |
43 | 43 | ||
44 | #include <plat/s3c2410.h> | ||
45 | #include <plat/s3c2412.h> | ||
46 | #include <plat/clock.h> | 44 | #include <plat/clock.h> |
47 | #include <plat/devs.h> | 45 | #include <plat/devs.h> |
48 | #include <plat/cpu.h> | 46 | #include <plat/cpu.h> |
49 | 47 | ||
48 | #include "common.h" | ||
50 | 49 | ||
51 | static struct map_desc vstms_iodesc[] __initdata = { | 50 | static struct map_desc vstms_iodesc[] __initdata = { |
52 | }; | 51 | }; |
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c index 668a78a8b195..4c4bc1c83b77 100644 --- a/arch/arm/mach-s3c24xx/pm-s3c2412.c +++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c | |||
@@ -29,7 +29,6 @@ | |||
29 | 29 | ||
30 | #include <plat/cpu.h> | 30 | #include <plat/cpu.h> |
31 | #include <plat/pm.h> | 31 | #include <plat/pm.h> |
32 | #include <plat/s3c2412.h> | ||
33 | 32 | ||
34 | #include "regs-dsc.h" | 33 | #include "regs-dsc.h" |
35 | #include "s3c2412-power.h" | 34 | #include "s3c2412-power.h" |
diff --git a/arch/arm/mach-s3c24xx/regs-dsc.h b/arch/arm/mach-s3c24xx/regs-dsc.h index 98fd4a05587c..61b3d1387d76 100644 --- a/arch/arm/mach-s3c24xx/regs-dsc.h +++ b/arch/arm/mach-s3c24xx/regs-dsc.h | |||
@@ -1,5 +1,4 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-dsc.h | 1 | /* |
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | 2 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> |
4 | * http://www.simtec.co.uk/products/SWLINUX/ | 3 | * http://www.simtec.co.uk/products/SWLINUX/ |
5 | * | 4 | * |
@@ -12,209 +11,15 @@ | |||
12 | 11 | ||
13 | 12 | ||
14 | #ifndef __ASM_ARCH_REGS_DSC_H | 13 | #ifndef __ASM_ARCH_REGS_DSC_H |
15 | #define __ASM_ARCH_REGS_DSC_H "2440-dsc" | 14 | #define __ASM_ARCH_REGS_DSC_H __FILE__ |
16 | 15 | ||
17 | #if defined(CONFIG_CPU_S3C2412) | 16 | /* S3C2412 */ |
18 | #define S3C2412_DSC0 S3C2410_GPIOREG(0xdc) | 17 | #define S3C2412_DSC0 S3C2410_GPIOREG(0xdc) |
19 | #define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) | 18 | #define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) |
20 | #endif | ||
21 | |||
22 | #if defined(CONFIG_CPU_S3C2416) | ||
23 | #define S3C2416_DSC0 S3C2410_GPIOREG(0xc0) | ||
24 | #define S3C2416_DSC1 S3C2410_GPIOREG(0xc4) | ||
25 | #define S3C2416_DSC2 S3C2410_GPIOREG(0xc8) | ||
26 | #define S3C2416_DSC3 S3C2410_GPIOREG(0x110) | ||
27 | |||
28 | #define S3C2416_SELECT_DSC0 (0 << 30) | ||
29 | #define S3C2416_SELECT_DSC1 (1 << 30) | ||
30 | #define S3C2416_SELECT_DSC2 (2 << 30) | ||
31 | #define S3C2416_SELECT_DSC3 (3 << 30) | ||
32 | |||
33 | #define S3C2416_DSC_GETSHIFT(x) (x & 30) | ||
34 | |||
35 | #define S3C2416_DSC0_CF (S3C2416_SELECT_DSC0 | 28) | ||
36 | #define S3C2416_DSC0_CF_5mA (0 << 28) | ||
37 | #define S3C2416_DSC0_CF_10mA (1 << 28) | ||
38 | #define S3C2416_DSC0_CF_15mA (2 << 28) | ||
39 | #define S3C2416_DSC0_CF_21mA (3 << 28) | ||
40 | #define S3C2416_DSC0_CF_MASK (3 << 28) | ||
41 | |||
42 | #define S3C2416_DSC0_nRBE (S3C2416_SELECT_DSC0 | 26) | ||
43 | #define S3C2416_DSC0_nRBE_5mA (0 << 26) | ||
44 | #define S3C2416_DSC0_nRBE_10mA (1 << 26) | ||
45 | #define S3C2416_DSC0_nRBE_15mA (2 << 26) | ||
46 | #define S3C2416_DSC0_nRBE_21mA (3 << 26) | ||
47 | #define S3C2416_DSC0_nRBE_MASK (3 << 26) | ||
48 | |||
49 | #define S3C2416_DSC0_nROE (S3C2416_SELECT_DSC0 | 24) | ||
50 | #define S3C2416_DSC0_nROE_5mA (0 << 24) | ||
51 | #define S3C2416_DSC0_nROE_10mA (1 << 24) | ||
52 | #define S3C2416_DSC0_nROE_15mA (2 << 24) | ||
53 | #define S3C2416_DSC0_nROE_21mA (3 << 24) | ||
54 | #define S3C2416_DSC0_nROE_MASK (3 << 24) | ||
55 | |||
56 | #endif | ||
57 | |||
58 | #if defined(CONFIG_CPU_S3C244X) | ||
59 | 19 | ||
20 | /* S3C2440 */ | ||
60 | #define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) | 21 | #define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) |
61 | #define S3C2440_DSC1 S3C2410_GPIOREG(0xc8) | 22 | #define S3C2440_DSC1 S3C2410_GPIOREG(0xc8) |
62 | 23 | ||
63 | #define S3C2440_SELECT_DSC0 (0) | ||
64 | #define S3C2440_SELECT_DSC1 (1<<31) | ||
65 | |||
66 | #define S3C2440_DSC_GETSHIFT(x) ((x) & 31) | ||
67 | |||
68 | #define S3C2440_DSC0_DISABLE (1<<31) | ||
69 | |||
70 | #define S3C2440_DSC0_ADDR (S3C2440_SELECT_DSC0 | 8) | ||
71 | #define S3C2440_DSC0_ADDR_12mA (0<<8) | ||
72 | #define S3C2440_DSC0_ADDR_10mA (1<<8) | ||
73 | #define S3C2440_DSC0_ADDR_8mA (2<<8) | ||
74 | #define S3C2440_DSC0_ADDR_6mA (3<<8) | ||
75 | #define S3C2440_DSC0_ADDR_MASK (3<<8) | ||
76 | |||
77 | /* D24..D31 */ | ||
78 | #define S3C2440_DSC0_DATA3 (S3C2440_SELECT_DSC0 | 6) | ||
79 | #define S3C2440_DSC0_DATA3_12mA (0<<6) | ||
80 | #define S3C2440_DSC0_DATA3_10mA (1<<6) | ||
81 | #define S3C2440_DSC0_DATA3_8mA (2<<6) | ||
82 | #define S3C2440_DSC0_DATA3_6mA (3<<6) | ||
83 | #define S3C2440_DSC0_DATA3_MASK (3<<6) | ||
84 | |||
85 | /* D16..D23 */ | ||
86 | #define S3C2440_DSC0_DATA2 (S3C2440_SELECT_DSC0 | 4) | ||
87 | #define S3C2440_DSC0_DATA2_12mA (0<<4) | ||
88 | #define S3C2440_DSC0_DATA2_10mA (1<<4) | ||
89 | #define S3C2440_DSC0_DATA2_8mA (2<<4) | ||
90 | #define S3C2440_DSC0_DATA2_6mA (3<<4) | ||
91 | #define S3C2440_DSC0_DATA2_MASK (3<<4) | ||
92 | |||
93 | /* D8..D15 */ | ||
94 | #define S3C2440_DSC0_DATA1 (S3C2440_SELECT_DSC0 | 2) | ||
95 | #define S3C2440_DSC0_DATA1_12mA (0<<2) | ||
96 | #define S3C2440_DSC0_DATA1_10mA (1<<2) | ||
97 | #define S3C2440_DSC0_DATA1_8mA (2<<2) | ||
98 | #define S3C2440_DSC0_DATA1_6mA (3<<2) | ||
99 | #define S3C2440_DSC0_DATA1_MASK (3<<2) | ||
100 | |||
101 | /* D0..D7 */ | ||
102 | #define S3C2440_DSC0_DATA0 (S3C2440_SELECT_DSC0 | 0) | ||
103 | #define S3C2440_DSC0_DATA0_12mA (0<<0) | ||
104 | #define S3C2440_DSC0_DATA0_10mA (1<<0) | ||
105 | #define S3C2440_DSC0_DATA0_8mA (2<<0) | ||
106 | #define S3C2440_DSC0_DATA0_6mA (3<<0) | ||
107 | #define S3C2440_DSC0_DATA0_MASK (3<<0) | ||
108 | |||
109 | #define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 28) | ||
110 | #define S3C2440_DSC1_SCK1_12mA (0<<28) | ||
111 | #define S3C2440_DSC1_SCK1_10mA (1<<28) | ||
112 | #define S3C2440_DSC1_SCK1_8mA (2<<28) | ||
113 | #define S3C2440_DSC1_SCK1_6mA (3<<28) | ||
114 | #define S3C2440_DSC1_SCK1_MASK (3<<28) | ||
115 | |||
116 | #define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 26) | ||
117 | #define S3C2440_DSC1_SCK0_12mA (0<<26) | ||
118 | #define S3C2440_DSC1_SCK0_10mA (1<<26) | ||
119 | #define S3C2440_DSC1_SCK0_8mA (2<<26) | ||
120 | #define S3C2440_DSC1_SCK0_6mA (3<<26) | ||
121 | #define S3C2440_DSC1_SCK0_MASK (3<<26) | ||
122 | |||
123 | #define S3C2440_DSC1_SCKE (S3C2440_SELECT_DSC1 | 24) | ||
124 | #define S3C2440_DSC1_SCKE_10mA (0<<24) | ||
125 | #define S3C2440_DSC1_SCKE_8mA (1<<24) | ||
126 | #define S3C2440_DSC1_SCKE_6mA (2<<24) | ||
127 | #define S3C2440_DSC1_SCKE_4mA (3<<24) | ||
128 | #define S3C2440_DSC1_SCKE_MASK (3<<24) | ||
129 | |||
130 | /* SDRAM nRAS/nCAS */ | ||
131 | #define S3C2440_DSC1_SDR (S3C2440_SELECT_DSC1 | 22) | ||
132 | #define S3C2440_DSC1_SDR_10mA (0<<22) | ||
133 | #define S3C2440_DSC1_SDR_8mA (1<<22) | ||
134 | #define S3C2440_DSC1_SDR_6mA (2<<22) | ||
135 | #define S3C2440_DSC1_SDR_4mA (3<<22) | ||
136 | #define S3C2440_DSC1_SDR_MASK (3<<22) | ||
137 | |||
138 | /* NAND Flash Controller */ | ||
139 | #define S3C2440_DSC1_NFC (S3C2440_SELECT_DSC1 | 20) | ||
140 | #define S3C2440_DSC1_NFC_10mA (0<<20) | ||
141 | #define S3C2440_DSC1_NFC_8mA (1<<20) | ||
142 | #define S3C2440_DSC1_NFC_6mA (2<<20) | ||
143 | #define S3C2440_DSC1_NFC_4mA (3<<20) | ||
144 | #define S3C2440_DSC1_NFC_MASK (3<<20) | ||
145 | |||
146 | /* nBE[0..3] */ | ||
147 | #define S3C2440_DSC1_nBE (S3C2440_SELECT_DSC1 | 18) | ||
148 | #define S3C2440_DSC1_nBE_10mA (0<<18) | ||
149 | #define S3C2440_DSC1_nBE_8mA (1<<18) | ||
150 | #define S3C2440_DSC1_nBE_6mA (2<<18) | ||
151 | #define S3C2440_DSC1_nBE_4mA (3<<18) | ||
152 | #define S3C2440_DSC1_nBE_MASK (3<<18) | ||
153 | |||
154 | #define S3C2440_DSC1_WOE (S3C2440_SELECT_DSC1 | 16) | ||
155 | #define S3C2440_DSC1_WOE_10mA (0<<16) | ||
156 | #define S3C2440_DSC1_WOE_8mA (1<<16) | ||
157 | #define S3C2440_DSC1_WOE_6mA (2<<16) | ||
158 | #define S3C2440_DSC1_WOE_4mA (3<<16) | ||
159 | #define S3C2440_DSC1_WOE_MASK (3<<16) | ||
160 | |||
161 | #define S3C2440_DSC1_CS7 (S3C2440_SELECT_DSC1 | 14) | ||
162 | #define S3C2440_DSC1_CS7_10mA (0<<14) | ||
163 | #define S3C2440_DSC1_CS7_8mA (1<<14) | ||
164 | #define S3C2440_DSC1_CS7_6mA (2<<14) | ||
165 | #define S3C2440_DSC1_CS7_4mA (3<<14) | ||
166 | #define S3C2440_DSC1_CS7_MASK (3<<14) | ||
167 | |||
168 | #define S3C2440_DSC1_CS6 (S3C2440_SELECT_DSC1 | 12) | ||
169 | #define S3C2440_DSC1_CS6_10mA (0<<12) | ||
170 | #define S3C2440_DSC1_CS6_8mA (1<<12) | ||
171 | #define S3C2440_DSC1_CS6_6mA (2<<12) | ||
172 | #define S3C2440_DSC1_CS6_4mA (3<<12) | ||
173 | #define S3C2440_DSC1_CS6_MASK (3<<12) | ||
174 | |||
175 | #define S3C2440_DSC1_CS5 (S3C2440_SELECT_DSC1 | 10) | ||
176 | #define S3C2440_DSC1_CS5_10mA (0<<10) | ||
177 | #define S3C2440_DSC1_CS5_8mA (1<<10) | ||
178 | #define S3C2440_DSC1_CS5_6mA (2<<10) | ||
179 | #define S3C2440_DSC1_CS5_4mA (3<<10) | ||
180 | #define S3C2440_DSC1_CS5_MASK (3<<10) | ||
181 | |||
182 | #define S3C2440_DSC1_CS4 (S3C2440_SELECT_DSC1 | 8) | ||
183 | #define S3C2440_DSC1_CS4_10mA (0<<8) | ||
184 | #define S3C2440_DSC1_CS4_8mA (1<<8) | ||
185 | #define S3C2440_DSC1_CS4_6mA (2<<8) | ||
186 | #define S3C2440_DSC1_CS4_4mA (3<<8) | ||
187 | #define S3C2440_DSC1_CS4_MASK (3<<8) | ||
188 | |||
189 | #define S3C2440_DSC1_CS3 (S3C2440_SELECT_DSC1 | 6) | ||
190 | #define S3C2440_DSC1_CS3_10mA (0<<6) | ||
191 | #define S3C2440_DSC1_CS3_8mA (1<<6) | ||
192 | #define S3C2440_DSC1_CS3_6mA (2<<6) | ||
193 | #define S3C2440_DSC1_CS3_4mA (3<<6) | ||
194 | #define S3C2440_DSC1_CS3_MASK (3<<6) | ||
195 | |||
196 | #define S3C2440_DSC1_CS2 (S3C2440_SELECT_DSC1 | 4) | ||
197 | #define S3C2440_DSC1_CS2_10mA (0<<4) | ||
198 | #define S3C2440_DSC1_CS2_8mA (1<<4) | ||
199 | #define S3C2440_DSC1_CS2_6mA (2<<4) | ||
200 | #define S3C2440_DSC1_CS2_4mA (3<<4) | ||
201 | #define S3C2440_DSC1_CS2_MASK (3<<4) | ||
202 | |||
203 | #define S3C2440_DSC1_CS1 (S3C2440_SELECT_DSC1 | 2) | ||
204 | #define S3C2440_DSC1_CS1_10mA (0<<2) | ||
205 | #define S3C2440_DSC1_CS1_8mA (1<<2) | ||
206 | #define S3C2440_DSC1_CS1_6mA (2<<2) | ||
207 | #define S3C2440_DSC1_CS1_4mA (3<<2) | ||
208 | #define S3C2440_DSC1_CS1_MASK (3<<2) | ||
209 | |||
210 | #define S3C2440_DSC1_CS0 (S3C2440_SELECT_DSC1 | 0) | ||
211 | #define S3C2440_DSC1_CS0_10mA (0<<0) | ||
212 | #define S3C2440_DSC1_CS0_8mA (1<<0) | ||
213 | #define S3C2440_DSC1_CS0_6mA (2<<0) | ||
214 | #define S3C2440_DSC1_CS0_4mA (3<<0) | ||
215 | #define S3C2440_DSC1_CS0_MASK (3<<0) | ||
216 | |||
217 | #endif /* CONFIG_CPU_S3C2440 */ | ||
218 | |||
219 | #endif /* __ASM_ARCH_REGS_DSC_H */ | 24 | #endif /* __ASM_ARCH_REGS_DSC_H */ |
220 | 25 | ||
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c index 9ebef95da721..d850ea5adac2 100644 --- a/arch/arm/mach-s3c24xx/s3c2410.c +++ b/arch/arm/mach-s3c24xx/s3c2410.c | |||
@@ -37,7 +37,6 @@ | |||
37 | #include <mach/regs-clock.h> | 37 | #include <mach/regs-clock.h> |
38 | #include <plat/regs-serial.h> | 38 | #include <plat/regs-serial.h> |
39 | 39 | ||
40 | #include <plat/s3c2410.h> | ||
41 | #include <plat/cpu.h> | 40 | #include <plat/cpu.h> |
42 | #include <plat/devs.h> | 41 | #include <plat/devs.h> |
43 | #include <plat/clock.h> | 42 | #include <plat/clock.h> |
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c index 0d592159a5c3..0f864d4c97de 100644 --- a/arch/arm/mach-s3c24xx/s3c2412.c +++ b/arch/arm/mach-s3c24xx/s3c2412.c | |||
@@ -44,7 +44,6 @@ | |||
44 | #include <plat/pm.h> | 44 | #include <plat/pm.h> |
45 | #include <plat/regs-serial.h> | 45 | #include <plat/regs-serial.h> |
46 | #include <plat/regs-spi.h> | 46 | #include <plat/regs-spi.h> |
47 | #include <plat/s3c2412.h> | ||
48 | 47 | ||
49 | #include "common.h" | 48 | #include "common.h" |
50 | #include "regs-dsc.h" | 49 | #include "regs-dsc.h" |
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c index e30476db0295..b9c5d382dafb 100644 --- a/arch/arm/mach-s3c24xx/s3c2416.c +++ b/arch/arm/mach-s3c24xx/s3c2416.c | |||
@@ -50,7 +50,6 @@ | |||
50 | #include <plat/gpio-core.h> | 50 | #include <plat/gpio-core.h> |
51 | #include <plat/gpio-cfg.h> | 51 | #include <plat/gpio-cfg.h> |
52 | #include <plat/gpio-cfg-helpers.h> | 52 | #include <plat/gpio-cfg-helpers.h> |
53 | #include <plat/s3c2416.h> | ||
54 | #include <plat/devs.h> | 53 | #include <plat/devs.h> |
55 | #include <plat/cpu.h> | 54 | #include <plat/cpu.h> |
56 | #include <plat/sdhci.h> | 55 | #include <plat/sdhci.h> |
diff --git a/arch/arm/mach-s3c24xx/s3c2440.c b/arch/arm/mach-s3c24xx/s3c2440.c index 559e394e8989..5f9d6569475d 100644 --- a/arch/arm/mach-s3c24xx/s3c2440.c +++ b/arch/arm/mach-s3c24xx/s3c2440.c | |||
@@ -33,7 +33,6 @@ | |||
33 | 33 | ||
34 | #include <plat/devs.h> | 34 | #include <plat/devs.h> |
35 | #include <plat/cpu.h> | 35 | #include <plat/cpu.h> |
36 | #include <plat/s3c244x.h> | ||
37 | #include <plat/pm.h> | 36 | #include <plat/pm.h> |
38 | 37 | ||
39 | #include <plat/gpio-core.h> | 38 | #include <plat/gpio-core.h> |
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c index f732826c2359..6819961f6b19 100644 --- a/arch/arm/mach-s3c24xx/s3c2442.c +++ b/arch/arm/mach-s3c24xx/s3c2442.c | |||
@@ -44,7 +44,6 @@ | |||
44 | 44 | ||
45 | #include <plat/clock.h> | 45 | #include <plat/clock.h> |
46 | #include <plat/cpu.h> | 46 | #include <plat/cpu.h> |
47 | #include <plat/s3c244x.h> | ||
48 | #include <plat/pm.h> | 47 | #include <plat/pm.h> |
49 | 48 | ||
50 | #include <plat/gpio-core.h> | 49 | #include <plat/gpio-core.h> |
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c index 165b6a6b3daa..8328cd65bf3d 100644 --- a/arch/arm/mach-s3c24xx/s3c2443.c +++ b/arch/arm/mach-s3c24xx/s3c2443.c | |||
@@ -36,7 +36,6 @@ | |||
36 | #include <plat/gpio-core.h> | 36 | #include <plat/gpio-core.h> |
37 | #include <plat/gpio-cfg.h> | 37 | #include <plat/gpio-cfg.h> |
38 | #include <plat/gpio-cfg-helpers.h> | 38 | #include <plat/gpio-cfg-helpers.h> |
39 | #include <plat/s3c2443.h> | ||
40 | #include <plat/devs.h> | 39 | #include <plat/devs.h> |
41 | #include <plat/cpu.h> | 40 | #include <plat/cpu.h> |
42 | #include <plat/fb-core.h> | 41 | #include <plat/fb-core.h> |
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c index ad2671baa910..2a35edb67354 100644 --- a/arch/arm/mach-s3c24xx/s3c244x.c +++ b/arch/arm/mach-s3c24xx/s3c244x.c | |||
@@ -37,8 +37,6 @@ | |||
37 | #include <plat/regs-serial.h> | 37 | #include <plat/regs-serial.h> |
38 | #include <mach/regs-gpio.h> | 38 | #include <mach/regs-gpio.h> |
39 | 39 | ||
40 | #include <plat/s3c2410.h> | ||
41 | #include <plat/s3c244x.h> | ||
42 | #include <plat/clock.h> | 40 | #include <plat/clock.h> |
43 | #include <plat/devs.h> | 41 | #include <plat/devs.h> |
44 | #include <plat/cpu.h> | 42 | #include <plat/cpu.h> |
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index f9ce1dc28ce4..31d0c9101272 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile | |||
@@ -32,7 +32,6 @@ obj-$(CONFIG_S3C64XX_DMA) += dma.o | |||
32 | 32 | ||
33 | obj-y += dev-uart.o | 33 | obj-y += dev-uart.o |
34 | obj-y += dev-audio.o | 34 | obj-y += dev-audio.o |
35 | obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o | ||
36 | 35 | ||
37 | # Device setup | 36 | # Device setup |
38 | 37 | ||
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h index 57b1ff4b2d7c..fe1a98cf0e4c 100644 --- a/arch/arm/mach-s3c64xx/include/mach/dma.h +++ b/arch/arm/mach-s3c64xx/include/mach/dma.h | |||
@@ -21,7 +21,6 @@ | |||
21 | */ | 21 | */ |
22 | enum dma_ch { | 22 | enum dma_ch { |
23 | /* DMA0/SDMA0 */ | 23 | /* DMA0/SDMA0 */ |
24 | DMACH_DT_PROP = -1, /* not yet supported, do not use */ | ||
25 | DMACH_UART0 = 0, | 24 | DMACH_UART0 = 0, |
26 | DMACH_UART0_SRC2, | 25 | DMACH_UART0_SRC2, |
27 | DMACH_UART1, | 26 | DMACH_UART1, |
diff --git a/arch/arm/mach-s5pc100/common.h b/arch/arm/mach-s5pc100/common.h index 9fbd3ae2b401..c41f912e9e1f 100644 --- a/arch/arm/mach-s5pc100/common.h +++ b/arch/arm/mach-s5pc100/common.h | |||
@@ -20,18 +20,9 @@ void s5pc100_setup_clocks(void); | |||
20 | 20 | ||
21 | void s5pc100_restart(char mode, const char *cmd); | 21 | void s5pc100_restart(char mode, const char *cmd); |
22 | 22 | ||
23 | #ifdef CONFIG_CPU_S5PC100 | ||
24 | |||
25 | extern int s5pc100_init(void); | 23 | extern int s5pc100_init(void); |
26 | extern void s5pc100_map_io(void); | 24 | extern void s5pc100_map_io(void); |
27 | extern void s5pc100_init_clocks(int xtal); | 25 | extern void s5pc100_init_clocks(int xtal); |
28 | extern void s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no); | 26 | extern void s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no); |
29 | 27 | ||
30 | #else | ||
31 | #define s5pc100_init_clocks NULL | ||
32 | #define s5pc100_init_uarts NULL | ||
33 | #define s5pc100_map_io NULL | ||
34 | #define s5pc100_init NULL | ||
35 | #endif | ||
36 | |||
37 | #endif /* __ARCH_ARM_MACH_S5PC100_COMMON_H */ | 28 | #endif /* __ARCH_ARM_MACH_S5PC100_COMMON_H */ |
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h index 6ed2af5c7518..0a1cc0aef720 100644 --- a/arch/arm/mach-s5pv210/common.h +++ b/arch/arm/mach-s5pv210/common.h | |||
@@ -20,18 +20,9 @@ void s5pv210_setup_clocks(void); | |||
20 | 20 | ||
21 | void s5pv210_restart(char mode, const char *cmd); | 21 | void s5pv210_restart(char mode, const char *cmd); |
22 | 22 | ||
23 | #ifdef CONFIG_CPU_S5PV210 | ||
24 | |||
25 | extern int s5pv210_init(void); | 23 | extern int s5pv210_init(void); |
26 | extern void s5pv210_map_io(void); | 24 | extern void s5pv210_map_io(void); |
27 | extern void s5pv210_init_clocks(int xtal); | 25 | extern void s5pv210_init_clocks(int xtal); |
28 | extern void s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no); | 26 | extern void s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no); |
29 | 27 | ||
30 | #else | ||
31 | #define s5pv210_init_clocks NULL | ||
32 | #define s5pv210_init_uarts NULL | ||
33 | #define s5pv210_map_io NULL | ||
34 | #define s5pv210_init NULL | ||
35 | #endif | ||
36 | |||
37 | #endif /* __ARCH_ARM_MACH_S5PV210_COMMON_H */ | 28 | #endif /* __ARCH_ARM_MACH_S5PV210_COMMON_H */ |
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 953eb1f9388d..384e27dd3601 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c | |||
@@ -23,7 +23,6 @@ | |||
23 | #include <linux/spinlock.h> | 23 | #include <linux/spinlock.h> |
24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
25 | #include <linux/delay.h> | 25 | #include <linux/delay.h> |
26 | #include <linux/irqchip/arm-gic.h> | ||
27 | #include <mach/common.h> | 26 | #include <mach/common.h> |
28 | #include <mach/emev2.h> | 27 | #include <mach/emev2.h> |
29 | #include <asm/smp_plat.h> | 28 | #include <asm/smp_plat.h> |
@@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu) | |||
85 | } | 84 | } |
86 | 85 | ||
87 | 86 | ||
88 | static void __cpuinit emev2_secondary_init(unsigned int cpu) | ||
89 | { | ||
90 | gic_secondary_init(0); | ||
91 | } | ||
92 | |||
93 | static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) | 87 | static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) |
94 | { | 88 | { |
95 | cpu = cpu_logical_map(cpu); | 89 | cpu = cpu_logical_map(cpu); |
@@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void) | |||
124 | struct smp_operations emev2_smp_ops __initdata = { | 118 | struct smp_operations emev2_smp_ops __initdata = { |
125 | .smp_init_cpus = emev2_smp_init_cpus, | 119 | .smp_init_cpus = emev2_smp_init_cpus, |
126 | .smp_prepare_cpus = emev2_smp_prepare_cpus, | 120 | .smp_prepare_cpus = emev2_smp_prepare_cpus, |
127 | .smp_secondary_init = emev2_secondary_init, | ||
128 | .smp_boot_secondary = emev2_boot_secondary, | 121 | .smp_boot_secondary = emev2_boot_secondary, |
129 | #ifdef CONFIG_HOTPLUG_CPU | 122 | #ifdef CONFIG_HOTPLUG_CPU |
130 | .cpu_kill = emev2_cpu_kill, | 123 | .cpu_kill = emev2_cpu_kill, |
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 3a4acf23edcf..994906560edd 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c | |||
@@ -23,7 +23,6 @@ | |||
23 | #include <linux/spinlock.h> | 23 | #include <linux/spinlock.h> |
24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
25 | #include <linux/delay.h> | 25 | #include <linux/delay.h> |
26 | #include <linux/irqchip/arm-gic.h> | ||
27 | #include <mach/common.h> | 26 | #include <mach/common.h> |
28 | #include <mach/r8a7779.h> | 27 | #include <mach/r8a7779.h> |
29 | #include <asm/smp_plat.h> | 28 | #include <asm/smp_plat.h> |
@@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) | |||
132 | } | 131 | } |
133 | 132 | ||
134 | 133 | ||
135 | static void __cpuinit r8a7779_secondary_init(unsigned int cpu) | ||
136 | { | ||
137 | gic_secondary_init(0); | ||
138 | } | ||
139 | |||
140 | static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) | 134 | static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) |
141 | { | 135 | { |
142 | struct r8a7779_pm_ch *ch = NULL; | 136 | struct r8a7779_pm_ch *ch = NULL; |
@@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void) | |||
186 | struct smp_operations r8a7779_smp_ops __initdata = { | 180 | struct smp_operations r8a7779_smp_ops __initdata = { |
187 | .smp_init_cpus = r8a7779_smp_init_cpus, | 181 | .smp_init_cpus = r8a7779_smp_init_cpus, |
188 | .smp_prepare_cpus = r8a7779_smp_prepare_cpus, | 182 | .smp_prepare_cpus = r8a7779_smp_prepare_cpus, |
189 | .smp_secondary_init = r8a7779_secondary_init, | ||
190 | .smp_boot_secondary = r8a7779_boot_secondary, | 183 | .smp_boot_secondary = r8a7779_boot_secondary, |
191 | #ifdef CONFIG_HOTPLUG_CPU | 184 | #ifdef CONFIG_HOTPLUG_CPU |
192 | .cpu_kill = r8a7779_cpu_kill, | 185 | .cpu_kill = r8a7779_cpu_kill, |
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index acb46a94ccdf..d0f9aca22477 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c | |||
@@ -23,7 +23,6 @@ | |||
23 | #include <linux/spinlock.h> | 23 | #include <linux/spinlock.h> |
24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
25 | #include <linux/delay.h> | 25 | #include <linux/delay.h> |
26 | #include <linux/irqchip/arm-gic.h> | ||
27 | #include <mach/common.h> | 26 | #include <mach/common.h> |
28 | #include <asm/cacheflush.h> | 27 | #include <asm/cacheflush.h> |
29 | #include <asm/smp_plat.h> | 28 | #include <asm/smp_plat.h> |
@@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void) | |||
59 | return scu_get_core_count(scu_base); | 58 | return scu_get_core_count(scu_base); |
60 | } | 59 | } |
61 | 60 | ||
62 | static void __cpuinit sh73a0_secondary_init(unsigned int cpu) | ||
63 | { | ||
64 | gic_secondary_init(0); | ||
65 | } | ||
66 | |||
67 | static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) | 61 | static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) |
68 | { | 62 | { |
69 | cpu = cpu_logical_map(cpu); | 63 | cpu = cpu_logical_map(cpu); |
@@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu) | |||
138 | struct smp_operations sh73a0_smp_ops __initdata = { | 132 | struct smp_operations sh73a0_smp_ops __initdata = { |
139 | .smp_init_cpus = sh73a0_smp_init_cpus, | 133 | .smp_init_cpus = sh73a0_smp_init_cpus, |
140 | .smp_prepare_cpus = sh73a0_smp_prepare_cpus, | 134 | .smp_prepare_cpus = sh73a0_smp_prepare_cpus, |
141 | .smp_secondary_init = sh73a0_secondary_init, | ||
142 | .smp_boot_secondary = sh73a0_boot_secondary, | 135 | .smp_boot_secondary = sh73a0_boot_secondary, |
143 | #ifdef CONFIG_HOTPLUG_CPU | 136 | #ifdef CONFIG_HOTPLUG_CPU |
144 | .cpu_kill = sh73a0_cpu_kill, | 137 | .cpu_kill = sh73a0_cpu_kill, |
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c index 84c60fa8daa0..ca14d1d5ac7f 100644 --- a/arch/arm/mach-socfpga/platsmp.c +++ b/arch/arm/mach-socfpga/platsmp.c | |||
@@ -22,7 +22,6 @@ | |||
22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
23 | #include <linux/of.h> | 23 | #include <linux/of.h> |
24 | #include <linux/of_address.h> | 24 | #include <linux/of_address.h> |
25 | #include <linux/irqchip/arm-gic.h> | ||
26 | 25 | ||
27 | #include <asm/cacheflush.h> | 26 | #include <asm/cacheflush.h> |
28 | #include <asm/smp_scu.h> | 27 | #include <asm/smp_scu.h> |
@@ -33,16 +32,6 @@ | |||
33 | extern void __iomem *sys_manager_base_addr; | 32 | extern void __iomem *sys_manager_base_addr; |
34 | extern void __iomem *rst_manager_base_addr; | 33 | extern void __iomem *rst_manager_base_addr; |
35 | 34 | ||
36 | static void __cpuinit socfpga_secondary_init(unsigned int cpu) | ||
37 | { | ||
38 | /* | ||
39 | * if any interrupts are already enabled for the primary | ||
40 | * core (e.g. timer irq), then they will not have been enabled | ||
41 | * for us: do so | ||
42 | */ | ||
43 | gic_secondary_init(0); | ||
44 | } | ||
45 | |||
46 | static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) | 35 | static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) |
47 | { | 36 | { |
48 | int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; | 37 | int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; |
@@ -109,7 +98,6 @@ static void socfpga_cpu_die(unsigned int cpu) | |||
109 | struct smp_operations socfpga_smp_ops __initdata = { | 98 | struct smp_operations socfpga_smp_ops __initdata = { |
110 | .smp_init_cpus = socfpga_smp_init_cpus, | 99 | .smp_init_cpus = socfpga_smp_init_cpus, |
111 | .smp_prepare_cpus = socfpga_smp_prepare_cpus, | 100 | .smp_prepare_cpus = socfpga_smp_prepare_cpus, |
112 | .smp_secondary_init = socfpga_secondary_init, | ||
113 | .smp_boot_secondary = socfpga_boot_secondary, | 101 | .smp_boot_secondary = socfpga_boot_secondary, |
114 | #ifdef CONFIG_HOTPLUG_CPU | 102 | #ifdef CONFIG_HOTPLUG_CPU |
115 | .cpu_die = socfpga_cpu_die, | 103 | .cpu_die = socfpga_cpu_die, |
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c index af4ade61cd95..551c69c9a228 100644 --- a/arch/arm/mach-spear13xx/platsmp.c +++ b/arch/arm/mach-spear13xx/platsmp.c | |||
@@ -15,7 +15,6 @@ | |||
15 | #include <linux/jiffies.h> | 15 | #include <linux/jiffies.h> |
16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
17 | #include <linux/smp.h> | 17 | #include <linux/smp.h> |
18 | #include <linux/irqchip/arm-gic.h> | ||
19 | #include <asm/cacheflush.h> | 18 | #include <asm/cacheflush.h> |
20 | #include <asm/smp_scu.h> | 19 | #include <asm/smp_scu.h> |
21 | #include <mach/spear.h> | 20 | #include <mach/spear.h> |
@@ -28,13 +27,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE); | |||
28 | static void __cpuinit spear13xx_secondary_init(unsigned int cpu) | 27 | static void __cpuinit spear13xx_secondary_init(unsigned int cpu) |
29 | { | 28 | { |
30 | /* | 29 | /* |
31 | * if any interrupts are already enabled for the primary | ||
32 | * core (e.g. timer irq), then they will not have been enabled | ||
33 | * for us: do so | ||
34 | */ | ||
35 | gic_secondary_init(0); | ||
36 | |||
37 | /* | ||
38 | * let the primary processor know we're out of the | 30 | * let the primary processor know we're out of the |
39 | * pen, then head off into the C entry point | 31 | * pen, then head off into the C entry point |
40 | */ | 32 | */ |
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c index c7d2b4a8d8cc..25a10191b021 100644 --- a/arch/arm/mach-spear13xx/spear13xx.c +++ b/arch/arm/mach-spear13xx/spear13xx.c | |||
@@ -15,12 +15,12 @@ | |||
15 | 15 | ||
16 | #include <linux/amba/pl022.h> | 16 | #include <linux/amba/pl022.h> |
17 | #include <linux/clk.h> | 17 | #include <linux/clk.h> |
18 | #include <linux/clocksource.h> | ||
18 | #include <linux/dw_dmac.h> | 19 | #include <linux/dw_dmac.h> |
19 | #include <linux/err.h> | 20 | #include <linux/err.h> |
20 | #include <linux/of.h> | 21 | #include <linux/of.h> |
21 | #include <asm/hardware/cache-l2x0.h> | 22 | #include <asm/hardware/cache-l2x0.h> |
22 | #include <asm/mach/map.h> | 23 | #include <asm/mach/map.h> |
23 | #include <asm/smp_twd.h> | ||
24 | #include <mach/dma.h> | 24 | #include <mach/dma.h> |
25 | #include <mach/generic.h> | 25 | #include <mach/generic.h> |
26 | #include <mach/spear.h> | 26 | #include <mach/spear.h> |
@@ -179,5 +179,5 @@ void __init spear13xx_timer_init(void) | |||
179 | clk_put(pclk); | 179 | clk_put(pclk); |
180 | 180 | ||
181 | spear_setup_of_timer(); | 181 | spear_setup_of_timer(); |
182 | twd_local_timer_of_register(); | 182 | clocksource_of_init(); |
183 | } | 183 | } |
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 8709a39bd34c..d259c782d742 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig | |||
@@ -1,10 +1,11 @@ | |||
1 | config ARCH_SUNXI | 1 | config ARCH_SUNXI |
2 | bool "Allwinner A1X SOCs" if ARCH_MULTI_V7 | 2 | bool "Allwinner A1X SOCs" if ARCH_MULTI_V7 |
3 | select CLKSRC_MMIO | 3 | select CLKSRC_MMIO |
4 | select CLKSRC_OF | ||
4 | select COMMON_CLK | 5 | select COMMON_CLK |
5 | select GENERIC_CLOCKEVENTS | 6 | select GENERIC_CLOCKEVENTS |
6 | select GENERIC_IRQ_CHIP | 7 | select GENERIC_IRQ_CHIP |
7 | select PINCTRL | 8 | select PINCTRL |
8 | select SPARSE_IRQ | 9 | select SPARSE_IRQ |
9 | select SUNXI_TIMER | 10 | select SUN4I_TIMER |
10 | select PINCTRL_SUNXI \ No newline at end of file | 11 | select PINCTRL_SUNXI |
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 23afb732cb40..706ce35396b8 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c | |||
@@ -10,63 +10,77 @@ | |||
10 | * warranty of any kind, whether express or implied. | 10 | * warranty of any kind, whether express or implied. |
11 | */ | 11 | */ |
12 | 12 | ||
13 | #include <linux/clocksource.h> | ||
13 | #include <linux/delay.h> | 14 | #include <linux/delay.h> |
14 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
15 | #include <linux/init.h> | 16 | #include <linux/init.h> |
17 | #include <linux/irqchip.h> | ||
16 | #include <linux/of_address.h> | 18 | #include <linux/of_address.h> |
17 | #include <linux/of_irq.h> | 19 | #include <linux/of_irq.h> |
18 | #include <linux/of_platform.h> | 20 | #include <linux/of_platform.h> |
19 | #include <linux/io.h> | 21 | #include <linux/io.h> |
20 | #include <linux/sunxi_timer.h> | ||
21 | 22 | ||
22 | #include <linux/irqchip/sunxi.h> | 23 | #include <linux/clk/sunxi.h> |
23 | 24 | ||
24 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
25 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
27 | #include <asm/system_misc.h> | ||
26 | 28 | ||
27 | #include "sunxi.h" | 29 | #include "sunxi.h" |
28 | 30 | ||
29 | #define WATCHDOG_CTRL_REG 0x00 | 31 | #define SUN4I_WATCHDOG_CTRL_REG 0x00 |
30 | #define WATCHDOG_CTRL_RESTART (1 << 0) | 32 | #define SUN4I_WATCHDOG_CTRL_RESTART (1 << 0) |
31 | #define WATCHDOG_MODE_REG 0x04 | 33 | #define SUN4I_WATCHDOG_MODE_REG 0x04 |
32 | #define WATCHDOG_MODE_ENABLE (1 << 0) | 34 | #define SUN4I_WATCHDOG_MODE_ENABLE (1 << 0) |
33 | #define WATCHDOG_MODE_RESET_ENABLE (1 << 1) | 35 | #define SUN4I_WATCHDOG_MODE_RESET_ENABLE (1 << 1) |
34 | 36 | ||
35 | static void __iomem *wdt_base; | 37 | static void __iomem *wdt_base; |
36 | 38 | ||
37 | static void sunxi_setup_restart(void) | 39 | static void sun4i_restart(char mode, const char *cmd) |
38 | { | ||
39 | struct device_node *np = of_find_compatible_node(NULL, NULL, | ||
40 | "allwinner,sunxi-wdt"); | ||
41 | if (WARN(!np, "unable to setup watchdog restart")) | ||
42 | return; | ||
43 | |||
44 | wdt_base = of_iomap(np, 0); | ||
45 | WARN(!wdt_base, "failed to map watchdog base address"); | ||
46 | } | ||
47 | |||
48 | static void sunxi_restart(char mode, const char *cmd) | ||
49 | { | 40 | { |
50 | if (!wdt_base) | 41 | if (!wdt_base) |
51 | return; | 42 | return; |
52 | 43 | ||
53 | /* Enable timer and set reset bit in the watchdog */ | 44 | /* Enable timer and set reset bit in the watchdog */ |
54 | writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE, | 45 | writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE, |
55 | wdt_base + WATCHDOG_MODE_REG); | 46 | wdt_base + SUN4I_WATCHDOG_MODE_REG); |
56 | 47 | ||
57 | /* | 48 | /* |
58 | * Restart the watchdog. The default (and lowest) interval | 49 | * Restart the watchdog. The default (and lowest) interval |
59 | * value for the watchdog is 0.5s. | 50 | * value for the watchdog is 0.5s. |
60 | */ | 51 | */ |
61 | writel(WATCHDOG_CTRL_RESTART, wdt_base + WATCHDOG_CTRL_REG); | 52 | writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG); |
62 | 53 | ||
63 | while (1) { | 54 | while (1) { |
64 | mdelay(5); | 55 | mdelay(5); |
65 | writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE, | 56 | writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE, |
66 | wdt_base + WATCHDOG_MODE_REG); | 57 | wdt_base + SUN4I_WATCHDOG_MODE_REG); |
67 | } | 58 | } |
68 | } | 59 | } |
69 | 60 | ||
61 | static struct of_device_id sunxi_restart_ids[] = { | ||
62 | { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart }, | ||
63 | { /*sentinel*/ } | ||
64 | }; | ||
65 | |||
66 | static void sunxi_setup_restart(void) | ||
67 | { | ||
68 | const struct of_device_id *of_id; | ||
69 | struct device_node *np; | ||
70 | |||
71 | np = of_find_matching_node(NULL, sunxi_restart_ids); | ||
72 | if (WARN(!np, "unable to setup watchdog restart")) | ||
73 | return; | ||
74 | |||
75 | wdt_base = of_iomap(np, 0); | ||
76 | WARN(!wdt_base, "failed to map watchdog base address"); | ||
77 | |||
78 | of_id = of_match_node(sunxi_restart_ids, np); | ||
79 | WARN(!of_id, "restart function not available"); | ||
80 | |||
81 | arm_pm_restart = of_id->data; | ||
82 | } | ||
83 | |||
70 | static struct map_desc sunxi_io_desc[] __initdata = { | 84 | static struct map_desc sunxi_io_desc[] __initdata = { |
71 | { | 85 | { |
72 | .virtual = (unsigned long) SUNXI_REGS_VIRT_BASE, | 86 | .virtual = (unsigned long) SUNXI_REGS_VIRT_BASE, |
@@ -81,6 +95,12 @@ void __init sunxi_map_io(void) | |||
81 | iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc)); | 95 | iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc)); |
82 | } | 96 | } |
83 | 97 | ||
98 | static void __init sunxi_timer_init(void) | ||
99 | { | ||
100 | sunxi_init_clocks(); | ||
101 | clocksource_of_init(); | ||
102 | } | ||
103 | |||
84 | static void __init sunxi_dt_init(void) | 104 | static void __init sunxi_dt_init(void) |
85 | { | 105 | { |
86 | sunxi_setup_restart(); | 106 | sunxi_setup_restart(); |
@@ -97,9 +117,7 @@ static const char * const sunxi_board_dt_compat[] = { | |||
97 | DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") | 117 | DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") |
98 | .init_machine = sunxi_dt_init, | 118 | .init_machine = sunxi_dt_init, |
99 | .map_io = sunxi_map_io, | 119 | .map_io = sunxi_map_io, |
100 | .init_irq = sunxi_init_irq, | 120 | .init_irq = irqchip_init, |
101 | .handle_irq = sunxi_handle_irq, | 121 | .init_time = sunxi_timer_init, |
102 | .restart = sunxi_restart, | ||
103 | .init_time = &sunxi_timer_init, | ||
104 | .dt_compat = sunxi_board_dt_compat, | 122 | .dt_compat = sunxi_board_dt_compat, |
105 | MACHINE_END | 123 | MACHINE_END |
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 09b578f9eb84..c1970005f805 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile | |||
@@ -10,6 +10,7 @@ obj-y += pm.o | |||
10 | obj-y += reset.o | 10 | obj-y += reset.o |
11 | obj-y += reset-handler.o | 11 | obj-y += reset-handler.o |
12 | obj-y += sleep.o | 12 | obj-y += sleep.o |
13 | obj-y += tegra.o | ||
13 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o | 14 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o |
14 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o | 15 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o |
15 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o | 16 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o |
@@ -26,9 +27,6 @@ obj-$(CONFIG_SMP) += platsmp.o headsmp.o | |||
26 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 27 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
27 | obj-$(CONFIG_TEGRA_PCI) += pcie.o | 28 | obj-$(CONFIG_TEGRA_PCI) += pcie.o |
28 | 29 | ||
29 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-dt-tegra20.o | ||
30 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o | ||
31 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += board-dt-tegra114.o | ||
32 | ifeq ($(CONFIG_CPU_IDLE),y) | 30 | ifeq ($(CONFIG_CPU_IDLE),y) |
33 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o | 31 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o |
34 | endif | 32 | endif |
diff --git a/arch/arm/mach-tegra/board-dt-tegra114.c b/arch/arm/mach-tegra/board-dt-tegra114.c deleted file mode 100644 index 085d63637b62..000000000000 --- a/arch/arm/mach-tegra/board-dt-tegra114.c +++ /dev/null | |||
@@ -1,46 +0,0 @@ | |||
1 | /* | ||
2 | * NVIDIA Tegra114 device tree board support | ||
3 | * | ||
4 | * Copyright (C) 2013 NVIDIA Corporation | ||
5 | * | ||
6 | * This software is licensed under the terms of the GNU General Public | ||
7 | * License version 2, as published by the Free Software Foundation, and | ||
8 | * may be copied, distributed, and modified under those terms. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | */ | ||
16 | |||
17 | #include <linux/of.h> | ||
18 | #include <linux/of_platform.h> | ||
19 | #include <linux/clocksource.h> | ||
20 | |||
21 | #include <asm/mach/arch.h> | ||
22 | |||
23 | #include "board.h" | ||
24 | #include "common.h" | ||
25 | |||
26 | static void __init tegra114_dt_init(void) | ||
27 | { | ||
28 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | ||
29 | } | ||
30 | |||
31 | static const char * const tegra114_dt_board_compat[] = { | ||
32 | "nvidia,tegra114", | ||
33 | NULL, | ||
34 | }; | ||
35 | |||
36 | DT_MACHINE_START(TEGRA114_DT, "NVIDIA Tegra114 (Flattened Device Tree)") | ||
37 | .smp = smp_ops(tegra_smp_ops), | ||
38 | .map_io = tegra_map_common_io, | ||
39 | .init_early = tegra114_init_early, | ||
40 | .init_irq = tegra_dt_init_irq, | ||
41 | .init_time = clocksource_of_init, | ||
42 | .init_machine = tegra114_dt_init, | ||
43 | .init_late = tegra_init_late, | ||
44 | .restart = tegra_assert_system_reset, | ||
45 | .dt_compat = tegra114_dt_board_compat, | ||
46 | MACHINE_END | ||
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c deleted file mode 100644 index bf68567e549d..000000000000 --- a/arch/arm/mach-tegra/board-dt-tegra30.c +++ /dev/null | |||
@@ -1,60 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-tegra/board-dt-tegra30.c | ||
3 | * | ||
4 | * NVIDIA Tegra30 device tree board support | ||
5 | * | ||
6 | * Copyright (C) 2011 NVIDIA Corporation | ||
7 | * | ||
8 | * Derived from: | ||
9 | * | ||
10 | * arch/arm/mach-tegra/board-dt-tegra20.c | ||
11 | * | ||
12 | * Copyright (C) 2010 Secret Lab Technologies, Ltd. | ||
13 | * Copyright (C) 2010 Google, Inc. | ||
14 | * | ||
15 | * This software is licensed under the terms of the GNU General Public | ||
16 | * License version 2, as published by the Free Software Foundation, and | ||
17 | * may be copied, distributed, and modified under those terms. | ||
18 | * | ||
19 | * This program is distributed in the hope that it will be useful, | ||
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
22 | * GNU General Public License for more details. | ||
23 | * | ||
24 | */ | ||
25 | |||
26 | #include <linux/clocksource.h> | ||
27 | #include <linux/kernel.h> | ||
28 | #include <linux/of.h> | ||
29 | #include <linux/of_address.h> | ||
30 | #include <linux/of_fdt.h> | ||
31 | #include <linux/of_irq.h> | ||
32 | #include <linux/of_platform.h> | ||
33 | |||
34 | #include <asm/mach/arch.h> | ||
35 | |||
36 | #include "board.h" | ||
37 | #include "common.h" | ||
38 | #include "iomap.h" | ||
39 | |||
40 | static void __init tegra30_dt_init(void) | ||
41 | { | ||
42 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | ||
43 | } | ||
44 | |||
45 | static const char *tegra30_dt_board_compat[] = { | ||
46 | "nvidia,tegra30", | ||
47 | NULL | ||
48 | }; | ||
49 | |||
50 | DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)") | ||
51 | .smp = smp_ops(tegra_smp_ops), | ||
52 | .map_io = tegra_map_common_io, | ||
53 | .init_early = tegra30_init_early, | ||
54 | .init_irq = tegra_dt_init_irq, | ||
55 | .init_time = clocksource_of_init, | ||
56 | .init_machine = tegra30_dt_init, | ||
57 | .init_late = tegra_init_late, | ||
58 | .restart = tegra_assert_system_reset, | ||
59 | .dt_compat = tegra30_dt_board_compat, | ||
60 | MACHINE_END | ||
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 86851c81a350..60431de585ca 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h | |||
@@ -26,9 +26,7 @@ | |||
26 | 26 | ||
27 | void tegra_assert_system_reset(char mode, const char *cmd); | 27 | void tegra_assert_system_reset(char mode, const char *cmd); |
28 | 28 | ||
29 | void __init tegra20_init_early(void); | 29 | void __init tegra_init_early(void); |
30 | void __init tegra30_init_early(void); | ||
31 | void __init tegra114_init_early(void); | ||
32 | void __init tegra_map_common_io(void); | 30 | void __init tegra_map_common_io(void); |
33 | void __init tegra_init_irq(void); | 31 | void __init tegra_init_irq(void); |
34 | void __init tegra_dt_init_irq(void); | 32 | void __init tegra_dt_init_irq(void); |
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 5449a3f2977b..f0315c95c76d 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c | |||
@@ -94,7 +94,7 @@ static void __init tegra_init_cache(void) | |||
94 | 94 | ||
95 | } | 95 | } |
96 | 96 | ||
97 | static void __init tegra_init_early(void) | 97 | void __init tegra_init_early(void) |
98 | { | 98 | { |
99 | tegra_cpu_reset_handler_init(); | 99 | tegra_cpu_reset_handler_init(); |
100 | tegra_apb_io_init(); | 100 | tegra_apb_io_init(); |
@@ -102,31 +102,9 @@ static void __init tegra_init_early(void) | |||
102 | tegra_init_cache(); | 102 | tegra_init_cache(); |
103 | tegra_pmc_init(); | 103 | tegra_pmc_init(); |
104 | tegra_powergate_init(); | 104 | tegra_powergate_init(); |
105 | tegra_hotplug_init(); | ||
105 | } | 106 | } |
106 | 107 | ||
107 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | ||
108 | void __init tegra20_init_early(void) | ||
109 | { | ||
110 | tegra_init_early(); | ||
111 | tegra20_hotplug_init(); | ||
112 | } | ||
113 | #endif | ||
114 | |||
115 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC | ||
116 | void __init tegra30_init_early(void) | ||
117 | { | ||
118 | tegra_init_early(); | ||
119 | tegra30_hotplug_init(); | ||
120 | } | ||
121 | #endif | ||
122 | |||
123 | #ifdef CONFIG_ARCH_TEGRA_114_SOC | ||
124 | void __init tegra114_init_early(void) | ||
125 | { | ||
126 | tegra_init_early(); | ||
127 | } | ||
128 | #endif | ||
129 | |||
130 | void __init tegra_init_late(void) | 108 | void __init tegra_init_late(void) |
131 | { | 109 | { |
132 | tegra_powergate_debugfs_init(); | 110 | tegra_powergate_debugfs_init(); |
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c index a599f6e36dea..8da9f78475da 100644 --- a/arch/arm/mach-tegra/hotplug.c +++ b/arch/arm/mach-tegra/hotplug.c | |||
@@ -1,8 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * | ||
3 | * Copyright (C) 2002 ARM Ltd. | 2 | * Copyright (C) 2002 ARM Ltd. |
4 | * All Rights Reserved | 3 | * All Rights Reserved |
5 | * Copyright (c) 2010, 2012 NVIDIA Corporation. All rights reserved. | 4 | * Copyright (c) 2010, 2012-2013, NVIDIA Corporation. All rights reserved. |
6 | * | 5 | * |
7 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License version 2 as | 7 | * it under the terms of the GNU General Public License version 2 as |
@@ -15,6 +14,7 @@ | |||
15 | #include <asm/cacheflush.h> | 14 | #include <asm/cacheflush.h> |
16 | #include <asm/smp_plat.h> | 15 | #include <asm/smp_plat.h> |
17 | 16 | ||
17 | #include "fuse.h" | ||
18 | #include "sleep.h" | 18 | #include "sleep.h" |
19 | 19 | ||
20 | static void (*tegra_hotplug_shutdown)(void); | 20 | static void (*tegra_hotplug_shutdown)(void); |
@@ -56,18 +56,13 @@ int tegra_cpu_disable(unsigned int cpu) | |||
56 | return cpu == 0 ? -EPERM : 0; | 56 | return cpu == 0 ? -EPERM : 0; |
57 | } | 57 | } |
58 | 58 | ||
59 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | 59 | void __init tegra_hotplug_init(void) |
60 | extern void tegra20_hotplug_shutdown(void); | ||
61 | void __init tegra20_hotplug_init(void) | ||
62 | { | 60 | { |
63 | tegra_hotplug_shutdown = tegra20_hotplug_shutdown; | 61 | if (!IS_ENABLED(CONFIG_HOTPLUG_CPU)) |
64 | } | 62 | return; |
65 | #endif | ||
66 | 63 | ||
67 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC | 64 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20) |
68 | extern void tegra30_hotplug_shutdown(void); | 65 | tegra_hotplug_shutdown = tegra20_hotplug_shutdown; |
69 | void __init tegra30_hotplug_init(void) | 66 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30) |
70 | { | 67 | tegra_hotplug_shutdown = tegra30_hotplug_shutdown; |
71 | tegra_hotplug_shutdown = tegra30_hotplug_shutdown; | ||
72 | } | 68 | } |
73 | #endif | ||
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index e78d52d83acd..c31db797e199 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c | |||
@@ -18,7 +18,6 @@ | |||
18 | #include <linux/jiffies.h> | 18 | #include <linux/jiffies.h> |
19 | #include <linux/smp.h> | 19 | #include <linux/smp.h> |
20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
21 | #include <linux/irqchip/arm-gic.h> | ||
22 | #include <linux/clk/tegra.h> | 21 | #include <linux/clk/tegra.h> |
23 | 22 | ||
24 | #include <asm/cacheflush.h> | 23 | #include <asm/cacheflush.h> |
@@ -26,53 +25,58 @@ | |||
26 | #include <asm/smp_scu.h> | 25 | #include <asm/smp_scu.h> |
27 | #include <asm/smp_plat.h> | 26 | #include <asm/smp_plat.h> |
28 | 27 | ||
29 | #include <mach/powergate.h> | ||
30 | |||
31 | #include "fuse.h" | 28 | #include "fuse.h" |
32 | #include "flowctrl.h" | 29 | #include "flowctrl.h" |
33 | #include "reset.h" | 30 | #include "reset.h" |
31 | #include "pmc.h" | ||
34 | 32 | ||
35 | #include "common.h" | 33 | #include "common.h" |
36 | #include "iomap.h" | 34 | #include "iomap.h" |
37 | 35 | ||
38 | extern void tegra_secondary_startup(void); | ||
39 | |||
40 | static cpumask_t tegra_cpu_init_mask; | 36 | static cpumask_t tegra_cpu_init_mask; |
41 | 37 | ||
42 | #define EVP_CPU_RESET_VECTOR \ | ||
43 | (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100) | ||
44 | |||
45 | static void __cpuinit tegra_secondary_init(unsigned int cpu) | 38 | static void __cpuinit tegra_secondary_init(unsigned int cpu) |
46 | { | 39 | { |
47 | /* | ||
48 | * if any interrupts are already enabled for the primary | ||
49 | * core (e.g. timer irq), then they will not have been enabled | ||
50 | * for us: do so | ||
51 | */ | ||
52 | gic_secondary_init(0); | ||
53 | |||
54 | cpumask_set_cpu(cpu, &tegra_cpu_init_mask); | 40 | cpumask_set_cpu(cpu, &tegra_cpu_init_mask); |
55 | } | 41 | } |
56 | 42 | ||
57 | static int tegra20_power_up_cpu(unsigned int cpu) | 43 | |
44 | static int tegra20_boot_secondary(unsigned int cpu, struct task_struct *idle) | ||
58 | { | 45 | { |
59 | /* Enable the CPU clock. */ | 46 | cpu = cpu_logical_map(cpu); |
60 | tegra_enable_cpu_clock(cpu); | ||
61 | 47 | ||
62 | /* Clear flow controller CSR. */ | 48 | /* |
63 | flowctrl_write_cpu_csr(cpu, 0); | 49 | * Force the CPU into reset. The CPU must remain in reset when |
50 | * the flow controller state is cleared (which will cause the | ||
51 | * flow controller to stop driving reset if the CPU has been | ||
52 | * power-gated via the flow controller). This will have no | ||
53 | * effect on first boot of the CPU since it should already be | ||
54 | * in reset. | ||
55 | */ | ||
56 | tegra_put_cpu_in_reset(cpu); | ||
64 | 57 | ||
58 | /* | ||
59 | * Unhalt the CPU. If the flow controller was used to | ||
60 | * power-gate the CPU this will cause the flow controller to | ||
61 | * stop driving reset. The CPU will remain in reset because the | ||
62 | * clock and reset block is now driving reset. | ||
63 | */ | ||
64 | flowctrl_write_cpu_halt(cpu, 0); | ||
65 | |||
66 | tegra_enable_cpu_clock(cpu); | ||
67 | flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */ | ||
68 | tegra_cpu_out_of_reset(cpu); | ||
65 | return 0; | 69 | return 0; |
66 | } | 70 | } |
67 | 71 | ||
68 | static int tegra30_power_up_cpu(unsigned int cpu) | 72 | static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle) |
69 | { | 73 | { |
70 | int ret, pwrgateid; | 74 | int ret; |
71 | unsigned long timeout; | 75 | unsigned long timeout; |
72 | 76 | ||
73 | pwrgateid = tegra_cpu_powergate_id(cpu); | 77 | cpu = cpu_logical_map(cpu); |
74 | if (pwrgateid < 0) | 78 | tegra_put_cpu_in_reset(cpu); |
75 | return pwrgateid; | 79 | flowctrl_write_cpu_halt(cpu, 0); |
76 | 80 | ||
77 | /* | 81 | /* |
78 | * The power up sequence of cold boot CPU and warm boot CPU | 82 | * The power up sequence of cold boot CPU and warm boot CPU |
@@ -85,13 +89,13 @@ static int tegra30_power_up_cpu(unsigned int cpu) | |||
85 | * the IO clamps. | 89 | * the IO clamps. |
86 | * For cold boot CPU, do not wait. After the cold boot CPU be | 90 | * For cold boot CPU, do not wait. After the cold boot CPU be |
87 | * booted, it will run to tegra_secondary_init() and set | 91 | * booted, it will run to tegra_secondary_init() and set |
88 | * tegra_cpu_init_mask which influences what tegra30_power_up_cpu() | 92 | * tegra_cpu_init_mask which influences what tegra30_boot_secondary() |
89 | * next time around. | 93 | * next time around. |
90 | */ | 94 | */ |
91 | if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) { | 95 | if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) { |
92 | timeout = jiffies + msecs_to_jiffies(50); | 96 | timeout = jiffies + msecs_to_jiffies(50); |
93 | do { | 97 | do { |
94 | if (tegra_powergate_is_powered(pwrgateid)) | 98 | if (tegra_pmc_cpu_is_powered(cpu)) |
95 | goto remove_clamps; | 99 | goto remove_clamps; |
96 | udelay(10); | 100 | udelay(10); |
97 | } while (time_before(jiffies, timeout)); | 101 | } while (time_before(jiffies, timeout)); |
@@ -103,14 +107,14 @@ static int tegra30_power_up_cpu(unsigned int cpu) | |||
103 | * be un-gated by un-toggling the power gate register | 107 | * be un-gated by un-toggling the power gate register |
104 | * manually. | 108 | * manually. |
105 | */ | 109 | */ |
106 | if (!tegra_powergate_is_powered(pwrgateid)) { | 110 | if (!tegra_pmc_cpu_is_powered(cpu)) { |
107 | ret = tegra_powergate_power_on(pwrgateid); | 111 | ret = tegra_pmc_cpu_power_on(cpu); |
108 | if (ret) | 112 | if (ret) |
109 | return ret; | 113 | return ret; |
110 | 114 | ||
111 | /* Wait for the power to come up. */ | 115 | /* Wait for the power to come up. */ |
112 | timeout = jiffies + msecs_to_jiffies(100); | 116 | timeout = jiffies + msecs_to_jiffies(100); |
113 | while (tegra_powergate_is_powered(pwrgateid)) { | 117 | while (tegra_pmc_cpu_is_powered(cpu)) { |
114 | if (time_after(jiffies, timeout)) | 118 | if (time_after(jiffies, timeout)) |
115 | return -ETIMEDOUT; | 119 | return -ETIMEDOUT; |
116 | udelay(10); | 120 | udelay(10); |
@@ -123,60 +127,26 @@ remove_clamps: | |||
123 | udelay(10); | 127 | udelay(10); |
124 | 128 | ||
125 | /* Remove I/O clamps. */ | 129 | /* Remove I/O clamps. */ |
126 | ret = tegra_powergate_remove_clamping(pwrgateid); | 130 | ret = tegra_pmc_cpu_remove_clamping(cpu); |
127 | if (ret) | 131 | if (ret) |
128 | return ret; | 132 | return ret; |
129 | 133 | ||
130 | udelay(10); | 134 | udelay(10); |
131 | 135 | ||
132 | /* Clear flow controller CSR. */ | 136 | flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */ |
133 | flowctrl_write_cpu_csr(cpu, 0); | 137 | tegra_cpu_out_of_reset(cpu); |
134 | |||
135 | return 0; | 138 | return 0; |
136 | } | 139 | } |
137 | 140 | ||
138 | static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct *idle) | 141 | static int __cpuinit tegra_boot_secondary(unsigned int cpu, |
142 | struct task_struct *idle) | ||
139 | { | 143 | { |
140 | int status; | 144 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20) |
141 | 145 | return tegra20_boot_secondary(cpu, idle); | |
142 | cpu = cpu_logical_map(cpu); | 146 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30) |
143 | 147 | return tegra30_boot_secondary(cpu, idle); | |
144 | /* | ||
145 | * Force the CPU into reset. The CPU must remain in reset when the | ||
146 | * flow controller state is cleared (which will cause the flow | ||
147 | * controller to stop driving reset if the CPU has been power-gated | ||
148 | * via the flow controller). This will have no effect on first boot | ||
149 | * of the CPU since it should already be in reset. | ||
150 | */ | ||
151 | tegra_put_cpu_in_reset(cpu); | ||
152 | |||
153 | /* | ||
154 | * Unhalt the CPU. If the flow controller was used to power-gate the | ||
155 | * CPU this will cause the flow controller to stop driving reset. | ||
156 | * The CPU will remain in reset because the clock and reset block | ||
157 | * is now driving reset. | ||
158 | */ | ||
159 | flowctrl_write_cpu_halt(cpu, 0); | ||
160 | 148 | ||
161 | switch (tegra_chip_id) { | 149 | return -EINVAL; |
162 | case TEGRA20: | ||
163 | status = tegra20_power_up_cpu(cpu); | ||
164 | break; | ||
165 | case TEGRA30: | ||
166 | status = tegra30_power_up_cpu(cpu); | ||
167 | break; | ||
168 | default: | ||
169 | status = -EINVAL; | ||
170 | break; | ||
171 | } | ||
172 | |||
173 | if (status) | ||
174 | goto done; | ||
175 | |||
176 | /* Take the CPU out of reset. */ | ||
177 | tegra_cpu_out_of_reset(cpu); | ||
178 | done: | ||
179 | return status; | ||
180 | } | 150 | } |
181 | 151 | ||
182 | static void __init tegra_smp_prepare_cpus(unsigned int max_cpus) | 152 | static void __init tegra_smp_prepare_cpus(unsigned int max_cpus) |
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 04a8e06f59a9..891fb70d0aa7 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c | |||
@@ -169,12 +169,7 @@ int tegra_cpu_do_idle(void) | |||
169 | 169 | ||
170 | static int tegra_sleep_cpu(unsigned long v2p) | 170 | static int tegra_sleep_cpu(unsigned long v2p) |
171 | { | 171 | { |
172 | /* Switch to the identity mapping. */ | 172 | setup_mm_for_reboot(); |
173 | cpu_switch_mm(idmap_pgd, &init_mm); | ||
174 | |||
175 | /* Flush the TLB. */ | ||
176 | local_flush_tlb_all(); | ||
177 | |||
178 | tegra_sleep_cpu_finish(v2p); | 173 | tegra_sleep_cpu_finish(v2p); |
179 | 174 | ||
180 | /* should never here */ | 175 | /* should never here */ |
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index d4fdb5fcec20..b30e921cc3a9 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (C) 2012,2013 NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -18,57 +18,149 @@ | |||
18 | #include <linux/kernel.h> | 18 | #include <linux/kernel.h> |
19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
20 | #include <linux/of.h> | 20 | #include <linux/of.h> |
21 | #include <linux/of_address.h> | ||
21 | 22 | ||
22 | #include "iomap.h" | 23 | #define PMC_CTRL 0x0 |
24 | #define PMC_CTRL_INTR_LOW (1 << 17) | ||
25 | #define PMC_PWRGATE_TOGGLE 0x30 | ||
26 | #define PMC_PWRGATE_TOGGLE_START (1 << 8) | ||
27 | #define PMC_REMOVE_CLAMPING 0x34 | ||
28 | #define PMC_PWRGATE_STATUS 0x38 | ||
23 | 29 | ||
24 | #define PMC_CTRL 0x0 | 30 | #define TEGRA_POWERGATE_PCIE 3 |
25 | #define PMC_CTRL_INTR_LOW (1 << 17) | 31 | #define TEGRA_POWERGATE_VDEC 4 |
32 | #define TEGRA_POWERGATE_CPU1 9 | ||
33 | #define TEGRA_POWERGATE_CPU2 10 | ||
34 | #define TEGRA_POWERGATE_CPU3 11 | ||
35 | |||
36 | static u8 tegra_cpu_domains[] = { | ||
37 | 0xFF, /* not available for CPU0 */ | ||
38 | TEGRA_POWERGATE_CPU1, | ||
39 | TEGRA_POWERGATE_CPU2, | ||
40 | TEGRA_POWERGATE_CPU3, | ||
41 | }; | ||
42 | static DEFINE_SPINLOCK(tegra_powergate_lock); | ||
43 | |||
44 | static void __iomem *tegra_pmc_base; | ||
45 | static bool tegra_pmc_invert_interrupt; | ||
26 | 46 | ||
27 | static inline u32 tegra_pmc_readl(u32 reg) | 47 | static inline u32 tegra_pmc_readl(u32 reg) |
28 | { | 48 | { |
29 | return readl(IO_ADDRESS(TEGRA_PMC_BASE + reg)); | 49 | return readl(tegra_pmc_base + reg); |
30 | } | 50 | } |
31 | 51 | ||
32 | static inline void tegra_pmc_writel(u32 val, u32 reg) | 52 | static inline void tegra_pmc_writel(u32 val, u32 reg) |
33 | { | 53 | { |
34 | writel(val, IO_ADDRESS(TEGRA_PMC_BASE + reg)); | 54 | writel(val, tegra_pmc_base + reg); |
55 | } | ||
56 | |||
57 | static int tegra_pmc_get_cpu_powerdomain_id(int cpuid) | ||
58 | { | ||
59 | if (cpuid <= 0 || cpuid >= num_possible_cpus()) | ||
60 | return -EINVAL; | ||
61 | return tegra_cpu_domains[cpuid]; | ||
62 | } | ||
63 | |||
64 | static bool tegra_pmc_powergate_is_powered(int id) | ||
65 | { | ||
66 | return (tegra_pmc_readl(PMC_PWRGATE_STATUS) >> id) & 1; | ||
67 | } | ||
68 | |||
69 | static int tegra_pmc_powergate_set(int id, bool new_state) | ||
70 | { | ||
71 | bool old_state; | ||
72 | unsigned long flags; | ||
73 | |||
74 | spin_lock_irqsave(&tegra_powergate_lock, flags); | ||
75 | |||
76 | old_state = tegra_pmc_powergate_is_powered(id); | ||
77 | WARN_ON(old_state == new_state); | ||
78 | |||
79 | tegra_pmc_writel(PMC_PWRGATE_TOGGLE_START | id, PMC_PWRGATE_TOGGLE); | ||
80 | |||
81 | spin_unlock_irqrestore(&tegra_powergate_lock, flags); | ||
82 | |||
83 | return 0; | ||
84 | } | ||
85 | |||
86 | static int tegra_pmc_powergate_remove_clamping(int id) | ||
87 | { | ||
88 | u32 mask; | ||
89 | |||
90 | /* | ||
91 | * Tegra has a bug where PCIE and VDE clamping masks are | ||
92 | * swapped relatively to the partition ids. | ||
93 | */ | ||
94 | if (id == TEGRA_POWERGATE_VDEC) | ||
95 | mask = (1 << TEGRA_POWERGATE_PCIE); | ||
96 | else if (id == TEGRA_POWERGATE_PCIE) | ||
97 | mask = (1 << TEGRA_POWERGATE_VDEC); | ||
98 | else | ||
99 | mask = (1 << id); | ||
100 | |||
101 | tegra_pmc_writel(mask, PMC_REMOVE_CLAMPING); | ||
102 | |||
103 | return 0; | ||
104 | } | ||
105 | |||
106 | bool tegra_pmc_cpu_is_powered(int cpuid) | ||
107 | { | ||
108 | int id; | ||
109 | |||
110 | id = tegra_pmc_get_cpu_powerdomain_id(cpuid); | ||
111 | if (id < 0) | ||
112 | return false; | ||
113 | return tegra_pmc_powergate_is_powered(id); | ||
114 | } | ||
115 | |||
116 | int tegra_pmc_cpu_power_on(int cpuid) | ||
117 | { | ||
118 | int id; | ||
119 | |||
120 | id = tegra_pmc_get_cpu_powerdomain_id(cpuid); | ||
121 | if (id < 0) | ||
122 | return id; | ||
123 | return tegra_pmc_powergate_set(id, true); | ||
124 | } | ||
125 | |||
126 | int tegra_pmc_cpu_remove_clamping(int cpuid) | ||
127 | { | ||
128 | int id; | ||
129 | |||
130 | id = tegra_pmc_get_cpu_powerdomain_id(cpuid); | ||
131 | if (id < 0) | ||
132 | return id; | ||
133 | return tegra_pmc_powergate_remove_clamping(id); | ||
35 | } | 134 | } |
36 | 135 | ||
37 | #ifdef CONFIG_OF | ||
38 | static const struct of_device_id matches[] __initconst = { | 136 | static const struct of_device_id matches[] __initconst = { |
137 | { .compatible = "nvidia,tegra114-pmc" }, | ||
138 | { .compatible = "nvidia,tegra30-pmc" }, | ||
39 | { .compatible = "nvidia,tegra20-pmc" }, | 139 | { .compatible = "nvidia,tegra20-pmc" }, |
40 | { } | 140 | { } |
41 | }; | 141 | }; |
42 | #endif | ||
43 | 142 | ||
44 | void __init tegra_pmc_init(void) | 143 | static void tegra_pmc_parse_dt(void) |
45 | { | 144 | { |
46 | /* | 145 | struct device_node *np; |
47 | * For now, Harmony is the only board that uses the PMC, and it wants | ||
48 | * the signal inverted. Seaboard would too if it used the PMC. | ||
49 | * Hopefully by the time other boards want to use the PMC, everything | ||
50 | * will be device-tree, or they also want it inverted. | ||
51 | */ | ||
52 | bool invert_interrupt = true; | ||
53 | u32 val; | ||
54 | 146 | ||
55 | #ifdef CONFIG_OF | 147 | np = of_find_matching_node(NULL, matches); |
56 | if (of_have_populated_dt()) { | 148 | BUG_ON(!np); |
57 | struct device_node *np; | ||
58 | 149 | ||
59 | invert_interrupt = false; | 150 | tegra_pmc_base = of_iomap(np, 0); |
151 | |||
152 | tegra_pmc_invert_interrupt = of_property_read_bool(np, | ||
153 | "nvidia,invert-interrupt"); | ||
154 | } | ||
155 | |||
156 | void __init tegra_pmc_init(void) | ||
157 | { | ||
158 | u32 val; | ||
60 | 159 | ||
61 | np = of_find_matching_node(NULL, matches); | 160 | tegra_pmc_parse_dt(); |
62 | if (np) { | ||
63 | if (of_find_property(np, "nvidia,invert-interrupt", | ||
64 | NULL)) | ||
65 | invert_interrupt = true; | ||
66 | } | ||
67 | } | ||
68 | #endif | ||
69 | 161 | ||
70 | val = tegra_pmc_readl(PMC_CTRL); | 162 | val = tegra_pmc_readl(PMC_CTRL); |
71 | if (invert_interrupt) | 163 | if (tegra_pmc_invert_interrupt) |
72 | val |= PMC_CTRL_INTR_LOW; | 164 | val |= PMC_CTRL_INTR_LOW; |
73 | else | 165 | else |
74 | val &= ~PMC_CTRL_INTR_LOW; | 166 | val &= ~PMC_CTRL_INTR_LOW; |
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h index 8995ee4a8768..7d44710368be 100644 --- a/arch/arm/mach-tegra/pmc.h +++ b/arch/arm/mach-tegra/pmc.h | |||
@@ -18,6 +18,10 @@ | |||
18 | #ifndef __MACH_TEGRA_PMC_H | 18 | #ifndef __MACH_TEGRA_PMC_H |
19 | #define __MACH_TEGRA_PMC_H | 19 | #define __MACH_TEGRA_PMC_H |
20 | 20 | ||
21 | bool tegra_pmc_cpu_is_powered(int cpuid); | ||
22 | int tegra_pmc_cpu_power_on(int cpuid); | ||
23 | int tegra_pmc_cpu_remove_clamping(int cpuid); | ||
24 | |||
21 | void tegra_pmc_init(void); | 25 | void tegra_pmc_init(void); |
22 | 26 | ||
23 | #endif | 27 | #endif |
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index bb308eab9079..2080fb12ce26 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. | 2 | * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -124,11 +124,11 @@ int tegra_sleep_cpu_finish(unsigned long); | |||
124 | void tegra_disable_clean_inv_dcache(void); | 124 | void tegra_disable_clean_inv_dcache(void); |
125 | 125 | ||
126 | #ifdef CONFIG_HOTPLUG_CPU | 126 | #ifdef CONFIG_HOTPLUG_CPU |
127 | void tegra20_hotplug_init(void); | 127 | void tegra20_hotplug_shutdown(void); |
128 | void tegra30_hotplug_init(void); | 128 | void tegra30_hotplug_shutdown(void); |
129 | void tegra_hotplug_init(void); | ||
129 | #else | 130 | #else |
130 | static inline void tegra20_hotplug_init(void) {} | 131 | static inline void tegra_hotplug_init(void) {} |
131 | static inline void tegra30_hotplug_init(void) {} | ||
132 | #endif | 132 | #endif |
133 | 133 | ||
134 | void tegra20_cpu_shutdown(int cpu); | 134 | void tegra20_cpu_shutdown(int cpu); |
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/tegra.c index a0edf2510280..27232c901a22 100644 --- a/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/arch/arm/mach-tegra/tegra.c | |||
@@ -1,6 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * nVidia Tegra device tree board support | 2 | * NVIDIA Tegra SoC device tree board support |
3 | * | 3 | * |
4 | * Copyright (C) 2011, 2013, NVIDIA Corporation | ||
4 | * Copyright (C) 2010 Secret Lab Technologies, Ltd. | 5 | * Copyright (C) 2010 Secret Lab Technologies, Ltd. |
5 | * Copyright (C) 2010 Google, Inc. | 6 | * Copyright (C) 2010 Google, Inc. |
6 | * | 7 | * |
@@ -111,7 +112,8 @@ static void __init harmony_init(void) | |||
111 | 112 | ||
112 | static void __init paz00_init(void) | 113 | static void __init paz00_init(void) |
113 | { | 114 | { |
114 | tegra_paz00_wifikill_init(); | 115 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) |
116 | tegra_paz00_wifikill_init(); | ||
115 | } | 117 | } |
116 | 118 | ||
117 | static struct { | 119 | static struct { |
@@ -137,19 +139,21 @@ static void __init tegra_dt_init_late(void) | |||
137 | } | 139 | } |
138 | } | 140 | } |
139 | 141 | ||
140 | static const char *tegra20_dt_board_compat[] = { | 142 | static const char * const tegra_dt_board_compat[] = { |
143 | "nvidia,tegra114", | ||
144 | "nvidia,tegra30", | ||
141 | "nvidia,tegra20", | 145 | "nvidia,tegra20", |
142 | NULL | 146 | NULL |
143 | }; | 147 | }; |
144 | 148 | ||
145 | DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)") | 149 | DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)") |
146 | .map_io = tegra_map_common_io, | 150 | .map_io = tegra_map_common_io, |
147 | .smp = smp_ops(tegra_smp_ops), | 151 | .smp = smp_ops(tegra_smp_ops), |
148 | .init_early = tegra20_init_early, | 152 | .init_early = tegra_init_early, |
149 | .init_irq = tegra_dt_init_irq, | 153 | .init_irq = tegra_dt_init_irq, |
150 | .init_time = clocksource_of_init, | 154 | .init_time = clocksource_of_init, |
151 | .init_machine = tegra_dt_init, | 155 | .init_machine = tegra_dt_init, |
152 | .init_late = tegra_dt_init_late, | 156 | .init_late = tegra_dt_init_late, |
153 | .restart = tegra_assert_system_reset, | 157 | .restart = tegra_assert_system_reset, |
154 | .dt_compat = tegra20_dt_board_compat, | 158 | .dt_compat = tegra_dt_board_compat, |
155 | MACHINE_END | 159 | MACHINE_END |
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index 18f7af339dc9..152b1309b9af 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c | |||
@@ -16,7 +16,6 @@ | |||
16 | #include <linux/device.h> | 16 | #include <linux/device.h> |
17 | #include <linux/smp.h> | 17 | #include <linux/smp.h> |
18 | #include <linux/io.h> | 18 | #include <linux/io.h> |
19 | #include <linux/irqchip/arm-gic.h> | ||
20 | 19 | ||
21 | #include <asm/cacheflush.h> | 20 | #include <asm/cacheflush.h> |
22 | #include <asm/smp_plat.h> | 21 | #include <asm/smp_plat.h> |
@@ -58,13 +57,6 @@ static DEFINE_SPINLOCK(boot_lock); | |||
58 | static void __cpuinit ux500_secondary_init(unsigned int cpu) | 57 | static void __cpuinit ux500_secondary_init(unsigned int cpu) |
59 | { | 58 | { |
60 | /* | 59 | /* |
61 | * if any interrupts are already enabled for the primary | ||
62 | * core (e.g. timer irq), then they will not have been enabled | ||
63 | * for us: do so | ||
64 | */ | ||
65 | gic_secondary_init(0); | ||
66 | |||
67 | /* | ||
68 | * let the primary processor know we're out of the | 60 | * let the primary processor know we're out of the |
69 | * pen, then head off into the C entry point | 61 | * pen, then head off into the C entry point |
70 | */ | 62 | */ |
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index a6af0b8732ba..d07bbe7f04a6 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c | |||
@@ -7,6 +7,7 @@ | |||
7 | #include <linux/io.h> | 7 | #include <linux/io.h> |
8 | #include <linux/errno.h> | 8 | #include <linux/errno.h> |
9 | #include <linux/clksrc-dbx500-prcmu.h> | 9 | #include <linux/clksrc-dbx500-prcmu.h> |
10 | #include <linux/clocksource.h> | ||
10 | #include <linux/of.h> | 11 | #include <linux/of.h> |
11 | #include <linux/of_address.h> | 12 | #include <linux/of_address.h> |
12 | #include <linux/platform_data/clocksource-nomadik-mtu.h> | 13 | #include <linux/platform_data/clocksource-nomadik-mtu.h> |
@@ -32,7 +33,7 @@ static void __init ux500_twd_init(void) | |||
32 | twd_local_timer = &u8500_twd_local_timer; | 33 | twd_local_timer = &u8500_twd_local_timer; |
33 | 34 | ||
34 | if (of_have_populated_dt()) | 35 | if (of_have_populated_dt()) |
35 | twd_local_timer_of_register(); | 36 | clocksource_of_init(); |
36 | else { | 37 | else { |
37 | err = twd_local_timer_register(twd_local_timer); | 38 | err = twd_local_timer_register(twd_local_timer); |
38 | if (err) | 39 | if (err) |
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index eb2b3a627f03..9366f37902d9 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c | |||
@@ -5,6 +5,7 @@ | |||
5 | #include <linux/amba/bus.h> | 5 | #include <linux/amba/bus.h> |
6 | #include <linux/amba/mmci.h> | 6 | #include <linux/amba/mmci.h> |
7 | #include <linux/io.h> | 7 | #include <linux/io.h> |
8 | #include <linux/clocksource.h> | ||
8 | #include <linux/smp.h> | 9 | #include <linux/smp.h> |
9 | #include <linux/init.h> | 10 | #include <linux/init.h> |
10 | #include <linux/irqchip.h> | 11 | #include <linux/irqchip.h> |
@@ -27,7 +28,6 @@ | |||
27 | #include <asm/arch_timer.h> | 28 | #include <asm/arch_timer.h> |
28 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
29 | #include <asm/sizes.h> | 30 | #include <asm/sizes.h> |
30 | #include <asm/smp_twd.h> | ||
31 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
32 | #include <asm/mach/map.h> | 32 | #include <asm/mach/map.h> |
33 | #include <asm/mach/time.h> | 33 | #include <asm/mach/time.h> |
@@ -434,6 +434,7 @@ static void __init v2m_dt_timer_init(void) | |||
434 | 434 | ||
435 | of_clk_init(NULL); | 435 | of_clk_init(NULL); |
436 | 436 | ||
437 | clocksource_of_init(); | ||
437 | do { | 438 | do { |
438 | node = of_find_compatible_node(node, NULL, "arm,sp804"); | 439 | node = of_find_compatible_node(node, NULL, "arm,sp804"); |
439 | } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB); | 440 | } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB); |
@@ -448,8 +449,7 @@ static void __init v2m_dt_timer_init(void) | |||
448 | irq_of_parse_and_map(node, 0)); | 449 | irq_of_parse_and_map(node, 0)); |
449 | } | 450 | } |
450 | 451 | ||
451 | if (arch_timer_of_register() != 0) | 452 | arch_timer_of_register(); |
452 | twd_local_timer_of_register(); | ||
453 | 453 | ||
454 | if (arch_timer_sched_clock_init() != 0) | 454 | if (arch_timer_sched_clock_init() != 0) |
455 | versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), | 455 | versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), |
diff --git a/arch/arm/mach-virt/platsmp.c b/arch/arm/mach-virt/platsmp.c index 8badaabe70a1..f4143f5bfa5b 100644 --- a/arch/arm/mach-virt/platsmp.c +++ b/arch/arm/mach-virt/platsmp.c | |||
@@ -21,8 +21,6 @@ | |||
21 | #include <linux/smp.h> | 21 | #include <linux/smp.h> |
22 | #include <linux/of.h> | 22 | #include <linux/of.h> |
23 | 23 | ||
24 | #include <linux/irqchip/arm-gic.h> | ||
25 | |||
26 | #include <asm/psci.h> | 24 | #include <asm/psci.h> |
27 | #include <asm/smp_plat.h> | 25 | #include <asm/smp_plat.h> |
28 | 26 | ||
@@ -45,14 +43,8 @@ static int __cpuinit virt_boot_secondary(unsigned int cpu, | |||
45 | return -ENODEV; | 43 | return -ENODEV; |
46 | } | 44 | } |
47 | 45 | ||
48 | static void __cpuinit virt_secondary_init(unsigned int cpu) | ||
49 | { | ||
50 | gic_secondary_init(0); | ||
51 | } | ||
52 | |||
53 | struct smp_operations __initdata virt_smp_ops = { | 46 | struct smp_operations __initdata virt_smp_ops = { |
54 | .smp_init_cpus = virt_smp_init_cpus, | 47 | .smp_init_cpus = virt_smp_init_cpus, |
55 | .smp_prepare_cpus = virt_smp_prepare_cpus, | 48 | .smp_prepare_cpus = virt_smp_prepare_cpus, |
56 | .smp_secondary_init = virt_secondary_init, | ||
57 | .smp_boot_secondary = virt_boot_secondary, | 49 | .smp_boot_secondary = virt_boot_secondary, |
58 | }; | 50 | }; |
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index a82cecb84948..ad97400ba3ad 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile | |||
@@ -3,7 +3,11 @@ | |||
3 | # | 3 | # |
4 | ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include | 4 | ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include |
5 | 5 | ||
6 | obj-y += addr-map.o | 6 | obj-$(CONFIG_ARCH_MVEBU) += addr-map.o |
7 | obj-$(CONFIG_ARCH_KIRKWOOD) += addr-map.o | ||
8 | obj-$(CONFIG_ARCH_DOVE) += addr-map.o | ||
9 | obj-$(CONFIG_ARCH_ORION5X) += addr-map.o | ||
10 | obj-$(CONFIG_ARCH_MV78XX0) += addr-map.o | ||
7 | 11 | ||
8 | orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o | 12 | orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o |
9 | obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o | 13 | obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o |
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c index f20a321088a2..8b8c06d2e9c4 100644 --- a/arch/arm/plat-orion/pcie.c +++ b/arch/arm/plat-orion/pcie.c | |||
@@ -120,12 +120,14 @@ void __init orion_pcie_reset(void __iomem *base) | |||
120 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks | 120 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks |
121 | * WIN[0-3] -> DRAM bank[0-3] | 121 | * WIN[0-3] -> DRAM bank[0-3] |
122 | */ | 122 | */ |
123 | static void __init orion_pcie_setup_wins(void __iomem *base, | 123 | static void __init orion_pcie_setup_wins(void __iomem *base) |
124 | struct mbus_dram_target_info *dram) | ||
125 | { | 124 | { |
125 | const struct mbus_dram_target_info *dram; | ||
126 | u32 size; | 126 | u32 size; |
127 | int i; | 127 | int i; |
128 | 128 | ||
129 | dram = mv_mbus_dram_info(); | ||
130 | |||
129 | /* | 131 | /* |
130 | * First, disable and clear BARs and windows. | 132 | * First, disable and clear BARs and windows. |
131 | */ | 133 | */ |
@@ -150,7 +152,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base, | |||
150 | */ | 152 | */ |
151 | size = 0; | 153 | size = 0; |
152 | for (i = 0; i < dram->num_cs; i++) { | 154 | for (i = 0; i < dram->num_cs; i++) { |
153 | struct mbus_dram_window *cs = dram->cs + i; | 155 | const struct mbus_dram_window *cs = dram->cs + i; |
154 | 156 | ||
155 | writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); | 157 | writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); |
156 | writel(0, base + PCIE_WIN04_REMAP_OFF(i)); | 158 | writel(0, base + PCIE_WIN04_REMAP_OFF(i)); |
@@ -184,7 +186,7 @@ void __init orion_pcie_setup(void __iomem *base) | |||
184 | /* | 186 | /* |
185 | * Point PCIe unit MBUS decode windows to DRAM space. | 187 | * Point PCIe unit MBUS decode windows to DRAM space. |
186 | */ | 188 | */ |
187 | orion_pcie_setup_wins(base, &orion_mbus_dram_info); | 189 | orion_pcie_setup_wins(base); |
188 | 190 | ||
189 | /* | 191 | /* |
190 | * Master + slave enable. | 192 | * Master + slave enable. |
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index a9d52167e16e..91c2d72e689b 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig | |||
@@ -37,14 +37,6 @@ if PLAT_SAMSUNG | |||
37 | 37 | ||
38 | comment "Boot options" | 38 | comment "Boot options" |
39 | 39 | ||
40 | config S3C_BOOT_WATCHDOG | ||
41 | bool "S3C Initialisation watchdog" | ||
42 | depends on S3C2410_WATCHDOG | ||
43 | help | ||
44 | Say y to enable the watchdog during the kernel decompression | ||
45 | stage. If the kernel fails to uncompress, then the watchdog | ||
46 | will trigger a reset and the system should restart. | ||
47 | |||
48 | config S3C_BOOT_ERROR_RESET | 40 | config S3C_BOOT_ERROR_RESET |
49 | bool "S3C Reboot on decompression error" | 41 | bool "S3C Reboot on decompression error" |
50 | help | 42 | help |
@@ -125,12 +117,6 @@ config SAMSUNG_GPIOLIB_4BIT | |||
125 | configuration. GPIOlib shall be compiled only for S3C64XX and S5P | 117 | configuration. GPIOlib shall be compiled only for S3C64XX and S5P |
126 | series of processors. | 118 | series of processors. |
127 | 119 | ||
128 | config S3C_GPIO_CFG_S3C64XX | ||
129 | bool | ||
130 | help | ||
131 | Internal configuration to enable S3C64XX style GPIO configuration | ||
132 | functions. | ||
133 | |||
134 | config S5P_GPIO_DRVSTR | 120 | config S5P_GPIO_DRVSTR |
135 | bool | 121 | bool |
136 | help | 122 | help |
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c index 71d58ddea9c1..ec0d731b0e7b 100644 --- a/arch/arm/plat-samsung/dma-ops.c +++ b/arch/arm/plat-samsung/dma-ops.c | |||
@@ -23,23 +23,15 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch, | |||
23 | struct device *dev, char *ch_name) | 23 | struct device *dev, char *ch_name) |
24 | { | 24 | { |
25 | dma_cap_mask_t mask; | 25 | dma_cap_mask_t mask; |
26 | void *filter_param; | ||
27 | 26 | ||
28 | dma_cap_zero(mask); | 27 | dma_cap_zero(mask); |
29 | dma_cap_set(param->cap, mask); | 28 | dma_cap_set(param->cap, mask); |
30 | 29 | ||
31 | /* | ||
32 | * If a dma channel property of a device node from device tree is | ||
33 | * specified, use that as the fliter parameter. | ||
34 | */ | ||
35 | filter_param = (dma_ch == DMACH_DT_PROP) ? | ||
36 | (void *)param->dt_dmach_prop : (void *)dma_ch; | ||
37 | |||
38 | if (dev->of_node) | 30 | if (dev->of_node) |
39 | return (unsigned)dma_request_slave_channel(dev, ch_name); | 31 | return (unsigned)dma_request_slave_channel(dev, ch_name); |
40 | else | 32 | else |
41 | return (unsigned)dma_request_channel(mask, pl330_filter, | 33 | return (unsigned)dma_request_channel(mask, pl330_filter, |
42 | filter_param); | 34 | (void *)dma_ch); |
43 | } | 35 | } |
44 | 36 | ||
45 | static int samsung_dmadev_release(unsigned ch, void *param) | 37 | static int samsung_dmadev_release(unsigned ch, void *param) |
diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h index 114178268b75..ce6d7634b6cb 100644 --- a/arch/arm/plat-samsung/include/plat/dma-ops.h +++ b/arch/arm/plat-samsung/include/plat/dma-ops.h | |||
@@ -18,7 +18,6 @@ | |||
18 | 18 | ||
19 | struct samsung_dma_req { | 19 | struct samsung_dma_req { |
20 | enum dma_transaction_type cap; | 20 | enum dma_transaction_type cap; |
21 | struct property *dt_dmach_prop; | ||
22 | struct s3c2410_dma_client *client; | 21 | struct s3c2410_dma_client *client; |
23 | }; | 22 | }; |
24 | 23 | ||
diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h index d384a8016b47..abe07fae71db 100644 --- a/arch/arm/plat-samsung/include/plat/dma-pl330.h +++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h | |||
@@ -21,7 +21,6 @@ | |||
21 | * use these just as IDs. | 21 | * use these just as IDs. |
22 | */ | 22 | */ |
23 | enum dma_ch { | 23 | enum dma_ch { |
24 | DMACH_DT_PROP = -1, | ||
25 | DMACH_UART0_RX = 0, | 24 | DMACH_UART0_RX = 0, |
26 | DMACH_UART0_TX, | 25 | DMACH_UART0_TX, |
27 | DMACH_UART1_RX, | 26 | DMACH_UART1_RX, |
diff --git a/arch/arm/plat-samsung/include/plat/irq.h b/arch/arm/plat-samsung/include/plat/irq.h deleted file mode 100644 index e21a89bc26c9..000000000000 --- a/arch/arm/plat-samsung/include/plat/irq.h +++ /dev/null | |||
@@ -1,116 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-samsung/include/plat/irq.h | ||
2 | * | ||
3 | * Copyright (c) 2004-2005 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Header file for S3C24XX CPU IRQ support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/io.h> | ||
14 | |||
15 | #include <mach/hardware.h> | ||
16 | #include <mach/regs-irq.h> | ||
17 | #include <mach/regs-gpio.h> | ||
18 | |||
19 | #define irqdbf(x...) | ||
20 | #define irqdbf2(x...) | ||
21 | |||
22 | #define EXTINT_OFF (IRQ_EINT4 - 4) | ||
23 | |||
24 | /* these are exported for arch/arm/mach-* usage */ | ||
25 | extern struct irq_chip s3c_irq_level_chip; | ||
26 | extern struct irq_chip s3c_irq_chip; | ||
27 | |||
28 | static inline void s3c_irqsub_mask(unsigned int irqno, | ||
29 | unsigned int parentbit, | ||
30 | int subcheck) | ||
31 | { | ||
32 | unsigned long mask; | ||
33 | unsigned long submask; | ||
34 | |||
35 | submask = __raw_readl(S3C2410_INTSUBMSK); | ||
36 | mask = __raw_readl(S3C2410_INTMSK); | ||
37 | |||
38 | submask |= (1UL << (irqno - IRQ_S3CUART_RX0)); | ||
39 | |||
40 | /* check to see if we need to mask the parent IRQ */ | ||
41 | |||
42 | if ((submask & subcheck) == subcheck) | ||
43 | __raw_writel(mask | parentbit, S3C2410_INTMSK); | ||
44 | |||
45 | /* write back masks */ | ||
46 | __raw_writel(submask, S3C2410_INTSUBMSK); | ||
47 | |||
48 | } | ||
49 | |||
50 | static inline void s3c_irqsub_unmask(unsigned int irqno, | ||
51 | unsigned int parentbit) | ||
52 | { | ||
53 | unsigned long mask; | ||
54 | unsigned long submask; | ||
55 | |||
56 | submask = __raw_readl(S3C2410_INTSUBMSK); | ||
57 | mask = __raw_readl(S3C2410_INTMSK); | ||
58 | |||
59 | submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0)); | ||
60 | mask &= ~parentbit; | ||
61 | |||
62 | /* write back masks */ | ||
63 | __raw_writel(submask, S3C2410_INTSUBMSK); | ||
64 | __raw_writel(mask, S3C2410_INTMSK); | ||
65 | } | ||
66 | |||
67 | |||
68 | static inline void s3c_irqsub_maskack(unsigned int irqno, | ||
69 | unsigned int parentmask, | ||
70 | unsigned int group) | ||
71 | { | ||
72 | unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); | ||
73 | |||
74 | s3c_irqsub_mask(irqno, parentmask, group); | ||
75 | |||
76 | __raw_writel(bit, S3C2410_SUBSRCPND); | ||
77 | |||
78 | /* only ack parent if we've got all the irqs (seems we must | ||
79 | * ack, all and hope that the irq system retriggers ok when | ||
80 | * the interrupt goes off again) | ||
81 | */ | ||
82 | |||
83 | if (1) { | ||
84 | __raw_writel(parentmask, S3C2410_SRCPND); | ||
85 | __raw_writel(parentmask, S3C2410_INTPND); | ||
86 | } | ||
87 | } | ||
88 | |||
89 | static inline void s3c_irqsub_ack(unsigned int irqno, | ||
90 | unsigned int parentmask, | ||
91 | unsigned int group) | ||
92 | { | ||
93 | unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); | ||
94 | |||
95 | __raw_writel(bit, S3C2410_SUBSRCPND); | ||
96 | |||
97 | /* only ack parent if we've got all the irqs (seems we must | ||
98 | * ack, all and hope that the irq system retriggers ok when | ||
99 | * the interrupt goes off again) | ||
100 | */ | ||
101 | |||
102 | if (1) { | ||
103 | __raw_writel(parentmask, S3C2410_SRCPND); | ||
104 | __raw_writel(parentmask, S3C2410_INTPND); | ||
105 | } | ||
106 | } | ||
107 | |||
108 | /* exported for use in arch/arm/mach-s3c2410 */ | ||
109 | |||
110 | #ifdef CONFIG_PM | ||
111 | extern int s3c_irq_wake(struct irq_data *data, unsigned int state); | ||
112 | #else | ||
113 | #define s3c_irq_wake NULL | ||
114 | #endif | ||
115 | |||
116 | extern int s3c_irqext_type(struct irq_data *d, unsigned int type); | ||
diff --git a/arch/arm/plat-samsung/include/plat/rtc-core.h b/arch/arm/plat-samsung/include/plat/rtc-core.h index 21d8594d37ca..7b542f7b7938 100644 --- a/arch/arm/plat-samsung/include/plat/rtc-core.h +++ b/arch/arm/plat-samsung/include/plat/rtc-core.h | |||
@@ -19,7 +19,7 @@ | |||
19 | /* re-define device name depending on support. */ | 19 | /* re-define device name depending on support. */ |
20 | static inline void s3c_rtc_setname(char *name) | 20 | static inline void s3c_rtc_setname(char *name) |
21 | { | 21 | { |
22 | #if defined(CONFIG_SAMSUNG_DEV_RTC) || defined(CONFIG_PLAT_S3C24XX) | 22 | #if defined(CONFIG_S3C_DEV_RTC) || defined(CONFIG_PLAT_S3C24XX) |
23 | s3c_device_rtc.name = name; | 23 | s3c_device_rtc.name = name; |
24 | #endif | 24 | #endif |
25 | } | 25 | } |
diff --git a/arch/arm/plat-samsung/include/plat/s3c2410.h b/arch/arm/plat-samsung/include/plat/s3c2410.h deleted file mode 100644 index 55b0e5f51e97..000000000000 --- a/arch/arm/plat-samsung/include/plat/s3c2410.h +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-samsung/include/plat/s3c2410.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Header file for s3c2410 machine directory | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #ifdef CONFIG_CPU_S3C2410 | ||
15 | |||
16 | extern int s3c2410_init(void); | ||
17 | extern int s3c2410a_init(void); | ||
18 | |||
19 | extern void s3c2410_map_io(void); | ||
20 | |||
21 | extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
22 | |||
23 | extern void s3c2410_init_clocks(int xtal); | ||
24 | |||
25 | #else | ||
26 | #define s3c2410_init_clocks NULL | ||
27 | #define s3c2410_init_uarts NULL | ||
28 | #define s3c2410_map_io NULL | ||
29 | #define s3c2410_init NULL | ||
30 | #define s3c2410a_init NULL | ||
31 | #endif | ||
diff --git a/arch/arm/plat-samsung/include/plat/s3c2412.h b/arch/arm/plat-samsung/include/plat/s3c2412.h deleted file mode 100644 index cbae50ddacc8..000000000000 --- a/arch/arm/plat-samsung/include/plat/s3c2412.h +++ /dev/null | |||
@@ -1,32 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-samsung/include/plat/s3c2412.h | ||
2 | * | ||
3 | * Copyright (c) 2006 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Header file for s3c2412 cpu support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifdef CONFIG_CPU_S3C2412 | ||
14 | |||
15 | extern int s3c2412_init(void); | ||
16 | |||
17 | extern void s3c2412_map_io(void); | ||
18 | |||
19 | extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
20 | |||
21 | extern void s3c2412_init_clocks(int xtal); | ||
22 | |||
23 | extern int s3c2412_baseclk_add(void); | ||
24 | |||
25 | extern void s3c2412_restart(char mode, const char *cmd); | ||
26 | #else | ||
27 | #define s3c2412_init_clocks NULL | ||
28 | #define s3c2412_init_uarts NULL | ||
29 | #define s3c2412_map_io NULL | ||
30 | #define s3c2412_init NULL | ||
31 | #define s3c2412_restart NULL | ||
32 | #endif | ||
diff --git a/arch/arm/plat-samsung/include/plat/s3c2416.h b/arch/arm/plat-samsung/include/plat/s3c2416.h deleted file mode 100644 index f27399a3c68d..000000000000 --- a/arch/arm/plat-samsung/include/plat/s3c2416.h +++ /dev/null | |||
@@ -1,37 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-samsung/include/plat/s3c2416.h | ||
2 | * | ||
3 | * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com> | ||
4 | * | ||
5 | * Header file for s3c2416 cpu support | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #ifdef CONFIG_CPU_S3C2416 | ||
13 | |||
14 | struct s3c2410_uartcfg; | ||
15 | |||
16 | extern int s3c2416_init(void); | ||
17 | |||
18 | extern void s3c2416_map_io(void); | ||
19 | |||
20 | extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
21 | |||
22 | extern void s3c2416_init_clocks(int xtal); | ||
23 | |||
24 | extern int s3c2416_baseclk_add(void); | ||
25 | |||
26 | extern void s3c2416_restart(char mode, const char *cmd); | ||
27 | |||
28 | extern void s3c2416_init_irq(void); | ||
29 | extern struct syscore_ops s3c2416_irq_syscore_ops; | ||
30 | |||
31 | #else | ||
32 | #define s3c2416_init_clocks NULL | ||
33 | #define s3c2416_init_uarts NULL | ||
34 | #define s3c2416_map_io NULL | ||
35 | #define s3c2416_init NULL | ||
36 | #define s3c2416_restart NULL | ||
37 | #endif | ||
diff --git a/arch/arm/plat-samsung/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h deleted file mode 100644 index 71b88ec48956..000000000000 --- a/arch/arm/plat-samsung/include/plat/s3c2443.h +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-samsung/include/plat/s3c2443.h | ||
2 | * | ||
3 | * Copyright (c) 2004-2005 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Header file for s3c2443 cpu support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifdef CONFIG_CPU_S3C2443 | ||
14 | |||
15 | struct s3c2410_uartcfg; | ||
16 | |||
17 | extern int s3c2443_init(void); | ||
18 | |||
19 | extern void s3c2443_map_io(void); | ||
20 | |||
21 | extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
22 | |||
23 | extern void s3c2443_init_clocks(int xtal); | ||
24 | |||
25 | extern int s3c2443_baseclk_add(void); | ||
26 | |||
27 | extern void s3c2443_restart(char mode, const char *cmd); | ||
28 | |||
29 | extern void s3c2443_init_irq(void); | ||
30 | #else | ||
31 | #define s3c2443_init_clocks NULL | ||
32 | #define s3c2443_init_uarts NULL | ||
33 | #define s3c2443_map_io NULL | ||
34 | #define s3c2443_init NULL | ||
35 | #define s3c2443_restart NULL | ||
36 | #endif | ||
diff --git a/arch/arm/plat-samsung/include/plat/s3c244x.h b/arch/arm/plat-samsung/include/plat/s3c244x.h deleted file mode 100644 index ea0c961b7603..000000000000 --- a/arch/arm/plat-samsung/include/plat/s3c244x.h +++ /dev/null | |||
@@ -1,42 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-samsung/include/plat/s3c244x.h | ||
2 | * | ||
3 | * Copyright (c) 2004-2005 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Header file for S3C2440 and S3C2442 cpu support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) | ||
14 | |||
15 | extern void s3c244x_map_io(void); | ||
16 | |||
17 | extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
18 | |||
19 | extern void s3c244x_init_clocks(int xtal); | ||
20 | |||
21 | #else | ||
22 | #define s3c244x_init_clocks NULL | ||
23 | #define s3c244x_init_uarts NULL | ||
24 | #endif | ||
25 | |||
26 | #ifdef CONFIG_CPU_S3C2440 | ||
27 | extern int s3c2440_init(void); | ||
28 | |||
29 | extern void s3c2440_map_io(void); | ||
30 | #else | ||
31 | #define s3c2440_init NULL | ||
32 | #define s3c2440_map_io NULL | ||
33 | #endif | ||
34 | |||
35 | #ifdef CONFIG_CPU_S3C2442 | ||
36 | extern int s3c2442_init(void); | ||
37 | |||
38 | extern void s3c2442_map_io(void); | ||
39 | #else | ||
40 | #define s3c2442_init NULL | ||
41 | #define s3c2442_map_io NULL | ||
42 | #endif | ||
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 9b87f38fc4f4..5560586abec0 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h | |||
@@ -206,7 +206,7 @@ static inline void s3c6400_default_sdhci2(void) { } | |||
206 | 206 | ||
207 | /* S5P64X0 SDHCI setup */ | 207 | /* S5P64X0 SDHCI setup */ |
208 | 208 | ||
209 | #ifdef CONFIG_S5P64X0_SETUP_SDHCI | 209 | #ifdef CONFIG_S5P64X0_SETUP_SDHCI_GPIO |
210 | static inline void s5p64x0_default_sdhci0(void) | 210 | static inline void s5p64x0_default_sdhci0(void) |
211 | { | 211 | { |
212 | #ifdef CONFIG_S3C_DEV_HSMMC | 212 | #ifdef CONFIG_S3C_DEV_HSMMC |
@@ -241,7 +241,7 @@ static inline void s5p64x0_default_sdhci1(void) { } | |||
241 | static inline void s5p6440_default_sdhci2(void) { } | 241 | static inline void s5p6440_default_sdhci2(void) { } |
242 | static inline void s5p6450_default_sdhci2(void) { } | 242 | static inline void s5p6450_default_sdhci2(void) { } |
243 | 243 | ||
244 | #endif /* CONFIG_S5P64X0_SETUP_SDHCI */ | 244 | #endif /* CONFIG_S5P64X0_SETUP_SDHCI_GPIO */ |
245 | 245 | ||
246 | /* S5PC100 SDHCI setup */ | 246 | /* S5PC100 SDHCI setup */ |
247 | 247 | ||
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c index f980cf3d2baa..5d205e74e495 100644 --- a/arch/arm/plat-samsung/irq-vic-timer.c +++ b/arch/arm/plat-samsung/irq-vic-timer.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/kernel.h> | 16 | #include <linux/kernel.h> |
17 | #include <linux/interrupt.h> | 17 | #include <linux/interrupt.h> |
18 | #include <linux/irq.h> | 18 | #include <linux/irq.h> |
19 | #include <linux/irqchip/chained_irq.h> | ||
19 | #include <linux/io.h> | 20 | #include <linux/io.h> |
20 | 21 | ||
21 | #include <mach/map.h> | 22 | #include <mach/map.h> |
@@ -23,8 +24,6 @@ | |||
23 | #include <plat/irq-vic-timer.h> | 24 | #include <plat/irq-vic-timer.h> |
24 | #include <plat/regs-timer.h> | 25 | #include <plat/regs-timer.h> |
25 | 26 | ||
26 | #include <asm/mach/irq.h> | ||
27 | |||
28 | static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) | 27 | static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) |
29 | { | 28 | { |
30 | struct irq_chip *chip = irq_get_chip(irq); | 29 | struct irq_chip *chip = irq_get_chip(irq); |
diff --git a/arch/arm/plat-samsung/s5p-irq-gpioint.c b/arch/arm/plat-samsung/s5p-irq-gpioint.c index bae56131a50a..fafdb059043a 100644 --- a/arch/arm/plat-samsung/s5p-irq-gpioint.c +++ b/arch/arm/plat-samsung/s5p-irq-gpioint.c | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
15 | #include <linux/interrupt.h> | 15 | #include <linux/interrupt.h> |
16 | #include <linux/irq.h> | 16 | #include <linux/irq.h> |
17 | #include <linux/irqchip/chained_irq.h> | ||
17 | #include <linux/io.h> | 18 | #include <linux/io.h> |
18 | #include <linux/gpio.h> | 19 | #include <linux/gpio.h> |
19 | #include <linux/slab.h> | 20 | #include <linux/slab.h> |
@@ -22,8 +23,6 @@ | |||
22 | #include <plat/gpio-core.h> | 23 | #include <plat/gpio-core.h> |
23 | #include <plat/gpio-cfg.h> | 24 | #include <plat/gpio-cfg.h> |
24 | 25 | ||
25 | #include <asm/mach/irq.h> | ||
26 | |||
27 | #define GPIO_BASE(chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u)) | 26 | #define GPIO_BASE(chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u)) |
28 | 27 | ||
29 | #define CON_OFFSET 0x700 | 28 | #define CON_OFFSET 0x700 |
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c index f2ac15561778..1e1b2d769748 100644 --- a/arch/arm/plat-versatile/platsmp.c +++ b/arch/arm/plat-versatile/platsmp.c | |||
@@ -14,7 +14,6 @@ | |||
14 | #include <linux/device.h> | 14 | #include <linux/device.h> |
15 | #include <linux/jiffies.h> | 15 | #include <linux/jiffies.h> |
16 | #include <linux/smp.h> | 16 | #include <linux/smp.h> |
17 | #include <linux/irqchip/arm-gic.h> | ||
18 | 17 | ||
19 | #include <asm/cacheflush.h> | 18 | #include <asm/cacheflush.h> |
20 | #include <asm/smp_plat.h> | 19 | #include <asm/smp_plat.h> |
@@ -37,13 +36,6 @@ static DEFINE_SPINLOCK(boot_lock); | |||
37 | void __cpuinit versatile_secondary_init(unsigned int cpu) | 36 | void __cpuinit versatile_secondary_init(unsigned int cpu) |
38 | { | 37 | { |
39 | /* | 38 | /* |
40 | * if any interrupts are already enabled for the primary | ||
41 | * core (e.g. timer irq), then they will not have been enabled | ||
42 | * for us: do so | ||
43 | */ | ||
44 | gic_secondary_init(0); | ||
45 | |||
46 | /* | ||
47 | * let the primary processor know we're out of the | 39 | * let the primary processor know we're out of the |
48 | * pen, then head off into the C entry point | 40 | * pen, then head off into the C entry point |
49 | */ | 41 | */ |
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c index b5c06f9766f6..f6a74872f14e 100644 --- a/drivers/clk/mxs/clk-imx23.c +++ b/drivers/clk/mxs/clk-imx23.c | |||
@@ -15,12 +15,15 @@ | |||
15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
17 | #include <linux/of.h> | 17 | #include <linux/of.h> |
18 | #include <mach/common.h> | 18 | #include <linux/of_address.h> |
19 | #include <mach/mx23.h> | ||
20 | #include "clk.h" | 19 | #include "clk.h" |
21 | 20 | ||
22 | #define DIGCTRL MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR) | 21 | static void __iomem *clkctrl; |
23 | #define CLKCTRL MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR) | 22 | static void __iomem *digctrl; |
23 | |||
24 | #define CLKCTRL clkctrl | ||
25 | #define DIGCTRL digctrl | ||
26 | |||
24 | #define PLLCTRL0 (CLKCTRL + 0x0000) | 27 | #define PLLCTRL0 (CLKCTRL + 0x0000) |
25 | #define CPU (CLKCTRL + 0x0020) | 28 | #define CPU (CLKCTRL + 0x0020) |
26 | #define HBUS (CLKCTRL + 0x0030) | 29 | #define HBUS (CLKCTRL + 0x0030) |
@@ -48,10 +51,10 @@ static void __init clk_misc_init(void) | |||
48 | u32 val; | 51 | u32 val; |
49 | 52 | ||
50 | /* Gate off cpu clock in WFI for power saving */ | 53 | /* Gate off cpu clock in WFI for power saving */ |
51 | __mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU); | 54 | writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); |
52 | 55 | ||
53 | /* Clear BYPASS for SAIF */ | 56 | /* Clear BYPASS for SAIF */ |
54 | __mxs_clrl(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ); | 57 | writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR); |
55 | 58 | ||
56 | /* SAIF has to use frac div for functional operation */ | 59 | /* SAIF has to use frac div for functional operation */ |
57 | val = readl_relaxed(SAIF); | 60 | val = readl_relaxed(SAIF); |
@@ -62,14 +65,14 @@ static void __init clk_misc_init(void) | |||
62 | * Source ssp clock from ref_io than ref_xtal, | 65 | * Source ssp clock from ref_io than ref_xtal, |
63 | * as ref_xtal only provides 24 MHz as maximum. | 66 | * as ref_xtal only provides 24 MHz as maximum. |
64 | */ | 67 | */ |
65 | __mxs_clrl(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ); | 68 | writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR); |
66 | 69 | ||
67 | /* | 70 | /* |
68 | * 480 MHz seems too high to be ssp clock source directly, | 71 | * 480 MHz seems too high to be ssp clock source directly, |
69 | * so set frac to get a 288 MHz ref_io. | 72 | * so set frac to get a 288 MHz ref_io. |
70 | */ | 73 | */ |
71 | __mxs_clrl(0x3f << BP_FRAC_IOFRAC, FRAC); | 74 | writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR); |
72 | __mxs_setl(30 << BP_FRAC_IOFRAC, FRAC); | 75 | writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET); |
73 | } | 76 | } |
74 | 77 | ||
75 | static const char *sel_pll[] __initconst = { "pll", "ref_xtal", }; | 78 | static const char *sel_pll[] __initconst = { "pll", "ref_xtal", }; |
@@ -101,6 +104,14 @@ int __init mx23_clocks_init(void) | |||
101 | struct device_node *np; | 104 | struct device_node *np; |
102 | u32 i; | 105 | u32 i; |
103 | 106 | ||
107 | np = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl"); | ||
108 | digctrl = of_iomap(np, 0); | ||
109 | WARN_ON(!digctrl); | ||
110 | |||
111 | np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl"); | ||
112 | clkctrl = of_iomap(np, 0); | ||
113 | WARN_ON(!clkctrl); | ||
114 | |||
104 | clk_misc_init(); | 115 | clk_misc_init(); |
105 | 116 | ||
106 | clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); | 117 | clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); |
@@ -153,19 +164,12 @@ int __init mx23_clocks_init(void) | |||
153 | return PTR_ERR(clks[i]); | 164 | return PTR_ERR(clks[i]); |
154 | } | 165 | } |
155 | 166 | ||
156 | np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl"); | 167 | clk_data.clks = clks; |
157 | if (np) { | 168 | clk_data.clk_num = ARRAY_SIZE(clks); |
158 | clk_data.clks = clks; | 169 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |
159 | clk_data.clk_num = ARRAY_SIZE(clks); | ||
160 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | ||
161 | } | ||
162 | |||
163 | clk_register_clkdev(clks[clk32k], NULL, "timrot"); | ||
164 | 170 | ||
165 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) | 171 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) |
166 | clk_prepare_enable(clks[clks_init_on[i]]); | 172 | clk_prepare_enable(clks[clks_init_on[i]]); |
167 | 173 | ||
168 | mxs_timer_init(); | ||
169 | |||
170 | return 0; | 174 | return 0; |
171 | } | 175 | } |
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c index 76ce6c6d1113..d0e5eed146de 100644 --- a/drivers/clk/mxs/clk-imx28.c +++ b/drivers/clk/mxs/clk-imx28.c | |||
@@ -15,11 +15,12 @@ | |||
15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
17 | #include <linux/of.h> | 17 | #include <linux/of.h> |
18 | #include <mach/common.h> | 18 | #include <linux/of_address.h> |
19 | #include <mach/mx28.h> | ||
20 | #include "clk.h" | 19 | #include "clk.h" |
21 | 20 | ||
22 | #define CLKCTRL MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR) | 21 | static void __iomem *clkctrl; |
22 | #define CLKCTRL clkctrl | ||
23 | |||
23 | #define PLL0CTRL0 (CLKCTRL + 0x0000) | 24 | #define PLL0CTRL0 (CLKCTRL + 0x0000) |
24 | #define PLL1CTRL0 (CLKCTRL + 0x0020) | 25 | #define PLL1CTRL0 (CLKCTRL + 0x0020) |
25 | #define PLL2CTRL0 (CLKCTRL + 0x0040) | 26 | #define PLL2CTRL0 (CLKCTRL + 0x0040) |
@@ -53,7 +54,8 @@ | |||
53 | #define BP_FRAC0_IO1FRAC 16 | 54 | #define BP_FRAC0_IO1FRAC 16 |
54 | #define BP_FRAC0_IO0FRAC 24 | 55 | #define BP_FRAC0_IO0FRAC 24 |
55 | 56 | ||
56 | #define DIGCTRL MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR) | 57 | static void __iomem *digctrl; |
58 | #define DIGCTRL digctrl | ||
57 | #define BP_SAIF_CLKMUX 10 | 59 | #define BP_SAIF_CLKMUX 10 |
58 | 60 | ||
59 | /* | 61 | /* |
@@ -72,8 +74,8 @@ int mxs_saif_clkmux_select(unsigned int clkmux) | |||
72 | if (clkmux > 0x3) | 74 | if (clkmux > 0x3) |
73 | return -EINVAL; | 75 | return -EINVAL; |
74 | 76 | ||
75 | __mxs_clrl(0x3 << BP_SAIF_CLKMUX, DIGCTRL); | 77 | writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR); |
76 | __mxs_setl(clkmux << BP_SAIF_CLKMUX, DIGCTRL); | 78 | writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET); |
77 | 79 | ||
78 | return 0; | 80 | return 0; |
79 | } | 81 | } |
@@ -83,13 +85,13 @@ static void __init clk_misc_init(void) | |||
83 | u32 val; | 85 | u32 val; |
84 | 86 | ||
85 | /* Gate off cpu clock in WFI for power saving */ | 87 | /* Gate off cpu clock in WFI for power saving */ |
86 | __mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU); | 88 | writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); |
87 | 89 | ||
88 | /* 0 is a bad default value for a divider */ | 90 | /* 0 is a bad default value for a divider */ |
89 | __mxs_setl(1 << BP_ENET_DIV_TIME, ENET); | 91 | writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET); |
90 | 92 | ||
91 | /* Clear BYPASS for SAIF */ | 93 | /* Clear BYPASS for SAIF */ |
92 | __mxs_clrl(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ); | 94 | writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR); |
93 | 95 | ||
94 | /* SAIF has to use frac div for functional operation */ | 96 | /* SAIF has to use frac div for functional operation */ |
95 | val = readl_relaxed(SAIF0); | 97 | val = readl_relaxed(SAIF0); |
@@ -109,7 +111,7 @@ static void __init clk_misc_init(void) | |||
109 | * Source ssp clock from ref_io than ref_xtal, | 111 | * Source ssp clock from ref_io than ref_xtal, |
110 | * as ref_xtal only provides 24 MHz as maximum. | 112 | * as ref_xtal only provides 24 MHz as maximum. |
111 | */ | 113 | */ |
112 | __mxs_clrl(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ); | 114 | writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR); |
113 | 115 | ||
114 | /* | 116 | /* |
115 | * 480 MHz seems too high to be ssp clock source directly, | 117 | * 480 MHz seems too high to be ssp clock source directly, |
@@ -156,6 +158,14 @@ int __init mx28_clocks_init(void) | |||
156 | struct device_node *np; | 158 | struct device_node *np; |
157 | u32 i; | 159 | u32 i; |
158 | 160 | ||
161 | np = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl"); | ||
162 | digctrl = of_iomap(np, 0); | ||
163 | WARN_ON(!digctrl); | ||
164 | |||
165 | np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl"); | ||
166 | clkctrl = of_iomap(np, 0); | ||
167 | WARN_ON(!clkctrl); | ||
168 | |||
159 | clk_misc_init(); | 169 | clk_misc_init(); |
160 | 170 | ||
161 | clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); | 171 | clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); |
@@ -231,20 +241,14 @@ int __init mx28_clocks_init(void) | |||
231 | return PTR_ERR(clks[i]); | 241 | return PTR_ERR(clks[i]); |
232 | } | 242 | } |
233 | 243 | ||
234 | np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl"); | 244 | clk_data.clks = clks; |
235 | if (np) { | 245 | clk_data.clk_num = ARRAY_SIZE(clks); |
236 | clk_data.clks = clks; | 246 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |
237 | clk_data.clk_num = ARRAY_SIZE(clks); | ||
238 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | ||
239 | } | ||
240 | 247 | ||
241 | clk_register_clkdev(clks[xbus], NULL, "timrot"); | ||
242 | clk_register_clkdev(clks[enet_out], NULL, "enet_out"); | 248 | clk_register_clkdev(clks[enet_out], NULL, "enet_out"); |
243 | 249 | ||
244 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) | 250 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) |
245 | clk_prepare_enable(clks[clks_init_on[i]]); | 251 | clk_prepare_enable(clks[clks_init_on[i]]); |
246 | 252 | ||
247 | mxs_timer_init(); | ||
248 | |||
249 | return 0; | 253 | return 0; |
250 | } | 254 | } |
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index e507ab7df60b..9002185a0a1a 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig | |||
@@ -25,7 +25,7 @@ config DW_APB_TIMER_OF | |||
25 | config ARMADA_370_XP_TIMER | 25 | config ARMADA_370_XP_TIMER |
26 | bool | 26 | bool |
27 | 27 | ||
28 | config SUNXI_TIMER | 28 | config SUN4I_TIMER |
29 | bool | 29 | bool |
30 | 30 | ||
31 | config VT8500_TIMER | 31 | config VT8500_TIMER |
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 96e25319659b..4897f243a000 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile | |||
@@ -16,7 +16,8 @@ obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o | |||
16 | obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o | 16 | obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o |
17 | obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o | 17 | obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o |
18 | obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o | 18 | obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o |
19 | obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o | 19 | obj-$(CONFIG_ARCH_MXS) += mxs_timer.o |
20 | obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o | ||
20 | obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o | 21 | obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o |
21 | obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o | 22 | obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o |
22 | obj-$(CONFIG_ARCH_BCM) += bcm_kona_timer.o | 23 | obj-$(CONFIG_ARCH_BCM) += bcm_kona_timer.o |
diff --git a/drivers/clocksource/bcm2835_timer.c b/drivers/clocksource/bcm2835_timer.c index 50c68fef944b..766611d29945 100644 --- a/drivers/clocksource/bcm2835_timer.c +++ b/drivers/clocksource/bcm2835_timer.c | |||
@@ -95,23 +95,13 @@ static irqreturn_t bcm2835_time_interrupt(int irq, void *dev_id) | |||
95 | } | 95 | } |
96 | } | 96 | } |
97 | 97 | ||
98 | static struct of_device_id bcm2835_time_match[] __initconst = { | 98 | static void __init bcm2835_timer_init(struct device_node *node) |
99 | { .compatible = "brcm,bcm2835-system-timer" }, | ||
100 | {} | ||
101 | }; | ||
102 | |||
103 | static void __init bcm2835_timer_init(void) | ||
104 | { | 99 | { |
105 | struct device_node *node; | ||
106 | void __iomem *base; | 100 | void __iomem *base; |
107 | u32 freq; | 101 | u32 freq; |
108 | int irq; | 102 | int irq; |
109 | struct bcm2835_timer *timer; | 103 | struct bcm2835_timer *timer; |
110 | 104 | ||
111 | node = of_find_matching_node(NULL, bcm2835_time_match); | ||
112 | if (!node) | ||
113 | panic("No bcm2835 timer node"); | ||
114 | |||
115 | base = of_iomap(node, 0); | 105 | base = of_iomap(node, 0); |
116 | if (!base) | 106 | if (!base) |
117 | panic("Can't remap registers"); | 107 | panic("Can't remap registers"); |
diff --git a/drivers/clocksource/clksrc-of.c b/drivers/clocksource/clksrc-of.c index bdabdaa8d00f..37f5325bec95 100644 --- a/drivers/clocksource/clksrc-of.c +++ b/drivers/clocksource/clksrc-of.c | |||
@@ -16,6 +16,7 @@ | |||
16 | 16 | ||
17 | #include <linux/init.h> | 17 | #include <linux/init.h> |
18 | #include <linux/of.h> | 18 | #include <linux/of.h> |
19 | #include <linux/clocksource.h> | ||
19 | 20 | ||
20 | extern struct of_device_id __clksrc_of_table[]; | 21 | extern struct of_device_id __clksrc_of_table[]; |
21 | 22 | ||
@@ -26,10 +27,10 @@ void __init clocksource_of_init(void) | |||
26 | { | 27 | { |
27 | struct device_node *np; | 28 | struct device_node *np; |
28 | const struct of_device_id *match; | 29 | const struct of_device_id *match; |
29 | void (*init_func)(void); | 30 | clocksource_of_init_fn init_func; |
30 | 31 | ||
31 | for_each_matching_node_and_match(np, __clksrc_of_table, &match) { | 32 | for_each_matching_node_and_match(np, __clksrc_of_table, &match) { |
32 | init_func = match->data; | 33 | init_func = match->data; |
33 | init_func(); | 34 | init_func(np); |
34 | } | 35 | } |
35 | } | 36 | } |
diff --git a/arch/arm/mach-mxs/timer.c b/drivers/clocksource/mxs_timer.c index 421020498a1b..02af4204af86 100644 --- a/arch/arm/mach-mxs/timer.c +++ b/drivers/clocksource/mxs_timer.c | |||
@@ -26,12 +26,12 @@ | |||
26 | #include <linux/clockchips.h> | 26 | #include <linux/clockchips.h> |
27 | #include <linux/clk.h> | 27 | #include <linux/clk.h> |
28 | #include <linux/of.h> | 28 | #include <linux/of.h> |
29 | #include <linux/of_address.h> | ||
29 | #include <linux/of_irq.h> | 30 | #include <linux/of_irq.h> |
31 | #include <linux/stmp_device.h> | ||
30 | 32 | ||
31 | #include <asm/mach/time.h> | 33 | #include <asm/mach/time.h> |
32 | #include <asm/sched_clock.h> | 34 | #include <asm/sched_clock.h> |
33 | #include <mach/mxs.h> | ||
34 | #include <mach/common.h> | ||
35 | 35 | ||
36 | /* | 36 | /* |
37 | * There are 2 versions of the timrot on Freescale MXS-based SoCs. | 37 | * There are 2 versions of the timrot on Freescale MXS-based SoCs. |
@@ -79,25 +79,25 @@ | |||
79 | static struct clock_event_device mxs_clockevent_device; | 79 | static struct clock_event_device mxs_clockevent_device; |
80 | static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED; | 80 | static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED; |
81 | 81 | ||
82 | static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR); | 82 | static void __iomem *mxs_timrot_base; |
83 | static u32 timrot_major_version; | 83 | static u32 timrot_major_version; |
84 | 84 | ||
85 | static inline void timrot_irq_disable(void) | 85 | static inline void timrot_irq_disable(void) |
86 | { | 86 | { |
87 | __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN, | 87 | __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base + |
88 | mxs_timrot_base + HW_TIMROT_TIMCTRLn(0)); | 88 | HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR); |
89 | } | 89 | } |
90 | 90 | ||
91 | static inline void timrot_irq_enable(void) | 91 | static inline void timrot_irq_enable(void) |
92 | { | 92 | { |
93 | __mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN, | 93 | __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base + |
94 | mxs_timrot_base + HW_TIMROT_TIMCTRLn(0)); | 94 | HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET); |
95 | } | 95 | } |
96 | 96 | ||
97 | static void timrot_irq_acknowledge(void) | 97 | static void timrot_irq_acknowledge(void) |
98 | { | 98 | { |
99 | __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ, | 99 | __raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base + |
100 | mxs_timrot_base + HW_TIMROT_TIMCTRLn(0)); | 100 | HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR); |
101 | } | 101 | } |
102 | 102 | ||
103 | static cycle_t timrotv1_get_cycles(struct clocksource *cs) | 103 | static cycle_t timrotv1_get_cycles(struct clocksource *cs) |
@@ -242,19 +242,15 @@ static int __init mxs_clocksource_init(struct clk *timer_clk) | |||
242 | return 0; | 242 | return 0; |
243 | } | 243 | } |
244 | 244 | ||
245 | void __init mxs_timer_init(void) | 245 | static void __init mxs_timer_init(struct device_node *np) |
246 | { | 246 | { |
247 | struct device_node *np; | ||
248 | struct clk *timer_clk; | 247 | struct clk *timer_clk; |
249 | int irq; | 248 | int irq; |
250 | 249 | ||
251 | np = of_find_compatible_node(NULL, NULL, "fsl,timrot"); | 250 | mxs_timrot_base = of_iomap(np, 0); |
252 | if (!np) { | 251 | WARN_ON(!mxs_timrot_base); |
253 | pr_err("%s: failed find timrot node\n", __func__); | ||
254 | return; | ||
255 | } | ||
256 | 252 | ||
257 | timer_clk = clk_get_sys("timrot", NULL); | 253 | timer_clk = of_clk_get(np, 0); |
258 | if (IS_ERR(timer_clk)) { | 254 | if (IS_ERR(timer_clk)) { |
259 | pr_err("%s: failed to get clk\n", __func__); | 255 | pr_err("%s: failed to get clk\n", __func__); |
260 | return; | 256 | return; |
@@ -265,11 +261,12 @@ void __init mxs_timer_init(void) | |||
265 | /* | 261 | /* |
266 | * Initialize timers to a known state | 262 | * Initialize timers to a known state |
267 | */ | 263 | */ |
268 | mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL); | 264 | stmp_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL); |
269 | 265 | ||
270 | /* get timrot version */ | 266 | /* get timrot version */ |
271 | timrot_major_version = __raw_readl(mxs_timrot_base + | 267 | timrot_major_version = __raw_readl(mxs_timrot_base + |
272 | (cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET : | 268 | (of_device_is_compatible(np, "fsl,imx23-timrot") ? |
269 | MX23_TIMROT_VERSION_OFFSET : | ||
273 | MX28_TIMROT_VERSION_OFFSET)); | 270 | MX28_TIMROT_VERSION_OFFSET)); |
274 | timrot_major_version >>= BP_TIMROT_MAJOR_VERSION; | 271 | timrot_major_version >>= BP_TIMROT_MAJOR_VERSION; |
275 | 272 | ||
@@ -304,3 +301,4 @@ void __init mxs_timer_init(void) | |||
304 | irq = irq_of_parse_and_map(np, 0); | 301 | irq = irq_of_parse_and_map(np, 0); |
305 | setup_irq(irq, &mxs_timer_irq); | 302 | setup_irq(irq, &mxs_timer_irq); |
306 | } | 303 | } |
304 | CLOCKSOURCE_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init); | ||
diff --git a/drivers/clocksource/sunxi_timer.c b/drivers/clocksource/sun4i_timer.c index 0ce85e29769b..d4674e78ef35 100644 --- a/drivers/clocksource/sunxi_timer.c +++ b/drivers/clocksource/sun4i_timer.c | |||
@@ -22,66 +22,64 @@ | |||
22 | #include <linux/of.h> | 22 | #include <linux/of.h> |
23 | #include <linux/of_address.h> | 23 | #include <linux/of_address.h> |
24 | #include <linux/of_irq.h> | 24 | #include <linux/of_irq.h> |
25 | #include <linux/sunxi_timer.h> | ||
26 | #include <linux/clk/sunxi.h> | ||
27 | 25 | ||
28 | #define TIMER_CTL_REG 0x00 | 26 | #define TIMER_IRQ_EN_REG 0x00 |
29 | #define TIMER_CTL_ENABLE (1 << 0) | 27 | #define TIMER_IRQ_EN(val) (1 << val) |
30 | #define TIMER_IRQ_ST_REG 0x04 | 28 | #define TIMER_IRQ_ST_REG 0x04 |
31 | #define TIMER0_CTL_REG 0x10 | 29 | #define TIMER_CTL_REG(val) (0x10 * val + 0x10) |
32 | #define TIMER0_CTL_ENABLE (1 << 0) | 30 | #define TIMER_CTL_ENABLE (1 << 0) |
33 | #define TIMER0_CTL_AUTORELOAD (1 << 1) | 31 | #define TIMER_CTL_AUTORELOAD (1 << 1) |
34 | #define TIMER0_CTL_ONESHOT (1 << 7) | 32 | #define TIMER_CTL_ONESHOT (1 << 7) |
35 | #define TIMER0_INTVAL_REG 0x14 | 33 | #define TIMER_INTVAL_REG(val) (0x10 * val + 0x14) |
36 | #define TIMER0_CNTVAL_REG 0x18 | 34 | #define TIMER_CNTVAL_REG(val) (0x10 * val + 0x18) |
37 | 35 | ||
38 | #define TIMER_SCAL 16 | 36 | #define TIMER_SCAL 16 |
39 | 37 | ||
40 | static void __iomem *timer_base; | 38 | static void __iomem *timer_base; |
41 | 39 | ||
42 | static void sunxi_clkevt_mode(enum clock_event_mode mode, | 40 | static void sun4i_clkevt_mode(enum clock_event_mode mode, |
43 | struct clock_event_device *clk) | 41 | struct clock_event_device *clk) |
44 | { | 42 | { |
45 | u32 u = readl(timer_base + TIMER0_CTL_REG); | 43 | u32 u = readl(timer_base + TIMER_CTL_REG(0)); |
46 | 44 | ||
47 | switch (mode) { | 45 | switch (mode) { |
48 | case CLOCK_EVT_MODE_PERIODIC: | 46 | case CLOCK_EVT_MODE_PERIODIC: |
49 | u &= ~(TIMER0_CTL_ONESHOT); | 47 | u &= ~(TIMER_CTL_ONESHOT); |
50 | writel(u | TIMER0_CTL_ENABLE, timer_base + TIMER0_CTL_REG); | 48 | writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0)); |
51 | break; | 49 | break; |
52 | 50 | ||
53 | case CLOCK_EVT_MODE_ONESHOT: | 51 | case CLOCK_EVT_MODE_ONESHOT: |
54 | writel(u | TIMER0_CTL_ONESHOT, timer_base + TIMER0_CTL_REG); | 52 | writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0)); |
55 | break; | 53 | break; |
56 | case CLOCK_EVT_MODE_UNUSED: | 54 | case CLOCK_EVT_MODE_UNUSED: |
57 | case CLOCK_EVT_MODE_SHUTDOWN: | 55 | case CLOCK_EVT_MODE_SHUTDOWN: |
58 | default: | 56 | default: |
59 | writel(u & ~(TIMER0_CTL_ENABLE), timer_base + TIMER0_CTL_REG); | 57 | writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0)); |
60 | break; | 58 | break; |
61 | } | 59 | } |
62 | } | 60 | } |
63 | 61 | ||
64 | static int sunxi_clkevt_next_event(unsigned long evt, | 62 | static int sun4i_clkevt_next_event(unsigned long evt, |
65 | struct clock_event_device *unused) | 63 | struct clock_event_device *unused) |
66 | { | 64 | { |
67 | u32 u = readl(timer_base + TIMER0_CTL_REG); | 65 | u32 u = readl(timer_base + TIMER_CTL_REG(0)); |
68 | writel(evt, timer_base + TIMER0_CNTVAL_REG); | 66 | writel(evt, timer_base + TIMER_CNTVAL_REG(0)); |
69 | writel(u | TIMER0_CTL_ENABLE | TIMER0_CTL_AUTORELOAD, | 67 | writel(u | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD, |
70 | timer_base + TIMER0_CTL_REG); | 68 | timer_base + TIMER_CTL_REG(0)); |
71 | 69 | ||
72 | return 0; | 70 | return 0; |
73 | } | 71 | } |
74 | 72 | ||
75 | static struct clock_event_device sunxi_clockevent = { | 73 | static struct clock_event_device sun4i_clockevent = { |
76 | .name = "sunxi_tick", | 74 | .name = "sun4i_tick", |
77 | .rating = 300, | 75 | .rating = 300, |
78 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | 76 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
79 | .set_mode = sunxi_clkevt_mode, | 77 | .set_mode = sun4i_clkevt_mode, |
80 | .set_next_event = sunxi_clkevt_next_event, | 78 | .set_next_event = sun4i_clkevt_next_event, |
81 | }; | 79 | }; |
82 | 80 | ||
83 | 81 | ||
84 | static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id) | 82 | static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id) |
85 | { | 83 | { |
86 | struct clock_event_device *evt = (struct clock_event_device *)dev_id; | 84 | struct clock_event_device *evt = (struct clock_event_device *)dev_id; |
87 | 85 | ||
@@ -91,30 +89,20 @@ static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id) | |||
91 | return IRQ_HANDLED; | 89 | return IRQ_HANDLED; |
92 | } | 90 | } |
93 | 91 | ||
94 | static struct irqaction sunxi_timer_irq = { | 92 | static struct irqaction sun4i_timer_irq = { |
95 | .name = "sunxi_timer0", | 93 | .name = "sun4i_timer0", |
96 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | 94 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
97 | .handler = sunxi_timer_interrupt, | 95 | .handler = sun4i_timer_interrupt, |
98 | .dev_id = &sunxi_clockevent, | 96 | .dev_id = &sun4i_clockevent, |
99 | }; | ||
100 | |||
101 | static struct of_device_id sunxi_timer_dt_ids[] = { | ||
102 | { .compatible = "allwinner,sunxi-timer" }, | ||
103 | { } | ||
104 | }; | 97 | }; |
105 | 98 | ||
106 | void __init sunxi_timer_init(void) | 99 | static void __init sun4i_timer_init(struct device_node *node) |
107 | { | 100 | { |
108 | struct device_node *node; | ||
109 | unsigned long rate = 0; | 101 | unsigned long rate = 0; |
110 | struct clk *clk; | 102 | struct clk *clk; |
111 | int ret, irq; | 103 | int ret, irq; |
112 | u32 val; | 104 | u32 val; |
113 | 105 | ||
114 | node = of_find_matching_node(NULL, sunxi_timer_dt_ids); | ||
115 | if (!node) | ||
116 | panic("No sunxi timer node"); | ||
117 | |||
118 | timer_base = of_iomap(node, 0); | 106 | timer_base = of_iomap(node, 0); |
119 | if (!timer_base) | 107 | if (!timer_base) |
120 | panic("Can't map registers"); | 108 | panic("Can't map registers"); |
@@ -123,8 +111,6 @@ void __init sunxi_timer_init(void) | |||
123 | if (irq <= 0) | 111 | if (irq <= 0) |
124 | panic("Can't parse IRQ"); | 112 | panic("Can't parse IRQ"); |
125 | 113 | ||
126 | sunxi_init_clocks(); | ||
127 | |||
128 | clk = of_clk_get(node, 0); | 114 | clk = of_clk_get(node, 0); |
129 | if (IS_ERR(clk)) | 115 | if (IS_ERR(clk)) |
130 | panic("Can't get timer clock"); | 116 | panic("Can't get timer clock"); |
@@ -132,29 +118,31 @@ void __init sunxi_timer_init(void) | |||
132 | rate = clk_get_rate(clk); | 118 | rate = clk_get_rate(clk); |
133 | 119 | ||
134 | writel(rate / (TIMER_SCAL * HZ), | 120 | writel(rate / (TIMER_SCAL * HZ), |
135 | timer_base + TIMER0_INTVAL_REG); | 121 | timer_base + TIMER_INTVAL_REG(0)); |
136 | 122 | ||
137 | /* set clock source to HOSC, 16 pre-division */ | 123 | /* set clock source to HOSC, 16 pre-division */ |
138 | val = readl(timer_base + TIMER0_CTL_REG); | 124 | val = readl(timer_base + TIMER_CTL_REG(0)); |
139 | val &= ~(0x07 << 4); | 125 | val &= ~(0x07 << 4); |
140 | val &= ~(0x03 << 2); | 126 | val &= ~(0x03 << 2); |
141 | val |= (4 << 4) | (1 << 2); | 127 | val |= (4 << 4) | (1 << 2); |
142 | writel(val, timer_base + TIMER0_CTL_REG); | 128 | writel(val, timer_base + TIMER_CTL_REG(0)); |
143 | 129 | ||
144 | /* set mode to auto reload */ | 130 | /* set mode to auto reload */ |
145 | val = readl(timer_base + TIMER0_CTL_REG); | 131 | val = readl(timer_base + TIMER_CTL_REG(0)); |
146 | writel(val | TIMER0_CTL_AUTORELOAD, timer_base + TIMER0_CTL_REG); | 132 | writel(val | TIMER_CTL_AUTORELOAD, timer_base + TIMER_CTL_REG(0)); |
147 | 133 | ||
148 | ret = setup_irq(irq, &sunxi_timer_irq); | 134 | ret = setup_irq(irq, &sun4i_timer_irq); |
149 | if (ret) | 135 | if (ret) |
150 | pr_warn("failed to setup irq %d\n", irq); | 136 | pr_warn("failed to setup irq %d\n", irq); |
151 | 137 | ||
152 | /* Enable timer0 interrupt */ | 138 | /* Enable timer0 interrupt */ |
153 | val = readl(timer_base + TIMER_CTL_REG); | 139 | val = readl(timer_base + TIMER_IRQ_EN_REG); |
154 | writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG); | 140 | writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG); |
155 | 141 | ||
156 | sunxi_clockevent.cpumask = cpumask_of(0); | 142 | sun4i_clockevent.cpumask = cpumask_of(0); |
157 | 143 | ||
158 | clockevents_config_and_register(&sunxi_clockevent, rate / TIMER_SCAL, | 144 | clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL, |
159 | 0x1, 0xff); | 145 | 0x1, 0xff); |
160 | } | 146 | } |
147 | CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer", | ||
148 | sun4i_timer_init); | ||
diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c index 0bde03feb095..ae877b021b54 100644 --- a/drivers/clocksource/tegra20_timer.c +++ b/drivers/clocksource/tegra20_timer.c | |||
@@ -154,29 +154,12 @@ static struct irqaction tegra_timer_irq = { | |||
154 | .dev_id = &tegra_clockevent, | 154 | .dev_id = &tegra_clockevent, |
155 | }; | 155 | }; |
156 | 156 | ||
157 | static const struct of_device_id timer_match[] __initconst = { | 157 | static void __init tegra20_init_timer(struct device_node *np) |
158 | { .compatible = "nvidia,tegra20-timer" }, | ||
159 | {} | ||
160 | }; | ||
161 | |||
162 | static const struct of_device_id rtc_match[] __initconst = { | ||
163 | { .compatible = "nvidia,tegra20-rtc" }, | ||
164 | {} | ||
165 | }; | ||
166 | |||
167 | static void __init tegra20_init_timer(void) | ||
168 | { | 158 | { |
169 | struct device_node *np; | ||
170 | struct clk *clk; | 159 | struct clk *clk; |
171 | unsigned long rate; | 160 | unsigned long rate; |
172 | int ret; | 161 | int ret; |
173 | 162 | ||
174 | np = of_find_matching_node(NULL, timer_match); | ||
175 | if (!np) { | ||
176 | pr_err("Failed to find timer DT node\n"); | ||
177 | BUG(); | ||
178 | } | ||
179 | |||
180 | timer_reg_base = of_iomap(np, 0); | 163 | timer_reg_base = of_iomap(np, 0); |
181 | if (!timer_reg_base) { | 164 | if (!timer_reg_base) { |
182 | pr_err("Can't map timer registers\n"); | 165 | pr_err("Can't map timer registers\n"); |
@@ -189,7 +172,7 @@ static void __init tegra20_init_timer(void) | |||
189 | BUG(); | 172 | BUG(); |
190 | } | 173 | } |
191 | 174 | ||
192 | clk = clk_get_sys("timer", NULL); | 175 | clk = of_clk_get(np, 0); |
193 | if (IS_ERR(clk)) { | 176 | if (IS_ERR(clk)) { |
194 | pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n"); | 177 | pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n"); |
195 | rate = 12000000; | 178 | rate = 12000000; |
@@ -200,30 +183,6 @@ static void __init tegra20_init_timer(void) | |||
200 | 183 | ||
201 | of_node_put(np); | 184 | of_node_put(np); |
202 | 185 | ||
203 | np = of_find_matching_node(NULL, rtc_match); | ||
204 | if (!np) { | ||
205 | pr_err("Failed to find RTC DT node\n"); | ||
206 | BUG(); | ||
207 | } | ||
208 | |||
209 | rtc_base = of_iomap(np, 0); | ||
210 | if (!rtc_base) { | ||
211 | pr_err("Can't map RTC registers"); | ||
212 | BUG(); | ||
213 | } | ||
214 | |||
215 | /* | ||
216 | * rtc registers are used by read_persistent_clock, keep the rtc clock | ||
217 | * enabled | ||
218 | */ | ||
219 | clk = clk_get_sys("rtc-tegra", NULL); | ||
220 | if (IS_ERR(clk)) | ||
221 | pr_warn("Unable to get rtc-tegra clock\n"); | ||
222 | else | ||
223 | clk_prepare_enable(clk); | ||
224 | |||
225 | of_node_put(np); | ||
226 | |||
227 | switch (rate) { | 186 | switch (rate) { |
228 | case 12000000: | 187 | case 12000000: |
229 | timer_writel(0x000b, TIMERUS_USEC_CFG); | 188 | timer_writel(0x000b, TIMERUS_USEC_CFG); |
@@ -259,12 +218,34 @@ static void __init tegra20_init_timer(void) | |||
259 | tegra_clockevent.irq = tegra_timer_irq.irq; | 218 | tegra_clockevent.irq = tegra_timer_irq.irq; |
260 | clockevents_config_and_register(&tegra_clockevent, 1000000, | 219 | clockevents_config_and_register(&tegra_clockevent, 1000000, |
261 | 0x1, 0x1fffffff); | 220 | 0x1, 0x1fffffff); |
262 | #ifdef CONFIG_HAVE_ARM_TWD | 221 | } |
263 | twd_local_timer_of_register(); | 222 | CLOCKSOURCE_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); |
264 | #endif | 223 | |
224 | static void __init tegra20_init_rtc(struct device_node *np) | ||
225 | { | ||
226 | struct clk *clk; | ||
227 | |||
228 | rtc_base = of_iomap(np, 0); | ||
229 | if (!rtc_base) { | ||
230 | pr_err("Can't map RTC registers"); | ||
231 | BUG(); | ||
232 | } | ||
233 | |||
234 | /* | ||
235 | * rtc registers are used by read_persistent_clock, keep the rtc clock | ||
236 | * enabled | ||
237 | */ | ||
238 | clk = of_clk_get(np, 0); | ||
239 | if (IS_ERR(clk)) | ||
240 | pr_warn("Unable to get rtc-tegra clock\n"); | ||
241 | else | ||
242 | clk_prepare_enable(clk); | ||
243 | |||
244 | of_node_put(np); | ||
245 | |||
265 | register_persistent_clock(NULL, tegra_read_persistent_clock); | 246 | register_persistent_clock(NULL, tegra_read_persistent_clock); |
266 | } | 247 | } |
267 | CLOCKSOURCE_OF_DECLARE(tegra20, "nvidia,tegra20-timer", tegra20_init_timer); | 248 | CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); |
268 | 249 | ||
269 | #ifdef CONFIG_PM | 250 | #ifdef CONFIG_PM |
270 | static u32 usec_config; | 251 | static u32 usec_config; |
diff --git a/drivers/clocksource/vt8500_timer.c b/drivers/clocksource/vt8500_timer.c index 8efc86b5b5dd..64f553f04fa4 100644 --- a/drivers/clocksource/vt8500_timer.c +++ b/drivers/clocksource/vt8500_timer.c | |||
@@ -129,22 +129,10 @@ static struct irqaction irq = { | |||
129 | .dev_id = &clockevent, | 129 | .dev_id = &clockevent, |
130 | }; | 130 | }; |
131 | 131 | ||
132 | static struct of_device_id vt8500_timer_ids[] = { | 132 | static void __init vt8500_timer_init(struct device_node *np) |
133 | { .compatible = "via,vt8500-timer" }, | ||
134 | { } | ||
135 | }; | ||
136 | |||
137 | static void __init vt8500_timer_init(void) | ||
138 | { | 133 | { |
139 | struct device_node *np; | ||
140 | int timer_irq; | 134 | int timer_irq; |
141 | 135 | ||
142 | np = of_find_matching_node(NULL, vt8500_timer_ids); | ||
143 | if (!np) { | ||
144 | pr_err("%s: Timer description missing from Device Tree\n", | ||
145 | __func__); | ||
146 | return; | ||
147 | } | ||
148 | regbase = of_iomap(np, 0); | 136 | regbase = of_iomap(np, 0); |
149 | if (!regbase) { | 137 | if (!regbase) { |
150 | pr_err("%s: Missing iobase description in Device Tree\n", | 138 | pr_err("%s: Missing iobase description in Device Tree\n", |
@@ -177,4 +165,4 @@ static void __init vt8500_timer_init(void) | |||
177 | 4, 0xf0000000); | 165 | 4, 0xf0000000); |
178 | } | 166 | } |
179 | 167 | ||
180 | CLOCKSOURCE_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init) | 168 | CLOCKSOURCE_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init); |
diff --git a/drivers/gpio/gpio-msm-v1.c b/drivers/gpio/gpio-msm-v1.c index 52a4d4286eba..c798585a3fe5 100644 --- a/drivers/gpio/gpio-msm-v1.c +++ b/drivers/gpio/gpio-msm-v1.c | |||
@@ -1,6 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2007 Google, Inc. | 2 | * Copyright (C) 2007 Google, Inc. |
3 | * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. | 3 | * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved. |
4 | * | 4 | * |
5 | * This software is licensed under the terms of the GNU General Public | 5 | * This software is licensed under the terms of the GNU General Public |
6 | * License version 2, as published by the Free Software Foundation, and | 6 | * License version 2, as published by the Free Software Foundation, and |
@@ -19,9 +19,10 @@ | |||
19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
20 | #include <linux/irq.h> | 20 | #include <linux/irq.h> |
21 | #include <linux/module.h> | 21 | #include <linux/module.h> |
22 | #include <mach/cpu.h> | 22 | #include <linux/device.h> |
23 | #include <linux/platform_device.h> | ||
24 | |||
23 | #include <mach/msm_gpiomux.h> | 25 | #include <mach/msm_gpiomux.h> |
24 | #include <mach/msm_iomap.h> | ||
25 | 26 | ||
26 | /* see 80-VA736-2 Rev C pp 695-751 | 27 | /* see 80-VA736-2 Rev C pp 695-751 |
27 | ** | 28 | ** |
@@ -34,10 +35,10 @@ | |||
34 | ** macros. | 35 | ** macros. |
35 | */ | 36 | */ |
36 | 37 | ||
37 | #define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off)) | 38 | #define MSM_GPIO1_REG(off) (off) |
38 | #define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off)) | 39 | #define MSM_GPIO2_REG(off) (off) |
39 | #define MSM_GPIO1_SHADOW_REG(off) (MSM_GPIO1_BASE + 0x800 + (off)) | 40 | #define MSM_GPIO1_SHADOW_REG(off) (off) |
40 | #define MSM_GPIO2_SHADOW_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off)) | 41 | #define MSM_GPIO2_SHADOW_REG(off) (off) |
41 | 42 | ||
42 | /* | 43 | /* |
43 | * MSM7X00 registers | 44 | * MSM7X00 registers |
@@ -276,16 +277,14 @@ | |||
276 | 277 | ||
277 | #define MSM_GPIO_BANK(soc, bank, first, last) \ | 278 | #define MSM_GPIO_BANK(soc, bank, first, last) \ |
278 | { \ | 279 | { \ |
279 | .regs = { \ | 280 | .regs[MSM_GPIO_OUT] = soc##_GPIO_OUT_##bank, \ |
280 | .out = soc##_GPIO_OUT_##bank, \ | 281 | .regs[MSM_GPIO_IN] = soc##_GPIO_IN_##bank, \ |
281 | .in = soc##_GPIO_IN_##bank, \ | 282 | .regs[MSM_GPIO_INT_STATUS] = soc##_GPIO_INT_STATUS_##bank, \ |
282 | .int_status = soc##_GPIO_INT_STATUS_##bank, \ | 283 | .regs[MSM_GPIO_INT_CLEAR] = soc##_GPIO_INT_CLEAR_##bank, \ |
283 | .int_clear = soc##_GPIO_INT_CLEAR_##bank, \ | 284 | .regs[MSM_GPIO_INT_EN] = soc##_GPIO_INT_EN_##bank, \ |
284 | .int_en = soc##_GPIO_INT_EN_##bank, \ | 285 | .regs[MSM_GPIO_INT_EDGE] = soc##_GPIO_INT_EDGE_##bank, \ |
285 | .int_edge = soc##_GPIO_INT_EDGE_##bank, \ | 286 | .regs[MSM_GPIO_INT_POS] = soc##_GPIO_INT_POS_##bank, \ |
286 | .int_pos = soc##_GPIO_INT_POS_##bank, \ | 287 | .regs[MSM_GPIO_OE] = soc##_GPIO_OE_##bank, \ |
287 | .oe = soc##_GPIO_OE_##bank, \ | ||
288 | }, \ | ||
289 | .chip = { \ | 288 | .chip = { \ |
290 | .base = (first), \ | 289 | .base = (first), \ |
291 | .ngpio = (last) - (first) + 1, \ | 290 | .ngpio = (last) - (first) + 1, \ |
@@ -301,39 +300,57 @@ | |||
301 | 300 | ||
302 | #define MSM_GPIO_BROKEN_INT_CLEAR 1 | 301 | #define MSM_GPIO_BROKEN_INT_CLEAR 1 |
303 | 302 | ||
304 | struct msm_gpio_regs { | 303 | enum msm_gpio_reg { |
305 | void __iomem *out; | 304 | MSM_GPIO_IN, |
306 | void __iomem *in; | 305 | MSM_GPIO_OUT, |
307 | void __iomem *int_status; | 306 | MSM_GPIO_INT_STATUS, |
308 | void __iomem *int_clear; | 307 | MSM_GPIO_INT_CLEAR, |
309 | void __iomem *int_en; | 308 | MSM_GPIO_INT_EN, |
310 | void __iomem *int_edge; | 309 | MSM_GPIO_INT_EDGE, |
311 | void __iomem *int_pos; | 310 | MSM_GPIO_INT_POS, |
312 | void __iomem *oe; | 311 | MSM_GPIO_OE, |
312 | MSM_GPIO_REG_NR | ||
313 | }; | 313 | }; |
314 | 314 | ||
315 | struct msm_gpio_chip { | 315 | struct msm_gpio_chip { |
316 | spinlock_t lock; | 316 | spinlock_t lock; |
317 | struct gpio_chip chip; | 317 | struct gpio_chip chip; |
318 | struct msm_gpio_regs regs; | 318 | unsigned long regs[MSM_GPIO_REG_NR]; |
319 | #if MSM_GPIO_BROKEN_INT_CLEAR | 319 | #if MSM_GPIO_BROKEN_INT_CLEAR |
320 | unsigned int_status_copy; | 320 | unsigned int_status_copy; |
321 | #endif | 321 | #endif |
322 | unsigned int both_edge_detect; | 322 | unsigned int both_edge_detect; |
323 | unsigned int int_enable[2]; /* 0: awake, 1: sleep */ | 323 | unsigned int int_enable[2]; /* 0: awake, 1: sleep */ |
324 | void __iomem *base; | ||
325 | }; | ||
326 | |||
327 | struct msm_gpio_initdata { | ||
328 | struct msm_gpio_chip *chips; | ||
329 | int count; | ||
324 | }; | 330 | }; |
325 | 331 | ||
332 | static void msm_gpio_writel(struct msm_gpio_chip *chip, u32 val, | ||
333 | enum msm_gpio_reg reg) | ||
334 | { | ||
335 | writel(val, chip->base + chip->regs[reg]); | ||
336 | } | ||
337 | |||
338 | static u32 msm_gpio_readl(struct msm_gpio_chip *chip, enum msm_gpio_reg reg) | ||
339 | { | ||
340 | return readl(chip->base + chip->regs[reg]); | ||
341 | } | ||
342 | |||
326 | static int msm_gpio_write(struct msm_gpio_chip *msm_chip, | 343 | static int msm_gpio_write(struct msm_gpio_chip *msm_chip, |
327 | unsigned offset, unsigned on) | 344 | unsigned offset, unsigned on) |
328 | { | 345 | { |
329 | unsigned mask = BIT(offset); | 346 | unsigned mask = BIT(offset); |
330 | unsigned val; | 347 | unsigned val; |
331 | 348 | ||
332 | val = readl(msm_chip->regs.out); | 349 | val = msm_gpio_readl(msm_chip, MSM_GPIO_OUT); |
333 | if (on) | 350 | if (on) |
334 | writel(val | mask, msm_chip->regs.out); | 351 | msm_gpio_writel(msm_chip, val | mask, MSM_GPIO_OUT); |
335 | else | 352 | else |
336 | writel(val & ~mask, msm_chip->regs.out); | 353 | msm_gpio_writel(msm_chip, val & ~mask, MSM_GPIO_OUT); |
337 | return 0; | 354 | return 0; |
338 | } | 355 | } |
339 | 356 | ||
@@ -342,13 +359,13 @@ static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip) | |||
342 | int loop_limit = 100; | 359 | int loop_limit = 100; |
343 | unsigned pol, val, val2, intstat; | 360 | unsigned pol, val, val2, intstat; |
344 | do { | 361 | do { |
345 | val = readl(msm_chip->regs.in); | 362 | val = msm_gpio_readl(msm_chip, MSM_GPIO_IN); |
346 | pol = readl(msm_chip->regs.int_pos); | 363 | pol = msm_gpio_readl(msm_chip, MSM_GPIO_INT_POS); |
347 | pol = (pol & ~msm_chip->both_edge_detect) | | 364 | pol = (pol & ~msm_chip->both_edge_detect) | |
348 | (~val & msm_chip->both_edge_detect); | 365 | (~val & msm_chip->both_edge_detect); |
349 | writel(pol, msm_chip->regs.int_pos); | 366 | msm_gpio_writel(msm_chip, pol, MSM_GPIO_INT_POS); |
350 | intstat = readl(msm_chip->regs.int_status); | 367 | intstat = msm_gpio_readl(msm_chip, MSM_GPIO_INT_STATUS); |
351 | val2 = readl(msm_chip->regs.in); | 368 | val2 = msm_gpio_readl(msm_chip, MSM_GPIO_IN); |
352 | if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0) | 369 | if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0) |
353 | return; | 370 | return; |
354 | } while (loop_limit-- > 0); | 371 | } while (loop_limit-- > 0); |
@@ -365,10 +382,11 @@ static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip, | |||
365 | /* Save interrupts that already triggered before we loose them. */ | 382 | /* Save interrupts that already triggered before we loose them. */ |
366 | /* Any interrupt that triggers between the read of int_status */ | 383 | /* Any interrupt that triggers between the read of int_status */ |
367 | /* and the write to int_clear will still be lost though. */ | 384 | /* and the write to int_clear will still be lost though. */ |
368 | msm_chip->int_status_copy |= readl(msm_chip->regs.int_status); | 385 | msm_chip->int_status_copy |= |
386 | msm_gpio_readl(msm_chip, MSM_GPIO_INT_STATUS); | ||
369 | msm_chip->int_status_copy &= ~bit; | 387 | msm_chip->int_status_copy &= ~bit; |
370 | #endif | 388 | #endif |
371 | writel(bit, msm_chip->regs.int_clear); | 389 | msm_gpio_writel(msm_chip, bit, MSM_GPIO_INT_CLEAR); |
372 | msm_gpio_update_both_edge_detect(msm_chip); | 390 | msm_gpio_update_both_edge_detect(msm_chip); |
373 | return 0; | 391 | return 0; |
374 | } | 392 | } |
@@ -377,10 +395,12 @@ static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |||
377 | { | 395 | { |
378 | struct msm_gpio_chip *msm_chip; | 396 | struct msm_gpio_chip *msm_chip; |
379 | unsigned long irq_flags; | 397 | unsigned long irq_flags; |
398 | u32 val; | ||
380 | 399 | ||
381 | msm_chip = container_of(chip, struct msm_gpio_chip, chip); | 400 | msm_chip = container_of(chip, struct msm_gpio_chip, chip); |
382 | spin_lock_irqsave(&msm_chip->lock, irq_flags); | 401 | spin_lock_irqsave(&msm_chip->lock, irq_flags); |
383 | writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe); | 402 | val = msm_gpio_readl(msm_chip, MSM_GPIO_OE) & ~BIT(offset); |
403 | msm_gpio_writel(msm_chip, val, MSM_GPIO_OE); | ||
384 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); | 404 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); |
385 | return 0; | 405 | return 0; |
386 | } | 406 | } |
@@ -390,11 +410,13 @@ msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |||
390 | { | 410 | { |
391 | struct msm_gpio_chip *msm_chip; | 411 | struct msm_gpio_chip *msm_chip; |
392 | unsigned long irq_flags; | 412 | unsigned long irq_flags; |
413 | u32 val; | ||
393 | 414 | ||
394 | msm_chip = container_of(chip, struct msm_gpio_chip, chip); | 415 | msm_chip = container_of(chip, struct msm_gpio_chip, chip); |
395 | spin_lock_irqsave(&msm_chip->lock, irq_flags); | 416 | spin_lock_irqsave(&msm_chip->lock, irq_flags); |
396 | msm_gpio_write(msm_chip, offset, value); | 417 | msm_gpio_write(msm_chip, offset, value); |
397 | writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe); | 418 | val = msm_gpio_readl(msm_chip, MSM_GPIO_OE) | BIT(offset); |
419 | msm_gpio_writel(msm_chip, val, MSM_GPIO_OE); | ||
398 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); | 420 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); |
399 | return 0; | 421 | return 0; |
400 | } | 422 | } |
@@ -404,7 +426,7 @@ static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) | |||
404 | struct msm_gpio_chip *msm_chip; | 426 | struct msm_gpio_chip *msm_chip; |
405 | 427 | ||
406 | msm_chip = container_of(chip, struct msm_gpio_chip, chip); | 428 | msm_chip = container_of(chip, struct msm_gpio_chip, chip); |
407 | return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0; | 429 | return (msm_gpio_readl(msm_chip, MSM_GPIO_IN) & (1U << offset)) ? 1 : 0; |
408 | } | 430 | } |
409 | 431 | ||
410 | static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | 432 | static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
@@ -450,6 +472,11 @@ static struct msm_gpio_chip msm_gpio_chips_msm7x01[] = { | |||
450 | MSM_GPIO_BANK(MSM7X00, 5, 107, 121), | 472 | MSM_GPIO_BANK(MSM7X00, 5, 107, 121), |
451 | }; | 473 | }; |
452 | 474 | ||
475 | static struct msm_gpio_initdata msm_gpio_7x01_init = { | ||
476 | .chips = msm_gpio_chips_msm7x01, | ||
477 | .count = ARRAY_SIZE(msm_gpio_chips_msm7x01), | ||
478 | }; | ||
479 | |||
453 | static struct msm_gpio_chip msm_gpio_chips_msm7x30[] = { | 480 | static struct msm_gpio_chip msm_gpio_chips_msm7x30[] = { |
454 | MSM_GPIO_BANK(MSM7X30, 0, 0, 15), | 481 | MSM_GPIO_BANK(MSM7X30, 0, 0, 15), |
455 | MSM_GPIO_BANK(MSM7X30, 1, 16, 43), | 482 | MSM_GPIO_BANK(MSM7X30, 1, 16, 43), |
@@ -461,6 +488,11 @@ static struct msm_gpio_chip msm_gpio_chips_msm7x30[] = { | |||
461 | MSM_GPIO_BANK(MSM7X30, 7, 151, 181), | 488 | MSM_GPIO_BANK(MSM7X30, 7, 151, 181), |
462 | }; | 489 | }; |
463 | 490 | ||
491 | static struct msm_gpio_initdata msm_gpio_7x30_init = { | ||
492 | .chips = msm_gpio_chips_msm7x30, | ||
493 | .count = ARRAY_SIZE(msm_gpio_chips_msm7x30), | ||
494 | }; | ||
495 | |||
464 | static struct msm_gpio_chip msm_gpio_chips_qsd8x50[] = { | 496 | static struct msm_gpio_chip msm_gpio_chips_qsd8x50[] = { |
465 | MSM_GPIO_BANK(QSD8X50, 0, 0, 15), | 497 | MSM_GPIO_BANK(QSD8X50, 0, 0, 15), |
466 | MSM_GPIO_BANK(QSD8X50, 1, 16, 42), | 498 | MSM_GPIO_BANK(QSD8X50, 1, 16, 42), |
@@ -472,6 +504,11 @@ static struct msm_gpio_chip msm_gpio_chips_qsd8x50[] = { | |||
472 | MSM_GPIO_BANK(QSD8X50, 7, 153, 164), | 504 | MSM_GPIO_BANK(QSD8X50, 7, 153, 164), |
473 | }; | 505 | }; |
474 | 506 | ||
507 | static struct msm_gpio_initdata msm_gpio_8x50_init = { | ||
508 | .chips = msm_gpio_chips_qsd8x50, | ||
509 | .count = ARRAY_SIZE(msm_gpio_chips_qsd8x50), | ||
510 | }; | ||
511 | |||
475 | static void msm_gpio_irq_ack(struct irq_data *d) | 512 | static void msm_gpio_irq_ack(struct irq_data *d) |
476 | { | 513 | { |
477 | unsigned long irq_flags; | 514 | unsigned long irq_flags; |
@@ -490,10 +527,10 @@ static void msm_gpio_irq_mask(struct irq_data *d) | |||
490 | 527 | ||
491 | spin_lock_irqsave(&msm_chip->lock, irq_flags); | 528 | spin_lock_irqsave(&msm_chip->lock, irq_flags); |
492 | /* level triggered interrupts are also latched */ | 529 | /* level triggered interrupts are also latched */ |
493 | if (!(readl(msm_chip->regs.int_edge) & BIT(offset))) | 530 | if (!(msm_gpio_readl(msm_chip, MSM_GPIO_INT_EDGE) & BIT(offset))) |
494 | msm_gpio_clear_detect_status(msm_chip, offset); | 531 | msm_gpio_clear_detect_status(msm_chip, offset); |
495 | msm_chip->int_enable[0] &= ~BIT(offset); | 532 | msm_chip->int_enable[0] &= ~BIT(offset); |
496 | writel(msm_chip->int_enable[0], msm_chip->regs.int_en); | 533 | msm_gpio_writel(msm_chip, msm_chip->int_enable[0], MSM_GPIO_INT_EN); |
497 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); | 534 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); |
498 | } | 535 | } |
499 | 536 | ||
@@ -505,10 +542,10 @@ static void msm_gpio_irq_unmask(struct irq_data *d) | |||
505 | 542 | ||
506 | spin_lock_irqsave(&msm_chip->lock, irq_flags); | 543 | spin_lock_irqsave(&msm_chip->lock, irq_flags); |
507 | /* level triggered interrupts are also latched */ | 544 | /* level triggered interrupts are also latched */ |
508 | if (!(readl(msm_chip->regs.int_edge) & BIT(offset))) | 545 | if (!(msm_gpio_readl(msm_chip, MSM_GPIO_INT_EDGE) & BIT(offset))) |
509 | msm_gpio_clear_detect_status(msm_chip, offset); | 546 | msm_gpio_clear_detect_status(msm_chip, offset); |
510 | msm_chip->int_enable[0] |= BIT(offset); | 547 | msm_chip->int_enable[0] |= BIT(offset); |
511 | writel(msm_chip->int_enable[0], msm_chip->regs.int_en); | 548 | msm_gpio_writel(msm_chip, msm_chip->int_enable[0], MSM_GPIO_INT_EN); |
512 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); | 549 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); |
513 | } | 550 | } |
514 | 551 | ||
@@ -537,12 +574,12 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) | |||
537 | unsigned val, mask = BIT(offset); | 574 | unsigned val, mask = BIT(offset); |
538 | 575 | ||
539 | spin_lock_irqsave(&msm_chip->lock, irq_flags); | 576 | spin_lock_irqsave(&msm_chip->lock, irq_flags); |
540 | val = readl(msm_chip->regs.int_edge); | 577 | val = msm_gpio_readl(msm_chip, MSM_GPIO_INT_EDGE); |
541 | if (flow_type & IRQ_TYPE_EDGE_BOTH) { | 578 | if (flow_type & IRQ_TYPE_EDGE_BOTH) { |
542 | writel(val | mask, msm_chip->regs.int_edge); | 579 | msm_gpio_writel(msm_chip, val | mask, MSM_GPIO_INT_EDGE); |
543 | __irq_set_handler_locked(d->irq, handle_edge_irq); | 580 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
544 | } else { | 581 | } else { |
545 | writel(val & ~mask, msm_chip->regs.int_edge); | 582 | msm_gpio_writel(msm_chip, val & ~mask, MSM_GPIO_INT_EDGE); |
546 | __irq_set_handler_locked(d->irq, handle_level_irq); | 583 | __irq_set_handler_locked(d->irq, handle_level_irq); |
547 | } | 584 | } |
548 | if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | 585 | if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { |
@@ -550,11 +587,12 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) | |||
550 | msm_gpio_update_both_edge_detect(msm_chip); | 587 | msm_gpio_update_both_edge_detect(msm_chip); |
551 | } else { | 588 | } else { |
552 | msm_chip->both_edge_detect &= ~mask; | 589 | msm_chip->both_edge_detect &= ~mask; |
553 | val = readl(msm_chip->regs.int_pos); | 590 | val = msm_gpio_readl(msm_chip, MSM_GPIO_INT_POS); |
554 | if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH)) | 591 | if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH)) |
555 | writel(val | mask, msm_chip->regs.int_pos); | 592 | val |= mask; |
556 | else | 593 | else |
557 | writel(val & ~mask, msm_chip->regs.int_pos); | 594 | val &= ~mask; |
595 | msm_gpio_writel(msm_chip, val, MSM_GPIO_INT_POS); | ||
558 | } | 596 | } |
559 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); | 597 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); |
560 | return 0; | 598 | return 0; |
@@ -567,7 +605,7 @@ static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
567 | 605 | ||
568 | for (i = 0; i < msm_gpio_count; i++) { | 606 | for (i = 0; i < msm_gpio_count; i++) { |
569 | struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i]; | 607 | struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i]; |
570 | val = readl(msm_chip->regs.int_status); | 608 | val = msm_gpio_readl(msm_chip, MSM_GPIO_INT_STATUS); |
571 | val &= msm_chip->int_enable[0]; | 609 | val &= msm_chip->int_enable[0]; |
572 | while (val) { | 610 | while (val) { |
573 | mask = val & -val; | 611 | mask = val & -val; |
@@ -592,22 +630,36 @@ static struct irq_chip msm_gpio_irq_chip = { | |||
592 | .irq_set_type = msm_gpio_irq_set_type, | 630 | .irq_set_type = msm_gpio_irq_set_type, |
593 | }; | 631 | }; |
594 | 632 | ||
595 | static int __init msm_init_gpio(void) | 633 | static int __devinit gpio_msm_v1_probe(struct platform_device *pdev) |
596 | { | 634 | { |
597 | int i, j = 0; | 635 | int i, j = 0; |
598 | 636 | const struct platform_device_id *dev_id = platform_get_device_id(pdev); | |
599 | if (cpu_is_msm7x01()) { | 637 | struct msm_gpio_initdata *data; |
600 | msm_gpio_chips = msm_gpio_chips_msm7x01; | 638 | int irq1, irq2; |
601 | msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_msm7x01); | 639 | struct resource *res; |
602 | } else if (cpu_is_msm7x30()) { | 640 | void __iomem *base1, __iomem *base2; |
603 | msm_gpio_chips = msm_gpio_chips_msm7x30; | 641 | |
604 | msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_msm7x30); | 642 | data = (struct msm_gpio_initdata *)dev_id->driver_data; |
605 | } else if (cpu_is_qsd8x50()) { | 643 | msm_gpio_chips = data->chips; |
606 | msm_gpio_chips = msm_gpio_chips_qsd8x50; | 644 | msm_gpio_count = data->count; |
607 | msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_qsd8x50); | 645 | |
608 | } else { | 646 | irq1 = platform_get_irq(pdev, 0); |
609 | return 0; | 647 | if (irq1 < 0) |
610 | } | 648 | return irq1; |
649 | |||
650 | irq2 = platform_get_irq(pdev, 1); | ||
651 | if (irq2 < 0) | ||
652 | return irq2; | ||
653 | |||
654 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
655 | base1 = devm_request_and_ioremap(&pdev->dev, res); | ||
656 | if (!base1) | ||
657 | return -EADDRNOTAVAIL; | ||
658 | |||
659 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | ||
660 | base2 = devm_request_and_ioremap(&pdev->dev, res); | ||
661 | if (!base2) | ||
662 | return -EADDRNOTAVAIL; | ||
611 | 663 | ||
612 | for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) { | 664 | for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) { |
613 | if (i - FIRST_GPIO_IRQ >= | 665 | if (i - FIRST_GPIO_IRQ >= |
@@ -621,16 +673,42 @@ static int __init msm_init_gpio(void) | |||
621 | } | 673 | } |
622 | 674 | ||
623 | for (i = 0; i < msm_gpio_count; i++) { | 675 | for (i = 0; i < msm_gpio_count; i++) { |
676 | if (i == 1) | ||
677 | msm_gpio_chips[i].base = base2; | ||
678 | else | ||
679 | msm_gpio_chips[i].base = base1; | ||
624 | spin_lock_init(&msm_gpio_chips[i].lock); | 680 | spin_lock_init(&msm_gpio_chips[i].lock); |
625 | writel(0, msm_gpio_chips[i].regs.int_en); | 681 | msm_gpio_writel(&msm_gpio_chips[i], 0, MSM_GPIO_INT_EN); |
626 | gpiochip_add(&msm_gpio_chips[i].chip); | 682 | gpiochip_add(&msm_gpio_chips[i].chip); |
627 | } | 683 | } |
628 | 684 | ||
629 | irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); | 685 | irq_set_chained_handler(irq1, msm_gpio_irq_handler); |
630 | irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); | 686 | irq_set_chained_handler(irq2, msm_gpio_irq_handler); |
631 | irq_set_irq_wake(INT_GPIO_GROUP1, 1); | 687 | irq_set_irq_wake(irq1, 1); |
632 | irq_set_irq_wake(INT_GPIO_GROUP2, 2); | 688 | irq_set_irq_wake(irq2, 2); |
633 | return 0; | 689 | return 0; |
634 | } | 690 | } |
635 | 691 | ||
636 | postcore_initcall(msm_init_gpio); | 692 | static struct platform_device_id gpio_msm_v1_device_ids[] = { |
693 | { "gpio-msm-7201", (unsigned long)&msm_gpio_7x01_init }, | ||
694 | { "gpio-msm-7x30", (unsigned long)&msm_gpio_7x30_init }, | ||
695 | { "gpio-msm-8x50", (unsigned long)&msm_gpio_8x50_init }, | ||
696 | { } | ||
697 | }; | ||
698 | MODULE_DEVICE_TABLE(platform, gpio_msm_v1_device_ids); | ||
699 | |||
700 | static struct platform_driver gpio_msm_v1_driver = { | ||
701 | .driver = { | ||
702 | .name = "gpio-msm-v1", | ||
703 | .owner = THIS_MODULE, | ||
704 | }, | ||
705 | .probe = gpio_msm_v1_probe, | ||
706 | .id_table = gpio_msm_v1_device_ids, | ||
707 | }; | ||
708 | |||
709 | static int __init gpio_msm_v1_init(void) | ||
710 | { | ||
711 | return platform_driver_register(&gpio_msm_v1_driver); | ||
712 | } | ||
713 | postcore_initcall(gpio_msm_v1_init); | ||
714 | MODULE_LICENSE("GPL v2"); | ||
diff --git a/drivers/gpio/gpio-msm-v2.c b/drivers/gpio/gpio-msm-v2.c index 55a7e7769af6..dd2eddeb1e0c 100644 --- a/drivers/gpio/gpio-msm-v2.c +++ b/drivers/gpio/gpio-msm-v2.c | |||
@@ -23,13 +23,12 @@ | |||
23 | #include <linux/init.h> | 23 | #include <linux/init.h> |
24 | #include <linux/interrupt.h> | 24 | #include <linux/interrupt.h> |
25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
26 | #include <linux/irqchip/chained_irq.h> | ||
26 | #include <linux/irq.h> | 27 | #include <linux/irq.h> |
27 | #include <linux/module.h> | 28 | #include <linux/module.h> |
28 | #include <linux/platform_device.h> | 29 | #include <linux/platform_device.h> |
29 | #include <linux/spinlock.h> | 30 | #include <linux/spinlock.h> |
30 | 31 | ||
31 | #include <asm/mach/irq.h> | ||
32 | |||
33 | #include <mach/msm_gpiomux.h> | 32 | #include <mach/msm_gpiomux.h> |
34 | #include <mach/msm_iomap.h> | 33 | #include <mach/msm_iomap.h> |
35 | 34 | ||
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 7877335c4cc8..7176743915d3 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
25 | #include <linux/irq.h> | 25 | #include <linux/irq.h> |
26 | #include <linux/irqdomain.h> | 26 | #include <linux/irqdomain.h> |
27 | #include <linux/irqchip/chained_irq.h> | ||
27 | #include <linux/gpio.h> | 28 | #include <linux/gpio.h> |
28 | #include <linux/platform_device.h> | 29 | #include <linux/platform_device.h> |
29 | #include <linux/slab.h> | 30 | #include <linux/slab.h> |
@@ -32,7 +33,6 @@ | |||
32 | #include <linux/of_device.h> | 33 | #include <linux/of_device.h> |
33 | #include <linux/module.h> | 34 | #include <linux/module.h> |
34 | #include <asm-generic/bug.h> | 35 | #include <asm-generic/bug.h> |
35 | #include <asm/mach/irq.h> | ||
36 | 36 | ||
37 | enum mxc_gpio_hwtype { | 37 | enum mxc_gpio_hwtype { |
38 | IMX1_GPIO, /* runs on i.mx1 */ | 38 | IMX1_GPIO, /* runs on i.mx1 */ |
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 159f5c57eb45..a612ea1c53cb 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c | |||
@@ -25,11 +25,10 @@ | |||
25 | #include <linux/of.h> | 25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | 26 | #include <linux/of_device.h> |
27 | #include <linux/irqdomain.h> | 27 | #include <linux/irqdomain.h> |
28 | #include <linux/irqchip/chained_irq.h> | ||
28 | #include <linux/gpio.h> | 29 | #include <linux/gpio.h> |
29 | #include <linux/platform_data/gpio-omap.h> | 30 | #include <linux/platform_data/gpio-omap.h> |
30 | 31 | ||
31 | #include <asm/mach/irq.h> | ||
32 | |||
33 | #define OFF_MODE 1 | 32 | #define OFF_MODE 1 |
34 | 33 | ||
35 | static LIST_HEAD(omap_gpio_list); | 34 | static LIST_HEAD(omap_gpio_list); |
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index d7008dfdd6f0..6a4bd0dae0ce 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/ioport.h> | 16 | #include <linux/ioport.h> |
17 | #include <linux/irq.h> | 17 | #include <linux/irq.h> |
18 | #include <linux/irqdomain.h> | 18 | #include <linux/irqdomain.h> |
19 | #include <linux/irqchip/chained_irq.h> | ||
19 | #include <linux/bitops.h> | 20 | #include <linux/bitops.h> |
20 | #include <linux/workqueue.h> | 21 | #include <linux/workqueue.h> |
21 | #include <linux/gpio.h> | 22 | #include <linux/gpio.h> |
@@ -25,7 +26,6 @@ | |||
25 | #include <linux/slab.h> | 26 | #include <linux/slab.h> |
26 | #include <linux/pinctrl/consumer.h> | 27 | #include <linux/pinctrl/consumer.h> |
27 | #include <linux/pm.h> | 28 | #include <linux/pm.h> |
28 | #include <asm/mach/irq.h> | ||
29 | 29 | ||
30 | #define GPIODIR 0x400 | 30 | #define GPIODIR 0x400 |
31 | #define GPIOIS 0x404 | 31 | #define GPIOIS 0x404 |
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c index 8325f580c0f1..2d3af981641e 100644 --- a/drivers/gpio/gpio-pxa.c +++ b/drivers/gpio/gpio-pxa.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <linux/init.h> | 19 | #include <linux/init.h> |
20 | #include <linux/irq.h> | 20 | #include <linux/irq.h> |
21 | #include <linux/irqdomain.h> | 21 | #include <linux/irqdomain.h> |
22 | #include <linux/irqchip/chained_irq.h> | ||
22 | #include <linux/io.h> | 23 | #include <linux/io.h> |
23 | #include <linux/of.h> | 24 | #include <linux/of.h> |
24 | #include <linux/of_device.h> | 25 | #include <linux/of_device.h> |
@@ -26,8 +27,6 @@ | |||
26 | #include <linux/syscore_ops.h> | 27 | #include <linux/syscore_ops.h> |
27 | #include <linux/slab.h> | 28 | #include <linux/slab.h> |
28 | 29 | ||
29 | #include <asm/mach/irq.h> | ||
30 | |||
31 | #include <mach/irqs.h> | 30 | #include <mach/irqs.h> |
32 | 31 | ||
33 | /* | 32 | /* |
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c index 414ad912232f..8e2155548888 100644 --- a/drivers/gpio/gpio-tegra.c +++ b/drivers/gpio/gpio-tegra.c | |||
@@ -27,11 +27,10 @@ | |||
27 | #include <linux/platform_device.h> | 27 | #include <linux/platform_device.h> |
28 | #include <linux/module.h> | 28 | #include <linux/module.h> |
29 | #include <linux/irqdomain.h> | 29 | #include <linux/irqdomain.h> |
30 | #include <linux/irqchip/chained_irq.h> | ||
30 | #include <linux/pinctrl/consumer.h> | 31 | #include <linux/pinctrl/consumer.h> |
31 | #include <linux/pm.h> | 32 | #include <linux/pm.h> |
32 | 33 | ||
33 | #include <asm/mach/irq.h> | ||
34 | |||
35 | #define GPIO_BANK(x) ((x) >> 5) | 34 | #define GPIO_BANK(x) ((x) >> 5) |
36 | #define GPIO_PORT(x) (((x) >> 3) & 0x3) | 35 | #define GPIO_PORT(x) (((x) >> 3) & 0x3) |
37 | #define GPIO_BIT(x) ((x) & 0x7) | 36 | #define GPIO_BIT(x) ((x) & 0x7) |
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 98e3b87bdf1b..d5e119ca9425 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile | |||
@@ -2,9 +2,10 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o | |||
2 | 2 | ||
3 | obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o | 3 | obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o |
4 | obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o | 4 | obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o |
5 | obj-$(CONFIG_ARCH_MXS) += irq-mxs.o | ||
5 | obj-$(CONFIG_METAG) += irq-metag-ext.o | 6 | obj-$(CONFIG_METAG) += irq-metag-ext.o |
6 | obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o | 7 | obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o |
7 | obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o | 8 | obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o |
8 | obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o | 9 | obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o |
9 | obj-$(CONFIG_ARM_GIC) += irq-gic.o | 10 | obj-$(CONFIG_ARM_GIC) += irq-gic.o |
10 | obj-$(CONFIG_ARM_VIC) += irq-vic.o | 11 | obj-$(CONFIG_ARM_VIC) += irq-vic.o |
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c index 04d86a9803f4..6a5201351507 100644 --- a/drivers/irqchip/exynos-combiner.c +++ b/drivers/irqchip/exynos-combiner.c | |||
@@ -13,6 +13,7 @@ | |||
13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
14 | #include <linux/io.h> | 14 | #include <linux/io.h> |
15 | #include <linux/irqdomain.h> | 15 | #include <linux/irqdomain.h> |
16 | #include <linux/irqchip/chained_irq.h> | ||
16 | #include <linux/of_address.h> | 17 | #include <linux/of_address.h> |
17 | #include <linux/of_irq.h> | 18 | #include <linux/of_irq.h> |
18 | #include <asm/mach/irq.h> | 19 | #include <asm/mach/irq.h> |
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index fc6aebf1e4b2..1760ceb68b7b 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <linux/module.h> | 28 | #include <linux/module.h> |
29 | #include <linux/list.h> | 29 | #include <linux/list.h> |
30 | #include <linux/smp.h> | 30 | #include <linux/smp.h> |
31 | #include <linux/cpu.h> | ||
31 | #include <linux/cpu_pm.h> | 32 | #include <linux/cpu_pm.h> |
32 | #include <linux/cpumask.h> | 33 | #include <linux/cpumask.h> |
33 | #include <linux/io.h> | 34 | #include <linux/io.h> |
@@ -38,12 +39,12 @@ | |||
38 | #include <linux/interrupt.h> | 39 | #include <linux/interrupt.h> |
39 | #include <linux/percpu.h> | 40 | #include <linux/percpu.h> |
40 | #include <linux/slab.h> | 41 | #include <linux/slab.h> |
42 | #include <linux/irqchip/chained_irq.h> | ||
41 | #include <linux/irqchip/arm-gic.h> | 43 | #include <linux/irqchip/arm-gic.h> |
42 | 44 | ||
43 | #include <asm/irq.h> | 45 | #include <asm/irq.h> |
44 | #include <asm/exception.h> | 46 | #include <asm/exception.h> |
45 | #include <asm/smp_plat.h> | 47 | #include <asm/smp_plat.h> |
46 | #include <asm/mach/irq.h> | ||
47 | 48 | ||
48 | #include "irqchip.h" | 49 | #include "irqchip.h" |
49 | 50 | ||
@@ -127,7 +128,7 @@ static inline void gic_set_base_accessor(struct gic_chip_data *data, | |||
127 | #else | 128 | #else |
128 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) | 129 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) |
129 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) | 130 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) |
130 | #define gic_set_base_accessor(d,f) | 131 | #define gic_set_base_accessor(d, f) |
131 | #endif | 132 | #endif |
132 | 133 | ||
133 | static inline void __iomem *gic_dist_base(struct irq_data *d) | 134 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
@@ -324,7 +325,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) | |||
324 | 325 | ||
325 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); | 326 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); |
326 | if (unlikely(gic_irq < 32 || gic_irq > 1020)) | 327 | if (unlikely(gic_irq < 32 || gic_irq > 1020)) |
327 | do_bad_IRQ(cascade_irq, desc); | 328 | handle_bad_irq(cascade_irq, desc); |
328 | else | 329 | else |
329 | generic_handle_irq(cascade_irq); | 330 | generic_handle_irq(cascade_irq); |
330 | 331 | ||
@@ -700,6 +701,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d, | |||
700 | return 0; | 701 | return 0; |
701 | } | 702 | } |
702 | 703 | ||
704 | #ifdef CONFIG_SMP | ||
705 | static int __cpuinit gic_secondary_init(struct notifier_block *nfb, | ||
706 | unsigned long action, void *hcpu) | ||
707 | { | ||
708 | if (action == CPU_STARTING) | ||
709 | gic_cpu_init(&gic_data[0]); | ||
710 | return NOTIFY_OK; | ||
711 | } | ||
712 | |||
713 | /* | ||
714 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | ||
715 | * priority because the GIC needs to be up before the ARM generic timers. | ||
716 | */ | ||
717 | static struct notifier_block __cpuinitdata gic_cpu_notifier = { | ||
718 | .notifier_call = gic_secondary_init, | ||
719 | .priority = 100, | ||
720 | }; | ||
721 | #endif | ||
722 | |||
703 | const struct irq_domain_ops gic_irq_domain_ops = { | 723 | const struct irq_domain_ops gic_irq_domain_ops = { |
704 | .map = gic_irq_domain_map, | 724 | .map = gic_irq_domain_map, |
705 | .xlate = gic_irq_domain_xlate, | 725 | .xlate = gic_irq_domain_xlate, |
@@ -790,6 +810,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, | |||
790 | 810 | ||
791 | #ifdef CONFIG_SMP | 811 | #ifdef CONFIG_SMP |
792 | set_smp_cross_call(gic_raise_softirq); | 812 | set_smp_cross_call(gic_raise_softirq); |
813 | register_cpu_notifier(&gic_cpu_notifier); | ||
793 | #endif | 814 | #endif |
794 | 815 | ||
795 | set_handle_irq(gic_handle_irq); | 816 | set_handle_irq(gic_handle_irq); |
@@ -800,15 +821,8 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, | |||
800 | gic_pm_init(gic); | 821 | gic_pm_init(gic); |
801 | } | 822 | } |
802 | 823 | ||
803 | void __cpuinit gic_secondary_init(unsigned int gic_nr) | ||
804 | { | ||
805 | BUG_ON(gic_nr >= MAX_GIC_NR); | ||
806 | |||
807 | gic_cpu_init(&gic_data[gic_nr]); | ||
808 | } | ||
809 | |||
810 | #ifdef CONFIG_OF | 824 | #ifdef CONFIG_OF |
811 | static int gic_cnt __initdata = 0; | 825 | static int gic_cnt __initdata; |
812 | 826 | ||
813 | int __init gic_of_init(struct device_node *node, struct device_node *parent) | 827 | int __init gic_of_init(struct device_node *node, struct device_node *parent) |
814 | { | 828 | { |
diff --git a/arch/arm/mach-mxs/icoll.c b/drivers/irqchip/irq-mxs.c index e26eeba46598..29889bbdcc6d 100644 --- a/arch/arm/mach-mxs/icoll.c +++ b/drivers/irqchip/irq-mxs.c | |||
@@ -22,10 +22,12 @@ | |||
22 | #include <linux/irqdomain.h> | 22 | #include <linux/irqdomain.h> |
23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | #include <linux/of.h> | 24 | #include <linux/of.h> |
25 | #include <linux/of_address.h> | ||
25 | #include <linux/of_irq.h> | 26 | #include <linux/of_irq.h> |
27 | #include <linux/stmp_device.h> | ||
26 | #include <asm/exception.h> | 28 | #include <asm/exception.h> |
27 | #include <mach/mxs.h> | 29 | |
28 | #include <mach/common.h> | 30 | #include "irqchip.h" |
29 | 31 | ||
30 | #define HW_ICOLL_VECTOR 0x0000 | 32 | #define HW_ICOLL_VECTOR 0x0000 |
31 | #define HW_ICOLL_LEVELACK 0x0010 | 33 | #define HW_ICOLL_LEVELACK 0x0010 |
@@ -38,7 +40,7 @@ | |||
38 | 40 | ||
39 | #define ICOLL_NUM_IRQS 128 | 41 | #define ICOLL_NUM_IRQS 128 |
40 | 42 | ||
41 | static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR); | 43 | static void __iomem *icoll_base; |
42 | static struct irq_domain *icoll_domain; | 44 | static struct irq_domain *icoll_domain; |
43 | 45 | ||
44 | static void icoll_ack_irq(struct irq_data *d) | 46 | static void icoll_ack_irq(struct irq_data *d) |
@@ -103,23 +105,17 @@ static struct irq_domain_ops icoll_irq_domain_ops = { | |||
103 | static void __init icoll_of_init(struct device_node *np, | 105 | static void __init icoll_of_init(struct device_node *np, |
104 | struct device_node *interrupt_parent) | 106 | struct device_node *interrupt_parent) |
105 | { | 107 | { |
108 | icoll_base = of_iomap(np, 0); | ||
109 | WARN_ON(!icoll_base); | ||
110 | |||
106 | /* | 111 | /* |
107 | * Interrupt Collector reset, which initializes the priority | 112 | * Interrupt Collector reset, which initializes the priority |
108 | * for each irq to level 0. | 113 | * for each irq to level 0. |
109 | */ | 114 | */ |
110 | mxs_reset_block(icoll_base + HW_ICOLL_CTRL); | 115 | stmp_reset_block(icoll_base + HW_ICOLL_CTRL); |
111 | 116 | ||
112 | icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS, | 117 | icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS, |
113 | &icoll_irq_domain_ops, NULL); | 118 | &icoll_irq_domain_ops, NULL); |
114 | WARN_ON(!icoll_domain); | 119 | WARN_ON(!icoll_domain); |
115 | } | 120 | } |
116 | 121 | IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init); | |
117 | static const struct of_device_id icoll_of_match[] __initconst = { | ||
118 | {.compatible = "fsl,icoll", .data = icoll_of_init}, | ||
119 | { /* sentinel */ } | ||
120 | }; | ||
121 | |||
122 | void __init icoll_init_irq(void) | ||
123 | { | ||
124 | of_irq_init(icoll_of_match); | ||
125 | } | ||
diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c new file mode 100644 index 000000000000..b66d4ae06898 --- /dev/null +++ b/drivers/irqchip/irq-sun4i.c | |||
@@ -0,0 +1,149 @@ | |||
1 | /* | ||
2 | * Allwinner A1X SoCs IRQ chip driver. | ||
3 | * | ||
4 | * Copyright (C) 2012 Maxime Ripard | ||
5 | * | ||
6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | ||
7 | * | ||
8 | * Based on code from | ||
9 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> | ||
10 | * Benn Huang <benn@allwinnertech.com> | ||
11 | * | ||
12 | * This file is licensed under the terms of the GNU General Public | ||
13 | * License version 2. This program is licensed "as is" without any | ||
14 | * warranty of any kind, whether express or implied. | ||
15 | */ | ||
16 | |||
17 | #include <linux/io.h> | ||
18 | #include <linux/irq.h> | ||
19 | #include <linux/of.h> | ||
20 | #include <linux/of_address.h> | ||
21 | #include <linux/of_irq.h> | ||
22 | |||
23 | #include <asm/exception.h> | ||
24 | #include <asm/mach/irq.h> | ||
25 | |||
26 | #include "irqchip.h" | ||
27 | |||
28 | #define SUN4I_IRQ_VECTOR_REG 0x00 | ||
29 | #define SUN4I_IRQ_PROTECTION_REG 0x08 | ||
30 | #define SUN4I_IRQ_NMI_CTRL_REG 0x0c | ||
31 | #define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x) | ||
32 | #define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x) | ||
33 | #define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x) | ||
34 | #define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x) | ||
35 | |||
36 | static void __iomem *sun4i_irq_base; | ||
37 | static struct irq_domain *sun4i_irq_domain; | ||
38 | |||
39 | static asmlinkage void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs); | ||
40 | |||
41 | void sun4i_irq_ack(struct irq_data *irqd) | ||
42 | { | ||
43 | unsigned int irq = irqd_to_hwirq(irqd); | ||
44 | unsigned int irq_off = irq % 32; | ||
45 | int reg = irq / 32; | ||
46 | u32 val; | ||
47 | |||
48 | val = readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg)); | ||
49 | writel(val | (1 << irq_off), | ||
50 | sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg)); | ||
51 | } | ||
52 | |||
53 | static void sun4i_irq_mask(struct irq_data *irqd) | ||
54 | { | ||
55 | unsigned int irq = irqd_to_hwirq(irqd); | ||
56 | unsigned int irq_off = irq % 32; | ||
57 | int reg = irq / 32; | ||
58 | u32 val; | ||
59 | |||
60 | val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg)); | ||
61 | writel(val & ~(1 << irq_off), | ||
62 | sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg)); | ||
63 | } | ||
64 | |||
65 | static void sun4i_irq_unmask(struct irq_data *irqd) | ||
66 | { | ||
67 | unsigned int irq = irqd_to_hwirq(irqd); | ||
68 | unsigned int irq_off = irq % 32; | ||
69 | int reg = irq / 32; | ||
70 | u32 val; | ||
71 | |||
72 | val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg)); | ||
73 | writel(val | (1 << irq_off), | ||
74 | sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg)); | ||
75 | } | ||
76 | |||
77 | static struct irq_chip sun4i_irq_chip = { | ||
78 | .name = "sun4i_irq", | ||
79 | .irq_ack = sun4i_irq_ack, | ||
80 | .irq_mask = sun4i_irq_mask, | ||
81 | .irq_unmask = sun4i_irq_unmask, | ||
82 | }; | ||
83 | |||
84 | static int sun4i_irq_map(struct irq_domain *d, unsigned int virq, | ||
85 | irq_hw_number_t hw) | ||
86 | { | ||
87 | irq_set_chip_and_handler(virq, &sun4i_irq_chip, | ||
88 | handle_level_irq); | ||
89 | set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); | ||
90 | |||
91 | return 0; | ||
92 | } | ||
93 | |||
94 | static struct irq_domain_ops sun4i_irq_ops = { | ||
95 | .map = sun4i_irq_map, | ||
96 | .xlate = irq_domain_xlate_onecell, | ||
97 | }; | ||
98 | |||
99 | static int __init sun4i_of_init(struct device_node *node, | ||
100 | struct device_node *parent) | ||
101 | { | ||
102 | sun4i_irq_base = of_iomap(node, 0); | ||
103 | if (!sun4i_irq_base) | ||
104 | panic("%s: unable to map IC registers\n", | ||
105 | node->full_name); | ||
106 | |||
107 | /* Disable all interrupts */ | ||
108 | writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0)); | ||
109 | writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1)); | ||
110 | writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2)); | ||
111 | |||
112 | /* Mask all the interrupts */ | ||
113 | writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0)); | ||
114 | writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1)); | ||
115 | writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2)); | ||
116 | |||
117 | /* Clear all the pending interrupts */ | ||
118 | writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)); | ||
119 | writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1)); | ||
120 | writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2)); | ||
121 | |||
122 | /* Enable protection mode */ | ||
123 | writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG); | ||
124 | |||
125 | /* Configure the external interrupt source type */ | ||
126 | writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG); | ||
127 | |||
128 | sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32, | ||
129 | &sun4i_irq_ops, NULL); | ||
130 | if (!sun4i_irq_domain) | ||
131 | panic("%s: unable to create IRQ domain\n", node->full_name); | ||
132 | |||
133 | set_handle_irq(sun4i_handle_irq); | ||
134 | |||
135 | return 0; | ||
136 | } | ||
137 | IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-ic", sun4i_of_init); | ||
138 | |||
139 | static asmlinkage void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs) | ||
140 | { | ||
141 | u32 irq, hwirq; | ||
142 | |||
143 | hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2; | ||
144 | while (hwirq != 0) { | ||
145 | irq = irq_find_mapping(sun4i_irq_domain, hwirq); | ||
146 | handle_IRQ(irq, regs); | ||
147 | hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2; | ||
148 | } | ||
149 | } | ||
diff --git a/drivers/irqchip/irq-sunxi.c b/drivers/irqchip/irq-sunxi.c deleted file mode 100644 index 10974fa42653..000000000000 --- a/drivers/irqchip/irq-sunxi.c +++ /dev/null | |||
@@ -1,151 +0,0 @@ | |||
1 | /* | ||
2 | * Allwinner A1X SoCs IRQ chip driver. | ||
3 | * | ||
4 | * Copyright (C) 2012 Maxime Ripard | ||
5 | * | ||
6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | ||
7 | * | ||
8 | * Based on code from | ||
9 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> | ||
10 | * Benn Huang <benn@allwinnertech.com> | ||
11 | * | ||
12 | * This file is licensed under the terms of the GNU General Public | ||
13 | * License version 2. This program is licensed "as is" without any | ||
14 | * warranty of any kind, whether express or implied. | ||
15 | */ | ||
16 | |||
17 | #include <linux/io.h> | ||
18 | #include <linux/irq.h> | ||
19 | #include <linux/of.h> | ||
20 | #include <linux/of_address.h> | ||
21 | #include <linux/of_irq.h> | ||
22 | |||
23 | #include <linux/irqchip/sunxi.h> | ||
24 | |||
25 | #define SUNXI_IRQ_VECTOR_REG 0x00 | ||
26 | #define SUNXI_IRQ_PROTECTION_REG 0x08 | ||
27 | #define SUNXI_IRQ_NMI_CTRL_REG 0x0c | ||
28 | #define SUNXI_IRQ_PENDING_REG(x) (0x10 + 0x4 * x) | ||
29 | #define SUNXI_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x) | ||
30 | #define SUNXI_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x) | ||
31 | #define SUNXI_IRQ_MASK_REG(x) (0x50 + 0x4 * x) | ||
32 | |||
33 | static void __iomem *sunxi_irq_base; | ||
34 | static struct irq_domain *sunxi_irq_domain; | ||
35 | |||
36 | void sunxi_irq_ack(struct irq_data *irqd) | ||
37 | { | ||
38 | unsigned int irq = irqd_to_hwirq(irqd); | ||
39 | unsigned int irq_off = irq % 32; | ||
40 | int reg = irq / 32; | ||
41 | u32 val; | ||
42 | |||
43 | val = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg)); | ||
44 | writel(val | (1 << irq_off), | ||
45 | sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg)); | ||
46 | } | ||
47 | |||
48 | static void sunxi_irq_mask(struct irq_data *irqd) | ||
49 | { | ||
50 | unsigned int irq = irqd_to_hwirq(irqd); | ||
51 | unsigned int irq_off = irq % 32; | ||
52 | int reg = irq / 32; | ||
53 | u32 val; | ||
54 | |||
55 | val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg)); | ||
56 | writel(val & ~(1 << irq_off), | ||
57 | sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg)); | ||
58 | } | ||
59 | |||
60 | static void sunxi_irq_unmask(struct irq_data *irqd) | ||
61 | { | ||
62 | unsigned int irq = irqd_to_hwirq(irqd); | ||
63 | unsigned int irq_off = irq % 32; | ||
64 | int reg = irq / 32; | ||
65 | u32 val; | ||
66 | |||
67 | val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg)); | ||
68 | writel(val | (1 << irq_off), | ||
69 | sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg)); | ||
70 | } | ||
71 | |||
72 | static struct irq_chip sunxi_irq_chip = { | ||
73 | .name = "sunxi_irq", | ||
74 | .irq_ack = sunxi_irq_ack, | ||
75 | .irq_mask = sunxi_irq_mask, | ||
76 | .irq_unmask = sunxi_irq_unmask, | ||
77 | }; | ||
78 | |||
79 | static int sunxi_irq_map(struct irq_domain *d, unsigned int virq, | ||
80 | irq_hw_number_t hw) | ||
81 | { | ||
82 | irq_set_chip_and_handler(virq, &sunxi_irq_chip, | ||
83 | handle_level_irq); | ||
84 | set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); | ||
85 | |||
86 | return 0; | ||
87 | } | ||
88 | |||
89 | static struct irq_domain_ops sunxi_irq_ops = { | ||
90 | .map = sunxi_irq_map, | ||
91 | .xlate = irq_domain_xlate_onecell, | ||
92 | }; | ||
93 | |||
94 | static int __init sunxi_of_init(struct device_node *node, | ||
95 | struct device_node *parent) | ||
96 | { | ||
97 | sunxi_irq_base = of_iomap(node, 0); | ||
98 | if (!sunxi_irq_base) | ||
99 | panic("%s: unable to map IC registers\n", | ||
100 | node->full_name); | ||
101 | |||
102 | /* Disable all interrupts */ | ||
103 | writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(0)); | ||
104 | writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(1)); | ||
105 | writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(2)); | ||
106 | |||
107 | /* Mask all the interrupts */ | ||
108 | writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(0)); | ||
109 | writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(1)); | ||
110 | writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(2)); | ||
111 | |||
112 | /* Clear all the pending interrupts */ | ||
113 | writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0)); | ||
114 | writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(1)); | ||
115 | writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(2)); | ||
116 | |||
117 | /* Enable protection mode */ | ||
118 | writel(0x01, sunxi_irq_base + SUNXI_IRQ_PROTECTION_REG); | ||
119 | |||
120 | /* Configure the external interrupt source type */ | ||
121 | writel(0x00, sunxi_irq_base + SUNXI_IRQ_NMI_CTRL_REG); | ||
122 | |||
123 | sunxi_irq_domain = irq_domain_add_linear(node, 3 * 32, | ||
124 | &sunxi_irq_ops, NULL); | ||
125 | if (!sunxi_irq_domain) | ||
126 | panic("%s: unable to create IRQ domain\n", node->full_name); | ||
127 | |||
128 | return 0; | ||
129 | } | ||
130 | |||
131 | static struct of_device_id sunxi_irq_dt_ids[] __initconst = { | ||
132 | { .compatible = "allwinner,sunxi-ic", .data = sunxi_of_init }, | ||
133 | { } | ||
134 | }; | ||
135 | |||
136 | void __init sunxi_init_irq(void) | ||
137 | { | ||
138 | of_irq_init(sunxi_irq_dt_ids); | ||
139 | } | ||
140 | |||
141 | asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs) | ||
142 | { | ||
143 | u32 irq, hwirq; | ||
144 | |||
145 | hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2; | ||
146 | while (hwirq != 0) { | ||
147 | irq = irq_find_mapping(sunxi_irq_domain, hwirq); | ||
148 | handle_IRQ(irq, regs); | ||
149 | hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2; | ||
150 | } | ||
151 | } | ||
diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c index 3cf97aaebe40..884d11c7355f 100644 --- a/drivers/irqchip/irq-vic.c +++ b/drivers/irqchip/irq-vic.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <linux/init.h> | 23 | #include <linux/init.h> |
24 | #include <linux/list.h> | 24 | #include <linux/list.h> |
25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
26 | #include <linux/irq.h> | ||
26 | #include <linux/irqdomain.h> | 27 | #include <linux/irqdomain.h> |
27 | #include <linux/of.h> | 28 | #include <linux/of.h> |
28 | #include <linux/of_address.h> | 29 | #include <linux/of_address.h> |
@@ -33,7 +34,7 @@ | |||
33 | #include <linux/irqchip/arm-vic.h> | 34 | #include <linux/irqchip/arm-vic.h> |
34 | 35 | ||
35 | #include <asm/exception.h> | 36 | #include <asm/exception.h> |
36 | #include <asm/mach/irq.h> | 37 | #include <asm/irq.h> |
37 | 38 | ||
38 | #include "irqchip.h" | 39 | #include "irqchip.h" |
39 | 40 | ||
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c index 7c0af0e80047..0ee4a57fe6b2 100644 --- a/drivers/mmc/host/msm_sdcc.c +++ b/drivers/mmc/host/msm_sdcc.c | |||
@@ -43,7 +43,6 @@ | |||
43 | #include <asm/sizes.h> | 43 | #include <asm/sizes.h> |
44 | 44 | ||
45 | #include <linux/platform_data/mmc-msm_sdcc.h> | 45 | #include <linux/platform_data/mmc-msm_sdcc.h> |
46 | #include <mach/msm_iomap.h> | ||
47 | #include <mach/dma.h> | 46 | #include <mach/dma.h> |
48 | #include <mach/clk.h> | 47 | #include <mach/clk.h> |
49 | 48 | ||
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c index 63fb265e0da6..8d6794cdf899 100644 --- a/drivers/mmc/host/s3cmci.c +++ b/drivers/mmc/host/s3cmci.c | |||
@@ -25,14 +25,93 @@ | |||
25 | 25 | ||
26 | #include <mach/dma.h> | 26 | #include <mach/dma.h> |
27 | 27 | ||
28 | #include <mach/regs-sdi.h> | ||
29 | |||
30 | #include <linux/platform_data/mmc-s3cmci.h> | 28 | #include <linux/platform_data/mmc-s3cmci.h> |
31 | 29 | ||
32 | #include "s3cmci.h" | 30 | #include "s3cmci.h" |
33 | 31 | ||
34 | #define DRIVER_NAME "s3c-mci" | 32 | #define DRIVER_NAME "s3c-mci" |
35 | 33 | ||
34 | #define S3C2410_SDICON (0x00) | ||
35 | #define S3C2410_SDIPRE (0x04) | ||
36 | #define S3C2410_SDICMDARG (0x08) | ||
37 | #define S3C2410_SDICMDCON (0x0C) | ||
38 | #define S3C2410_SDICMDSTAT (0x10) | ||
39 | #define S3C2410_SDIRSP0 (0x14) | ||
40 | #define S3C2410_SDIRSP1 (0x18) | ||
41 | #define S3C2410_SDIRSP2 (0x1C) | ||
42 | #define S3C2410_SDIRSP3 (0x20) | ||
43 | #define S3C2410_SDITIMER (0x24) | ||
44 | #define S3C2410_SDIBSIZE (0x28) | ||
45 | #define S3C2410_SDIDCON (0x2C) | ||
46 | #define S3C2410_SDIDCNT (0x30) | ||
47 | #define S3C2410_SDIDSTA (0x34) | ||
48 | #define S3C2410_SDIFSTA (0x38) | ||
49 | |||
50 | #define S3C2410_SDIDATA (0x3C) | ||
51 | #define S3C2410_SDIIMSK (0x40) | ||
52 | |||
53 | #define S3C2440_SDIDATA (0x40) | ||
54 | #define S3C2440_SDIIMSK (0x3C) | ||
55 | |||
56 | #define S3C2440_SDICON_SDRESET (1 << 8) | ||
57 | #define S3C2410_SDICON_SDIOIRQ (1 << 3) | ||
58 | #define S3C2410_SDICON_FIFORESET (1 << 1) | ||
59 | #define S3C2410_SDICON_CLOCKTYPE (1 << 0) | ||
60 | |||
61 | #define S3C2410_SDICMDCON_LONGRSP (1 << 10) | ||
62 | #define S3C2410_SDICMDCON_WAITRSP (1 << 9) | ||
63 | #define S3C2410_SDICMDCON_CMDSTART (1 << 8) | ||
64 | #define S3C2410_SDICMDCON_SENDERHOST (1 << 6) | ||
65 | #define S3C2410_SDICMDCON_INDEX (0x3f) | ||
66 | |||
67 | #define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12) | ||
68 | #define S3C2410_SDICMDSTAT_CMDSENT (1 << 11) | ||
69 | #define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10) | ||
70 | #define S3C2410_SDICMDSTAT_RSPFIN (1 << 9) | ||
71 | |||
72 | #define S3C2440_SDIDCON_DS_WORD (2 << 22) | ||
73 | #define S3C2410_SDIDCON_TXAFTERRESP (1 << 20) | ||
74 | #define S3C2410_SDIDCON_RXAFTERCMD (1 << 19) | ||
75 | #define S3C2410_SDIDCON_BLOCKMODE (1 << 17) | ||
76 | #define S3C2410_SDIDCON_WIDEBUS (1 << 16) | ||
77 | #define S3C2410_SDIDCON_DMAEN (1 << 15) | ||
78 | #define S3C2410_SDIDCON_STOP (1 << 14) | ||
79 | #define S3C2440_SDIDCON_DATSTART (1 << 14) | ||
80 | |||
81 | #define S3C2410_SDIDCON_XFER_RXSTART (2 << 12) | ||
82 | #define S3C2410_SDIDCON_XFER_TXSTART (3 << 12) | ||
83 | |||
84 | #define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF) | ||
85 | |||
86 | #define S3C2410_SDIDSTA_SDIOIRQDETECT (1 << 9) | ||
87 | #define S3C2410_SDIDSTA_FIFOFAIL (1 << 8) | ||
88 | #define S3C2410_SDIDSTA_CRCFAIL (1 << 7) | ||
89 | #define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6) | ||
90 | #define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5) | ||
91 | #define S3C2410_SDIDSTA_XFERFINISH (1 << 4) | ||
92 | #define S3C2410_SDIDSTA_TXDATAON (1 << 1) | ||
93 | #define S3C2410_SDIDSTA_RXDATAON (1 << 0) | ||
94 | |||
95 | #define S3C2440_SDIFSTA_FIFORESET (1 << 16) | ||
96 | #define S3C2440_SDIFSTA_FIFOFAIL (3 << 14) | ||
97 | #define S3C2410_SDIFSTA_TFDET (1 << 13) | ||
98 | #define S3C2410_SDIFSTA_RFDET (1 << 12) | ||
99 | #define S3C2410_SDIFSTA_COUNTMASK (0x7f) | ||
100 | |||
101 | #define S3C2410_SDIIMSK_RESPONSECRC (1 << 17) | ||
102 | #define S3C2410_SDIIMSK_CMDSENT (1 << 16) | ||
103 | #define S3C2410_SDIIMSK_CMDTIMEOUT (1 << 15) | ||
104 | #define S3C2410_SDIIMSK_RESPONSEND (1 << 14) | ||
105 | #define S3C2410_SDIIMSK_SDIOIRQ (1 << 12) | ||
106 | #define S3C2410_SDIIMSK_FIFOFAIL (1 << 11) | ||
107 | #define S3C2410_SDIIMSK_CRCSTATUS (1 << 10) | ||
108 | #define S3C2410_SDIIMSK_DATACRC (1 << 9) | ||
109 | #define S3C2410_SDIIMSK_DATATIMEOUT (1 << 8) | ||
110 | #define S3C2410_SDIIMSK_DATAFINISH (1 << 7) | ||
111 | #define S3C2410_SDIIMSK_TXFIFOHALF (1 << 4) | ||
112 | #define S3C2410_SDIIMSK_RXFIFOLAST (1 << 2) | ||
113 | #define S3C2410_SDIIMSK_RXFIFOHALF (1 << 0) | ||
114 | |||
36 | enum dbg_channels { | 115 | enum dbg_channels { |
37 | dbg_err = (1 << 0), | 116 | dbg_err = (1 << 0), |
38 | dbg_debug = (1 << 1), | 117 | dbg_debug = (1 << 1), |
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 4d7f531e945d..5d7529ed5392 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <linux/interrupt.h> | 18 | #include <linux/interrupt.h> |
19 | #include <linux/irq.h> | 19 | #include <linux/irq.h> |
20 | #include <linux/irqdomain.h> | 20 | #include <linux/irqdomain.h> |
21 | #include <linux/irqchip/chained_irq.h> | ||
21 | #include <linux/io.h> | 22 | #include <linux/io.h> |
22 | #include <linux/gpio.h> | 23 | #include <linux/gpio.h> |
23 | #include <linux/pinctrl/machine.h> | 24 | #include <linux/pinctrl/machine.h> |
@@ -27,8 +28,6 @@ | |||
27 | /* Since we request GPIOs from ourself */ | 28 | /* Since we request GPIOs from ourself */ |
28 | #include <linux/pinctrl/consumer.h> | 29 | #include <linux/pinctrl/consumer.h> |
29 | 30 | ||
30 | #include <asm/mach/irq.h> | ||
31 | |||
32 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
33 | #include <mach/at91_pio.h> | 32 | #include <mach/at91_pio.h> |
34 | 33 | ||
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c index 8b10b1ac9071..ec1567842a7e 100644 --- a/drivers/pinctrl/pinctrl-exynos.c +++ b/drivers/pinctrl/pinctrl-exynos.c | |||
@@ -23,14 +23,13 @@ | |||
23 | #include <linux/interrupt.h> | 23 | #include <linux/interrupt.h> |
24 | #include <linux/irqdomain.h> | 24 | #include <linux/irqdomain.h> |
25 | #include <linux/irq.h> | 25 | #include <linux/irq.h> |
26 | #include <linux/irqchip/chained_irq.h> | ||
26 | #include <linux/of_irq.h> | 27 | #include <linux/of_irq.h> |
27 | #include <linux/io.h> | 28 | #include <linux/io.h> |
28 | #include <linux/slab.h> | 29 | #include <linux/slab.h> |
29 | #include <linux/spinlock.h> | 30 | #include <linux/spinlock.h> |
30 | #include <linux/err.h> | 31 | #include <linux/err.h> |
31 | 32 | ||
32 | #include <asm/mach/irq.h> | ||
33 | |||
34 | #include "pinctrl-samsung.h" | 33 | #include "pinctrl-samsung.h" |
35 | #include "pinctrl-exynos.h" | 34 | #include "pinctrl-exynos.h" |
36 | 35 | ||
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c index 435bf3078d2c..34281754b629 100644 --- a/drivers/pinctrl/pinctrl-nomadik.c +++ b/drivers/pinctrl/pinctrl-nomadik.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <linux/interrupt.h> | 23 | #include <linux/interrupt.h> |
24 | #include <linux/irq.h> | 24 | #include <linux/irq.h> |
25 | #include <linux/irqdomain.h> | 25 | #include <linux/irqdomain.h> |
26 | #include <linux/irqchip/chained_irq.h> | ||
26 | #include <linux/slab.h> | 27 | #include <linux/slab.h> |
27 | #include <linux/of_device.h> | 28 | #include <linux/of_device.h> |
28 | #include <linux/of_address.h> | 29 | #include <linux/of_address.h> |
@@ -33,7 +34,6 @@ | |||
33 | /* Since we request GPIOs from ourself */ | 34 | /* Since we request GPIOs from ourself */ |
34 | #include <linux/pinctrl/consumer.h> | 35 | #include <linux/pinctrl/consumer.h> |
35 | #include <linux/platform_data/pinctrl-nomadik.h> | 36 | #include <linux/platform_data/pinctrl-nomadik.h> |
36 | #include <asm/mach/irq.h> | ||
37 | #include "pinctrl-nomadik.h" | 37 | #include "pinctrl-nomadik.h" |
38 | #include "core.h" | 38 | #include "core.h" |
39 | 39 | ||
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c index fb9062570745..1ed23d02011e 100644 --- a/drivers/pinctrl/pinctrl-sirf.c +++ b/drivers/pinctrl/pinctrl-sirf.c | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <linux/slab.h> | 14 | #include <linux/slab.h> |
15 | #include <linux/err.h> | 15 | #include <linux/err.h> |
16 | #include <linux/irqdomain.h> | 16 | #include <linux/irqdomain.h> |
17 | #include <linux/irqchip/chained_irq.h> | ||
17 | #include <linux/pinctrl/pinctrl.h> | 18 | #include <linux/pinctrl/pinctrl.h> |
18 | #include <linux/pinctrl/pinmux.h> | 19 | #include <linux/pinctrl/pinmux.h> |
19 | #include <linux/pinctrl/consumer.h> | 20 | #include <linux/pinctrl/consumer.h> |
@@ -25,7 +26,6 @@ | |||
25 | #include <linux/bitops.h> | 26 | #include <linux/bitops.h> |
26 | #include <linux/gpio.h> | 27 | #include <linux/gpio.h> |
27 | #include <linux/of_gpio.h> | 28 | #include <linux/of_gpio.h> |
28 | #include <asm/mach/irq.h> | ||
29 | 29 | ||
30 | #define DRIVER_NAME "pinmux-sirf" | 30 | #define DRIVER_NAME "pinmux-sirf" |
31 | 31 | ||
diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c index 295b349a05cf..a4908ecd74fb 100644 --- a/drivers/pinctrl/spear/pinctrl-plgpio.c +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c | |||
@@ -15,12 +15,12 @@ | |||
15 | #include <linux/io.h> | 15 | #include <linux/io.h> |
16 | #include <linux/irq.h> | 16 | #include <linux/irq.h> |
17 | #include <linux/irqdomain.h> | 17 | #include <linux/irqdomain.h> |
18 | #include <linux/irqchip/chained_irq.h> | ||
18 | #include <linux/module.h> | 19 | #include <linux/module.h> |
19 | #include <linux/pinctrl/consumer.h> | 20 | #include <linux/pinctrl/consumer.h> |
20 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
21 | #include <linux/pm.h> | 22 | #include <linux/pm.h> |
22 | #include <linux/spinlock.h> | 23 | #include <linux/spinlock.h> |
23 | #include <asm/mach/irq.h> | ||
24 | 24 | ||
25 | #define MAX_GPIO_PER_REG 32 | 25 | #define MAX_GPIO_PER_REG 32 |
26 | #define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG) | 26 | #define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG) |
diff --git a/drivers/rtc/rtc-stmp3xxx.c b/drivers/rtc/rtc-stmp3xxx.c index a9cd26a26dc0..483ce086990b 100644 --- a/drivers/rtc/rtc-stmp3xxx.c +++ b/drivers/rtc/rtc-stmp3xxx.c | |||
@@ -30,8 +30,6 @@ | |||
30 | #include <linux/stmp_device.h> | 30 | #include <linux/stmp_device.h> |
31 | #include <linux/stmp3xxx_rtc_wdt.h> | 31 | #include <linux/stmp3xxx_rtc_wdt.h> |
32 | 32 | ||
33 | #include <mach/common.h> | ||
34 | |||
35 | #define STMP3XXX_RTC_CTRL 0x0 | 33 | #define STMP3XXX_RTC_CTRL 0x0 |
36 | #define STMP3XXX_RTC_CTRL_SET 0x4 | 34 | #define STMP3XXX_RTC_CTRL_SET 0x4 |
37 | #define STMP3XXX_RTC_CTRL_CLR 0x8 | 35 | #define STMP3XXX_RTC_CTRL_CLR 0x8 |
@@ -264,7 +262,7 @@ static int stmp3xxx_rtc_probe(struct platform_device *pdev) | |||
264 | 262 | ||
265 | platform_set_drvdata(pdev, rtc_data); | 263 | platform_set_drvdata(pdev, rtc_data); |
266 | 264 | ||
267 | mxs_reset_block(rtc_data->io); | 265 | stmp_reset_block(rtc_data->io); |
268 | writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | | 266 | writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | |
269 | STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN | | 267 | STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN | |
270 | STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE, | 268 | STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE, |
@@ -307,7 +305,7 @@ static int stmp3xxx_rtc_resume(struct device *dev) | |||
307 | { | 305 | { |
308 | struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); | 306 | struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); |
309 | 307 | ||
310 | mxs_reset_block(rtc_data->io); | 308 | stmp_reset_block(rtc_data->io); |
311 | writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | | 309 | writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | |
312 | STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN | | 310 | STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN | |
313 | STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE, | 311 | STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE, |
diff --git a/drivers/staging/iio/adc/mxs-lradc.c b/drivers/staging/iio/adc/mxs-lradc.c index 6044e1717b20..2856b8fd44ad 100644 --- a/drivers/staging/iio/adc/mxs-lradc.c +++ b/drivers/staging/iio/adc/mxs-lradc.c | |||
@@ -36,9 +36,6 @@ | |||
36 | #include <linux/delay.h> | 36 | #include <linux/delay.h> |
37 | #include <linux/input.h> | 37 | #include <linux/input.h> |
38 | 38 | ||
39 | #include <mach/mxs.h> | ||
40 | #include <mach/common.h> | ||
41 | |||
42 | #include <linux/iio/iio.h> | 39 | #include <linux/iio/iio.h> |
43 | #include <linux/iio/buffer.h> | 40 | #include <linux/iio/buffer.h> |
44 | #include <linux/iio/trigger.h> | 41 | #include <linux/iio/trigger.h> |
diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-common.c b/drivers/staging/imx-drm/ipu-v3/ipu-common.c index 055b99db50ff..0880ef1a01ba 100644 --- a/drivers/staging/imx-drm/ipu-v3/ipu-common.c +++ b/drivers/staging/imx-drm/ipu-v3/ipu-common.c | |||
@@ -25,8 +25,8 @@ | |||
25 | #include <linux/clk.h> | 25 | #include <linux/clk.h> |
26 | #include <linux/list.h> | 26 | #include <linux/list.h> |
27 | #include <linux/irq.h> | 27 | #include <linux/irq.h> |
28 | #include <linux/irqchip/chained_irq.h> | ||
28 | #include <linux/of_device.h> | 29 | #include <linux/of_device.h> |
29 | #include <asm/mach/irq.h> | ||
30 | 30 | ||
31 | #include "imx-ipu-v3.h" | 31 | #include "imx-ipu-v3.h" |
32 | #include "ipu-prv.h" | 32 | #include "ipu-prv.h" |
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c index 114583a8e92b..07592c00af26 100644 --- a/drivers/usb/host/ohci-exynos.c +++ b/drivers/usb/host/ohci-exynos.c | |||
@@ -14,7 +14,7 @@ | |||
14 | #include <linux/clk.h> | 14 | #include <linux/clk.h> |
15 | #include <linux/of.h> | 15 | #include <linux/of.h> |
16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
17 | #include <linux/platform_data/usb-exynos.h> | 17 | #include <linux/platform_data/usb-ohci-exynos.h> |
18 | #include <linux/usb/phy.h> | 18 | #include <linux/usb/phy.h> |
19 | #include <linux/usb/samsung_usb_phy.h> | 19 | #include <linux/usb/samsung_usb_phy.h> |
20 | 20 | ||
diff --git a/include/linux/clk/mxs.h b/include/linux/clk/mxs.h new file mode 100644 index 000000000000..90c30dc3efc7 --- /dev/null +++ b/include/linux/clk/mxs.h | |||
@@ -0,0 +1,16 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2013 Freescale Semiconductor, Inc. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | |||
9 | #ifndef __LINUX_CLK_MXS_H | ||
10 | #define __LINUX_CLK_MXS_H | ||
11 | |||
12 | int mx23_clocks_init(void); | ||
13 | int mx28_clocks_init(void); | ||
14 | int mxs_saif_clkmux_select(unsigned int clkmux); | ||
15 | |||
16 | #endif | ||
diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h index aa7032c7238f..7279b94c01da 100644 --- a/include/linux/clocksource.h +++ b/include/linux/clocksource.h | |||
@@ -333,15 +333,23 @@ extern int clocksource_mmio_init(void __iomem *, const char *, | |||
333 | 333 | ||
334 | extern int clocksource_i8253_init(void); | 334 | extern int clocksource_i8253_init(void); |
335 | 335 | ||
336 | struct device_node; | ||
337 | typedef void(*clocksource_of_init_fn)(struct device_node *); | ||
336 | #ifdef CONFIG_CLKSRC_OF | 338 | #ifdef CONFIG_CLKSRC_OF |
337 | extern void clocksource_of_init(void); | 339 | extern void clocksource_of_init(void); |
338 | 340 | ||
339 | #define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \ | 341 | #define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \ |
340 | static const struct of_device_id __clksrc_of_table_##name \ | 342 | static const struct of_device_id __clksrc_of_table_##name \ |
341 | __used __section(__clksrc_of_table) \ | 343 | __used __section(__clksrc_of_table) \ |
342 | = { .compatible = compat, .data = fn }; | 344 | = { .compatible = compat, \ |
345 | .data = (fn == (clocksource_of_init_fn)NULL) ? fn : fn } | ||
343 | #else | 346 | #else |
344 | #define CLOCKSOURCE_OF_DECLARE(name, compat, fn) | 347 | static inline void clocksource_of_init(void) {} |
348 | #define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \ | ||
349 | static const struct of_device_id __clksrc_of_table_##name \ | ||
350 | __attribute__((unused)) \ | ||
351 | = { .compatible = compat, \ | ||
352 | .data = (fn == (clocksource_of_init_fn)NULL) ? fn : fn } | ||
345 | #endif | 353 | #endif |
346 | 354 | ||
347 | #endif /* _LINUX_CLOCKSOURCE_H */ | 355 | #endif /* _LINUX_CLOCKSOURCE_H */ |
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h index 3fd8e4290a1c..3e203eb23cc7 100644 --- a/include/linux/irqchip/arm-gic.h +++ b/include/linux/irqchip/arm-gic.h | |||
@@ -65,7 +65,6 @@ extern struct irq_chip gic_arch_extn; | |||
65 | 65 | ||
66 | void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, | 66 | void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, |
67 | u32 offset, struct device_node *); | 67 | u32 offset, struct device_node *); |
68 | void gic_secondary_init(unsigned int); | ||
69 | void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); | 68 | void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); |
70 | 69 | ||
71 | static inline void gic_init(unsigned int nr, int start, | 70 | static inline void gic_init(unsigned int nr, int start, |
diff --git a/include/linux/irqchip/chained_irq.h b/include/linux/irqchip/chained_irq.h new file mode 100644 index 000000000000..adf4c30f3af6 --- /dev/null +++ b/include/linux/irqchip/chained_irq.h | |||
@@ -0,0 +1,52 @@ | |||
1 | /* | ||
2 | * Chained IRQ handlers support. | ||
3 | * | ||
4 | * Copyright (C) 2011 ARM Ltd. | ||
5 | * | ||
6 | * This program is free software: you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | #ifndef __IRQCHIP_CHAINED_IRQ_H | ||
19 | #define __IRQCHIP_CHAINED_IRQ_H | ||
20 | |||
21 | #include <linux/irq.h> | ||
22 | |||
23 | /* | ||
24 | * Entry/exit functions for chained handlers where the primary IRQ chip | ||
25 | * may implement either fasteoi or level-trigger flow control. | ||
26 | */ | ||
27 | static inline void chained_irq_enter(struct irq_chip *chip, | ||
28 | struct irq_desc *desc) | ||
29 | { | ||
30 | /* FastEOI controllers require no action on entry. */ | ||
31 | if (chip->irq_eoi) | ||
32 | return; | ||
33 | |||
34 | if (chip->irq_mask_ack) { | ||
35 | chip->irq_mask_ack(&desc->irq_data); | ||
36 | } else { | ||
37 | chip->irq_mask(&desc->irq_data); | ||
38 | if (chip->irq_ack) | ||
39 | chip->irq_ack(&desc->irq_data); | ||
40 | } | ||
41 | } | ||
42 | |||
43 | static inline void chained_irq_exit(struct irq_chip *chip, | ||
44 | struct irq_desc *desc) | ||
45 | { | ||
46 | if (chip->irq_eoi) | ||
47 | chip->irq_eoi(&desc->irq_data); | ||
48 | else | ||
49 | chip->irq_unmask(&desc->irq_data); | ||
50 | } | ||
51 | |||
52 | #endif /* __IRQCHIP_CHAINED_IRQ_H */ | ||
diff --git a/arch/arm/mach-h720x/include/mach/timex.h b/include/linux/irqchip/mxs.h index 3f2f447ff36b..9039a538a919 100644 --- a/arch/arm/mach-h720x/include/mach/timex.h +++ b/include/linux/irqchip/mxs.h | |||
@@ -1,15 +1,14 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/mach-h720x/include/mach/timex.h | 2 | * Copyright (C) 2013 Freescale Semiconductor, Inc. |
3 | * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc. | ||
4 | * | 3 | * |
5 | * This program is free software; you can redistribute it and/or modify | 4 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License version 2 as | 5 | * it under the terms of the GNU General Public License version 2 as |
7 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
8 | */ | 7 | */ |
9 | 8 | ||
10 | #ifndef __ASM_ARCH_TIMEX | 9 | #ifndef __LINUX_IRQCHIP_MXS_H |
11 | #define __ASM_ARCH_TIMEX | 10 | #define __LINUX_IRQCHIP_MXS_H |
12 | 11 | ||
13 | #define CLOCK_TICK_RATE 3686400 | 12 | extern void icoll_handle_irq(struct pt_regs *); |
14 | 13 | ||
15 | #endif | 14 | #endif |
diff --git a/include/linux/irqchip/sunxi.h b/include/linux/irqchip/sunxi.h deleted file mode 100644 index 1fe2c2260e2b..000000000000 --- a/include/linux/irqchip/sunxi.h +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2012 Maxime Ripard | ||
3 | * | ||
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | */ | ||
16 | |||
17 | #ifndef __LINUX_IRQCHIP_SUNXI_H | ||
18 | #define __LINUX_IRQCHIP_SUNXI_H | ||
19 | |||
20 | #include <asm/exception.h> | ||
21 | |||
22 | extern void sunxi_init_irq(void); | ||
23 | |||
24 | extern asmlinkage void __exception_irq_entry sunxi_handle_irq( | ||
25 | struct pt_regs *regs); | ||
26 | |||
27 | #endif | ||
diff --git a/include/linux/platform_data/usb-exynos.h b/include/linux/platform_data/usb-ohci-exynos.h index c256c595be5e..c256c595be5e 100644 --- a/include/linux/platform_data/usb-exynos.h +++ b/include/linux/platform_data/usb-ohci-exynos.h | |||
diff --git a/include/linux/sunxi_timer.h b/include/linux/sunxi_timer.h deleted file mode 100644 index 18081787e5f3..000000000000 --- a/include/linux/sunxi_timer.h +++ /dev/null | |||
@@ -1,24 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2012 Maxime Ripard | ||
3 | * | ||
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | */ | ||
16 | |||
17 | #ifndef __SUNXI_TIMER_H | ||
18 | #define __SUNXI_TIMER_H | ||
19 | |||
20 | #include <asm/mach/time.h> | ||
21 | |||
22 | void sunxi_timer_init(void); | ||
23 | |||
24 | #endif | ||
diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c index 3a2aa1d19b93..41a6136e3535 100644 --- a/sound/soc/mxs/mxs-saif.c +++ b/sound/soc/mxs/mxs-saif.c | |||
@@ -33,11 +33,12 @@ | |||
33 | #include <sound/pcm_params.h> | 33 | #include <sound/pcm_params.h> |
34 | #include <sound/soc.h> | 34 | #include <sound/soc.h> |
35 | #include <asm/mach-types.h> | 35 | #include <asm/mach-types.h> |
36 | #include <mach/hardware.h> | ||
37 | #include <mach/mxs.h> | ||
38 | 36 | ||
39 | #include "mxs-saif.h" | 37 | #include "mxs-saif.h" |
40 | 38 | ||
39 | #define MXS_SET_ADDR 0x4 | ||
40 | #define MXS_CLR_ADDR 0x8 | ||
41 | |||
41 | static struct mxs_saif *mxs_saif[2]; | 42 | static struct mxs_saif *mxs_saif[2]; |
42 | 43 | ||
43 | /* | 44 | /* |