2 files changed, 15 insertions, 60 deletions

diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 615e5b1fb025..6bf626700557 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -46,15 +46,8 @@
 
 static bool is_offset_valid;
 static u8 smps_offset;
-/*
- * Flag to ensure Smartreflex bit in TWL
- * being cleared in board file is not overwritten.
- */
-static bool __initdata twl_sr_enable_autoinit;
 
-#define TWL4030_DCDC_GLOBAL_CFG        0x06
 #define REG_SMPS_OFFSET         0xE0
-#define SMARTREFLEX_ENABLE     BIT(3)
 
 static unsigned long twl4030_vsel_to_uv(const u8 vsel)
 {
@@ -251,18 +244,6 @@ int __init omap3_twl_init(void)
         if (!cpu_is_omap34xx())
                 return -ENODEV;
 
-        /*
-         * The smartreflex bit on twl4030 specifies if the setting of voltage
-         * is done over the I2C_SR path. Since this setting is independent of
-         * the actual usage of smartreflex AVS module, we enable TWL SR bit
-         * by default irrespective of whether smartreflex AVS module is enabled
-         * on the OMAP side or not. This is because without this bit enabled,
-         * the voltage scaling through vp forceupdate/bypass mechanism of
-         * voltage scaling will not function on TWL over I2C_SR.
-         */
-        if (!twl_sr_enable_autoinit)
-                omap3_twl_set_sr_bit(true);
-
         voltdm = voltdm_lookup("mpu_iva");
         omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
 
@@ -271,44 +252,3 @@ int __init omap3_twl_init(void)
 
         return 0;
 }
-
-/**
- * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
- * @enable: enable SR mode in twl or not
- *
- * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
- * voltage scaling through OMAP SR works. Else, the smartreflex bit
- * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
- * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
- * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
- * in those scenarios this bit is to be cleared (enable = false).
- *
- * Returns 0 on success, error is returned if I2C read/write fails.
- */
-int __init omap3_twl_set_sr_bit(bool enable)
-{
-        u8 temp;
-        int ret;
-        if (twl_sr_enable_autoinit)
-                pr_warning("%s: unexpected multiple calls\n", __func__);
-
-        ret = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
-                              TWL4030_DCDC_GLOBAL_CFG);
-        if (ret)
-                goto err;
-
-        if (enable)
-                temp |= SMARTREFLEX_ENABLE;
-        else
-                temp &= ~SMARTREFLEX_ENABLE;
-
-        ret = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
-                               TWL4030_DCDC_GLOBAL_CFG);
-        if (!ret) {
-                twl_sr_enable_autoinit = true;
-                return 0;
-        }
-err:
-        pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
-        return ret;
-}
diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index ed718328eff1..ad7d04f95dd1 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -98,7 +98,11 @@
 #define TWL4030_BASEADD_BACKUP          0x0014
 #define TWL4030_BASEADD_INT             0x002E
 #define TWL4030_BASEADD_PM_MASTER       0x0036
+
 #define TWL4030_BASEADD_PM_RECEIVER     0x005B
+#define TWL4030_DCDC_GLOBAL_CFG         0x06
+#define SMARTREFLEX_ENABLE              BIT(3)
+
 #define TWL4030_BASEADD_RTC             0x001C
 #define TWL4030_BASEADD_SECURED_REG     0x0000
 
@@ -1204,6 +1208,11 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
          * Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
          * Program I2C_SCL_CTRL_PU(bit 0)=0, I2C_SDA_CTRL_PU (bit 2)=0,
          * SR_I2C_SCL_CTRL_PU(bit 4)=0 and SR_I2C_SDA_CTRL_PU(bit 6)=0.
+         *
+         * Also, always enable SmartReflex bit as that's needed for omaps to
+         * to do anything over I2C4 for voltage scaling even if SmartReflex
+         * is disabled. Without the SmartReflex bit omap sys_clkreq idle
+         * signal will never trigger for retention idle.
          */
         if (twl_class_is_4030()) {
                 u8 temp;
@@ -1212,6 +1221,12 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
                 temp &= ~(SR_I2C_SDA_CTRL_PU | SR_I2C_SCL_CTRL_PU | \
                         I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU);
                 twl_i2c_write_u8(TWL4030_MODULE_INTBR, temp, REG_GPPUPDCTR1);
+
+                twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
+                                TWL4030_DCDC_GLOBAL_CFG);
+                temp |= SMARTREFLEX_ENABLE;
+                twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
+                                 TWL4030_DCDC_GLOBAL_CFG);
         }
 
         if (node) {