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-rw-r--r--Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt232
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1* Texas Instruments Keystone Navigator Queue Management SubSystem driver
2
3The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
4the main hardware sub system which forms the backbone of the Keystone
5multi-core Navigator. QMSS consist of queue managers, packed-data structure
6processors(PDSP), linking RAM, descriptor pools and infrastructure
7Packet DMA.
8The Queue Manager is a hardware module that is responsible for accelerating
9management of the packet queues. Packets are queued/de-queued by writing or
10reading descriptor address to a particular memory mapped location. The PDSPs
11perform QMSS related functions like accumulation, QoS, or event management.
12Linking RAM registers are used to link the descriptors which are stored in
13descriptor RAM. Descriptor RAM is configurable as internal or external memory.
14The QMSS driver manages the PDSP setups, linking RAM regions,
15queue pool management (allocation, push, pop and notify) and descriptor
16pool management.
17
18
19Required properties:
20- compatible : Must be "ti,keystone-navigator-qmss";
21- clocks : phandle to the reference clock for this device.
22- queue-range : <start number> total range of queue numbers for the device.
23- linkram0 : <address size> for internal link ram, where size is the total
24 link ram entries.
25- linkram1 : <address size> for external link ram, where size is the total
26 external link ram entries. If the address is specified as "0"
27 driver will allocate memory.
28- qmgrs : child node describing the individual queue managers on the
29 SoC. On keystone 1 devices there should be only one node.
30 On keystone 2 devices there can be more than 1 node.
31 -- managed-queues : the actual queues managed by each queue manager
32 instance, specified as <"base queue #" "# of queues">.
33 -- reg : Address and size of the register set for the device.
34 Register regions should be specified in the following
35 order
36 - Queue Peek region.
37 - Queue status RAM.
38 - Queue configuration region.
39 - Descriptor memory setup region.
40 - Queue Management/Queue Proxy region for queue Push.
41 - Queue Management/Queue Proxy region for queue Pop.
42- queue-pools : child node classifying the queue ranges into pools.
43 Queue ranges are grouped into 3 type of pools:
44 - qpend : pool of qpend(interruptible) queues
45 - general-purpose : pool of general queues, primarly used
46 as free descriptor queues or the
47 transmit DMA queues.
48 - accumulator : pool of queues on PDSP accumulator channel
49 Each range can have the following properties:
50 -- qrange : number of queues to use per queue range, specified as
51 <"base queue #" "# of queues">.
52 -- interrupts : Optional property to specify the interrupt mapping
53 for interruptible queues. The driver additionaly sets
54 the interrupt affinity hint based on the cpu mask.
55 -- qalloc-by-id : Optional property to specify that the queues in this
56 range can only be allocated by queue id.
57 -- accumulator : Accumulator channel specification. Any of the PDSPs in
58 QMSS can be loaded with the accumulator firmware. The
59 accumulator firmware’s job is to poll a select number of
60 queues looking for descriptors that have been pushed
61 into them. Descriptors are popped from the queue and
62 placed in a buffer provided by the host. When the list
63 becomes full or a programmed time period expires, the
64 accumulator triggers an interrupt to the host to read
65 the buffer for descriptor information. This firmware
66 comes in 16, 32, and 48 channel builds. Each of these
67 channels can be configured to monitor 32 contiguous
68 queues. Accumulator channel property is specified as:
69 <pdsp-id, channel, entries, pacing mode, latency>
70 pdsp-id : QMSS PDSP running accumulator firmware
71 on which the channel has to be
72 configured
73 channel : Accumulator channel number
74 entries : Size of the accumulator descriptor list
75 pacing mode : Interrupt pacing mode
76 0 : None, i.e interrupt on list full only
77 1 : Time delay since last interrupt
78 2 : Time delay since first new packet
79 3 : Time delay since last new packet
80 latency : time to delay the interrupt, specified
81 in microseconds.
82 -- multi-queue : Optional property to specify that the channel has to
83 monitor upto 32 queues starting at the base queue #.
84- descriptor-regions : child node describing the memory regions for keystone
85 navigator packet DMA descriptors. The memory for
86 descriptors will be allocated by the driver.
87 -- id : region number in QMSS.
88 -- region-spec : specifies the number of descriptors in the
89 region, specified as
90 <"# of descriptors" "descriptor size">.
91 -- link-index : start index, i.e. index of the first
92 descriptor in the region.
93
94Optional properties:
95- dma-coherent : Present if DMA operations are coherent.
96- pdsps : child node describing the PDSP configuration.
97 -- firmware : firmware to be loaded on the PDSP.
98 -- id : the qmss pdsp that will run the firmware.
99 -- reg : Address and size of the register set for the PDSP.
100 Register regions should be specified in the following
101 order
102 - PDSP internal RAM region.
103 - PDSP control/status region registers.
104 - QMSS interrupt distributor registers.
105 - PDSP command interface region.
106
107Example:
108
109qmss: qmss@2a40000 {
110 compatible = "ti,keystone-qmss";
111 dma-coherent;
112 #address-cells = <1>;
113 #size-cells = <1>;
114 clocks = <&chipclk13>;
115 ranges;
116 queue-range = <0 0x4000>;
117 linkram0 = <0x100000 0x8000>;
118 linkram1 = <0x0 0x10000>;
119
120 qmgrs {
121 #address-cells = <1>;
122 #size-cells = <1>;
123 ranges;
124 qmgr0 {
125 managed-queues = <0 0x2000>;
126 reg = <0x2a40000 0x20000>,
127 <0x2a06000 0x400>,
128 <0x2a02000 0x1000>,
129 <0x2a03000 0x1000>,
130 <0x23a80000 0x20000>,
131 <0x2a80000 0x20000>;
132 };
133
134 qmgr1 {
135 managed-queues = <0x2000 0x2000>;
136 reg = <0x2a60000 0x20000>,
137 <0x2a06400 0x400>,
138 <0x2a04000 0x1000>,
139 <0x2a05000 0x1000>,
140 <0x23aa0000 0x20000>,
141 <0x2aa0000 0x20000>;
142 };
143 };
144 queue-pools {
145 qpend {
146 qpend-0 {
147 qrange = <658 8>;
148 interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
149 0 43 0xf04 0 44 0xf04 0 45 0xf04
150 0 46 0xf04 0 47 0xf04>;
151 };
152 qpend-1 {
153 qrange = <8704 16>;
154 interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
155 0 51 0xf04 0 52 0xf04 0 53 0xf04
156 0 54 0xf04 0 55 0xf04 0 56 0xf04
157 0 57 0xf04 0 58 0xf04 0 59 0xf04
158 0 60 0xf04 0 61 0xf04 0 62 0xf04
159 0 63 0xf04>;
160 qalloc-by-id;
161 };
162 qpend-2 {
163 qrange = <8720 16>;
164 interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
165 0 59 0xf04 0 68 0xf04 0 69 0xf04
166 0 70 0xf04 0 71 0xf04 0 72 0xf04
167 0 73 0xf04 0 74 0xf04 0 75 0xf04
168 0 76 0xf04 0 77 0xf04 0 78 0xf04
169 0 79 0xf04>;
170 };
171 };
172 general-purpose {
173 gp-0 {
174 qrange = <4000 64>;
175 };
176 netcp-tx {
177 qrange = <640 9>;
178 qalloc-by-id;
179 };
180 };
181 accumulator {
182 acc-0 {
183 qrange = <128 32>;
184 accumulator = <0 36 16 2 50>;
185 interrupts = <0 215 0xf01>;
186 multi-queue;
187 qalloc-by-id;
188 };
189 acc-1 {
190 qrange = <160 32>;
191 accumulator = <0 37 16 2 50>;
192 interrupts = <0 216 0xf01>;
193 multi-queue;
194 };
195 acc-2 {
196 qrange = <192 32>;
197 accumulator = <0 38 16 2 50>;
198 interrupts = <0 217 0xf01>;
199 multi-queue;
200 };
201 acc-3 {
202 qrange = <224 32>;
203 accumulator = <0 39 16 2 50>;
204 interrupts = <0 218 0xf01>;
205 multi-queue;
206 };
207 };
208 };
209 descriptor-regions {
210 #address-cells = <1>;
211 #size-cells = <1>;
212 ranges;
213 region-12 {
214 id = <12>;
215 region-spec = <8192 128>; /* num_desc desc_size */
216 link-index = <0x4000>;
217 };
218 };
219 pdsps {
220 #address-cells = <1>;
221 #size-cells = <1>;
222 ranges;
223 pdsp0@0x2a10000 {
224 firmware = "keystone/qmss_pdsp_acc48_k2_le_1_0_0_8.fw";
225 reg = <0x2a10000 0x1000>,
226 <0x2a0f000 0x100>,
227 <0x2a0c000 0x3c8>,
228 <0x2a20000 0x4000>;
229 id = <0>;
230 };
231 };
232}; /* qmss */
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