diff options
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event_intel_ds.c | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c index 07d9a052ee72..32e9ed81cd00 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c | |||
| @@ -206,6 +206,8 @@ union hsw_tsx_tuning { | |||
| 206 | u64 value; | 206 | u64 value; |
| 207 | }; | 207 | }; |
| 208 | 208 | ||
| 209 | #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL | ||
| 210 | |||
| 209 | void init_debug_store_on_cpu(int cpu) | 211 | void init_debug_store_on_cpu(int cpu) |
| 210 | { | 212 | { |
| 211 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; | 213 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; |
| @@ -807,6 +809,16 @@ static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs) | |||
| 807 | return 0; | 809 | return 0; |
| 808 | } | 810 | } |
| 809 | 811 | ||
| 812 | static inline u64 intel_hsw_transaction(struct pebs_record_hsw *pebs) | ||
| 813 | { | ||
| 814 | u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32; | ||
| 815 | |||
| 816 | /* For RTM XABORTs also log the abort code from AX */ | ||
| 817 | if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1)) | ||
| 818 | txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT; | ||
| 819 | return txn; | ||
| 820 | } | ||
| 821 | |||
| 810 | static void __intel_pmu_pebs_event(struct perf_event *event, | 822 | static void __intel_pmu_pebs_event(struct perf_event *event, |
| 811 | struct pt_regs *iregs, void *__pebs) | 823 | struct pt_regs *iregs, void *__pebs) |
| 812 | { | 824 | { |
| @@ -885,10 +897,14 @@ static void __intel_pmu_pebs_event(struct perf_event *event, | |||
| 885 | x86_pmu.intel_cap.pebs_format >= 1) | 897 | x86_pmu.intel_cap.pebs_format >= 1) |
| 886 | data.addr = pebs->dla; | 898 | data.addr = pebs->dla; |
| 887 | 899 | ||
| 888 | /* Only set the TSX weight when no memory weight was requested. */ | 900 | if (x86_pmu.intel_cap.pebs_format >= 2) { |
| 889 | if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) && !fll && | 901 | /* Only set the TSX weight when no memory weight. */ |
| 890 | (x86_pmu.intel_cap.pebs_format >= 2)) | 902 | if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) && !fll) |
| 891 | data.weight = intel_hsw_weight(pebs); | 903 | data.weight = intel_hsw_weight(pebs); |
| 904 | |||
| 905 | if (event->attr.sample_type & PERF_SAMPLE_TRANSACTION) | ||
| 906 | data.txn = intel_hsw_transaction(pebs); | ||
| 907 | } | ||
| 892 | 908 | ||
| 893 | if (has_branch_stack(event)) | 909 | if (has_branch_stack(event)) |
| 894 | data.br_stack = &cpuc->lbr_stack; | 910 | data.br_stack = &cpuc->lbr_stack; |
