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-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_calib.c70
1 files changed, 1 insertions, 69 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
index 9f54cb58053c..28248248add2 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
@@ -1235,46 +1235,12 @@ static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
1235 struct ath9k_hw_cal_data *caldata = ah->caldata; 1235 struct ath9k_hw_cal_data *caldata = ah->caldata;
1236 bool txiqcal_done = false; 1236 bool txiqcal_done = false;
1237 bool is_reusable = true, status = true; 1237 bool is_reusable = true, status = true;
1238 bool run_rtt_cal = false, run_agc_cal, sep_iq_cal = false; 1238 bool run_agc_cal = false, sep_iq_cal = false;
1239 bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
1240 u32 rx_delay = 0; 1239 u32 rx_delay = 0;
1241 u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
1242 AR_PHY_AGC_CONTROL_FLTR_CAL |
1243 AR_PHY_AGC_CONTROL_PKDET_CAL;
1244 1240
1245 /* Use chip chainmask only for calibration */ 1241 /* Use chip chainmask only for calibration */
1246 ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask); 1242 ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
1247 1243
1248 if (rtt) {
1249 if (!ar9003_hw_rtt_restore(ah, chan))
1250 run_rtt_cal = true;
1251
1252 if (run_rtt_cal)
1253 ath_dbg(common, CALIBRATE, "RTT calibration to be done\n");
1254 }
1255
1256 run_agc_cal = run_rtt_cal;
1257
1258 if (run_rtt_cal) {
1259 ar9003_hw_rtt_enable(ah);
1260 ar9003_hw_rtt_set_mask(ah, 0x00);
1261 ar9003_hw_rtt_clear_hist(ah);
1262 }
1263
1264 if (rtt) {
1265 if (!run_rtt_cal) {
1266 agc_ctrl = REG_READ(ah, AR_PHY_AGC_CONTROL);
1267 agc_supp_cals &= agc_ctrl;
1268 agc_ctrl &= ~(AR_PHY_AGC_CONTROL_OFFSET_CAL |
1269 AR_PHY_AGC_CONTROL_FLTR_CAL |
1270 AR_PHY_AGC_CONTROL_PKDET_CAL);
1271 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
1272 } else {
1273 if (ah->ah_flags & AH_FASTCC)
1274 run_agc_cal = true;
1275 }
1276 }
1277
1278 if (ah->enabled_cals & TX_CL_CAL) { 1244 if (ah->enabled_cals & TX_CL_CAL) {
1279 if (caldata && test_bit(TXCLCAL_DONE, &caldata->cal_flags)) 1245 if (caldata && test_bit(TXCLCAL_DONE, &caldata->cal_flags))
1280 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, 1246 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
@@ -1313,9 +1279,6 @@ static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
1313 } 1279 }
1314 1280
1315skip_tx_iqcal: 1281skip_tx_iqcal:
1316 if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
1317 ar9003_mci_init_cal_req(ah, &is_reusable);
1318
1319 if (sep_iq_cal) { 1282 if (sep_iq_cal) {
1320 txiqcal_done = ar9003_hw_tx_iq_cal_run(ah); 1283 txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
1321 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 1284 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
@@ -1342,8 +1305,6 @@ skip_tx_iqcal:
1342 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, 1305 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1343 AR_PHY_AGC_CONTROL_CAL, 1306 AR_PHY_AGC_CONTROL_CAL,
1344 0, AH_WAIT_TIMEOUT); 1307 0, AH_WAIT_TIMEOUT);
1345
1346 ar9003_hw_do_manual_peak_cal(ah, chan, run_rtt_cal);
1347 } 1308 }
1348 1309
1349 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) { 1310 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
@@ -1351,18 +1312,7 @@ skip_tx_iqcal:
1351 udelay(5); 1312 udelay(5);
1352 } 1313 }
1353 1314
1354 if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
1355 ar9003_mci_init_cal_done(ah);
1356
1357 if (rtt && !run_rtt_cal) {
1358 agc_ctrl |= agc_supp_cals;
1359 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
1360 }
1361
1362 if (!status) { 1315 if (!status) {
1363 if (run_rtt_cal)
1364 ar9003_hw_rtt_disable(ah);
1365
1366 ath_dbg(common, CALIBRATE, 1316 ath_dbg(common, CALIBRATE,
1367 "offset calibration failed to complete in %d ms; noisy environment?\n", 1317 "offset calibration failed to complete in %d ms; noisy environment?\n",
1368 AH_WAIT_TIMEOUT / 1000); 1318 AH_WAIT_TIMEOUT / 1000);
@@ -1376,24 +1326,6 @@ skip_tx_iqcal:
1376 1326
1377 ar9003_hw_cl_cal_post_proc(ah, is_reusable); 1327 ar9003_hw_cl_cal_post_proc(ah, is_reusable);
1378 1328
1379 if (run_rtt_cal && caldata) {
1380 if (is_reusable) {
1381 if (!ath9k_hw_rfbus_req(ah)) {
1382 ath_err(ath9k_hw_common(ah),
1383 "Could not stop baseband\n");
1384 } else {
1385 ar9003_hw_rtt_fill_hist(ah);
1386
1387 if (test_bit(SW_PKDET_DONE, &caldata->cal_flags))
1388 ar9003_hw_rtt_load_hist(ah);
1389 }
1390
1391 ath9k_hw_rfbus_done(ah);
1392 }
1393
1394 ar9003_hw_rtt_disable(ah);
1395 }
1396
1397 /* Revert chainmask to runtime parameters */ 1329 /* Revert chainmask to runtime parameters */
1398 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); 1330 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
1399 1331