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-rw-r--r--arch/cris/arch-v32/mach-fs/pinmux.c152
-rw-r--r--arch/cris/include/arch-v32/mach-fs/mach/pinmux.h2
2 files changed, 83 insertions, 71 deletions
diff --git a/arch/cris/arch-v32/mach-fs/pinmux.c b/arch/cris/arch-v32/mach-fs/pinmux.c
index 38f29eec14a6..05a04708b8eb 100644
--- a/arch/cris/arch-v32/mach-fs/pinmux.c
+++ b/arch/cris/arch-v32/mach-fs/pinmux.c
@@ -26,7 +26,29 @@ static DEFINE_SPINLOCK(pinmux_lock);
26 26
27static void crisv32_pinmux_set(int port); 27static void crisv32_pinmux_set(int port);
28 28
29int crisv32_pinmux_init(void) 29static int __crisv32_pinmux_alloc(int port, int first_pin, int last_pin,
30 enum pin_mode mode)
31{
32 int i;
33
34 for (i = first_pin; i <= last_pin; i++) {
35 if ((pins[port][i] != pinmux_none)
36 && (pins[port][i] != pinmux_gpio)
37 && (pins[port][i] != mode)) {
38#ifdef DEBUG
39 panic("Pinmux alloc failed!\n");
40#endif
41 return -EPERM;
42 }
43 }
44
45 for (i = first_pin; i <= last_pin; i++)
46 pins[port][i] = mode;
47
48 crisv32_pinmux_set(port);
49}
50
51static int crisv32_pinmux_init(void)
30{ 52{
31 static int initialized; 53 static int initialized;
32 54
@@ -37,20 +59,20 @@ int crisv32_pinmux_init(void)
37 pa.pa0 = pa.pa1 = pa.pa2 = pa.pa3 = 59 pa.pa0 = pa.pa1 = pa.pa2 = pa.pa3 =
38 pa.pa4 = pa.pa5 = pa.pa6 = pa.pa7 = regk_pinmux_yes; 60 pa.pa4 = pa.pa5 = pa.pa6 = pa.pa7 = regk_pinmux_yes;
39 REG_WR(pinmux, regi_pinmux, rw_pa, pa); 61 REG_WR(pinmux, regi_pinmux, rw_pa, pa);
40 crisv32_pinmux_alloc(PORT_B, 0, PORT_PINS - 1, pinmux_gpio); 62 __crisv32_pinmux_alloc(PORT_B, 0, PORT_PINS - 1, pinmux_gpio);
41 crisv32_pinmux_alloc(PORT_C, 0, PORT_PINS - 1, pinmux_gpio); 63 __crisv32_pinmux_alloc(PORT_C, 0, PORT_PINS - 1, pinmux_gpio);
42 crisv32_pinmux_alloc(PORT_D, 0, PORT_PINS - 1, pinmux_gpio); 64 __crisv32_pinmux_alloc(PORT_D, 0, PORT_PINS - 1, pinmux_gpio);
43 crisv32_pinmux_alloc(PORT_E, 0, PORT_PINS - 1, pinmux_gpio); 65 __crisv32_pinmux_alloc(PORT_E, 0, PORT_PINS - 1, pinmux_gpio);
44 } 66 }
45 67
46 return 0; 68 return 0;
47} 69}
48 70
49int 71int crisv32_pinmux_alloc(int port, int first_pin, int last_pin,
50crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode) 72 enum pin_mode mode)
51{ 73{
52 int i;
53 unsigned long flags; 74 unsigned long flags;
75 int ret;
54 76
55 crisv32_pinmux_init(); 77 crisv32_pinmux_init();
56 78
@@ -59,26 +81,11 @@ crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode)
59 81
60 spin_lock_irqsave(&pinmux_lock, flags); 82 spin_lock_irqsave(&pinmux_lock, flags);
61 83
62 for (i = first_pin; i <= last_pin; i++) { 84 ret = __crisv32_pinmux_alloc(port, first_pin, last_pin, mode);
63 if ((pins[port][i] != pinmux_none)
64 && (pins[port][i] != pinmux_gpio)
65 && (pins[port][i] != mode)) {
66 spin_unlock_irqrestore(&pinmux_lock, flags);
67#ifdef DEBUG
68 panic("Pinmux alloc failed!\n");
69#endif
70 return -EPERM;
71 }
72 }
73
74 for (i = first_pin; i <= last_pin; i++)
75 pins[port][i] = mode;
76
77 crisv32_pinmux_set(port);
78 85
79 spin_unlock_irqrestore(&pinmux_lock, flags); 86 spin_unlock_irqrestore(&pinmux_lock, flags);
80 87
81 return 0; 88 return ret;
82} 89}
83 90
84int crisv32_pinmux_alloc_fixed(enum fixed_function function) 91int crisv32_pinmux_alloc_fixed(enum fixed_function function)
@@ -98,58 +105,58 @@ int crisv32_pinmux_alloc_fixed(enum fixed_function function)
98 105
99 switch (function) { 106 switch (function) {
100 case pinmux_ser1: 107 case pinmux_ser1:
101 ret = crisv32_pinmux_alloc(PORT_C, 4, 7, pinmux_fixed); 108 ret = __crisv32_pinmux_alloc(PORT_C, 4, 7, pinmux_fixed);
102 hwprot.ser1 = regk_pinmux_yes; 109 hwprot.ser1 = regk_pinmux_yes;
103 break; 110 break;
104 case pinmux_ser2: 111 case pinmux_ser2:
105 ret = crisv32_pinmux_alloc(PORT_C, 8, 11, pinmux_fixed); 112 ret = __crisv32_pinmux_alloc(PORT_C, 8, 11, pinmux_fixed);
106 hwprot.ser2 = regk_pinmux_yes; 113 hwprot.ser2 = regk_pinmux_yes;
107 break; 114 break;
108 case pinmux_ser3: 115 case pinmux_ser3:
109 ret = crisv32_pinmux_alloc(PORT_C, 12, 15, pinmux_fixed); 116 ret = __crisv32_pinmux_alloc(PORT_C, 12, 15, pinmux_fixed);
110 hwprot.ser3 = regk_pinmux_yes; 117 hwprot.ser3 = regk_pinmux_yes;
111 break; 118 break;
112 case pinmux_sser0: 119 case pinmux_sser0:
113 ret = crisv32_pinmux_alloc(PORT_C, 0, 3, pinmux_fixed); 120 ret = __crisv32_pinmux_alloc(PORT_C, 0, 3, pinmux_fixed);
114 ret |= crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed); 121 ret |= __crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed);
115 hwprot.sser0 = regk_pinmux_yes; 122 hwprot.sser0 = regk_pinmux_yes;
116 break; 123 break;
117 case pinmux_sser1: 124 case pinmux_sser1:
118 ret = crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed); 125 ret = __crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed);
119 hwprot.sser1 = regk_pinmux_yes; 126 hwprot.sser1 = regk_pinmux_yes;
120 break; 127 break;
121 case pinmux_ata0: 128 case pinmux_ata0:
122 ret = crisv32_pinmux_alloc(PORT_D, 5, 7, pinmux_fixed); 129 ret = __crisv32_pinmux_alloc(PORT_D, 5, 7, pinmux_fixed);
123 ret |= crisv32_pinmux_alloc(PORT_D, 15, 17, pinmux_fixed); 130 ret |= __crisv32_pinmux_alloc(PORT_D, 15, 17, pinmux_fixed);
124 hwprot.ata0 = regk_pinmux_yes; 131 hwprot.ata0 = regk_pinmux_yes;
125 break; 132 break;
126 case pinmux_ata1: 133 case pinmux_ata1:
127 ret = crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed); 134 ret = __crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed);
128 ret |= crisv32_pinmux_alloc(PORT_E, 17, 17, pinmux_fixed); 135 ret |= __crisv32_pinmux_alloc(PORT_E, 17, 17, pinmux_fixed);
129 hwprot.ata1 = regk_pinmux_yes; 136 hwprot.ata1 = regk_pinmux_yes;
130 break; 137 break;
131 case pinmux_ata2: 138 case pinmux_ata2:
132 ret = crisv32_pinmux_alloc(PORT_C, 11, 15, pinmux_fixed); 139 ret = __crisv32_pinmux_alloc(PORT_C, 11, 15, pinmux_fixed);
133 ret |= crisv32_pinmux_alloc(PORT_E, 3, 3, pinmux_fixed); 140 ret |= __crisv32_pinmux_alloc(PORT_E, 3, 3, pinmux_fixed);
134 hwprot.ata2 = regk_pinmux_yes; 141 hwprot.ata2 = regk_pinmux_yes;
135 break; 142 break;
136 case pinmux_ata3: 143 case pinmux_ata3:
137 ret = crisv32_pinmux_alloc(PORT_C, 8, 10, pinmux_fixed); 144 ret = __crisv32_pinmux_alloc(PORT_C, 8, 10, pinmux_fixed);
138 ret |= crisv32_pinmux_alloc(PORT_C, 0, 2, pinmux_fixed); 145 ret |= __crisv32_pinmux_alloc(PORT_C, 0, 2, pinmux_fixed);
139 hwprot.ata2 = regk_pinmux_yes; 146 hwprot.ata2 = regk_pinmux_yes;
140 break; 147 break;
141 case pinmux_ata: 148 case pinmux_ata:
142 ret = crisv32_pinmux_alloc(PORT_B, 0, 15, pinmux_fixed); 149 ret = __crisv32_pinmux_alloc(PORT_B, 0, 15, pinmux_fixed);
143 ret |= crisv32_pinmux_alloc(PORT_D, 8, 15, pinmux_fixed); 150 ret |= __crisv32_pinmux_alloc(PORT_D, 8, 15, pinmux_fixed);
144 hwprot.ata = regk_pinmux_yes; 151 hwprot.ata = regk_pinmux_yes;
145 break; 152 break;
146 case pinmux_eth1: 153 case pinmux_eth1:
147 ret = crisv32_pinmux_alloc(PORT_E, 0, 17, pinmux_fixed); 154 ret = __crisv32_pinmux_alloc(PORT_E, 0, 17, pinmux_fixed);
148 hwprot.eth1 = regk_pinmux_yes; 155 hwprot.eth1 = regk_pinmux_yes;
149 hwprot.eth1_mgm = regk_pinmux_yes; 156 hwprot.eth1_mgm = regk_pinmux_yes;
150 break; 157 break;
151 case pinmux_timer: 158 case pinmux_timer:
152 ret = crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed); 159 ret = __crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed);