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-rw-r--r--arch/arm/mach-omap2/Kconfig3
-rw-r--r--arch/arm/mach-omap2/Makefile1
-rw-r--r--arch/arm/mach-omap2/mux.h12
-rw-r--r--arch/arm/mach-omap2/mux44xx.c900
-rw-r--r--arch/arm/mach-omap2/mux44xx.h277
5 files changed, 1193 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index ab784bfde908..e14c73d81997 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -85,6 +85,9 @@ config OMAP_PACKAGE_CUS
85config OMAP_PACKAGE_CBP 85config OMAP_PACKAGE_CBP
86 bool 86 bool
87 87
88config OMAP_PACKAGE_CBL
89 bool
90
88comment "OMAP Board Type" 91comment "OMAP Board Type"
89 depends on ARCH_OMAP2PLUS 92 depends on ARCH_OMAP2PLUS
90 93
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 60e51bcf53bd..d32d660abab1 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -42,6 +42,7 @@ AFLAGS_sram34xx.o :=-Wa,-march=armv7-a
42obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o 42obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o
43obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o 43obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o
44obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o 44obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
45obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o
45 46
46# SMS/SDRC 47# SMS/SDRC
47obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o 48obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 86549bedd526..7aca779b588c 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -10,6 +10,7 @@
10#include "mux2420.h" 10#include "mux2420.h"
11#include "mux2430.h" 11#include "mux2430.h"
12#include "mux34xx.h" 12#include "mux34xx.h"
13#include "mux44xx.h"
13 14
14#define OMAP_MUX_TERMINATOR 0xffff 15#define OMAP_MUX_TERMINATOR 0xffff
15 16
@@ -37,6 +38,9 @@
37#define OMAP_OFF_PULL_UP (1 << 13) 38#define OMAP_OFF_PULL_UP (1 << 13)
38#define OMAP_WAKEUP_EN (1 << 14) 39#define OMAP_WAKEUP_EN (1 << 14)
39 40
41/* 44xx specific mux bit defines */
42#define OMAP_WAKEUP_EVENT (1 << 15)
43
40/* Active pin states */ 44/* Active pin states */
41#define OMAP_PIN_OUTPUT 0 45#define OMAP_PIN_OUTPUT 0
42#define OMAP_PIN_INPUT OMAP_INPUT_EN 46#define OMAP_PIN_INPUT OMAP_INPUT_EN
@@ -58,6 +62,7 @@
58 62
59/* Flags for omapX_mux_init */ 63/* Flags for omapX_mux_init */
60#define OMAP_PACKAGE_MASK 0xffff 64#define OMAP_PACKAGE_MASK 0xffff
65#define OMAP_PACKAGE_CBL 7 /* 547-pin 0.40 0.40 */
61#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */ 66#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */
62#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */ 67#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */
63#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */ 68#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */
@@ -240,6 +245,13 @@ int omap2430_mux_init(struct omap_board_mux *board_mux, int flags);
240int omap3_mux_init(struct omap_board_mux *board_mux, int flags); 245int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
241 246
242/** 247/**
248 * omap4_mux_init() - initialize mux system with board specific set
249 * @board_mux: Board specific mux table
250 * @flags: OMAP package type used for the board
251 */
252int omap4_mux_init(struct omap_board_mux *board_mux, int flags);
253
254/**
243 * omap_mux_init - private mux init function, do not call 255 * omap_mux_init - private mux init function, do not call
244 */ 256 */
245int omap_mux_init(const char *name, u32 flags, 257int omap_mux_init(const char *name, u32 flags,
diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c
new file mode 100644
index 000000000000..5e9d60a18146
--- /dev/null
+++ b/arch/arm/mach-omap2/mux44xx.c
@@ -0,0 +1,900 @@
1/*
2 * OMAP44xx ES1.0 pin mux definition
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 *
8 * - Based on mux34xx.c done by Tony Lindgren <tony@atomide.com>
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20#include <linux/module.h>
21#include <linux/init.h>
22
23#include "mux.h"
24
25#ifdef CONFIG_OMAP_MUX
26
27#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
28{ \
29 .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
30 .gpio = (g), \
31 .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
32}
33
34#else
35
36#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
37{ \
38 .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
39 .gpio = (g), \
40}
41
42#endif
43
44#define _OMAP4_BALLENTRY(M0, bb, bt) \
45{ \
46 .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
47 .balls = { bb, bt }, \
48}
49
50/*
51 * Superset of all mux modes for omap4
52 */
53static struct omap_mux __initdata omap4_core_muxmodes[] = {
54 _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
55 NULL, NULL, NULL, NULL),
56 _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
57 NULL, NULL, NULL, NULL),
58 _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
59 NULL, NULL, NULL, NULL),
60 _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
61 NULL, NULL, NULL, NULL),
62 _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4",
63 "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
64 _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5",
65 "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
66 _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6",
67 "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
68 _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7",
69 "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
70 _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
71 "gpio_32", NULL, NULL, NULL, NULL),
72 _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
73 "gpio_33", NULL, NULL, NULL, NULL),
74 _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
75 "gpio_34", NULL, NULL, NULL, NULL),
76 _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
77 "gpio_35", NULL, NULL, NULL, NULL),
78 _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
79 "gpio_36", NULL, NULL, NULL, NULL),
80 _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
81 "gpio_37", NULL, NULL, NULL, NULL),
82 _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
83 "gpio_38", NULL, NULL, NULL, NULL),
84 _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
85 "gpio_39", NULL, NULL, NULL, NULL),
86 _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
87 "gpio_40", "venc_656_data0", NULL, NULL, NULL),
88 _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1",
89 "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
90 _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2",
91 "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
92 _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3",
93 "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
94 _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4",
95 "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
96 _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5",
97 "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
98 _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6",
99 "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
100 _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7",
101 "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
102 _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", NULL, "c2c_clkout0",
103 "gpio_48", NULL, NULL, NULL, "safe_mode"),
104 _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1",
105 "gpio_49", NULL, NULL, NULL, "safe_mode"),
106 _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50",
107 "sys_ndmareq0", NULL, NULL, NULL),
108 _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6",
109 "gpio_51", NULL, NULL, NULL, "safe_mode"),
110 _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", NULL, "c2c_dataout7",
111 "gpio_52", NULL, NULL, NULL, "safe_mode"),
112 _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir",
113 "c2c_dataout4", "gpio_53", NULL, NULL, NULL,
114 "safe_mode"),
115 _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54",
116 "sys_ndmareq1", NULL, NULL, NULL),
117 _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
118 "sys_ndmareq2", NULL, NULL, NULL),
119 _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
120 "gpio_56", "sys_ndmareq3", NULL, NULL, NULL),
121 _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL,
122 NULL, NULL, NULL, NULL),
123 _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL,
124 NULL, NULL, NULL, NULL),
125 _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL,
126 "gpio_59", NULL, NULL, NULL, NULL),
127 _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5",
128 "gpio_60", NULL, NULL, NULL, "safe_mode"),
129 _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL,
130 "gpio_61", NULL, NULL, NULL, NULL),
131 _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2",
132 "gpio_62", NULL, NULL, NULL, "safe_mode"),
133 _OMAP4_MUXENTRY(C2C_DATA11, 100, "c2c_data11", "usbc1_icusb_txen",
134 "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
135 NULL, "safe_mode"),
136 _OMAP4_MUXENTRY(C2C_DATA12, 101, "c2c_data12", "dsi1_te0",
137 "c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL,
138 "safe_mode"),
139 _OMAP4_MUXENTRY(C2C_DATA13, 102, "c2c_data13", "dsi1_te1",
140 "c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL,
141 "safe_mode"),
142 _OMAP4_MUXENTRY(C2C_DATA14, 103, "c2c_data14", "dsi2_te0",
143 "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
144 NULL, "safe_mode"),
145 _OMAP4_MUXENTRY(C2C_DATA15, 104, "c2c_data15", "dsi2_te1",
146 "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
147 "safe_mode"),
148 _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL,
149 NULL, NULL, "safe_mode"),
150 _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL,
151 NULL, NULL, "safe_mode"),
152 _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL,
153 "gpio_65", NULL, NULL, NULL, "safe_mode"),
154 _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL,
155 "gpio_66", NULL, NULL, NULL, "safe_mode"),
156 _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL,
157 NULL, NULL, "safe_mode"),
158 _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL,
159 NULL, NULL, "safe_mode"),
160 _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL,
161 NULL, NULL, "safe_mode"),
162 _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL,
163 NULL, NULL, "safe_mode"),
164 _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL,
165 NULL, NULL, "safe_mode"),
166 _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL,
167 NULL, NULL, "safe_mode"),
168 _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL,
169 NULL, NULL, "safe_mode"),
170 _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL,
171 NULL, NULL, "safe_mode"),
172 _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL,
173 NULL, NULL, "safe_mode"),
174 _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL,
175 NULL, NULL, "safe_mode"),
176 _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL,
177 NULL, NULL, "safe_mode"),
178 _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL,
179 NULL, NULL, "safe_mode"),
180 _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL,
181 NULL, NULL, "safe_mode"),
182 _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL,
183 NULL, NULL, "safe_mode"),
184 _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81",
185 NULL, NULL, NULL, "safe_mode"),
186 _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82",
187 NULL, NULL, NULL, "safe_mode"),
188 _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL,
189 "gpio_83", NULL, NULL, NULL, "safe_mode"),
190 _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk",
191 "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk",
192 NULL, "hw_dbg20", "safe_mode"),
193 _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp",
194 "hsi1_cadata", "mcbsp4_clkr", "gpio_85",
195 "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21",
196 "safe_mode"),
197 _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir",
198 "hsi1_caflag", "mcbsp4_fsr", "gpio_86",
199 "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
200 _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt",
201 "hsi1_acready", "mcbsp4_fsx", "gpio_87",
202 "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23",
203 "safe_mode"),
204 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
205 "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
206 "usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv", "hw_dbg24",
207 "safe_mode"),
208 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
209 "hsi1_acdata", "mcbsp4_dx", "gpio_89",
210 "usbb1_ulpiphy_dat1", "usbb1_mm_txse0", "hw_dbg25",
211 "safe_mode"),
212 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
213 "hsi1_acflag", "mcbsp4_dr", "gpio_90",
214 "usbb1_ulpiphy_dat2", "usbb1_mm_txdat", "hw_dbg26",
215 "safe_mode"),
216 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
217 "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
218 "usbb1_mm_txen", "hw_dbg27", "safe_mode"),
219 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4",
220 "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92",
221 "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
222 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5",
223 "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93",
224 "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
225 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6",
226 "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94",
227 "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30",
228 "safe_mode"),
229 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7",
230 "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95",
231 "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31",
232 "safe_mode"),
233 _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL,
234 "gpio_96", NULL, NULL, NULL, "safe_mode"),
235 _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL,
236 NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
237 _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL,
238 "gpio_98", NULL, NULL, NULL, "safe_mode"),
239 _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL,
240 "gpio_99", NULL, NULL, NULL, "safe_mode"),
241 _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19",
242 "gpio_100", NULL, NULL, NULL, "safe_mode"),
243 _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx",
244 "gpio_101", NULL, NULL, NULL, "safe_mode"),
245 _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18",
246 "gpio_102", NULL, NULL, NULL, "safe_mode"),
247 _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17",
248 "gpio_103", NULL, NULL, NULL, "safe_mode"),
249 _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16",
250 "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
251 _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15",
252 "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
253 _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL,
254 "gpio_106", NULL, NULL, NULL, "safe_mode"),
255 _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL,
256 "gpio_107", NULL, NULL, NULL, "safe_mode"),
257 _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL,
258 "gpio_108", NULL, NULL, NULL, "safe_mode"),
259 _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL,
260 "gpio_109", NULL, NULL, NULL, "safe_mode"),
261 _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk",
262 "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm",
263 NULL, NULL, "safe_mode"),
264 _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi",
265 "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL,
266 NULL, "safe_mode"),
267 _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo",
268 "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL,
269 NULL, "safe_mode"),
270 _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0",
271 "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL,
272 NULL, "safe_mode"),
273 _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx",
274 "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
275 NULL, "safe_mode"),
276 _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr",
277 "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
278 NULL, "safe_mode"),
279 _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2",
280 "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL,
281 "safe_mode"),
282 _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3",
283 "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL,
284 "safe_mode"),
285 _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data",
286 "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
287 "safe_mode"),
288 _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data",
289 "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
290 "safe_mode"),
291 _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx",
292 NULL, NULL, NULL, NULL, NULL, "safe_mode"),
293 _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx",
294 NULL, NULL, NULL, NULL, NULL, "safe_mode"),
295 _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118",
296 NULL, NULL, NULL, "safe_mode"),
297 _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
298 "gpio_119", "usbb2_mm_txse0", NULL, NULL,
299 "safe_mode"),
300 _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
301 "gpio_120", "usbb2_mm_txdat", NULL, NULL,
302 "safe_mode"),
303 _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
304 NULL, "gpio_121", NULL, NULL, NULL, "safe_mode"),
305 _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
306 "abe_dmic_clk2", "gpio_122", NULL, NULL, NULL,
307 "safe_mode"),
308 _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL,
309 "gpio_123", NULL, NULL, NULL, "safe_mode"),
310 _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL,
311 "gpio_124", NULL, NULL, NULL, "safe_mode"),
312 _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL,
313 "gpio_125", NULL, NULL, NULL, "safe_mode"),
314 _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL,
315 "gpio_126", NULL, NULL, NULL, "safe_mode"),
316 _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb",
317 "gpio_127", NULL, NULL, NULL, "safe_mode"),
318 _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL,
319 NULL, NULL),
320 _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL,
321 NULL, NULL),
322 _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL,
323 "gpio_128", NULL, NULL, NULL, "safe_mode"),
324 _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL,
325 "gpio_129", NULL, NULL, NULL, "safe_mode"),
326 _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130",
327 NULL, NULL, NULL, "safe_mode"),
328 _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131",
329 NULL, NULL, NULL, "safe_mode"),
330 _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132",
331 NULL, NULL, NULL, "safe_mode"),
332 _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133",
333 NULL, NULL, NULL, "safe_mode"),
334 _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134",
335 NULL, NULL, NULL, "safe_mode"),
336 _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL,
337 "gpio_135", NULL, NULL, NULL, "safe_mode"),
338 _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL,
339 "gpio_136", NULL, NULL, NULL, "safe_mode"),
340 _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137",
341 NULL, NULL, NULL, "safe_mode"),
342 _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL,
343 "gpio_138", NULL, NULL, NULL, "safe_mode"),
344 _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts",
345 "slimbus2_clock", "gpio_139", NULL, NULL, NULL,
346 "safe_mode"),
347 _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts",
348 "slimbus2_data", "gpio_140", NULL, NULL, NULL,
349 "safe_mode"),
350 _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx",
351 NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
352 _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL,
353 "gpio_142", NULL, NULL, NULL, "safe_mode"),
354 _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx",
355 "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
356 NULL, "safe_mode"),
357 _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx",
358 "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
359 NULL, "safe_mode"),
360 _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
361 "usbc1_icusb_dp", "gpio_145", NULL, NULL, NULL,
362 "safe_mode"),
363 _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
364 "usbc1_icusb_dm", "gpio_146", NULL, NULL, NULL,
365 "safe_mode"),
366 _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
367 "usbc1_icusb_rcv", "gpio_147", NULL, NULL, NULL,
368 "safe_mode"),
369 _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
370 "usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL,
371 "safe_mode"),
372 _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
373 "gpio_149", NULL, NULL, NULL, "safe_mode"),
374 _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
375 "gpio_150", NULL, NULL, NULL, "safe_mode"),
376 _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", NULL,
377 "gpio_151", NULL, NULL, NULL, "safe_mode"),
378 _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", NULL,
379 "gpio_152", NULL, NULL, NULL, "safe_mode"),
380 _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", NULL,
381 "gpio_153", NULL, NULL, NULL, "safe_mode"),
382 _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", NULL,
383 "gpio_154", NULL, NULL, NULL, "safe_mode"),
384 _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", NULL,
385 "gpio_155", NULL, NULL, NULL, "safe_mode"),
386 _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", NULL,
387 "gpio_156", NULL, NULL, NULL, "safe_mode"),
388 _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk",
389 "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157",
390 "hsi2_cawake", NULL, NULL, "safe_mode"),
391 _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
392 "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
393 "hsi2_cadata", "dispc2_data23", NULL, "reserved"),
394 _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
395 "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
396 "hsi2_caflag", "dispc2_data22", NULL, "reserved"),
397 _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
398 "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
399 "hsi2_acready", "dispc2_data21", NULL, "reserved"),
400 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
401 "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
402 "hsi2_acwake", "dispc2_data20", NULL, "reserved"),
403 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
404 "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
405 "hsi2_acdata", "dispc2_data19", NULL, "reserved"),
406 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
407 "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
408 "hsi2_acflag", "dispc2_data18", NULL, "reserved"),
409 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
410 "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
411 "hsi2_caready", "dispc2_data15", NULL, "reserved"),
412 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
413 "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
414 "mcspi3_somi", "dispc2_data14", NULL, "reserved"),
415 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
416 "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
417 "mcspi3_cs0", "dispc2_data13", NULL, "reserved"),
418 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
419 "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
420 "mcspi3_simo", "dispc2_data12", NULL, "reserved"),
421 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
422 "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
423 "mcspi3_clk", "dispc2_data11", NULL, "reserved"),
424 _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL,
425 "gpio_169", NULL, NULL, NULL, "safe_mode"),
426 _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL,
427 NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
428 _OMAP4_MUXENTRY(UNIPRO_TX0, 171, "unipro_tx0", "kpd_col0", NULL,
429 "gpio_171", NULL, NULL, NULL, "safe_mode"),
430 _OMAP4_MUXENTRY(UNIPRO_TY0, 172, "unipro_ty0", "kpd_col1", NULL,
431 "gpio_172", NULL, NULL, NULL, "safe_mode"),
432 _OMAP4_MUXENTRY(UNIPRO_TX1, 173, "unipro_tx1", "kpd_col2", NULL,
433 "gpio_173", NULL, NULL, NULL, "safe_mode"),
434 _OMAP4_MUXENTRY(UNIPRO_TY1, 174, "unipro_ty1", "kpd_col3", NULL,
435 "gpio_174", NULL, NULL, NULL, "safe_mode"),
436 _OMAP4_MUXENTRY(UNIPRO_TX2, 0, "unipro_tx2", "kpd_col4", NULL,
437 "gpio_0", NULL, NULL, NULL, "safe_mode"),
438 _OMAP4_MUXENTRY(UNIPRO_TY2, 1, "unipro_ty2", "kpd_col5", NULL,
439 "gpio_1", NULL, NULL, NULL, "safe_mode"),
440 _OMAP4_MUXENTRY(UNIPRO_RX0, 0, "unipro_rx0", "kpd_row0", NULL,
441 "gpi_175", NULL, NULL, NULL, "safe_mode"),
442 _OMAP4_MUXENTRY(UNIPRO_RY0, 0, "unipro_ry0", "kpd_row1", NULL,
443 "gpi_176", NULL, NULL, NULL, "safe_mode"),
444 _OMAP4_MUXENTRY(UNIPRO_RX1, 0, "unipro_rx1", "kpd_row2", NULL,
445 "gpi_177", NULL, NULL, NULL, "safe_mode"),
446 _OMAP4_MUXENTRY(UNIPRO_RY1, 0, "unipro_ry1", "kpd_row3", NULL,
447 "gpi_178", NULL, NULL, NULL, "safe_mode"),
448 _OMAP4_MUXENTRY(UNIPRO_RX2, 0, "unipro_rx2", "kpd_row4", NULL,
449 "gpi_2", NULL, NULL, NULL, "safe_mode"),
450 _OMAP4_MUXENTRY(UNIPRO_RY2, 0, "unipro_ry2", "kpd_row5", NULL,
451 "gpi_3", NULL, NULL, NULL, "safe_mode"),
452 _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL,
453 NULL, NULL, NULL, NULL),
454 _OMAP4_MUXENTRY(USBA0_OTG_DP, 179, "usba0_otg_dp", "uart3_rx_irrx",
455 "uart2_rx", "gpio_179", NULL, NULL, NULL,
456 "safe_mode"),
457 _OMAP4_MUXENTRY(USBA0_OTG_DM, 180, "usba0_otg_dm", "uart3_tx_irtx",
458 "uart2_tx", "gpio_180", NULL, NULL, NULL,
459 "safe_mode"),
460 _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL,
461 "gpio_181", NULL, NULL, NULL, "safe_mode"),
462 _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL,
463 "gpio_182", NULL, NULL, NULL, "safe_mode"),
464 _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL,
465 NULL, NULL, "safe_mode"),
466 _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183",
467 NULL, NULL, NULL, "safe_mode"),
468 _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184",
469 NULL, NULL, NULL, "safe_mode"),
470 _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185",
471 NULL, NULL, NULL, "safe_mode"),
472 _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186",
473 NULL, NULL, NULL, "safe_mode"),
474 _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187",
475 NULL, NULL, NULL, "safe_mode"),
476 _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188",
477 NULL, NULL, NULL, "safe_mode"),
478 _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189",
479 NULL, NULL, NULL, "safe_mode"),
480 _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL,
481 NULL, "hw_dbg0", "safe_mode"),
482 _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL,
483 NULL, "hw_dbg1", "safe_mode"),
484 _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
485 "gpio_13", NULL, "dispc2_fid", "hw_dbg2", "reserved"),
486 _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
487 "gpio_14", NULL, "dispc2_data10", "hw_dbg3",
488 "reserved"),
489 _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
490 "gpio_15", NULL, "dispc2_data9", "hw_dbg4",
491 "reserved"),
492 _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
493 "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
494 "hw_dbg5", "reserved"),
495 _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
496 "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
497 "dispc2_data17", "hw_dbg6", "reserved"),
498 _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
499 "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
500 "dispc2_hsync", "hw_dbg7", "reserved"),
501 _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
502 "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
503 "hw_dbg8", "reserved"),
504 _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
505 "uart3_cts_rctx", "gpio_20", "rfbi_we",
506 "dispc2_vsync", "hw_dbg9", "reserved"),
507 _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
508 NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
509 "reserved"),
510 _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
511 NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
512 "hw_dbg11", "reserved"),
513 _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
514 NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
515 "hw_dbg12", "reserved"),
516 _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
517 NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
518 "hw_dbg13", "reserved"),
519 _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
520 "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
521 "hw_dbg14", "reserved"),
522 _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
523 NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
524 "hw_dbg15", "reserved"),
525 _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
526 "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
527 "hw_dbg16", "reserved"),
528 _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
529 "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
530 "hw_dbg17", "reserved"),
531 _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
532 "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
533 "hw_dbg18", "reserved"),
534 _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
535 "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
536 "hw_dbg19", "reserved"),
537 { .reg_offset = OMAP_MUX_TERMINATOR },
538};
539
540/*
541 * Balls for 44XX CBL package
542 * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
543 * 0.40mm Ball Pitch (Bottom)
544 */
545#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
546 && defined(CONFIG_OMAP_PACKAGE_CBL)
547struct omap_ball __initdata omap4_core_cbl_ball[] = {
548 _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
549 _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
550 _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
551 _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
552 _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
553 _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
554 _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
555 _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
556 _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
557 _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
558 _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
559 _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
560 _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
561 _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
562 _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
563 _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
564 _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
565 _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
566 _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
567 _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
568 _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
569 _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
570 _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
571 _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
572 _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
573 _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
574 _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
575 _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
576 _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
577 _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
578 _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
579 _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
580 _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
581 _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
582 _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
583 _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
584 _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
585 _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
586 _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
587 _OMAP4_BALLENTRY(C2C_DATA11, "d23", NULL),
588 _OMAP4_BALLENTRY(C2C_DATA12, "a24", NULL),
589 _OMAP4_BALLENTRY(C2C_DATA13, "b24", NULL),
590 _OMAP4_BALLENTRY(C2C_DATA14, "c24", NULL),
591 _OMAP4_BALLENTRY(C2C_DATA15, "d24", NULL),
592 _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
593 _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
594 _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
595 _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
596 _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
597 _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
598 _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
599 _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
600 _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
601 _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
602 _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
603 _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
604 _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
605 _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
606 _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
607 _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
608 _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
609 _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
610 _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
611 _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
612 _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
613 _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
614 _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
615 _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
616 _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
617 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
618 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
619 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
620 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
621 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
622 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
623 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
624 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
625 _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
626 _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
627 _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
628 _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
629 _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
630 _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
631 _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
632 _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
633 _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
634 _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
635 _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
636 _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
637 _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
638 _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
639 _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
640 _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
641 _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
642 _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
643 _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
644 _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
645 _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
646 _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
647 _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
648 _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
649 _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
650 _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
651 _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
652 _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
653 _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
654 _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
655 _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
656 _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
657 _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
658 _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
659 _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
660 _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
661 _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
662 _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
663 _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
664 _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
665 _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
666 _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
667 _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
668 _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
669 _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
670 _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
671 _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
672 _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
673 _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
674 _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
675 _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
676 _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
677 _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
678 _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
679 _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
680 _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
681 _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
682 _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
683 _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
684 _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
685 _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
686 _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
687 _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
688 _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
689 _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
690 _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
691 _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
692 _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
693 _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
694 _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
695 _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
696 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
697 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
698 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
699 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
700 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
701 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
702 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
703 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
704 _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
705 _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
706 _OMAP4_BALLENTRY(UNIPRO_TX0, "g26", NULL),
707 _OMAP4_BALLENTRY(UNIPRO_TY0, "g25", NULL),
708 _OMAP4_BALLENTRY(UNIPRO_TX1, "h26", NULL),
709 _OMAP4_BALLENTRY(UNIPRO_TY1, "h25", NULL),
710 _OMAP4_BALLENTRY(UNIPRO_TX2, "j27", NULL),
711 _OMAP4_BALLENTRY(UNIPRO_TY2, "h27", NULL),
712 _OMAP4_BALLENTRY(UNIPRO_RX0, "j26", NULL),
713 _OMAP4_BALLENTRY(UNIPRO_RY0, "j25", NULL),
714 _OMAP4_BALLENTRY(UNIPRO_RX1, "k26", NULL),
715 _OMAP4_BALLENTRY(UNIPRO_RY1, "k25", NULL),
716 _OMAP4_BALLENTRY(UNIPRO_RX2, "l27", NULL),
717 _OMAP4_BALLENTRY(UNIPRO_RY2, "k27", NULL),
718 _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
719 _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
720 _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
721 _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
722 _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
723 _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
724 _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
725 _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
726 _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
727 _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
728 _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
729 _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
730 _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
731 _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
732 _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
733 _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
734 _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
735 _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
736 _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
737 _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
738 _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
739 _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
740 _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
741 _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
742 _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
743 _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
744 _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
745 _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
746 _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
747 _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
748 _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
749 _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
750 _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
751 { .reg_offset = OMAP_MUX_TERMINATOR },
752};
753#else
754#define omap4_core_cbl_ball NULL
755#endif
756
757/*
758 * Superset of all mux modes for omap4
759 */
760static struct omap_mux __initdata omap4_wkup_muxmodes[] = {
761 _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL,
762 NULL, NULL, "safe_mode"),
763 _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL,
764 NULL, NULL, "safe_mode"),
765 _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2",
766 NULL, NULL, NULL, "safe_mode"),
767 _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL,
768 NULL, NULL, "safe_mode"),
769 _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4",
770 NULL, NULL, NULL, "safe_mode"),
771 _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL,
772 NULL, NULL),
773 _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL,
774 NULL, NULL),
775 _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL,
776 "c2c_wakereqin", NULL, NULL, NULL),
777 _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL,
778 "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"),
779 _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL,
780 NULL, NULL, NULL, NULL),
781 _OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req",
782 "sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL,
783 "safe_mode"),
784 _OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req",
785 "sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL,
786 NULL, "safe_mode"),
787 _OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req",
788 "sys_secure_indicator", "gpio_wk31", "c2c_wakereqout",
789 NULL, NULL, "safe_mode"),
790 _OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out",
791 NULL, "gpio_wk7", NULL, NULL, NULL, NULL),
792 _OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL,
793 "gpio_wk8", NULL, NULL, NULL, NULL),
794 _OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL,
795 NULL, NULL),
796 _OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL,
797 NULL, NULL, NULL, NULL),
798 _OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL,
799 NULL, NULL, NULL, NULL),
800 _OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL,
801 NULL, NULL, NULL),
802 _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL,
803 NULL, "gpio_wk29", NULL, NULL, NULL, NULL),
804 _OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL,
805 "gpio_wk9", "c2c_wakereqout", NULL, NULL,
806 "safe_mode"),
807 _OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL,
808 "gpio_wk10", NULL, NULL, NULL, "safe_mode"),
809 _OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL,
810 NULL, NULL, NULL),
811 _OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL,
812 NULL, "safe_mode"),
813 _OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL,
814 NULL, NULL, NULL),
815 _OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL,
816 NULL, NULL, NULL, "safe_mode"),
817 _OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL,
818 NULL, NULL),
819 _OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL,
820 NULL, NULL),
821 { .reg_offset = OMAP_MUX_TERMINATOR },
822};
823
824/*
825 * Balls for 44XX CBL package
826 * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
827 * 0.40mm Ball Pitch (Bottom)
828 */
829#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
830 && defined(CONFIG_OMAP_PACKAGE_CBL)
831struct omap_ball __initdata omap4_wkup_cbl_ball[] = {
832 _OMAP4_BALLENTRY(SIM_IO, "h4", NULL),
833 _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL),
834 _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL),
835 _OMAP4_BALLENTRY(SIM_CD, "j1", NULL),
836 _OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL),
837 _OMAP4_BALLENTRY(SR_SCL, "ag9", NULL),
838 _OMAP4_BALLENTRY(SR_SDA, "af9", NULL),
839 _OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL),
840 _OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL),
841 _OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL),
842 _OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL),
843 _OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL),
844 _OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL),
845 _OMAP4_BALLENTRY(FREF_CLK4_REQ, "ac2", NULL),
846 _OMAP4_BALLENTRY(FREF_CLK4_OUT, "ac3", NULL),
847 _OMAP4_BALLENTRY(SYS_32K, "ag7", NULL),
848 _OMAP4_BALLENTRY(SYS_NRESPWRON, "ae7", NULL),
849 _OMAP4_BALLENTRY(SYS_NRESWARM, "af7", NULL),
850 _OMAP4_BALLENTRY(SYS_PWR_REQ, "ah7", NULL),
851 _OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, "ag6", NULL),
852 _OMAP4_BALLENTRY(SYS_BOOT6, "af8", NULL),
853 _OMAP4_BALLENTRY(SYS_BOOT7, "ae8", NULL),
854 _OMAP4_BALLENTRY(JTAG_NTRST, "ah2", NULL),
855 _OMAP4_BALLENTRY(JTAG_TCK, "ag1", NULL),
856 _OMAP4_BALLENTRY(JTAG_RTCK, "ae3", NULL),
857 _OMAP4_BALLENTRY(JTAG_TMS_TMSC, "ah1", NULL),
858 _OMAP4_BALLENTRY(JTAG_TDI, "ae1", NULL),
859 _OMAP4_BALLENTRY(JTAG_TDO, "ae2", NULL),
860 { .reg_offset = OMAP_MUX_TERMINATOR },
861};
862#else
863#define omap4_wkup_cbl_ball NULL
864#endif
865
866
867int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags)
868{
869 struct omap_ball *package_balls_core, *package_balls_wkup;
870 int ret;
871
872 switch (flags & OMAP_PACKAGE_MASK) {
873 case OMAP_PACKAGE_CBL:
874 package_balls_core = omap4_core_cbl_ball;
875 package_balls_wkup = omap4_wkup_cbl_ball;
876 break;
877 default:
878 pr_err("mux: Unknown omap package, mux disabled\n");
879 return -EINVAL;
880 }
881
882 ret = omap_mux_init("core",
883 OMAP_MUX_GPIO_IN_MODE3,
884 OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE,
885 OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE,
886 omap4_core_muxmodes, NULL, board_subset,
887 package_balls_core);
888 if (ret)
889 return ret;
890
891 ret = omap_mux_init("wkup",
892 OMAP_MUX_GPIO_IN_MODE3,
893 OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE,
894 OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE,
895 omap4_wkup_muxmodes, NULL, board_subset,
896 package_balls_wkup);
897
898 return ret;
899}
900
diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h
new file mode 100644
index 000000000000..ea8b235d1487
--- /dev/null
+++ b/arch/arm/mach-omap2/mux44xx.h
@@ -0,0 +1,277 @@
1/*
2 * OMAP44xx MUX registers and bitfields
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 *
8 * This file is automatically generated from the OMAP hardware databases.
9 * We respectfully ask that any modifications to this file be coordinated
10 * with the public linux-omap@vger.kernel.org mailing list and the
11 * authors above to ensure that the autogeneration scripts are kept
12 * up-to-date with the file contents.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
20#define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
21
22#define OMAP4_MUX(M0, mux_value) \
23{ \
24 .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
25 .value = (mux_value), \
26}
27
28/* ctrl_module_pad_core base address */
29#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE 0x4a100000
30
31/* ctrl_module_pad_core registers offset */
32#define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET 0x0040
33#define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET 0x0042
34#define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET 0x0044
35#define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET 0x0046
36#define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET 0x0048
37#define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET 0x004a
38#define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET 0x004c
39#define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET 0x004e
40#define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET 0x0050
41#define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET 0x0052
42#define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET 0x0054
43#define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET 0x0056
44#define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET 0x0058
45#define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET 0x005a
46#define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET 0x005c
47#define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET 0x005e
48#define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET 0x0060
49#define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET 0x0062
50#define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET 0x0064
51#define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET 0x0066
52#define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET 0x0068
53#define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET 0x006a
54#define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET 0x006c
55#define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET 0x006e
56#define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET 0x0070
57#define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET 0x0072
58#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET 0x0074
59#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET 0x0076
60#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET 0x0078
61#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET 0x007a
62#define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET 0x007c
63#define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET 0x007e
64#define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET 0x0080
65#define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET 0x0082
66#define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET 0x0084
67#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET 0x0086
68#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET 0x0088
69#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET 0x008a
70#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET 0x008c
71#define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET 0x008e
72#define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET 0x0090
73#define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET 0x0092
74#define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET 0x0094
75#define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET 0x0096
76#define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET 0x0098
77#define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET 0x009a
78#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET 0x009c
79#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET 0x009e
80#define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET 0x00a0
81#define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET 0x00a2
82#define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET 0x00a4
83#define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET 0x00a6
84#define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET 0x00a8
85#define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET 0x00aa
86#define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET 0x00ac
87#define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET 0x00ae
88#define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET 0x00b0
89#define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET 0x00b2
90#define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET 0x00b4
91#define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET 0x00b6
92#define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET 0x00b8
93#define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET 0x00ba
94#define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET 0x00bc
95#define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET 0x00be
96#define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET 0x00c0
97#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET 0x00c2
98#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET 0x00c4
99#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET 0x00c6
100#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET 0x00c8
101#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET 0x00ca
102#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET 0x00cc
103#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET 0x00ce
104#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET 0x00d0
105#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET 0x00d2
106#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET 0x00d4
107#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET 0x00d6
108#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET 0x00d8
109#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET 0x00da
110#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET 0x00dc
111#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET 0x00de
112#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET 0x00e0
113#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET 0x00e2
114#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET 0x00e4
115#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET 0x00e6
116#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET 0x00e8
117#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET 0x00ea
118#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET 0x00ec
119#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET 0x00ee
120#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET 0x00f0
121#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET 0x00f2
122#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET 0x00f4
123#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET 0x00f6
124#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET 0x00f8
125#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET 0x00fa
126#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET 0x00fc
127#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET 0x00fe
128#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET 0x0100
129#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET 0x0102
130#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET 0x0104
131#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET 0x0106
132#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET 0x0108
133#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET 0x010a
134#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET 0x010c
135#define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET 0x010e
136#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET 0x0110
137#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET 0x0112
138#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET 0x0114
139#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET 0x0116
140#define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET 0x0118
141#define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET 0x011a
142#define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET 0x011c
143#define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET 0x011e
144#define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET 0x0120
145#define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET 0x0122
146#define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET 0x0124
147#define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET 0x0126
148#define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET 0x0128
149#define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET 0x012a
150#define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET 0x012c
151#define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET 0x012e
152#define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET 0x0130
153#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET 0x0132
154#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET 0x0134
155#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET 0x0136
156#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET 0x0138
157#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET 0x013a
158#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET 0x013c
159#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET 0x013e
160#define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET 0x0140
161#define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET 0x0142
162#define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET 0x0144
163#define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET 0x0146
164#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET 0x0148
165#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET 0x014a
166#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET 0x014c
167#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET 0x014e
168#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET 0x0150
169#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET 0x0152
170#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET 0x0154
171#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET 0x0156
172#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET 0x0158
173#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET 0x015a
174#define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET 0x015c
175#define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET 0x015e
176#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET 0x0160
177#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET 0x0162
178#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET 0x0164
179#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET 0x0166
180#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET 0x0168
181#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET 0x016a
182#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET 0x016c
183#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET 0x016e
184#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET 0x0170
185#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET 0x0172
186#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET 0x0174
187#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET 0x0176
188#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET 0x0178
189#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET 0x017a
190#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET 0x017c
191#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET 0x017e
192#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET 0x0180
193#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET 0x0182
194#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET 0x0184
195#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET 0x0186
196#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET 0x0188
197#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET 0x018a
198#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET 0x018c
199#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET 0x018e
200#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET 0x0190
201#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET 0x0192
202#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET 0x0194
203#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET 0x0196
204#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET 0x0198
205#define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET 0x019a
206#define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET 0x019c
207#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET 0x019e
208#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET 0x01a0
209#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET 0x01a2
210#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET 0x01a4
211#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET 0x01a6
212#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET 0x01a8
213#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET 0x01aa
214#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET 0x01ac
215#define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET 0x01ae
216#define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET 0x01b0
217#define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET 0x01b2
218#define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET 0x01b4
219#define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET 0x01b6
220#define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET 0x01b8
221#define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET 0x01ba
222#define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET 0x01bc
223#define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET 0x01be
224#define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET 0x01c0
225#define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET 0x01c2
226#define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET 0x01c4
227#define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET 0x01c6
228#define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET 0x01c8
229#define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET 0x01ca
230#define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET 0x01cc
231#define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET 0x01ce
232#define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET 0x01d0
233#define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET 0x01d2
234#define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET 0x01d4
235
236#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE \
237 (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET \
238 - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2)
239
240/* ctrl_module_pad_wkup base address */
241#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE 0x4a31e000
242
243/* ctrl_module_pad_wkup registers offset */
244#define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET 0x0040
245#define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET 0x0042
246#define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET 0x0044
247#define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET 0x0046
248#define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET 0x0048
249#define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET 0x004a
250#define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET 0x004c
251#define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET 0x004e
252#define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET 0x0050
253#define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET 0x0052
254#define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET 0x0054
255#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET 0x0056
256#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET 0x0058
257#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET 0x005a
258#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET 0x005c
259#define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET 0x005e
260#define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET 0x0060
261#define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET 0x0062
262#define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET 0x0064
263#define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET 0x0066
264#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET 0x0068
265#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET 0x006a
266#define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET 0x006c
267#define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET 0x006e
268#define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET 0x0070
269#define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET 0x0072
270#define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET 0x0074
271#define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET 0x0076
272
273#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE \
274 (OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET \
275 - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2)
276
277#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 01:53:41 -0500