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-rw-r--r--drivers/scsi/mpt2sas/mpi/mpi2.h5
-rw-r--r--drivers/scsi/mpt2sas/mpi/mpi2_cnfg.h266
-rw-r--r--drivers/scsi/mpt2sas/mpi/mpi2_ioc.h18
-rw-r--r--drivers/scsi/mpt2sas/mpi/mpi2_raid.h14
-rw-r--r--drivers/scsi/mpt2sas/mpi/mpi2_tool.h16
5 files changed, 305 insertions, 14 deletions
diff --git a/drivers/scsi/mpt2sas/mpi/mpi2.h b/drivers/scsi/mpt2sas/mpi/mpi2.h
index f9f6c0839276..914168105297 100644
--- a/drivers/scsi/mpt2sas/mpi/mpi2.h
+++ b/drivers/scsi/mpt2sas/mpi/mpi2.h
@@ -8,7 +8,7 @@
8 * scatter/gather formats. 8 * scatter/gather formats.
9 * Creation Date: June 21, 2006 9 * Creation Date: June 21, 2006
10 * 10 *
11 * mpi2.h Version: 02.00.12 11 * mpi2.h Version: 02.00.13
12 * 12 *
13 * Version History 13 * Version History
14 * --------------- 14 * ---------------
@@ -52,6 +52,7 @@
52 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 52 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
53 * bytes reserved. 53 * bytes reserved.
54 * Added RAID Accelerator functionality. 54 * Added RAID Accelerator functionality.
55 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
55 * -------------------------------------------------------------------------- 56 * --------------------------------------------------------------------------
56 */ 57 */
57 58
@@ -77,7 +78,7 @@
77#define MPI2_VERSION_02_00 (0x0200) 78#define MPI2_VERSION_02_00 (0x0200)
78 79
79/* versioning for this MPI header set */ 80/* versioning for this MPI header set */
80#define MPI2_HEADER_VERSION_UNIT (0x0C) 81#define MPI2_HEADER_VERSION_UNIT (0x0D)
81#define MPI2_HEADER_VERSION_DEV (0x00) 82#define MPI2_HEADER_VERSION_DEV (0x00)
82#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 83#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
83#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 84#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
diff --git a/drivers/scsi/mpt2sas/mpi/mpi2_cnfg.h b/drivers/scsi/mpt2sas/mpi/mpi2_cnfg.h
index 5af66dbe3239..1611c57a6fdf 100644
--- a/drivers/scsi/mpt2sas/mpi/mpi2_cnfg.h
+++ b/drivers/scsi/mpt2sas/mpi/mpi2_cnfg.h
@@ -6,7 +6,7 @@
6 * Title: MPI Configuration messages and pages 6 * Title: MPI Configuration messages and pages
7 * Creation Date: November 10, 2006 7 * Creation Date: November 10, 2006
8 * 8 *
9 * mpi2_cnfg.h Version: 02.00.11 9 * mpi2_cnfg.h Version: 02.00.12
10 * 10 *
11 * Version History 11 * Version History
12 * --------------- 12 * ---------------
@@ -100,6 +100,13 @@
100 * Added expander reduced functionality data to SAS 100 * Added expander reduced functionality data to SAS
101 * Expander Page 0. 101 * Expander Page 0.
102 * Added SAS PHY Page 2 and SAS PHY Page 3. 102 * Added SAS PHY Page 2 and SAS PHY Page 3.
103 * 07-30-09 02.00.12 Added IO Unit Page 7.
104 * Added new device ids.
105 * Added SAS IO Unit Page 5.
106 * Added partial and slumber power management capable flags
107 * to SAS Device Page 0 Flags field.
108 * Added PhyInfo defines for power condition.
109 * Added Ethernet configuration pages.
103 * -------------------------------------------------------------------------- 110 * --------------------------------------------------------------------------
104 */ 111 */
105 112
@@ -182,6 +189,7 @@ typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
182#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 189#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
183#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 190#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
184#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 191#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
192#define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
185 193
186 194
187/***************************************************************************** 195/*****************************************************************************
@@ -268,6 +276,14 @@ typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
268#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 276#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
269 277
270 278
279/* Ethernet PageAddress format */
280#define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
281#define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
282
283#define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
284
285
286
271/**************************************************************************** 287/****************************************************************************
272* Configuration messages 288* Configuration messages
273****************************************************************************/ 289****************************************************************************/
@@ -348,6 +364,7 @@ typedef struct _MPI2_CONFIG_REPLY
348#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 364#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
349#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 365#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
350#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 366#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
367
351#define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 368#define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
352#define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 369#define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
353#define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 370#define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
@@ -795,6 +812,56 @@ typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
795#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 812#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
796 813
797 814
815/* IO Unit Page 7 */
816
817typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
818 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
819 U16 Reserved1; /* 0x04 */
820 U8 PCIeWidth; /* 0x06 */
821 U8 PCIeSpeed; /* 0x07 */
822 U32 ProcessorState; /* 0x08 */
823 U32 Reserved2; /* 0x0C */
824 U16 IOCTemperature; /* 0x10 */
825 U8 IOCTemperatureUnits; /* 0x12 */
826 U8 IOCSpeed; /* 0x13 */
827 U32 Reserved3; /* 0x14 */
828} MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
829 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
830
831#define MPI2_IOUNITPAGE7_PAGEVERSION (0x00)
832
833/* defines for IO Unit Page 7 PCIeWidth field */
834#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
835#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
836#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
837#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
838
839/* defines for IO Unit Page 7 PCIeSpeed field */
840#define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
841#define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
842#define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
843
844/* defines for IO Unit Page 7 ProcessorState field */
845#define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
846#define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
847
848#define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
849#define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
850#define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
851
852/* defines for IO Unit Page 7 IOCTemperatureUnits field */
853#define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
854#define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
855#define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
856
857/* defines for IO Unit Page 7 IOCSpeed field */
858#define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
859#define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
860#define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
861#define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
862
863
864
798/**************************************************************************** 865/****************************************************************************
799* IOC Config Pages 866* IOC Config Pages
800****************************************************************************/ 867****************************************************************************/
@@ -1478,6 +1545,12 @@ typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1478 1545
1479/* values for PhyInfo fields */ 1546/* values for PhyInfo fields */
1480#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1547#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1548
1549#define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1550#define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1551#define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1552#define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1553
1481#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 1554#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1482#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 1555#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1483#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 1556#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
@@ -1690,11 +1763,11 @@ typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1690/* values for SAS IO Unit Page 1 PortFlags */ 1763/* values for SAS IO Unit Page 1 PortFlags */
1691#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 1764#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1692 1765
1693/* values for SAS IO Unit Page 2 PhyFlags */ 1766/* values for SAS IO Unit Page 1 PhyFlags */
1694#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 1767#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
1695#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1768#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1696 1769
1697/* values for SAS IO Unit Page 0 MaxMinLinkRate */ 1770/* values for SAS IO Unit Page 1 MaxMinLinkRate */
1698#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 1771#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
1699#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 1772#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
1700#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 1773#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
@@ -1753,6 +1826,74 @@ typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
1753#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 1826#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
1754 1827
1755 1828
1829/* SAS IO Unit Page 5 */
1830
1831typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
1832 U8 ControlFlags; /* 0x00 */
1833 U8 Reserved1; /* 0x01 */
1834 U16 InactivityTimerExponent; /* 0x02 */
1835 U8 SATAPartialTimeout; /* 0x04 */
1836 U8 Reserved2; /* 0x05 */
1837 U8 SATASlumberTimeout; /* 0x06 */
1838 U8 Reserved3; /* 0x07 */
1839 U8 SASPartialTimeout; /* 0x08 */
1840 U8 Reserved4; /* 0x09 */
1841 U8 SASSlumberTimeout; /* 0x0A */
1842 U8 Reserved5; /* 0x0B */
1843} MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1844 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1845 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
1846
1847/* defines for ControlFlags field */
1848#define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
1849#define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
1850#define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
1851#define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
1852
1853/* defines for InactivityTimerExponent field */
1854#define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
1855#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
1856#define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
1857#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
1858#define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
1859#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
1860#define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
1861#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
1862
1863#define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
1864#define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
1865#define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
1866#define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
1867#define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
1868#define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
1869#define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
1870#define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
1871
1872/*
1873 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1874 * one and check Header.ExtPageLength or NumPhys at runtime.
1875 */
1876#ifndef MPI2_SAS_IOUNIT5_PHY_MAX
1877#define MPI2_SAS_IOUNIT5_PHY_MAX (1)
1878#endif
1879
1880typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
1881 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1882 U8 NumPhys; /* 0x08 */
1883 U8 Reserved1; /* 0x09 */
1884 U16 Reserved2; /* 0x0A */
1885 U32 Reserved3; /* 0x0C */
1886 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings
1887 [MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
1888} MPI2_CONFIG_PAGE_SASIOUNIT_5,
1889 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
1890 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
1891
1892#define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x00)
1893
1894
1895
1896
1756/**************************************************************************** 1897/****************************************************************************
1757* SAS Expander Config Pages 1898* SAS Expander Config Pages
1758****************************************************************************/ 1899****************************************************************************/
@@ -1935,6 +2076,8 @@ typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
1935/* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2076/* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
1936 2077
1937/* values for SAS Device Page 0 Flags field */ 2078/* values for SAS Device Page 0 Flags field */
2079#define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2080#define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
1938#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2081#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
1939#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2082#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
1940#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2083#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
@@ -2351,5 +2494,122 @@ typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2351#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 2494#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
2352 2495
2353 2496
2497/****************************************************************************
2498* Ethernet Config Pages
2499****************************************************************************/
2500
2501/* Ethernet Page 0 */
2502
2503/* IP address (union of IPv4 and IPv6) */
2504typedef union _MPI2_ETHERNET_IP_ADDR {
2505 U32 IPv4Addr;
2506 U32 IPv6Addr[4];
2507} MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
2508 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
2509
2510#define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
2511
2512typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
2513 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2514 U8 NumInterfaces; /* 0x08 */
2515 U8 Reserved0; /* 0x09 */
2516 U16 Reserved1; /* 0x0A */
2517 U32 Status; /* 0x0C */
2518 U8 MediaState; /* 0x10 */
2519 U8 Reserved2; /* 0x11 */
2520 U16 Reserved3; /* 0x12 */
2521 U8 MacAddress[6]; /* 0x14 */
2522 U8 Reserved4; /* 0x1A */
2523 U8 Reserved5; /* 0x1B */
2524 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
2525 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
2526 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
2527 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
2528 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
2529 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
2530 U8 HostName
2531 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2532} MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
2533 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
2534
2535#define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
2536
2537/* values for Ethernet Page 0 Status field */
2538#define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
2539#define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
2540#define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
2541#define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
2542#define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
2543#define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
2544#define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
2545#define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
2546#define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
2547#define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
2548#define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
2549#define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
2550
2551/* values for Ethernet Page 0 MediaState field */
2552#define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
2553#define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
2554#define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
2555
2556#define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
2557#define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
2558#define MPI2_ETHPG0_MS_10MBIT (0x01)
2559#define MPI2_ETHPG0_MS_100MBIT (0x02)
2560#define MPI2_ETHPG0_MS_1GBIT (0x03)
2561
2562
2563/* Ethernet Page 1 */
2564
2565typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
2566 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2567 U32 Reserved0; /* 0x08 */
2568 U32 Flags; /* 0x0C */
2569 U8 MediaState; /* 0x10 */
2570 U8 Reserved1; /* 0x11 */
2571 U16 Reserved2; /* 0x12 */
2572 U8 MacAddress[6]; /* 0x14 */
2573 U8 Reserved3; /* 0x1A */
2574 U8 Reserved4; /* 0x1B */
2575 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
2576 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
2577 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
2578 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
2579 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
2580 U32 Reserved5; /* 0x6C */
2581 U32 Reserved6; /* 0x70 */
2582 U32 Reserved7; /* 0x74 */
2583 U32 Reserved8; /* 0x78 */
2584 U8 HostName
2585 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2586} MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
2587 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
2588
2589#define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
2590
2591/* values for Ethernet Page 1 Flags field */
2592#define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
2593#define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
2594#define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
2595#define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
2596#define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
2597#define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
2598#define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
2599#define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
2600#define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
2601
2602/* values for Ethernet Page 1 MediaState field */
2603#define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
2604#define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
2605#define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
2606
2607#define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
2608#define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
2609#define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
2610#define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
2611#define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
2612
2613
2354#endif 2614#endif
2355 2615
diff --git a/drivers/scsi/mpt2sas/mpi/mpi2_ioc.h b/drivers/scsi/mpt2sas/mpi/mpi2_ioc.h
index c294128bdeb4..ea51ce868690 100644
--- a/drivers/scsi/mpt2sas/mpi/mpi2_ioc.h
+++ b/drivers/scsi/mpt2sas/mpi/mpi2_ioc.h
@@ -6,7 +6,7 @@
6 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 6 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
7 * Creation Date: October 11, 2006 7 * Creation Date: October 11, 2006
8 * 8 *
9 * mpi2_ioc.h Version: 02.00.11 9 * mpi2_ioc.h Version: 02.00.12
10 * 10 *
11 * Version History 11 * Version History
12 * --------------- 12 * ---------------
@@ -84,6 +84,9 @@
84 * Added two new reason codes for SAS Device Status Change 84 * Added two new reason codes for SAS Device Status Change
85 * Event. 85 * Event.
86 * Added new event: SAS PHY Counter. 86 * Added new event: SAS PHY Counter.
87 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
88 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
89 * Added new product id family for 2208.
87 * -------------------------------------------------------------------------- 90 * --------------------------------------------------------------------------
88 */ 91 */
89 92
@@ -274,6 +277,7 @@ typedef struct _MPI2_IOC_FACTS_REPLY
274#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 277#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
275#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) 278#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
276#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) 279#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
280#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
277#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 281#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
278#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 282#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
279#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) 283#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
@@ -448,6 +452,7 @@ typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
448#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) 452#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
449#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) 453#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
450#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022) 454#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
455#define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
451 456
452 457
453/* Log Entry Added Event data */ 458/* Log Entry Added Event data */
@@ -469,6 +474,16 @@ typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
469 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 474 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
470 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t; 475 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
471 476
477/* GPIO Interrupt Event data */
478
479typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
480 U8 GPIONum; /* 0x00 */
481 U8 Reserved1; /* 0x01 */
482 U16 Reserved2; /* 0x02 */
483} MPI2_EVENT_DATA_GPIO_INTERRUPT,
484 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
485 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
486
472/* Hard Reset Received Event data */ 487/* Hard Reset Received Event data */
473 488
474typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED 489typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
@@ -1117,6 +1132,7 @@ typedef struct _MPI2_FW_IMAGE_HEADER
1117#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF) 1132#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1118/* SAS */ 1133/* SAS */
1119#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0010) 1134#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0010)
1135#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0011)
1120 1136
1121/* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ 1137/* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1122 1138
diff --git a/drivers/scsi/mpt2sas/mpi/mpi2_raid.h b/drivers/scsi/mpt2sas/mpi/mpi2_raid.h
index 7134816d9046..5160c33d2a00 100644
--- a/drivers/scsi/mpt2sas/mpi/mpi2_raid.h
+++ b/drivers/scsi/mpt2sas/mpi/mpi2_raid.h
@@ -6,7 +6,7 @@
6 * Title: MPI Integrated RAID messages and structures 6 * Title: MPI Integrated RAID messages and structures
7 * Creation Date: April 26, 2007 7 * Creation Date: April 26, 2007
8 * 8 *
9 * mpi2_raid.h Version: 02.00.03 9 * mpi2_raid.h Version: 02.00.04
10 * 10 *
11 * Version History 11 * Version History
12 * --------------- 12 * ---------------
@@ -20,6 +20,8 @@
20 * 05-21-08 02.00.03 Added MPI2_RAID_VOL_CREATION_NUM_PHYSDISKS so that 20 * 05-21-08 02.00.03 Added MPI2_RAID_VOL_CREATION_NUM_PHYSDISKS so that
21 * the PhysDisk array in MPI2_RAID_VOLUME_CREATION_STRUCT 21 * the PhysDisk array in MPI2_RAID_VOLUME_CREATION_STRUCT
22 * can be sized by the build environment. 22 * can be sized by the build environment.
23 * 07-30-09 02.00.04 Added proper define for the Use Default Settings bit of
24 * VolumeCreationFlags and marked the old one as obsolete.
23 * -------------------------------------------------------------------------- 25 * --------------------------------------------------------------------------
24 */ 26 */
25 27
@@ -217,10 +219,14 @@ typedef struct _MPI2_RAID_VOLUME_CREATION_STRUCT
217/* use MPI2_RAID_VOL_TYPE_ defines from mpi2_cnfg.h for VolumeType */ 219/* use MPI2_RAID_VOL_TYPE_ defines from mpi2_cnfg.h for VolumeType */
218 220
219/* defines for the VolumeCreationFlags field */ 221/* defines for the VolumeCreationFlags field */
222#define MPI2_RAID_VOL_CREATION_DEFAULT_SETTINGS (0x80000000)
223#define MPI2_RAID_VOL_CREATION_BACKGROUND_INIT (0x00000004)
224#define MPI2_RAID_VOL_CREATION_LOW_LEVEL_INIT (0x00000002)
225#define MPI2_RAID_VOL_CREATION_MIGRATE_DATA (0x00000001)
226/* The following is an obsolete define.
227 * It must be shifted left 24 bits in order to set the proper bit.
228 */
220#define MPI2_RAID_VOL_CREATION_USE_DEFAULT_SETTINGS (0x80) 229#define MPI2_RAID_VOL_CREATION_USE_DEFAULT_SETTINGS (0x80)
221#define MPI2_RAID_VOL_CREATION_BACKGROUND_INIT (0x04)
222#define MPI2_RAID_VOL_CREATION_LOW_LEVEL_INIT (0x02)
223#define MPI2_RAID_VOL_CREATION_MIGRATE_DATA (0x01)
224 230
225 231
226/* RAID Online Capacity Expansion Structure */ 232/* RAID Online Capacity Expansion Structure */
diff --git a/drivers/scsi/mpt2sas/mpi/mpi2_tool.h b/drivers/scsi/mpt2sas/mpi/mpi2_tool.h
index 007e950f7bfa..73fcdbf92632 100644
--- a/drivers/scsi/mpt2sas/mpi/mpi2_tool.h
+++ b/drivers/scsi/mpt2sas/mpi/mpi2_tool.h
@@ -6,7 +6,7 @@
6 * Title: MPI diagnostic tool structures and definitions 6 * Title: MPI diagnostic tool structures and definitions
7 * Creation Date: March 26, 2007 7 * Creation Date: March 26, 2007
8 * 8 *
9 * mpi2_tool.h Version: 02.00.03 9 * mpi2_tool.h Version: 02.00.04
10 * 10 *
11 * Version History 11 * Version History
12 * --------------- 12 * ---------------
@@ -18,6 +18,10 @@
18 * structures and defines. 18 * structures and defines.
19 * 02-29-08 02.00.02 Modified various names to make them 32-character unique. 19 * 02-29-08 02.00.02 Modified various names to make them 32-character unique.
20 * 05-06-09 02.00.03 Added ISTWI Read Write Tool and Diagnostic CLI Tool. 20 * 05-06-09 02.00.03 Added ISTWI Read Write Tool and Diagnostic CLI Tool.
21 * 07-30-09 02.00.04 Added ExtendedType field to DiagnosticBufferPost request
22 * and reply messages.
23 * Added MPI2_DIAG_BUF_TYPE_EXTENDED.
24 * Incremented MPI2_DIAG_BUF_TYPE_COUNT.
21 * -------------------------------------------------------------------------- 25 * --------------------------------------------------------------------------
22 */ 26 */
23 27
@@ -282,7 +286,7 @@ typedef struct _MPI2_TOOLBOX_DIAGNOSTIC_CLI_REPLY {
282 286
283typedef struct _MPI2_DIAG_BUFFER_POST_REQUEST 287typedef struct _MPI2_DIAG_BUFFER_POST_REQUEST
284{ 288{
285 U8 Reserved1; /* 0x00 */ 289 U8 ExtendedType; /* 0x00 */
286 U8 BufferType; /* 0x01 */ 290 U8 BufferType; /* 0x01 */
287 U8 ChainOffset; /* 0x02 */ 291 U8 ChainOffset; /* 0x02 */
288 U8 Function; /* 0x03 */ 292 U8 Function; /* 0x03 */
@@ -301,11 +305,15 @@ typedef struct _MPI2_DIAG_BUFFER_POST_REQUEST
301} MPI2_DIAG_BUFFER_POST_REQUEST, MPI2_POINTER PTR_MPI2_DIAG_BUFFER_POST_REQUEST, 305} MPI2_DIAG_BUFFER_POST_REQUEST, MPI2_POINTER PTR_MPI2_DIAG_BUFFER_POST_REQUEST,
302 Mpi2DiagBufferPostRequest_t, MPI2_POINTER pMpi2DiagBufferPostRequest_t; 306 Mpi2DiagBufferPostRequest_t, MPI2_POINTER pMpi2DiagBufferPostRequest_t;
303 307
308/* values for the ExtendedType field */
309#define MPI2_DIAG_EXTENDED_TYPE_UTILIZATION (0x02)
310
304/* values for the BufferType field */ 311/* values for the BufferType field */
305#define MPI2_DIAG_BUF_TYPE_TRACE (0x00) 312#define MPI2_DIAG_BUF_TYPE_TRACE (0x00)
306#define MPI2_DIAG_BUF_TYPE_SNAPSHOT (0x01) 313#define MPI2_DIAG_BUF_TYPE_SNAPSHOT (0x01)
314#define MPI2_DIAG_BUF_TYPE_EXTENDED (0x02)
307/* count of the number of buffer types */ 315/* count of the number of buffer types */
308#define MPI2_DIAG_BUF_TYPE_COUNT (0x02) 316#define MPI2_DIAG_BUF_TYPE_COUNT (0x03)
309 317
310 318
311/**************************************************************************** 319/****************************************************************************
@@ -314,7 +322,7 @@ typedef struct _MPI2_DIAG_BUFFER_POST_REQUEST
314 322
315typedef struct _MPI2_DIAG_BUFFER_POST_REPLY 323typedef struct _MPI2_DIAG_BUFFER_POST_REPLY
316{ 324{
317 U8 Reserved1; /* 0x00 */ 325 U8 ExtendedType; /* 0x00 */
318 U8 BufferType; /* 0x01 */ 326 U8 BufferType; /* 0x01 */
319 U8 MsgLength; /* 0x02 */ 327 U8 MsgLength; /* 0x02 */
320 U8 Function; /* 0x03 */ 328 U8 Function; /* 0x03 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 17:26:36 -0400