aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/dm.c733
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/dm.h164
2 files changed, 897 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/dm.c b/drivers/net/wireless/rtlwifi/rtl8192se/dm.c
new file mode 100644
index 000000000000..da86db86fa4a
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/dm.c
@@ -0,0 +1,733 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../base.h"
32#include "reg.h"
33#include "def.h"
34#include "phy.h"
35#include "dm.h"
36#include "fw.h"
37
38struct dig_t digtable;
39static const u32 edca_setting_dl[PEER_MAX] = {
40 0xa44f, /* 0 UNKNOWN */
41 0x5ea44f, /* 1 REALTEK_90 */
42 0x5ea44f, /* 2 REALTEK_92SE */
43 0xa630, /* 3 BROAD */
44 0xa44f, /* 4 RAL */
45 0xa630, /* 5 ATH */
46 0xa630, /* 6 CISCO */
47 0xa42b, /* 7 MARV */
48};
49
50static const u32 edca_setting_dl_gmode[PEER_MAX] = {
51 0x4322, /* 0 UNKNOWN */
52 0xa44f, /* 1 REALTEK_90 */
53 0x5ea44f, /* 2 REALTEK_92SE */
54 0xa42b, /* 3 BROAD */
55 0x5e4322, /* 4 RAL */
56 0x4322, /* 5 ATH */
57 0xa430, /* 6 CISCO */
58 0x5ea44f, /* 7 MARV */
59};
60
61static const u32 edca_setting_ul[PEER_MAX] = {
62 0x5e4322, /* 0 UNKNOWN */
63 0xa44f, /* 1 REALTEK_90 */
64 0x5ea44f, /* 2 REALTEK_92SE */
65 0x5ea322, /* 3 BROAD */
66 0x5ea422, /* 4 RAL */
67 0x5ea322, /* 5 ATH */
68 0x3ea44f, /* 6 CISCO */
69 0x5ea44f, /* 7 MARV */
70};
71
72static void _rtl92s_dm_check_edca_turbo(struct ieee80211_hw *hw)
73{
74 struct rtl_priv *rtlpriv = rtl_priv(hw);
75 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
76
77 static u64 last_txok_cnt;
78 static u64 last_rxok_cnt;
79 u64 cur_txok_cnt = 0;
80 u64 cur_rxok_cnt = 0;
81
82 u32 edca_be_ul = edca_setting_ul[mac->vendor];
83 u32 edca_be_dl = edca_setting_dl[mac->vendor];
84 u32 edca_gmode = edca_setting_dl_gmode[mac->vendor];
85
86 if (mac->link_state != MAC80211_LINKED) {
87 rtlpriv->dm.current_turbo_edca = false;
88 goto dm_checkedcaturbo_exit;
89 }
90
91 if ((!rtlpriv->dm.is_any_nonbepkts) &&
92 (!rtlpriv->dm.disable_framebursting)) {
93 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
94 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
95
96 if (rtlpriv->phy.rf_type == RF_1T2R) {
97 if (cur_txok_cnt > 4 * cur_rxok_cnt) {
98 /* Uplink TP is present. */
99 if (rtlpriv->dm.is_cur_rdlstate ||
100 !rtlpriv->dm.current_turbo_edca) {
101 rtl_write_dword(rtlpriv, EDCAPARA_BE,
102 edca_be_ul);
103 rtlpriv->dm.is_cur_rdlstate = false;
104 }
105 } else {/* Balance TP is present. */
106 if (!rtlpriv->dm.is_cur_rdlstate ||
107 !rtlpriv->dm.current_turbo_edca) {
108 if (mac->mode == WIRELESS_MODE_G ||
109 mac->mode == WIRELESS_MODE_B)
110 rtl_write_dword(rtlpriv,
111 EDCAPARA_BE,
112 edca_gmode);
113 else
114 rtl_write_dword(rtlpriv,
115 EDCAPARA_BE,
116 edca_be_dl);
117 rtlpriv->dm.is_cur_rdlstate = true;
118 }
119 }
120 rtlpriv->dm.current_turbo_edca = true;
121 } else {
122 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
123 if (!rtlpriv->dm.is_cur_rdlstate ||
124 !rtlpriv->dm.current_turbo_edca) {
125 if (mac->mode == WIRELESS_MODE_G ||
126 mac->mode == WIRELESS_MODE_B)
127 rtl_write_dword(rtlpriv,
128 EDCAPARA_BE,
129 edca_gmode);
130 else
131 rtl_write_dword(rtlpriv,
132 EDCAPARA_BE,
133 edca_be_dl);
134 rtlpriv->dm.is_cur_rdlstate = true;
135 }
136 } else {
137 if (rtlpriv->dm.is_cur_rdlstate ||
138 !rtlpriv->dm.current_turbo_edca) {
139 rtl_write_dword(rtlpriv, EDCAPARA_BE,
140 edca_be_ul);
141 rtlpriv->dm.is_cur_rdlstate = false;
142 }
143 }
144 rtlpriv->dm.current_turbo_edca = true;
145 }
146 } else {
147 if (rtlpriv->dm.current_turbo_edca) {
148 u8 tmp = AC0_BE;
149 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
150 (u8 *)(&tmp));
151 rtlpriv->dm.current_turbo_edca = false;
152 }
153 }
154
155dm_checkedcaturbo_exit:
156 rtlpriv->dm.is_any_nonbepkts = false;
157 last_txok_cnt = rtlpriv->stats.txbytesunicast;
158 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
159}
160
161static void _rtl92s_dm_txpowertracking_callback_thermalmeter(
162 struct ieee80211_hw *hw)
163{
164 struct rtl_priv *rtlpriv = rtl_priv(hw);
165 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
166 u8 thermalvalue = 0;
167
168 rtlpriv->dm.txpower_trackinginit = true;
169
170 thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
171
172 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
173 ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
174 "eeprom_thermalmeter 0x%x\n", thermalvalue,
175 rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter));
176
177 if (thermalvalue) {
178 rtlpriv->dm.thermalvalue = thermalvalue;
179 rtl92s_phy_set_fw_cmd(hw, FW_CMD_TXPWR_TRACK_THERMAL);
180 }
181
182 rtlpriv->dm.txpowercount = 0;
183}
184
185static void _rtl92s_dm_check_txpowertracking_thermalmeter(
186 struct ieee80211_hw *hw)
187{
188 struct rtl_priv *rtlpriv = rtl_priv(hw);
189 struct rtl_phy *rtlphy = &(rtlpriv->phy);
190 static u8 tm_trigger;
191 u8 tx_power_checkcnt = 5;
192
193 /* 2T2R TP issue */
194 if (rtlphy->rf_type == RF_2T2R)
195 return;
196
197 if (!rtlpriv->dm.txpower_tracking)
198 return;
199
200 if (rtlpriv->dm.txpowercount <= tx_power_checkcnt) {
201 rtlpriv->dm.txpowercount++;
202 return;
203 }
204
205 if (!tm_trigger) {
206 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER,
207 RFREG_OFFSET_MASK, 0x60);
208 tm_trigger = 1;
209 } else {
210 _rtl92s_dm_txpowertracking_callback_thermalmeter(hw);
211 tm_trigger = 0;
212 }
213}
214
215static void _rtl92s_dm_refresh_rateadaptive_mask(struct ieee80211_hw *hw)
216{
217 struct rtl_priv *rtlpriv = rtl_priv(hw);
218 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
219 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
220 struct rate_adaptive *ra = &(rtlpriv->ra);
221
222 u32 low_rssi_thresh = 0;
223 u32 middle_rssi_thresh = 0;
224 u32 high_rssi_thresh = 0;
225 u8 rssi_level;
226 struct ieee80211_sta *sta = NULL;
227
228 if (is_hal_stop(rtlhal))
229 return;
230
231 if (!rtlpriv->dm.useramask)
232 return;
233
234 if (!rtlpriv->dm.inform_fw_driverctrldm) {
235 rtl92s_phy_set_fw_cmd(hw, FW_CMD_CTRL_DM_BY_DRIVER);
236 rtlpriv->dm.inform_fw_driverctrldm = true;
237 }
238
239 rcu_read_lock();
240 if (mac->opmode == NL80211_IFTYPE_STATION)
241 sta = get_sta(hw, mac->vif, mac->bssid);
242 if ((mac->link_state == MAC80211_LINKED) &&
243 (mac->opmode == NL80211_IFTYPE_STATION)) {
244 switch (ra->pre_ratr_state) {
245 case DM_RATR_STA_HIGH:
246 high_rssi_thresh = 40;
247 middle_rssi_thresh = 30;
248 low_rssi_thresh = 20;
249 break;
250 case DM_RATR_STA_MIDDLE:
251 high_rssi_thresh = 44;
252 middle_rssi_thresh = 30;
253 low_rssi_thresh = 20;
254 break;
255 case DM_RATR_STA_LOW:
256 high_rssi_thresh = 44;
257 middle_rssi_thresh = 34;
258 low_rssi_thresh = 20;
259 break;
260 case DM_RATR_STA_ULTRALOW:
261 high_rssi_thresh = 44;
262 middle_rssi_thresh = 34;
263 low_rssi_thresh = 24;
264 break;
265 default:
266 high_rssi_thresh = 44;
267 middle_rssi_thresh = 34;
268 low_rssi_thresh = 24;
269 break;
270 }
271
272 if (rtlpriv->dm.undecorated_smoothed_pwdb >
273 (long)high_rssi_thresh) {
274 ra->ratr_state = DM_RATR_STA_HIGH;
275 rssi_level = 1;
276 } else if (rtlpriv->dm.undecorated_smoothed_pwdb >
277 (long)middle_rssi_thresh) {
278 ra->ratr_state = DM_RATR_STA_LOW;
279 rssi_level = 3;
280 } else if (rtlpriv->dm.undecorated_smoothed_pwdb >
281 (long)low_rssi_thresh) {
282 ra->ratr_state = DM_RATR_STA_LOW;
283 rssi_level = 5;
284 } else {
285 ra->ratr_state = DM_RATR_STA_ULTRALOW;
286 rssi_level = 6;
287 }
288
289 if (ra->pre_ratr_state != ra->ratr_state) {
290 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, ("RSSI = %ld "
291 "RSSI_LEVEL = %d PreState = %d, CurState = %d\n",
292 rtlpriv->dm.undecorated_smoothed_pwdb,
293 ra->ratr_state,
294 ra->pre_ratr_state, ra->ratr_state));
295
296 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
297 ra->ratr_state);
298 ra->pre_ratr_state = ra->ratr_state;
299 }
300 }
301 rcu_read_unlock();
302}
303
304static void _rtl92s_dm_switch_baseband_mrc(struct ieee80211_hw *hw)
305{
306 struct rtl_priv *rtlpriv = rtl_priv(hw);
307 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
308 struct rtl_phy *rtlphy = &(rtlpriv->phy);
309 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
310 bool current_mrc;
311 bool enable_mrc = true;
312 long tmpentry_maxpwdb = 0;
313 u8 rssi_a = 0;
314 u8 rssi_b = 0;
315
316 if (is_hal_stop(rtlhal))
317 return;
318
319 if ((rtlphy->rf_type == RF_1T1R) || (rtlphy->rf_type == RF_2T2R))
320 return;
321
322 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_MRC, (u8 *)(&current_mrc));
323
324 if (mac->link_state >= MAC80211_LINKED) {
325 if (rtlpriv->dm.undecorated_smoothed_pwdb > tmpentry_maxpwdb) {
326 rssi_a = rtlpriv->stats.rx_rssi_percentage[RF90_PATH_A];
327 rssi_b = rtlpriv->stats.rx_rssi_percentage[RF90_PATH_B];
328 }
329 }
330
331 /* MRC settings would NOT affect TP on Wireless B mode. */
332 if (mac->mode != WIRELESS_MODE_B) {
333 if ((rssi_a == 0) && (rssi_b == 0)) {
334 enable_mrc = true;
335 } else if (rssi_b > 30) {
336 /* Turn on B-Path */
337 enable_mrc = true;
338 } else if (rssi_b < 5) {
339 /* Turn off B-path */
340 enable_mrc = false;
341 /* Take care of RSSI differentiation. */
342 } else if (rssi_a > 15 && (rssi_a >= rssi_b)) {
343 if ((rssi_a - rssi_b) > 15)
344 /* Turn off B-path */
345 enable_mrc = false;
346 else if ((rssi_a - rssi_b) < 10)
347 /* Turn on B-Path */
348 enable_mrc = true;
349 else
350 enable_mrc = current_mrc;
351 } else {
352 /* Turn on B-Path */
353 enable_mrc = true;
354 }
355 }
356
357 /* Update MRC settings if needed. */
358 if (enable_mrc != current_mrc)
359 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC,
360 (u8 *)&enable_mrc);
361
362}
363
364void rtl92s_dm_init_edca_turbo(struct ieee80211_hw *hw)
365{
366 struct rtl_priv *rtlpriv = rtl_priv(hw);
367
368 rtlpriv->dm.current_turbo_edca = false;
369 rtlpriv->dm.is_any_nonbepkts = false;
370 rtlpriv->dm.is_cur_rdlstate = false;
371}
372
373static void _rtl92s_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
374{
375 struct rtl_priv *rtlpriv = rtl_priv(hw);
376 struct rate_adaptive *ra = &(rtlpriv->ra);
377
378 ra->ratr_state = DM_RATR_STA_MAX;
379 ra->pre_ratr_state = DM_RATR_STA_MAX;
380
381 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
382 rtlpriv->dm.useramask = true;
383 else
384 rtlpriv->dm.useramask = false;
385
386 rtlpriv->dm.useramask = false;
387 rtlpriv->dm.inform_fw_driverctrldm = false;
388}
389
390static void _rtl92s_dm_init_txpowertracking_thermalmeter(
391 struct ieee80211_hw *hw)
392{
393 struct rtl_priv *rtlpriv = rtl_priv(hw);
394
395 rtlpriv->dm.txpower_tracking = true;
396 rtlpriv->dm.txpowercount = 0;
397 rtlpriv->dm.txpower_trackinginit = false;
398}
399
400static void _rtl92s_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
401{
402 struct rtl_priv *rtlpriv = rtl_priv(hw);
403 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
404 u32 ret_value;
405
406 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
407 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
408
409 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
410 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
411 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
412 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
413 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
414
415 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
416 falsealm_cnt->cnt_rate_illegal + falsealm_cnt->cnt_crc8_fail +
417 falsealm_cnt->cnt_mcs_fail;
418
419 /* read CCK false alarm */
420 ret_value = rtl_get_bbreg(hw, 0xc64, MASKDWORD);
421 falsealm_cnt->cnt_cck_fail = (ret_value & 0xffff);
422 falsealm_cnt->cnt_all = falsealm_cnt->cnt_ofdm_fail +
423 falsealm_cnt->cnt_cck_fail;
424}
425
426static void rtl92s_backoff_enable_flag(struct ieee80211_hw *hw)
427{
428 struct rtl_priv *rtlpriv = rtl_priv(hw);
429 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
430
431 if (falsealm_cnt->cnt_all > digtable.fa_highthresh) {
432 if ((digtable.backoff_val - 6) <
433 digtable.backoffval_range_min)
434 digtable.backoff_val = digtable.backoffval_range_min;
435 else
436 digtable.backoff_val -= 6;
437 } else if (falsealm_cnt->cnt_all < digtable.fa_lowthresh) {
438 if ((digtable.backoff_val + 6) >
439 digtable.backoffval_range_max)
440 digtable.backoff_val =
441 digtable.backoffval_range_max;
442 else
443 digtable.backoff_val += 6;
444 }
445}
446
447static void _rtl92s_dm_initial_gain_sta_beforeconnect(struct ieee80211_hw *hw)
448{
449 struct rtl_priv *rtlpriv = rtl_priv(hw);
450 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
451 static u8 initialized, force_write;
452 u8 initial_gain = 0;
453
454 if ((digtable.pre_sta_connectstate == digtable.cur_sta_connectstate) ||
455 (digtable.cur_sta_connectstate == DIG_STA_BEFORE_CONNECT)) {
456 if (digtable.cur_sta_connectstate == DIG_STA_BEFORE_CONNECT) {
457 if (rtlpriv->psc.rfpwr_state != ERFON)
458 return;
459
460 if (digtable.backoff_enable_flag == true)
461 rtl92s_backoff_enable_flag(hw);
462 else
463 digtable.backoff_val = DM_DIG_BACKOFF;
464
465 if ((digtable.rssi_val + 10 - digtable.backoff_val) >
466 digtable.rx_gain_range_max)
467 digtable.cur_igvalue =
468 digtable.rx_gain_range_max;
469 else if ((digtable.rssi_val + 10 - digtable.backoff_val)
470 < digtable.rx_gain_range_min)
471 digtable.cur_igvalue =
472 digtable.rx_gain_range_min;
473 else
474 digtable.cur_igvalue = digtable.rssi_val + 10 -
475 digtable.backoff_val;
476
477 if (falsealm_cnt->cnt_all > 10000)
478 digtable.cur_igvalue =
479 (digtable.cur_igvalue > 0x33) ?
480 digtable.cur_igvalue : 0x33;
481
482 if (falsealm_cnt->cnt_all > 16000)
483 digtable.cur_igvalue =
484 digtable.rx_gain_range_max;
485 /* connected -> connected or disconnected -> disconnected */
486 } else {
487 /* Firmware control DIG, do nothing in driver dm */
488 return;
489 }
490 /* disconnected -> connected or connected ->
491 * disconnected or beforeconnect->(dis)connected */
492 } else {
493 /* Enable FW DIG */
494 digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
495 rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_ENABLE);
496
497 digtable.backoff_val = DM_DIG_BACKOFF;
498 digtable.cur_igvalue = rtlpriv->phy.default_initialgain[0];
499 digtable.pre_igvalue = 0;
500 return;
501 }
502
503 /* Forced writing to prevent from fw-dig overwriting. */
504 if (digtable.pre_igvalue != rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1,
505 MASKBYTE0))
506 force_write = 1;
507
508 if ((digtable.pre_igvalue != digtable.cur_igvalue) ||
509 !initialized || force_write) {
510 /* Disable FW DIG */
511 rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_DISABLE);
512
513 initial_gain = (u8)digtable.cur_igvalue;
514
515 /* Set initial gain. */
516 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, initial_gain);
517 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, initial_gain);
518 digtable.pre_igvalue = digtable.cur_igvalue;
519 initialized = 1;
520 force_write = 0;
521 }
522}
523
524static void _rtl92s_dm_ctrl_initgain_bytwoport(struct ieee80211_hw *hw)
525{
526 struct rtl_priv *rtlpriv = rtl_priv(hw);
527
528 if (rtlpriv->mac80211.act_scanning)
529 return;
530
531 /* Decide the current status and if modify initial gain or not */
532 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED ||
533 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
534 digtable.cur_sta_connectstate = DIG_STA_CONNECT;
535 else
536 digtable.cur_sta_connectstate = DIG_STA_DISCONNECT;
537
538 digtable.rssi_val = rtlpriv->dm.undecorated_smoothed_pwdb;
539
540 /* Change dig mode to rssi */
541 if (digtable.cur_sta_connectstate != DIG_STA_DISCONNECT) {
542 if (digtable.dig_twoport_algorithm ==
543 DIG_TWO_PORT_ALGO_FALSE_ALARM) {
544 digtable.dig_twoport_algorithm = DIG_TWO_PORT_ALGO_RSSI;
545 rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_MODE_SS);
546 }
547 }
548
549 _rtl92s_dm_false_alarm_counter_statistics(hw);
550 _rtl92s_dm_initial_gain_sta_beforeconnect(hw);
551
552 digtable.pre_sta_connectstate = digtable.cur_sta_connectstate;
553}
554
555static void _rtl92s_dm_ctrl_initgain_byrssi(struct ieee80211_hw *hw)
556{
557 struct rtl_priv *rtlpriv = rtl_priv(hw);
558 struct rtl_phy *rtlphy = &(rtlpriv->phy);
559
560 /* 2T2R TP issue */
561 if (rtlphy->rf_type == RF_2T2R)
562 return;
563
564 if (!rtlpriv->dm.dm_initialgain_enable)
565 return;
566
567 if (digtable.dig_enable_flag == false)
568 return;
569
570 _rtl92s_dm_ctrl_initgain_bytwoport(hw);
571}
572
573static void _rtl92s_dm_dynamic_txpower(struct ieee80211_hw *hw)
574{
575 struct rtl_priv *rtlpriv = rtl_priv(hw);
576 struct rtl_phy *rtlphy = &(rtlpriv->phy);
577 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
578 long undecorated_smoothed_pwdb;
579 long txpwr_threshold_lv1, txpwr_threshold_lv2;
580
581 /* 2T2R TP issue */
582 if (rtlphy->rf_type == RF_2T2R)
583 return;
584
585 if (!rtlpriv->dm.dynamic_txpower_enable ||
586 rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
587 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
588 return;
589 }
590
591 if ((mac->link_state < MAC80211_LINKED) &&
592 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
593 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
594 ("Not connected to any\n"));
595
596 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
597
598 rtlpriv->dm.last_dtp_lvl = TX_HIGHPWR_LEVEL_NORMAL;
599 return;
600 }
601
602 if (mac->link_state >= MAC80211_LINKED) {
603 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
604 undecorated_smoothed_pwdb =
605 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
606 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
607 ("AP Client PWDB = 0x%lx\n",
608 undecorated_smoothed_pwdb));
609 } else {
610 undecorated_smoothed_pwdb =
611 rtlpriv->dm.undecorated_smoothed_pwdb;
612 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
613 ("STA Default Port PWDB = 0x%lx\n",
614 undecorated_smoothed_pwdb));
615 }
616 } else {
617 undecorated_smoothed_pwdb =
618 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
619
620 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
621 ("AP Ext Port PWDB = 0x%lx\n",
622 undecorated_smoothed_pwdb));
623 }
624
625 txpwr_threshold_lv2 = TX_POWER_NEAR_FIELD_THRESH_LVL2;
626 txpwr_threshold_lv1 = TX_POWER_NEAR_FIELD_THRESH_LVL1;
627
628 if (rtl_get_bbreg(hw, 0xc90, MASKBYTE0) == 1)
629 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
630 else if (undecorated_smoothed_pwdb >= txpwr_threshold_lv2)
631 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL2;
632 else if ((undecorated_smoothed_pwdb < (txpwr_threshold_lv2 - 3)) &&
633 (undecorated_smoothed_pwdb >= txpwr_threshold_lv1))
634 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL1;
635 else if (undecorated_smoothed_pwdb < (txpwr_threshold_lv1 - 3))
636 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
637
638 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl))
639 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
640
641 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
642}
643
644static void _rtl92s_dm_init_dig(struct ieee80211_hw *hw)
645{
646 struct rtl_priv *rtlpriv = rtl_priv(hw);
647
648 /* Disable DIG scheme now.*/
649 digtable.dig_enable_flag = true;
650 digtable.backoff_enable_flag = true;
651
652 if ((rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) &&
653 (hal_get_firmwareversion(rtlpriv) >= 0x3c))
654 digtable.dig_algorithm = DIG_ALGO_BY_TOW_PORT;
655 else
656 digtable.dig_algorithm =
657 DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM;
658
659 digtable.dig_twoport_algorithm = DIG_TWO_PORT_ALGO_RSSI;
660 digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
661 /* off=by real rssi value, on=by digtable.rssi_val for new dig */
662 digtable.dig_dbgmode = DM_DBG_OFF;
663 digtable.dig_slgorithm_switch = 0;
664
665 /* 2007/10/04 MH Define init gain threshol. */
666 digtable.dig_state = DM_STA_DIG_MAX;
667 digtable.dig_highpwrstate = DM_STA_DIG_MAX;
668
669 digtable.cur_sta_connectstate = DIG_STA_DISCONNECT;
670 digtable.pre_sta_connectstate = DIG_STA_DISCONNECT;
671 digtable.cur_ap_connectstate = DIG_AP_DISCONNECT;
672 digtable.pre_ap_connectstate = DIG_AP_DISCONNECT;
673
674 digtable.rssi_lowthresh = DM_DIG_THRESH_LOW;
675 digtable.rssi_highthresh = DM_DIG_THRESH_HIGH;
676
677 digtable.fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
678 digtable.fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
679
680 digtable.rssi_highpower_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
681 digtable.rssi_highpower_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
682
683 /* for dig debug rssi value */
684 digtable.rssi_val = 50;
685 digtable.backoff_val = DM_DIG_BACKOFF;
686 digtable.rx_gain_range_max = DM_DIG_MAX;
687
688 digtable.rx_gain_range_min = DM_DIG_MIN;
689
690 digtable.backoffval_range_max = DM_DIG_BACKOFF_MAX;
691 digtable.backoffval_range_min = DM_DIG_BACKOFF_MIN;
692}
693
694static void _rtl92s_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
695{
696 struct rtl_priv *rtlpriv = rtl_priv(hw);
697
698 if ((hal_get_firmwareversion(rtlpriv) >= 60) &&
699 (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER))
700 rtlpriv->dm.dynamic_txpower_enable = true;
701 else
702 rtlpriv->dm.dynamic_txpower_enable = false;
703
704 rtlpriv->dm.last_dtp_lvl = TX_HIGHPWR_LEVEL_NORMAL;
705 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
706}
707
708void rtl92s_dm_init(struct ieee80211_hw *hw)
709{
710 struct rtl_priv *rtlpriv = rtl_priv(hw);
711
712 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
713 rtlpriv->dm.undecorated_smoothed_pwdb = -1;
714
715 _rtl92s_dm_init_dynamic_txpower(hw);
716 rtl92s_dm_init_edca_turbo(hw);
717 _rtl92s_dm_init_rate_adaptive_mask(hw);
718 _rtl92s_dm_init_txpowertracking_thermalmeter(hw);
719 _rtl92s_dm_init_dig(hw);
720
721 rtl_write_dword(rtlpriv, WFM5, FW_CCA_CHK_ENABLE);
722}
723
724void rtl92s_dm_watchdog(struct ieee80211_hw *hw)
725{
726 _rtl92s_dm_check_edca_turbo(hw);
727 _rtl92s_dm_check_txpowertracking_thermalmeter(hw);
728 _rtl92s_dm_ctrl_initgain_byrssi(hw);
729 _rtl92s_dm_dynamic_txpower(hw);
730 _rtl92s_dm_refresh_rateadaptive_mask(hw);
731 _rtl92s_dm_switch_baseband_mrc(hw);
732}
733
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/dm.h b/drivers/net/wireless/rtlwifi/rtl8192se/dm.h
new file mode 100644
index 000000000000..9051a556acc4
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/dm.h
@@ -0,0 +1,164 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29#ifndef __RTL_92S_DM_H__
30#define __RTL_92S_DM_H__
31
32struct dig_t {
33 u8 dig_enable_flag;
34 u8 dig_algorithm;
35 u8 dig_twoport_algorithm;
36 u8 dig_ext_port_stage;
37 u8 dig_dbgmode;
38 u8 dig_slgorithm_switch;
39
40 long rssi_lowthresh;
41 long rssi_highthresh;
42
43 u32 fa_lowthresh;
44 u32 fa_highthresh;
45
46 long rssi_highpower_lowthresh;
47 long rssi_highpower_highthresh;
48
49 u8 dig_state;
50 u8 dig_highpwrstate;
51 u8 cur_sta_connectstate;
52 u8 pre_sta_connectstate;
53 u8 cur_ap_connectstate;
54 u8 pre_ap_connectstate;
55
56 u8 cur_pd_thstate;
57 u8 pre_pd_thstate;
58 u8 cur_cs_ratiostate;
59 u8 pre_cs_ratiostate;
60
61 u32 pre_igvalue;
62 u32 cur_igvalue;
63
64 u8 backoff_enable_flag;
65 char backoff_val;
66 char backoffval_range_max;
67 char backoffval_range_min;
68 u8 rx_gain_range_max;
69 u8 rx_gain_range_min;
70
71 long rssi_val;
72};
73
74enum dm_dig_alg {
75 DIG_ALGO_BY_FALSE_ALARM = 0,
76 DIG_ALGO_BY_RSSI = 1,
77 DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM = 2,
78 DIG_ALGO_BY_TOW_PORT = 3,
79 DIG_ALGO_MAX
80};
81
82enum dm_dig_two_port_alg {
83 DIG_TWO_PORT_ALGO_RSSI = 0,
84 DIG_TWO_PORT_ALGO_FALSE_ALARM = 1,
85};
86
87enum dm_dig_dbg {
88 DM_DBG_OFF = 0,
89 DM_DBG_ON = 1,
90 DM_DBG_MAX
91};
92
93enum dm_dig_sta {
94 DM_STA_DIG_OFF = 0,
95 DM_STA_DIG_ON,
96 DM_STA_DIG_MAX
97};
98
99enum dm_dig_connect {
100 DIG_STA_DISCONNECT = 0,
101 DIG_STA_CONNECT = 1,
102 DIG_STA_BEFORE_CONNECT = 2,
103 DIG_AP_DISCONNECT = 3,
104 DIG_AP_CONNECT = 4,
105 DIG_AP_ADD_STATION = 5,
106 DIG_CONNECT_MAX
107};
108
109enum dm_dig_ext_port_alg {
110 DIG_EXT_PORT_STAGE_0 = 0,
111 DIG_EXT_PORT_STAGE_1 = 1,
112 DIG_EXT_PORT_STAGE_2 = 2,
113 DIG_EXT_PORT_STAGE_3 = 3,
114 DIG_EXT_PORT_STAGE_MAX = 4,
115};
116
117enum dm_ratr_sta {
118 DM_RATR_STA_HIGH = 0,
119 DM_RATR_STA_MIDDLEHIGH = 1,
120 DM_RATR_STA_MIDDLE = 2,
121 DM_RATR_STA_MIDDLELOW = 3,
122 DM_RATR_STA_LOW = 4,
123 DM_RATR_STA_ULTRALOW = 5,
124 DM_RATR_STA_MAX
125};
126
127#define DM_TYPE_BYFW 0
128#define DM_TYPE_BYDRIVER 1
129
130#define TX_HIGH_PWR_LEVEL_NORMAL 0
131#define TX_HIGH_PWR_LEVEL_LEVEL1 1
132#define TX_HIGH_PWR_LEVEL_LEVEL2 2
133
134#define HAL_DM_DIG_DISABLE BIT(0) /* Disable Dig */
135#define HAL_DM_HIPWR_DISABLE BIT(1) /* Disable High Power */
136
137#define TX_HIGHPWR_LEVEL_NORMAL 0
138#define TX_HIGHPWR_LEVEL_NORMAL1 1
139#define TX_HIGHPWR_LEVEL_NORMAL2 2
140
141#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
142#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
143
144#define DM_DIG_THRESH_HIGH 40
145#define DM_DIG_THRESH_LOW 35
146#define DM_FALSEALARM_THRESH_LOW 40
147#define DM_FALSEALARM_THRESH_HIGH 1000
148#define DM_DIG_HIGH_PWR_THRESH_HIGH 75
149#define DM_DIG_HIGH_PWR_THRESH_LOW 70
150#define DM_DIG_BACKOFF 12
151#define DM_DIG_MAX 0x3e
152#define DM_DIG_MIN 0x1c
153#define DM_DIG_MIN_Netcore 0x12
154#define DM_DIG_BACKOFF_MAX 12
155#define DM_DIG_BACKOFF_MIN -4
156
157extern struct dig_t digtable;
158
159void rtl92s_dm_watchdog(struct ieee80211_hw *hw);
160void rtl92s_dm_init(struct ieee80211_hw *hw);
161void rtl92s_dm_init_edca_turbo(struct ieee80211_hw *hw);
162
163#endif
164
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 11:53:08 -0500