3 files changed, 109 insertions, 1 deletions

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 4eee0f139cbd..385c083d24b2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
 
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
-         common.o gpio.o dma.o wd_timer.o display.o i2c.o
+         common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o
 
 omap-2-3-common                         = irq.o sdrc.o
 hwmod-common                            = omap_hwmod.o \
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
new file mode 100644
index 000000000000..297ebe03f09c
--- /dev/null
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -0,0 +1,72 @@
+/*
+ * IP block integration code for the HDQ1W/1-wire IP block
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by
+ *     Avinash.H.M <avinashhm@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+
+#include <plat/omap_hwmod.h>
+#include <plat/hdq1w.h>
+
+#include "common.h"
+
+/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_MODULE_SOFTRESET_WAIT       10000
+
+/**
+ * omap_hdq1w_reset - reset the OMAP HDQ1W module
+ * @oh: struct omap_hwmod *
+ *
+ * OCP soft reset the HDQ1W IP block.  Section 20.6.1.4 "HDQ1W/1-Wire
+ * Software Reset" of the OMAP34xx Technical Reference Manual Revision
+ * ZR (SWPU223R) does not include the rather important fact that, for
+ * the reset to succeed, the HDQ1W module's internal clock gate must be
+ * programmed to allow the clock to propagate to the rest of the
+ * module.  In this sense, it's rather similar to the I2C custom reset
+ * function.  Returns 0.
+ */
+int omap_hdq1w_reset(struct omap_hwmod *oh)
+{
+        u32 v;
+        int c = 0;
+
+        /* Write to the SOFTRESET bit */
+        omap_hwmod_softreset(oh);
+
+        /* Enable the module's internal clocks */
+        v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET);
+        v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT;
+        omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET);
+
+        /* Poll on RESETDONE bit */
+        omap_test_timeout((omap_hwmod_read(oh,
+                                           oh->class->sysc->syss_offs)
+                           & SYSS_RESETDONE_MASK),
+                          MAX_MODULE_SOFTRESET_WAIT, c);
+
+        if (c == MAX_MODULE_SOFTRESET_WAIT)
+                pr_warning("%s: %s: softreset failed (waited %d usec)\n",
+                           __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+        else
+                pr_debug("%s: %s: softreset in %d usec\n", __func__,
+                         oh->name, c);
+
+        return 0;
+}
diff --git a/arch/arm/plat-omap/include/plat/hdq1w.h b/arch/arm/plat-omap/include/plat/hdq1w.h
new file mode 100644
index 000000000000..0c1efc846d8d
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/hdq1w.h
@@ -0,0 +1,36 @@
+/*
+ * Shared macros and function prototypes for the HDQ1W/1-wire IP block
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+#ifndef ARCH_ARM_MACH_OMAP2_HDQ1W_H
+#define ARCH_ARM_MACH_OMAP2_HDQ1W_H
+
+#include <plat/omap_hwmod.h>
+
+/*
+ * XXX A future cleanup patch should modify
+ * drivers/w1/masters/omap_hdq.c to use these macros
+ */
+#define HDQ_CTRL_STATUS_OFFSET                  0x0c
+#define HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT       5
+
+
+extern int omap_hdq1w_reset(struct omap_hwmod *oh);
+
+#endif