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-rw-r--r--drivers/irqchip/irq-gic.c71
-rw-r--r--include/linux/irqchip/arm-gic.h2
-rw-r--r--kernel/irq/dummychip.c1
3 files changed, 2 insertions, 72 deletions
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 7b315e385ba3..01999d74bd3a 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -82,19 +82,6 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock);
82#define NR_GIC_CPU_IF 8 82#define NR_GIC_CPU_IF 8
83static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; 83static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
84 84
85/*
86 * Supported arch specific GIC irq extension.
87 * Default make them NULL.
88 */
89struct irq_chip gic_arch_extn = {
90 .irq_eoi = NULL,
91 .irq_mask = NULL,
92 .irq_unmask = NULL,
93 .irq_retrigger = NULL,
94 .irq_set_type = NULL,
95 .irq_set_wake = NULL,
96};
97
98#ifndef MAX_GIC_NR 85#ifndef MAX_GIC_NR
99#define MAX_GIC_NR 1 86#define MAX_GIC_NR 1
100#endif 87#endif
@@ -167,34 +154,16 @@ static int gic_peek_irq(struct irq_data *d, u32 offset)
167 154
168static void gic_mask_irq(struct irq_data *d) 155static void gic_mask_irq(struct irq_data *d)
169{ 156{
170 unsigned long flags;
171
172 raw_spin_lock_irqsave(&irq_controller_lock, flags);
173 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); 157 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
174 if (gic_arch_extn.irq_mask)
175 gic_arch_extn.irq_mask(d);
176 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
177} 158}
178 159
179static void gic_unmask_irq(struct irq_data *d) 160static void gic_unmask_irq(struct irq_data *d)
180{ 161{
181 unsigned long flags;
182
183 raw_spin_lock_irqsave(&irq_controller_lock, flags);
184 if (gic_arch_extn.irq_unmask)
185 gic_arch_extn.irq_unmask(d);
186 gic_poke_irq(d, GIC_DIST_ENABLE_SET); 162 gic_poke_irq(d, GIC_DIST_ENABLE_SET);
187 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
188} 163}
189 164
190static void gic_eoi_irq(struct irq_data *d) 165static void gic_eoi_irq(struct irq_data *d)
191{ 166{
192 if (gic_arch_extn.irq_eoi) {
193 raw_spin_lock(&irq_controller_lock);
194 gic_arch_extn.irq_eoi(d);
195 raw_spin_unlock(&irq_controller_lock);
196 }
197
198 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); 167 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
199} 168}
200 169
@@ -251,8 +220,6 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
251{ 220{
252 void __iomem *base = gic_dist_base(d); 221 void __iomem *base = gic_dist_base(d);
253 unsigned int gicirq = gic_irq(d); 222 unsigned int gicirq = gic_irq(d);
254 unsigned long flags;
255 int ret;
256 223
257 /* Interrupt configuration for SGIs can't be changed */ 224 /* Interrupt configuration for SGIs can't be changed */
258 if (gicirq < 16) 225 if (gicirq < 16)
@@ -263,25 +230,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
263 type != IRQ_TYPE_EDGE_RISING) 230 type != IRQ_TYPE_EDGE_RISING)
264 return -EINVAL; 231 return -EINVAL;
265 232
266 raw_spin_lock_irqsave(&irq_controller_lock, flags); 233 return gic_configure_irq(gicirq, type, base, NULL);
267
268 if (gic_arch_extn.irq_set_type)
269 gic_arch_extn.irq_set_type(d, type);
270
271 ret = gic_configure_irq(gicirq, type, base, NULL);
272
273 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
274
275 return ret;
276}
277
278static int gic_retrigger(struct irq_data *d)
279{
280 if (gic_arch_extn.irq_retrigger)
281 return gic_arch_extn.irq_retrigger(d);
282
283 /* the genirq layer expects 0 if we can't retrigger in hardware */
284 return 0;
285} 234}
286 235
287#ifdef CONFIG_SMP 236#ifdef CONFIG_SMP
@@ -312,21 +261,6 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
312} 261}
313#endif 262#endif
314 263
315#ifdef CONFIG_PM
316static int gic_set_wake(struct irq_data *d, unsigned int on)
317{
318 int ret = -ENXIO;
319
320 if (gic_arch_extn.irq_set_wake)
321 ret = gic_arch_extn.irq_set_wake(d, on);
322
323 return ret;
324}
325
326#else
327#define gic_set_wake NULL
328#endif
329
330static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 264static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
331{ 265{
332 u32 irqstat, irqnr; 266 u32 irqstat, irqnr;
@@ -385,11 +319,9 @@ static struct irq_chip gic_chip = {
385 .irq_unmask = gic_unmask_irq, 319 .irq_unmask = gic_unmask_irq,
386 .irq_eoi = gic_eoi_irq, 320 .irq_eoi = gic_eoi_irq,
387 .irq_set_type = gic_set_type, 321 .irq_set_type = gic_set_type,
388 .irq_retrigger = gic_retrigger,
389#ifdef CONFIG_SMP 322#ifdef CONFIG_SMP
390 .irq_set_affinity = gic_set_affinity, 323 .irq_set_affinity = gic_set_affinity,
391#endif 324#endif
392 .irq_set_wake = gic_set_wake,
393 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 325 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
394 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 326 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
395}; 327};
@@ -1055,7 +987,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
1055 set_handle_irq(gic_handle_irq); 987 set_handle_irq(gic_handle_irq);
1056 } 988 }
1057 989
1058 gic_chip.flags |= gic_arch_extn.flags;
1059 gic_dist_init(gic); 990 gic_dist_init(gic);
1060 gic_cpu_init(gic); 991 gic_cpu_init(gic);
1061 gic_pm_init(gic); 992 gic_pm_init(gic);
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 36ec4ae74634..9de976b4f9a7 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -95,8 +95,6 @@
95 95
96struct device_node; 96struct device_node;
97 97
98extern struct irq_chip gic_arch_extn;
99
100void gic_set_irqchip_flags(unsigned long flags); 98void gic_set_irqchip_flags(unsigned long flags);
101void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, 99void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
102 u32 offset, struct device_node *); 100 u32 offset, struct device_node *);
diff --git a/kernel/irq/dummychip.c b/kernel/irq/dummychip.c
index 988dc58e8847..2feb6feca0cc 100644
--- a/kernel/irq/dummychip.c
+++ b/kernel/irq/dummychip.c
@@ -57,5 +57,6 @@ struct irq_chip dummy_irq_chip = {
57 .irq_ack = noop, 57 .irq_ack = noop,
58 .irq_mask = noop, 58 .irq_mask = noop,
59 .irq_unmask = noop, 59 .irq_unmask = noop,
60 .flags = IRQCHIP_SKIP_SET_WAKE,
60}; 61};
61EXPORT_SYMBOL_GPL(dummy_irq_chip); 62EXPORT_SYMBOL_GPL(dummy_irq_chip);