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-rw-r--r--drivers/gpu/drm/i915/intel_display.c5
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c47
2 files changed, 29 insertions, 23 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fc9b98794b25..6fe4d07778e3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3615,6 +3615,11 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
3615 intel_update_watermarks(dev); 3615 intel_update_watermarks(dev);
3616 3616
3617 intel_enable_pll(dev_priv, pipe); 3617 intel_enable_pll(dev_priv, pipe);
3618
3619 for_each_encoder_on_crtc(dev, crtc, encoder)
3620 if (encoder->pre_enable)
3621 encoder->pre_enable(encoder);
3622
3618 intel_enable_pipe(dev_priv, pipe, false); 3623 intel_enable_pipe(dev_priv, pipe, false);
3619 intel_enable_plane(dev_priv, plane, pipe); 3624 intel_enable_plane(dev_priv, plane, pipe);
3620 3625
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index bff78a3ec37b..c7154bfa54cf 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -51,7 +51,6 @@ struct intel_lvds_encoder {
51 51
52 u32 pfit_control; 52 u32 pfit_control;
53 u32 pfit_pgm_ratios; 53 u32 pfit_pgm_ratios;
54 bool pfit_dirty;
55 bool is_dual_link; 54 bool is_dual_link;
56 u32 reg; 55 u32 reg;
57 56
@@ -151,6 +150,29 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
151 I915_WRITE(lvds_encoder->reg, temp); 150 I915_WRITE(lvds_encoder->reg, temp);
152} 151}
153 152
153static void intel_pre_enable_lvds(struct intel_encoder *encoder)
154{
155 struct drm_device *dev = encoder->base.dev;
156 struct intel_lvds_encoder *enc = to_lvds_encoder(&encoder->base);
157 struct drm_i915_private *dev_priv = dev->dev_private;
158
159 if (HAS_PCH_SPLIT(dev) || !enc->pfit_control)
160 return;
161
162 /*
163 * Enable automatic panel scaling so that non-native modes
164 * fill the screen. The panel fitter should only be
165 * adjusted whilst the pipe is disabled, according to
166 * register description and PRM.
167 */
168 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
169 enc->pfit_control,
170 enc->pfit_pgm_ratios);
171
172 I915_WRITE(PFIT_PGM_RATIOS, enc->pfit_pgm_ratios);
173 I915_WRITE(PFIT_CONTROL, enc->pfit_control);
174}
175
154/** 176/**
155 * Sets the power state for the panel. 177 * Sets the power state for the panel.
156 */ 178 */
@@ -172,22 +194,6 @@ static void intel_enable_lvds(struct intel_encoder *encoder)
172 194
173 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); 195 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
174 196
175 if (lvds_encoder->pfit_dirty) {
176 /*
177 * Enable automatic panel scaling so that non-native modes
178 * fill the screen. The panel fitter should only be
179 * adjusted whilst the pipe is disabled, according to
180 * register description and PRM.
181 */
182 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
183 lvds_encoder->pfit_control,
184 lvds_encoder->pfit_pgm_ratios);
185
186 I915_WRITE(PFIT_PGM_RATIOS, lvds_encoder->pfit_pgm_ratios);
187 I915_WRITE(PFIT_CONTROL, lvds_encoder->pfit_control);
188 lvds_encoder->pfit_dirty = false;
189 }
190
191 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); 197 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
192 POSTING_READ(lvds_encoder->reg); 198 POSTING_READ(lvds_encoder->reg);
193 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) 199 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
@@ -217,11 +223,6 @@ static void intel_disable_lvds(struct intel_encoder *encoder)
217 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) 223 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
218 DRM_ERROR("timed out waiting for panel to power off\n"); 224 DRM_ERROR("timed out waiting for panel to power off\n");
219 225
220 if (lvds_encoder->pfit_control) {
221 I915_WRITE(PFIT_CONTROL, 0);
222 lvds_encoder->pfit_dirty = true;
223 }
224
225 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); 226 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
226 POSTING_READ(lvds_encoder->reg); 227 POSTING_READ(lvds_encoder->reg);
227} 228}
@@ -461,7 +462,6 @@ out:
461 pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) { 462 pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) {
462 lvds_encoder->pfit_control = pfit_control; 463 lvds_encoder->pfit_control = pfit_control;
463 lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios; 464 lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios;
464 lvds_encoder->pfit_dirty = true;
465 } 465 }
466 dev_priv->lvds_border_bits = border; 466 dev_priv->lvds_border_bits = border;
467 467
@@ -1101,6 +1101,7 @@ bool intel_lvds_init(struct drm_device *dev)
1101 DRM_MODE_ENCODER_LVDS); 1101 DRM_MODE_ENCODER_LVDS);
1102 1102
1103 intel_encoder->enable = intel_enable_lvds; 1103 intel_encoder->enable = intel_enable_lvds;
1104 intel_encoder->pre_enable = intel_pre_enable_lvds;
1104 intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds; 1105 intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds;
1105 intel_encoder->disable = intel_disable_lvds; 1106 intel_encoder->disable = intel_disable_lvds;
1106 intel_encoder->get_hw_state = intel_lvds_get_hw_state; 1107 intel_encoder->get_hw_state = intel_lvds_get_hw_state;