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-rw-r--r--drivers/gpu/drm/radeon/sumo_dpm.c19
-rw-r--r--drivers/gpu/drm/radeon/sumo_dpm.h1
-rw-r--r--drivers/gpu/drm/radeon/sumo_smc.c2
-rw-r--r--drivers/gpu/drm/radeon/trinity_dpm.c6
4 files changed, 11 insertions, 17 deletions
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c
index 6074aafb58a7..e6e6e9059a6d 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.c
+++ b/drivers/gpu/drm/radeon/sumo_dpm.c
@@ -84,11 +84,6 @@ struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev)
84 return pi; 84 return pi;
85} 85}
86 86
87u32 sumo_get_xclk(struct radeon_device *rdev)
88{
89 return rdev->clock.spll.reference_freq;
90}
91
92static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable) 87static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
93{ 88{
94 if (enable) 89 if (enable)
@@ -124,7 +119,7 @@ static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable)
124static void sumo_program_git(struct radeon_device *rdev) 119static void sumo_program_git(struct radeon_device *rdev)
125{ 120{
126 u32 p, u; 121 u32 p, u;
127 u32 xclk = sumo_get_xclk(rdev); 122 u32 xclk = radeon_get_xclk(rdev);
128 123
129 r600_calculate_u_and_p(SUMO_GICST_DFLT, 124 r600_calculate_u_and_p(SUMO_GICST_DFLT,
130 xclk, 16, &p, &u); 125 xclk, 16, &p, &u);
@@ -135,7 +130,7 @@ static void sumo_program_git(struct radeon_device *rdev)
135static void sumo_program_grsd(struct radeon_device *rdev) 130static void sumo_program_grsd(struct radeon_device *rdev)
136{ 131{
137 u32 p, u; 132 u32 p, u;
138 u32 xclk = sumo_get_xclk(rdev); 133 u32 xclk = radeon_get_xclk(rdev);
139 u32 grs = 256 * 25 / 100; 134 u32 grs = 256 * 25 / 100;
140 135
141 r600_calculate_u_and_p(1, xclk, 14, &p, &u); 136 r600_calculate_u_and_p(1, xclk, 14, &p, &u);
@@ -155,7 +150,7 @@ static void sumo_gfx_powergating_initialize(struct radeon_device *rdev)
155 u32 p, u; 150 u32 p, u;
156 u32 p_c, p_p, d_p; 151 u32 p_c, p_p, d_p;
157 u32 r_t, i_t; 152 u32 r_t, i_t;
158 u32 xclk = sumo_get_xclk(rdev); 153 u32 xclk = radeon_get_xclk(rdev);
159 154
160 if (rdev->family == CHIP_PALM) { 155 if (rdev->family == CHIP_PALM) {
161 p_c = 4; 156 p_c = 4;
@@ -319,7 +314,7 @@ static void sumo_calculate_bsp(struct radeon_device *rdev,
319 u32 high_clk) 314 u32 high_clk)
320{ 315{
321 struct sumo_power_info *pi = sumo_get_pi(rdev); 316 struct sumo_power_info *pi = sumo_get_pi(rdev);
322 u32 xclk = sumo_get_xclk(rdev); 317 u32 xclk = radeon_get_xclk(rdev);
323 318
324 pi->pasi = 65535 * 100 / high_clk; 319 pi->pasi = 65535 * 100 / high_clk;
325 pi->asi = 65535 * 100 / high_clk; 320 pi->asi = 65535 * 100 / high_clk;
@@ -466,7 +461,7 @@ void sumo_clear_vc(struct radeon_device *rdev)
466void sumo_program_sstp(struct radeon_device *rdev) 461void sumo_program_sstp(struct radeon_device *rdev)
467{ 462{
468 u32 p, u; 463 u32 p, u;
469 u32 xclk = sumo_get_xclk(rdev); 464 u32 xclk = radeon_get_xclk(rdev);
470 465
471 r600_calculate_u_and_p(SUMO_SST_DFLT, 466 r600_calculate_u_and_p(SUMO_SST_DFLT,
472 xclk, 16, &p, &u); 467 xclk, 16, &p, &u);
@@ -909,7 +904,7 @@ static void sumo_start_am(struct radeon_device *rdev)
909 904
910static void sumo_program_ttp(struct radeon_device *rdev) 905static void sumo_program_ttp(struct radeon_device *rdev)
911{ 906{
912 u32 xclk = sumo_get_xclk(rdev); 907 u32 xclk = radeon_get_xclk(rdev);
913 u32 p, u; 908 u32 p, u;
914 u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5); 909 u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);
915 910
@@ -955,7 +950,7 @@ static void sumo_program_dc_hto(struct radeon_device *rdev)
955{ 950{
956 u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4); 951 u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);
957 u32 p, u; 952 u32 p, u;
958 u32 xclk = sumo_get_xclk(rdev); 953 u32 xclk = radeon_get_xclk(rdev);
959 954
960 r600_calculate_u_and_p(100000, 955 r600_calculate_u_and_p(100000,
961 xclk, 14, &p, &u); 956 xclk, 14, &p, &u);
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.h b/drivers/gpu/drm/radeon/sumo_dpm.h
index a3a7a6190713..07dda299c784 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.h
+++ b/drivers/gpu/drm/radeon/sumo_dpm.h
@@ -188,7 +188,6 @@ struct sumo_power_info {
188#define SUMO_GFXPOWERGATINGT_DFLT 100 188#define SUMO_GFXPOWERGATINGT_DFLT 100
189 189
190/* sumo_dpm.c */ 190/* sumo_dpm.c */
191u32 sumo_get_xclk(struct radeon_device *rdev);
192void sumo_gfx_clockgating_initialize(struct radeon_device *rdev); 191void sumo_gfx_clockgating_initialize(struct radeon_device *rdev);
193void sumo_program_vc(struct radeon_device *rdev, u32 vrc); 192void sumo_program_vc(struct radeon_device *rdev, u32 vrc);
194void sumo_clear_vc(struct radeon_device *rdev); 193void sumo_clear_vc(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/sumo_smc.c b/drivers/gpu/drm/radeon/sumo_smc.c
index 22c8151fb8f5..18abba5b5810 100644
--- a/drivers/gpu/drm/radeon/sumo_smc.c
+++ b/drivers/gpu/drm/radeon/sumo_smc.c
@@ -146,7 +146,7 @@ void sumo_enable_boost_timer(struct radeon_device *rdev)
146{ 146{
147 struct sumo_power_info *pi = sumo_get_pi(rdev); 147 struct sumo_power_info *pi = sumo_get_pi(rdev);
148 u32 period, unit, timer_value; 148 u32 period, unit, timer_value;
149 u32 xclk = sumo_get_xclk(rdev); 149 u32 xclk = radeon_get_xclk(rdev);
150 150
151 unit = (RREG32_RCU(RCU_LCLK_SCALING_CNTL) & LCLK_SCALING_TIMER_PRESCALER_MASK) 151 unit = (RREG32_RCU(RCU_LCLK_SCALING_CNTL) & LCLK_SCALING_TIMER_PRESCALER_MASK)
152 >> LCLK_SCALING_TIMER_PRESCALER_SHIFT; 152 >> LCLK_SCALING_TIMER_PRESCALER_SHIFT;
diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c
index 1699e93805b4..b2dc905c5815 100644
--- a/drivers/gpu/drm/radeon/trinity_dpm.c
+++ b/drivers/gpu/drm/radeon/trinity_dpm.c
@@ -361,7 +361,7 @@ static void trinity_gfx_powergating_initialize(struct radeon_device *rdev)
361 u32 p, u; 361 u32 p, u;
362 u32 value; 362 u32 value;
363 struct atom_clock_dividers dividers; 363 struct atom_clock_dividers dividers;
364 u32 xclk = sumo_get_xclk(rdev); 364 u32 xclk = radeon_get_xclk(rdev);
365 u32 sssd = 1; 365 u32 sssd = 1;
366 int ret; 366 int ret;
367 u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT; 367 u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
@@ -880,7 +880,7 @@ static void trinity_setup_uvd_dpm_interval(struct radeon_device *rdev,
880 u32 p, u; 880 u32 p, u;
881 u32 tp = RREG32_SMC(PM_TP); 881 u32 tp = RREG32_SMC(PM_TP);
882 u32 val; 882 u32 val;
883 u32 xclk = sumo_get_xclk(rdev); 883 u32 xclk = radeon_get_xclk(rdev);
884 884
885 r600_calculate_u_and_p(interval, xclk, 16, &p, &u); 885 r600_calculate_u_and_p(interval, xclk, 16, &p, &u);
886 886
@@ -1000,7 +1000,7 @@ static void trinity_program_sclk_dpm(struct radeon_device *rdev)
1000 u32 p, u; 1000 u32 p, u;
1001 u32 tp = RREG32_SMC(PM_TP); 1001 u32 tp = RREG32_SMC(PM_TP);
1002 u32 ni; 1002 u32 ni;
1003 u32 xclk = sumo_get_xclk(rdev); 1003 u32 xclk = radeon_get_xclk(rdev);
1004 u32 value; 1004 u32 value;
1005 1005
1006 r600_calculate_u_and_p(400, xclk, 16, &p, &u); 1006 r600_calculate_u_and_p(400, xclk, 16, &p, &u);