aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--arch/arm/mach-mvebu/pmsu.c13
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index b31a8293a347..5fda549d1c6b 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -143,7 +143,7 @@ static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
143} 143}
144 144
145/* No locking is needed because we only access per-CPU registers */ 145/* No locking is needed because we only access per-CPU registers */
146int armada_370_xp_pmsu_idle_enter(unsigned long deepidle) 146static int armada_370_xp_prepare(unsigned long deepidle)
147{ 147{
148 unsigned int hw_cpu = cpu_logical_map(smp_processor_id()); 148 unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
149 u32 reg; 149 u32 reg;
@@ -179,6 +179,17 @@ int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
179 reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP; 179 reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
180 writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); 180 writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
181 181
182 return 0;
183}
184
185int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
186{
187 int ret;
188
189 ret = armada_370_xp_prepare(deepidle);
190 if (ret)
191 return ret;
192
182 v7_exit_coherency_flush(all); 193 v7_exit_coherency_flush(all);
183 194
184 ll_disable_coherency(); 195 ll_disable_coherency();