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-rw-r--r--arch/mips/alchemy/devboards/Makefile2
-rw-r--r--arch/mips/alchemy/devboards/bcsr.c76
-rw-r--r--arch/mips/alchemy/devboards/db1x00/board_setup.c62
-rw-r--r--arch/mips/alchemy/devboards/pb1100/board_setup.c7
-rw-r--r--arch/mips/alchemy/devboards/pb1200/board_setup.c49
-rw-r--r--arch/mips/alchemy/devboards/pb1200/irqmap.c42
-rw-r--r--arch/mips/alchemy/devboards/pb1200/platform.c25
-rw-r--r--arch/mips/alchemy/devboards/pb1500/board_setup.c7
-rw-r--r--arch/mips/alchemy/devboards/pb1550/board_setup.c11
-rw-r--r--arch/mips/include/asm/mach-db1x00/bcsr.h235
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1200.h109
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1x00.h92
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1100.h49
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1200.h109
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1500.h13
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1550.h89
-rw-r--r--drivers/mtd/nand/au1550nd.c4
-rw-r--r--drivers/net/irda/au1k_ir.c14
-rw-r--r--drivers/pcmcia/au1000_db1x00.c76
19 files changed, 475 insertions, 596 deletions
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index 730f9f2b30e8..adc6717d7688 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -2,7 +2,7 @@
2# Alchemy Develboards 2# Alchemy Develboards
3# 3#
4 4
5obj-y += prom.o 5obj-y += prom.o bcsr.o
6obj-$(CONFIG_PM) += pm.o 6obj-$(CONFIG_PM) += pm.o
7obj-$(CONFIG_MIPS_PB1000) += pb1000/ 7obj-$(CONFIG_MIPS_PB1000) += pb1000/
8obj-$(CONFIG_MIPS_PB1100) += pb1100/ 8obj-$(CONFIG_MIPS_PB1100) += pb1100/
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
new file mode 100644
index 000000000000..85b7715901af
--- /dev/null
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -0,0 +1,76 @@
1/*
2 * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
3 *
4 * All Alchemy development boards (except, of course, the weird PB1000)
5 * have a few registers in a CPLD with standardised layout; they mostly
6 * only differ in base address.
7 * All registers are 16bits wide with 32bit spacing.
8 */
9
10#include <linux/module.h>
11#include <linux/spinlock.h>
12#include <asm/addrspace.h>
13#include <asm/io.h>
14#include <asm/mach-db1x00/bcsr.h>
15
16static struct bcsr_reg {
17 void __iomem *raddr;
18 spinlock_t lock;
19} bcsr_regs[BCSR_CNT];
20
21void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys)
22{
23 int i;
24
25 bcsr1_phys = KSEG1ADDR(CPHYSADDR(bcsr1_phys));
26 bcsr2_phys = KSEG1ADDR(CPHYSADDR(bcsr2_phys));
27
28 for (i = 0; i < BCSR_CNT; i++) {
29 if (i >= BCSR_HEXLEDS)
30 bcsr_regs[i].raddr = (void __iomem *)bcsr2_phys +
31 (0x04 * (i - BCSR_HEXLEDS));
32 else
33 bcsr_regs[i].raddr = (void __iomem *)bcsr1_phys +
34 (0x04 * i);
35
36 spin_lock_init(&bcsr_regs[i].lock);
37 }
38}
39
40unsigned short bcsr_read(enum bcsr_id reg)
41{
42 unsigned short r;
43 unsigned long flags;
44
45 spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
46 r = __raw_readw(bcsr_regs[reg].raddr);
47 spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
48 return r;
49}
50EXPORT_SYMBOL_GPL(bcsr_read);
51
52void bcsr_write(enum bcsr_id reg, unsigned short val)
53{
54 unsigned long flags;
55
56 spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
57 __raw_writew(val, bcsr_regs[reg].raddr);
58 wmb();
59 spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
60}
61EXPORT_SYMBOL_GPL(bcsr_write);
62
63void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set)
64{
65 unsigned short r;
66 unsigned long flags;
67
68 spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
69 r = __raw_readw(bcsr_regs[reg].raddr);
70 r &= ~clr;
71 r |= set;
72 __raw_writew(r, bcsr_regs[reg].raddr);
73 wmb();
74 spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
75}
76EXPORT_SYMBOL_GPL(bcsr_mod);
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index de30d8ea7176..e713390c69e6 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -32,12 +32,10 @@
32 32
33#include <asm/mach-au1x00/au1000.h> 33#include <asm/mach-au1x00/au1000.h>
34#include <asm/mach-db1x00/db1x00.h> 34#include <asm/mach-db1x00/db1x00.h>
35#include <asm/mach-db1x00/bcsr.h>
35 36
36#include <prom.h> 37#include <prom.h>
37 38
38
39static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
40
41const char *get_system_type(void) 39const char *get_system_type(void)
42{ 40{
43#ifdef CONFIG_MIPS_BOSPORUS 41#ifdef CONFIG_MIPS_BOSPORUS
@@ -49,15 +47,43 @@ const char *get_system_type(void)
49 47
50void board_reset(void) 48void board_reset(void)
51{ 49{
52 /* Hit BCSR.SW_RESET[RESET] */ 50 bcsr_write(BCSR_SYSTEM, 0);
53 bcsr->swreset = 0x0000;
54} 51}
55 52
56void __init board_setup(void) 53void __init board_setup(void)
57{ 54{
55 unsigned long bcsr1, bcsr2;
58 u32 pin_func = 0; 56 u32 pin_func = 0;
59 char *argptr; 57 char *argptr;
60 58
59 bcsr1 = DB1000_BCSR_PHYS_ADDR;
60 bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
61
62#ifdef CONFIG_MIPS_DB1000
63 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
64#endif
65#ifdef CONFIG_MIPS_DB1500
66 printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
67#endif
68#ifdef CONFIG_MIPS_DB1100
69 printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
70#endif
71#ifdef CONFIG_MIPS_BOSPORUS
72 printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
73#endif
74#ifdef CONFIG_MIPS_MIRAGE
75 printk(KERN_INFO "AMD Alchemy Mirage Board\n");
76#endif
77#ifdef CONFIG_MIPS_DB1550
78 printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
79
80 bcsr1 = DB1550_BCSR_PHYS_ADDR;
81 bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
82#endif
83
84 /* initialize board register space */
85 bcsr_init(bcsr1, bcsr2);
86
61 argptr = prom_getcmdline(); 87 argptr = prom_getcmdline();
62#ifdef CONFIG_SERIAL_8250_CONSOLE 88#ifdef CONFIG_SERIAL_8250_CONSOLE
63 argptr = strstr(argptr, "console="); 89 argptr = strstr(argptr, "console=");
@@ -89,11 +115,10 @@ void __init board_setup(void)
89 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF; 115 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
90 au_writel(pin_func, SYS_PINFUNC); 116 au_writel(pin_func, SYS_PINFUNC);
91 /* Power off until the driver is in use */ 117 /* Power off until the driver is in use */
92 bcsr->resets &= ~BCSR_RESETS_IRDA_MODE_MASK; 118 bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
93 bcsr->resets |= BCSR_RESETS_IRDA_MODE_OFF; 119 BCSR_RESETS_IRDA_MODE_OFF);
94 au_sync();
95#endif 120#endif
96 bcsr->pcmcia = 0x0000; /* turn off PCMCIA power */ 121 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
97 122
98 /* Enable GPIO[31:0] inputs */ 123 /* Enable GPIO[31:0] inputs */
99 alchemy_gpio1_input_enable(); 124 alchemy_gpio1_input_enable();
@@ -123,23 +148,4 @@ void __init board_setup(void)
123#endif 148#endif
124 149
125 au_sync(); 150 au_sync();
126
127#ifdef CONFIG_MIPS_DB1000
128 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
129#endif
130#ifdef CONFIG_MIPS_DB1500
131 printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
132#endif
133#ifdef CONFIG_MIPS_DB1100
134 printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
135#endif
136#ifdef CONFIG_MIPS_BOSPORUS
137 printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
138#endif
139#ifdef CONFIG_MIPS_MIRAGE
140 printk(KERN_INFO "AMD Alchemy Mirage Board\n");
141#endif
142#ifdef CONFIG_MIPS_DB1550
143 printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
144#endif
145} 151}
diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c
index 61263081ef58..eb749fb9daa1 100644
--- a/arch/mips/alchemy/devboards/pb1100/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c
@@ -30,6 +30,7 @@
30 30
31#include <asm/mach-au1x00/au1000.h> 31#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-pb1x00/pb1100.h> 32#include <asm/mach-pb1x00/pb1100.h>
33#include <asm/mach-db1x00/bcsr.h>
33 34
34#include <prom.h> 35#include <prom.h>
35 36
@@ -49,8 +50,7 @@ const char *get_system_type(void)
49 50
50void board_reset(void) 51void board_reset(void)
51{ 52{
52 /* Hit BCSR.RST_VDDI[SOFT_RESET] */ 53 bcsr_write(BCSR_SYSTEM, 0);
53 au_writel(0x00000000, PB1100_RST_VDDI);
54} 54}
55 55
56void __init board_init_irq(void) 56void __init board_init_irq(void)
@@ -63,6 +63,9 @@ void __init board_setup(void)
63 volatile void __iomem *base = (volatile void __iomem *)0xac000000UL; 63 volatile void __iomem *base = (volatile void __iomem *)0xac000000UL;
64 char *argptr; 64 char *argptr;
65 65
66 bcsr_init(DB1000_BCSR_PHYS_ADDR,
67 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
68
66 argptr = prom_getcmdline(); 69 argptr = prom_getcmdline();
67#ifdef CONFIG_SERIAL_8250_CONSOLE 70#ifdef CONFIG_SERIAL_8250_CONSOLE
68 argptr = strstr(argptr, "console="); 71 argptr = strstr(argptr, "console=");
diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c
index 94e6b7e7753d..db563800c31d 100644
--- a/arch/mips/alchemy/devboards/pb1200/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c
@@ -27,6 +27,8 @@
27#include <linux/init.h> 27#include <linux/init.h>
28#include <linux/sched.h> 28#include <linux/sched.h>
29 29
30#include <asm/mach-db1x00/bcsr.h>
31
30#include <prom.h> 32#include <prom.h>
31#include <au1xxx.h> 33#include <au1xxx.h>
32 34
@@ -38,14 +40,25 @@ const char *get_system_type(void)
38 40
39void board_reset(void) 41void board_reset(void)
40{ 42{
41 bcsr->resets = 0; 43 bcsr_write(BCSR_RESETS, 0);
42 bcsr->system = 0; 44 bcsr_write(BCSR_SYSTEM, 0);
43} 45}
44 46
45void __init board_setup(void) 47void __init board_setup(void)
46{ 48{
47 char *argptr; 49 char *argptr;
48 50
51#ifdef CONFIG_MIPS_PB1200
52 printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
53 bcsr_init(PB1200_BCSR_PHYS_ADDR,
54 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
55#endif
56#ifdef CONFIG_MIPS_DB1200
57 printk(KERN_INFO "AMD Alchemy Db1200 Board\n");
58 bcsr_init(DB1200_BCSR_PHYS_ADDR,
59 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
60#endif
61
49 argptr = prom_getcmdline(); 62 argptr = prom_getcmdline();
50#ifdef CONFIG_SERIAL_8250_CONSOLE 63#ifdef CONFIG_SERIAL_8250_CONSOLE
51 argptr = strstr(argptr, "console="); 64 argptr = strstr(argptr, "console=");
@@ -82,7 +95,7 @@ void __init board_setup(void)
82 u32 pin_func; 95 u32 pin_func;
83 96
84 /* Select SMBus in CPLD */ 97 /* Select SMBus in CPLD */
85 bcsr->resets &= ~BCSR_RESETS_PCS0MUX; 98 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
86 99
87 pin_func = au_readl(SYS_PINFUNC); 100 pin_func = au_readl(SYS_PINFUNC);
88 au_sync(); 101 au_sync();
@@ -116,38 +129,24 @@ void __init board_setup(void)
116 129
117 /* 130 /*
118 * The Pb1200 development board uses external MUX for PSC0 to 131 * The Pb1200 development board uses external MUX for PSC0 to
119 * support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI 132 * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI
120 */ 133 */
121#ifdef CONFIG_I2C_AU1550 134#ifdef CONFIG_I2C_AU1550
122 bcsr->resets &= ~BCSR_RESETS_PCS0MUX; 135 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
123#endif 136#endif
124 au_sync(); 137 au_sync();
125
126#ifdef CONFIG_MIPS_PB1200
127 printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
128#endif
129#ifdef CONFIG_MIPS_DB1200
130 printk(KERN_INFO "AMD Alchemy Db1200 Board\n");
131#endif
132} 138}
133 139
134int board_au1200fb_panel(void) 140int board_au1200fb_panel(void)
135{ 141{
136 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 142 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
137 int p;
138
139 p = bcsr->switches;
140 p >>= 8;
141 p &= 0x0F;
142 return p;
143} 143}
144 144
145int board_au1200fb_panel_init(void) 145int board_au1200fb_panel_init(void)
146{ 146{
147 /* Apply power */ 147 /* Apply power */
148 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 148 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
149 149 BCSR_BOARD_LCDBL);
150 bcsr->board |= BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL;
151 /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */ 150 /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */
152 return 0; 151 return 0;
153} 152}
@@ -155,10 +154,8 @@ int board_au1200fb_panel_init(void)
155int board_au1200fb_panel_shutdown(void) 154int board_au1200fb_panel_shutdown(void)
156{ 155{
157 /* Remove power */ 156 /* Remove power */
158 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 157 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
159 158 BCSR_BOARD_LCDBL, 0);
160 bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
161 BCSR_BOARD_LCDBL);
162 /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */ 159 /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */
163 return 0; 160 return 0;
164} 161}
diff --git a/arch/mips/alchemy/devboards/pb1200/irqmap.c b/arch/mips/alchemy/devboards/pb1200/irqmap.c
index fe47498da280..f379b02213f1 100644
--- a/arch/mips/alchemy/devboards/pb1200/irqmap.c
+++ b/arch/mips/alchemy/devboards/pb1200/irqmap.c
@@ -38,11 +38,14 @@
38#define PB1200_INT_END DB1200_INT_END 38#define PB1200_INT_END DB1200_INT_END
39#endif 39#endif
40 40
41#include <asm/mach-db1x00/bcsr.h>
42
41struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { 43struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
42 /* This is external interrupt cascade */ 44 /* This is external interrupt cascade */
43 { AU1000_GPIO_7, IRQF_TRIGGER_LOW, 0 }, 45 { AU1000_GPIO_7, IRQF_TRIGGER_LOW, 0 },
44}; 46};
45 47
48static void __iomem *bcsr_virt;
46 49
47/* 50/*
48 * Support for External interrupts on the Pb1200 Development platform. 51 * Support for External interrupts on the Pb1200 Development platform.
@@ -50,7 +53,7 @@ struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
50 53
51static void pb1200_cascade_handler(unsigned int irq, struct irq_desc *d) 54static void pb1200_cascade_handler(unsigned int irq, struct irq_desc *d)
52{ 55{
53 unsigned short bisr = bcsr->int_status; 56 unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
54 57
55 for ( ; bisr; bisr &= bisr - 1) 58 for ( ; bisr; bisr &= bisr - 1)
56 generic_handle_irq(PB1200_INT_BEGIN + __ffs(bisr)); 59 generic_handle_irq(PB1200_INT_BEGIN + __ffs(bisr));
@@ -61,24 +64,27 @@ static void pb1200_cascade_handler(unsigned int irq, struct irq_desc *d)
61 */ 64 */
62static void pb1200_mask_irq(unsigned int irq_nr) 65static void pb1200_mask_irq(unsigned int irq_nr)
63{ 66{
64 bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN); 67 unsigned short v = 1 << (irq_nr - PB1200_INT_BEGIN);
65 bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN); 68 __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
66 au_sync(); 69 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
70 wmb();
67} 71}
68 72
69static void pb1200_maskack_irq(unsigned int irq_nr) 73static void pb1200_maskack_irq(unsigned int irq_nr)
70{ 74{
71 bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN); 75 unsigned short v = 1 << (irq_nr - PB1200_INT_BEGIN);
72 bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN); 76 __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
73 bcsr->int_status = 1 << (irq_nr - PB1200_INT_BEGIN); /* ack */ 77 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
74 au_sync(); 78 __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */
79 wmb();
75} 80}
76 81
77static void pb1200_unmask_irq(unsigned int irq_nr) 82static void pb1200_unmask_irq(unsigned int irq_nr)
78{ 83{
79 bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN); 84 unsigned short v = 1 << (irq_nr - PB1200_INT_BEGIN);
80 bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN); 85 __raw_writew(v, bcsr_virt + BCSR_REG_INTSET);
81 au_sync(); 86 __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
87 wmb();
82} 88}
83 89
84static struct irq_chip pb1200_cpld_irq_type = { 90static struct irq_chip pb1200_cpld_irq_type = {
@@ -100,8 +106,10 @@ void __init board_init_irq(void)
100 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); 106 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
101 107
102#ifdef CONFIG_MIPS_PB1200 108#ifdef CONFIG_MIPS_PB1200
109 bcsr_virt = (void __iomem *)KSEG1ADDR(PB1200_BCSR_PHYS_ADDR);
110
103 /* We have a problem with CPLD rev 3. */ 111 /* We have a problem with CPLD rev 3. */
104 if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) { 112 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
105 printk(KERN_ERR "WARNING!!!\n"); 113 printk(KERN_ERR "WARNING!!!\n");
106 printk(KERN_ERR "WARNING!!!\n"); 114 printk(KERN_ERR "WARNING!!!\n");
107 printk(KERN_ERR "WARNING!!!\n"); 115 printk(KERN_ERR "WARNING!!!\n");
@@ -119,12 +127,14 @@ void __init board_init_irq(void)
119 printk(KERN_ERR "WARNING!!!\n"); 127 printk(KERN_ERR "WARNING!!!\n");
120 panic("Game over. Your score is 0."); 128 panic("Game over. Your score is 0.");
121 } 129 }
130#else
131 bcsr_virt = (void __iomem *)KSEG1ADDR(DB1200_BCSR_PHYS_ADDR);
122#endif 132#endif
133
123 /* mask & disable & ack all */ 134 /* mask & disable & ack all */
124 bcsr->intclr_mask = 0xffff; 135 bcsr_write(BCSR_INTCLR, 0xffff);
125 bcsr->intclr = 0xffff; 136 bcsr_write(BCSR_MASKCLR, 0xffff);
126 bcsr->int_status = 0xffff; 137 bcsr_write(BCSR_INTSTAT, 0xffff);
127 au_sync();
128 138
129 for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++) 139 for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++)
130 set_irq_chip_and_handler_name(irq, &pb1200_cpld_irq_type, 140 set_irq_chip_and_handler_name(irq, &pb1200_cpld_irq_type,
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index b93dff4a6789..dfdaabf77909 100644
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -26,27 +26,28 @@
26 26
27#include <asm/mach-au1x00/au1xxx.h> 27#include <asm/mach-au1x00/au1xxx.h>
28#include <asm/mach-au1x00/au1100_mmc.h> 28#include <asm/mach-au1x00/au1100_mmc.h>
29#include <asm/mach-db1x00/bcsr.h>
29 30
30static int mmc_activity; 31static int mmc_activity;
31 32
32static void pb1200mmc0_set_power(void *mmc_host, int state) 33static void pb1200mmc0_set_power(void *mmc_host, int state)
33{ 34{
34 if (state) 35 if (state)
35 bcsr->board |= BCSR_BOARD_SD0PWR; 36 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
36 else 37 else
37 bcsr->board &= ~BCSR_BOARD_SD0PWR; 38 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
38 39
39 au_sync_delay(1); 40 msleep(1);
40} 41}
41 42
42static int pb1200mmc0_card_readonly(void *mmc_host) 43static int pb1200mmc0_card_readonly(void *mmc_host)
43{ 44{
44 return (bcsr->status & BCSR_STATUS_SD0WP) ? 1 : 0; 45 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
45} 46}
46 47
47static int pb1200mmc0_card_inserted(void *mmc_host) 48static int pb1200mmc0_card_inserted(void *mmc_host)
48{ 49{
49 return (bcsr->sig_status & BCSR_INT_SD0INSERT) ? 1 : 0; 50 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
50} 51}
51 52
52static void pb1200_mmcled_set(struct led_classdev *led, 53static void pb1200_mmcled_set(struct led_classdev *led,
@@ -54,10 +55,10 @@ static void pb1200_mmcled_set(struct led_classdev *led,
54{ 55{
55 if (brightness != LED_OFF) { 56 if (brightness != LED_OFF) {
56 if (++mmc_activity == 1) 57 if (++mmc_activity == 1)
57 bcsr->disk_leds &= ~(1 << 8); 58 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
58 } else { 59 } else {
59 if (--mmc_activity == 0) 60 if (--mmc_activity == 0)
60 bcsr->disk_leds |= (1 << 8); 61 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
61 } 62 }
62} 63}
63 64
@@ -69,21 +70,21 @@ static struct led_classdev pb1200mmc_led = {
69static void pb1200mmc1_set_power(void *mmc_host, int state) 70static void pb1200mmc1_set_power(void *mmc_host, int state)
70{ 71{
71 if (state) 72 if (state)
72 bcsr->board |= BCSR_BOARD_SD1PWR; 73 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
73 else 74 else
74 bcsr->board &= ~BCSR_BOARD_SD1PWR; 75 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
75 76
76 au_sync_delay(1); 77 msleep(1);
77} 78}
78 79
79static int pb1200mmc1_card_readonly(void *mmc_host) 80static int pb1200mmc1_card_readonly(void *mmc_host)
80{ 81{
81 return (bcsr->status & BCSR_STATUS_SD1WP) ? 1 : 0; 82 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
82} 83}
83 84
84static int pb1200mmc1_card_inserted(void *mmc_host) 85static int pb1200mmc1_card_inserted(void *mmc_host)
85{ 86{
86 return (bcsr->sig_status & BCSR_INT_SD1INSERT) ? 1 : 0; 87 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
87} 88}
88#endif 89#endif
89 90
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
index d7a56569e7ed..c5389e5afb93 100644
--- a/arch/mips/alchemy/devboards/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -30,6 +30,7 @@
30 30
31#include <asm/mach-au1x00/au1000.h> 31#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-pb1x00/pb1500.h> 32#include <asm/mach-pb1x00/pb1500.h>
33#include <asm/mach-db1x00/bcsr.h>
33 34
34#include <prom.h> 35#include <prom.h>
35 36
@@ -55,8 +56,7 @@ const char *get_system_type(void)
55 56
56void board_reset(void) 57void board_reset(void)
57{ 58{
58 /* Hit BCSR.RST_VDDI[SOFT_RESET] */ 59 bcsr_write(BCSR_SYSTEM, 0);
59 au_writel(0x00000000, PB1500_RST_VDDI);
60} 60}
61 61
62void __init board_init_irq(void) 62void __init board_init_irq(void)
@@ -70,6 +70,9 @@ void __init board_setup(void)
70 u32 sys_freqctrl, sys_clksrc; 70 u32 sys_freqctrl, sys_clksrc;
71 char *argptr; 71 char *argptr;
72 72
73 bcsr_init(DB1000_BCSR_PHYS_ADDR,
74 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
75
73 argptr = prom_getcmdline(); 76 argptr = prom_getcmdline();
74#ifdef CONFIG_SERIAL_8250_CONSOLE 77#ifdef CONFIG_SERIAL_8250_CONSOLE
75 argptr = strstr(argptr, "console="); 78 argptr = strstr(argptr, "console=");
diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
index b6e9e7d247a3..af7a1b5fe7c7 100644
--- a/arch/mips/alchemy/devboards/pb1550/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c
@@ -32,6 +32,7 @@
32 32
33#include <asm/mach-au1x00/au1000.h> 33#include <asm/mach-au1x00/au1000.h>
34#include <asm/mach-pb1x00/pb1550.h> 34#include <asm/mach-pb1x00/pb1550.h>
35#include <asm/mach-db1x00/bcsr.h>
35 36
36#include <prom.h> 37#include <prom.h>
37 38
@@ -53,8 +54,7 @@ const char *get_system_type(void)
53 54
54void board_reset(void) 55void board_reset(void)
55{ 56{
56 /* Hit BCSR.SYSTEM[RESET] */ 57 bcsr_write(BCSR_SYSTEM, 0);
57 au_writew(au_readw(0xAF00001C) & ~BCSR_SYSTEM_RESET, 0xAF00001C);
58} 58}
59 59
60void __init board_init_irq(void) 60void __init board_init_irq(void)
@@ -66,6 +66,10 @@ void __init board_setup(void)
66{ 66{
67 u32 pin_func; 67 u32 pin_func;
68 68
69 bcsr_init(PB1550_BCSR_PHYS_ADDR,
70 PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
71
72
69#ifdef CONFIG_SERIAL_8250_CONSOLE 73#ifdef CONFIG_SERIAL_8250_CONSOLE
70 char *argptr; 74 char *argptr;
71 argptr = prom_getcmdline(); 75 argptr = prom_getcmdline();
@@ -85,8 +89,7 @@ void __init board_setup(void)
85 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; 89 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
86 au_writel(pin_func, SYS_PINFUNC); 90 au_writel(pin_func, SYS_PINFUNC);
87 91
88 au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */ 92 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
89 au_sync();
90 93
91 printk(KERN_INFO "AMD Alchemy Pb1550 Board\n"); 94 printk(KERN_INFO "AMD Alchemy Pb1550 Board\n");
92} 95}
diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h
new file mode 100644
index 000000000000..ecbe19e3c14e
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/bcsr.h
@@ -0,0 +1,235 @@
1/*
2 * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
3 *
4 * All Alchemy development boards (except, of course, the weird PB1000)
5 * have a few registers in a CPLD with standardised layout; they mostly
6 * only differ in base address and bit meanings in the RESETS and BOARD
7 * registers.
8 *
9 * All data taken from the official AMD board documentation sheets.
10 */
11
12#ifndef _DB1XXX_BCSR_H_
13#define _DB1XXX_BCSR_H_
14
15
16/* BCSR base addresses on various boards. BCSR base 2 refers to the
17 * physical address of the first HEXLEDS register, which is usually
18 * a variable offset from the WHOAMI register.
19 */
20
21/* DB1000, DB1100, DB1500, PB1100, PB1500 */
22#define DB1000_BCSR_PHYS_ADDR 0x0E000000
23#define DB1000_BCSR_HEXLED_OFS 0x01000000
24
25#define DB1550_BCSR_PHYS_ADDR 0x0F000000
26#define DB1550_BCSR_HEXLED_OFS 0x00400000
27
28#define PB1550_BCSR_PHYS_ADDR 0x0F000000
29#define PB1550_BCSR_HEXLED_OFS 0x00800000
30
31#define DB1200_BCSR_PHYS_ADDR 0x19800000
32#define DB1200_BCSR_HEXLED_OFS 0x00400000
33
34#define PB1200_BCSR_PHYS_ADDR 0x0D800000
35#define PB1200_BCSR_HEXLED_OFS 0x00400000
36
37
38enum bcsr_id {
39 /* BCSR base 1 */
40 BCSR_WHOAMI = 0,
41 BCSR_STATUS,
42 BCSR_SWITCHES,
43 BCSR_RESETS,
44 BCSR_PCMCIA,
45 BCSR_BOARD,
46 BCSR_LEDS,
47 BCSR_SYSTEM,
48 /* Au1200/1300 based boards */
49 BCSR_INTCLR,
50 BCSR_INTSET,
51 BCSR_MASKCLR,
52 BCSR_MASKSET,
53 BCSR_SIGSTAT,
54 BCSR_INTSTAT,
55
56 /* BCSR base 2 */
57 BCSR_HEXLEDS,
58 BCSR_RSVD1,
59 BCSR_HEXCLEAR,
60
61 BCSR_CNT,
62};
63
64/* register offsets, valid for all Db1xxx/Pb1xxx boards */
65#define BCSR_REG_WHOAMI 0x00
66#define BCSR_REG_STATUS 0x04
67#define BCSR_REG_SWITCHES 0x08
68#define BCSR_REG_RESETS 0x0c
69#define BCSR_REG_PCMCIA 0x10
70#define BCSR_REG_BOARD 0x14
71#define BCSR_REG_LEDS 0x18
72#define BCSR_REG_SYSTEM 0x1c
73/* Au1200/Au1300 based boards: CPLD IRQ muxer */
74#define BCSR_REG_INTCLR 0x20
75#define BCSR_REG_INTSET 0x24
76#define BCSR_REG_MASKCLR 0x28
77#define BCSR_REG_MASKSET 0x2c
78#define BCSR_REG_SIGSTAT 0x30
79#define BCSR_REG_INTSTAT 0x34
80
81/* hexled control, offset from BCSR base 2 */
82#define BCSR_REG_HEXLEDS 0x00
83#define BCSR_REG_HEXCLEAR 0x08
84
85/*
86 * Register Bits and Pieces.
87 */
88#define BCSR_WHOAMI_DCID(x) ((x) & 0xf)
89#define BCSR_WHOAMI_CPLD(x) (((x) >> 4) & 0xf)
90#define BCSR_WHOAMI_BOARD(x) (((x) >> 8) & 0xf)
91
92/* register "WHOAMI" bits 11:8 identify the board */
93enum bcsr_whoami_boards {
94 BCSR_WHOAMI_PB1500 = 1,
95 BCSR_WHOAMI_PB1500R2,
96 BCSR_WHOAMI_PB1100,
97 BCSR_WHOAMI_DB1000,
98 BCSR_WHOAMI_DB1100,
99 BCSR_WHOAMI_DB1500,
100 BCSR_WHOAMI_DB1550,
101 BCSR_WHOAMI_PB1550_DDR,
102 BCSR_WHOAMI_PB1550 = BCSR_WHOAMI_PB1550_DDR,
103 BCSR_WHOAMI_PB1550_SDR,
104 BCSR_WHOAMI_PB1200_DDR1,
105 BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1,
106 BCSR_WHOAMI_PB1200_DDR2,
107 BCSR_WHOAMI_DB1200,
108};
109
110/* STATUS reg. Unless otherwise noted, they're valid on all boards.
111 * PB1200 = DB1200.
112 */
113#define BCSR_STATUS_PC0VS 0x0003
114#define BCSR_STATUS_PC1VS 0x000C
115#define BCSR_STATUS_PC0FI 0x0010
116#define BCSR_STATUS_PC1FI 0x0020
117#define BCSR_STATUS_PB1550_SWAPBOOT 0x0040
118#define BCSR_STATUS_SRAMWIDTH 0x0080
119#define BCSR_STATUS_FLASHBUSY 0x0100
120#define BCSR_STATUS_ROMBUSY 0x0400
121#define BCSR_STATUS_SD0WP 0x0400 /* DB1200 */
122#define BCSR_STATUS_SD1WP 0x0800
123#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */
124#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000
125#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200 */
126#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200 */
127#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */
128#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */
129#define BCSR_STATUS_FLASHDEN 0xC000
130#define BCSR_STATUS_DB1550_U0RXD 0x1000 /* DB1550 */
131#define BCSR_STATUS_DB1550_U3RXD 0x2000 /* DB1550 */
132#define BCSR_STATUS_PB1550_U0RXD 0x1000 /* PB1550 */
133#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */
134#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */
135
136
137/* DB/PB1000,1100,1500,1550 */
138#define BCSR_RESETS_PHY0 0x0001
139#define BCSR_RESETS_PHY1 0x0002
140#define BCSR_RESETS_DC 0x0004
141#define BCSR_RESETS_FIR_SEL 0x2000
142#define BCSR_RESETS_IRDA_MODE_MASK 0xC000
143#define BCSR_RESETS_IRDA_MODE_FULL 0x0000
144#define BCSR_RESETS_PB1550_WSCFSM 0x2000
145#define BCSR_RESETS_IRDA_MODE_OFF 0x4000
146#define BCSR_RESETS_IRDA_MODE_2_3 0x8000
147#define BCSR_RESETS_IRDA_MODE_1_3 0xC000
148#define BCSR_RESETS_DMAREQ 0x8000 /* PB1550 */
149
150#define BCSR_BOARD_PCIM66EN 0x0001
151#define BCSR_BOARD_SD0PWR 0x0040
152#define BCSR_BOARD_SD1PWR 0x0080
153#define BCSR_BOARD_PCIM33 0x0100
154#define BCSR_BOARD_PCIEXTARB 0x0200
155#define BCSR_BOARD_GPIO200RST 0x0400
156#define BCSR_BOARD_PCICLKOUT 0x0800
157#define BCSR_BOARD_PCICFG 0x1000
158#define BCSR_BOARD_SPISEL 0x4000 /* PB/DB1550 */
159#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */
160#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */
161
162
163/* DB/PB1200 */
164#define BCSR_RESETS_ETH 0x0001
165#define BCSR_RESETS_CAMERA 0x0002
166#define BCSR_RESETS_DC 0x0004
167#define BCSR_RESETS_IDE 0x0008
168#define BCSR_RESETS_TV 0x0010 /* DB1200 */
169/* Not resets but in the same register */
170#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */
171#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */
172#define BCSR_RESETS_PSC0MUX 0x1000
173#define BCSR_RESETS_PSC1MUX 0x2000
174#define BCSR_RESETS_SPISEL 0x4000
175#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */
176
177#define BCSR_BOARD_LCDVEE 0x0001
178#define BCSR_BOARD_LCDVDD 0x0002
179#define BCSR_BOARD_LCDBL 0x0004
180#define BCSR_BOARD_CAMSNAP 0x0010
181#define BCSR_BOARD_CAMPWR 0x0020
182#define BCSR_BOARD_SD0PWR 0x0040
183
184
185#define BCSR_SWITCHES_DIP 0x00FF
186#define BCSR_SWITCHES_DIP_1 0x0080
187#define BCSR_SWITCHES_DIP_2 0x0040
188#define BCSR_SWITCHES_DIP_3 0x0020
189#define BCSR_SWITCHES_DIP_4 0x0010
190#define BCSR_SWITCHES_DIP_5 0x0008
191#define BCSR_SWITCHES_DIP_6 0x0004
192#define BCSR_SWITCHES_DIP_7 0x0002
193#define BCSR_SWITCHES_DIP_8 0x0001
194#define BCSR_SWITCHES_ROTARY 0x0F00
195
196
197#define BCSR_PCMCIA_PC0VPP 0x0003
198#define BCSR_PCMCIA_PC0VCC 0x000C
199#define BCSR_PCMCIA_PC0DRVEN 0x0010
200#define BCSR_PCMCIA_PC0RST 0x0080
201#define BCSR_PCMCIA_PC1VPP 0x0300
202#define BCSR_PCMCIA_PC1VCC 0x0C00
203#define BCSR_PCMCIA_PC1DRVEN 0x1000
204#define BCSR_PCMCIA_PC1RST 0x8000
205
206
207#define BCSR_LEDS_DECIMALS 0x0003
208#define BCSR_LEDS_LED0 0x0100
209#define BCSR_LEDS_LED1 0x0200
210#define BCSR_LEDS_LED2 0x0400
211#define BCSR_LEDS_LED3 0x0800
212
213
214#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */
215#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */
216#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */
217
218
219
220
221/* initialize BCSR for a board. Provide the PHYSICAL addresses of both
222 * BCSR spaces.
223 */
224void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys);
225
226/* read a board register */
227unsigned short bcsr_read(enum bcsr_id reg);
228
229/* write to a board register */
230void bcsr_write(enum bcsr_id reg, unsigned short val);
231
232/* modify a register. clear bits set in 'clr', set bits set in 'set' */
233void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set);
234
235#endif
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index 27f26102b1bb..2909b834e4af 100644
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -45,113 +45,6 @@
45#define AC97_PSC_BASE PSC1_BASE_ADDR 45#define AC97_PSC_BASE PSC1_BASE_ADDR
46#define I2S_PSC_BASE PSC1_BASE_ADDR 46#define I2S_PSC_BASE PSC1_BASE_ADDR
47 47
48#define BCSR_KSEG1_ADDR 0xB9800000
49
50typedef volatile struct
51{
52 /*00*/ u16 whoami;
53 u16 reserved0;
54 /*04*/ u16 status;
55 u16 reserved1;
56 /*08*/ u16 switches;
57 u16 reserved2;
58 /*0C*/ u16 resets;
59 u16 reserved3;
60
61 /*10*/ u16 pcmcia;
62 u16 reserved4;
63 /*14*/ u16 board;
64 u16 reserved5;
65 /*18*/ u16 disk_leds;
66 u16 reserved6;
67 /*1C*/ u16 system;
68 u16 reserved7;
69
70 /*20*/ u16 intclr;
71 u16 reserved8;
72 /*24*/ u16 intset;
73 u16 reserved9;
74 /*28*/ u16 intclr_mask;
75 u16 reserved10;
76 /*2C*/ u16 intset_mask;
77 u16 reserved11;
78
79 /*30*/ u16 sig_status;
80 u16 reserved12;
81 /*34*/ u16 int_status;
82 u16 reserved13;
83 /*38*/ u16 reserved14;
84 u16 reserved15;
85 /*3C*/ u16 reserved16;
86 u16 reserved17;
87
88} BCSR;
89
90static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
91
92/*
93 * Register bit definitions for the BCSRs
94 */
95#define BCSR_WHOAMI_DCID 0x000F
96#define BCSR_WHOAMI_CPLD 0x00F0
97#define BCSR_WHOAMI_BOARD 0x0F00
98
99#define BCSR_STATUS_PCMCIA0VS 0x0003
100#define BCSR_STATUS_PCMCIA1VS 0x000C
101#define BCSR_STATUS_SWAPBOOT 0x0040
102#define BCSR_STATUS_FLASHBUSY 0x0100
103#define BCSR_STATUS_IDECBLID 0x0200
104#define BCSR_STATUS_SD0WP 0x0400
105#define BCSR_STATUS_U0RXD 0x1000
106#define BCSR_STATUS_U1RXD 0x2000
107
108#define BCSR_SWITCHES_OCTAL 0x00FF
109#define BCSR_SWITCHES_DIP_1 0x0080
110#define BCSR_SWITCHES_DIP_2 0x0040
111#define BCSR_SWITCHES_DIP_3 0x0020
112#define BCSR_SWITCHES_DIP_4 0x0010
113#define BCSR_SWITCHES_DIP_5 0x0008
114#define BCSR_SWITCHES_DIP_6 0x0004
115#define BCSR_SWITCHES_DIP_7 0x0002
116#define BCSR_SWITCHES_DIP_8 0x0001
117#define BCSR_SWITCHES_ROTARY 0x0F00
118
119#define BCSR_RESETS_ETH 0x0001
120#define BCSR_RESETS_CAMERA 0x0002
121#define BCSR_RESETS_DC 0x0004
122#define BCSR_RESETS_IDE 0x0008
123#define BCSR_RESETS_TV 0x0010
124/* Not resets but in the same register */
125#define BCSR_RESETS_PWMR1MUX 0x0800
126#define BCSR_RESETS_PCS0MUX 0x1000
127#define BCSR_RESETS_PCS1MUX 0x2000
128#define BCSR_RESETS_SPISEL 0x4000
129
130#define BCSR_PCMCIA_PC0VPP 0x0003
131#define BCSR_PCMCIA_PC0VCC 0x000C
132#define BCSR_PCMCIA_PC0DRVEN 0x0010
133#define BCSR_PCMCIA_PC0RST 0x0080
134#define BCSR_PCMCIA_PC1VPP 0x0300
135#define BCSR_PCMCIA_PC1VCC 0x0C00
136#define BCSR_PCMCIA_PC1DRVEN 0x1000
137#define BCSR_PCMCIA_PC1RST 0x8000
138
139#define BCSR_BOARD_LCDVEE 0x0001
140#define BCSR_BOARD_LCDVDD 0x0002
141#define BCSR_BOARD_LCDBL 0x0004
142#define BCSR_BOARD_CAMSNAP 0x0010
143#define BCSR_BOARD_CAMPWR 0x0020
144#define BCSR_BOARD_SD0PWR 0x0040
145
146#define BCSR_LEDS_DECIMALS 0x0003
147#define BCSR_LEDS_LED0 0x0100
148#define BCSR_LEDS_LED1 0x0200
149#define BCSR_LEDS_LED2 0x0400
150#define BCSR_LEDS_LED3 0x0800
151
152#define BCSR_SYSTEM_POWEROFF 0x4000
153#define BCSR_SYSTEM_RESET 0x8000
154
155/* Bit positions for the different interrupt sources */ 48/* Bit positions for the different interrupt sources */
156#define BCSR_INT_IDE 0x0001 49#define BCSR_INT_IDE 0x0001
157#define BCSR_INT_ETH 0x0002 50#define BCSR_INT_ETH 0x0002
@@ -222,7 +115,7 @@ enum external_pb1200_ints {
222 115
223#define BOARD_PC0_INT DB1200_PC0_INT 116#define BOARD_PC0_INT DB1200_PC0_INT
224#define BOARD_PC1_INT DB1200_PC1_INT 117#define BOARD_PC1_INT DB1200_PC1_INT
225#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET))) 118#define BOARD_CARD_INSERTED(SOCKET) (bcsr_read(BCSR_SIGSTAT) & (1 << (8 + (2 * SOCKET))))
226 119
227/* NAND chip select */ 120/* NAND chip select */
228#define NAND_CS 1 121#define NAND_CS 1
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
index 1a515b8c870f..cfa64297da08 100644
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ b/arch/mips/include/asm/mach-db1x00/db1x00.h
@@ -41,102 +41,10 @@
41#define SMBUS_PSC_BASE PSC2_BASE_ADDR 41#define SMBUS_PSC_BASE PSC2_BASE_ADDR
42#define I2S_PSC_BASE PSC3_BASE_ADDR 42#define I2S_PSC_BASE PSC3_BASE_ADDR
43 43
44#define BCSR_KSEG1_ADDR 0xAF000000
45#define NAND_PHYS_ADDR 0x20000000 44#define NAND_PHYS_ADDR 0x20000000
46 45
47#else
48#define BCSR_KSEG1_ADDR 0xAE000000
49#endif 46#endif
50 47
51/*
52 * Overlay data structure of the DBAu1x00 board registers.
53 * Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
54 */
55typedef volatile struct
56{
57 /*00*/ unsigned short whoami;
58 unsigned short reserved0;
59 /*04*/ unsigned short status;
60 unsigned short reserved1;
61 /*08*/ unsigned short switches;
62 unsigned short reserved2;
63 /*0C*/ unsigned short resets;
64 unsigned short reserved3;
65 /*10*/ unsigned short pcmcia;
66 unsigned short reserved4;
67 /*14*/ unsigned short specific;
68 unsigned short reserved5;
69 /*18*/ unsigned short leds;
70 unsigned short reserved6;
71 /*1C*/ unsigned short swreset;
72 unsigned short reserved7;
73
74} BCSR;
75
76
77/*
78 * Register/mask bit definitions for the BCSRs
79 */
80#define BCSR_WHOAMI_DCID 0x000F
81#define BCSR_WHOAMI_CPLD 0x00F0
82#define BCSR_WHOAMI_BOARD 0x0F00
83
84#define BCSR_STATUS_PC0VS 0x0003
85#define BCSR_STATUS_PC1VS 0x000C
86#define BCSR_STATUS_PC0FI 0x0010
87#define BCSR_STATUS_PC1FI 0x0020
88#define BCSR_STATUS_FLASHBUSY 0x0100
89#define BCSR_STATUS_ROMBUSY 0x0400
90#define BCSR_STATUS_SWAPBOOT 0x2000
91#define BCSR_STATUS_FLASHDEN 0xC000
92
93#define BCSR_SWITCHES_DIP 0x00FF
94#define BCSR_SWITCHES_DIP_1 0x0080
95#define BCSR_SWITCHES_DIP_2 0x0040
96#define BCSR_SWITCHES_DIP_3 0x0020
97#define BCSR_SWITCHES_DIP_4 0x0010
98#define BCSR_SWITCHES_DIP_5 0x0008
99#define BCSR_SWITCHES_DIP_6 0x0004
100#define BCSR_SWITCHES_DIP_7 0x0002
101#define BCSR_SWITCHES_DIP_8 0x0001
102#define BCSR_SWITCHES_ROTARY 0x0F00
103
104#define BCSR_RESETS_PHY0 0x0001
105#define BCSR_RESETS_PHY1 0x0002
106#define BCSR_RESETS_DC 0x0004
107#define BCSR_RESETS_FIR_SEL 0x2000
108#define BCSR_RESETS_IRDA_MODE_MASK 0xC000
109#define BCSR_RESETS_IRDA_MODE_FULL 0x0000
110#define BCSR_RESETS_IRDA_MODE_OFF 0x4000
111#define BCSR_RESETS_IRDA_MODE_2_3 0x8000
112#define BCSR_RESETS_IRDA_MODE_1_3 0xC000
113
114#define BCSR_PCMCIA_PC0VPP 0x0003
115#define BCSR_PCMCIA_PC0VCC 0x000C
116#define BCSR_PCMCIA_PC0DRVEN 0x0010
117#define BCSR_PCMCIA_PC0RST 0x0080
118#define BCSR_PCMCIA_PC1VPP 0x0300
119#define BCSR_PCMCIA_PC1VCC 0x0C00
120#define BCSR_PCMCIA_PC1DRVEN 0x1000
121#define BCSR_PCMCIA_PC1RST 0x8000
122
123#define BCSR_BOARD_PCIM66EN 0x0001
124#define BCSR_BOARD_SD0_PWR 0x0040
125#define BCSR_BOARD_SD1_PWR 0x0080
126#define BCSR_BOARD_PCIM33 0x0100
127#define BCSR_BOARD_GPIO200RST 0x0400
128#define BCSR_BOARD_PCICFG 0x1000
129#define BCSR_BOARD_SD0_WP 0x4000
130#define BCSR_BOARD_SD1_WP 0x8000
131
132#define BCSR_LEDS_DECIMALS 0x0003
133#define BCSR_LEDS_LED0 0x0100
134#define BCSR_LEDS_LED1 0x0200
135#define BCSR_LEDS_LED2 0x0400
136#define BCSR_LEDS_LED3 0x0800
137
138#define BCSR_SWRESET_RESET 0x0080
139
140/* PCMCIA DBAu1x00 specific defines */ 48/* PCMCIA DBAu1x00 specific defines */
141#define PCMCIA_MAX_SOCK 1 49#define PCMCIA_MAX_SOCK 1
142#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) 50#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1100.h b/arch/mips/include/asm/mach-pb1x00/pb1100.h
index b1a60f1cbd02..f2bf73a11fb2 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1100.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1100.h
@@ -26,55 +26,6 @@
26#ifndef __ASM_PB1100_H 26#ifndef __ASM_PB1100_H
27#define __ASM_PB1100_H 27#define __ASM_PB1100_H
28 28
29#define PB1100_IDENT 0xAE000000
30#define BOARD_STATUS_REG 0xAE000004
31# define PB1100_ROM_SEL (1 << 15)
32# define PB1100_ROM_SIZ (1 << 14)
33# define PB1100_SWAP_BOOT (1 << 13)
34# define PB1100_FLASH_WP (1 << 12)
35# define PB1100_ROM_H_STS (1 << 11)
36# define PB1100_ROM_L_STS (1 << 10)
37# define PB1100_FLASH_H_STS (1 << 9)
38# define PB1100_FLASH_L_STS (1 << 8)
39# define PB1100_SRAM_SIZ (1 << 7)
40# define PB1100_TSC_BUSY (1 << 6)
41# define PB1100_PCMCIA_VS_MASK (3 << 4)
42# define PB1100_RS232_CD (1 << 3)
43# define PB1100_RS232_CTS (1 << 2)
44# define PB1100_RS232_DSR (1 << 1)
45# define PB1100_RS232_RI (1 << 0)
46
47#define PB1100_IRDA_RS232 0xAE00000C
48# define PB1100_IRDA_FULL (0 << 14) /* full power */
49# define PB1100_IRDA_SHUTDOWN (1 << 14)
50# define PB1100_IRDA_TT (2 << 14) /* 2/3 power */
51# define PB1100_IRDA_OT (3 << 14) /* 1/3 power */
52# define PB1100_IRDA_FIR (1 << 13)
53
54#define PCMCIA_BOARD_REG 0xAE000010
55# define PB1100_SD_WP1_RO (1 << 15) /* read only */
56# define PB1100_SD_WP0_RO (1 << 14) /* read only */
57# define PB1100_SD_PWR1 (1 << 11) /* applies power to SD1 */
58# define PB1100_SD_PWR0 (1 << 10) /* applies power to SD0 */
59# define PB1100_SEL_SD_CONN1 (1 << 9)
60# define PB1100_SEL_SD_CONN0 (1 << 8)
61# define PC_DEASSERT_RST (1 << 7)
62# define PC_DRV_EN (1 << 4)
63
64#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
65
66#define PB1100_RST_VDDI 0xAE00001C
67# define PB1100_SOFT_RESET (1 << 15) /* clear to reset the board */
68# define PB1100_VDDI_MASK 0x1F
69
70#define PB1100_LEDS 0xAE000018
71
72/*
73 * 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
74 * 7:0 is the LED Display's decimal points.
75 */
76#define PB1100_HEX_LED 0xAE000018
77
78/* PCMCIA Pb1100 specific defines */ 29/* PCMCIA Pb1100 specific defines */
79#define PCMCIA_MAX_SOCK 0 30#define PCMCIA_MAX_SOCK 0
80#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) 31#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
index c8618df88cb5..a51512c68177 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
@@ -43,113 +43,8 @@
43 * Refer to board documentation. 43 * Refer to board documentation.
44 */ 44 */
45#define AC97_PSC_BASE PSC1_BASE_ADDR 45#define AC97_PSC_BASE PSC1_BASE_ADDR
46#define I2S_PSC_BASE PSC1_BASE_ADDR 46#define I2S_PSC_BASE PSC1_BASE_ADDR
47 47
48#define BCSR_KSEG1_ADDR 0xAD800000
49
50typedef volatile struct
51{
52 /*00*/ u16 whoami;
53 u16 reserved0;
54 /*04*/ u16 status;
55 u16 reserved1;
56 /*08*/ u16 switches;
57 u16 reserved2;
58 /*0C*/ u16 resets;
59 u16 reserved3;
60
61 /*10*/ u16 pcmcia;
62 u16 reserved4;
63 /*14*/ u16 board;
64 u16 reserved5;
65 /*18*/ u16 disk_leds;
66 u16 reserved6;
67 /*1C*/ u16 system;
68 u16 reserved7;
69
70 /*20*/ u16 intclr;
71 u16 reserved8;
72 /*24*/ u16 intset;
73 u16 reserved9;
74 /*28*/ u16 intclr_mask;
75 u16 reserved10;
76 /*2C*/ u16 intset_mask;
77 u16 reserved11;
78
79 /*30*/ u16 sig_status;
80 u16 reserved12;
81 /*34*/ u16 int_status;
82 u16 reserved13;
83 /*38*/ u16 reserved14;
84 u16 reserved15;
85 /*3C*/ u16 reserved16;
86 u16 reserved17;
87
88} BCSR;
89
90static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
91
92/*
93 * Register bit definitions for the BCSRs
94 */
95#define BCSR_WHOAMI_DCID 0x000F
96#define BCSR_WHOAMI_CPLD 0x00F0
97#define BCSR_WHOAMI_BOARD 0x0F00
98
99#define BCSR_STATUS_PCMCIA0VS 0x0003
100#define BCSR_STATUS_PCMCIA1VS 0x000C
101#define BCSR_STATUS_SWAPBOOT 0x0040
102#define BCSR_STATUS_FLASHBUSY 0x0100
103#define BCSR_STATUS_IDECBLID 0x0200
104#define BCSR_STATUS_SD0WP 0x0400
105#define BCSR_STATUS_SD1WP 0x0800
106#define BCSR_STATUS_U0RXD 0x1000
107#define BCSR_STATUS_U1RXD 0x2000
108
109#define BCSR_SWITCHES_OCTAL 0x00FF
110#define BCSR_SWITCHES_DIP_1 0x0080
111#define BCSR_SWITCHES_DIP_2 0x0040
112#define BCSR_SWITCHES_DIP_3 0x0020
113#define BCSR_SWITCHES_DIP_4 0x0010
114#define BCSR_SWITCHES_DIP_5 0x0008
115#define BCSR_SWITCHES_DIP_6 0x0004
116#define BCSR_SWITCHES_DIP_7 0x0002
117#define BCSR_SWITCHES_DIP_8 0x0001
118#define BCSR_SWITCHES_ROTARY 0x0F00
119
120#define BCSR_RESETS_ETH 0x0001
121#define BCSR_RESETS_CAMERA 0x0002
122#define BCSR_RESETS_DC 0x0004
123#define BCSR_RESETS_IDE 0x0008
124/* not resets but in the same register */
125#define BCSR_RESETS_WSCFSM 0x0800
126#define BCSR_RESETS_PCS0MUX 0x1000
127#define BCSR_RESETS_PCS1MUX 0x2000
128#define BCSR_RESETS_SPISEL 0x4000
129#define BCSR_RESETS_SD1MUX 0x8000
130
131#define BCSR_PCMCIA_PC0VPP 0x0003
132#define BCSR_PCMCIA_PC0VCC 0x000C
133#define BCSR_PCMCIA_PC0DRVEN 0x0010
134#define BCSR_PCMCIA_PC0RST 0x0080
135#define BCSR_PCMCIA_PC1VPP 0x0300
136#define BCSR_PCMCIA_PC1VCC 0x0C00
137#define BCSR_PCMCIA_PC1DRVEN 0x1000
138#define BCSR_PCMCIA_PC1RST 0x8000
139
140#define BCSR_BOARD_LCDVEE 0x0001
141#define BCSR_BOARD_LCDVDD 0x0002
142#define BCSR_BOARD_LCDBL 0x0004
143#define BCSR_BOARD_CAMSNAP 0x0010
144#define BCSR_BOARD_CAMPWR 0x0020
145#define BCSR_BOARD_SD0PWR 0x0040
146#define BCSR_BOARD_SD1PWR 0x0080
147
148#define BCSR_LEDS_DECIMALS 0x00FF
149#define BCSR_LEDS_LED0 0x0100
150#define BCSR_LEDS_LED1 0x0200
151#define BCSR_LEDS_LED2 0x0400
152#define BCSR_LEDS_LED3 0x0800
153 48
154#define BCSR_SYSTEM_VDDI 0x001F 49#define BCSR_SYSTEM_VDDI 0x001F
155#define BCSR_SYSTEM_POWEROFF 0x4000 50#define BCSR_SYSTEM_POWEROFF 0x4000
@@ -251,7 +146,7 @@ enum external_pb1200_ints {
251 146
252#define BOARD_PC0_INT PB1200_PC0_INT 147#define BOARD_PC0_INT PB1200_PC0_INT
253#define BOARD_PC1_INT PB1200_PC1_INT 148#define BOARD_PC1_INT PB1200_PC1_INT
254#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET))) 149#define BOARD_CARD_INSERTED(SOCKET) (bcsr_read(BCSR_SIGSTAT & (1 << (8 + (2 * SOCKET))))
255 150
256/* NAND chip select */ 151/* NAND chip select */
257#define NAND_CS 1 152#define NAND_CS 1
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1500.h b/arch/mips/include/asm/mach-pb1x00/pb1500.h
index da51a2eb7b82..82431a7ab942 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1500.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1500.h
@@ -26,19 +26,6 @@
26#ifndef __ASM_PB1500_H 26#ifndef __ASM_PB1500_H
27#define __ASM_PB1500_H 27#define __ASM_PB1500_H
28 28
29#define IDENT_BOARD_REG 0xAE000000
30#define BOARD_STATUS_REG 0xAE000004
31#define PCI_BOARD_REG 0xAE000010
32#define PCMCIA_BOARD_REG 0xAE000010
33# define PC_DEASSERT_RST 0x80
34# define PC_DRV_EN 0x10
35#define PB1500_G_CONTROL 0xAE000014
36#define PB1500_RST_VDDI 0xAE00001C
37#define PB1500_LEDS 0xAE000018
38
39#define PB1500_HEX_LED 0xAF000004
40#define PB1500_HEX_LED_BLANK 0xAF000008
41
42/* PCMCIA Pb1500 specific defines */ 29/* PCMCIA Pb1500 specific defines */
43#define PCMCIA_MAX_SOCK 0 30#define PCMCIA_MAX_SOCK 0
44#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) 31#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
index 6704a11497db..306d584abbd4 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -40,95 +40,6 @@
40#define SMBUS_PSC_BASE PSC2_BASE_ADDR 40#define SMBUS_PSC_BASE PSC2_BASE_ADDR
41#define I2S_PSC_BASE PSC3_BASE_ADDR 41#define I2S_PSC_BASE PSC3_BASE_ADDR
42 42
43#define BCSR_PHYS_ADDR 0xAF000000
44
45typedef volatile struct
46{
47 /*00*/ u16 whoami;
48 u16 reserved0;
49 /*04*/ u16 status;
50 u16 reserved1;
51 /*08*/ u16 switches;
52 u16 reserved2;
53 /*0C*/ u16 resets;
54 u16 reserved3;
55 /*10*/ u16 pcmcia;
56 u16 reserved4;
57 /*14*/ u16 pci;
58 u16 reserved5;
59 /*18*/ u16 leds;
60 u16 reserved6;
61 /*1C*/ u16 system;
62 u16 reserved7;
63
64} BCSR;
65
66static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
67
68/*
69 * Register bit definitions for the BCSRs
70 */
71#define BCSR_WHOAMI_DCID 0x000F
72#define BCSR_WHOAMI_CPLD 0x00F0
73#define BCSR_WHOAMI_BOARD 0x0F00
74
75#define BCSR_STATUS_PCMCIA0VS 0x0003
76#define BCSR_STATUS_PCMCIA1VS 0x000C
77#define BCSR_STATUS_PCMCIA0FI 0x0010
78#define BCSR_STATUS_PCMCIA1FI 0x0020
79#define BCSR_STATUS_SWAPBOOT 0x0040
80#define BCSR_STATUS_SRAMWIDTH 0x0080
81#define BCSR_STATUS_FLASHBUSY 0x0100
82#define BCSR_STATUS_ROMBUSY 0x0200
83#define BCSR_STATUS_USBOTGID 0x0800
84#define BCSR_STATUS_U0RXD 0x1000
85#define BCSR_STATUS_U1RXD 0x2000
86#define BCSR_STATUS_U3RXD 0x8000
87
88#define BCSR_SWITCHES_OCTAL 0x00FF
89#define BCSR_SWITCHES_DIP_1 0x0080
90#define BCSR_SWITCHES_DIP_2 0x0040
91#define BCSR_SWITCHES_DIP_3 0x0020
92#define BCSR_SWITCHES_DIP_4 0x0010
93#define BCSR_SWITCHES_DIP_5 0x0008
94#define BCSR_SWITCHES_DIP_6 0x0004
95#define BCSR_SWITCHES_DIP_7 0x0002
96#define BCSR_SWITCHES_DIP_8 0x0001
97#define BCSR_SWITCHES_ROTARY 0x0F00
98
99#define BCSR_RESETS_PHY0 0x0001
100#define BCSR_RESETS_PHY1 0x0002
101#define BCSR_RESETS_DC 0x0004
102#define BCSR_RESETS_WSC 0x2000
103#define BCSR_RESETS_SPISEL 0x4000
104#define BCSR_RESETS_DMAREQ 0x8000
105
106#define BCSR_PCMCIA_PC0VPP 0x0003
107#define BCSR_PCMCIA_PC0VCC 0x000C
108#define BCSR_PCMCIA_PC0DRVEN 0x0010
109#define BCSR_PCMCIA_PC0RST 0x0080
110#define BCSR_PCMCIA_PC1VPP 0x0300
111#define BCSR_PCMCIA_PC1VCC 0x0C00
112#define BCSR_PCMCIA_PC1DRVEN 0x1000
113#define BCSR_PCMCIA_PC1RST 0x8000
114
115#define BCSR_PCI_M66EN 0x0001
116#define BCSR_PCI_M33 0x0100
117#define BCSR_PCI_EXTERNARB 0x0200
118#define BCSR_PCI_GPIO200RST 0x0400
119#define BCSR_PCI_CLKOUT 0x0800
120#define BCSR_PCI_CFGHOST 0x1000
121
122#define BCSR_LEDS_DECIMALS 0x00FF
123#define BCSR_LEDS_LED0 0x0100
124#define BCSR_LEDS_LED1 0x0200
125#define BCSR_LEDS_LED2 0x0400
126#define BCSR_LEDS_LED3 0x0800
127
128#define BCSR_SYSTEM_VDDI 0x001F
129#define BCSR_SYSTEM_POWEROFF 0x4000
130#define BCSR_SYSTEM_RESET 0x8000
131
132#define PCMCIA_MAX_SOCK 1 43#define PCMCIA_MAX_SOCK 1
133#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) 44#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
134 45
diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c
index 92c334ff4508..43d46e424040 100644
--- a/drivers/mtd/nand/au1550nd.c
+++ b/drivers/mtd/nand/au1550nd.c
@@ -19,6 +19,7 @@
19#include <asm/io.h> 19#include <asm/io.h>
20 20
21#include <asm/mach-au1x00/au1xxx.h> 21#include <asm/mach-au1x00/au1xxx.h>
22#include <asm/mach-db1x00/bcsr.h>
22 23
23/* 24/*
24 * MTD structure for NAND controller 25 * MTD structure for NAND controller
@@ -475,7 +476,8 @@ static int __init au1xxx_nand_init(void)
475 /* set gpio206 high */ 476 /* set gpio206 high */
476 au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR); 477 au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR);
477 478
478 boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr->status >> 6) & 0x1); 479 boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
480
479 switch (boot_swapboot) { 481 switch (boot_swapboot) {
480 case 0: 482 case 0:
481 case 2: 483 case 2:
diff --git a/drivers/net/irda/au1k_ir.c b/drivers/net/irda/au1k_ir.c
index 9b2eebdbb25b..b5cbd39d0685 100644
--- a/drivers/net/irda/au1k_ir.c
+++ b/drivers/net/irda/au1k_ir.c
@@ -36,6 +36,7 @@
36#include <asm/pb1000.h> 36#include <asm/pb1000.h>
37#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) 37#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100)
38#include <asm/db1x00.h> 38#include <asm/db1x00.h>
39#include <asm/mach-db1x00/bcsr.h>
39#else 40#else
40#error au1k_ir: unsupported board 41#error au1k_ir: unsupported board
41#endif 42#endif
@@ -66,10 +67,6 @@ static char version[] __devinitdata =
66 67
67#define RUN_AT(x) (jiffies + (x)) 68#define RUN_AT(x) (jiffies + (x))
68 69
69#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100)
70static BCSR * const bcsr = (BCSR *)0xAE000000;
71#endif
72
73static DEFINE_SPINLOCK(ir_lock); 70static DEFINE_SPINLOCK(ir_lock);
74 71
75/* 72/*
@@ -282,9 +279,8 @@ static int au1k_irda_net_init(struct net_device *dev)
282 279
283#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) 280#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100)
284 /* power on */ 281 /* power on */
285 bcsr->resets &= ~BCSR_RESETS_IRDA_MODE_MASK; 282 bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
286 bcsr->resets |= BCSR_RESETS_IRDA_MODE_FULL; 283 BCSR_RESETS_IRDA_MODE_FULL);
287 au_sync();
288#endif 284#endif
289 285
290 return 0; 286 return 0;
@@ -720,14 +716,14 @@ au1k_irda_set_speed(struct net_device *dev, int speed)
720 716
721 if (speed == 4000000) { 717 if (speed == 4000000) {
722#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) 718#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100)
723 bcsr->resets |= BCSR_RESETS_FIR_SEL; 719 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_FIR_SEL);
724#else /* Pb1000 and Pb1100 */ 720#else /* Pb1000 and Pb1100 */
725 writel(1<<13, CPLD_AUX1); 721 writel(1<<13, CPLD_AUX1);
726#endif 722#endif
727 } 723 }
728 else { 724 else {
729#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) 725#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100)
730 bcsr->resets &= ~BCSR_RESETS_FIR_SEL; 726 bcsr_mod(BCSR_RESETS, BCSR_RESETS_FIR_SEL, 0);
731#else /* Pb1000 and Pb1100 */ 727#else /* Pb1000 and Pb1100 */
732 writel(readl(CPLD_AUX1) & ~(1<<13), CPLD_AUX1); 728 writel(readl(CPLD_AUX1) & ~(1<<13), CPLD_AUX1);
733#endif 729#endif
diff --git a/drivers/pcmcia/au1000_db1x00.c b/drivers/pcmcia/au1000_db1x00.c
index c78d77fd7e3b..3fdd664e41c6 100644
--- a/drivers/pcmcia/au1000_db1x00.c
+++ b/drivers/pcmcia/au1000_db1x00.c
@@ -47,9 +47,9 @@
47 #include <pb1200.h> 47 #include <pb1200.h>
48#else 48#else
49 #include <asm/mach-db1x00/db1x00.h> 49 #include <asm/mach-db1x00/db1x00.h>
50 static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
51#endif 50#endif
52 51
52#include <asm/mach-db1x00/bcsr.h>
53#include "au1000_generic.h" 53#include "au1000_generic.h"
54 54
55#if 0 55#if 0
@@ -76,8 +76,8 @@ static int db1x00_pcmcia_hw_init(struct au1000_pcmcia_socket *skt)
76 76
77static void db1x00_pcmcia_shutdown(struct au1000_pcmcia_socket *skt) 77static void db1x00_pcmcia_shutdown(struct au1000_pcmcia_socket *skt)
78{ 78{
79 bcsr->pcmcia = 0; /* turn off power */ 79 bcsr_write(BCSR_PCMCIA, 0); /* turn off power */
80 au_sync_delay(2); 80 msleep(2);
81} 81}
82 82
83static void 83static void
@@ -93,19 +93,19 @@ db1x00_pcmcia_socket_state(struct au1000_pcmcia_socket *skt, struct pcmcia_state
93 93
94 switch (skt->nr) { 94 switch (skt->nr) {
95 case 0: 95 case 0:
96 vs = bcsr->status & 0x3; 96 vs = bcsr_read(BCSR_STATUS) & 0x3;
97#if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200) 97#if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200)
98 inserted = BOARD_CARD_INSERTED(0); 98 inserted = BOARD_CARD_INSERTED(0);
99#else 99#else
100 inserted = !(bcsr->status & (1<<4)); 100 inserted = !(bcsr_read(BCSR_STATUS) & (1 << 4));
101#endif 101#endif
102 break; 102 break;
103 case 1: 103 case 1:
104 vs = (bcsr->status & 0xC)>>2; 104 vs = (bcsr_read(BCSR_STATUS) & 0xC) >> 2;
105#if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200) 105#if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200)
106 inserted = BOARD_CARD_INSERTED(1); 106 inserted = BOARD_CARD_INSERTED(1);
107#else 107#else
108 inserted = !(bcsr->status & (1<<5)); 108 inserted = !(bcsr_read(BCSR_STATUS) & (1<<5));
109#endif 109#endif
110 break; 110 break;
111 default:/* should never happen */ 111 default:/* should never happen */
@@ -114,7 +114,7 @@ db1x00_pcmcia_socket_state(struct au1000_pcmcia_socket *skt, struct pcmcia_state
114 114
115 if (inserted) 115 if (inserted)
116 debug("db1x00 socket %d: inserted %d, vs %d pcmcia %x\n", 116 debug("db1x00 socket %d: inserted %d, vs %d pcmcia %x\n",
117 skt->nr, inserted, vs, bcsr->pcmcia); 117 skt->nr, inserted, vs, bcsr_read(BCSR_PCMCIA));
118 118
119 if (inserted) { 119 if (inserted) {
120 switch (vs) { 120 switch (vs) {
@@ -136,19 +136,21 @@ db1x00_pcmcia_socket_state(struct au1000_pcmcia_socket *skt, struct pcmcia_state
136 /* if the card was previously inserted and then ejected, 136 /* if the card was previously inserted and then ejected,
137 * we should turn off power to it 137 * we should turn off power to it
138 */ 138 */
139 if ((skt->nr == 0) && (bcsr->pcmcia & BCSR_PCMCIA_PC0RST)) { 139 if ((skt->nr == 0) &&
140 bcsr->pcmcia &= ~(BCSR_PCMCIA_PC0RST | 140 (bcsr_read(BCSR_PCMCIA) & BCSR_PCMCIA_PC0RST)) {
141 BCSR_PCMCIA_PC0DRVEN | 141 bcsr_mod(BCSR_PCMCIA, BCSR_PCMCIA_PC0RST |
142 BCSR_PCMCIA_PC0VPP | 142 BCSR_PCMCIA_PC0DRVEN |
143 BCSR_PCMCIA_PC0VCC); 143 BCSR_PCMCIA_PC0VPP |
144 au_sync_delay(10); 144 BCSR_PCMCIA_PC0VCC, 0);
145 msleep(10);
145 } 146 }
146 else if ((skt->nr == 1) && bcsr->pcmcia & BCSR_PCMCIA_PC1RST) { 147 else if ((skt->nr == 1) &&
147 bcsr->pcmcia &= ~(BCSR_PCMCIA_PC1RST | 148 (bcsr_read(BCSR_PCMCIA) & BCSR_PCMCIA_PC1RST)) {
148 BCSR_PCMCIA_PC1DRVEN | 149 bcsr_mod(BCSR_PCMCIA, BCSR_PCMCIA_PC1RST |
149 BCSR_PCMCIA_PC1VPP | 150 BCSR_PCMCIA_PC1DRVEN |
150 BCSR_PCMCIA_PC1VCC); 151 BCSR_PCMCIA_PC1VPP |
151 au_sync_delay(10); 152 BCSR_PCMCIA_PC1VCC, 0);
153 msleep(10);
152 } 154 }
153 } 155 }
154 156
@@ -171,7 +173,7 @@ db1x00_pcmcia_configure_socket(struct au1000_pcmcia_socket *skt, struct socket_s
171 * initializing a socket not to wipe out the settings of the 173 * initializing a socket not to wipe out the settings of the
172 * other socket. 174 * other socket.
173 */ 175 */
174 pwr = bcsr->pcmcia; 176 pwr = bcsr_read(BCSR_PCMCIA);
175 pwr &= ~(0xf << sock*8); /* clear voltage settings */ 177 pwr &= ~(0xf << sock*8); /* clear voltage settings */
176 178
177 state->Vpp = 0; 179 state->Vpp = 0;
@@ -228,37 +230,37 @@ db1x00_pcmcia_configure_socket(struct au1000_pcmcia_socket *skt, struct socket_s
228 break; 230 break;
229 } 231 }
230 232
231 bcsr->pcmcia = pwr; 233 bcsr_write(BCSR_PCMCIA, pwr);
232 au_sync_delay(300); 234 msleep(300);
233 235
234 if (sock == 0) { 236 if (sock == 0) {
235 if (!(state->flags & SS_RESET)) { 237 if (!(state->flags & SS_RESET)) {
236 pwr |= BCSR_PCMCIA_PC0DRVEN; 238 pwr |= BCSR_PCMCIA_PC0DRVEN;
237 bcsr->pcmcia = pwr; 239 bcsr_write(BCSR_PCMCIA, pwr);
238 au_sync_delay(300); 240 msleep(300);
239 pwr |= BCSR_PCMCIA_PC0RST; 241 pwr |= BCSR_PCMCIA_PC0RST;
240 bcsr->pcmcia = pwr; 242 bcsr_write(BCSR_PCMCIA, pwr);
241 au_sync_delay(100); 243 msleep(100);
242 } 244 }
243 else { 245 else {
244 pwr &= ~(BCSR_PCMCIA_PC0RST | BCSR_PCMCIA_PC0DRVEN); 246 pwr &= ~(BCSR_PCMCIA_PC0RST | BCSR_PCMCIA_PC0DRVEN);
245 bcsr->pcmcia = pwr; 247 bcsr_write(BCSR_PCMCIA, pwr);
246 au_sync_delay(100); 248 msleep(100);
247 } 249 }
248 } 250 }
249 else { 251 else {
250 if (!(state->flags & SS_RESET)) { 252 if (!(state->flags & SS_RESET)) {
251 pwr |= BCSR_PCMCIA_PC1DRVEN; 253 pwr |= BCSR_PCMCIA_PC1DRVEN;
252 bcsr->pcmcia = pwr; 254 bcsr_write(BCSR_PCMCIA, pwr);
253 au_sync_delay(300); 255 msleep(300);
254 pwr |= BCSR_PCMCIA_PC1RST; 256 pwr |= BCSR_PCMCIA_PC1RST;
255 bcsr->pcmcia = pwr; 257 bcsr_write(BCSR_PCMCIA, pwr);
256 au_sync_delay(100); 258 msleep(100);
257 } 259 }
258 else { 260 else {
259 pwr &= ~(BCSR_PCMCIA_PC1RST | BCSR_PCMCIA_PC1DRVEN); 261 pwr &= ~(BCSR_PCMCIA_PC1RST | BCSR_PCMCIA_PC1DRVEN);
260 bcsr->pcmcia = pwr; 262 bcsr_write(BCSR_PCMCIA, pwr);
261 au_sync_delay(100); 263 msleep(100);
262 } 264 }
263 } 265 }
264 return 0; 266 return 0;
@@ -298,8 +300,8 @@ struct pcmcia_low_level db1x00_pcmcia_ops = {
298int au1x_board_init(struct device *dev) 300int au1x_board_init(struct device *dev)
299{ 301{
300 int ret = -ENODEV; 302 int ret = -ENODEV;
301 bcsr->pcmcia = 0; /* turn off power, if it's not already off */ 303 bcsr_write(BCSR_PCMCIA, 0); /* turn off power, if it's not already off */
302 au_sync_delay(2); 304 msleep(2);
303 ret = au1x00_pcmcia_socket_probe(dev, &db1x00_pcmcia_ops, 0, 2); 305 ret = au1x00_pcmcia_socket_probe(dev, &db1x00_pcmcia_ops, 0, 2);
304 return ret; 306 return ret;
305} 307}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 05:20:28 -0400