3 files changed, 26 insertions, 6 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7570c3bc5e2d..0866ac3d0a3f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -242,8 +242,12 @@
  */
 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
 #define MI_FLUSH_DW             MI_INSTR(0x26, 1) /* for GEN6 */
-#define   MI_INVALIDATE_TLB     (1<<18)
-#define   MI_INVALIDATE_BSD     (1<<7)
+#define   MI_FLUSH_DW_STORE_INDEX       (1<<21)
+#define   MI_INVALIDATE_TLB             (1<<18)
+#define   MI_FLUSH_DW_OP_STOREDW        (1<<14)
+#define   MI_INVALIDATE_BSD             (1<<7)
+#define   MI_FLUSH_DW_USE_GTT           (1<<2)
+#define   MI_FLUSH_DW_USE_PPGTT         (0<<2)
 #define MI_BATCH_BUFFER         MI_INSTR(0x30, 1)
 #define   MI_BATCH_NON_SECURE           (1)
 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b13393b593b8..1591955044c8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1395,10 +1395,17 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
                 return ret;
 
         cmd = MI_FLUSH_DW;
+        /*
+         * Bspec vol 1c.5 - video engine command streamer:
+         * "If ENABLED, all TLBs will be invalidated once the flush
+         * operation is complete. This bit is only valid when the
+         * Post-Sync Operation field is a value of 1h or 3h."
+         */
         if (invalidate & I915_GEM_GPU_DOMAINS)
-                cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
+                cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
+                        MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
         intel_ring_emit(ring, cmd);
-        intel_ring_emit(ring, 0);
+        intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
         intel_ring_emit(ring, 0);
         intel_ring_emit(ring, MI_NOOP);
         intel_ring_advance(ring);
@@ -1460,10 +1467,17 @@ static int blt_ring_flush(struct intel_ring_buffer *ring,
                 return ret;
 
         cmd = MI_FLUSH_DW;
+        /*
+         * Bspec vol 1c.3 - blitter engine command streamer:
+         * "If ENABLED, all TLBs will be invalidated once the flush
+         * operation is complete. This bit is only valid when the
+         * Post-Sync Operation field is a value of 1h or 3h."
+         */
         if (invalidate & I915_GEM_DOMAIN_RENDER)
-                cmd |= MI_INVALIDATE_TLB;
+                cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
+                        MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_OP_STOREDW;
         intel_ring_emit(ring, cmd);
-        intel_ring_emit(ring, 0);
+        intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
         intel_ring_emit(ring, 0);
         intel_ring_emit(ring, MI_NOOP);
         intel_ring_advance(ring);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 3745d1dc1fa1..5af65b89765f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -183,6 +183,8 @@ intel_read_status_page(struct intel_ring_buffer *ring,
  * The area from dword 0x20 to 0x3ff is available for driver usage.
  */
 #define I915_GEM_HWS_INDEX              0x20
+#define I915_GEM_HWS_SCRATCH_INDEX      0x30
+#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
 
 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);