2 files changed, 15 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
index 111b1f5021b9..7634cc1c9436 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
@@ -144,6 +144,10 @@
         status = "okay";
 };
 
+&pcie {
+        status = "okay";
+};
+
 &ssi2 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 8d718b55a07f..2d721095a369 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -283,6 +283,10 @@
                         >;
                 };
 
+                pinctrl_pcie: pciegrp {
+                        fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000>;
+                };
+
                 pinctrl_uart3: uart3grp {
                         fsl,pins = <
                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
@@ -353,6 +357,13 @@
         };
 };
 
+&pcie {
+        pinctrl-name = "default";
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio4 17 0>;
+        status = "disabled";
+};
+
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3>;