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-rw-r--r--arch/arm/mach-stmp378x/stmp378x.c109
-rw-r--r--arch/arm/mach-stmp37xx/stmp37xx.c84
-rw-r--r--arch/arm/plat-stmp3xxx/clock.c167
-rw-r--r--arch/arm/plat-stmp3xxx/core.c3
-rw-r--r--arch/arm/plat-stmp3xxx/dma.c137
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/dma.h16
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/pinmux.h7
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/platform.h21
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h195
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/system.h8
-rw-r--r--arch/arm/plat-stmp3xxx/irq.c22
-rw-r--r--arch/arm/plat-stmp3xxx/pinmux.c163
-rw-r--r--arch/arm/plat-stmp3xxx/timer.c111
13 files changed, 462 insertions, 581 deletions
diff --git a/arch/arm/mach-stmp378x/stmp378x.c b/arch/arm/mach-stmp378x/stmp378x.c
index f156ec7306c0..9a363fb2acf3 100644
--- a/arch/arm/mach-stmp378x/stmp378x.c
+++ b/arch/arm/mach-stmp378x/stmp378x.c
@@ -47,25 +47,28 @@
47static void stmp378x_ack_irq(unsigned int irq) 47static void stmp378x_ack_irq(unsigned int irq)
48{ 48{
49 /* Tell ICOLL to release IRQ line */ 49 /* Tell ICOLL to release IRQ line */
50 HW_ICOLL_VECTOR_WR(0x0); 50 __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
51 51
52 /* ACK current interrupt */ 52 /* ACK current interrupt */
53 HW_ICOLL_LEVELACK_WR(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0); 53 __raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */,
54 REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
54 55
55 /* Barrier */ 56 /* Barrier */
56 (void) HW_ICOLL_STAT_RD(); 57 (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
57} 58}
58 59
59static void stmp378x_mask_irq(unsigned int irq) 60static void stmp378x_mask_irq(unsigned int irq)
60{ 61{
61 /* IRQ disable */ 62 /* IRQ disable */
62 HW_ICOLL_INTERRUPTn_CLR(irq, BM_ICOLL_INTERRUPTn_ENABLE); 63 stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE,
64 REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
63} 65}
64 66
65static void stmp378x_unmask_irq(unsigned int irq) 67static void stmp378x_unmask_irq(unsigned int irq)
66{ 68{
67 /* IRQ enable */ 69 /* IRQ enable */
68 HW_ICOLL_INTERRUPTn_SET(irq, BM_ICOLL_INTERRUPTn_ENABLE); 70 stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE,
71 REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
69} 72}
70 73
71static struct irq_chip stmp378x_chip = { 74static struct irq_chip stmp378x_chip = {
@@ -84,52 +87,63 @@ void __init stmp378x_init_irq(void)
84 */ 87 */
85void stmp3xxx_arch_dma_enable_interrupt(int channel) 88void stmp3xxx_arch_dma_enable_interrupt(int channel)
86{ 89{
87 int dmabus = channel / 16; 90 void __iomem *c1, *c2;
88 91
89 switch (dmabus) { 92 switch (STMP3XXX_DMA_BUS(channel)) {
90 case STMP3XXX_BUS_APBH: 93 case STMP3XXX_BUS_APBH:
91 HW_APBH_CTRL1_SET(1 << (16 + (channel % 16))); 94 c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
92 HW_APBH_CTRL2_SET(1 << (16 + (channel % 16))); 95 c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
93 break; 96 break;
94 97
95 case STMP3XXX_BUS_APBX: 98 case STMP3XXX_BUS_APBX:
96 HW_APBX_CTRL1_SET(1 << (16 + (channel % 16))); 99 c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
97 HW_APBX_CTRL2_SET(1 << (16 + (channel % 16))); 100 c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
98 break; 101 break;
102
103 default:
104 return;
99 } 105 }
106 stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1);
107 stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2);
100} 108}
101EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt); 109EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
102 110
103void stmp3xxx_arch_dma_clear_interrupt(int channel) 111void stmp3xxx_arch_dma_clear_interrupt(int channel)
104{ 112{
105 int dmabus = channel / 16; 113 void __iomem *c1, *c2;
106 114
107 switch (dmabus) { 115 switch (STMP3XXX_DMA_BUS(channel)) {
108 case STMP3XXX_BUS_APBH: 116 case STMP3XXX_BUS_APBH:
109 HW_APBH_CTRL1_CLR(1 << (channel % 16)); 117 c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
110 HW_APBH_CTRL2_CLR(1 << (channel % 16)); 118 c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
111 break; 119 break;
112 120
113 case STMP3XXX_BUS_APBX: 121 case STMP3XXX_BUS_APBX:
114 HW_APBX_CTRL1_CLR(1 << (channel % 16)); 122 c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
115 HW_APBX_CTRL2_CLR(1 << (channel % 16)); 123 c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
116 break; 124 break;
125
126 default:
127 return;
117 } 128 }
129 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1);
130 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2);
118} 131}
119EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt); 132EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
120 133
121int stmp3xxx_arch_dma_is_interrupt(int channel) 134int stmp3xxx_arch_dma_is_interrupt(int channel)
122{ 135{
123 int dmabus = channel / 16;
124 int r = 0; 136 int r = 0;
125 137
126 switch (dmabus) { 138 switch (STMP3XXX_DMA_BUS(channel)) {
127 case STMP3XXX_BUS_APBH: 139 case STMP3XXX_BUS_APBH:
128 r = HW_APBH_CTRL1_RD() & (1 << (channel % 16)); 140 r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
141 (1 << STMP3XXX_DMA_CHANNEL(channel));
129 break; 142 break;
130 143
131 case STMP3XXX_BUS_APBX: 144 case STMP3XXX_BUS_APBX:
132 r = HW_APBX_CTRL1_RD() & (1 << (channel % 16)); 145 r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) &
146 (1 << STMP3XXX_DMA_CHANNEL(channel));
133 break; 147 break;
134 } 148 }
135 return r; 149 return r;
@@ -138,42 +152,41 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
138 152
139void stmp3xxx_arch_dma_reset_channel(int channel) 153void stmp3xxx_arch_dma_reset_channel(int channel)
140{ 154{
141 int dmabus = channel / 16; 155 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
142 unsigned chbit = 1 << (channel % 16); 156 void __iomem *c0;
157 u32 mask;
143 158
144 switch (dmabus) { 159 switch (STMP3XXX_DMA_BUS(channel)) {
145 case STMP3XXX_BUS_APBH: 160 case STMP3XXX_BUS_APBH:
146 /* Reset channel and wait for it to complete */ 161 c0 = REGS_APBH_BASE + HW_APBH_CTRL0;
147 HW_APBH_CTRL0_SET(chbit << 162 mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL;
148 BP_APBH_CTRL0_RESET_CHANNEL);
149 while (HW_APBH_CTRL0_RD() &
150 (chbit << BP_APBH_CTRL0_RESET_CHANNEL))
151 continue;
152 break; 163 break;
153
154 case STMP3XXX_BUS_APBX: 164 case STMP3XXX_BUS_APBX:
155 /* Reset channel and wait for it to complete */ 165 c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL;
156 HW_APBX_CHANNEL_CTRL_SET( 166 mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL;
157 BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit));
158 while (HW_APBX_CHANNEL_CTRL_RD() &
159 BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit))
160 continue;
161 break; 167 break;
168 default:
169 return;
162 } 170 }
171
172 /* Reset channel and wait for it to complete */
173 stmp3xxx_setl(mask, c0);
174 while (__raw_readl(c0) & mask)
175 cpu_relax();
163} 176}
164EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel); 177EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
165 178
166void stmp3xxx_arch_dma_freeze(int channel) 179void stmp3xxx_arch_dma_freeze(int channel)
167{ 180{
168 int dmabus = channel / 16; 181 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
169 unsigned chbit = 1 << (channel % 16); 182 u32 mask = 1 << chbit;
170 183
171 switch (dmabus) { 184 switch (STMP3XXX_DMA_BUS(channel)) {
172 case STMP3XXX_BUS_APBH: 185 case STMP3XXX_BUS_APBH:
173 HW_APBH_CTRL0_SET(1<<chbit); 186 stmp3xxx_setl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
174 break; 187 break;
175 case STMP3XXX_BUS_APBX: 188 case STMP3XXX_BUS_APBX:
176 HW_APBX_CHANNEL_CTRL_SET(1<<chbit); 189 stmp3xxx_setl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
177 break; 190 break;
178 } 191 }
179} 192}
@@ -181,15 +194,15 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
181 194
182void stmp3xxx_arch_dma_unfreeze(int channel) 195void stmp3xxx_arch_dma_unfreeze(int channel)
183{ 196{
184 int dmabus = channel / 16; 197 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
185 unsigned chbit = 1 << (channel % 16); 198 u32 mask = 1 << chbit;
186 199
187 switch (dmabus) { 200 switch (STMP3XXX_DMA_BUS(channel)) {
188 case STMP3XXX_BUS_APBH: 201 case STMP3XXX_BUS_APBH:
189 HW_APBH_CTRL0_CLR(1<<chbit); 202 stmp3xxx_clearl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
190 break; 203 break;
191 case STMP3XXX_BUS_APBX: 204 case STMP3XXX_BUS_APBX:
192 HW_APBX_CHANNEL_CTRL_CLR(1<<chbit); 205 stmp3xxx_clearl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
193 break; 206 break;
194 } 207 }
195} 208}
@@ -201,7 +214,7 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
201 * 214 *
202 * Logical Physical 215 * Logical Physical
203 * f0000000 80000000 On-chip registers 216 * f0000000 80000000 On-chip registers
204 * f1000000 00000000 256k on-chip SRAM 217 * f1000000 00000000 32k on-chip SRAM
205 */ 218 */
206 219
207static struct map_desc stmp378x_io_desc[] __initdata = { 220static struct map_desc stmp378x_io_desc[] __initdata = {
diff --git a/arch/arm/mach-stmp37xx/stmp37xx.c b/arch/arm/mach-stmp37xx/stmp37xx.c
index 83a41c90c252..8c7d6fb191a3 100644
--- a/arch/arm/mach-stmp37xx/stmp37xx.c
+++ b/arch/arm/mach-stmp37xx/stmp37xx.c
@@ -34,6 +34,7 @@
34#include <mach/stmp3xxx.h> 34#include <mach/stmp3xxx.h>
35#include <mach/dma.h> 35#include <mach/dma.h>
36 36
37#include <mach/platform.h>
37#include <mach/regs-icoll.h> 38#include <mach/regs-icoll.h>
38#include <mach/regs-apbh.h> 39#include <mach/regs-apbh.h>
39#include <mach/regs-apbx.h> 40#include <mach/regs-apbx.h>
@@ -45,25 +46,28 @@
45static void stmp37xx_ack_irq(unsigned int irq) 46static void stmp37xx_ack_irq(unsigned int irq)
46{ 47{
47 /* Disable IRQ */ 48 /* Disable IRQ */
48 HW_ICOLL_PRIORITYn_CLR(irq / 4, 0x04 << ((irq % 4) * 8)); 49 stmp3xxx_clearl(0x04 << ((irq % 4) * 8),
50 REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
49 51
50 /* ACK current interrupt */ 52 /* ACK current interrupt */
51 HW_ICOLL_LEVELACK_WR(1); 53 __raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
52 54
53 /* Barrier */ 55 /* Barrier */
54 (void) HW_ICOLL_STAT_RD(); 56 (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
55} 57}
56 58
57static void stmp37xx_mask_irq(unsigned int irq) 59static void stmp37xx_mask_irq(unsigned int irq)
58{ 60{
59 /* IRQ disable */ 61 /* IRQ disable */
60 HW_ICOLL_PRIORITYn_CLR(irq / 4, 0x04 << ((irq % 4) * 8)); 62 stmp3xxx_clearl(0x04 << ((irq % 4) * 8),
63 REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
61} 64}
62 65
63static void stmp37xx_unmask_irq(unsigned int irq) 66static void stmp37xx_unmask_irq(unsigned int irq)
64{ 67{
65 /* IRQ enable */ 68 /* IRQ enable */
66 HW_ICOLL_PRIORITYn_SET(irq / 4, 0x04 << ((irq % 4) * 8)); 69 stmp3xxx_setl(0x04 << ((irq % 4) * 8),
70 REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
67} 71}
68 72
69static struct irq_chip stmp37xx_chip = { 73static struct irq_chip stmp37xx_chip = {
@@ -82,15 +86,15 @@ void __init stmp37xx_init_irq(void)
82 */ 86 */
83void stmp3xxx_arch_dma_enable_interrupt(int channel) 87void stmp3xxx_arch_dma_enable_interrupt(int channel)
84{ 88{
85 int dmabus = channel / 16; 89 switch (STMP3XXX_DMA_BUS(channel)) {
86
87 switch (dmabus) {
88 case STMP3XXX_BUS_APBH: 90 case STMP3XXX_BUS_APBH:
89 HW_APBH_CTRL1_SET(1 << (8 + (channel % 16))); 91 stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
92 REGS_APBH_BASE + HW_APBH_CTRL1);
90 break; 93 break;
91 94
92 case STMP3XXX_BUS_APBX: 95 case STMP3XXX_BUS_APBX:
93 HW_APBX_CTRL1_SET(1 << (8 + (channel % 16))); 96 stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
97 REGS_APBX_BASE + HW_APBX_CTRL1);
94 break; 98 break;
95 } 99 }
96} 100}
@@ -98,15 +102,15 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
98 102
99void stmp3xxx_arch_dma_clear_interrupt(int channel) 103void stmp3xxx_arch_dma_clear_interrupt(int channel)
100{ 104{
101 int dmabus = channel / 16; 105 switch (STMP3XXX_DMA_BUS(channel)) {
102
103 switch (dmabus) {
104 case STMP3XXX_BUS_APBH: 106 case STMP3XXX_BUS_APBH:
105 HW_APBH_CTRL1_CLR(1 << (channel % 16)); 107 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
108 REGS_APBH_BASE + HW_APBH_CTRL1);
106 break; 109 break;
107 110
108 case STMP3XXX_BUS_APBX: 111 case STMP3XXX_BUS_APBX:
109 HW_APBX_CTRL1_CLR(1 << (channel % 16)); 112 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
113 REGS_APBX_BASE + HW_APBX_CTRL1);
110 break; 114 break;
111 } 115 }
112} 116}
@@ -116,15 +120,15 @@ int stmp3xxx_arch_dma_is_interrupt(int channel)
116{ 120{
117 int r = 0; 121 int r = 0;
118 122
119 int dmabus = channel / 16; 123 switch (STMP3XXX_DMA_BUS(channel)) {
120
121 switch (dmabus) {
122 case STMP3XXX_BUS_APBH: 124 case STMP3XXX_BUS_APBH:
123 r = HW_APBH_CTRL1_RD() & (1 << (channel % 16)); 125 r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
126 (1 << STMP3XXX_DMA_CHANNEL(channel));
124 break; 127 break;
125 128
126 case STMP3XXX_BUS_APBX: 129 case STMP3XXX_BUS_APBX:
127 r = HW_APBX_CTRL1_RD() & (1 << (channel % 16)); 130 r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
131 (1 << STMP3XXX_DMA_CHANNEL(channel));
128 break; 132 break;
129 } 133 }
130 return r; 134 return r;
@@ -133,24 +137,24 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
133 137
134void stmp3xxx_arch_dma_reset_channel(int channel) 138void stmp3xxx_arch_dma_reset_channel(int channel)
135{ 139{
136 int dmabus = channel / 16; 140 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
137 unsigned chbit = 1 << (channel % 16);
138 141
139 switch (dmabus) { 142 switch (STMP3XXX_DMA_BUS(channel)) {
140 case STMP3XXX_BUS_APBH: 143 case STMP3XXX_BUS_APBH:
141 /* Reset channel and wait for it to complete */ 144 /* Reset channel and wait for it to complete */
142 HW_APBH_CTRL0_SET(chbit << BP_APBH_CTRL0_RESET_CHANNEL); 145 stmp3xxx_setl(chbit << BP_APBH_CTRL0_RESET_CHANNEL,
143 while (HW_APBH_CTRL0_RD() & 146 REGS_APBH_BASE + HW_APBH_CTRL0);
147 while (__raw_readl(REGS_APBH_BASE + HW_APBH_CTRL0) &
144 (chbit << BP_APBH_CTRL0_RESET_CHANNEL)) 148 (chbit << BP_APBH_CTRL0_RESET_CHANNEL))
145 continue; 149 cpu_relax();
146 break; 150 break;
147 151
148 case STMP3XXX_BUS_APBX: 152 case STMP3XXX_BUS_APBX:
149 /* Reset channel and wait for it to complete */ 153 stmp3xxx_setl(chbit << BP_APBX_CTRL0_RESET_CHANNEL,
150 HW_APBX_CTRL0_SET(chbit << BP_APBX_CTRL0_RESET_CHANNEL); 154 REGS_APBX_BASE + HW_APBX_CTRL0);
151 while (HW_APBX_CTRL0_RD() & 155 while (__raw_readl(REGS_APBX_BASE + HW_APBX_CTRL0) &
152 (chbit << BP_APBX_CTRL0_RESET_CHANNEL)) 156 (chbit << BP_APBX_CTRL0_RESET_CHANNEL))
153 continue; 157 cpu_relax();
154 break; 158 break;
155 } 159 }
156} 160}
@@ -158,15 +162,14 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
158 162
159void stmp3xxx_arch_dma_freeze(int channel) 163void stmp3xxx_arch_dma_freeze(int channel)
160{ 164{
161 int dmabus = channel / 16; 165 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
162 unsigned chbit = 1 << (channel % 16);
163 166
164 switch (dmabus) { 167 switch (STMP3XXX_DMA_BUS(channel)) {
165 case STMP3XXX_BUS_APBH: 168 case STMP3XXX_BUS_APBH:
166 HW_APBH_CTRL0_SET(1<<chbit); 169 stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
167 break; 170 break;
168 case STMP3XXX_BUS_APBX: 171 case STMP3XXX_BUS_APBX:
169 HW_APBX_CTRL0_SET(1<<chbit); 172 stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
170 break; 173 break;
171 } 174 }
172} 175}
@@ -174,15 +177,14 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
174 177
175void stmp3xxx_arch_dma_unfreeze(int channel) 178void stmp3xxx_arch_dma_unfreeze(int channel)
176{ 179{
177 int dmabus = channel / 16; 180 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
178 unsigned chbit = 1 << (channel % 16);
179 181
180 switch (dmabus) { 182 switch (STMP3XXX_DMA_BUS(channel)) {
181 case STMP3XXX_BUS_APBH: 183 case STMP3XXX_BUS_APBH:
182 HW_APBH_CTRL0_CLR(1<<chbit); 184 stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
183 break; 185 break;
184 case STMP3XXX_BUS_APBX: 186 case STMP3XXX_BUS_APBX:
185 HW_APBX_CTRL0_CLR(1<<chbit); 187 stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
186 break; 188 break;
187 } 189 }
188} 190}
@@ -194,7 +196,7 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
194 * 196 *
195 * Logical Physical 197 * Logical Physical
196 * f0000000 80000000 On-chip registers 198 * f0000000 80000000 On-chip registers
197 * f1000000 00000000 256k on-chip SRAM 199 * f1000000 00000000 32k on-chip SRAM
198 */ 200 */
199static struct map_desc stmp37xx_io_desc[] __initdata = { 201static struct map_desc stmp37xx_io_desc[] __initdata = {
200 { 202 {
diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c
index 9a1d46b470cd..5d2f19a09e44 100644
--- a/arch/arm/plat-stmp3xxx/clock.c
+++ b/arch/arm/plat-stmp3xxx/clock.c
@@ -15,6 +15,7 @@
15 * http://www.opensource.org/licenses/gpl-license.html 15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html 16 * http://www.gnu.org/copyleft/gpl.html
17 */ 17 */
18#define DEBUG
18#include <linux/kernel.h> 19#include <linux/kernel.h>
19#include <linux/module.h> 20#include <linux/module.h>
20#include <linux/init.h> 21#include <linux/init.h>
@@ -27,6 +28,7 @@
27 28
28#include <asm/mach-types.h> 29#include <asm/mach-types.h>
29#include <asm/clkdev.h> 30#include <asm/clkdev.h>
31#include <mach/platform.h>
30#include <mach/regs-clkctrl.h> 32#include <mach/regs-clkctrl.h>
31 33
32#include "clock.h" 34#include "clock.h"
@@ -187,8 +189,8 @@ static long lcdif_get_rate(struct clk *clk)
187 div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask; 189 div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
188 if (div) { 190 if (div) {
189 rate /= div; 191 rate /= div;
190 div = (HW_CLKCTRL_FRAC_RD() & BM_CLKCTRL_FRAC_PIXFRAC) >> 192 div = (__raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) &
191 BP_CLKCTRL_FRAC_PIXFRAC; 193 BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC;
192 rate /= div; 194 rate /= div;
193 } 195 }
194 clk->rate = rate; 196 clk->rate = rate;
@@ -263,15 +265,19 @@ static int lcdif_set_rate(struct clk *clk, u32 rate)
263 lowest_result / 1000, lowest_result % 1000); 265 lowest_result / 1000, lowest_result % 1000);
264 266
265 /* Program ref_pix phase fractional divider */ 267 /* Program ref_pix phase fractional divider */
266 HW_CLKCTRL_FRAC_WR((HW_CLKCTRL_FRAC_RD() & ~BM_CLKCTRL_FRAC_PIXFRAC) | 268 reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
267 BF_CLKCTRL_FRAC_PIXFRAC(lowest_fracdiv)); 269 reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC;
270 reg_val |= BF(lowest_fracdiv, CLKCTRL_FRAC_PIXFRAC);
271 __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
272
268 /* Ungate PFD */ 273 /* Ungate PFD */
269 HW_CLKCTRL_FRAC_CLR(BM_CLKCTRL_FRAC_CLKGATEPIX); 274 stmp3xxx_clearl(BM_CLKCTRL_FRAC_CLKGATEPIX,
275 REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
270 276
271 /* Program pix divider */ 277 /* Program pix divider */
272 reg_val = __raw_readl(clk->scale_reg); 278 reg_val = __raw_readl(clk->scale_reg);
273 reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE); 279 reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE);
274 reg_val |= BF_CLKCTRL_PIX_DIV(lowest_div); 280 reg_val |= BF(lowest_div, CLKCTRL_PIX_DIV);
275 __raw_writel(reg_val, clk->scale_reg); 281 __raw_writel(reg_val, clk->scale_reg);
276 282
277 /* Wait for divider update */ 283 /* Wait for divider update */
@@ -287,7 +293,9 @@ static int lcdif_set_rate(struct clk *clk, u32 rate)
287 } 293 }
288 294
289 /* Switch to ref_pix source */ 295 /* Switch to ref_pix source */
290 HW_CLKCTRL_CLKSEQ_CLR(BM_CLKCTRL_CLKSEQ_BYPASS_PIX); 296 reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
297 reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX;
298 __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
291 299
292out: 300out:
293 return ret; 301 return ret;
@@ -296,6 +304,8 @@ out:
296 304
297static int cpu_set_rate(struct clk *clk, u32 rate) 305static int cpu_set_rate(struct clk *clk, u32 rate)
298{ 306{
307 u32 reg_val;
308
299 if (rate < 24000) 309 if (rate < 24000)
300 return -EINVAL; 310 return -EINVAL;
301 else if (rate == 24000) { 311 else if (rate == 24000) {
@@ -344,7 +354,12 @@ static int cpu_set_rate(struct clk *clk, u32 rate)
344 __raw_writel(1<<7, clk->scale_reg + 8); 354 __raw_writel(1<<7, clk->scale_reg + 8);
345 /* write clkctrl_cpu */ 355 /* write clkctrl_cpu */
346 clk->saved_div = clkctrl_cpu; 356 clk->saved_div = clkctrl_cpu;
347 HW_CLKCTRL_CPU_WR((HW_CLKCTRL_CPU_RD() & ~0x3f) | clkctrl_cpu); 357
358 reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
359 reg_val &= ~0x3F;
360 reg_val |= clkctrl_cpu;
361 __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
362
348 for (i = 10000; i; i--) 363 for (i = 10000; i; i--)
349 if (!clk_is_busy(clk)) 364 if (!clk_is_busy(clk))
350 break; 365 break;
@@ -364,7 +379,7 @@ static long cpu_get_rate(struct clk *clk)
364 long rate = clk->parent->rate * 18; 379 long rate = clk->parent->rate * 18;
365 380
366 rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f; 381 rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
367 rate /= HW_CLKCTRL_CPU_RD() & 0x3f; 382 rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) & 0x3f;
368 rate = ((rate + 9) / 10) * 10; 383 rate = ((rate + 9) / 10) * 10;
369 clk->rate = rate; 384 clk->rate = rate;
370 385
@@ -411,7 +426,7 @@ static long emi_get_rate(struct clk *clk)
411 long rate = clk->parent->rate * 18; 426 long rate = clk->parent->rate * 18;
412 427
413 rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f; 428 rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
414 rate /= HW_CLKCTRL_EMI_RD() & 0x3f; 429 rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) & 0x3f;
415 clk->rate = rate; 430 clk->rate = rate;
416 431
417 return rate; 432 return rate;
@@ -427,44 +442,52 @@ static int clkseq_set_parent(struct clk *clk, struct clk *parent)
427 shift = 4; 442 shift = 4;
428 443
429 if (clk->bypass_reg) { 444 if (clk->bypass_reg) {
430 u32 hbus_mask = BM_CLKCTRL_HBUS_DIV_FRAC_EN | 445#ifdef CONFIG_ARCH_STMP378X
431 BM_CLKCTRL_HBUS_DIV; 446 u32 hbus_val, cpu_val;
432 447
433 if (clk == &cpu_clk && shift == 4) { 448 if (clk == &cpu_clk && shift == 4) {
434 u32 hbus_val = HW_CLKCTRL_HBUS_RD(); 449 hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
435 u32 cpu_val = HW_CLKCTRL_CPU_RD(); 450 HW_CLKCTRL_HBUS);
436 hbus_val &= ~hbus_mask; 451 cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
437 hbus_val |= 1; 452 HW_CLKCTRL_CPU);
453
454 hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
455 BM_CLKCTRL_HBUS_DIV);
438 clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU; 456 clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU;
439 cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; 457 cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
440 cpu_val |= 1; 458 cpu_val |= 1;
441 __raw_writel(1 << clk->bypass_shift, 459
442 clk->bypass_reg + shift);
443 if (machine_is_stmp378x()) { 460 if (machine_is_stmp378x()) {
444 HW_CLKCTRL_HBUS_WR(hbus_val); 461 __raw_writel(hbus_val,
445 HW_CLKCTRL_CPU_WR(cpu_val); 462 REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
463 __raw_writel(cpu_val,
464 REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
446 hclk.rate = 0; 465 hclk.rate = 0;
447 } 466 }
448 } else if (clk == &cpu_clk && shift == 8) { 467 } else if (clk == &cpu_clk && shift == 8) {
449 u32 hbus_val = HW_CLKCTRL_HBUS_RD(); 468 hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
450 u32 cpu_val = HW_CLKCTRL_CPU_RD(); 469 HW_CLKCTRL_HBUS);
451 hbus_val &= ~hbus_mask; 470 cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
471 HW_CLKCTRL_CPU);
472 hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
473 BM_CLKCTRL_HBUS_DIV);
452 hbus_val |= 2; 474 hbus_val |= 2;
453 cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; 475 cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
454 if (clk->saved_div) 476 if (clk->saved_div)
455 cpu_val |= clk->saved_div; 477 cpu_val |= clk->saved_div;
456 else 478 else
457 cpu_val |= 2; 479 cpu_val |= 2;
480
458 if (machine_is_stmp378x()) { 481 if (machine_is_stmp378x()) {
459 HW_CLKCTRL_HBUS_WR(hbus_val); 482 __raw_writel(hbus_val,
460 HW_CLKCTRL_CPU_WR(cpu_val); 483 REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
484 __raw_writel(cpu_val,
485 REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
461 hclk.rate = 0; 486 hclk.rate = 0;
462 } 487 }
463 __raw_writel(1 << clk->bypass_shift, 488 }
464 clk->bypass_reg + shift); 489#endif
465 } else 490 __raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift);
466 __raw_writel(1 << clk->bypass_shift,
467 clk->bypass_reg + shift);
468 491
469 ret = 0; 492 ret = 0;
470 } 493 }
@@ -640,7 +663,7 @@ static struct clk osc_24M = {
640 663
641static struct clk pll_clk = { 664static struct clk pll_clk = {
642 .parent = &osc_24M, 665 .parent = &osc_24M,
643 .enable_reg = HW_CLKCTRL_PLLCTRL0_ADDR, 666 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
644 .enable_shift = 16, 667 .enable_shift = 16,
645 .enable_wait = 10, 668 .enable_wait = 10,
646 .flags = FIXED_RATE | ENABLED, 669 .flags = FIXED_RATE | ENABLED,
@@ -650,11 +673,11 @@ static struct clk pll_clk = {
650 673
651static struct clk cpu_clk = { 674static struct clk cpu_clk = {
652 .parent = &pll_clk, 675 .parent = &pll_clk,
653 .scale_reg = HW_CLKCTRL_FRAC_ADDR, 676 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
654 .scale_shift = 0, 677 .scale_shift = 0,
655 .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, 678 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
656 .bypass_shift = 7, 679 .bypass_shift = 7,
657 .busy_reg = HW_CLKCTRL_CPU_ADDR, 680 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU,
658 .busy_bit = 28, 681 .busy_bit = 28,
659 .flags = RATE_PROPAGATES | ENABLED, 682 .flags = RATE_PROPAGATES | ENABLED,
660 .ops = &cpu_ops, 683 .ops = &cpu_ops,
@@ -662,10 +685,10 @@ static struct clk cpu_clk = {
662 685
663static struct clk io_clk = { 686static struct clk io_clk = {
664 .parent = &pll_clk, 687 .parent = &pll_clk,
665 .enable_reg = HW_CLKCTRL_FRAC_ADDR, 688 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
666 .enable_shift = 31, 689 .enable_shift = 31,
667 .enable_negate = 1, 690 .enable_negate = 1,
668 .scale_reg = HW_CLKCTRL_FRAC_ADDR, 691 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
669 .scale_shift = 24, 692 .scale_shift = 24,
670 .flags = RATE_PROPAGATES | ENABLED, 693 .flags = RATE_PROPAGATES | ENABLED,
671 .ops = &io_ops, 694 .ops = &io_ops,
@@ -673,10 +696,10 @@ static struct clk io_clk = {
673 696
674static struct clk hclk = { 697static struct clk hclk = {
675 .parent = &cpu_clk, 698 .parent = &cpu_clk,
676 .scale_reg = HW_CLKCTRL_HBUS_ADDR, 699 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
677 .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, 700 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
678 .bypass_shift = 7, 701 .bypass_shift = 7,
679 .busy_reg = HW_CLKCTRL_HBUS_ADDR, 702 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
680 .busy_bit = 29, 703 .busy_bit = 29,
681 .flags = RATE_PROPAGATES | ENABLED, 704 .flags = RATE_PROPAGATES | ENABLED,
682 .ops = &hbus_ops, 705 .ops = &hbus_ops,
@@ -684,8 +707,8 @@ static struct clk hclk = {
684 707
685static struct clk xclk = { 708static struct clk xclk = {
686 .parent = &osc_24M, 709 .parent = &osc_24M,
687 .scale_reg = HW_CLKCTRL_XBUS_ADDR, 710 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
688 .busy_reg = HW_CLKCTRL_XBUS_ADDR, 711 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
689 .busy_bit = 31, 712 .busy_bit = 31,
690 .flags = RATE_PROPAGATES | ENABLED, 713 .flags = RATE_PROPAGATES | ENABLED,
691 .ops = &xbus_ops, 714 .ops = &xbus_ops,
@@ -693,7 +716,7 @@ static struct clk xclk = {
693 716
694static struct clk uart_clk = { 717static struct clk uart_clk = {
695 .parent = &xclk, 718 .parent = &xclk,
696 .enable_reg = HW_CLKCTRL_XTAL_ADDR, 719 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
697 .enable_shift = 31, 720 .enable_shift = 31,
698 .enable_negate = 1, 721 .enable_negate = 1,
699 .flags = ENABLED, 722 .flags = ENABLED,
@@ -702,7 +725,7 @@ static struct clk uart_clk = {
702 725
703static struct clk audio_clk = { 726static struct clk audio_clk = {
704 .parent = &xclk, 727 .parent = &xclk,
705 .enable_reg = HW_CLKCTRL_XTAL_ADDR, 728 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
706 .enable_shift = 30, 729 .enable_shift = 30,
707 .enable_negate = 1, 730 .enable_negate = 1,
708 .ops = &min_ops, 731 .ops = &min_ops,
@@ -710,7 +733,7 @@ static struct clk audio_clk = {
710 733
711static struct clk pwm_clk = { 734static struct clk pwm_clk = {
712 .parent = &xclk, 735 .parent = &xclk,
713 .enable_reg = HW_CLKCTRL_XTAL_ADDR, 736 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
714 .enable_shift = 29, 737 .enable_shift = 29,
715 .enable_negate = 1, 738 .enable_negate = 1,
716 .ops = &min_ops, 739 .ops = &min_ops,
@@ -718,7 +741,7 @@ static struct clk pwm_clk = {
718 741
719static struct clk dri_clk = { 742static struct clk dri_clk = {
720 .parent = &xclk, 743 .parent = &xclk,
721 .enable_reg = HW_CLKCTRL_XTAL_ADDR, 744 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
722 .enable_shift = 28, 745 .enable_shift = 28,
723 .enable_negate = 1, 746 .enable_negate = 1,
724 .ops = &min_ops, 747 .ops = &min_ops,
@@ -726,7 +749,7 @@ static struct clk dri_clk = {
726 749
727static struct clk digctl_clk = { 750static struct clk digctl_clk = {
728 .parent = &xclk, 751 .parent = &xclk,
729 .enable_reg = HW_CLKCTRL_XTAL_ADDR, 752 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
730 .enable_shift = 27, 753 .enable_shift = 27,
731 .enable_negate = 1, 754 .enable_negate = 1,
732 .ops = &min_ops, 755 .ops = &min_ops,
@@ -734,7 +757,7 @@ static struct clk digctl_clk = {
734 757
735static struct clk timer_clk = { 758static struct clk timer_clk = {
736 .parent = &xclk, 759 .parent = &xclk,
737 .enable_reg = HW_CLKCTRL_XTAL_ADDR, 760 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
738 .enable_shift = 26, 761 .enable_shift = 26,
739 .enable_negate = 1, 762 .enable_negate = 1,
740 .flags = ENABLED, 763 .flags = ENABLED,
@@ -743,13 +766,13 @@ static struct clk timer_clk = {
743 766
744static struct clk lcdif_clk = { 767static struct clk lcdif_clk = {
745 .parent = &pll_clk, 768 .parent = &pll_clk,
746 .scale_reg = HW_CLKCTRL_PIX_ADDR, 769 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
747 .busy_reg = HW_CLKCTRL_PIX_ADDR, 770 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
748 .busy_bit = 29, 771 .busy_bit = 29,
749 .enable_reg = HW_CLKCTRL_PIX_ADDR, 772 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
750 .enable_shift = 31, 773 .enable_shift = 31,
751 .enable_negate = 1, 774 .enable_negate = 1,
752 .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, 775 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
753 .bypass_shift = 1, 776 .bypass_shift = 1,
754 .flags = NEEDS_SET_PARENT, 777 .flags = NEEDS_SET_PARENT,
755 .ops = &lcdif_ops, 778 .ops = &lcdif_ops,
@@ -757,12 +780,12 @@ static struct clk lcdif_clk = {
757 780
758static struct clk ssp_clk = { 781static struct clk ssp_clk = {
759 .parent = &io_clk, 782 .parent = &io_clk,
760 .scale_reg = HW_CLKCTRL_SSP_ADDR, 783 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
761 .busy_reg = HW_CLKCTRL_SSP_ADDR, 784 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
762 .busy_bit = 29, 785 .busy_bit = 29,
763 .enable_reg = HW_CLKCTRL_SSP_ADDR, 786 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
764 .enable_shift = 31, 787 .enable_shift = 31,
765 .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, 788 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
766 .bypass_shift = 5, 789 .bypass_shift = 5,
767 .enable_negate = 1, 790 .enable_negate = 1,
768 .flags = NEEDS_SET_PARENT, 791 .flags = NEEDS_SET_PARENT,
@@ -771,13 +794,13 @@ static struct clk ssp_clk = {
771 794
772static struct clk gpmi_clk = { 795static struct clk gpmi_clk = {
773 .parent = &io_clk, 796 .parent = &io_clk,
774 .scale_reg = HW_CLKCTRL_GPMI_ADDR, 797 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
775 .busy_reg = HW_CLKCTRL_GPMI_ADDR, 798 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
776 .busy_bit = 29, 799 .busy_bit = 29,
777 .enable_reg = HW_CLKCTRL_GPMI_ADDR, 800 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
778 .enable_shift = 31, 801 .enable_shift = 31,
779 .enable_negate = 1, 802 .enable_negate = 1,
780 .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, 803 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
781 .bypass_shift = 4, 804 .bypass_shift = 4,
782 .flags = NEEDS_SET_PARENT, 805 .flags = NEEDS_SET_PARENT,
783 .ops = &std_ops, 806 .ops = &std_ops,
@@ -785,7 +808,7 @@ static struct clk gpmi_clk = {
785 808
786static struct clk spdif_clk = { 809static struct clk spdif_clk = {
787 .parent = &pll_clk, 810 .parent = &pll_clk,
788 .enable_reg = HW_CLKCTRL_SPDIF_ADDR, 811 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF,
789 .enable_shift = 31, 812 .enable_shift = 31,
790 .enable_negate = 1, 813 .enable_negate = 1,
791 .ops = &min_ops, 814 .ops = &min_ops,
@@ -793,14 +816,14 @@ static struct clk spdif_clk = {
793 816
794static struct clk emi_clk = { 817static struct clk emi_clk = {
795 .parent = &pll_clk, 818 .parent = &pll_clk,
796 .enable_reg = HW_CLKCTRL_EMI_ADDR, 819 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
797 .enable_shift = 31, 820 .enable_shift = 31,
798 .enable_negate = 1, 821 .enable_negate = 1,
799 .scale_reg = HW_CLKCTRL_FRAC_ADDR, 822 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
800 .scale_shift = 8, 823 .scale_shift = 8,
801 .busy_reg = HW_CLKCTRL_EMI_ADDR, 824 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
802 .busy_bit = 28, 825 .busy_bit = 28,
803 .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, 826 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
804 .bypass_shift = 6, 827 .bypass_shift = 6,
805 .flags = ENABLED, 828 .flags = ENABLED,
806 .ops = &emi_ops, 829 .ops = &emi_ops,
@@ -808,37 +831,37 @@ static struct clk emi_clk = {
808 831
809static struct clk ir_clk = { 832static struct clk ir_clk = {
810 .parent = &io_clk, 833 .parent = &io_clk,
811 .enable_reg = HW_CLKCTRL_IR_ADDR, 834 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_IR,
812 .enable_shift = 31, 835 .enable_shift = 31,
813 .enable_negate = 1, 836 .enable_negate = 1,
814 .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, 837 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
815 .bypass_shift = 3, 838 .bypass_shift = 3,
816 .ops = &min_ops, 839 .ops = &min_ops,
817}; 840};
818 841
819static struct clk saif_clk = { 842static struct clk saif_clk = {
820 .parent = &pll_clk, 843 .parent = &pll_clk,
821 .scale_reg = HW_CLKCTRL_SAIF_ADDR, 844 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
822 .busy_reg = HW_CLKCTRL_SAIF_ADDR, 845 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
823 .busy_bit = 29, 846 .busy_bit = 29,
824 .enable_reg = HW_CLKCTRL_SAIF_ADDR, 847 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
825 .enable_shift = 31, 848 .enable_shift = 31,
826 .enable_negate = 1, 849 .enable_negate = 1,
827 .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, 850 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
828 .bypass_shift = 0, 851 .bypass_shift = 0,
829 .ops = &std_ops, 852 .ops = &std_ops,
830}; 853};
831 854
832static struct clk usb_clk = { 855static struct clk usb_clk = {
833 .parent = &pll_clk, 856 .parent = &pll_clk,
834 .enable_reg = HW_CLKCTRL_PLLCTRL0_ADDR, 857 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
835 .enable_shift = 18, 858 .enable_shift = 18,
836 .enable_negate = 1, 859 .enable_negate = 1,
837 .ops = &min_ops, 860 .ops = &min_ops,
838}; 861};
839 862
840/* list of all the clocks */ 863/* list of all the clocks */
841static __initdata struct clk_lookup onchip_clks[] = { 864static struct clk_lookup onchip_clks[] = {
842 { 865 {
843 .con_id = "osc_24M", 866 .con_id = "osc_24M",
844 .clk = &osc_24M, 867 .clk = &osc_24M,
diff --git a/arch/arm/plat-stmp3xxx/core.c b/arch/arm/plat-stmp3xxx/core.c
index 6e2fef1639b0..37b8a09148a4 100644
--- a/arch/arm/plat-stmp3xxx/core.c
+++ b/arch/arm/plat-stmp3xxx/core.c
@@ -20,6 +20,7 @@
20#include <linux/io.h> 20#include <linux/io.h>
21 21
22#include <mach/stmp3xxx.h> 22#include <mach/stmp3xxx.h>
23#include <mach/platform.h>
23#include <mach/dma.h> 24#include <mach/dma.h>
24#include <mach/regs-clkctrl.h> 25#include <mach/regs-clkctrl.h>
25 26
@@ -121,7 +122,7 @@ struct platform_device stmp3xxx_dbguart = {
121void __init stmp3xxx_init(void) 122void __init stmp3xxx_init(void)
122{ 123{
123 /* Turn off auto-slow and other tricks */ 124 /* Turn off auto-slow and other tricks */
124 HW_CLKCTRL_HBUS_CLR(0x07f00000U); 125 stmp3xxx_clearl(0x7f00000, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
125 126
126 stmp3xxx_dma_init(); 127 stmp3xxx_dma_init();
127} 128}
diff --git a/arch/arm/plat-stmp3xxx/dma.c b/arch/arm/plat-stmp3xxx/dma.c
index cf42de05e568..d2f497764dce 100644
--- a/arch/arm/plat-stmp3xxx/dma.c
+++ b/arch/arm/plat-stmp3xxx/dma.c
@@ -23,6 +23,7 @@
23 23
24#include <asm/page.h> 24#include <asm/page.h>
25 25
26#include <mach/platform.h>
26#include <mach/dma.h> 27#include <mach/dma.h>
27#include <mach/regs-apbx.h> 28#include <mach/regs-apbx.h>
28#include <mach/regs-apbh.h> 29#include <mach/regs-apbh.h>
@@ -35,16 +36,6 @@ static struct stmp3xxx_dma_user {
35 const char *name; 36 const char *name;
36} channels[MAX_DMA_CHANNELS]; 37} channels[MAX_DMA_CHANNELS];
37 38
38static inline int dmach(int ch)
39{
40 return ch % 16;
41}
42
43static inline int dmabus(int ch)
44{
45 return ch / 16;
46}
47
48#define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS) 39#define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS)
49#define IS_USED(ch) (channels[ch].inuse) 40#define IS_USED(ch) (channels[ch].inuse)
50 41
@@ -101,17 +92,19 @@ int stmp3xxx_dma_read_semaphore(int channel)
101{ 92{
102 int sem = -1; 93 int sem = -1;
103 94
104 switch (dmabus(channel)) { 95 switch (STMP3XXX_DMA_BUS(channel)) {
105 case STMP3XXX_BUS_APBH: 96 case STMP3XXX_BUS_APBH:
106 sem = 97 sem = __raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
107 (HW_APBH_CHn_SEMA_RD(dmach(channel)) & 98 STMP3XXX_DMA_CHANNEL(channel) * 0x70);
108 BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE; 99 sem &= BM_APBH_CHn_SEMA_PHORE;
100 sem >>= BP_APBH_CHn_SEMA_PHORE;
109 break; 101 break;
110 102
111 case STMP3XXX_BUS_APBX: 103 case STMP3XXX_BUS_APBX:
112 sem = 104 sem = __raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
113 (HW_APBX_CHn_SEMA_RD(dmach(channel)) & 105 STMP3XXX_DMA_CHANNEL(channel) * 0x70);
114 BM_APBX_CHn_SEMA_PHORE) >> BP_APBX_CHn_SEMA_PHORE; 106 sem &= BM_APBX_CHn_SEMA_PHORE;
107 sem >>= BP_APBX_CHn_SEMA_PHORE;
115 break; 108 break;
116 default: 109 default:
117 BUG(); 110 BUG();
@@ -189,39 +182,44 @@ EXPORT_SYMBOL(stmp3xxx_dma_free_command);
189void stmp3xxx_dma_go(int channel, 182void stmp3xxx_dma_go(int channel,
190 struct stmp3xxx_dma_descriptor *head, u32 semaphore) 183 struct stmp3xxx_dma_descriptor *head, u32 semaphore)
191{ 184{
192 int ch = dmach(channel); 185 int ch = STMP3XXX_DMA_CHANNEL(channel);
186 void __iomem *c, *s;
193 187
194 switch (dmabus(channel)) { 188 switch (STMP3XXX_DMA_BUS(channel)) {
195 case STMP3XXX_BUS_APBH: 189 case STMP3XXX_BUS_APBH:
196 /* Set next command */ 190 c = REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR + 0x70 * ch;
197 HW_APBH_CHn_NXTCMDAR_WR(ch, head->handle); 191 s = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * ch;
198 /* Set counting semaphore (kicks off transfer). Assumes
199 peripheral has been set up correctly */
200 HW_APBH_CHn_SEMA_WR(ch, semaphore);
201 break; 192 break;
202 193
203 case STMP3XXX_BUS_APBX: 194 case STMP3XXX_BUS_APBX:
204 /* Set next command */ 195 c = REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR + 0x70 * ch;
205 HW_APBX_CHn_NXTCMDAR_WR(ch, head->handle); 196 s = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * ch;
206 /* Set counting semaphore (kicks off transfer). Assumes
207 peripheral has been set up correctly */
208 HW_APBX_CHn_SEMA_WR(ch, semaphore);
209 break; 197 break;
198
199 default:
200 return;
210 } 201 }
202
203 /* Set next command */
204 __raw_writel(head->handle, c);
205 /* Set counting semaphore (kicks off transfer). Assumes
206 peripheral has been set up correctly */
207 __raw_writel(semaphore, s);
211} 208}
212EXPORT_SYMBOL(stmp3xxx_dma_go); 209EXPORT_SYMBOL(stmp3xxx_dma_go);
213 210
214int stmp3xxx_dma_running(int channel) 211int stmp3xxx_dma_running(int channel)
215{ 212{
216 switch (dmabus(channel)) { 213 switch (STMP3XXX_DMA_BUS(channel)) {
217 case STMP3XXX_BUS_APBH: 214 case STMP3XXX_BUS_APBH:
218 return HW_APBH_CHn_SEMA_RD(dmach(channel)) & 215 return (__raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
219 BM_APBH_CHn_SEMA_PHORE; 216 0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
217 BM_APBH_CHn_SEMA_PHORE;
220 218
221 case STMP3XXX_BUS_APBX: 219 case STMP3XXX_BUS_APBX:
222 return HW_APBX_CHn_SEMA_RD(dmach(channel)) & 220 return (__raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
223 BM_APBX_CHn_SEMA_PHORE; 221 0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
224 222 BM_APBX_CHn_SEMA_PHORE;
225 default: 223 default:
226 BUG(); 224 BUG();
227 return 0; 225 return 0;
@@ -238,7 +236,7 @@ void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain)
238 236
239 for (i = 0; i < chain->total_count; i++) 237 for (i = 0; i < chain->total_count; i++)
240 stmp3xxx_dma_free_command( 238 stmp3xxx_dma_free_command(
241 STMP3xxx_DMA(chain->channel, chain->bus), 239 STMP3XXX_DMA(chain->channel, chain->bus),
242 &chain->chain[i]); 240 &chain->chain[i]);
243} 241}
244EXPORT_SYMBOL(stmp3xxx_dma_free_chain); 242EXPORT_SYMBOL(stmp3xxx_dma_free_chain);
@@ -291,16 +289,15 @@ int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
291 chain->free_count = items; 289 chain->free_count = items;
292 chain->active_count = 0; 290 chain->active_count = 0;
293 chain->cooked_count = 0; 291 chain->cooked_count = 0;
294 chain->bus = dmabus(ch); 292 chain->bus = STMP3XXX_DMA_BUS(ch);
295 chain->channel = dmach(ch); 293 chain->channel = STMP3XXX_DMA_CHANNEL(ch);
296 return err; 294 return err;
297} 295}
298EXPORT_SYMBOL(stmp3xxx_dma_make_chain); 296EXPORT_SYMBOL(stmp3xxx_dma_make_chain);
299 297
300void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain) 298void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain)
301{ 299{
302 BUG_ON(stmp3xxx_dma_running(STMP3xxx_DMA(chain->channel, chain->bus)) > 300 BUG_ON(stmp3xxx_dma_running(STMP3XXX_DMA(chain->channel, chain->bus)));
303 0);
304 chain->free_index = 0; 301 chain->free_index = 0;
305 chain->active_index = 0; 302 chain->active_index = 0;
306 chain->cooked_index = 0; 303 chain->cooked_index = 0;
@@ -325,6 +322,8 @@ EXPORT_SYMBOL(stmp37xx_circ_advance_free);
325void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain, 322void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
326 unsigned count) 323 unsigned count)
327{ 324{
325 void __iomem *c;
326 u32 mask_clr, mask;
328 BUG_ON(chain->free_count < count); 327 BUG_ON(chain->free_count < count);
329 328
330 chain->free_count -= count; 329 chain->free_count -= count;
@@ -334,26 +333,24 @@ void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
334 333
335 switch (chain->bus) { 334 switch (chain->bus) {
336 case STMP3XXX_BUS_APBH: 335 case STMP3XXX_BUS_APBH:
337 /* Set counting semaphore (kicks off transfer). Assumes 336 c = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * chain->channel;
338 peripheral has been set up correctly */ 337 mask_clr = BM_APBH_CHn_SEMA_INCREMENT_SEMA;
339 HW_APBH_CHn_SEMA_CLR(chain->channel, 338 mask = BF(count, APBH_CHn_SEMA_INCREMENT_SEMA);
340 BM_APBH_CHn_SEMA_INCREMENT_SEMA);
341 HW_APBH_CHn_SEMA_SET(chain->channel,
342 BF_APBH_CHn_SEMA_INCREMENT_SEMA(count));
343 break; 339 break;
344
345 case STMP3XXX_BUS_APBX: 340 case STMP3XXX_BUS_APBX:
346 /* Set counting semaphore (kicks off transfer). Assumes 341 c = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * chain->channel;
347 peripheral has been set up correctly */ 342 mask_clr = BM_APBX_CHn_SEMA_INCREMENT_SEMA;
348 HW_APBX_CHn_SEMA_CLR(chain->channel, 343 mask = BF(count, APBX_CHn_SEMA_INCREMENT_SEMA);
349 BM_APBX_CHn_SEMA_INCREMENT_SEMA);
350 HW_APBX_CHn_SEMA_SET(chain->channel,
351 BF_APBX_CHn_SEMA_INCREMENT_SEMA(count));
352 break; 344 break;
353
354 default: 345 default:
355 BUG(); 346 BUG();
347 return;
356 } 348 }
349
350 /* Set counting semaphore (kicks off transfer). Assumes
351 peripheral has been set up correctly */
352 stmp3xxx_clearl(mask_clr, c);
353 stmp3xxx_setl(mask, c);
357} 354}
358EXPORT_SYMBOL(stmp37xx_circ_advance_active); 355EXPORT_SYMBOL(stmp37xx_circ_advance_active);
359 356
@@ -362,7 +359,7 @@ unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain)
362 unsigned cooked; 359 unsigned cooked;
363 360
364 cooked = chain->active_count - 361 cooked = chain->active_count -
365 stmp3xxx_dma_read_semaphore(STMP3xxx_DMA(chain->channel, chain->bus)); 362 stmp3xxx_dma_read_semaphore(STMP3XXX_DMA(chain->channel, chain->bus));
366 363
367 chain->active_count -= cooked; 364 chain->active_count -= cooked;
368 chain->active_index += cooked; 365 chain->active_index += cooked;
@@ -383,38 +380,41 @@ void stmp3xxx_dma_set_alt_target(int channel, int function)
383#else 380#else
384#error wrong arch 381#error wrong arch
385#endif 382#endif
386 int shift = dmach(channel) * bits; 383 int shift = STMP3XXX_DMA_CHANNEL(channel) * bits;
387 unsigned mask = (1<<bits) - 1; 384 unsigned mask = (1<<bits) - 1;
385 void __iomem *c;
388 386
389 BUG_ON(function < 0 || function >= (1<<bits)); 387 BUG_ON(function < 0 || function >= (1<<bits));
390 pr_debug("%s: channel = %d, using mask %x, " 388 pr_debug("%s: channel = %d, using mask %x, "
391 "shift = %d\n", __func__, channel, mask, shift); 389 "shift = %d\n", __func__, channel, mask, shift);
392 390
393 switch (dmabus(channel)) { 391 switch (STMP3XXX_DMA_BUS(channel)) {
394 case STMP3XXX_BUS_APBH: 392 case STMP3XXX_BUS_APBH:
395 HW_APBH_DEVSEL_CLR(mask<<shift); 393 c = REGS_APBH_BASE + HW_APBH_DEVSEL;
396 HW_APBH_DEVSEL_SET(function<<shift);
397 break; 394 break;
398 case STMP3XXX_BUS_APBX: 395 case STMP3XXX_BUS_APBX:
399 HW_APBX_DEVSEL_CLR(mask<<shift); 396 c = REGS_APBX_BASE + HW_APBX_DEVSEL;
400 HW_APBX_DEVSEL_SET(function<<shift);
401 break; 397 break;
402 default: 398 default:
403 BUG(); 399 BUG();
404 } 400 }
401 stmp3xxx_clearl(mask << shift, c);
402 stmp3xxx_setl(mask << shift, c);
405} 403}
406EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target); 404EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target);
407 405
408void stmp3xxx_dma_suspend(void) 406void stmp3xxx_dma_suspend(void)
409{ 407{
410 HW_APBH_CTRL0_SET(BM_APBH_CTRL0_CLKGATE); 408 stmp3xxx_setl(BM_APBH_CTRL0_CLKGATE, REGS_APBH_BASE + HW_APBH_CTRL0);
411 HW_APBX_CTRL0_SET(BM_APBX_CTRL0_CLKGATE); 409 stmp3xxx_setl(BM_APBX_CTRL0_CLKGATE, REGS_APBX_BASE + HW_APBX_CTRL0);
412} 410}
413 411
414void stmp3xxx_dma_resume(void) 412void stmp3xxx_dma_resume(void)
415{ 413{
416 HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST); 414 stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
417 HW_APBX_CTRL0_CLR(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST); 415 REGS_APBH_BASE + HW_APBH_CTRL0);
416 stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
417 REGS_APBX_BASE + HW_APBX_CTRL0);
418} 418}
419 419
420#ifdef CONFIG_CPU_FREQ 420#ifdef CONFIG_CPU_FREQ
@@ -452,11 +452,12 @@ static struct dma_notifier_block dma_cpufreq_nb = {
452 452
453void __init stmp3xxx_dma_init(void) 453void __init stmp3xxx_dma_init(void)
454{ 454{
455 HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST); 455 stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
456 HW_APBX_CTRL0_CLR(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST); 456 REGS_APBH_BASE + HW_APBH_CTRL0);
457 stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
458 REGS_APBX_BASE + HW_APBX_CTRL0);
457#ifdef CONFIG_CPU_FREQ 459#ifdef CONFIG_CPU_FREQ
458 cpufreq_register_notifier(&dma_cpufreq_nb.nb, 460 cpufreq_register_notifier(&dma_cpufreq_nb.nb,
459 CPUFREQ_TRANSITION_NOTIFIER); 461 CPUFREQ_TRANSITION_NOTIFIER);
460#endif /* CONFIG_CPU_FREQ */ 462#endif /* CONFIG_CPU_FREQ */
461
462} 463}
diff --git a/arch/arm/plat-stmp3xxx/include/mach/dma.h b/arch/arm/plat-stmp3xxx/include/mach/dma.h
index 1e305b2bfe73..7c58557c6766 100644
--- a/arch/arm/plat-stmp3xxx/include/mach/dma.h
+++ b/arch/arm/plat-stmp3xxx/include/mach/dma.h
@@ -25,16 +25,14 @@
25#define MAX_PIO_WORDS (15) 25#define MAX_PIO_WORDS (15)
26#endif 26#endif
27 27
28#define STMP3XXX_BUS_APBH 0 28#define STMP3XXX_BUS_APBH 0
29#define STMP3XXX_BUS_APBX 1 29#define STMP3XXX_BUS_APBX 1
30#define STMP3XXX_DMA_MAX_CHANNEL 16 30#define STMP3XXX_DMA_MAX_CHANNEL 16
31 31#define STMP3XXX_DMA_BUS(dma) ((dma) / 16)
32 32#define STMP3XXX_DMA_CHANNEL(dma) ((dma) % 16)
33#define STMP3xxx_DMA(channel, bus) ((bus) * 16 + (channel)) 33#define STMP3XXX_DMA(channel, bus) ((bus) * 16 + (channel))
34 34#define MAX_DMA_ADDRESS 0xffffffff
35#define MAX_DMA_ADDRESS 0xffffffff 35#define MAX_DMA_CHANNELS 32
36
37#define MAX_DMA_CHANNELS 32
38 36
39struct stmp3xxx_dma_command { 37struct stmp3xxx_dma_command {
40 u32 next; 38 u32 next;
diff --git a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
index 526c068d7c44..cc5af82279ad 100644
--- a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
+++ b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
@@ -146,10 +146,9 @@ struct stmp3xxx_pinmux_bank {
146 u8 strengths[HW_DRIVE_PINDRV_NUM]; 146 u8 strengths[HW_DRIVE_PINDRV_NUM];
147 147
148 /* GPIO things */ 148 /* GPIO things */
149 void __iomem *hw_gpio_read, 149 void __iomem *hw_gpio_in,
150 *hw_gpio_set, 150 *hw_gpio_out,
151 *hw_gpio_clr, 151 *hw_gpio_doe;
152 *hw_gpio_doe;
153 int irq, virq; 152 int irq, virq;
154}; 153};
155 154
diff --git a/arch/arm/plat-stmp3xxx/include/mach/platform.h b/arch/arm/plat-stmp3xxx/include/mach/platform.h
index 525c41379bbe..7007ddaa91eb 100644
--- a/arch/arm/plat-stmp3xxx/include/mach/platform.h
+++ b/arch/arm/plat-stmp3xxx/include/mach/platform.h
@@ -14,6 +14,9 @@
14#ifndef __ASM_PLAT_PLATFORM_H 14#ifndef __ASM_PLAT_PLATFORM_H
15#define __ASM_PLAT_PLATFORM_H 15#define __ASM_PLAT_PLATFORM_H
16 16
17#ifndef __ASSEMBLER__
18#include <linux/io.h>
19#endif
17#include <asm/sizes.h> 20#include <asm/sizes.h>
18 21
19/* Virtual address where registers are mapped */ 22/* Virtual address where registers are mapped */
@@ -44,4 +47,22 @@
44#define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR 47#define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR
45#endif 48#endif
46 49
50#define HW_STMP3XXX_SET 0x04
51#define HW_STMP3XXX_CLR 0x08
52#define HW_STMP3XXX_TOG 0x0c
53
54#ifndef __ASSEMBLER__
55static inline void stmp3xxx_clearl(u32 v, void __iomem *r)
56{
57 __raw_writel(v, r + HW_STMP3XXX_CLR);
58}
59
60static inline void stmp3xxx_setl(u32 v, void __iomem *r)
61{
62 __raw_writel(v, r + HW_STMP3XXX_SET);
63}
64#endif
65
66#define BF(value, field) (((value) << BP_##field) & BM_##field)
67
47#endif /* __ASM_ARCH_PLATFORM_H */ 68#endif /* __ASM_ARCH_PLATFORM_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h
deleted file mode 100644
index 47797b2b36af..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h
+++ /dev/null
@@ -1,195 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X SoC register access interfaces
3 *
4 * The SoC registers may be accessed via:
5 *
6 * - single 32 bit address, or
7 * - four 32 bit addresses - general purpose, set, clear and toggle bits
8 *
9 * Multiple IP blocks (e.g. SSP, UART) provide identical register sets per
10 * each module
11 *
12 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
13 *
14 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
15 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
16 */
17
18/*
19 * The code contained herein is licensed under the GNU General Public
20 * License. You may obtain a copy of the GNU General Public License
21 * Version 2 or later at the following locations:
22 *
23 * http://www.opensource.org/licenses/gpl-license.html
24 * http://www.gnu.org/copyleft/gpl.html
25 */
26#ifndef __ASM_PLAT_STMP3XXX_REGS_H
27#define __ASM_PLAT_STMP3XXX_REGS_H
28
29#ifndef __ASSEMBLER__
30#include <linux/io.h>
31#endif
32
33#include "platform.h"
34
35#define REGS_BASE STMP3XXX_REGS_BASE
36
37#define HW_STMP3xxx_SET 0x04
38#define HW_STMP3xxx_CLR 0x08
39#define HW_STMP3xxx_TOG 0x0c
40
41#ifndef __ASSEMBLER__
42#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr) \
43 static const u32 id##_OFFSET = offset; \
44 static inline u32 id##_RD_NB(const void __iomem *regbase) { \
45 if (!rd) \
46 printk(KERN_ERR"%s: cannot READ at %p+%x\n", \
47 #id, regbase, offset); \
48 return __raw_readl(regbase + offset); \
49 } \
50 static inline void id##_WR_NB(void __iomem *regbase, u32 v) { \
51 if (!wr) \
52 printk(KERN_ERR"%s: cannot WRITE at %p+%x\n", \
53 #id, regbase, offset); \
54 __raw_writel(v, regbase + offset); \
55 } \
56 static inline void id##_SET_NB(void __iomem *regbase, u32 v) { \
57 if (!wr) \
58 printk(KERN_ERR"%s: cannot SET at %p+%x\n", \
59 #id, regbase, offset); \
60 if (regset) \
61 __raw_writel(v, regbase + \
62 offset + HW_STMP3xxx_SET); \
63 else \
64 __raw_writel(v | __raw_readl(regbase + offset), \
65 regbase + offset); \
66 } \
67 static inline void id##_CLR_NB(void __iomem *regbase, u32 v) { \
68 if (!wr) \
69 printk(KERN_ERR"%s: cannot CLR at %p+%x\n", \
70 #id, regbase, offset); \
71 if (regset) \
72 __raw_writel(v, regbase + \
73 offset + HW_STMP3xxx_CLR); \
74 else \
75 __raw_writel( \
76 ~v & __raw_readl(regbase + offset), \
77 regbase + offset); \
78 } \
79 static inline void id##_TOG_NB(void __iomem *regbase, u32 v) { \
80 if (!wr) \
81 printk(KERN_ERR"%s: cannot TOG at %p+%x\n", \
82 #id, regbase, offset); \
83 if (regset) \
84 __raw_writel(v, regbase + \
85 offset + HW_STMP3xxx_TOG); \
86 else \
87 __raw_writel(v ^ __raw_readl(regbase + offset), \
88 regbase + offset); \
89 } \
90 static inline u32 id##_RD(void) { return id##_RD_NB(base); } \
91 static inline void id##_WR(u32 v) { id##_WR_NB(base, v); } \
92 static inline void id##_SET(u32 v) { id##_SET_NB(base, v); } \
93 static inline void id##_CLR(u32 v) { id##_CLR_NB(base, v); } \
94 static inline void id##_TOG(u32 v) { id##_TOG_NB(base, v); }
95
96#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step)\
97 static inline u32 id##_OFFSET(int i) { \
98 return offset + i * step; \
99 } \
100 static inline u32 id##_RD_NB(const void __iomem *regbase, int i) {\
101 if (!rd) \
102 printk(KERN_ERR"%s(%d): can't READ at %p+%x\n", \
103 #id, i, regbase, offset + i * step); \
104 return __raw_readl(regbase + offset + i * step); \
105 } \
106 static inline void id##_WR_NB(void __iomem *regbase, int i, u32 v) {\
107 if (!wr) \
108 printk(KERN_ERR"%s(%d): can't WRITE at %p+%x\n",\
109 #id, i, regbase, offset + i * step); \
110 __raw_writel(v, regbase + offset + i * step); \
111 } \
112 static inline void id##_SET_NB(void __iomem *regbase, int i, u32 v) {\
113 if (!wr) \
114 printk(KERN_ERR"%s(%d): can't SET at %p+%x\n", \
115 #id, i, regbase, offset + i * step); \
116 if (regset) \
117 __raw_writel(v, regbase + offset + \
118 i * step + HW_STMP3xxx_SET); \
119 else \
120 __raw_writel(v | __raw_readl(regbase + \
121 offset + i * step), \
122 regbase + offset + i * step); \
123 } \
124 static inline void id##_CLR_NB(void __iomem *regbase, int i, u32 v) {\
125 if (!wr) \
126 printk(KERN_ERR"%s(%d): cannot CLR at %p+%x\n", \
127 #id, i, regbase, offset + i * step); \
128 if (regset) \
129 __raw_writel(v, regbase + offset + \
130 i * step + HW_STMP3xxx_CLR); \
131 else \
132 __raw_writel(~v & __raw_readl(regbase + \
133 offset + i * step), \
134 regbase + offset + i * step); \
135 } \
136 static inline void id##_TOG_NB(void __iomem *regbase, int i, u32 v) {\
137 if (!wr) \
138 printk(KERN_ERR"%s(%d): cannot TOG at %p+%x\n", \
139 #id, i, regbase, offset + i * step); \
140 if (regset) \
141 __raw_writel(v, regbase + offset + \
142 i * step + HW_STMP3xxx_TOG); \
143 else \
144 __raw_writel(v ^ __raw_readl(regbase + offset \
145 + i * step), \
146 regbase + offset + i * step); \
147 } \
148 static inline u32 id##_RD(int i) \
149 { \
150 return id##_RD_NB(base, i); \
151 } \
152 static inline void id##_WR(int i, u32 v) \
153 { \
154 id##_WR_NB(base, i, v); \
155 } \
156 static inline void id##_SET(int i, u32 v) \
157 { \
158 id##_SET_NB(base, i, v); \
159 } \
160 static inline void id##_CLR(int i, u32 v) \
161 { \
162 id##_CLR_NB(base, i, v); \
163 } \
164 static inline void id##_TOG(int i, u32 v) \
165 { \
166 id##_TOG_NB(base, i, v); \
167 }
168
169#define HW_REGISTER_WO(id, base, offset)\
170 HW_REGISTER_FUNCS(id, base, offset, 1, 0, 1)
171#define HW_REGISTER_RO(id, base, offset)\
172 HW_REGISTER_FUNCS(id, base, offset, 1, 1, 0)
173#define HW_REGISTER(id, base, offset) \
174 HW_REGISTER_FUNCS(id, base, offset, 1, 1, 1)
175#define HW_REGISTER_0(id, base, offset) \
176 HW_REGISTER_FUNCS(id, base, offset, 0, 1, 1)
177#define HW_REGISTER_INDEXED(id, base, offset, step) \
178 HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1, 1, 1, step)
179#define HW_REGISTER_RO_INDEXED(id, base, offset, step) \
180 HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1, 1, 0, step)
181#define HW_REGISTER_0_INDEXED(id, base, offset, step) \
182 HW_REGISTER_FUNCS_INDEXED(id, base, offset, 0, 1, 1, step)
183#else /* __ASSEMBLER__ */
184#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr)
185#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step)
186#define HW_REGISTER_WO(id, base, offset)
187#define HW_REGISTER_RO(id, base, offset)
188#define HW_REGISTER(id, base, offset)
189#define HW_REGISTER_0(id, base, offset)
190#define HW_REGISTER_INDEXED(id, base, offset, step)
191#define HW_REGISTER_RO_INDEXED(id, base, offset, step)
192#define HW_REGISTER_0_INDEXED(id, base, offset, step)
193#endif /* __ASSEMBLER__ */
194
195#endif /* __ASM_PLAT_STMP3XXX_REGS_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/system.h b/arch/arm/plat-stmp3xxx/include/mach/system.h
index dac48d267148..28a988889319 100644
--- a/arch/arm/plat-stmp3xxx/include/mach/system.h
+++ b/arch/arm/plat-stmp3xxx/include/mach/system.h
@@ -17,6 +17,7 @@
17#define __ASM_ARCH_SYSTEM_H 17#define __ASM_ARCH_SYSTEM_H
18 18
19#include <asm/proc-fns.h> 19#include <asm/proc-fns.h>
20#include <mach/platform.h>
20#include <mach/regs-clkctrl.h> 21#include <mach/regs-clkctrl.h>
21#include <mach/regs-power.h> 22#include <mach/regs-power.h>
22 23
@@ -33,13 +34,14 @@ static inline void arch_idle(void)
33static inline void arch_reset(char mode, const char *cmd) 34static inline void arch_reset(char mode, const char *cmd)
34{ 35{
35 /* Set BATTCHRG to default value */ 36 /* Set BATTCHRG to default value */
36 HW_POWER_CHARGE_WR(0x00010000); 37 __raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE);
37 38
38 /* Set MINPWR to default value */ 39 /* Set MINPWR to default value */
39 HW_POWER_MINPWR_WR(0); 40 __raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR);
40 41
41 /* Reset digital side of chip (but not power or RTC) */ 42 /* Reset digital side of chip (but not power or RTC) */
42 HW_CLKCTRL_RESET_WR(BM_CLKCTRL_RESET_DIG); 43 __raw_writel(BM_CLKCTRL_RESET_DIG,
44 REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET);
43 45
44 /* Should not return */ 46 /* Should not return */
45} 47}
diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c
index cb3659096681..20de4e0401ef 100644
--- a/arch/arm/plat-stmp3xxx/irq.c
+++ b/arch/arm/plat-stmp3xxx/irq.c
@@ -22,21 +22,15 @@
22#include <linux/sysdev.h> 22#include <linux/sysdev.h>
23 23
24#include <mach/stmp3xxx.h> 24#include <mach/stmp3xxx.h>
25#include <mach/platform.h>
25#include <mach/regs-icoll.h> 26#include <mach/regs-icoll.h>
26 27
27void __init stmp3xxx_init_irq(struct irq_chip *chip) 28void __init stmp3xxx_init_irq(struct irq_chip *chip)
28{ 29{
29 unsigned int i; 30 unsigned int i, lv;
30 31
31 /* Reset the interrupt controller */ 32 /* Reset the interrupt controller */
32 HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_CLKGATE); 33 stmp3xxx_reset_block(REGS_ICOLL_BASE + HW_ICOLL_CTRL, true);
33 udelay(10);
34 HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST);
35 udelay(10);
36 HW_ICOLL_CTRL_SET(BM_ICOLL_CTRL_SFTRST);
37 while (!(HW_ICOLL_CTRL_RD() & BM_ICOLL_CTRL_CLKGATE))
38 continue;
39 HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST | BM_ICOLL_CTRL_CLKGATE);
40 34
41 /* Disable all interrupts initially */ 35 /* Disable all interrupts initially */
42 for (i = 0; i < NR_REAL_IRQS; i++) { 36 for (i = 0; i < NR_REAL_IRQS; i++) {
@@ -47,13 +41,11 @@ void __init stmp3xxx_init_irq(struct irq_chip *chip)
47 } 41 }
48 42
49 /* Ensure vector is cleared */ 43 /* Ensure vector is cleared */
50 HW_ICOLL_LEVELACK_WR(1); 44 for (lv = 0; lv < 4; lv++)
51 HW_ICOLL_LEVELACK_WR(2); 45 __raw_writel(1 << lv, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
52 HW_ICOLL_LEVELACK_WR(4); 46 __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
53 HW_ICOLL_LEVELACK_WR(8);
54 47
55 HW_ICOLL_VECTOR_WR(0);
56 /* Barrier */ 48 /* Barrier */
57 (void) HW_ICOLL_STAT_RD(); 49 (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
58} 50}
59 51
diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c
index 9b28cc83f31c..d41200382208 100644
--- a/arch/arm/plat-stmp3xxx/pinmux.c
+++ b/arch/arm/plat-stmp3xxx/pinmux.c
@@ -15,6 +15,7 @@
15 * http://www.opensource.org/licenses/gpl-license.html 15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html 16 * http://www.gnu.org/copyleft/gpl.html
17 */ 17 */
18#define DEBUG
18#include <linux/module.h> 19#include <linux/module.h>
19#include <linux/kernel.h> 20#include <linux/kernel.h>
20#include <linux/errno.h> 21#include <linux/errno.h>
@@ -25,6 +26,7 @@
25#include <linux/irq.h> 26#include <linux/irq.h>
26 27
27#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <mach/platform.h>
28#include <mach/regs-pinctrl.h> 30#include <mach/regs-pinctrl.h>
29#include <mach/pins.h> 31#include <mach/pins.h>
30#include <mach/pinmux.h> 32#include <mach/pinmux.h>
@@ -33,97 +35,94 @@
33static struct stmp3xxx_pinmux_bank pinmux_banks[] = { 35static struct stmp3xxx_pinmux_bank pinmux_banks[] = {
34 [0] = { 36 [0] = {
35 .hw_muxsel = { 37 .hw_muxsel = {
36 HW_PINCTRL_MUXSEL0_ADDR, 38 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0,
37 HW_PINCTRL_MUXSEL1_ADDR 39 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1,
38 }, 40 },
39 .hw_drive = { 41 .hw_drive = {
40 HW_PINCTRL_DRIVE0_ADDR, 42 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0,
41 HW_PINCTRL_DRIVE1_ADDR, 43 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1,
42 HW_PINCTRL_DRIVE2_ADDR, 44 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2,
43 HW_PINCTRL_DRIVE3_ADDR 45 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3,
44 }, 46 },
45 .hw_pull = HW_PINCTRL_PULL0_ADDR, 47 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0,
46 .functions = { 0x0, 0x1, 0x2, 0x3 }, 48 .functions = { 0x0, 0x1, 0x2, 0x3 },
47 .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff }, 49 .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
48 50
49 .hw_gpio_read = HW_PINCTRL_DIN0_ADDR, 51 .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0,
50 .hw_gpio_set = HW_PINCTRL_DOUT0_ADDR + HW_STMP3xxx_SET, 52 .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0,
51 .hw_gpio_clr = HW_PINCTRL_DOUT0_ADDR + HW_STMP3xxx_CLR, 53 .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0,
52 .hw_gpio_doe = HW_PINCTRL_DOE0_ADDR,
53 .irq = IRQ_GPIO0, 54 .irq = IRQ_GPIO0,
54 55
55 .pin2irq = HW_PINCTRL_PIN2IRQ0_ADDR, 56 .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0,
56 .irqstat = HW_PINCTRL_IRQSTAT0_ADDR, 57 .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0,
57 .irqlevel = HW_PINCTRL_IRQLEVEL0_ADDR, 58 .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0,
58 .irqpolarity = HW_PINCTRL_IRQPOL0_ADDR, 59 .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0,
59 .irqen = HW_PINCTRL_IRQEN0_ADDR, 60 .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0,
60 }, 61 },
61 [1] = { 62 [1] = {
62 .hw_muxsel = { 63 .hw_muxsel = {
63 HW_PINCTRL_MUXSEL2_ADDR, 64 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2,
64 HW_PINCTRL_MUXSEL3_ADDR 65 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3,
65 }, 66 },
66 .hw_drive = { 67 .hw_drive = {
67 HW_PINCTRL_DRIVE4_ADDR, 68 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4,
68 HW_PINCTRL_DRIVE5_ADDR, 69 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5,
69 HW_PINCTRL_DRIVE6_ADDR, 70 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6,
70 HW_PINCTRL_DRIVE7_ADDR 71 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7,
71 }, 72 },
72 .hw_pull = HW_PINCTRL_PULL1_ADDR, 73 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL1,
73 .functions = { 0x0, 0x1, 0x2, 0x3 }, 74 .functions = { 0x0, 0x1, 0x2, 0x3 },
74 .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff }, 75 .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
75 76
76 .hw_gpio_read = HW_PINCTRL_DIN1_ADDR, 77 .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN1,
77 .hw_gpio_set = HW_PINCTRL_DOUT1_ADDR + HW_STMP3xxx_SET, 78 .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1,
78 .hw_gpio_clr = HW_PINCTRL_DOUT1_ADDR + HW_STMP3xxx_CLR, 79 .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE1,
79 .hw_gpio_doe = HW_PINCTRL_DOE1_ADDR,
80 .irq = IRQ_GPIO1, 80 .irq = IRQ_GPIO1,
81 81
82 .pin2irq = HW_PINCTRL_PIN2IRQ1_ADDR, 82 .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1,
83 .irqstat = HW_PINCTRL_IRQSTAT1_ADDR, 83 .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1,
84 .irqlevel = HW_PINCTRL_IRQLEVEL1_ADDR, 84 .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1,
85 .irqpolarity = HW_PINCTRL_IRQPOL1_ADDR, 85 .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1,
86 .irqen = HW_PINCTRL_IRQEN1_ADDR, 86 .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1,
87 }, 87 },
88 [2] = { 88 [2] = {
89 .hw_muxsel = { 89 .hw_muxsel = {
90 HW_PINCTRL_MUXSEL4_ADDR, 90 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4,
91 HW_PINCTRL_MUXSEL5_ADDR, 91 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5,
92 }, 92 },
93 .hw_drive = { 93 .hw_drive = {
94 HW_PINCTRL_DRIVE8_ADDR, 94 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8,
95 HW_PINCTRL_DRIVE9_ADDR, 95 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9,
96 HW_PINCTRL_DRIVE10_ADDR, 96 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10,
97 HW_PINCTRL_DRIVE11_ADDR, 97 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11,
98 }, 98 },
99 .hw_pull = HW_PINCTRL_PULL2_ADDR, 99 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL2,
100 .functions = { 0x0, 0x1, 0x2, 0x3 }, 100 .functions = { 0x0, 0x1, 0x2, 0x3 },
101 .strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 }, 101 .strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 },
102 102
103 .hw_gpio_read = HW_PINCTRL_DIN2_ADDR, 103 .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN2,
104 .hw_gpio_set = HW_PINCTRL_DOUT2_ADDR + HW_STMP3xxx_SET, 104 .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2,
105 .hw_gpio_clr = HW_PINCTRL_DOUT2_ADDR + HW_STMP3xxx_CLR, 105 .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE2,
106 .hw_gpio_doe = HW_PINCTRL_DOE2_ADDR,
107 .irq = IRQ_GPIO2, 106 .irq = IRQ_GPIO2,
108 107
109 .pin2irq = HW_PINCTRL_PIN2IRQ2_ADDR, 108 .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2,
110 .irqstat = HW_PINCTRL_IRQSTAT2_ADDR, 109 .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2,
111 .irqlevel = HW_PINCTRL_IRQLEVEL2_ADDR, 110 .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2,
112 .irqpolarity = HW_PINCTRL_IRQPOL2_ADDR, 111 .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2,
113 .irqen = HW_PINCTRL_IRQEN2_ADDR, 112 .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2,
114 }, 113 },
115 [3] = { 114 [3] = {
116 .hw_muxsel = { 115 .hw_muxsel = {
117 HW_PINCTRL_MUXSEL6_ADDR, 116 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6,
118 HW_PINCTRL_MUXSEL7_ADDR, 117 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7,
119 }, 118 },
120 .hw_drive = { 119 .hw_drive = {
121 HW_PINCTRL_DRIVE12_ADDR, 120 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12,
122 HW_PINCTRL_DRIVE13_ADDR, 121 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13,
123 HW_PINCTRL_DRIVE14_ADDR, 122 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14,
124 NULL, 123 NULL,
125 }, 124 },
126 .hw_pull = HW_PINCTRL_PULL3_ADDR, 125 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL3,
127 .functions = {0x0, 0x1, 0x2, 0x3}, 126 .functions = {0x0, 0x1, 0x2, 0x3},
128 .strengths = {0x0, 0x1, 0x2, 0x3, 0xff}, 127 .strengths = {0x0, 0x1, 0x2, 0x3, 0xff},
129 }, 128 },
@@ -196,8 +195,8 @@ void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
196 195
197 pr_debug("%s: writing 0x%x to 0x%p register\n", __func__, 196 pr_debug("%s: writing 0x%x to 0x%p register\n", __func__,
198 val << shift, hwdrive); 197 val << shift, hwdrive);
199 __raw_writel(HW_DRIVE_PINDRV_MASK << shift, hwdrive + HW_STMP3xxx_CLR); 198 stmp3xxx_clearl(HW_DRIVE_PINDRV_MASK << shift, hwdrive);
200 __raw_writel(val << shift, hwdrive + HW_STMP3xxx_SET); 199 stmp3xxx_setl(val << shift, hwdrive);
201} 200}
202 201
203void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage, 202void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
@@ -221,11 +220,9 @@ void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
221 pr_debug("%s: changing 0x%x bit in 0x%p register\n", 220 pr_debug("%s: changing 0x%x bit in 0x%p register\n",
222 __func__, HW_DRIVE_PINV_MASK << shift, hwdrive); 221 __func__, HW_DRIVE_PINV_MASK << shift, hwdrive);
223 if (voltage == PIN_1_8V) 222 if (voltage == PIN_1_8V)
224 __raw_writel(HW_DRIVE_PINV_MASK << shift, 223 stmp3xxx_clearl(HW_DRIVE_PINV_MASK << shift, hwdrive);
225 hwdrive + HW_STMP3xxx_CLR);
226 else 224 else
227 __raw_writel(HW_DRIVE_PINV_MASK << shift, 225 stmp3xxx_setl(HW_DRIVE_PINV_MASK << shift, hwdrive);
228 hwdrive + HW_STMP3xxx_SET);
229} 226}
230 227
231void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label) 228void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label)
@@ -245,8 +242,10 @@ void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label)
245 242
246 pr_debug("%s: changing 0x%x bit in 0x%p register\n", 243 pr_debug("%s: changing 0x%x bit in 0x%p register\n",
247 __func__, 1 << pin, hwpull); 244 __func__, 1 << pin, hwpull);
248 __raw_writel(1 << pin, 245 if (enable)
249 hwpull + (enable ? HW_STMP3xxx_SET : HW_STMP3xxx_CLR)); 246 stmp3xxx_setl(1 << pin, hwpull);
247 else
248 stmp3xxx_clearl(1 << pin, hwpull);
250} 249}
251 250
252int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label) 251int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label)
@@ -290,8 +289,8 @@ void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun)
290 shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN; 289 shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
291 pr_debug("%s: writing 0x%x to 0x%p register\n", 290 pr_debug("%s: writing 0x%x to 0x%p register\n",
292 __func__, val << shift, hwmux); 291 __func__, val << shift, hwmux);
293 __raw_writel(HW_MUXSEL_PINFUN_MASK << shift, hwmux + HW_STMP3xxx_CLR); 292 stmp3xxx_clearl(HW_MUXSEL_PINFUN_MASK << shift, hwmux);
294 __raw_writel(val << shift, hwmux + HW_STMP3xxx_SET); 293 stmp3xxx_setl(val << shift, hwmux);
295} 294}
296 295
297void stmp3xxx_release_pin(unsigned id, const char *label) 296void stmp3xxx_release_pin(unsigned id, const char *label)
@@ -388,10 +387,15 @@ static int stmp3xxx_set_irqtype(unsigned irq, unsigned type)
388 __func__, type); 387 __func__, type);
389 return -ENXIO; 388 return -ENXIO;
390 } 389 }
391 __raw_writel(1 << gpio, 390
392 pm->irqlevel + (l ? HW_STMP3xxx_SET : HW_STMP3xxx_CLR)); 391 if (l)
393 __raw_writel(1 << gpio, 392 stmp3xxx_setl(1 << gpio, pm->irqlevel);
394 pm->irqpolarity + (p ? HW_STMP3xxx_SET : HW_STMP3xxx_CLR)); 393 else
394 stmp3xxx_clearl(1 << gpio, pm->irqlevel);
395 if (p)
396 stmp3xxx_setl(1 << gpio, pm->irqpolarity);
397 else
398 stmp3xxx_clearl(1 << gpio, pm->irqpolarity);
395 return 0; 399 return 0;
396} 400}
397 401
@@ -402,8 +406,8 @@ static void stmp3xxx_pin_ack_irq(unsigned irq)
402 unsigned gpio; 406 unsigned gpio;
403 407
404 stmp3xxx_irq_to_gpio(irq, &pm, &gpio); 408 stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
405 stat = __raw_readl(pm->irqstat) & (1<<gpio); 409 stat = __raw_readl(pm->irqstat) & (1 << gpio);
406 __raw_writel(stat, pm->irqstat + HW_STMP3xxx_CLR); 410 stmp3xxx_clearl(stat, pm->irqstat);
407} 411}
408 412
409static void stmp3xxx_pin_mask_irq(unsigned irq) 413static void stmp3xxx_pin_mask_irq(unsigned irq)
@@ -412,8 +416,8 @@ static void stmp3xxx_pin_mask_irq(unsigned irq)
412 unsigned gpio; 416 unsigned gpio;
413 417
414 stmp3xxx_irq_to_gpio(irq, &pm, &gpio); 418 stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
415 __raw_writel(1 << gpio, pm->irqen + HW_STMP3xxx_CLR); 419 stmp3xxx_clearl(1 << gpio, pm->irqen);
416 __raw_writel(1 << gpio, pm->pin2irq + HW_STMP3xxx_CLR); 420 stmp3xxx_clearl(1 << gpio, pm->pin2irq);
417} 421}
418 422
419static void stmp3xxx_pin_unmask_irq(unsigned irq) 423static void stmp3xxx_pin_unmask_irq(unsigned irq)
@@ -422,8 +426,8 @@ static void stmp3xxx_pin_unmask_irq(unsigned irq)
422 unsigned gpio; 426 unsigned gpio;
423 427
424 stmp3xxx_irq_to_gpio(irq, &pm, &gpio); 428 stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
425 __raw_writel(1 << gpio, pm->irqen + HW_STMP3xxx_SET); 429 stmp3xxx_setl(1 << gpio, pm->irqen);
426 __raw_writel(1 << gpio, pm->pin2irq + HW_STMP3xxx_SET); 430 stmp3xxx_setl(1 << gpio, pm->pin2irq);
427} 431}
428 432
429static inline 433static inline
@@ -443,7 +447,7 @@ static int stmp3xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
443 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); 447 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
444 unsigned v; 448 unsigned v;
445 449
446 v = __raw_readl(pm->hw_gpio_read) & (1 << offset); 450 v = __raw_readl(pm->hw_gpio_in) & (1 << offset);
447 return v ? 1 : 0; 451 return v ? 1 : 0;
448} 452}
449 453
@@ -451,14 +455,17 @@ static void stmp3xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int v)
451{ 455{
452 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); 456 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
453 457
454 __raw_writel(1 << offset, v ? pm->hw_gpio_set : pm->hw_gpio_clr); 458 if (v)
459 stmp3xxx_setl(1 << offset, pm->hw_gpio_out);
460 else
461 stmp3xxx_clearl(1 << offset, pm->hw_gpio_out);
455} 462}
456 463
457static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v) 464static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v)
458{ 465{
459 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); 466 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
460 467
461 __raw_writel(1 << offset, pm->hw_gpio_doe + HW_STMP3xxx_SET); 468 stmp3xxx_setl(1 << offset, pm->hw_gpio_doe);
462 stmp3xxx_gpio_set(chip, offset, v); 469 stmp3xxx_gpio_set(chip, offset, v);
463 return 0; 470 return 0;
464} 471}
@@ -467,7 +474,7 @@ static int stmp3xxx_gpio_input(struct gpio_chip *chip, unsigned offset)
467{ 474{
468 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); 475 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
469 476
470 __raw_writel(1 << offset, pm->hw_gpio_doe + HW_STMP3xxx_CLR); 477 stmp3xxx_clearl(1 << offset, pm->hw_gpio_doe);
471 return 0; 478 return 0;
472} 479}
473 480
diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c
index 7d872f0aee70..063c7bc0e740 100644
--- a/arch/arm/plat-stmp3xxx/timer.c
+++ b/arch/arm/plat-stmp3xxx/timer.c
@@ -26,6 +26,7 @@
26 26
27#include <asm/mach/time.h> 27#include <asm/mach/time.h>
28#include <mach/stmp3xxx.h> 28#include <mach/stmp3xxx.h>
29#include <mach/platform.h>
29#include <mach/regs-timrot.h> 30#include <mach/regs-timrot.h>
30 31
31static irqreturn_t 32static irqreturn_t
@@ -33,13 +34,22 @@ stmp3xxx_timer_interrupt(int irq, void *dev_id)
33{ 34{
34 struct clock_event_device *c = dev_id; 35 struct clock_event_device *c = dev_id;
35 36
36 if (HW_TIMROT_TIMCTRLn_RD(0) & (1<<15)) { 37 /* timer 0 */
37 HW_TIMROT_TIMCTRLn_CLR(0, (1<<15)); 38 if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) &
39 BM_TIMROT_TIMCTRLn_IRQ) {
40 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
41 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
38 c->event_handler(c); 42 c->event_handler(c);
39 } else if (HW_TIMROT_TIMCTRLn_RD(1) & (1<<15)) { 43 }
40 HW_TIMROT_TIMCTRLn_CLR(1, (1<<15)); 44
41 HW_TIMROT_TIMCTRLn_CLR(1, BM_TIMROT_TIMCTRLn_IRQ_EN); 45 /* timer 1 */
42 HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); 46 else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1)
47 & BM_TIMROT_TIMCTRLn_IRQ) {
48 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
49 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
50 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN,
51 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
52 __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
43 } 53 }
44 54
45 return IRQ_HANDLED; 55 return IRQ_HANDLED;
@@ -47,14 +57,16 @@ stmp3xxx_timer_interrupt(int irq, void *dev_id)
47 57
48static cycle_t stmp3xxx_clock_read(struct clocksource *cs) 58static cycle_t stmp3xxx_clock_read(struct clocksource *cs)
49{ 59{
50 return ~((HW_TIMROT_TIMCOUNTn_RD(1) & 0xFFFF0000) >> 16); 60 return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1)
61 & 0xFFFF0000) >> 16);
51} 62}
52 63
53static int 64static int
54stmp3xxx_timrot_set_next_event(unsigned long delta, 65stmp3xxx_timrot_set_next_event(unsigned long delta,
55 struct clock_event_device *dev) 66 struct clock_event_device *dev)
56{ 67{
57 HW_TIMROT_TIMCOUNTn_WR(0, delta); /* reload */ 68 /* reload the timer */
69 __raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
58 return 0; 70 return 0;
59} 71}
60 72
@@ -102,25 +114,29 @@ static void __init stmp3xxx_init_timer(void)
102 ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot); 114 ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);
103 ckevt_timrot.cpumask = cpumask_of(0); 115 ckevt_timrot.cpumask = cpumask_of(0);
104 116
105 HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST | 117 stmp3xxx_reset_block(REGS_TIMROT_BASE, false);
106 BM_TIMROT_ROTCTRL_CLKGATE); 118
107 HW_TIMROT_TIMCOUNTn_WR(0, 0); 119 /* clear two timers */
108 HW_TIMROT_TIMCOUNTn_WR(1, 0); 120 __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
109 121 __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
110 HW_TIMROT_TIMCTRLn_WR(0, 122
111 (BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */ 123 /* configure them */
112 BF_TIMROT_TIMCTRLn_PRESCALE(0) | 124 __raw_writel(
113 BM_TIMROT_TIMCTRLn_RELOAD | 125 (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
114 BM_TIMROT_TIMCTRLn_UPDATE | 126 BM_TIMROT_TIMCTRLn_RELOAD |
115 BM_TIMROT_TIMCTRLn_IRQ_EN)); 127 BM_TIMROT_TIMCTRLn_UPDATE |
116 HW_TIMROT_TIMCTRLn_WR(1, 128 BM_TIMROT_TIMCTRLn_IRQ_EN,
117 (BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */ 129 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
118 BF_TIMROT_TIMCTRLn_PRESCALE(0) | 130 __raw_writel(
119 BM_TIMROT_TIMCTRLn_RELOAD | 131 (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
120 BM_TIMROT_TIMCTRLn_UPDATE)); 132 BM_TIMROT_TIMCTRLn_RELOAD |
121 133 BM_TIMROT_TIMCTRLn_UPDATE |
122 HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1); 134 BM_TIMROT_TIMCTRLn_IRQ_EN,
123 HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */ 135 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
136
137 __raw_writel(CLOCK_TICK_RATE / HZ - 1,
138 REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
139 __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
124 140
125 setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq); 141 setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq);
126 142
@@ -132,30 +148,31 @@ static void __init stmp3xxx_init_timer(void)
132 148
133void stmp3xxx_suspend_timer(void) 149void stmp3xxx_suspend_timer(void)
134{ 150{
135 HW_TIMROT_TIMCTRLn_CLR(0, BM_TIMROT_TIMCTRLn_IRQ_EN); 151 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ,
136 HW_TIMROT_TIMCTRLn_CLR(0, (1<<15)); 152 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
137 HW_TIMROT_ROTCTRL_SET(BM_TIMROT_ROTCTRL_CLKGATE); 153 stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE,
154 REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
138} 155}
139 156
140void stmp3xxx_resume_timer(void) 157void stmp3xxx_resume_timer(void)
141{ 158{
142 HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST | 159 stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE,
143 BM_TIMROT_ROTCTRL_CLKGATE); 160 REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
144 161 __raw_writel(
145 162 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */
146 HW_TIMROT_TIMCTRLn_WR(0, 163 BM_TIMROT_TIMCTRLn_RELOAD |
147 (BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */ 164 BM_TIMROT_TIMCTRLn_UPDATE |
148 BF_TIMROT_TIMCTRLn_PRESCALE(0) | 165 BM_TIMROT_TIMCTRLn_IRQ_EN,
149 BM_TIMROT_TIMCTRLn_UPDATE | 166 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
150 BM_TIMROT_TIMCTRLn_IRQ_EN)); 167 __raw_writel(
151 HW_TIMROT_TIMCTRLn_WR(1, 168 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */
152 (BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */ 169 BM_TIMROT_TIMCTRLn_RELOAD |
153 BF_TIMROT_TIMCTRLn_PRESCALE(0) | 170 BM_TIMROT_TIMCTRLn_UPDATE |
154 BM_TIMROT_TIMCTRLn_RELOAD | 171 BM_TIMROT_TIMCTRLn_IRQ_EN,
155 BM_TIMROT_TIMCTRLn_UPDATE)); 172 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
156 173 __raw_writel(CLOCK_TICK_RATE / HZ - 1,
157 HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1); 174 REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
158 HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */ 175 __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
159} 176}
160 177
161#else 178#else
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 15:20:23 -0400