3 files changed, 4 insertions, 133 deletions

diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 1e4fa3da3f70..6420e8df4e45 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -113,11 +113,7 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 }
 #endif
 
-extern void pcibios_resource_to_bus(struct pci_dev *dev,
-        struct pci_bus_region *region, struct resource *res);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                                    struct pci_bus_region *region);
+#define ARCH_HAS_GENERIC_PCI_OFFSETS
 
 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index acacd1407c63..9553b14002dd 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -51,67 +51,6 @@ static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
          qube_raq_galileo_early_fixup);
 
-static void __devinit cobalt_legacy_ide_resource_fixup(struct pci_dev *dev,
-                                                       struct resource *res)
-{
-        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
-        unsigned long offset = hose->io_offset;
-        struct resource orig = *res;
-
-        if (!(res->flags & IORESOURCE_IO) ||
-            !(res->flags & IORESOURCE_PCI_FIXED))
-                return;
-
-        res->start -= offset;
-        res->end -= offset;
-        dev_printk(KERN_DEBUG, &dev->dev, "converted legacy %pR to bus %pR\n",
-                   &orig, res);
-}
-
-static void __devinit cobalt_legacy_ide_fixup(struct pci_dev *dev)
-{
-        u32 class;
-        u8 progif;
-
-        /*
-         * If the IDE controller is in legacy mode, pci_setup_device() fills in
-         * the resources with the legacy addresses that normally appear on the
-         * PCI bus, just as if we had read them from a BAR.
-         *
-         * However, with the GT-64111, those legacy addresses, e.g., 0x1f0,
-         * will never appear on the PCI bus because it converts memory accesses
-         * in the PCI I/O region (which is never at address zero) into I/O port
-         * accesses with no address translation.
-         *
-         * For example, if GT_DEF_PCI0_IO_BASE is 0x10000000, a load or store
-         * to physical address 0x100001f0 will become a PCI access to I/O port
-         * 0x100001f0.  There's no way to generate an access to I/O port 0x1f0,
-         * but the VT82C586 IDE controller does respond at 0x100001f0 because
-         * it only decodes the low 24 bits of the address.
-         *
-         * When this quirk runs, the pci_dev resources should contain bus
-         * addresses, not Linux I/O port numbers, so convert legacy addresses
-         * like 0x1f0 to bus addresses like 0x100001f0.  Later, we'll convert
-         * them back with pcibios_fixup_bus() or pcibios_bus_to_resource().
-         */
-        class = dev->class >> 8;
-        if (class != PCI_CLASS_STORAGE_IDE)
-                return;
-
-        pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
-        if ((progif & 1) == 0) {
-                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[0]);
-                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[1]);
-        }
-        if ((progif & 4) == 0) {
-                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[2]);
-                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[3]);
-        }
-}
-
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
-          cobalt_legacy_ide_fixup);
-
 static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
 {
         unsigned short cfgword;
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 19f6d194a568..0514866fa925 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -88,8 +88,9 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
         if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
                 next_busno = (*hose->get_busno)();
 
-        pci_add_resource(&resources, hose->mem_resource);
-        pci_add_resource(&resources, hose->io_resource);
+        pci_add_resource_offset(&resources,
+                                hose->mem_resource, hose->mem_offset);
+        pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset);
         bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
                                 &resources);
         if (!bus)
@@ -247,45 +248,13 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
         return pcibios_plat_dev_init(dev);
 }
 
-static void pcibios_fixup_device_resources(struct pci_dev *dev,
-        struct pci_bus *bus)
-{
-        /* Update device resources.  */
-        struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
-        unsigned long offset = 0;
-        int i;
-
-        for (i = 0; i < PCI_NUM_RESOURCES; i++) {
-                if (!dev->resource[i].start)
-                        continue;
-                if (dev->resource[i].flags & IORESOURCE_IO)
-                        offset = hose->io_offset;
-                else if (dev->resource[i].flags & IORESOURCE_MEM)
-                        offset = hose->mem_offset;
-
-                dev->resource[i].start += offset;
-                dev->resource[i].end += offset;
-        }
-}
-
 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
 {
-        /* Propagate hose info into the subordinate devices.  */
-
-        struct list_head *ln;
         struct pci_dev *dev = bus->self;
 
         if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
             (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
                 pci_read_bridge_bases(bus);
-                pcibios_fixup_device_resources(dev, bus);
-        }
-
-        for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
-                dev = pci_dev_b(ln);
-
-                if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
-                        pcibios_fixup_device_resources(dev, bus);
         }
 }
 
@@ -295,40 +264,7 @@ pcibios_update_irq(struct pci_dev *dev, int irq)
         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 }
 
-void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                         struct resource *res)
-{
-        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = hose->io_offset;
-        else if (res->flags & IORESOURCE_MEM)
-                offset = hose->mem_offset;
-
-        region->start = res->start - offset;
-        region->end = res->end - offset;
-}
-
-void __devinit
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                        struct pci_bus_region *region)
-{
-        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = hose->io_offset;
-        else if (res->flags & IORESOURCE_MEM)
-                offset = hose->mem_offset;
-
-        res->start = region->start + offset;
-        res->end = region->end + offset;
-}
-
 #ifdef CONFIG_HOTPLUG
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-EXPORT_SYMBOL(pcibios_bus_to_resource);
 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
 #endif