3 files changed, 20 insertions, 16 deletions

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index ee845fad939b..46e1d7ef163f 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -87,9 +87,9 @@
                 interrupts = <1 9 0xf04>;
         };
 
-        gpio0: gpio@ffc40000 {
+        gpio0: gpio@e6050000 {
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
-                reg = <0 0xffc40000 0 0x2c>;
+                reg = <0 0xe6050000 0 0x50>;
                 interrupt-parent = <&gic>;
                 interrupts = <0 4 0x4>;
                 #gpio-cells = <2>;
@@ -99,9 +99,9 @@
                 interrupt-controller;
         };
 
-        gpio1: gpio@ffc41000 {
+        gpio1: gpio@e6051000 {
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
-                reg = <0 0xffc41000 0 0x2c>;
+                reg = <0 0xe6051000 0 0x50>;
                 interrupt-parent = <&gic>;
                 interrupts = <0 5 0x4>;
                 #gpio-cells = <2>;
@@ -111,9 +111,9 @@
                 interrupt-controller;
         };
 
-        gpio2: gpio@ffc42000 {
+        gpio2: gpio@e6052000 {
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
-                reg = <0 0xffc42000 0 0x2c>;
+                reg = <0 0xe6052000 0 0x50>;
                 interrupt-parent = <&gic>;
                 interrupts = <0 6 0x4>;
                 #gpio-cells = <2>;
@@ -123,9 +123,9 @@
                 interrupt-controller;
         };
 
-        gpio3: gpio@ffc43000 {
+        gpio3: gpio@e6053000 {
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
-                reg = <0 0xffc43000 0 0x2c>;
+                reg = <0 0xe6053000 0 0x50>;
                 interrupt-parent = <&gic>;
                 interrupts = <0 7 0x4>;
                 #gpio-cells = <2>;
@@ -135,9 +135,9 @@
                 interrupt-controller;
         };
 
-        gpio4: gpio@ffc44000 {
+        gpio4: gpio@e6054000 {
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
-                reg = <0 0xffc44000 0 0x2c>;
+                reg = <0 0xe6054000 0 0x50>;
                 interrupt-parent = <&gic>;
                 interrupts = <0 8 0x4>;
                 #gpio-cells = <2>;
@@ -147,9 +147,9 @@
                 interrupt-controller;
         };
 
-        gpio5: gpio@ffc45000 {
+        gpio5: gpio@e6055000 {
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
-                reg = <0 0xffc45000 0 0x2c>;
+                reg = <0 0xe6055000 0 0x50>;
                 interrupt-parent = <&gic>;
                 interrupts = <0 9 0x4>;
                 #gpio-cells = <2>;
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index a8d3ce646fb9..e0406fd37390 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -245,7 +245,9 @@ static void __init lager_init(void)
 {
         lager_add_standard_devices();
 
-        phy_register_fixup_for_id("r8a7790-ether-ff:01", lager_ksz8041_fixup);
+        if (IS_ENABLED(CONFIG_PHYLIB))
+                phy_register_fixup_for_id("r8a7790-ether-ff:01",
+                                          lager_ksz8041_fixup);
 }
 
 static const char * const lager_boards_compat_dt[] __initconst = {
diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c
index 82cec63a9011..3ee78f02e5d7 100644
--- a/drivers/irqchip/irq-renesas-intc-irqpin.c
+++ b/drivers/irqchip/irq-renesas-intc-irqpin.c
@@ -149,8 +149,9 @@ static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
 static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
                                          int irq, int do_mask)
 {
-        int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */
-        int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */
+        /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
+        int bitfield_width = 4;
+        int shift = 32 - (irq + 1) * bitfield_width;
 
         intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
                                       shift, bitfield_width,
@@ -159,8 +160,9 @@ static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
 
 static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
 {
+        /* The SENSE register is assumed to be 32-bit. */
         int bitfield_width = p->config.sense_bitfield_width;
-        int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */
+        int shift = 32 - (irq + 1) * bitfield_width;
 
         dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);