diff options
| -rw-r--r-- | sound/soc/davinci/davinci-mcasp.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c index 1456a173c20f..2b637e05af3e 100644 --- a/sound/soc/davinci/davinci-mcasp.c +++ b/sound/soc/davinci/davinci-mcasp.c | |||
| @@ -434,7 +434,8 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
| 434 | mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); | 434 | mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
| 435 | mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | 435 | mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); |
| 436 | 436 | ||
| 437 | mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26)); | 437 | mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, |
| 438 | ACLKX | AHCLKX | AFSX); | ||
| 438 | break; | 439 | break; |
| 439 | case SND_SOC_DAIFMT_CBM_CFS: | 440 | case SND_SOC_DAIFMT_CBM_CFS: |
| 440 | /* codec is clock master and frame slave */ | 441 | /* codec is clock master and frame slave */ |
| @@ -444,7 +445,8 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
| 444 | mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); | 445 | mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
| 445 | mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | 446 | mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); |
| 446 | 447 | ||
| 447 | mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x2d << 26)); | 448 | mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, |
| 449 | ACLKX | AFSX | ACLKR | AFSR); | ||
| 448 | break; | 450 | break; |
| 449 | case SND_SOC_DAIFMT_CBM_CFM: | 451 | case SND_SOC_DAIFMT_CBM_CFM: |
| 450 | /* codec is clock and frame master */ | 452 | /* codec is clock and frame master */ |
| @@ -454,7 +456,8 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
| 454 | mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); | 456 | mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
| 455 | mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | 457 | mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); |
| 456 | 458 | ||
| 457 | mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, (0x3f << 26)); | 459 | mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, |
| 460 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); | ||
| 458 | break; | 461 | break; |
| 459 | 462 | ||
| 460 | default: | 463 | default: |
