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-rw-r--r--Documentation/devicetree/bindings/arm/omap/omap.txt53
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt6
-rw-r--r--arch/arm/boot/dts/exynos4210-origen.dts2
-rw-r--r--arch/arm/boot/dts/exynos4412-odroidx.dts5
-rw-r--r--arch/arm/boot/dts/exynos4412-origen.dts7
-rw-r--r--arch/arm/boot/dts/exynos4412-trats2.dts20
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi7
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi13
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts2
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts3
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5420-pinctrl.dtsi2
-rw-r--r--arch/arm/boot/dts/qcom-msm8660-surf.dts4
-rw-r--r--arch/arm/boot/dts/qcom-msm8960-cdp.dts2
-rw-r--r--arch/arm/boot/dts/ste-u300.dts6
-rw-r--r--arch/arm/configs/omap2plus_defconfig3
-rw-r--r--arch/arm/mach-at91/sam9_smc.c2
-rw-r--r--arch/arm/mach-bcm2835/Kconfig2
-rw-r--r--arch/arm/mach-msm/board-trout.c12
-rw-r--r--arch/arm/mach-mvebu/Makefile2
-rw-r--r--arch/arm/mach-mvebu/armada-370-xp.c32
-rw-r--r--arch/arm/mach-mvebu/mvebu-soc-id.c119
-rw-r--r--arch/arm/mach-mvebu/mvebu-soc-id.h32
-rw-r--r--arch/arm/mach-omap2/board-generic.c7
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c50
-rw-r--r--arch/arm/mach-s3c64xx/mach-mini6410.c10
-rw-r--r--arch/arm/mach-u300/regulator.c4
-rw-r--r--arch/arm/mach-u300/timer.c38
-rw-r--r--arch/arm/plat-samsung/include/plat/uncompress.h2
-rw-r--r--drivers/clk/samsung/clk-exynos4.c3
-rw-r--r--drivers/i2c/busses/i2c-mv64xxx.c5
-rw-r--r--drivers/irqchip/irq-sirfsoc.c3
32 files changed, 381 insertions, 79 deletions
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index 808c1543b0f8..34dc40cffdfd 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -31,6 +31,59 @@ spinlock@1 {
31 ti,hwmods = "spinlock"; 31 ti,hwmods = "spinlock";
32}; 32};
33 33
34SoC Type (optional):
35
36- General Purpose devices
37 compatible = "ti,gp"
38- High Security devices
39 compatible = "ti,hs"
40
41SoC Families:
42
43- OMAP2 generic - defaults to OMAP2420
44 compatible = "ti,omap2"
45- OMAP3 generic - defaults to OMAP3430
46 compatible = "ti,omap3"
47- OMAP4 generic - defaults to OMAP4430
48 compatible = "ti,omap4"
49- OMAP5 generic - defaults to OMAP5430
50 compatible = "ti,omap5"
51- DRA7 generic - defaults to DRA742
52 compatible = "ti,dra7"
53- AM43x generic - defaults to AM4372
54 compatible = "ti,am43"
55
56SoCs:
57
58- OMAP2420
59 compatible = "ti,omap2420", "ti,omap2"
60- OMAP2430
61 compatible = "ti,omap2430", "ti,omap2"
62
63- OMAP3430
64 compatible = "ti,omap3430", "ti,omap3"
65- AM3517
66 compatible = "ti,am3517", "ti,omap3"
67- OMAP3630
68 compatible = "ti,omap36xx", "ti,omap3"
69- AM33xx
70 compatible = "ti,am33xx", "ti,omap3"
71
72- OMAP4430
73 compatible = "ti,omap4430", "ti,omap4"
74- OMAP4460
75 compatible = "ti,omap4460", "ti,omap4"
76
77- OMAP5430
78 compatible = "ti,omap5430", "ti,omap5"
79- OMAP5432
80 compatible = "ti,omap5432", "ti,omap5"
81
82- DRA742
83 compatible = "ti,dra7xx", "ti,dra7"
84
85- AM4372
86 compatible = "ti,am4372", "ti,am43"
34 87
35Boards: 88Boards:
36 89
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt b/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
index 82e8f6f17179..582b4652a82a 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
@@ -5,7 +5,11 @@ Required properties :
5 5
6 - reg : Offset and length of the register set for the device 6 - reg : Offset and length of the register set for the device
7 - compatible : Should be "marvell,mv64xxx-i2c" or "allwinner,sun4i-i2c" 7 - compatible : Should be "marvell,mv64xxx-i2c" or "allwinner,sun4i-i2c"
8 or "marvell,mv78230-i2c" 8 or "marvell,mv78230-i2c" or "marvell,mv78230-a0-i2c"
9 Note: Only use "marvell,mv78230-a0-i2c" for a very rare,
10 initial version of the SoC which had broken offload
11 support. Linux auto-detects this and sets it
12 appropriately.
9 - interrupts : The interrupt number 13 - interrupts : The interrupt number
10 14
11Optional properties : 15Optional properties :
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 1a12fb23767c..2aa13cb3bbed 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -313,7 +313,7 @@
313 display-timings { 313 display-timings {
314 native-mode = <&timing0>; 314 native-mode = <&timing0>;
315 timing0: timing { 315 timing0: timing {
316 clock-frequency = <50000>; 316 clock-frequency = <47500000>;
317 hactive = <1024>; 317 hactive = <1024>;
318 vactive = <600>; 318 vactive = <600>;
319 hfront-porch = <64>; 319 hfront-porch = <64>;
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 46c678ee119c..8aad5f72ced7 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -38,9 +38,7 @@
38 }; 38 };
39 }; 39 };
40 40
41 mshc@12550000 { 41 mmc@12550000 {
42 #address-cells = <1>;
43 #size-cells = <0>;
44 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; 42 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
45 pinctrl-names = "default"; 43 pinctrl-names = "default";
46 vmmc-supply = <&ldo20_reg &buck8_reg>; 44 vmmc-supply = <&ldo20_reg &buck8_reg>;
@@ -49,7 +47,6 @@
49 num-slots = <1>; 47 num-slots = <1>;
50 supports-highspeed; 48 supports-highspeed;
51 broken-cd; 49 broken-cd;
52 fifo-depth = <0x80>;
53 card-detect-delay = <200>; 50 card-detect-delay = <200>;
54 samsung,dw-mshc-ciu-div = <3>; 51 samsung,dw-mshc-ciu-div = <3>;
55 samsung,dw-mshc-sdr-timing = <2 3>; 52 samsung,dw-mshc-sdr-timing = <2 3>;
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index d65984c440f6..6bc053924e9e 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -122,9 +122,7 @@
122 status = "okay"; 122 status = "okay";
123 }; 123 };
124 124
125 mshc@12550000 { 125 mmc@12550000 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; 126 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
129 pinctrl-names = "default"; 127 pinctrl-names = "default";
130 status = "okay"; 128 status = "okay";
@@ -132,7 +130,6 @@
132 num-slots = <1>; 130 num-slots = <1>;
133 supports-highspeed; 131 supports-highspeed;
134 broken-cd; 132 broken-cd;
135 fifo-depth = <0x80>;
136 card-detect-delay = <200>; 133 card-detect-delay = <200>;
137 samsung,dw-mshc-ciu-div = <3>; 134 samsung,dw-mshc-ciu-div = <3>;
138 samsung,dw-mshc-sdr-timing = <2 3>; 135 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -159,7 +156,7 @@
159 display-timings { 156 display-timings {
160 native-mode = <&timing0>; 157 native-mode = <&timing0>;
161 timing0: timing { 158 timing0: timing {
162 clock-frequency = <50000>; 159 clock-frequency = <47500000>;
163 hactive = <1024>; 160 hactive = <1024>;
164 vactive = <600>; 161 vactive = <600>;
165 hfront-porch = <64>; 162 hfront-porch = <64>;
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index fb7b9ae5f399..890ad275cb85 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -442,13 +442,25 @@
442 }; 442 };
443 }; 443 };
444 444
445 sdhci@12510000 { 445 mmc@12550000 {
446 bus-width = <8>; 446 num-slots = <1>;
447 supports-highspeed;
448 broken-cd;
447 non-removable; 449 non-removable;
448 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; 450 card-detect-delay = <200>;
449 pinctrl-names = "default";
450 vmmc-supply = <&vemmc_reg>; 451 vmmc-supply = <&vemmc_reg>;
452 clock-frequency = <400000000>;
453 samsung,dw-mshc-ciu-div = <0>;
454 samsung,dw-mshc-sdr-timing = <2 3>;
455 samsung,dw-mshc-ddr-timing = <1 2>;
456 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
457 pinctrl-names = "default";
451 status = "okay"; 458 status = "okay";
459
460 slot@0 {
461 reg = <0>;
462 bus-width = <8>;
463 };
452 }; 464 };
453 465
454 serial@13800000 { 466 serial@13800000 {
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index e743e677a9e2..85812bd95a86 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -61,11 +61,4 @@
61 }; 61 };
62 }; 62 };
63 63
64 mshc@12550000 {
65 compatible = "samsung,exynos4412-dw-mshc";
66 reg = <0x12550000 0x1000>;
67 interrupts = <0 77 0>;
68 #address-cells = <1>;
69 #size-cells = <0>;
70 };
71}; 64};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index ad531fe6ab95..1917c829e64e 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -28,6 +28,7 @@
28 pinctrl3 = &pinctrl_3; 28 pinctrl3 = &pinctrl_3;
29 fimc-lite0 = &fimc_lite_0; 29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1; 30 fimc-lite1 = &fimc_lite_1;
31 mshc0 = &mshc_0;
31 }; 32 };
32 33
33 pd_isp: isp-power-domain@10023CA0 { 34 pd_isp: isp-power-domain@10023CA0 {
@@ -176,4 +177,16 @@
176 }; 177 };
177 }; 178 };
178 }; 179 };
180
181 mshc_0: mmc@12550000 {
182 compatible = "samsung,exynos4412-dw-mshc";
183 reg = <0x12550000 0x1000>;
184 interrupts = <0 77 0>;
185 #address-cells = <1>;
186 #size-cells = <0>;
187 fifo-depth = <0x80>;
188 clocks = <&clock 301>, <&clock 149>;
189 clock-names = "biu", "ciu";
190 status = "disabled";
191 };
179}; 192};
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 684527087aa4..bbfb23f942e1 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -302,11 +302,13 @@
302 buck7_reg: BUCK7 { 302 buck7_reg: BUCK7 {
303 regulator-name = "PVDD_BUCK7"; 303 regulator-name = "PVDD_BUCK7";
304 regulator-always-on; 304 regulator-always-on;
305 op_mode = <1>;
305 }; 306 };
306 307
307 buck8_reg: BUCK8 { 308 buck8_reg: BUCK8 {
308 regulator-name = "PVDD_BUCK8"; 309 regulator-name = "PVDD_BUCK8";
309 regulator-always-on; 310 regulator-always-on;
311 op_mode = <1>;
310 }; 312 };
311 313
312 buck9_reg: BUCK9 { 314 buck9_reg: BUCK9 {
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index fd711e245e8d..c65f52a6dcea 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -85,7 +85,7 @@
85 keypad,num-rows = <8>; 85 keypad,num-rows = <8>;
86 keypad,num-columns = <13>; 86 keypad,num-columns = <13>;
87 google,needs-ghost-filter; 87 google,needs-ghost-filter;
88 linux,keymap = <0x0001003a /* CAPSLK */ 88 linux,keymap = <0x0001007d /* L_META */
89 0x0002003b /* F1 */ 89 0x0002003b /* F1 */
90 0x00030030 /* B */ 90 0x00030030 /* B */
91 0x00040044 /* F10 */ 91 0x00040044 /* F10 */
@@ -130,6 +130,7 @@
130 0x04060024 /* J */ 130 0x04060024 /* J */
131 0x04080027 /* ; */ 131 0x04080027 /* ; */
132 0x04090026 /* L */ 132 0x04090026 /* L */
133 0x040a002b /* \ */
133 0x040b001c /* ENTER */ 134 0x040b001c /* ENTER */
134 135
135 0x0501002c /* Z */ 136 0x0501002c /* Z */
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 177becde7a26..6feaa1c454fa 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -60,11 +60,13 @@
60 device_type = "cpu"; 60 device_type = "cpu";
61 compatible = "arm,cortex-a15"; 61 compatible = "arm,cortex-a15";
62 reg = <0>; 62 reg = <0>;
63 clock-frequency = <1700000000>;
63 }; 64 };
64 cpu@1 { 65 cpu@1 {
65 device_type = "cpu"; 66 device_type = "cpu";
66 compatible = "arm,cortex-a15"; 67 compatible = "arm,cortex-a15";
67 reg = <1>; 68 reg = <1>;
69 clock-frequency = <1700000000>;
68 }; 70 };
69 }; 71 };
70 72
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index e695aba5f73c..e62c8eb57438 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -64,7 +64,7 @@
64 samsung,pins = "gpx0-7"; 64 samsung,pins = "gpx0-7";
65 samsung,pin-function = <3>; 65 samsung,pin-function = <3>;
66 samsung,pin-pud = <0>; 66 samsung,pin-pud = <0>;
67 samaung,pin-drv = <0>; 67 samsung,pin-drv = <0>;
68 }; 68 };
69 }; 69 };
70 70
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 386d42870215..1187185cf25b 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -28,11 +28,11 @@
28 28
29 msmgpio: gpio@800000 { 29 msmgpio: gpio@800000 {
30 compatible = "qcom,msm-gpio"; 30 compatible = "qcom,msm-gpio";
31 reg = <0x00800000 0x1000>; 31 reg = <0x00800000 0x4000>;
32 gpio-controller; 32 gpio-controller;
33 #gpio-cells = <2>; 33 #gpio-cells = <2>;
34 ngpio = <173>; 34 ngpio = <173>;
35 interrupts = <0 32 0x4>; 35 interrupts = <0 16 0x4>;
36 interrupt-controller; 36 interrupt-controller;
37 #interrupt-cells = <2>; 37 #interrupt-cells = <2>;
38 }; 38 };
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index 93e9f7e0b7ad..6ccbac77931e 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -31,7 +31,7 @@
31 gpio-controller; 31 gpio-controller;
32 #gpio-cells = <2>; 32 #gpio-cells = <2>;
33 ngpio = <150>; 33 ngpio = <150>;
34 interrupts = <0 32 0x4>; 34 interrupts = <0 16 0x4>;
35 interrupt-controller; 35 interrupt-controller;
36 #interrupt-cells = <2>; 36 #interrupt-cells = <2>;
37 reg = <0x800000 0x4000>; 37 reg = <0x800000 0x4000>;
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 8a1032c1ffc9..a9da4800daf0 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -307,7 +307,7 @@
307 clocks = <&i2c0_clk>; 307 clocks = <&i2c0_clk>;
308 #address-cells = <1>; 308 #address-cells = <1>;
309 #size-cells = <0>; 309 #size-cells = <0>;
310 ab3100: ab3100@0x48 { 310 ab3100: ab3100@48 {
311 compatible = "stericsson,ab3100"; 311 compatible = "stericsson,ab3100";
312 reg = <0x48>; 312 reg = <0x48>;
313 interrupt-parent = <&vica>; 313 interrupt-parent = <&vica>;
@@ -385,10 +385,10 @@
385 clocks = <&i2c1_clk>; 385 clocks = <&i2c1_clk>;
386 #address-cells = <1>; 386 #address-cells = <1>;
387 #size-cells = <0>; 387 #size-cells = <0>;
388 fwcam0: fwcam@0x10 { 388 fwcam0: fwcam@10 {
389 reg = <0x10>; 389 reg = <0x10>;
390 }; 390 };
391 fwcam1: fwcam@0x5d { 391 fwcam1: fwcam@5d {
392 reg = <0x5d>; 392 reg = <0x5d>;
393 }; 393 };
394 }; 394 };
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index bfa80a11e8c7..3a0b53d225e7 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -208,6 +208,8 @@ CONFIG_SND_DEBUG=y
208CONFIG_SND_USB_AUDIO=m 208CONFIG_SND_USB_AUDIO=m
209CONFIG_SND_SOC=m 209CONFIG_SND_SOC=m
210CONFIG_SND_OMAP_SOC=m 210CONFIG_SND_OMAP_SOC=m
211CONFIG_SND_AM33XX_SOC_EVM=m
212CONFIG_SND_DAVINCI_SOC=m
211CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m 213CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
212CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m 214CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
213CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m 215CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
@@ -222,6 +224,7 @@ CONFIG_USB_TEST=y
222CONFIG_NOP_USB_XCEIV=y 224CONFIG_NOP_USB_XCEIV=y
223CONFIG_OMAP_USB2=y 225CONFIG_OMAP_USB2=y
224CONFIG_OMAP_USB3=y 226CONFIG_OMAP_USB3=y
227CONFIG_AM335X_PHY_USB=y
225CONFIG_USB_GADGET=y 228CONFIG_USB_GADGET=y
226CONFIG_USB_GADGET_DEBUG=y 229CONFIG_USB_GADGET_DEBUG=y
227CONFIG_USB_GADGET_DEBUG_FILES=y 230CONFIG_USB_GADGET_DEBUG_FILES=y
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index 99a0a1d2b7dc..b26156bf15db 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -101,7 +101,7 @@ static void sam9_smc_cs_read(void __iomem *base,
101 /* Pulse register */ 101 /* Pulse register */
102 val = __raw_readl(base + AT91_SMC_PULSE); 102 val = __raw_readl(base + AT91_SMC_PULSE);
103 103
104 config->nwe_setup = val & AT91_SMC_NWEPULSE; 104 config->nwe_pulse = val & AT91_SMC_NWEPULSE;
105 config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8; 105 config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
106 config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16; 106 config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
107 config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24; 107 config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
diff --git a/arch/arm/mach-bcm2835/Kconfig b/arch/arm/mach-bcm2835/Kconfig
index 560045cafc34..d1f9612f8c15 100644
--- a/arch/arm/mach-bcm2835/Kconfig
+++ b/arch/arm/mach-bcm2835/Kconfig
@@ -12,4 +12,4 @@ config ARCH_BCM2835
12 select PINCTRL_BCM2835 12 select PINCTRL_BCM2835
13 help 13 help
14 This enables support for the Broadcom BCM2835 SoC. This SoC is 14 This enables support for the Broadcom BCM2835 SoC. This SoC is
15 use in the Raspberry Pi, and Roku 2 devices. 15 used in the Raspberry Pi and Roku 2 devices.
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index ccf6621bc664..015d544aa017 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -13,6 +13,7 @@
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 * 14 *
15 */ 15 */
16#define pr_fmt(fmt) "%s: " fmt, __func__
16 17
17#include <linux/kernel.h> 18#include <linux/kernel.h>
18#include <linux/init.h> 19#include <linux/init.h>
@@ -68,12 +69,11 @@ static void __init trout_init(void)
68 69
69 platform_add_devices(devices, ARRAY_SIZE(devices)); 70 platform_add_devices(devices, ARRAY_SIZE(devices));
70 71
71#ifdef CONFIG_MMC 72 if (IS_ENABLED(CONFIG_MMC)) {
72 rc = trout_init_mmc(system_rev); 73 rc = trout_init_mmc(system_rev);
73 if (rc) 74 if (rc)
74 printk(KERN_CRIT "%s: MMC init failure (%d)\n", __func__, rc); 75 pr_crit("MMC init failure (%d)\n", rc);
75#endif 76 }
76
77} 77}
78 78
79static struct map_desc trout_io_desc[] __initdata = { 79static struct map_desc trout_io_desc[] __initdata = {
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 2d04f0e21870..878aebe98dcc 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -3,7 +3,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
3 3
4AFLAGS_coherency_ll.o := -Wa,-march=armv7-a 4AFLAGS_coherency_ll.o := -Wa,-march=armv7-a
5 5
6obj-y += system-controller.o 6obj-y += system-controller.o mvebu-soc-id.o
7obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o 7obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o
8obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o 8obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o
9obj-$(CONFIG_SMP) += platsmp.o headsmp.o 9obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index e2acff98e750..f6c9d1d85c14 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -21,6 +21,7 @@
21#include <linux/clocksource.h> 21#include <linux/clocksource.h>
22#include <linux/dma-mapping.h> 22#include <linux/dma-mapping.h>
23#include <linux/mbus.h> 23#include <linux/mbus.h>
24#include <linux/slab.h>
24#include <asm/hardware/cache-l2x0.h> 25#include <asm/hardware/cache-l2x0.h>
25#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
26#include <asm/mach/map.h> 27#include <asm/mach/map.h>
@@ -28,6 +29,7 @@
28#include "armada-370-xp.h" 29#include "armada-370-xp.h"
29#include "common.h" 30#include "common.h"
30#include "coherency.h" 31#include "coherency.h"
32#include "mvebu-soc-id.h"
31 33
32static void __init armada_370_xp_map_io(void) 34static void __init armada_370_xp_map_io(void)
33{ 35{
@@ -45,8 +47,38 @@ static void __init armada_370_xp_timer_and_clk_init(void)
45#endif 47#endif
46} 48}
47 49
50static void __init i2c_quirk(void)
51{
52 struct device_node *np;
53 u32 dev, rev;
54
55 /*
56 * Only revisons more recent than A0 support the offload
57 * mechanism. We can exit only if we are sure that we can
58 * get the SoC revision and it is more recent than A0.
59 */
60 if (mvebu_get_soc_id(&rev, &dev) == 0 && dev > MV78XX0_A0_REV)
61 return;
62
63 for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") {
64 struct property *new_compat;
65
66 new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL);
67
68 new_compat->name = kstrdup("compatible", GFP_KERNEL);
69 new_compat->length = sizeof("marvell,mv78230-a0-i2c");
70 new_compat->value = kstrdup("marvell,mv78230-a0-i2c",
71 GFP_KERNEL);
72
73 of_update_property(np, new_compat);
74 }
75 return;
76}
77
48static void __init armada_370_xp_dt_init(void) 78static void __init armada_370_xp_dt_init(void)
49{ 79{
80 if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
81 i2c_quirk();
50 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 82 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
51} 83}
52 84
diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c
new file mode 100644
index 000000000000..fe4fc1cbdfaf
--- /dev/null
+++ b/arch/arm/mach-mvebu/mvebu-soc-id.c
@@ -0,0 +1,119 @@
1/*
2 * ID and revision information for mvebu SoCs
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 *
12 * All the mvebu SoCs have information related to their variant and
13 * revision that can be read from the PCI control register. This is
14 * done before the PCI initialization to avoid any conflict. Once the
15 * ID and revision are retrieved, the mapping is freed.
16 */
17
18#define pr_fmt(fmt) "mvebu-soc-id: " fmt
19
20#include <linux/clk.h>
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/kernel.h>
24#include <linux/of.h>
25#include <linux/of_address.h>
26#include "mvebu-soc-id.h"
27
28#define PCIE_DEV_ID_OFF 0x0
29#define PCIE_DEV_REV_OFF 0x8
30
31#define SOC_ID_MASK 0xFFFF0000
32#define SOC_REV_MASK 0xFF
33
34static u32 soc_dev_id;
35static u32 soc_rev;
36static bool is_id_valid;
37
38static const struct of_device_id mvebu_pcie_of_match_table[] = {
39 { .compatible = "marvell,armada-xp-pcie", },
40 { .compatible = "marvell,armada-370-pcie", },
41 {},
42};
43
44int mvebu_get_soc_id(u32 *dev, u32 *rev)
45{
46 if (is_id_valid) {
47 *dev = soc_dev_id;
48 *rev = soc_rev;
49 return 0;
50 } else
51 return -1;
52}
53
54static int __init mvebu_soc_id_init(void)
55{
56 struct device_node *np;
57 int ret = 0;
58 void __iomem *pci_base;
59 struct clk *clk;
60 struct device_node *child;
61
62 np = of_find_matching_node(NULL, mvebu_pcie_of_match_table);
63 if (!np)
64 return ret;
65
66 /*
67 * ID and revision are available from any port, so we
68 * just pick the first one
69 */
70 child = of_get_next_child(np, NULL);
71 if (child == NULL) {
72 pr_err("cannot get pci node\n");
73 ret = -ENOMEM;
74 goto clk_err;
75 }
76
77 clk = of_clk_get_by_name(child, NULL);
78 if (IS_ERR(clk)) {
79 pr_err("cannot get clock\n");
80 ret = -ENOMEM;
81 goto clk_err;
82 }
83
84 ret = clk_prepare_enable(clk);
85 if (ret) {
86 pr_err("cannot enable clock\n");
87 goto clk_err;
88 }
89
90 pci_base = of_iomap(child, 0);
91 if (IS_ERR(pci_base)) {
92 pr_err("cannot map registers\n");
93 ret = -ENOMEM;
94 goto res_ioremap;
95 }
96
97 /* SoC ID */
98 soc_dev_id = readl(pci_base + PCIE_DEV_ID_OFF) >> 16;
99
100 /* SoC revision */
101 soc_rev = readl(pci_base + PCIE_DEV_REV_OFF) & SOC_REV_MASK;
102
103 is_id_valid = true;
104
105 pr_info("MVEBU SoC ID=0x%X, Rev=0x%X\n", soc_dev_id, soc_rev);
106
107 iounmap(pci_base);
108
109res_ioremap:
110 clk_disable_unprepare(clk);
111
112clk_err:
113 of_node_put(child);
114 of_node_put(np);
115
116 return ret;
117}
118core_initcall(mvebu_soc_id_init);
119
diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.h b/arch/arm/mach-mvebu/mvebu-soc-id.h
new file mode 100644
index 000000000000..31654252fe35
--- /dev/null
+++ b/arch/arm/mach-mvebu/mvebu-soc-id.h
@@ -0,0 +1,32 @@
1/*
2 * Marvell EBU SoC ID and revision definitions.
3 *
4 * Copyright (C) 2014 Marvell Semiconductor
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __LINUX_MVEBU_SOC_ID_H
12#define __LINUX_MVEBU_SOC_ID_H
13
14/* Armada XP ID */
15#define MV78230_DEV_ID 0x7823
16#define MV78260_DEV_ID 0x7826
17#define MV78460_DEV_ID 0x7846
18
19/* Armada XP Revision */
20#define MV78XX0_A0_REV 0x1
21#define MV78XX0_B0_REV 0x2
22
23#ifdef CONFIG_ARCH_MVEBU
24int mvebu_get_soc_id(u32 *dev, u32 *rev);
25#else
26static inline int mvebu_get_soc_id(u32 *dev, u32 *rev)
27{
28 return -1;
29}
30#endif
31
32#endif /* __LINUX_MVEBU_SOC_ID_H */
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 8d972ff18c56..8e3daa11602b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -78,6 +78,7 @@ MACHINE_END
78 78
79#ifdef CONFIG_ARCH_OMAP3 79#ifdef CONFIG_ARCH_OMAP3
80static const char *omap3_boards_compat[] __initdata = { 80static const char *omap3_boards_compat[] __initdata = {
81 "ti,omap3430",
81 "ti,omap3", 82 "ti,omap3",
82 NULL, 83 NULL,
83}; 84};
@@ -173,6 +174,8 @@ MACHINE_END
173 174
174#ifdef CONFIG_ARCH_OMAP4 175#ifdef CONFIG_ARCH_OMAP4
175static const char *omap4_boards_compat[] __initdata = { 176static const char *omap4_boards_compat[] __initdata = {
177 "ti,omap4460",
178 "ti,omap4430",
176 "ti,omap4", 179 "ti,omap4",
177 NULL, 180 NULL,
178}; 181};
@@ -193,6 +196,8 @@ MACHINE_END
193 196
194#ifdef CONFIG_SOC_OMAP5 197#ifdef CONFIG_SOC_OMAP5
195static const char *omap5_boards_compat[] __initdata = { 198static const char *omap5_boards_compat[] __initdata = {
199 "ti,omap5432",
200 "ti,omap5430",
196 "ti,omap5", 201 "ti,omap5",
197 NULL, 202 NULL,
198}; 203};
@@ -213,6 +218,7 @@ MACHINE_END
213 218
214#ifdef CONFIG_SOC_AM43XX 219#ifdef CONFIG_SOC_AM43XX
215static const char *am43_boards_compat[] __initdata = { 220static const char *am43_boards_compat[] __initdata = {
221 "ti,am4372",
216 "ti,am43", 222 "ti,am43",
217 NULL, 223 NULL,
218}; 224};
@@ -230,6 +236,7 @@ MACHINE_END
230 236
231#ifdef CONFIG_SOC_DRA7XX 237#ifdef CONFIG_SOC_DRA7XX
232static const char *dra7xx_boards_compat[] __initdata = { 238static const char *dra7xx_boards_compat[] __initdata = {
239 "ti,dra7xx",
233 "ti,dra7", 240 "ti,dra7",
234 NULL, 241 NULL,
235}; 242};
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 662c7fd633cc..174caecc3186 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -65,6 +65,22 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
65 return 1; 65 return 1;
66} 66}
67 67
68/* This function will go away once the device-tree convertion is complete */
69static void gpmc_set_legacy(struct omap_nand_platform_data *gpmc_nand_data,
70 struct gpmc_settings *s)
71{
72 /* Enable RD PIN Monitoring Reg */
73 if (gpmc_nand_data->dev_ready) {
74 s->wait_on_read = true;
75 s->wait_on_write = true;
76 }
77
78 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
79 s->device_width = GPMC_DEVWIDTH_16BIT;
80 else
81 s->device_width = GPMC_DEVWIDTH_8BIT;
82}
83
68int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, 84int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
69 struct gpmc_timings *gpmc_t) 85 struct gpmc_timings *gpmc_t)
70{ 86{
@@ -98,32 +114,22 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
98 dev_err(dev, "Unable to set gpmc timings: %d\n", err); 114 dev_err(dev, "Unable to set gpmc timings: %d\n", err);
99 return err; 115 return err;
100 } 116 }
117 }
101 118
102 if (gpmc_nand_data->of_node) { 119 if (gpmc_nand_data->of_node)
103 gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); 120 gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
104 } else { 121 else
105 /* Enable RD PIN Monitoring Reg */ 122 gpmc_set_legacy(gpmc_nand_data, &s);
106 if (gpmc_nand_data->dev_ready) {
107 s.wait_on_read = true;
108 s.wait_on_write = true;
109 }
110 }
111
112 s.device_nand = true;
113 123
114 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) 124 s.device_nand = true;
115 s.device_width = GPMC_DEVWIDTH_16BIT;
116 else
117 s.device_width = GPMC_DEVWIDTH_8BIT;
118 125
119 err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); 126 err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
120 if (err < 0) 127 if (err < 0)
121 goto out_free_cs; 128 goto out_free_cs;
122 129
123 err = gpmc_configure(GPMC_CONFIG_WP, 0); 130 err = gpmc_configure(GPMC_CONFIG_WP, 0);
124 if (err < 0) 131 if (err < 0)
125 goto out_free_cs; 132 goto out_free_cs;
126 }
127 133
128 gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); 134 gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
129 135
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 8c84d3448dac..8d553a418e1c 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -37,7 +37,9 @@
37#include <plat/devs.h> 37#include <plat/devs.h>
38#include <plat/fb.h> 38#include <plat/fb.h>
39#include <linux/platform_data/mtd-nand-s3c2410.h> 39#include <linux/platform_data/mtd-nand-s3c2410.h>
40#include <linux/platform_data/mmc-sdhci-s3c.h>
40#include <plat/regs-serial.h> 41#include <plat/regs-serial.h>
42#include <plat/sdhci.h>
41#include <linux/platform_data/touchscreen-s3c2410.h> 43#include <linux/platform_data/touchscreen-s3c2410.h>
42 44
43#include <video/platform_lcd.h> 45#include <video/platform_lcd.h>
@@ -215,6 +217,13 @@ static struct platform_device mini6410_lcd_powerdev = {
215 .dev.platform_data = &mini6410_lcd_power_data, 217 .dev.platform_data = &mini6410_lcd_power_data,
216}; 218};
217 219
220static struct s3c_sdhci_platdata mini6410_hsmmc1_pdata = {
221 .max_width = 4,
222 .cd_type = S3C_SDHCI_CD_GPIO,
223 .ext_cd_gpio = S3C64XX_GPN(10),
224 .ext_cd_gpio_invert = true,
225};
226
218static struct platform_device *mini6410_devices[] __initdata = { 227static struct platform_device *mini6410_devices[] __initdata = {
219 &mini6410_device_eth, 228 &mini6410_device_eth,
220 &s3c_device_hsmmc0, 229 &s3c_device_hsmmc0,
@@ -322,6 +331,7 @@ static void __init mini6410_machine_init(void)
322 331
323 s3c_nand_set_platdata(&mini6410_nand_info); 332 s3c_nand_set_platdata(&mini6410_nand_info);
324 s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]); 333 s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]);
334 s3c_sdhci1_set_platdata(&mini6410_hsmmc1_pdata);
325 s3c24xx_ts_set_platdata(NULL); 335 s3c24xx_ts_set_platdata(NULL);
326 336
327 /* configure nCS1 width to 16 bits */ 337 /* configure nCS1 width to 16 bits */
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index bf40cd478fe9..0493a845b6bc 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -69,9 +69,9 @@ static int __init __u300_init_boardpower(struct platform_device *pdev)
69 return -ENODEV; 69 return -ENODEV;
70 } 70 }
71 regmap = syscon_node_to_regmap(syscon_np); 71 regmap = syscon_node_to_regmap(syscon_np);
72 if (!regmap) { 72 if (IS_ERR(regmap)) {
73 pr_crit("U300: could not locate syscon regmap\n"); 73 pr_crit("U300: could not locate syscon regmap\n");
74 return -ENODEV; 74 return PTR_ERR(regmap);
75 } 75 }
76 76
77 main_power_15 = regulator_get(&pdev->dev, "vana15"); 77 main_power_15 = regulator_get(&pdev->dev, "vana15");
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 9a5f9fb352ce..5226162fac69 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -184,11 +184,13 @@
184#define U300_TIMER_APP_CRC (0x100) 184#define U300_TIMER_APP_CRC (0x100)
185#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE (0x00000001) 185#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE (0x00000001)
186 186
187#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
188#define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
189
190static void __iomem *u300_timer_base; 187static void __iomem *u300_timer_base;
191 188
189struct u300_clockevent_data {
190 struct clock_event_device cevd;
191 unsigned ticks_per_jiffy;
192};
193
192/* 194/*
193 * The u300_set_mode() function is always called first, if we 195 * The u300_set_mode() function is always called first, if we
194 * have oneshot timer active, the oneshot scheduling function 196 * have oneshot timer active, the oneshot scheduling function
@@ -197,6 +199,9 @@ static void __iomem *u300_timer_base;
197static void u300_set_mode(enum clock_event_mode mode, 199static void u300_set_mode(enum clock_event_mode mode,
198 struct clock_event_device *evt) 200 struct clock_event_device *evt)
199{ 201{
202 struct u300_clockevent_data *cevdata =
203 container_of(evt, struct u300_clockevent_data, cevd);
204
200 switch (mode) { 205 switch (mode) {
201 case CLOCK_EVT_MODE_PERIODIC: 206 case CLOCK_EVT_MODE_PERIODIC:
202 /* Disable interrupts on GPT1 */ 207 /* Disable interrupts on GPT1 */
@@ -209,7 +214,7 @@ static void u300_set_mode(enum clock_event_mode mode,
209 * Set the periodic mode to a certain number of ticks per 214 * Set the periodic mode to a certain number of ticks per
210 * jiffy. 215 * jiffy.
211 */ 216 */
212 writel(TICKS_PER_JIFFY, 217 writel(cevdata->ticks_per_jiffy,
213 u300_timer_base + U300_TIMER_APP_GPT1TC); 218 u300_timer_base + U300_TIMER_APP_GPT1TC);
214 /* 219 /*
215 * Set continuous mode, so the timer keeps triggering 220 * Set continuous mode, so the timer keeps triggering
@@ -305,20 +310,23 @@ static int u300_set_next_event(unsigned long cycles,
305 return 0; 310 return 0;
306} 311}
307 312
308 313static struct u300_clockevent_data u300_clockevent_data = {
309/* Use general purpose timer 1 as clock event */ 314 /* Use general purpose timer 1 as clock event */
310static struct clock_event_device clockevent_u300_1mhz = { 315 .cevd = {
311 .name = "GPT1", 316 .name = "GPT1",
312 .rating = 300, /* Reasonably fast and accurate clock event */ 317 /* Reasonably fast and accurate clock event */
313 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 318 .rating = 300,
314 .set_next_event = u300_set_next_event, 319 .features = CLOCK_EVT_FEAT_PERIODIC |
315 .set_mode = u300_set_mode, 320 CLOCK_EVT_FEAT_ONESHOT,
321 .set_next_event = u300_set_next_event,
322 .set_mode = u300_set_mode,
323 },
316}; 324};
317 325
318/* Clock event timer interrupt handler */ 326/* Clock event timer interrupt handler */
319static irqreturn_t u300_timer_interrupt(int irq, void *dev_id) 327static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
320{ 328{
321 struct clock_event_device *evt = &clockevent_u300_1mhz; 329 struct clock_event_device *evt = &u300_clockevent_data.cevd;
322 /* ACK/Clear timer IRQ for the APP GPT1 Timer */ 330 /* ACK/Clear timer IRQ for the APP GPT1 Timer */
323 331
324 writel(U300_TIMER_APP_GPT1IA_IRQ_ACK, 332 writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
@@ -379,6 +387,8 @@ static void __init u300_timer_init_of(struct device_node *np)
379 clk_prepare_enable(clk); 387 clk_prepare_enable(clk);
380 rate = clk_get_rate(clk); 388 rate = clk_get_rate(clk);
381 389
390 u300_clockevent_data.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
391
382 setup_sched_clock(u300_read_sched_clock, 32, rate); 392 setup_sched_clock(u300_read_sched_clock, 32, rate);
383 393
384 u300_delay_timer.read_current_timer = &u300_read_current_timer; 394 u300_delay_timer.read_current_timer = &u300_read_current_timer;
@@ -428,7 +438,7 @@ static void __init u300_timer_init_of(struct device_node *np)
428 pr_err("timer: failed to initialize U300 clock source\n"); 438 pr_err("timer: failed to initialize U300 clock source\n");
429 439
430 /* Configure and register the clockevent */ 440 /* Configure and register the clockevent */
431 clockevents_config_and_register(&clockevent_u300_1mhz, rate, 441 clockevents_config_and_register(&u300_clockevent_data.cevd, rate,
432 1, 0xffffffff); 442 1, 0xffffffff);
433 443
434 /* 444 /*
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 4afc32f90b6d..f48dc0a4736c 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -145,6 +145,8 @@ static inline void arch_enable_uart_fifo(void)
145 if (!(fifocon & S3C2410_UFCON_RESETBOTH)) 145 if (!(fifocon & S3C2410_UFCON_RESETBOTH))
146 break; 146 break;
147 } 147 }
148
149 uart_wr(S3C2410_UFCON, S3C2410_UFCON_FIFOMODE);
148 } 150 }
149} 151}
150#else 152#else
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 1a7c1b929c69..3852e44db0f8 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -530,7 +530,8 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
530 DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), 530 DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
531 DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), 531 DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
532 DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), 532 DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
533 DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8), 533 DIV_F(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
534 CLK_SET_RATE_PARENT, 0),
534 DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), 535 DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
535 DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), 536 DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
536 DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), 537 DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index 8be7e42aa4de..b8c5187b9ee0 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -692,6 +692,7 @@ static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
692 { .compatible = "allwinner,sun4i-i2c", .data = &mv64xxx_i2c_regs_sun4i}, 692 { .compatible = "allwinner,sun4i-i2c", .data = &mv64xxx_i2c_regs_sun4i},
693 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx}, 693 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
694 { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx}, 694 { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
695 { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
695 {} 696 {}
696}; 697};
697MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table); 698MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
@@ -783,6 +784,10 @@ mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
783 drv_data->errata_delay = true; 784 drv_data->errata_delay = true;
784 } 785 }
785 786
787 if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
788 drv_data->offload_enabled = false;
789 drv_data->errata_delay = true;
790 }
786out: 791out:
787 return rc; 792 return rc;
788#endif 793#endif
diff --git a/drivers/irqchip/irq-sirfsoc.c b/drivers/irqchip/irq-sirfsoc.c
index 4851afae38dc..3a070c587ed9 100644
--- a/drivers/irqchip/irq-sirfsoc.c
+++ b/drivers/irqchip/irq-sirfsoc.c
@@ -34,9 +34,10 @@ sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
34 struct irq_chip_type *ct; 34 struct irq_chip_type *ct;
35 int ret; 35 int ret;
36 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 36 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
37 unsigned int set = IRQ_LEVEL;
37 38
38 ret = irq_alloc_domain_generic_chips(sirfsoc_irqdomain, num, 1, "irq_sirfsoc", 39 ret = irq_alloc_domain_generic_chips(sirfsoc_irqdomain, num, 1, "irq_sirfsoc",
39 handle_level_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE); 40 handle_level_irq, clr, set, IRQ_GC_INIT_MASK_CACHE);
40 41
41 gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, irq_start); 42 gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, irq_start);
42 gc->reg_base = base; 43 gc->reg_base = base;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 13:21:36 -0500