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-rw-r--r--drivers/char/agp/uninorth-agp.c2
-rw-r--r--drivers/gpu/drm/radeon/atom.c4
-rw-r--r--drivers/gpu/drm/radeon/atombios.h22
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c132
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c1046
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c14
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h2
-rw-r--r--drivers/gpu/drm/radeon/ni.c8
-rw-r--r--drivers/gpu/drm/radeon/nid.h4
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c607
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c248
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h19
-rw-r--r--include/drm/drm_dp_helper.h5
17 files changed, 1375 insertions, 753 deletions
diff --git a/drivers/char/agp/uninorth-agp.c b/drivers/char/agp/uninorth-agp.c
index f845a8f718b3..a32c492baf5c 100644
--- a/drivers/char/agp/uninorth-agp.c
+++ b/drivers/char/agp/uninorth-agp.c
@@ -80,7 +80,7 @@ static void uninorth_tlbflush(struct agp_memory *mem)
80 ctrl | UNI_N_CFG_GART_INVAL); 80 ctrl | UNI_N_CFG_GART_INVAL);
81 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl); 81 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl);
82 82
83 if (uninorth_rev <= 0x30) { 83 if (!mem && uninorth_rev <= 0x30) {
84 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 84 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
85 ctrl | UNI_N_CFG_GART_2xRESET); 85 ctrl | UNI_N_CFG_GART_2xRESET);
86 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 86 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 7bd745689097..ebdb0fdb8348 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -652,12 +652,12 @@ static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg)
652 652
653static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg) 653static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
654{ 654{
655 uint8_t count = U8((*ptr)++); 655 unsigned count = U8((*ptr)++);
656 SDEBUG(" count: %d\n", count); 656 SDEBUG(" count: %d\n", count);
657 if (arg == ATOM_UNIT_MICROSEC) 657 if (arg == ATOM_UNIT_MICROSEC)
658 udelay(count); 658 udelay(count);
659 else 659 else
660 schedule_timeout_uninterruptible(msecs_to_jiffies(count)); 660 msleep(count);
661} 661}
662 662
663static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg) 663static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 7fd88497b930..49611e2365d9 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -726,6 +726,7 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
726#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d 726#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d
727#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e 727#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e
728#define ATOM_ENCODER_CMD_SETUP 0x0f 728#define ATOM_ENCODER_CMD_SETUP 0x0f
729#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10
729 730
730// ucStatus 731// ucStatus
731#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 732#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10
@@ -765,13 +766,19 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
765 USHORT usPixelClock; // in 10KHz; for bios convenient 766 USHORT usPixelClock; // in 10KHz; for bios convenient
766 ATOM_DIG_ENCODER_CONFIG_V3 acConfig; 767 ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
767 UCHAR ucAction; 768 UCHAR ucAction;
768 UCHAR ucEncoderMode; 769 union {
770 UCHAR ucEncoderMode;
769 // =0: DP encoder 771 // =0: DP encoder
770 // =1: LVDS encoder 772 // =1: LVDS encoder
771 // =2: DVI encoder 773 // =2: DVI encoder
772 // =3: HDMI encoder 774 // =3: HDMI encoder
773 // =4: SDVO encoder 775 // =4: SDVO encoder
774 // =5: DP audio 776 // =5: DP audio
777 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
778 // =0: external DP
779 // =1: internal DP2
780 // =0x11: internal DP1 for NutMeg/Travis DP translator
781 };
775 UCHAR ucLaneNum; // how many lanes to enable 782 UCHAR ucLaneNum; // how many lanes to enable
776 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 783 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
777 UCHAR ucReserved; 784 UCHAR ucReserved;
@@ -816,13 +823,19 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
816 UCHAR ucConfig; 823 UCHAR ucConfig;
817 }; 824 };
818 UCHAR ucAction; 825 UCHAR ucAction;
819 UCHAR ucEncoderMode; 826 union {
827 UCHAR ucEncoderMode;
820 // =0: DP encoder 828 // =0: DP encoder
821 // =1: LVDS encoder 829 // =1: LVDS encoder
822 // =2: DVI encoder 830 // =2: DVI encoder
823 // =3: HDMI encoder 831 // =3: HDMI encoder
824 // =4: SDVO encoder 832 // =4: SDVO encoder
825 // =5: DP audio 833 // =5: DP audio
834 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
835 // =0: external DP
836 // =1: internal DP2
837 // =0x11: internal DP1 for NutMeg/Travis DP translator
838 };
826 UCHAR ucLaneNum; // how many lanes to enable 839 UCHAR ucLaneNum; // how many lanes to enable
827 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 840 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
828 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version 841 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
@@ -836,6 +849,11 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
836#define PANEL_12BIT_PER_COLOR 0x04 849#define PANEL_12BIT_PER_COLOR 0x04
837#define PANEL_16BIT_PER_COLOR 0x05 850#define PANEL_16BIT_PER_COLOR 0x05
838 851
852//define ucPanelMode
853#define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00
854#define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01
855#define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11
856
839/****************************************************************************/ 857/****************************************************************************/
840// Structures used by UNIPHYTransmitterControlTable 858// Structures used by UNIPHYTransmitterControlTable
841// LVTMATransmitterControlTable 859// LVTMATransmitterControlTable
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 529a3a704731..ec848787d7d9 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -420,7 +420,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
420 420
421 if (ASIC_IS_DCE5(rdev)) { 421 if (ASIC_IS_DCE5(rdev)) {
422 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); 422 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
423 args.v3.ucSpreadSpectrumType = ss->type; 423 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
424 switch (pll_id) { 424 switch (pll_id) {
425 case ATOM_PPLL1: 425 case ATOM_PPLL1:
426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; 426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
@@ -440,10 +440,12 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
440 case ATOM_PPLL_INVALID: 440 case ATOM_PPLL_INVALID:
441 return; 441 return;
442 } 442 }
443 args.v2.ucEnable = enable; 443 args.v3.ucEnable = enable;
444 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
445 args.v3.ucEnable = ATOM_DISABLE;
444 } else if (ASIC_IS_DCE4(rdev)) { 446 } else if (ASIC_IS_DCE4(rdev)) {
445 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 447 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
446 args.v2.ucSpreadSpectrumType = ss->type; 448 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
447 switch (pll_id) { 449 switch (pll_id) {
448 case ATOM_PPLL1: 450 case ATOM_PPLL1:
449 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; 451 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
@@ -464,32 +466,36 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
464 return; 466 return;
465 } 467 }
466 args.v2.ucEnable = enable; 468 args.v2.ucEnable = enable;
469 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
470 args.v2.ucEnable = ATOM_DISABLE;
467 } else if (ASIC_IS_DCE3(rdev)) { 471 } else if (ASIC_IS_DCE3(rdev)) {
468 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 472 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
469 args.v1.ucSpreadSpectrumType = ss->type; 473 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
470 args.v1.ucSpreadSpectrumStep = ss->step; 474 args.v1.ucSpreadSpectrumStep = ss->step;
471 args.v1.ucSpreadSpectrumDelay = ss->delay; 475 args.v1.ucSpreadSpectrumDelay = ss->delay;
472 args.v1.ucSpreadSpectrumRange = ss->range; 476 args.v1.ucSpreadSpectrumRange = ss->range;
473 args.v1.ucPpll = pll_id; 477 args.v1.ucPpll = pll_id;
474 args.v1.ucEnable = enable; 478 args.v1.ucEnable = enable;
475 } else if (ASIC_IS_AVIVO(rdev)) { 479 } else if (ASIC_IS_AVIVO(rdev)) {
476 if (enable == ATOM_DISABLE) { 480 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
481 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
477 atombios_disable_ss(crtc); 482 atombios_disable_ss(crtc);
478 return; 483 return;
479 } 484 }
480 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 485 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
481 args.lvds_ss_2.ucSpreadSpectrumType = ss->type; 486 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
482 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; 487 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
483 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; 488 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
484 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; 489 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
485 args.lvds_ss_2.ucEnable = enable; 490 args.lvds_ss_2.ucEnable = enable;
486 } else { 491 } else {
487 if (enable == ATOM_DISABLE) { 492 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
493 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
488 atombios_disable_ss(crtc); 494 atombios_disable_ss(crtc);
489 return; 495 return;
490 } 496 }
491 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 497 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
492 args.lvds_ss.ucSpreadSpectrumType = ss->type; 498 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
493 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; 499 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
494 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; 500 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
495 args.lvds_ss.ucEnable = enable; 501 args.lvds_ss.ucEnable = enable;
@@ -512,6 +518,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
512 struct radeon_device *rdev = dev->dev_private; 518 struct radeon_device *rdev = dev->dev_private;
513 struct drm_encoder *encoder = NULL; 519 struct drm_encoder *encoder = NULL;
514 struct radeon_encoder *radeon_encoder = NULL; 520 struct radeon_encoder *radeon_encoder = NULL;
521 struct drm_connector *connector = NULL;
515 u32 adjusted_clock = mode->clock; 522 u32 adjusted_clock = mode->clock;
516 int encoder_mode = 0; 523 int encoder_mode = 0;
517 u32 dp_clock = mode->clock; 524 u32 dp_clock = mode->clock;
@@ -546,9 +553,12 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
546 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 553 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
547 if (encoder->crtc == crtc) { 554 if (encoder->crtc == crtc) {
548 radeon_encoder = to_radeon_encoder(encoder); 555 radeon_encoder = to_radeon_encoder(encoder);
556 connector = radeon_get_connector_for_encoder(encoder);
557 if (connector)
558 bpc = connector->display_info.bpc;
549 encoder_mode = atombios_get_encoder_mode(encoder); 559 encoder_mode = atombios_get_encoder_mode(encoder);
550 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) { 560 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
551 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 561 radeon_encoder_is_dp_bridge(encoder)) {
552 if (connector) { 562 if (connector) {
553 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 563 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
554 struct radeon_connector_atom_dig *dig_connector = 564 struct radeon_connector_atom_dig *dig_connector =
@@ -612,7 +622,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
612 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 622 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
613 args.v1.ucTransmitterID = radeon_encoder->encoder_id; 623 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
614 args.v1.ucEncodeMode = encoder_mode; 624 args.v1.ucEncodeMode = encoder_mode;
615 if (ss_enabled) 625 if (ss_enabled && ss->percentage)
616 args.v1.ucConfig |= 626 args.v1.ucConfig |=
617 ADJUST_DISPLAY_CONFIG_SS_ENABLE; 627 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
618 628
@@ -625,10 +635,11 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
625 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; 635 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
626 args.v3.sInput.ucEncodeMode = encoder_mode; 636 args.v3.sInput.ucEncodeMode = encoder_mode;
627 args.v3.sInput.ucDispPllConfig = 0; 637 args.v3.sInput.ucDispPllConfig = 0;
628 if (ss_enabled) 638 if (ss_enabled && ss->percentage)
629 args.v3.sInput.ucDispPllConfig |= 639 args.v3.sInput.ucDispPllConfig |=
630 DISPPLL_CONFIG_SS_ENABLE; 640 DISPPLL_CONFIG_SS_ENABLE;
631 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 641 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT) ||
642 radeon_encoder_is_dp_bridge(encoder)) {
632 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 643 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
633 if (encoder_mode == ATOM_ENCODER_MODE_DP) { 644 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
634 args.v3.sInput.ucDispPllConfig |= 645 args.v3.sInput.ucDispPllConfig |=
@@ -754,7 +765,10 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc,
754 u32 ref_div, 765 u32 ref_div,
755 u32 fb_div, 766 u32 fb_div,
756 u32 frac_fb_div, 767 u32 frac_fb_div,
757 u32 post_div) 768 u32 post_div,
769 int bpc,
770 bool ss_enabled,
771 struct radeon_atom_ss *ss)
758{ 772{
759 struct drm_device *dev = crtc->dev; 773 struct drm_device *dev = crtc->dev;
760 struct radeon_device *rdev = dev->dev_private; 774 struct radeon_device *rdev = dev->dev_private;
@@ -801,6 +815,8 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc,
801 args.v3.ucPostDiv = post_div; 815 args.v3.ucPostDiv = post_div;
802 args.v3.ucPpll = pll_id; 816 args.v3.ucPpll = pll_id;
803 args.v3.ucMiscInfo = (pll_id << 2); 817 args.v3.ucMiscInfo = (pll_id << 2);
818 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
819 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
804 args.v3.ucTransmitterId = encoder_id; 820 args.v3.ucTransmitterId = encoder_id;
805 args.v3.ucEncoderMode = encoder_mode; 821 args.v3.ucEncoderMode = encoder_mode;
806 break; 822 break;
@@ -812,6 +828,17 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc,
812 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 828 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
813 args.v5.ucPostDiv = post_div; 829 args.v5.ucPostDiv = post_div;
814 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 830 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
831 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
832 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
833 switch (bpc) {
834 case 8:
835 default:
836 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
837 break;
838 case 10:
839 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
840 break;
841 }
815 args.v5.ucTransmitterID = encoder_id; 842 args.v5.ucTransmitterID = encoder_id;
816 args.v5.ucEncoderMode = encoder_mode; 843 args.v5.ucEncoderMode = encoder_mode;
817 args.v5.ucPpll = pll_id; 844 args.v5.ucPpll = pll_id;
@@ -824,6 +851,23 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc,
824 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 851 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
825 args.v6.ucPostDiv = post_div; 852 args.v6.ucPostDiv = post_div;
826 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ 853 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
854 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
855 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
856 switch (bpc) {
857 case 8:
858 default:
859 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
860 break;
861 case 10:
862 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
863 break;
864 case 12:
865 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
866 break;
867 case 16:
868 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
869 break;
870 }
827 args.v6.ucTransmitterID = encoder_id; 871 args.v6.ucTransmitterID = encoder_id;
828 args.v6.ucEncoderMode = encoder_mode; 872 args.v6.ucEncoderMode = encoder_mode;
829 args.v6.ucPpll = pll_id; 873 args.v6.ucPpll = pll_id;
@@ -855,6 +899,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
855 int encoder_mode = 0; 899 int encoder_mode = 0;
856 struct radeon_atom_ss ss; 900 struct radeon_atom_ss ss;
857 bool ss_enabled = false; 901 bool ss_enabled = false;
902 int bpc = 8;
858 903
859 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 904 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
860 if (encoder->crtc == crtc) { 905 if (encoder->crtc == crtc) {
@@ -891,41 +936,30 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
891 struct radeon_connector_atom_dig *dig_connector = 936 struct radeon_connector_atom_dig *dig_connector =
892 radeon_connector->con_priv; 937 radeon_connector->con_priv;
893 int dp_clock; 938 int dp_clock;
939 bpc = connector->display_info.bpc;
894 940
895 switch (encoder_mode) { 941 switch (encoder_mode) {
896 case ATOM_ENCODER_MODE_DP: 942 case ATOM_ENCODER_MODE_DP:
897 /* DP/eDP */ 943 /* DP/eDP */
898 dp_clock = dig_connector->dp_clock / 10; 944 dp_clock = dig_connector->dp_clock / 10;
899 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 945 if (ASIC_IS_DCE4(rdev))
900 if (ASIC_IS_DCE4(rdev)) 946 ss_enabled =
901 ss_enabled = 947 radeon_atombios_get_asic_ss_info(rdev, &ss,
902 radeon_atombios_get_asic_ss_info(rdev, &ss, 948 ASIC_INTERNAL_SS_ON_DP,
903 dig->lcd_ss_id, 949 dp_clock);
904 dp_clock); 950 else {
905 else 951 if (dp_clock == 16200) {
906 ss_enabled = 952 ss_enabled =
907 radeon_atombios_get_ppll_ss_info(rdev, &ss, 953 radeon_atombios_get_ppll_ss_info(rdev, &ss,
908 dig->lcd_ss_id); 954 ATOM_DP_SS_ID2);
909 } else { 955 if (!ss_enabled)
910 if (ASIC_IS_DCE4(rdev))
911 ss_enabled =
912 radeon_atombios_get_asic_ss_info(rdev, &ss,
913 ASIC_INTERNAL_SS_ON_DP,
914 dp_clock);
915 else {
916 if (dp_clock == 16200) {
917 ss_enabled =
918 radeon_atombios_get_ppll_ss_info(rdev, &ss,
919 ATOM_DP_SS_ID2);
920 if (!ss_enabled)
921 ss_enabled =
922 radeon_atombios_get_ppll_ss_info(rdev, &ss,
923 ATOM_DP_SS_ID1);
924 } else
925 ss_enabled = 956 ss_enabled =
926 radeon_atombios_get_ppll_ss_info(rdev, &ss, 957 radeon_atombios_get_ppll_ss_info(rdev, &ss,
927 ATOM_DP_SS_ID1); 958 ATOM_DP_SS_ID1);
928 } 959 } else
960 ss_enabled =
961 radeon_atombios_get_ppll_ss_info(rdev, &ss,
962 ATOM_DP_SS_ID1);
929 } 963 }
930 break; 964 break;
931 case ATOM_ENCODER_MODE_LVDS: 965 case ATOM_ENCODER_MODE_LVDS:
@@ -974,7 +1008,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
974 1008
975 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1009 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
976 encoder_mode, radeon_encoder->encoder_id, mode->clock, 1010 encoder_mode, radeon_encoder->encoder_id, mode->clock,
977 ref_div, fb_div, frac_fb_div, post_div); 1011 ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);
978 1012
979 if (ss_enabled) { 1013 if (ss_enabled) {
980 /* calculate ss amount and step size */ 1014 /* calculate ss amount and step size */
@@ -982,7 +1016,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
982 u32 step_size; 1016 u32 step_size;
983 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000; 1017 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
984 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; 1018 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
985 ss.amount |= ((amount - (ss.amount * 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & 1019 ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
986 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; 1020 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
987 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) 1021 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
988 step_size = (4 * amount * ref_div * (ss.rate * 2048)) / 1022 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
@@ -1395,11 +1429,19 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1395 uint32_t pll_in_use = 0; 1429 uint32_t pll_in_use = 0;
1396 1430
1397 if (ASIC_IS_DCE4(rdev)) { 1431 if (ASIC_IS_DCE4(rdev)) {
1398 /* if crtc is driving DP and we have an ext clock, use that */
1399 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1432 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1400 if (test_encoder->crtc && (test_encoder->crtc == crtc)) { 1433 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1434 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1435 * depending on the asic:
1436 * DCE4: PPLL or ext clock
1437 * DCE5: DCPLL or ext clock
1438 *
1439 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1440 * PPLL/DCPLL programming and only program the DP DTO for the
1441 * crtc virtual pixel clock.
1442 */
1401 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) { 1443 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1402 if (rdev->clock.dp_extclk) 1444 if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
1403 return ATOM_PPLL_INVALID; 1445 return ATOM_PPLL_INVALID;
1404 } 1446 }
1405 } 1447 }
@@ -1515,6 +1557,8 @@ static void atombios_crtc_commit(struct drm_crtc *crtc)
1515static void atombios_crtc_disable(struct drm_crtc *crtc) 1557static void atombios_crtc_disable(struct drm_crtc *crtc)
1516{ 1558{
1517 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1559 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1560 struct radeon_atom_ss ss;
1561
1518 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1562 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1519 1563
1520 switch (radeon_crtc->pll_id) { 1564 switch (radeon_crtc->pll_id) {
@@ -1522,7 +1566,7 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
1522 case ATOM_PPLL2: 1566 case ATOM_PPLL2:
1523 /* disable the ppll */ 1567 /* disable the ppll */
1524 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1568 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1525 0, 0, ATOM_DISABLE, 0, 0, 0, 0); 1569 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1526 break; 1570 break;
1527 default: 1571 default:
1528 break; 1572 break;
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 695de9a38506..8c0f9e36ff8e 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -43,158 +43,242 @@ static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB" 43 "0dB", "3.5dB", "6dB", "9.5dB"
44}; 44};
45 45
46static const int dp_clocks[] = { 46/***** radeon AUX functions *****/
47 54000, /* 1 lane, 1.62 Ghz */ 47union aux_channel_transaction {
48 90000, /* 1 lane, 2.70 Ghz */ 48 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
49 108000, /* 2 lane, 1.62 Ghz */ 49 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
50 180000, /* 2 lane, 2.70 Ghz */
51 216000, /* 4 lane, 1.62 Ghz */
52 360000, /* 4 lane, 2.70 Ghz */
53}; 50};
54 51
55static const int num_dp_clocks = sizeof(dp_clocks) / sizeof(int); 52static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
53 u8 *send, int send_bytes,
54 u8 *recv, int recv_size,
55 u8 delay, u8 *ack)
56{
57 struct drm_device *dev = chan->dev;
58 struct radeon_device *rdev = dev->dev_private;
59 union aux_channel_transaction args;
60 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
61 unsigned char *base;
62 int recv_bytes;
63
64 memset(&args, 0, sizeof(args));
56 65
57/* common helper functions */ 66 base = (unsigned char *)rdev->mode_info.atom_context->scratch;
58static int dp_lanes_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock) 67
68 memcpy(base, send, send_bytes);
69
70 args.v1.lpAuxRequest = 0;
71 args.v1.lpDataOut = 16;
72 args.v1.ucDataOutLen = 0;
73 args.v1.ucChannelID = chan->rec.i2c_id;
74 args.v1.ucDelay = delay / 10;
75 if (ASIC_IS_DCE4(rdev))
76 args.v2.ucHPD_ID = chan->rec.hpd;
77
78 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
79
80 *ack = args.v1.ucReplyStatus;
81
82 /* timeout */
83 if (args.v1.ucReplyStatus == 1) {
84 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
85 return -ETIMEDOUT;
86 }
87
88 /* flags not zero */
89 if (args.v1.ucReplyStatus == 2) {
90 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
91 return -EBUSY;
92 }
93
94 /* error */
95 if (args.v1.ucReplyStatus == 3) {
96 DRM_DEBUG_KMS("dp_aux_ch error\n");
97 return -EIO;
98 }
99
100 recv_bytes = args.v1.ucDataOutLen;
101 if (recv_bytes > recv_size)
102 recv_bytes = recv_size;
103
104 if (recv && recv_size)
105 memcpy(recv, base + 16, recv_bytes);
106
107 return recv_bytes;
108}
109
110static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
111 u16 address, u8 *send, u8 send_bytes, u8 delay)
59{ 112{
60 int i; 113 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
61 u8 max_link_bw; 114 int ret;
62 u8 max_lane_count; 115 u8 msg[20];
116 int msg_bytes = send_bytes + 4;
117 u8 ack;
63 118
64 if (!dpcd) 119 if (send_bytes > 16)
65 return 0; 120 return -1;
66 121
67 max_link_bw = dpcd[DP_MAX_LINK_RATE]; 122 msg[0] = address;
68 max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 123 msg[1] = address >> 8;
124 msg[2] = AUX_NATIVE_WRITE << 4;
125 msg[3] = (msg_bytes << 4) | (send_bytes - 1);
126 memcpy(&msg[4], send, send_bytes);
69 127
70 switch (max_link_bw) { 128 while (1) {
71 case DP_LINK_BW_1_62: 129 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
72 default: 130 msg, msg_bytes, NULL, 0, delay, &ack);
73 for (i = 0; i < num_dp_clocks; i++) { 131 if (ret < 0)
74 if (i % 2) 132 return ret;
75 continue; 133 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
76 switch (max_lane_count) { 134 break;
77 case 1: 135 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
78 if (i > 1) 136 udelay(400);
79 return 0; 137 else
80 break; 138 return -EIO;
81 case 2:
82 if (i > 3)
83 return 0;
84 break;
85 case 4:
86 default:
87 break;
88 }
89 if (dp_clocks[i] > mode_clock) {
90 if (i < 2)
91 return 1;
92 else if (i < 4)
93 return 2;
94 else
95 return 4;
96 }
97 }
98 break;
99 case DP_LINK_BW_2_7:
100 for (i = 0; i < num_dp_clocks; i++) {
101 switch (max_lane_count) {
102 case 1:
103 if (i > 1)
104 return 0;
105 break;
106 case 2:
107 if (i > 3)
108 return 0;
109 break;
110 case 4:
111 default:
112 break;
113 }
114 if (dp_clocks[i] > mode_clock) {
115 if (i < 2)
116 return 1;
117 else if (i < 4)
118 return 2;
119 else
120 return 4;
121 }
122 }
123 break;
124 } 139 }
125 140
126 return 0; 141 return send_bytes;
127} 142}
128 143
129static int dp_link_clock_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock) 144static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
145 u16 address, u8 *recv, int recv_bytes, u8 delay)
130{ 146{
131 int i; 147 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
132 u8 max_link_bw; 148 u8 msg[4];
133 u8 max_lane_count; 149 int msg_bytes = 4;
150 u8 ack;
151 int ret;
134 152
135 if (!dpcd) 153 msg[0] = address;
136 return 0; 154 msg[1] = address >> 8;
155 msg[2] = AUX_NATIVE_READ << 4;
156 msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
157
158 while (1) {
159 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
160 msg, msg_bytes, recv, recv_bytes, delay, &ack);
161 if (ret == 0)
162 return -EPROTO;
163 if (ret < 0)
164 return ret;
165 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
166 return ret;
167 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
168 udelay(400);
169 else
170 return -EIO;
171 }
172}
137 173
138 max_link_bw = dpcd[DP_MAX_LINK_RATE]; 174static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
139 max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 175 u16 reg, u8 val)
176{
177 radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
178}
140 179
141 switch (max_link_bw) { 180static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
142 case DP_LINK_BW_1_62: 181 u16 reg)
182{
183 u8 val = 0;
184
185 radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
186
187 return val;
188}
189
190int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
191 u8 write_byte, u8 *read_byte)
192{
193 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
194 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
195 u16 address = algo_data->address;
196 u8 msg[5];
197 u8 reply[2];
198 unsigned retry;
199 int msg_bytes;
200 int reply_bytes = 1;
201 int ret;
202 u8 ack;
203
204 /* Set up the command byte */
205 if (mode & MODE_I2C_READ)
206 msg[2] = AUX_I2C_READ << 4;
207 else
208 msg[2] = AUX_I2C_WRITE << 4;
209
210 if (!(mode & MODE_I2C_STOP))
211 msg[2] |= AUX_I2C_MOT << 4;
212
213 msg[0] = address;
214 msg[1] = address >> 8;
215
216 switch (mode) {
217 case MODE_I2C_WRITE:
218 msg_bytes = 5;
219 msg[3] = msg_bytes << 4;
220 msg[4] = write_byte;
221 break;
222 case MODE_I2C_READ:
223 msg_bytes = 4;
224 msg[3] = msg_bytes << 4;
225 break;
143 default: 226 default:
144 for (i = 0; i < num_dp_clocks; i++) { 227 msg_bytes = 4;
145 if (i % 2) 228 msg[3] = 3 << 4;
146 continue;
147 switch (max_lane_count) {
148 case 1:
149 if (i > 1)
150 return 0;
151 break;
152 case 2:
153 if (i > 3)
154 return 0;
155 break;
156 case 4:
157 default:
158 break;
159 }
160 if (dp_clocks[i] > mode_clock)
161 return 162000;
162 }
163 break; 229 break;
164 case DP_LINK_BW_2_7:
165 for (i = 0; i < num_dp_clocks; i++) {
166 switch (max_lane_count) {
167 case 1:
168 if (i > 1)
169 return 0;
170 break;
171 case 2:
172 if (i > 3)
173 return 0;
174 break;
175 case 4:
176 default:
177 break;
178 }
179 if (dp_clocks[i] > mode_clock)
180 return (i % 2) ? 270000 : 162000;
181 }
182 } 230 }
183 231
184 return 0; 232 for (retry = 0; retry < 4; retry++) {
185} 233 ret = radeon_process_aux_ch(auxch,
234 msg, msg_bytes, reply, reply_bytes, 0, &ack);
235 if (ret < 0) {
236 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
237 return ret;
238 }
186 239
187int dp_mode_valid(u8 dpcd[DP_DPCD_SIZE], int mode_clock) 240 switch (ack & AUX_NATIVE_REPLY_MASK) {
188{ 241 case AUX_NATIVE_REPLY_ACK:
189 int lanes = dp_lanes_for_mode_clock(dpcd, mode_clock); 242 /* I2C-over-AUX Reply field is only valid
190 int dp_clock = dp_link_clock_for_mode_clock(dpcd, mode_clock); 243 * when paired with AUX ACK.
244 */
245 break;
246 case AUX_NATIVE_REPLY_NACK:
247 DRM_DEBUG_KMS("aux_ch native nack\n");
248 return -EREMOTEIO;
249 case AUX_NATIVE_REPLY_DEFER:
250 DRM_DEBUG_KMS("aux_ch native defer\n");
251 udelay(400);
252 continue;
253 default:
254 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
255 return -EREMOTEIO;
256 }
191 257
192 if ((lanes == 0) || (dp_clock == 0)) 258 switch (ack & AUX_I2C_REPLY_MASK) {
193 return MODE_CLOCK_HIGH; 259 case AUX_I2C_REPLY_ACK:
260 if (mode == MODE_I2C_READ)
261 *read_byte = reply[0];
262 return ret;
263 case AUX_I2C_REPLY_NACK:
264 DRM_DEBUG_KMS("aux_i2c nack\n");
265 return -EREMOTEIO;
266 case AUX_I2C_REPLY_DEFER:
267 DRM_DEBUG_KMS("aux_i2c defer\n");
268 udelay(400);
269 break;
270 default:
271 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
272 return -EREMOTEIO;
273 }
274 }
194 275
195 return MODE_OK; 276 DRM_ERROR("aux i2c too many retries, giving up\n");
277 return -EREMOTEIO;
196} 278}
197 279
280/***** general DP utility functions *****/
281
198static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r) 282static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
199{ 283{
200 return link_status[r - DP_LANE0_1_STATUS]; 284 return link_status[r - DP_LANE0_1_STATUS];
@@ -242,7 +326,7 @@ static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
242 return true; 326 return true;
243} 327}
244 328
245static u8 dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], 329static u8 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
246 int lane) 330 int lane)
247 331
248{ 332{
@@ -255,7 +339,7 @@ static u8 dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE]
255 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 339 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
256} 340}
257 341
258static u8 dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], 342static u8 dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
259 int lane) 343 int lane)
260{ 344{
261 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 345 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
@@ -267,22 +351,8 @@ static u8 dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_
267 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 351 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
268} 352}
269 353
270/* XXX fix me -- chip specific */
271#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 354#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
272static u8 dp_pre_emphasis_max(u8 voltage_swing) 355#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
273{
274 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
275 case DP_TRAIN_VOLTAGE_SWING_400:
276 return DP_TRAIN_PRE_EMPHASIS_6;
277 case DP_TRAIN_VOLTAGE_SWING_600:
278 return DP_TRAIN_PRE_EMPHASIS_6;
279 case DP_TRAIN_VOLTAGE_SWING_800:
280 return DP_TRAIN_PRE_EMPHASIS_3_5;
281 case DP_TRAIN_VOLTAGE_SWING_1200:
282 default:
283 return DP_TRAIN_PRE_EMPHASIS_0;
284 }
285}
286 356
287static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], 357static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
288 int lane_count, 358 int lane_count,
@@ -308,10 +378,10 @@ static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
308 } 378 }
309 379
310 if (v >= DP_VOLTAGE_MAX) 380 if (v >= DP_VOLTAGE_MAX)
311 v = DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; 381 v |= DP_TRAIN_MAX_SWING_REACHED;
312 382
313 if (p >= dp_pre_emphasis_max(v)) 383 if (p >= DP_PRE_EMPHASIS_MAX)
314 p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 384 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
315 385
316 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", 386 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
317 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 387 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
@@ -321,110 +391,109 @@ static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
321 train_set[lane] = v | p; 391 train_set[lane] = v | p;
322} 392}
323 393
324union aux_channel_transaction { 394/* convert bits per color to bits per pixel */
325 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; 395/* get bpc from the EDID */
326 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; 396static int convert_bpc_to_bpp(int bpc)
327};
328
329/* radeon aux chan functions */
330bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
331 int num_bytes, u8 *read_byte,
332 u8 read_buf_len, u8 delay)
333{ 397{
334 struct drm_device *dev = chan->dev; 398 if (bpc == 0)
335 struct radeon_device *rdev = dev->dev_private; 399 return 24;
336 union aux_channel_transaction args; 400 else
337 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); 401 return bpc * 3;
338 unsigned char *base; 402}
339 int retry_count = 0;
340
341 memset(&args, 0, sizeof(args));
342
343 base = (unsigned char *)rdev->mode_info.atom_context->scratch;
344
345retry:
346 memcpy(base, req_bytes, num_bytes);
347
348 args.v1.lpAuxRequest = 0;
349 args.v1.lpDataOut = 16;
350 args.v1.ucDataOutLen = 0;
351 args.v1.ucChannelID = chan->rec.i2c_id;
352 args.v1.ucDelay = delay / 10;
353 if (ASIC_IS_DCE4(rdev))
354 args.v2.ucHPD_ID = chan->rec.hpd;
355 403
356 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 404/* get the max pix clock supported by the link rate and lane num */
405static int dp_get_max_dp_pix_clock(int link_rate,
406 int lane_num,
407 int bpp)
408{
409 return (link_rate * lane_num * 8) / bpp;
410}
357 411
358 if (args.v1.ucReplyStatus && !args.v1.ucDataOutLen) { 412static int dp_get_max_link_rate(u8 dpcd[DP_DPCD_SIZE])
359 if (args.v1.ucReplyStatus == 0x20 && retry_count++ < 10) 413{
360 goto retry; 414 switch (dpcd[DP_MAX_LINK_RATE]) {
361 DRM_DEBUG_KMS("failed to get auxch %02x%02x %02x %02x 0x%02x %02x after %d retries\n", 415 case DP_LINK_BW_1_62:
362 req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3], 416 default:
363 chan->rec.i2c_id, args.v1.ucReplyStatus, retry_count); 417 return 162000;
364 return false; 418 case DP_LINK_BW_2_7:
419 return 270000;
420 case DP_LINK_BW_5_4:
421 return 540000;
365 } 422 }
423}
366 424
367 if (args.v1.ucDataOutLen && read_byte && read_buf_len) { 425static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE])
368 if (read_buf_len < args.v1.ucDataOutLen) { 426{
369 DRM_ERROR("Buffer to small for return answer %d %d\n", 427 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
370 read_buf_len, args.v1.ucDataOutLen);
371 return false;
372 }
373 {
374 int len = min(read_buf_len, args.v1.ucDataOutLen);
375 memcpy(read_byte, base + 16, len);
376 }
377 }
378 return true;
379} 428}
380 429
381bool radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, uint16_t address, 430static u8 dp_get_dp_link_rate_coded(int link_rate)
382 uint8_t send_bytes, uint8_t *send)
383{ 431{
384 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 432 switch (link_rate) {
385 u8 msg[20]; 433 case 162000:
386 u8 msg_len, dp_msg_len; 434 default:
387 bool ret; 435 return DP_LINK_BW_1_62;
436 case 270000:
437 return DP_LINK_BW_2_7;
438 case 540000:
439 return DP_LINK_BW_5_4;
440 }
441}
388 442
389 dp_msg_len = 4; 443/***** radeon specific DP functions *****/
390 msg[0] = address;
391 msg[1] = address >> 8;
392 msg[2] = AUX_NATIVE_WRITE << 4;
393 dp_msg_len += send_bytes;
394 msg[3] = (dp_msg_len << 4) | (send_bytes - 1);
395 444
396 if (send_bytes > 16) 445/* First get the min lane# when low rate is used according to pixel clock
397 return false; 446 * (prefer low rate), second check max lane# supported by DP panel,
447 * if the max lane# < low rate lane# then use max lane# instead.
448 */
449static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
450 u8 dpcd[DP_DPCD_SIZE],
451 int pix_clock)
452{
453 int bpp = convert_bpc_to_bpp(connector->display_info.bpc);
454 int max_link_rate = dp_get_max_link_rate(dpcd);
455 int max_lane_num = dp_get_max_lane_number(dpcd);
456 int lane_num;
457 int max_dp_pix_clock;
458
459 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
460 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
461 if (pix_clock <= max_dp_pix_clock)
462 break;
463 }
398 464
399 memcpy(&msg[4], send, send_bytes); 465 return lane_num;
400 msg_len = 4 + send_bytes;
401 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, NULL, 0, 0);
402 return ret;
403} 466}
404 467
405bool radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, uint16_t address, 468static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
406 uint8_t delay, uint8_t expected_bytes, 469 u8 dpcd[DP_DPCD_SIZE],
407 uint8_t *read_p) 470 int pix_clock)
408{ 471{
409 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 472 int bpp = convert_bpc_to_bpp(connector->display_info.bpc);
410 u8 msg[20]; 473 int lane_num, max_pix_clock;
411 u8 msg_len, dp_msg_len; 474
412 bool ret = false; 475 if (radeon_connector_encoder_is_dp_bridge(connector))
413 msg_len = 4; 476 return 270000;
414 dp_msg_len = 4; 477
415 msg[0] = address; 478 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
416 msg[1] = address >> 8; 479 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
417 msg[2] = AUX_NATIVE_READ << 4; 480 if (pix_clock <= max_pix_clock)
418 msg[3] = (dp_msg_len) << 4; 481 return 162000;
419 msg[3] |= expected_bytes - 1; 482 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
483 if (pix_clock <= max_pix_clock)
484 return 270000;
485 if (radeon_connector_is_dp12_capable(connector)) {
486 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
487 if (pix_clock <= max_pix_clock)
488 return 540000;
489 }
420 490
421 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, read_p, expected_bytes, delay); 491 return dp_get_max_link_rate(dpcd);
422 return ret;
423} 492}
424 493
425/* radeon dp functions */ 494static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
426static u8 radeon_dp_encoder_service(struct radeon_device *rdev, int action, int dp_clock, 495 int action, int dp_clock,
427 uint8_t ucconfig, uint8_t lane_num) 496 u8 ucconfig, u8 lane_num)
428{ 497{
429 DP_ENCODER_SERVICE_PARAMETERS args; 498 DP_ENCODER_SERVICE_PARAMETERS args;
430 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 499 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
@@ -454,60 +523,86 @@ bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
454{ 523{
455 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 524 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
456 u8 msg[25]; 525 u8 msg[25];
457 int ret; 526 int ret, i;
458 527
459 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, 0, 8, msg); 528 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 8, 0);
460 if (ret) { 529 if (ret > 0) {
461 memcpy(dig_connector->dpcd, msg, 8); 530 memcpy(dig_connector->dpcd, msg, 8);
462 { 531 DRM_DEBUG_KMS("DPCD: ");
463 int i; 532 for (i = 0; i < 8; i++)
464 DRM_DEBUG_KMS("DPCD: "); 533 DRM_DEBUG_KMS("%02x ", msg[i]);
465 for (i = 0; i < 8; i++) 534 DRM_DEBUG_KMS("\n");
466 DRM_DEBUG_KMS("%02x ", msg[i]);
467 DRM_DEBUG_KMS("\n");
468 }
469 return true; 535 return true;
470 } 536 }
471 dig_connector->dpcd[0] = 0; 537 dig_connector->dpcd[0] = 0;
472 return false; 538 return false;
473} 539}
474 540
541static void radeon_dp_set_panel_mode(struct drm_encoder *encoder,
542 struct drm_connector *connector)
543{
544 struct drm_device *dev = encoder->dev;
545 struct radeon_device *rdev = dev->dev_private;
546 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
547
548 if (!ASIC_IS_DCE4(rdev))
549 return;
550
551 if (radeon_connector_encoder_is_dp_bridge(connector))
552 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
553
554 atombios_dig_encoder_setup(encoder,
555 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
556 panel_mode);
557}
558
475void radeon_dp_set_link_config(struct drm_connector *connector, 559void radeon_dp_set_link_config(struct drm_connector *connector,
476 struct drm_display_mode *mode) 560 struct drm_display_mode *mode)
477{ 561{
478 struct radeon_connector *radeon_connector; 562 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
479 struct radeon_connector_atom_dig *dig_connector; 563 struct radeon_connector_atom_dig *dig_connector;
480 564
481 if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
482 (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
483 return;
484
485 radeon_connector = to_radeon_connector(connector);
486 if (!radeon_connector->con_priv) 565 if (!radeon_connector->con_priv)
487 return; 566 return;
488 dig_connector = radeon_connector->con_priv; 567 dig_connector = radeon_connector->con_priv;
489 568
490 dig_connector->dp_clock = 569 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
491 dp_link_clock_for_mode_clock(dig_connector->dpcd, mode->clock); 570 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
492 dig_connector->dp_lane_count = 571 dig_connector->dp_clock =
493 dp_lanes_for_mode_clock(dig_connector->dpcd, mode->clock); 572 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
573 dig_connector->dp_lane_count =
574 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
575 }
494} 576}
495 577
496int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector, 578int radeon_dp_mode_valid_helper(struct drm_connector *connector,
497 struct drm_display_mode *mode) 579 struct drm_display_mode *mode)
498{ 580{
499 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 581 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
582 struct radeon_connector_atom_dig *dig_connector;
583 int dp_clock;
584
585 if (!radeon_connector->con_priv)
586 return MODE_CLOCK_HIGH;
587 dig_connector = radeon_connector->con_priv;
588
589 dp_clock =
590 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
591
592 if ((dp_clock == 540000) &&
593 (!radeon_connector_is_dp12_capable(connector)))
594 return MODE_CLOCK_HIGH;
500 595
501 return dp_mode_valid(dig_connector->dpcd, mode->clock); 596 return MODE_OK;
502} 597}
503 598
504static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector, 599static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
505 u8 link_status[DP_LINK_STATUS_SIZE]) 600 u8 link_status[DP_LINK_STATUS_SIZE])
506{ 601{
507 int ret; 602 int ret;
508 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, 100, 603 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
509 DP_LINK_STATUS_SIZE, link_status); 604 link_status, DP_LINK_STATUS_SIZE, 100);
510 if (!ret) { 605 if (ret <= 0) {
511 DRM_ERROR("displayport link status failed\n"); 606 DRM_ERROR("displayport link status failed\n");
512 return false; 607 return false;
513 } 608 }
@@ -518,292 +613,309 @@ static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector,
518 return true; 613 return true;
519} 614}
520 615
521bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) 616struct radeon_dp_link_train_info {
522{ 617 struct radeon_device *rdev;
523 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 618 struct drm_encoder *encoder;
619 struct drm_connector *connector;
620 struct radeon_connector *radeon_connector;
621 int enc_id;
622 int dp_clock;
623 int dp_lane_count;
624 int rd_interval;
625 bool tp3_supported;
626 u8 dpcd[8];
627 u8 train_set[4];
524 u8 link_status[DP_LINK_STATUS_SIZE]; 628 u8 link_status[DP_LINK_STATUS_SIZE];
629 u8 tries;
630};
525 631
526 if (!atom_dp_get_link_status(radeon_connector, link_status)) 632static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
527 return false; 633{
528 if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count)) 634 /* set the initial vs/emph on the source */
529 return false; 635 atombios_dig_transmitter_setup(dp_info->encoder,
530 return true; 636 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
637 0, dp_info->train_set[0]); /* sets all lanes at once */
638
639 /* set the vs/emph on the sink */
640 radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
641 dp_info->train_set, dp_info->dp_lane_count, 0);
531} 642}
532 643
533static void dp_set_power(struct radeon_connector *radeon_connector, u8 power_state) 644static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
534{ 645{
535 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 646 int rtp = 0;
536 647
537 if (dig_connector->dpcd[0] >= 0x11) { 648 /* set training pattern on the source */
538 radeon_dp_aux_native_write(radeon_connector, DP_SET_POWER, 1, 649 if (ASIC_IS_DCE4(dp_info->rdev)) {
539 &power_state); 650 switch (tp) {
651 case DP_TRAINING_PATTERN_1:
652 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
653 break;
654 case DP_TRAINING_PATTERN_2:
655 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
656 break;
657 case DP_TRAINING_PATTERN_3:
658 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
659 break;
660 }
661 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
662 } else {
663 switch (tp) {
664 case DP_TRAINING_PATTERN_1:
665 rtp = 0;
666 break;
667 case DP_TRAINING_PATTERN_2:
668 rtp = 1;
669 break;
670 }
671 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
672 dp_info->dp_clock, dp_info->enc_id, rtp);
540 } 673 }
541}
542 674
543static void dp_set_downspread(struct radeon_connector *radeon_connector, u8 downspread) 675 /* enable training pattern on the sink */
544{ 676 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
545 radeon_dp_aux_native_write(radeon_connector, DP_DOWNSPREAD_CTRL, 1,
546 &downspread);
547} 677}
548 678
549static void dp_set_link_bw_lanes(struct radeon_connector *radeon_connector, 679static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
550 u8 link_configuration[DP_LINK_CONFIGURATION_SIZE])
551{ 680{
552 radeon_dp_aux_native_write(radeon_connector, DP_LINK_BW_SET, 2, 681 u8 tmp;
553 link_configuration);
554}
555 682
556static void dp_update_dpvs_emph(struct radeon_connector *radeon_connector, 683 /* power up the sink */
557 struct drm_encoder *encoder, 684 if (dp_info->dpcd[0] >= 0x11)
558 u8 train_set[4]) 685 radeon_write_dpcd_reg(dp_info->radeon_connector,
559{ 686 DP_SET_POWER, DP_SET_POWER_D0);
560 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 687
561 int i; 688 /* possibly enable downspread on the sink */
689 if (dp_info->dpcd[3] & 0x1)
690 radeon_write_dpcd_reg(dp_info->radeon_connector,
691 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
692 else
693 radeon_write_dpcd_reg(dp_info->radeon_connector,
694 DP_DOWNSPREAD_CTRL, 0);
562 695
563 for (i = 0; i < dig_connector->dp_lane_count; i++) 696 radeon_dp_set_panel_mode(dp_info->encoder, dp_info->connector);
564 atombios_dig_transmitter_setup(encoder,
565 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
566 i, train_set[i]);
567 697
568 radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_LANE0_SET, 698 /* set the lane count on the sink */
569 dig_connector->dp_lane_count, train_set); 699 tmp = dp_info->dp_lane_count;
570} 700 if (dp_info->dpcd[0] >= 0x11)
701 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
702 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
571 703
572static void dp_set_training(struct radeon_connector *radeon_connector, 704 /* set the link rate on the sink */
573 u8 training) 705 tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock);
574{ 706 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
575 radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_PATTERN_SET,
576 1, &training);
577}
578 707
579void dp_link_train(struct drm_encoder *encoder, 708 /* start training on the source */
580 struct drm_connector *connector) 709 if (ASIC_IS_DCE4(dp_info->rdev))
581{ 710 atombios_dig_encoder_setup(dp_info->encoder,
582 struct drm_device *dev = encoder->dev; 711 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
583 struct radeon_device *rdev = dev->dev_private; 712 else
584 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 713 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
585 struct radeon_encoder_atom_dig *dig; 714 dp_info->dp_clock, dp_info->enc_id, 0);
586 struct radeon_connector *radeon_connector;
587 struct radeon_connector_atom_dig *dig_connector;
588 int enc_id = 0;
589 bool clock_recovery, channel_eq;
590 u8 link_status[DP_LINK_STATUS_SIZE];
591 u8 link_configuration[DP_LINK_CONFIGURATION_SIZE];
592 u8 tries, voltage;
593 u8 train_set[4];
594 int i;
595 715
596 if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) && 716 /* disable the training pattern on the sink */
597 (connector->connector_type != DRM_MODE_CONNECTOR_eDP)) 717 radeon_write_dpcd_reg(dp_info->radeon_connector,
598 return; 718 DP_TRAINING_PATTERN_SET,
719 DP_TRAINING_PATTERN_DISABLE);
599 720
600 if (!radeon_encoder->enc_priv) 721 return 0;
601 return; 722}
602 dig = radeon_encoder->enc_priv;
603 723
604 radeon_connector = to_radeon_connector(connector); 724static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
605 if (!radeon_connector->con_priv) 725{
606 return; 726 udelay(400);
607 dig_connector = radeon_connector->con_priv;
608 727
609 if (dig->dig_encoder) 728 /* disable the training pattern on the sink */
610 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; 729 radeon_write_dpcd_reg(dp_info->radeon_connector,
611 else 730 DP_TRAINING_PATTERN_SET,
612 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; 731 DP_TRAINING_PATTERN_DISABLE);
613 if (dig->linkb)
614 enc_id |= ATOM_DP_CONFIG_LINK_B;
615 else
616 enc_id |= ATOM_DP_CONFIG_LINK_A;
617 732
618 memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 733 /* disable the training pattern on the source */
619 if (dig_connector->dp_clock == 270000) 734 if (ASIC_IS_DCE4(dp_info->rdev))
620 link_configuration[0] = DP_LINK_BW_2_7; 735 atombios_dig_encoder_setup(dp_info->encoder,
736 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
621 else 737 else
622 link_configuration[0] = DP_LINK_BW_1_62; 738 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
623 link_configuration[1] = dig_connector->dp_lane_count; 739 dp_info->dp_clock, dp_info->enc_id, 0);
624 if (dig_connector->dpcd[0] >= 0x11)
625 link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
626 740
627 /* power up the sink */ 741 return 0;
628 dp_set_power(radeon_connector, DP_SET_POWER_D0); 742}
629 /* disable the training pattern on the sink */
630 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
631 /* set link bw and lanes on the sink */
632 dp_set_link_bw_lanes(radeon_connector, link_configuration);
633 /* disable downspread on the sink */
634 dp_set_downspread(radeon_connector, 0);
635 if (ASIC_IS_DCE4(rdev)) {
636 /* start training on the source */
637 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_START);
638 /* set training pattern 1 on the source */
639 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1);
640 } else {
641 /* start training on the source */
642 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START,
643 dig_connector->dp_clock, enc_id, 0);
644 /* set training pattern 1 on the source */
645 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
646 dig_connector->dp_clock, enc_id, 0);
647 }
648 743
649 /* set initial vs/emph */ 744static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
650 memset(train_set, 0, 4); 745{
651 udelay(400); 746 bool clock_recovery;
652 /* set training pattern 1 on the sink */ 747 u8 voltage;
653 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_1); 748 int i;
654 749
655 dp_update_dpvs_emph(radeon_connector, encoder, train_set); 750 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
751 memset(dp_info->train_set, 0, 4);
752 radeon_dp_update_vs_emph(dp_info);
753
754 udelay(400);
656 755
657 /* clock recovery loop */ 756 /* clock recovery loop */
658 clock_recovery = false; 757 clock_recovery = false;
659 tries = 0; 758 dp_info->tries = 0;
660 voltage = 0xff; 759 voltage = 0xff;
661 for (;;) { 760 while (1) {
662 udelay(100); 761 if (dp_info->rd_interval == 0)
663 if (!atom_dp_get_link_status(radeon_connector, link_status)) 762 udelay(100);
763 else
764 mdelay(dp_info->rd_interval * 4);
765
766 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status))
664 break; 767 break;
665 768
666 if (dp_clock_recovery_ok(link_status, dig_connector->dp_lane_count)) { 769 if (dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
667 clock_recovery = true; 770 clock_recovery = true;
668 break; 771 break;
669 } 772 }
670 773
671 for (i = 0; i < dig_connector->dp_lane_count; i++) { 774 for (i = 0; i < dp_info->dp_lane_count; i++) {
672 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 775 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
673 break; 776 break;
674 } 777 }
675 if (i == dig_connector->dp_lane_count) { 778 if (i == dp_info->dp_lane_count) {
676 DRM_ERROR("clock recovery reached max voltage\n"); 779 DRM_ERROR("clock recovery reached max voltage\n");
677 break; 780 break;
678 } 781 }
679 782
680 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 783 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
681 ++tries; 784 ++dp_info->tries;
682 if (tries == 5) { 785 if (dp_info->tries == 5) {
683 DRM_ERROR("clock recovery tried 5 times\n"); 786 DRM_ERROR("clock recovery tried 5 times\n");
684 break; 787 break;
685 } 788 }
686 } else 789 } else
687 tries = 0; 790 dp_info->tries = 0;
688 791
689 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 792 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
690 793
691 /* Compute new train_set as requested by sink */ 794 /* Compute new train_set as requested by sink */
692 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set); 795 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
693 dp_update_dpvs_emph(radeon_connector, encoder, train_set); 796
797 radeon_dp_update_vs_emph(dp_info);
694 } 798 }
695 if (!clock_recovery) 799 if (!clock_recovery) {
696 DRM_ERROR("clock recovery failed\n"); 800 DRM_ERROR("clock recovery failed\n");
697 else 801 return -1;
802 } else {
698 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", 803 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
699 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 804 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
700 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> 805 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
701 DP_TRAIN_PRE_EMPHASIS_SHIFT); 806 DP_TRAIN_PRE_EMPHASIS_SHIFT);
807 return 0;
808 }
809}
702 810
811static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
812{
813 bool channel_eq;
703 814
704 /* set training pattern 2 on the sink */ 815 if (dp_info->tp3_supported)
705 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2); 816 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
706 /* set training pattern 2 on the source */
707 if (ASIC_IS_DCE4(rdev))
708 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2);
709 else 817 else
710 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, 818 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
711 dig_connector->dp_clock, enc_id, 1);
712 819
713 /* channel equalization loop */ 820 /* channel equalization loop */
714 tries = 0; 821 dp_info->tries = 0;
715 channel_eq = false; 822 channel_eq = false;
716 for (;;) { 823 while (1) {
717 udelay(400); 824 if (dp_info->rd_interval == 0)
718 if (!atom_dp_get_link_status(radeon_connector, link_status)) 825 udelay(400);
826 else
827 mdelay(dp_info->rd_interval * 4);
828
829 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status))
719 break; 830 break;
720 831
721 if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count)) { 832 if (dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
722 channel_eq = true; 833 channel_eq = true;
723 break; 834 break;
724 } 835 }
725 836
726 /* Try 5 times */ 837 /* Try 5 times */
727 if (tries > 5) { 838 if (dp_info->tries > 5) {
728 DRM_ERROR("channel eq failed: 5 tries\n"); 839 DRM_ERROR("channel eq failed: 5 tries\n");
729 break; 840 break;
730 } 841 }
731 842
732 /* Compute new train_set as requested by sink */ 843 /* Compute new train_set as requested by sink */
733 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set); 844 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
734 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
735 845
736 tries++; 846 radeon_dp_update_vs_emph(dp_info);
847 dp_info->tries++;
737 } 848 }
738 849
739 if (!channel_eq) 850 if (!channel_eq) {
740 DRM_ERROR("channel eq failed\n"); 851 DRM_ERROR("channel eq failed\n");
741 else 852 return -1;
853 } else {
742 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", 854 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
743 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 855 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
744 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) 856 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
745 >> DP_TRAIN_PRE_EMPHASIS_SHIFT); 857 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
746 858 return 0;
747 /* disable the training pattern on the sink */ 859 }
748 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
749
750 /* disable the training pattern on the source */
751 if (ASIC_IS_DCE4(rdev))
752 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE);
753 else
754 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
755 dig_connector->dp_clock, enc_id, 0);
756} 860}
757 861
758int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 862void radeon_dp_link_train(struct drm_encoder *encoder,
759 uint8_t write_byte, uint8_t *read_byte) 863 struct drm_connector *connector)
760{ 864{
761 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 865 struct drm_device *dev = encoder->dev;
762 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter; 866 struct radeon_device *rdev = dev->dev_private;
763 int ret = 0; 867 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
764 uint16_t address = algo_data->address; 868 struct radeon_encoder_atom_dig *dig;
765 uint8_t msg[5]; 869 struct radeon_connector *radeon_connector;
766 uint8_t reply[2]; 870 struct radeon_connector_atom_dig *dig_connector;
767 int msg_len, dp_msg_len; 871 struct radeon_dp_link_train_info dp_info;
768 int reply_bytes; 872 u8 tmp;
769
770 /* Set up the command byte */
771 if (mode & MODE_I2C_READ)
772 msg[2] = AUX_I2C_READ << 4;
773 else
774 msg[2] = AUX_I2C_WRITE << 4;
775
776 if (!(mode & MODE_I2C_STOP))
777 msg[2] |= AUX_I2C_MOT << 4;
778 873
779 msg[0] = address; 874 if (!radeon_encoder->enc_priv)
780 msg[1] = address >> 8; 875 return;
876 dig = radeon_encoder->enc_priv;
781 877
782 reply_bytes = 1; 878 radeon_connector = to_radeon_connector(connector);
879 if (!radeon_connector->con_priv)
880 return;
881 dig_connector = radeon_connector->con_priv;
783 882
784 msg_len = 4; 883 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
785 dp_msg_len = 3; 884 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
786 switch (mode) { 885 return;
787 case MODE_I2C_WRITE:
788 msg[4] = write_byte;
789 msg_len++;
790 dp_msg_len += 2;
791 break;
792 case MODE_I2C_READ:
793 dp_msg_len += 1;
794 break;
795 default:
796 break;
797 }
798 886
799 msg[3] = (dp_msg_len) << 4; 887 dp_info.enc_id = 0;
800 ret = radeon_process_aux_ch(auxch, msg, msg_len, reply, reply_bytes, 0); 888 if (dig->dig_encoder)
889 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
890 else
891 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
892 if (dig->linkb)
893 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
894 else
895 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
801 896
802 if (ret) { 897 dp_info.rd_interval = radeon_read_dpcd_reg(radeon_connector, DP_TRAINING_AUX_RD_INTERVAL);
803 if (read_byte) 898 tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
804 *read_byte = reply[0]; 899 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
805 return reply_bytes; 900 dp_info.tp3_supported = true;
806 } 901 else
807 return -EREMOTEIO; 902 dp_info.tp3_supported = false;
903
904 memcpy(dp_info.dpcd, dig_connector->dpcd, 8);
905 dp_info.rdev = rdev;
906 dp_info.encoder = encoder;
907 dp_info.connector = connector;
908 dp_info.radeon_connector = radeon_connector;
909 dp_info.dp_lane_count = dig_connector->dp_lane_count;
910 dp_info.dp_clock = dig_connector->dp_clock;
911
912 if (radeon_dp_link_train_init(&dp_info))
913 goto done;
914 if (radeon_dp_link_train_cr(&dp_info))
915 goto done;
916 if (radeon_dp_link_train_ce(&dp_info))
917 goto done;
918done:
919 if (radeon_dp_link_train_finish(&dp_info))
920 return;
808} 921}
809
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index c20eac3379e6..34cd5a878088 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1578,7 +1578,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1578 u32 sq_stack_resource_mgmt_2; 1578 u32 sq_stack_resource_mgmt_2;
1579 u32 sq_stack_resource_mgmt_3; 1579 u32 sq_stack_resource_mgmt_3;
1580 u32 vgt_cache_invalidation; 1580 u32 vgt_cache_invalidation;
1581 u32 hdp_host_path_cntl; 1581 u32 hdp_host_path_cntl, tmp;
1582 int i, j, num_shader_engines, ps_thread_count; 1582 int i, j, num_shader_engines, ps_thread_count;
1583 1583
1584 switch (rdev->family) { 1584 switch (rdev->family) {
@@ -1933,8 +1933,12 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1933 rdev->config.evergreen.tile_config |= (3 << 0); 1933 rdev->config.evergreen.tile_config |= (3 << 0);
1934 break; 1934 break;
1935 } 1935 }
1936 rdev->config.evergreen.tile_config |= 1936 /* num banks is 8 on all fusion asics */
1937 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; 1937 if (rdev->flags & RADEON_IS_IGP)
1938 rdev->config.evergreen.tile_config |= 8 << 4;
1939 else
1940 rdev->config.evergreen.tile_config |=
1941 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1938 rdev->config.evergreen.tile_config |= 1942 rdev->config.evergreen.tile_config |=
1939 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8; 1943 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1940 rdev->config.evergreen.tile_config |= 1944 rdev->config.evergreen.tile_config |=
@@ -2138,6 +2142,10 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
2138 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4) 2142 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2139 WREG32(i, 0); 2143 WREG32(i, 0);
2140 2144
2145 tmp = RREG32(HDP_MISC_CNTL);
2146 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2147 WREG32(HDP_MISC_CNTL, tmp);
2148
2141 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 2149 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2142 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 2150 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2143 2151
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 94533849927e..75b57e394f2b 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -64,6 +64,8 @@
64#define GB_BACKEND_MAP 0x98FC 64#define GB_BACKEND_MAP 0x98FC
65#define DMIF_ADDR_CONFIG 0xBD4 65#define DMIF_ADDR_CONFIG 0xBD4
66#define HDP_ADDR_CONFIG 0x2F48 66#define HDP_ADDR_CONFIG 0x2F48
67#define HDP_MISC_CNTL 0x2F4C
68#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
67 69
68#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 70#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
69#define GC_USER_RB_BACKEND_DISABLE 0x9B7C 71#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 7aade20f63a8..a0cc7a5ff031 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -417,7 +417,7 @@ static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
417 num_shader_engines = 1; 417 num_shader_engines = 1;
418 if (num_shader_engines > rdev->config.cayman.max_shader_engines) 418 if (num_shader_engines > rdev->config.cayman.max_shader_engines)
419 num_shader_engines = rdev->config.cayman.max_shader_engines; 419 num_shader_engines = rdev->config.cayman.max_shader_engines;
420 if (num_backends_per_asic > num_shader_engines) 420 if (num_backends_per_asic < num_shader_engines)
421 num_backends_per_asic = num_shader_engines; 421 num_backends_per_asic = num_shader_engines;
422 if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines)) 422 if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines))
423 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines; 423 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines;
@@ -829,7 +829,7 @@ static void cayman_gpu_init(struct radeon_device *rdev)
829 rdev->config.cayman.tile_config |= 829 rdev->config.cayman.tile_config |=
830 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; 830 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
831 rdev->config.cayman.tile_config |= 831 rdev->config.cayman.tile_config |=
832 (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT; 832 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
833 rdev->config.cayman.tile_config |= 833 rdev->config.cayman.tile_config |=
834 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; 834 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
835 835
@@ -931,6 +931,10 @@ static void cayman_gpu_init(struct radeon_device *rdev)
931 WREG32(CB_PERF_CTR3_SEL_0, 0); 931 WREG32(CB_PERF_CTR3_SEL_0, 0);
932 WREG32(CB_PERF_CTR3_SEL_1, 0); 932 WREG32(CB_PERF_CTR3_SEL_1, 0);
933 933
934 tmp = RREG32(HDP_MISC_CNTL);
935 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
936 WREG32(HDP_MISC_CNTL, tmp);
937
934 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 938 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
935 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 939 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
936 940
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 0f9a08b53fbd..9736746da2d6 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -136,6 +136,8 @@
136#define HDP_NONSURFACE_INFO 0x2C08 136#define HDP_NONSURFACE_INFO 0x2C08
137#define HDP_NONSURFACE_SIZE 0x2C0C 137#define HDP_NONSURFACE_SIZE 0x2C0C
138#define HDP_ADDR_CONFIG 0x2F48 138#define HDP_ADDR_CONFIG 0x2F48
139#define HDP_MISC_CNTL 0x2F4C
140#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
139 141
140#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 142#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
141#define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C 143#define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C
@@ -351,7 +353,7 @@
351#define MULTI_GPU_TILE_SIZE_MASK 0x03000000 353#define MULTI_GPU_TILE_SIZE_MASK 0x03000000
352#define MULTI_GPU_TILE_SIZE_SHIFT 24 354#define MULTI_GPU_TILE_SIZE_SHIFT 24
353#define ROW_SIZE(x) ((x) << 28) 355#define ROW_SIZE(x) ((x) << 28)
354#define ROW_SIZE_MASK 0x30000007 356#define ROW_SIZE_MASK 0x30000000
355#define ROW_SIZE_SHIFT 28 357#define ROW_SIZE_SHIFT 28
356#define NUM_LOWER_PIPES(x) ((x) << 30) 358#define NUM_LOWER_PIPES(x) ((x) << 30)
357#define NUM_LOWER_PIPES_MASK 0x40000000 359#define NUM_LOWER_PIPES_MASK 0x40000000
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index ca576191d058..d948265db87e 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -782,6 +782,7 @@ static struct radeon_asic evergreen_asic = {
782 .hpd_fini = &evergreen_hpd_fini, 782 .hpd_fini = &evergreen_hpd_fini,
783 .hpd_sense = &evergreen_hpd_sense, 783 .hpd_sense = &evergreen_hpd_sense,
784 .hpd_set_polarity = &evergreen_hpd_set_polarity, 784 .hpd_set_polarity = &evergreen_hpd_set_polarity,
785 .ioctl_wait_idle = r600_ioctl_wait_idle,
785 .gui_idle = &r600_gui_idle, 786 .gui_idle = &r600_gui_idle,
786 .pm_misc = &evergreen_pm_misc, 787 .pm_misc = &evergreen_pm_misc,
787 .pm_prepare = &evergreen_pm_prepare, 788 .pm_prepare = &evergreen_pm_prepare,
@@ -828,6 +829,7 @@ static struct radeon_asic sumo_asic = {
828 .hpd_fini = &evergreen_hpd_fini, 829 .hpd_fini = &evergreen_hpd_fini,
829 .hpd_sense = &evergreen_hpd_sense, 830 .hpd_sense = &evergreen_hpd_sense,
830 .hpd_set_polarity = &evergreen_hpd_set_polarity, 831 .hpd_set_polarity = &evergreen_hpd_set_polarity,
832 .ioctl_wait_idle = r600_ioctl_wait_idle,
831 .gui_idle = &r600_gui_idle, 833 .gui_idle = &r600_gui_idle,
832 .pm_misc = &evergreen_pm_misc, 834 .pm_misc = &evergreen_pm_misc,
833 .pm_prepare = &evergreen_pm_prepare, 835 .pm_prepare = &evergreen_pm_prepare,
@@ -874,6 +876,7 @@ static struct radeon_asic btc_asic = {
874 .hpd_fini = &evergreen_hpd_fini, 876 .hpd_fini = &evergreen_hpd_fini,
875 .hpd_sense = &evergreen_hpd_sense, 877 .hpd_sense = &evergreen_hpd_sense,
876 .hpd_set_polarity = &evergreen_hpd_set_polarity, 878 .hpd_set_polarity = &evergreen_hpd_set_polarity,
879 .ioctl_wait_idle = r600_ioctl_wait_idle,
877 .gui_idle = &r600_gui_idle, 880 .gui_idle = &r600_gui_idle,
878 .pm_misc = &evergreen_pm_misc, 881 .pm_misc = &evergreen_pm_misc,
879 .pm_prepare = &evergreen_pm_prepare, 882 .pm_prepare = &evergreen_pm_prepare,
@@ -920,6 +923,7 @@ static struct radeon_asic cayman_asic = {
920 .hpd_fini = &evergreen_hpd_fini, 923 .hpd_fini = &evergreen_hpd_fini,
921 .hpd_sense = &evergreen_hpd_sense, 924 .hpd_sense = &evergreen_hpd_sense,
922 .hpd_set_polarity = &evergreen_hpd_set_polarity, 925 .hpd_set_polarity = &evergreen_hpd_set_polarity,
926 .ioctl_wait_idle = r600_ioctl_wait_idle,
923 .gui_idle = &r600_gui_idle, 927 .gui_idle = &r600_gui_idle,
924 .pm_misc = &evergreen_pm_misc, 928 .pm_misc = &evergreen_pm_misc,
925 .pm_prepare = &evergreen_pm_prepare, 929 .pm_prepare = &evergreen_pm_prepare,
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 5f45fa12bb8b..ee1dccb3fec9 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -50,20 +50,21 @@ void radeon_connector_hotplug(struct drm_connector *connector)
50 struct radeon_device *rdev = dev->dev_private; 50 struct radeon_device *rdev = dev->dev_private;
51 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 51 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
52 52
53 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 53 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
54 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 54
55 55 /* powering up/down the eDP panel generates hpd events which
56 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 56 * can interfere with modesetting.
57 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 57 */
58 if ((radeon_dp_getsinktype(radeon_connector) == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 58 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
59 (radeon_dp_getsinktype(radeon_connector) == CONNECTOR_OBJECT_ID_eDP)) { 59 return;
60 if (radeon_dp_needs_link_train(radeon_connector)) {
61 if (connector->encoder)
62 dp_link_train(connector->encoder, connector);
63 }
64 }
65 }
66 60
61 /* pre-r600 did not always have the hpd pins mapped accurately to connectors */
62 if (rdev->family >= CHIP_R600) {
63 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
64 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
65 else
66 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
67 }
67} 68}
68 69
69static void radeon_property_change_mode(struct drm_encoder *encoder) 70static void radeon_property_change_mode(struct drm_encoder *encoder)
@@ -1054,23 +1055,124 @@ static int radeon_dp_get_modes(struct drm_connector *connector)
1054 int ret; 1055 int ret;
1055 1056
1056 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1057 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1058 struct drm_encoder *encoder;
1059 struct drm_display_mode *mode;
1060
1057 if (!radeon_dig_connector->edp_on) 1061 if (!radeon_dig_connector->edp_on)
1058 atombios_set_edp_panel_power(connector, 1062 atombios_set_edp_panel_power(connector,
1059 ATOM_TRANSMITTER_ACTION_POWER_ON); 1063 ATOM_TRANSMITTER_ACTION_POWER_ON);
1060 } 1064 ret = radeon_ddc_get_modes(radeon_connector);
1061 ret = radeon_ddc_get_modes(radeon_connector);
1062 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1063 if (!radeon_dig_connector->edp_on) 1065 if (!radeon_dig_connector->edp_on)
1064 atombios_set_edp_panel_power(connector, 1066 atombios_set_edp_panel_power(connector,
1065 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1067 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1066 } 1068
1069 if (ret > 0) {
1070 encoder = radeon_best_single_encoder(connector);
1071 if (encoder) {
1072 radeon_fixup_lvds_native_mode(encoder, connector);
1073 /* add scaled modes */
1074 radeon_add_common_modes(encoder, connector);
1075 }
1076 return ret;
1077 }
1078
1079 encoder = radeon_best_single_encoder(connector);
1080 if (!encoder)
1081 return 0;
1082
1083 /* we have no EDID modes */
1084 mode = radeon_fp_native_mode(encoder);
1085 if (mode) {
1086 ret = 1;
1087 drm_mode_probed_add(connector, mode);
1088 /* add the width/height from vbios tables if available */
1089 connector->display_info.width_mm = mode->width_mm;
1090 connector->display_info.height_mm = mode->height_mm;
1091 /* add scaled modes */
1092 radeon_add_common_modes(encoder, connector);
1093 }
1094 } else
1095 ret = radeon_ddc_get_modes(radeon_connector);
1067 1096
1068 return ret; 1097 return ret;
1069} 1098}
1070 1099
1100bool radeon_connector_encoder_is_dp_bridge(struct drm_connector *connector)
1101{
1102 struct drm_mode_object *obj;
1103 struct drm_encoder *encoder;
1104 struct radeon_encoder *radeon_encoder;
1105 int i;
1106 bool found = false;
1107
1108 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1109 if (connector->encoder_ids[i] == 0)
1110 break;
1111
1112 obj = drm_mode_object_find(connector->dev, connector->encoder_ids[i], DRM_MODE_OBJECT_ENCODER);
1113 if (!obj)
1114 continue;
1115
1116 encoder = obj_to_encoder(obj);
1117 radeon_encoder = to_radeon_encoder(encoder);
1118
1119 switch (radeon_encoder->encoder_id) {
1120 case ENCODER_OBJECT_ID_TRAVIS:
1121 case ENCODER_OBJECT_ID_NUTMEG:
1122 found = true;
1123 break;
1124 default:
1125 break;
1126 }
1127 }
1128
1129 return found;
1130}
1131
1132bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector)
1133{
1134 struct drm_mode_object *obj;
1135 struct drm_encoder *encoder;
1136 struct radeon_encoder *radeon_encoder;
1137 int i;
1138 bool found = false;
1139
1140 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1141 if (connector->encoder_ids[i] == 0)
1142 break;
1143
1144 obj = drm_mode_object_find(connector->dev, connector->encoder_ids[i], DRM_MODE_OBJECT_ENCODER);
1145 if (!obj)
1146 continue;
1147
1148 encoder = obj_to_encoder(obj);
1149 radeon_encoder = to_radeon_encoder(encoder);
1150 if (radeon_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1151 found = true;
1152 }
1153
1154 return found;
1155}
1156
1157bool radeon_connector_is_dp12_capable(struct drm_connector *connector)
1158{
1159 struct drm_device *dev = connector->dev;
1160 struct radeon_device *rdev = dev->dev_private;
1161
1162 if (ASIC_IS_DCE5(rdev) &&
1163 (rdev->clock.dp_extclk >= 53900) &&
1164 radeon_connector_encoder_is_hbr2(connector)) {
1165 return true;
1166 }
1167
1168 return false;
1169}
1170
1071static enum drm_connector_status 1171static enum drm_connector_status
1072radeon_dp_detect(struct drm_connector *connector, bool force) 1172radeon_dp_detect(struct drm_connector *connector, bool force)
1073{ 1173{
1174 struct drm_device *dev = connector->dev;
1175 struct radeon_device *rdev = dev->dev_private;
1074 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1176 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1075 enum drm_connector_status ret = connector_status_disconnected; 1177 enum drm_connector_status ret = connector_status_disconnected;
1076 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; 1178 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
@@ -1081,6 +1183,15 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
1081 } 1183 }
1082 1184
1083 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1185 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1186 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
1187 if (encoder) {
1188 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1189 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
1190
1191 /* check if panel is valid */
1192 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1193 ret = connector_status_connected;
1194 }
1084 /* eDP is always DP */ 1195 /* eDP is always DP */
1085 radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1196 radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1086 if (!radeon_dig_connector->edp_on) 1197 if (!radeon_dig_connector->edp_on)
@@ -1093,12 +1204,18 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
1093 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1204 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1094 } else { 1205 } else {
1095 radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector); 1206 radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector);
1096 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1207 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
1097 if (radeon_dp_getdpcd(radeon_connector)) 1208 ret = connector_status_connected;
1098 ret = connector_status_connected; 1209 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1210 radeon_dp_getdpcd(radeon_connector);
1099 } else { 1211 } else {
1100 if (radeon_ddc_probe(radeon_connector)) 1212 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1101 ret = connector_status_connected; 1213 if (radeon_dp_getdpcd(radeon_connector))
1214 ret = connector_status_connected;
1215 } else {
1216 if (radeon_ddc_probe(radeon_connector))
1217 ret = connector_status_connected;
1218 }
1102 } 1219 }
1103 } 1220 }
1104 1221
@@ -1114,11 +1231,38 @@ static int radeon_dp_mode_valid(struct drm_connector *connector,
1114 1231
1115 /* XXX check mode bandwidth */ 1232 /* XXX check mode bandwidth */
1116 1233
1117 if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1234 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1118 (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 1235 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
1119 return radeon_dp_mode_valid_helper(radeon_connector, mode); 1236
1120 else 1237 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1238 return MODE_PANEL;
1239
1240 if (encoder) {
1241 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1242 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
1243
1244 /* AVIVO hardware supports downscaling modes larger than the panel
1245 * to the panel size, but I'm not sure this is desirable.
1246 */
1247 if ((mode->hdisplay > native_mode->hdisplay) ||
1248 (mode->vdisplay > native_mode->vdisplay))
1249 return MODE_PANEL;
1250
1251 /* if scaling is disabled, block non-native modes */
1252 if (radeon_encoder->rmx_type == RMX_OFF) {
1253 if ((mode->hdisplay != native_mode->hdisplay) ||
1254 (mode->vdisplay != native_mode->vdisplay))
1255 return MODE_PANEL;
1256 }
1257 }
1121 return MODE_OK; 1258 return MODE_OK;
1259 } else {
1260 if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1261 (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
1262 return radeon_dp_mode_valid_helper(connector, mode);
1263 else
1264 return MODE_OK;
1265 }
1122} 1266}
1123 1267
1124struct drm_connector_helper_funcs radeon_dp_connector_helper_funcs = { 1268struct drm_connector_helper_funcs radeon_dp_connector_helper_funcs = {
@@ -1151,8 +1295,11 @@ radeon_add_atom_connector(struct drm_device *dev,
1151 struct drm_connector *connector; 1295 struct drm_connector *connector;
1152 struct radeon_connector *radeon_connector; 1296 struct radeon_connector *radeon_connector;
1153 struct radeon_connector_atom_dig *radeon_dig_connector; 1297 struct radeon_connector_atom_dig *radeon_dig_connector;
1298 struct drm_encoder *encoder;
1299 struct radeon_encoder *radeon_encoder;
1154 uint32_t subpixel_order = SubPixelNone; 1300 uint32_t subpixel_order = SubPixelNone;
1155 bool shared_ddc = false; 1301 bool shared_ddc = false;
1302 bool is_dp_bridge = false;
1156 1303
1157 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1304 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1158 return; 1305 return;
@@ -1184,6 +1331,21 @@ radeon_add_atom_connector(struct drm_device *dev,
1184 } 1331 }
1185 } 1332 }
1186 1333
1334 /* check if it's a dp bridge */
1335 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1336 radeon_encoder = to_radeon_encoder(encoder);
1337 if (radeon_encoder->devices & supported_device) {
1338 switch (radeon_encoder->encoder_id) {
1339 case ENCODER_OBJECT_ID_TRAVIS:
1340 case ENCODER_OBJECT_ID_NUTMEG:
1341 is_dp_bridge = true;
1342 break;
1343 default:
1344 break;
1345 }
1346 }
1347 }
1348
1187 radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL); 1349 radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL);
1188 if (!radeon_connector) 1350 if (!radeon_connector)
1189 return; 1351 return;
@@ -1201,61 +1363,39 @@ radeon_add_atom_connector(struct drm_device *dev,
1201 if (!radeon_connector->router_bus) 1363 if (!radeon_connector->router_bus)
1202 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1364 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1203 } 1365 }
1204 switch (connector_type) { 1366
1205 case DRM_MODE_CONNECTOR_VGA: 1367 if (is_dp_bridge) {
1206 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
1207 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
1208 if (i2c_bus->valid) {
1209 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1210 if (!radeon_connector->ddc_bus)
1211 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1212 }
1213 radeon_connector->dac_load_detect = true;
1214 drm_connector_attach_property(&radeon_connector->base,
1215 rdev->mode_info.load_detect_property,
1216 1);
1217 /* no HPD on analog connectors */
1218 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1219 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1220 connector->interlace_allowed = true;
1221 connector->doublescan_allowed = true;
1222 break;
1223 case DRM_MODE_CONNECTOR_DVIA:
1224 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
1225 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
1226 if (i2c_bus->valid) {
1227 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1228 if (!radeon_connector->ddc_bus)
1229 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1230 }
1231 radeon_connector->dac_load_detect = true;
1232 drm_connector_attach_property(&radeon_connector->base,
1233 rdev->mode_info.load_detect_property,
1234 1);
1235 /* no HPD on analog connectors */
1236 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1237 connector->interlace_allowed = true;
1238 connector->doublescan_allowed = true;
1239 break;
1240 case DRM_MODE_CONNECTOR_DVII:
1241 case DRM_MODE_CONNECTOR_DVID:
1242 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); 1368 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1243 if (!radeon_dig_connector) 1369 if (!radeon_dig_connector)
1244 goto failed; 1370 goto failed;
1245 radeon_dig_connector->igp_lane_info = igp_lane_info; 1371 radeon_dig_connector->igp_lane_info = igp_lane_info;
1246 radeon_connector->con_priv = radeon_dig_connector; 1372 radeon_connector->con_priv = radeon_dig_connector;
1247 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); 1373 drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type);
1248 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); 1374 drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
1249 if (i2c_bus->valid) { 1375 if (i2c_bus->valid) {
1376 /* add DP i2c bus */
1377 if (connector_type == DRM_MODE_CONNECTOR_eDP)
1378 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "eDP-auxch");
1379 else
1380 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch");
1381 if (!radeon_dig_connector->dp_i2c_bus)
1382 DRM_ERROR("DP: Failed to assign dp ddc bus! Check dmesg for i2c errors.\n");
1250 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); 1383 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1251 if (!radeon_connector->ddc_bus) 1384 if (!radeon_connector->ddc_bus)
1252 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1385 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1253 } 1386 }
1254 subpixel_order = SubPixelHorizontalRGB; 1387 switch (connector_type) {
1255 drm_connector_attach_property(&radeon_connector->base, 1388 case DRM_MODE_CONNECTOR_VGA:
1256 rdev->mode_info.coherent_mode_property, 1389 case DRM_MODE_CONNECTOR_DVIA:
1257 1); 1390 default:
1258 if (ASIC_IS_AVIVO(rdev)) { 1391 connector->interlace_allowed = true;
1392 connector->doublescan_allowed = true;
1393 break;
1394 case DRM_MODE_CONNECTOR_DVII:
1395 case DRM_MODE_CONNECTOR_DVID:
1396 case DRM_MODE_CONNECTOR_HDMIA:
1397 case DRM_MODE_CONNECTOR_HDMIB:
1398 case DRM_MODE_CONNECTOR_DisplayPort:
1259 drm_connector_attach_property(&radeon_connector->base, 1399 drm_connector_attach_property(&radeon_connector->base,
1260 rdev->mode_info.underscan_property, 1400 rdev->mode_info.underscan_property,
1261 UNDERSCAN_OFF); 1401 UNDERSCAN_OFF);
@@ -1265,131 +1405,234 @@ radeon_add_atom_connector(struct drm_device *dev,
1265 drm_connector_attach_property(&radeon_connector->base, 1405 drm_connector_attach_property(&radeon_connector->base,
1266 rdev->mode_info.underscan_vborder_property, 1406 rdev->mode_info.underscan_vborder_property,
1267 0); 1407 0);
1408 subpixel_order = SubPixelHorizontalRGB;
1409 connector->interlace_allowed = true;
1410 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1411 connector->doublescan_allowed = true;
1412 else
1413 connector->doublescan_allowed = false;
1414 break;
1415 case DRM_MODE_CONNECTOR_LVDS:
1416 case DRM_MODE_CONNECTOR_eDP:
1417 drm_connector_attach_property(&radeon_connector->base,
1418 dev->mode_config.scaling_mode_property,
1419 DRM_MODE_SCALE_FULLSCREEN);
1420 subpixel_order = SubPixelHorizontalRGB;
1421 connector->interlace_allowed = false;
1422 connector->doublescan_allowed = false;
1423 break;
1268 } 1424 }
1269 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1425 } else {
1426 switch (connector_type) {
1427 case DRM_MODE_CONNECTOR_VGA:
1428 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
1429 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
1430 if (i2c_bus->valid) {
1431 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1432 if (!radeon_connector->ddc_bus)
1433 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1434 }
1270 radeon_connector->dac_load_detect = true; 1435 radeon_connector->dac_load_detect = true;
1271 drm_connector_attach_property(&radeon_connector->base, 1436 drm_connector_attach_property(&radeon_connector->base,
1272 rdev->mode_info.load_detect_property, 1437 rdev->mode_info.load_detect_property,
1273 1); 1438 1);
1274 } 1439 /* no HPD on analog connectors */
1275 connector->interlace_allowed = true; 1440 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1276 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1441 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1442 connector->interlace_allowed = true;
1277 connector->doublescan_allowed = true; 1443 connector->doublescan_allowed = true;
1278 else 1444 break;
1279 connector->doublescan_allowed = false; 1445 case DRM_MODE_CONNECTOR_DVIA:
1280 break; 1446 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
1281 case DRM_MODE_CONNECTOR_HDMIA: 1447 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
1282 case DRM_MODE_CONNECTOR_HDMIB: 1448 if (i2c_bus->valid) {
1283 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); 1449 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1284 if (!radeon_dig_connector) 1450 if (!radeon_connector->ddc_bus)
1285 goto failed; 1451 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1286 radeon_dig_connector->igp_lane_info = igp_lane_info; 1452 }
1287 radeon_connector->con_priv = radeon_dig_connector; 1453 radeon_connector->dac_load_detect = true;
1288 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
1289 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
1290 if (i2c_bus->valid) {
1291 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1292 if (!radeon_connector->ddc_bus)
1293 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1294 }
1295 drm_connector_attach_property(&radeon_connector->base,
1296 rdev->mode_info.coherent_mode_property,
1297 1);
1298 if (ASIC_IS_AVIVO(rdev)) {
1299 drm_connector_attach_property(&radeon_connector->base, 1454 drm_connector_attach_property(&radeon_connector->base,
1300 rdev->mode_info.underscan_property, 1455 rdev->mode_info.load_detect_property,
1301 UNDERSCAN_OFF); 1456 1);
1457 /* no HPD on analog connectors */
1458 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1459 connector->interlace_allowed = true;
1460 connector->doublescan_allowed = true;
1461 break;
1462 case DRM_MODE_CONNECTOR_DVII:
1463 case DRM_MODE_CONNECTOR_DVID:
1464 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1465 if (!radeon_dig_connector)
1466 goto failed;
1467 radeon_dig_connector->igp_lane_info = igp_lane_info;
1468 radeon_connector->con_priv = radeon_dig_connector;
1469 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
1470 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
1471 if (i2c_bus->valid) {
1472 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1473 if (!radeon_connector->ddc_bus)
1474 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1475 }
1476 subpixel_order = SubPixelHorizontalRGB;
1302 drm_connector_attach_property(&radeon_connector->base, 1477 drm_connector_attach_property(&radeon_connector->base,
1303 rdev->mode_info.underscan_hborder_property, 1478 rdev->mode_info.coherent_mode_property,
1304 0); 1479 1);
1480 if (ASIC_IS_AVIVO(rdev)) {
1481 drm_connector_attach_property(&radeon_connector->base,
1482 rdev->mode_info.underscan_property,
1483 UNDERSCAN_OFF);
1484 drm_connector_attach_property(&radeon_connector->base,
1485 rdev->mode_info.underscan_hborder_property,
1486 0);
1487 drm_connector_attach_property(&radeon_connector->base,
1488 rdev->mode_info.underscan_vborder_property,
1489 0);
1490 }
1491 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1492 radeon_connector->dac_load_detect = true;
1493 drm_connector_attach_property(&radeon_connector->base,
1494 rdev->mode_info.load_detect_property,
1495 1);
1496 }
1497 connector->interlace_allowed = true;
1498 if (connector_type == DRM_MODE_CONNECTOR_DVII)
1499 connector->doublescan_allowed = true;
1500 else
1501 connector->doublescan_allowed = false;
1502 break;
1503 case DRM_MODE_CONNECTOR_HDMIA:
1504 case DRM_MODE_CONNECTOR_HDMIB:
1505 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1506 if (!radeon_dig_connector)
1507 goto failed;
1508 radeon_dig_connector->igp_lane_info = igp_lane_info;
1509 radeon_connector->con_priv = radeon_dig_connector;
1510 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
1511 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
1512 if (i2c_bus->valid) {
1513 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1514 if (!radeon_connector->ddc_bus)
1515 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1516 }
1305 drm_connector_attach_property(&radeon_connector->base, 1517 drm_connector_attach_property(&radeon_connector->base,
1306 rdev->mode_info.underscan_vborder_property, 1518 rdev->mode_info.coherent_mode_property,
1307 0); 1519 1);
1308 } 1520 if (ASIC_IS_AVIVO(rdev)) {
1309 subpixel_order = SubPixelHorizontalRGB; 1521 drm_connector_attach_property(&radeon_connector->base,
1310 connector->interlace_allowed = true; 1522 rdev->mode_info.underscan_property,
1311 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1523 UNDERSCAN_OFF);
1312 connector->doublescan_allowed = true; 1524 drm_connector_attach_property(&radeon_connector->base,
1313 else 1525 rdev->mode_info.underscan_hborder_property,
1314 connector->doublescan_allowed = false; 1526 0);
1315 break; 1527 drm_connector_attach_property(&radeon_connector->base,
1316 case DRM_MODE_CONNECTOR_DisplayPort: 1528 rdev->mode_info.underscan_vborder_property,
1317 case DRM_MODE_CONNECTOR_eDP: 1529 0);
1318 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); 1530 }
1319 if (!radeon_dig_connector) 1531 subpixel_order = SubPixelHorizontalRGB;
1320 goto failed; 1532 connector->interlace_allowed = true;
1321 radeon_dig_connector->igp_lane_info = igp_lane_info; 1533 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1322 radeon_connector->con_priv = radeon_dig_connector; 1534 connector->doublescan_allowed = true;
1323 drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type);
1324 drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
1325 if (i2c_bus->valid) {
1326 /* add DP i2c bus */
1327 if (connector_type == DRM_MODE_CONNECTOR_eDP)
1328 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "eDP-auxch");
1329 else 1535 else
1536 connector->doublescan_allowed = false;
1537 break;
1538 case DRM_MODE_CONNECTOR_DisplayPort:
1539 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1540 if (!radeon_dig_connector)
1541 goto failed;
1542 radeon_dig_connector->igp_lane_info = igp_lane_info;
1543 radeon_connector->con_priv = radeon_dig_connector;
1544 drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type);
1545 drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
1546 if (i2c_bus->valid) {
1547 /* add DP i2c bus */
1330 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch"); 1548 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch");
1331 if (!radeon_dig_connector->dp_i2c_bus) 1549 if (!radeon_dig_connector->dp_i2c_bus)
1332 DRM_ERROR("DP: Failed to assign dp ddc bus! Check dmesg for i2c errors.\n"); 1550 DRM_ERROR("DP: Failed to assign dp ddc bus! Check dmesg for i2c errors.\n");
1333 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); 1551 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1334 if (!radeon_connector->ddc_bus) 1552 if (!radeon_connector->ddc_bus)
1335 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1553 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1336 } 1554 }
1337 subpixel_order = SubPixelHorizontalRGB; 1555 subpixel_order = SubPixelHorizontalRGB;
1338 drm_connector_attach_property(&radeon_connector->base,
1339 rdev->mode_info.coherent_mode_property,
1340 1);
1341 if (ASIC_IS_AVIVO(rdev)) {
1342 drm_connector_attach_property(&radeon_connector->base, 1556 drm_connector_attach_property(&radeon_connector->base,
1343 rdev->mode_info.underscan_property, 1557 rdev->mode_info.coherent_mode_property,
1344 UNDERSCAN_OFF); 1558 1);
1559 if (ASIC_IS_AVIVO(rdev)) {
1560 drm_connector_attach_property(&radeon_connector->base,
1561 rdev->mode_info.underscan_property,
1562 UNDERSCAN_OFF);
1563 drm_connector_attach_property(&radeon_connector->base,
1564 rdev->mode_info.underscan_hborder_property,
1565 0);
1566 drm_connector_attach_property(&radeon_connector->base,
1567 rdev->mode_info.underscan_vborder_property,
1568 0);
1569 }
1570 connector->interlace_allowed = true;
1571 /* in theory with a DP to VGA converter... */
1572 connector->doublescan_allowed = false;
1573 break;
1574 case DRM_MODE_CONNECTOR_eDP:
1575 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1576 if (!radeon_dig_connector)
1577 goto failed;
1578 radeon_dig_connector->igp_lane_info = igp_lane_info;
1579 radeon_connector->con_priv = radeon_dig_connector;
1580 drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type);
1581 drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
1582 if (i2c_bus->valid) {
1583 /* add DP i2c bus */
1584 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "eDP-auxch");
1585 if (!radeon_dig_connector->dp_i2c_bus)
1586 DRM_ERROR("DP: Failed to assign dp ddc bus! Check dmesg for i2c errors.\n");
1587 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1588 if (!radeon_connector->ddc_bus)
1589 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1590 }
1345 drm_connector_attach_property(&radeon_connector->base, 1591 drm_connector_attach_property(&radeon_connector->base,
1346 rdev->mode_info.underscan_hborder_property, 1592 dev->mode_config.scaling_mode_property,
1347 0); 1593 DRM_MODE_SCALE_FULLSCREEN);
1594 subpixel_order = SubPixelHorizontalRGB;
1595 connector->interlace_allowed = false;
1596 connector->doublescan_allowed = false;
1597 break;
1598 case DRM_MODE_CONNECTOR_SVIDEO:
1599 case DRM_MODE_CONNECTOR_Composite:
1600 case DRM_MODE_CONNECTOR_9PinDIN:
1601 drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
1602 drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
1603 radeon_connector->dac_load_detect = true;
1348 drm_connector_attach_property(&radeon_connector->base, 1604 drm_connector_attach_property(&radeon_connector->base,
1349 rdev->mode_info.underscan_vborder_property, 1605 rdev->mode_info.load_detect_property,
1350 0); 1606 1);
1351 } 1607 drm_connector_attach_property(&radeon_connector->base,
1352 connector->interlace_allowed = true; 1608 rdev->mode_info.tv_std_property,
1353 /* in theory with a DP to VGA converter... */ 1609 radeon_atombios_get_tv_info(rdev));
1354 connector->doublescan_allowed = false; 1610 /* no HPD on analog connectors */
1355 break; 1611 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1356 case DRM_MODE_CONNECTOR_SVIDEO: 1612 connector->interlace_allowed = false;
1357 case DRM_MODE_CONNECTOR_Composite: 1613 connector->doublescan_allowed = false;
1358 case DRM_MODE_CONNECTOR_9PinDIN: 1614 break;
1359 drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); 1615 case DRM_MODE_CONNECTOR_LVDS:
1360 drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); 1616 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1361 radeon_connector->dac_load_detect = true; 1617 if (!radeon_dig_connector)
1362 drm_connector_attach_property(&radeon_connector->base, 1618 goto failed;
1363 rdev->mode_info.load_detect_property, 1619 radeon_dig_connector->igp_lane_info = igp_lane_info;
1364 1); 1620 radeon_connector->con_priv = radeon_dig_connector;
1365 drm_connector_attach_property(&radeon_connector->base, 1621 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
1366 rdev->mode_info.tv_std_property, 1622 drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs);
1367 radeon_atombios_get_tv_info(rdev)); 1623 if (i2c_bus->valid) {
1368 /* no HPD on analog connectors */ 1624 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1369 radeon_connector->hpd.hpd = RADEON_HPD_NONE; 1625 if (!radeon_connector->ddc_bus)
1370 connector->interlace_allowed = false; 1626 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1371 connector->doublescan_allowed = false; 1627 }
1372 break; 1628 drm_connector_attach_property(&radeon_connector->base,
1373 case DRM_MODE_CONNECTOR_LVDS: 1629 dev->mode_config.scaling_mode_property,
1374 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); 1630 DRM_MODE_SCALE_FULLSCREEN);
1375 if (!radeon_dig_connector) 1631 subpixel_order = SubPixelHorizontalRGB;
1376 goto failed; 1632 connector->interlace_allowed = false;
1377 radeon_dig_connector->igp_lane_info = igp_lane_info; 1633 connector->doublescan_allowed = false;
1378 radeon_connector->con_priv = radeon_dig_connector; 1634 break;
1379 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
1380 drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs);
1381 if (i2c_bus->valid) {
1382 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1383 if (!radeon_connector->ddc_bus)
1384 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1385 } 1635 }
1386 drm_connector_attach_property(&radeon_connector->base,
1387 dev->mode_config.scaling_mode_property,
1388 DRM_MODE_SCALE_FULLSCREEN);
1389 subpixel_order = SubPixelHorizontalRGB;
1390 connector->interlace_allowed = false;
1391 connector->doublescan_allowed = false;
1392 break;
1393 } 1636 }
1394 1637
1395 if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) { 1638 if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) {
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 890217e678d3..5b61364e31f4 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -923,6 +923,9 @@ int radeon_resume_kms(struct drm_device *dev)
923 radeon_fbdev_set_suspend(rdev, 0); 923 radeon_fbdev_set_suspend(rdev, 0);
924 console_unlock(); 924 console_unlock();
925 925
926 /* init dig PHYs */
927 if (rdev->is_atom_bios)
928 radeon_atom_encoder_init(rdev);
926 /* reset hpd state */ 929 /* reset hpd state */
927 radeon_hpd_init(rdev); 930 radeon_hpd_init(rdev);
928 /* blat the mode back in */ 931 /* blat the mode back in */
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 06719340edcb..ae247eec87c0 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -1345,6 +1345,11 @@ int radeon_modeset_init(struct radeon_device *rdev)
1345 if (!ret) { 1345 if (!ret) {
1346 return ret; 1346 return ret;
1347 } 1347 }
1348
1349 /* init dig PHYs */
1350 if (rdev->is_atom_bios)
1351 radeon_atom_encoder_init(rdev);
1352
1348 /* initialize hpd */ 1353 /* initialize hpd */
1349 radeon_hpd_init(rdev); 1354 radeon_hpd_init(rdev);
1350 1355
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 63d2de8771dc..1d330606292f 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -50,9 +50,10 @@
50 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 50 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
51 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 51 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
52 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 52 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
53 * 2.10.0 - fusion 2D tiling
53 */ 54 */
54#define KMS_DRIVER_MAJOR 2 55#define KMS_DRIVER_MAJOR 2
55#define KMS_DRIVER_MINOR 9 56#define KMS_DRIVER_MINOR 10
56#define KMS_DRIVER_PATCHLEVEL 0 57#define KMS_DRIVER_PATCHLEVEL 0
57int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 58int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
58int radeon_driver_unload_kms(struct drm_device *dev); 59int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 99477480b98b..1b557554696e 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -229,6 +229,22 @@ radeon_get_connector_for_encoder(struct drm_encoder *encoder)
229 return NULL; 229 return NULL;
230} 230}
231 231
232static struct drm_connector *
233radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
234{
235 struct drm_device *dev = encoder->dev;
236 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
237 struct drm_connector *connector;
238 struct radeon_connector *radeon_connector;
239
240 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
241 radeon_connector = to_radeon_connector(connector);
242 if (radeon_encoder->devices & radeon_connector->devices)
243 return connector;
244 }
245 return NULL;
246}
247
232struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder) 248struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
233{ 249{
234 struct drm_device *dev = encoder->dev; 250 struct drm_device *dev = encoder->dev;
@@ -250,6 +266,25 @@ struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder
250 return NULL; 266 return NULL;
251} 267}
252 268
269bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder)
270{
271 struct drm_encoder *other_encoder = radeon_atom_get_external_encoder(encoder);
272
273 if (other_encoder) {
274 struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder);
275
276 switch (radeon_encoder->encoder_id) {
277 case ENCODER_OBJECT_ID_TRAVIS:
278 case ENCODER_OBJECT_ID_NUTMEG:
279 return true;
280 default:
281 return false;
282 }
283 }
284
285 return false;
286}
287
253void radeon_panel_mode_fixup(struct drm_encoder *encoder, 288void radeon_panel_mode_fixup(struct drm_encoder *encoder,
254 struct drm_display_mode *adjusted_mode) 289 struct drm_display_mode *adjusted_mode)
255{ 290{
@@ -621,6 +656,10 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
621 struct radeon_connector *radeon_connector; 656 struct radeon_connector *radeon_connector;
622 struct radeon_connector_atom_dig *dig_connector; 657 struct radeon_connector_atom_dig *dig_connector;
623 658
659 /* dp bridges are always DP */
660 if (radeon_encoder_is_dp_bridge(encoder))
661 return ATOM_ENCODER_MODE_DP;
662
624 connector = radeon_get_connector_for_encoder(encoder); 663 connector = radeon_get_connector_for_encoder(encoder);
625 if (!connector) { 664 if (!connector) {
626 switch (radeon_encoder->encoder_id) { 665 switch (radeon_encoder->encoder_id) {
@@ -668,7 +707,6 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
668 return ATOM_ENCODER_MODE_LVDS; 707 return ATOM_ENCODER_MODE_LVDS;
669 break; 708 break;
670 case DRM_MODE_CONNECTOR_DisplayPort: 709 case DRM_MODE_CONNECTOR_DisplayPort:
671 case DRM_MODE_CONNECTOR_eDP:
672 dig_connector = radeon_connector->con_priv; 710 dig_connector = radeon_connector->con_priv;
673 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 711 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
674 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 712 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
@@ -682,6 +720,8 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
682 } else 720 } else
683 return ATOM_ENCODER_MODE_DVI; 721 return ATOM_ENCODER_MODE_DVI;
684 break; 722 break;
723 case DRM_MODE_CONNECTOR_eDP:
724 return ATOM_ENCODER_MODE_DP;
685 case DRM_MODE_CONNECTOR_DVIA: 725 case DRM_MODE_CONNECTOR_DVIA:
686 case DRM_MODE_CONNECTOR_VGA: 726 case DRM_MODE_CONNECTOR_VGA:
687 return ATOM_ENCODER_MODE_CRT; 727 return ATOM_ENCODER_MODE_CRT;
@@ -747,7 +787,7 @@ union dig_encoder_control {
747}; 787};
748 788
749void 789void
750atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) 790atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
751{ 791{
752 struct drm_device *dev = encoder->dev; 792 struct drm_device *dev = encoder->dev;
753 struct radeon_device *rdev = dev->dev_private; 793 struct radeon_device *rdev = dev->dev_private;
@@ -760,6 +800,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
760 int dp_clock = 0; 800 int dp_clock = 0;
761 int dp_lane_count = 0; 801 int dp_lane_count = 0;
762 int hpd_id = RADEON_HPD_NONE; 802 int hpd_id = RADEON_HPD_NONE;
803 int bpc = 8;
763 804
764 if (connector) { 805 if (connector) {
765 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 806 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -769,6 +810,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
769 dp_clock = dig_connector->dp_clock; 810 dp_clock = dig_connector->dp_clock;
770 dp_lane_count = dig_connector->dp_lane_count; 811 dp_lane_count = dig_connector->dp_lane_count;
771 hpd_id = radeon_connector->hpd.hpd; 812 hpd_id = radeon_connector->hpd.hpd;
813 bpc = connector->display_info.bpc;
772 } 814 }
773 815
774 /* no dig encoder assigned */ 816 /* no dig encoder assigned */
@@ -791,7 +833,10 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
791 833
792 args.v1.ucAction = action; 834 args.v1.ucAction = action;
793 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 835 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
794 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 836 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
837 args.v3.ucPanelMode = panel_mode;
838 else
839 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
795 840
796 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) || 841 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
797 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) 842 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
@@ -810,7 +855,27 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
810 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 855 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
811 } 856 }
812 args.v4.acConfig.ucDigSel = dig->dig_encoder; 857 args.v4.acConfig.ucDigSel = dig->dig_encoder;
813 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR; 858 switch (bpc) {
859 case 0:
860 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
861 break;
862 case 6:
863 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
864 break;
865 case 8:
866 default:
867 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
868 break;
869 case 10:
870 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
871 break;
872 case 12:
873 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
874 break;
875 case 16:
876 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
877 break;
878 }
814 if (hpd_id == RADEON_HPD_NONE) 879 if (hpd_id == RADEON_HPD_NONE)
815 args.v4.ucHPD_ID = 0; 880 args.v4.ucHPD_ID = 0;
816 else 881 else
@@ -819,7 +884,27 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
819 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) 884 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
820 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 885 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
821 args.v3.acConfig.ucDigSel = dig->dig_encoder; 886 args.v3.acConfig.ucDigSel = dig->dig_encoder;
822 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; 887 switch (bpc) {
888 case 0:
889 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
890 break;
891 case 6:
892 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
893 break;
894 case 8:
895 default:
896 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
897 break;
898 case 10:
899 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
900 break;
901 case 12:
902 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
903 break;
904 case 16:
905 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
906 break;
907 }
823 } else { 908 } else {
824 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) 909 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
825 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 910 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
@@ -859,7 +944,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
859 struct radeon_device *rdev = dev->dev_private; 944 struct radeon_device *rdev = dev->dev_private;
860 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 945 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
861 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 946 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
862 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 947 struct drm_connector *connector;
863 union dig_transmitter_control args; 948 union dig_transmitter_control args;
864 int index = 0; 949 int index = 0;
865 uint8_t frev, crev; 950 uint8_t frev, crev;
@@ -870,6 +955,11 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
870 int connector_object_id = 0; 955 int connector_object_id = 0;
871 int igp_lane_info = 0; 956 int igp_lane_info = 0;
872 957
958 if (action == ATOM_TRANSMITTER_ACTION_INIT)
959 connector = radeon_get_connector_for_encoder_init(encoder);
960 else
961 connector = radeon_get_connector_for_encoder(encoder);
962
873 if (connector) { 963 if (connector) {
874 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 964 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
875 struct radeon_connector_atom_dig *dig_connector = 965 struct radeon_connector_atom_dig *dig_connector =
@@ -931,10 +1021,10 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
931 else 1021 else
932 args.v3.ucLaneNum = 4; 1022 args.v3.ucLaneNum = 4;
933 1023
934 if (dig->linkb) { 1024 if (dig->linkb)
935 args.v3.acConfig.ucLinkSel = 1; 1025 args.v3.acConfig.ucLinkSel = 1;
1026 if (dig->dig_encoder & 1)
936 args.v3.acConfig.ucEncoderSel = 1; 1027 args.v3.acConfig.ucEncoderSel = 1;
937 }
938 1028
939 /* Select the PLL for the PHY 1029 /* Select the PLL for the PHY
940 * DP PHY should be clocked from external src if there is 1030 * DP PHY should be clocked from external src if there is
@@ -946,11 +1036,16 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
946 } 1036 }
947 1037
948 if (ASIC_IS_DCE5(rdev)) { 1038 if (ASIC_IS_DCE5(rdev)) {
949 if (is_dp && rdev->clock.dp_extclk) 1039 /* On DCE5 DCPLL usually generates the DP ref clock */
950 args.v4.acConfig.ucRefClkSource = 3; /* external src */ 1040 if (is_dp) {
951 else 1041 if (rdev->clock.dp_extclk)
1042 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1043 else
1044 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1045 } else
952 args.v4.acConfig.ucRefClkSource = pll_id; 1046 args.v4.acConfig.ucRefClkSource = pll_id;
953 } else { 1047 } else {
1048 /* On DCE4, if there is an external clock, it generates the DP ref clock */
954 if (is_dp && rdev->clock.dp_extclk) 1049 if (is_dp && rdev->clock.dp_extclk)
955 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1050 args.v3.acConfig.ucRefClkSource = 2; /* external src */
956 else 1051 else
@@ -1047,7 +1142,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
1047 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1142 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1048} 1143}
1049 1144
1050void 1145bool
1051atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1146atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1052{ 1147{
1053 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1148 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -1058,23 +1153,37 @@ atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1058 uint8_t frev, crev; 1153 uint8_t frev, crev;
1059 1154
1060 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1155 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1061 return; 1156 goto done;
1062 1157
1063 if (!ASIC_IS_DCE4(rdev)) 1158 if (!ASIC_IS_DCE4(rdev))
1064 return; 1159 goto done;
1065 1160
1066 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1161 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1067 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1162 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1068 return; 1163 goto done;
1069 1164
1070 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1165 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1071 return; 1166 goto done;
1072 1167
1073 memset(&args, 0, sizeof(args)); 1168 memset(&args, 0, sizeof(args));
1074 1169
1075 args.v1.ucAction = action; 1170 args.v1.ucAction = action;
1076 1171
1077 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1172 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1173
1174 /* wait for the panel to power up */
1175 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1176 int i;
1177
1178 for (i = 0; i < 300; i++) {
1179 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1180 return true;
1181 mdelay(1);
1182 }
1183 return false;
1184 }
1185done:
1186 return true;
1078} 1187}
1079 1188
1080union external_encoder_control { 1189union external_encoder_control {
@@ -1092,13 +1201,19 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
1092 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1201 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1093 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1202 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1094 union external_encoder_control args; 1203 union external_encoder_control args;
1095 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1204 struct drm_connector *connector;
1096 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1205 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1097 u8 frev, crev; 1206 u8 frev, crev;
1098 int dp_clock = 0; 1207 int dp_clock = 0;
1099 int dp_lane_count = 0; 1208 int dp_lane_count = 0;
1100 int connector_object_id = 0; 1209 int connector_object_id = 0;
1101 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1210 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1211 int bpc = 8;
1212
1213 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1214 connector = radeon_get_connector_for_encoder_init(encoder);
1215 else
1216 connector = radeon_get_connector_for_encoder(encoder);
1102 1217
1103 if (connector) { 1218 if (connector) {
1104 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1219 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -1109,6 +1224,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
1109 dp_lane_count = dig_connector->dp_lane_count; 1224 dp_lane_count = dig_connector->dp_lane_count;
1110 connector_object_id = 1225 connector_object_id =
1111 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1226 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1227 bpc = connector->display_info.bpc;
1112 } 1228 }
1113 1229
1114 memset(&args, 0, sizeof(args)); 1230 memset(&args, 0, sizeof(args));
@@ -1166,7 +1282,27 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
1166 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1282 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1167 break; 1283 break;
1168 } 1284 }
1169 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR; 1285 switch (bpc) {
1286 case 0:
1287 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1288 break;
1289 case 6:
1290 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1291 break;
1292 case 8:
1293 default:
1294 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1295 break;
1296 case 10:
1297 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1298 break;
1299 case 12:
1300 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1301 break;
1302 case 16:
1303 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1304 break;
1305 }
1170 break; 1306 break;
1171 default: 1307 default:
1172 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1308 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
@@ -1307,9 +1443,11 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1307 ATOM_TRANSMITTER_ACTION_POWER_ON); 1443 ATOM_TRANSMITTER_ACTION_POWER_ON);
1308 radeon_dig_connector->edp_on = true; 1444 radeon_dig_connector->edp_on = true;
1309 } 1445 }
1310 dp_link_train(encoder, connector);
1311 if (ASIC_IS_DCE4(rdev)) 1446 if (ASIC_IS_DCE4(rdev))
1312 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON); 1447 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1448 radeon_dp_link_train(encoder, connector);
1449 if (ASIC_IS_DCE4(rdev))
1450 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1313 } 1451 }
1314 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1452 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1315 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1453 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
@@ -1322,7 +1460,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1322 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1460 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1323 1461
1324 if (ASIC_IS_DCE4(rdev)) 1462 if (ASIC_IS_DCE4(rdev))
1325 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF); 1463 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1326 if (connector && 1464 if (connector &&
1327 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 1465 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1328 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1466 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -1601,12 +1739,9 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1601 /* DCE4/5 */ 1739 /* DCE4/5 */
1602 if (ASIC_IS_DCE4(rdev)) { 1740 if (ASIC_IS_DCE4(rdev)) {
1603 dig = radeon_encoder->enc_priv; 1741 dig = radeon_encoder->enc_priv;
1604 if (ASIC_IS_DCE41(rdev)) { 1742 if (ASIC_IS_DCE41(rdev))
1605 if (dig->linkb) 1743 return radeon_crtc->crtc_id;
1606 return 1; 1744 else {
1607 else
1608 return 0;
1609 } else {
1610 switch (radeon_encoder->encoder_id) { 1745 switch (radeon_encoder->encoder_id) {
1611 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1746 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1612 if (dig->linkb) 1747 if (dig->linkb)
@@ -1662,6 +1797,34 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1662 return 1; 1797 return 1;
1663} 1798}
1664 1799
1800/* This only needs to be called once at startup */
1801void
1802radeon_atom_encoder_init(struct radeon_device *rdev)
1803{
1804 struct drm_device *dev = rdev->ddev;
1805 struct drm_encoder *encoder;
1806
1807 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1808 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1809 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1810
1811 switch (radeon_encoder->encoder_id) {
1812 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1813 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1814 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1815 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1816 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1817 break;
1818 default:
1819 break;
1820 }
1821
1822 if (ext_encoder && ASIC_IS_DCE41(rdev))
1823 atombios_external_encoder_setup(encoder, ext_encoder,
1824 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1825 }
1826}
1827
1665static void 1828static void
1666radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 1829radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1667 struct drm_display_mode *mode, 1830 struct drm_display_mode *mode,
@@ -1696,19 +1859,17 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1696 /* disable the transmitter */ 1859 /* disable the transmitter */
1697 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1860 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1698 /* setup and enable the encoder */ 1861 /* setup and enable the encoder */
1699 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP); 1862 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1700 1863
1701 /* init and enable the transmitter */ 1864 /* enable the transmitter */
1702 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1703 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1865 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1704 } else { 1866 } else {
1705 /* disable the encoder and transmitter */ 1867 /* disable the encoder and transmitter */
1706 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1868 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1707 atombios_dig_encoder_setup(encoder, ATOM_DISABLE); 1869 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1708 1870
1709 /* setup and enable the encoder and transmitter */ 1871 /* setup and enable the encoder and transmitter */
1710 atombios_dig_encoder_setup(encoder, ATOM_ENABLE); 1872 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1711 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1712 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1873 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1713 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1874 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1714 } 1875 }
@@ -1733,12 +1894,10 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1733 } 1894 }
1734 1895
1735 if (ext_encoder) { 1896 if (ext_encoder) {
1736 if (ASIC_IS_DCE41(rdev)) { 1897 if (ASIC_IS_DCE41(rdev))
1737 atombios_external_encoder_setup(encoder, ext_encoder,
1738 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1739 atombios_external_encoder_setup(encoder, ext_encoder, 1898 atombios_external_encoder_setup(encoder, ext_encoder,
1740 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1899 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1741 } else 1900 else
1742 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1901 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1743 } 1902 }
1744 1903
@@ -1845,8 +2004,9 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1845 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2004 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1846 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2005 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1847 2006
1848 if (radeon_encoder->active_device & 2007 if ((radeon_encoder->active_device &
1849 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) { 2008 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2009 radeon_encoder_is_dp_bridge(encoder)) {
1850 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2010 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1851 if (dig) 2011 if (dig)
1852 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); 2012 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
@@ -1855,11 +2015,17 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1855 radeon_atom_output_lock(encoder, true); 2015 radeon_atom_output_lock(encoder, true);
1856 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2016 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1857 2017
1858 /* select the clock/data port if it uses a router */
1859 if (connector) { 2018 if (connector) {
1860 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2019 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2020
2021 /* select the clock/data port if it uses a router */
1861 if (radeon_connector->router.cd_valid) 2022 if (radeon_connector->router.cd_valid)
1862 radeon_router_select_cd_port(radeon_connector); 2023 radeon_router_select_cd_port(radeon_connector);
2024
2025 /* turn eDP panel on for mode set */
2026 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2027 atombios_set_edp_panel_power(connector,
2028 ATOM_TRANSMITTER_ACTION_POWER_ON);
1863 } 2029 }
1864 2030
1865 /* this is needed for the pll/ss setup to work correctly in some cases */ 2031 /* this is needed for the pll/ss setup to work correctly in some cases */
@@ -1914,7 +2080,7 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1914 else { 2080 else {
1915 /* disable the encoder and transmitter */ 2081 /* disable the encoder and transmitter */
1916 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 2082 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1917 atombios_dig_encoder_setup(encoder, ATOM_DISABLE); 2083 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1918 } 2084 }
1919 break; 2085 break;
1920 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2086 case ENCODER_OBJECT_ID_INTERNAL_DDI:
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 9c57538231d5..977a341266b6 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -464,22 +464,27 @@ radeon_atombios_get_tv_info(struct radeon_device *rdev);
464extern struct drm_connector * 464extern struct drm_connector *
465radeon_get_connector_for_encoder(struct drm_encoder *encoder); 465radeon_get_connector_for_encoder(struct drm_encoder *encoder);
466 466
467extern bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder);
468extern bool radeon_connector_encoder_is_dp_bridge(struct drm_connector *connector);
469extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
470extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
471
467extern void radeon_connector_hotplug(struct drm_connector *connector); 472extern void radeon_connector_hotplug(struct drm_connector *connector);
468extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 473extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
469extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
470 struct drm_display_mode *mode); 474 struct drm_display_mode *mode);
471extern void radeon_dp_set_link_config(struct drm_connector *connector, 475extern void radeon_dp_set_link_config(struct drm_connector *connector,
472 struct drm_display_mode *mode); 476 struct drm_display_mode *mode);
473extern void dp_link_train(struct drm_encoder *encoder, 477extern void radeon_dp_link_train(struct drm_encoder *encoder,
474 struct drm_connector *connector); 478 struct drm_connector *connector);
475extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 479extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
476extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 480extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
477extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action); 481extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
482extern void radeon_atom_encoder_init(struct radeon_device *rdev);
478extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 483extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
479 int action, uint8_t lane_num, 484 int action, uint8_t lane_num,
480 uint8_t lane_set); 485 uint8_t lane_set);
481extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 486extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
482 uint8_t write_byte, uint8_t *read_byte); 487 u8 write_byte, u8 *read_byte);
483 488
484extern void radeon_i2c_init(struct radeon_device *rdev); 489extern void radeon_i2c_init(struct radeon_device *rdev);
485extern void radeon_i2c_fini(struct radeon_device *rdev); 490extern void radeon_i2c_fini(struct radeon_device *rdev);
@@ -545,7 +550,7 @@ struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, i
545extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 550extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
546extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 551extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
547extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 552extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
548extern void atombios_set_edp_panel_power(struct drm_connector *connector, int action); 553extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
549extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 554extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
550 555
551extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 556extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 83a389e44543..91567bbdb027 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -53,6 +53,7 @@
53 53
54#define DP_MAX_LANE_COUNT 0x002 54#define DP_MAX_LANE_COUNT 0x002
55# define DP_MAX_LANE_COUNT_MASK 0x1f 55# define DP_MAX_LANE_COUNT_MASK 0x1f
56# define DP_TPS3_SUPPORTED (1 << 6)
56# define DP_ENHANCED_FRAME_CAP (1 << 7) 57# define DP_ENHANCED_FRAME_CAP (1 << 7)
57 58
58#define DP_MAX_DOWNSPREAD 0x003 59#define DP_MAX_DOWNSPREAD 0x003
@@ -71,10 +72,13 @@
71 72
72#define DP_MAIN_LINK_CHANNEL_CODING 0x006 73#define DP_MAIN_LINK_CHANNEL_CODING 0x006
73 74
75#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
76
74/* link configuration */ 77/* link configuration */
75#define DP_LINK_BW_SET 0x100 78#define DP_LINK_BW_SET 0x100
76# define DP_LINK_BW_1_62 0x06 79# define DP_LINK_BW_1_62 0x06
77# define DP_LINK_BW_2_7 0x0a 80# define DP_LINK_BW_2_7 0x0a
81# define DP_LINK_BW_5_4 0x14
78 82
79#define DP_LANE_COUNT_SET 0x101 83#define DP_LANE_COUNT_SET 0x101
80# define DP_LANE_COUNT_MASK 0x0f 84# define DP_LANE_COUNT_MASK 0x0f
@@ -84,6 +88,7 @@
84# define DP_TRAINING_PATTERN_DISABLE 0 88# define DP_TRAINING_PATTERN_DISABLE 0
85# define DP_TRAINING_PATTERN_1 1 89# define DP_TRAINING_PATTERN_1 1
86# define DP_TRAINING_PATTERN_2 2 90# define DP_TRAINING_PATTERN_2 2
91# define DP_TRAINING_PATTERN_3 3
87# define DP_TRAINING_PATTERN_MASK 0x3 92# define DP_TRAINING_PATTERN_MASK 0x3
88 93
89# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) 94# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-04 22:18:10 -0400