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-rw-r--r--arch/powerpc/platforms/82xx/Kconfig21
-rw-r--r--arch/powerpc/platforms/82xx/Makefile5
-rw-r--r--arch/powerpc/platforms/82xx/m82xx_pci.h19
-rw-r--r--arch/powerpc/platforms/82xx/mpc82xx.c111
-rw-r--r--arch/powerpc/platforms/82xx/mpc82xx_ads.c661
-rw-r--r--arch/powerpc/platforms/82xx/pq2ads.h67
6 files changed, 884 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/82xx/Kconfig b/arch/powerpc/platforms/82xx/Kconfig
new file mode 100644
index 000000000000..47d841ecf2e2
--- /dev/null
+++ b/arch/powerpc/platforms/82xx/Kconfig
@@ -0,0 +1,21 @@
1menu "Platform support"
2 depends on PPC_82xx
3
4choice
5 prompt "Machine Type"
6 default MPC82xx_ADS
7
8config MPC82xx_ADS
9 bool "Freescale MPC82xx ADS"
10 select DEFAULT_UIMAGE
11 select PQ2ADS
12 select 8272
13 select 8260
14 select CPM2
15 select FSL_SOC
16 help
17 This option enables support for the MPC8272 ADS board
18
19endchoice
20
21endmenu
diff --git a/arch/powerpc/platforms/82xx/Makefile b/arch/powerpc/platforms/82xx/Makefile
new file mode 100644
index 000000000000..d9fd4c84d2e0
--- /dev/null
+++ b/arch/powerpc/platforms/82xx/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the PowerPC 82xx linux kernel.
3#
4obj-$(CONFIG_PPC_82xx) += mpc82xx.o
5obj-$(CONFIG_MPC82xx_ADS) += mpc82xx_ads.o
diff --git a/arch/powerpc/platforms/82xx/m82xx_pci.h b/arch/powerpc/platforms/82xx/m82xx_pci.h
new file mode 100644
index 000000000000..9cd8893b5a32
--- /dev/null
+++ b/arch/powerpc/platforms/82xx/m82xx_pci.h
@@ -0,0 +1,19 @@
1#ifndef _PPC_KERNEL_M82XX_PCI_H
2#define _PPC_KERNEL_M82XX_PCI_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#include <asm/m8260_pci.h>
12
13#define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET)
14
15#ifndef _IO_BASE
16#define _IO_BASE isa_io_base
17#endif
18
19#endif /* _PPC_KERNEL_M8260_PCI_H */
diff --git a/arch/powerpc/platforms/82xx/mpc82xx.c b/arch/powerpc/platforms/82xx/mpc82xx.c
new file mode 100644
index 000000000000..89d702de4863
--- /dev/null
+++ b/arch/powerpc/platforms/82xx/mpc82xx.c
@@ -0,0 +1,111 @@
1/*
2 * MPC82xx setup and early boot code plus other random bits.
3 *
4 * Author: Vitaly Bordug <vbordug@ru.mvista.com>
5 *
6 * Copyright (c) 2006 MontaVista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/config.h>
15#include <linux/stddef.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/errno.h>
19#include <linux/reboot.h>
20#include <linux/pci.h>
21#include <linux/interrupt.h>
22#include <linux/kdev_t.h>
23#include <linux/major.h>
24#include <linux/console.h>
25#include <linux/delay.h>
26#include <linux/seq_file.h>
27#include <linux/root_dev.h>
28#include <linux/initrd.h>
29#include <linux/module.h>
30#include <linux/fsl_devices.h>
31#include <linux/fs_uart_pd.h>
32
33#include <asm/system.h>
34#include <asm/pgtable.h>
35#include <asm/page.h>
36#include <asm/atomic.h>
37#include <asm/time.h>
38#include <asm/io.h>
39#include <asm/machdep.h>
40#include <asm/bootinfo.h>
41#include <asm/pci-bridge.h>
42#include <asm/mpc8260.h>
43#include <asm/irq.h>
44#include <mm/mmu_decl.h>
45#include <asm/prom.h>
46#include <asm/cpm2.h>
47#include <asm/udbg.h>
48#include <asm/i8259.h>
49#include <linux/fs_enet_pd.h>
50
51#include <sysdev/fsl_soc.h>
52#include <sysdev/cpm2_pic.h>
53
54#include "pq2ads_pd.h"
55
56static int __init get_freq(char *name, unsigned long *val)
57{
58 struct device_node *cpu;
59 unsigned int *fp;
60 int found = 0;
61
62 /* The cpu node should have timebase and clock frequency properties */
63 cpu = of_find_node_by_type(NULL, "cpu");
64
65 if (cpu) {
66 fp = (unsigned int *)get_property(cpu, name, NULL);
67 if (fp) {
68 found = 1;
69 *val = *fp++;
70 }
71
72 of_node_put(cpu);
73 }
74
75 return found;
76}
77
78void __init m82xx_calibrate_decr(void)
79{
80 ppc_tb_freq = 125000000;
81 if (!get_freq("bus-frequency", &ppc_tb_freq)) {
82 printk(KERN_ERR "WARNING: Estimating decrementer frequency "
83 "(not found)\n");
84 }
85 ppc_tb_freq /= 4;
86 ppc_proc_freq = 1000000000;
87 if (!get_freq("clock-frequency", &ppc_proc_freq))
88 printk(KERN_ERR "WARNING: Estimating processor frequency"
89 "(not found)\n");
90}
91
92void mpc82xx_ads_show_cpuinfo(struct seq_file *m)
93{
94 uint pvid, svid, phid1;
95 uint memsize = total_memory;
96
97 pvid = mfspr(SPRN_PVR);
98 svid = mfspr(SPRN_SVR);
99
100 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
101 seq_printf(m, "Machine\t\t: %s\n", CPUINFO_MACHINE);
102 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
103 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
104
105 /* Display cpu Pll setting */
106 phid1 = mfspr(SPRN_HID1);
107 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
108
109 /* Display the amount of memory */
110 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
111}
diff --git a/arch/powerpc/platforms/82xx/mpc82xx_ads.c b/arch/powerpc/platforms/82xx/mpc82xx_ads.c
new file mode 100644
index 000000000000..4276f087f26e
--- /dev/null
+++ b/arch/powerpc/platforms/82xx/mpc82xx_ads.c
@@ -0,0 +1,661 @@
1/*
2 * MPC82xx_ads setup and early boot code plus other random bits.
3 *
4 * Author: Vitaly Bordug <vbordug@ru.mvista.com>
5 * m82xx_restart fix by Wade Farnsworth <wfarnsworth@mvista.com>
6 *
7 * Copyright (c) 2006 MontaVista Software, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15
16#include <linux/config.h>
17#include <linux/stddef.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/reboot.h>
22#include <linux/pci.h>
23#include <linux/interrupt.h>
24#include <linux/kdev_t.h>
25#include <linux/major.h>
26#include <linux/console.h>
27#include <linux/delay.h>
28#include <linux/seq_file.h>
29#include <linux/root_dev.h>
30#include <linux/initrd.h>
31#include <linux/module.h>
32#include <linux/fsl_devices.h>
33#include <linux/fs_uart_pd.h>
34
35#include <asm/system.h>
36#include <asm/pgtable.h>
37#include <asm/page.h>
38#include <asm/atomic.h>
39#include <asm/time.h>
40#include <asm/io.h>
41#include <asm/machdep.h>
42#include <asm/bootinfo.h>
43#include <asm/pci-bridge.h>
44#include <asm/mpc8260.h>
45#include <asm/irq.h>
46#include <mm/mmu_decl.h>
47#include <asm/prom.h>
48#include <asm/cpm2.h>
49#include <asm/udbg.h>
50#include <asm/i8259.h>
51#include <linux/fs_enet_pd.h>
52
53#include <sysdev/fsl_soc.h>
54#include <../sysdev/cpm2_pic.h>
55
56#include "pq2ads_pd.h"
57
58#ifdef CONFIG_PCI
59static uint pci_clk_frq;
60static struct {
61 unsigned long *pci_int_stat_reg;
62 unsigned long *pci_int_mask_reg;
63} pci_regs;
64
65static unsigned long pci_int_base;
66static struct irq_host *pci_pic_host;
67static struct device_node *pci_pic_node;
68#endif
69
70static void __init mpc82xx_ads_pic_init(void)
71{
72 struct device_node *np = of_find_compatible_node(NULL, "cpm-pic", "CPM2");
73 struct resource r;
74 cpm2_map_t *cpm_reg;
75
76 if (np == NULL) {
77 printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
78 return;
79 }
80 if (of_address_to_resource(np, 0, &r)) {
81 printk(KERN_ERR "PIC init: invalid resource\n");
82 of_node_put(np);
83 return;
84 }
85 cpm2_pic_init(np);
86 of_node_put(np);
87
88 /* Initialize the default interrupt mapping priorities,
89 * in case the boot rom changed something on us.
90 */
91 cpm_reg = (cpm2_map_t *) ioremap(get_immrbase(), sizeof(cpm2_map_t));
92 cpm_reg->im_intctl.ic_siprr = 0x05309770;
93 iounmap(cpm_reg);
94#ifdef CONFIG_PCI
95 /* Initialize stuff for the 82xx CPLD IC and install demux */
96 m82xx_pci_init_irq();
97#endif
98}
99
100static void init_fcc1_ioports(struct fs_platform_info *fpi)
101{
102 struct io_port *io;
103 u32 tempval;
104 cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
105 struct device_node *np;
106 struct resource r;
107 u32 *bcsr;
108
109 np = of_find_node_by_type(NULL, "memory");
110 if (!np) {
111 printk(KERN_INFO "No memory node in device tree\n");
112 return;
113 }
114 if (of_address_to_resource(np, 1, &r)) {
115 printk(KERN_INFO "No memory reg property [1] in devicetree\n");
116 return;
117 }
118 of_node_put(np);
119 bcsr = ioremap(r.start + 4, sizeof(u32));
120 io = &immap->im_ioport;
121
122 /* Enable the PHY */
123 clrbits32(bcsr, BCSR1_FETHIEN);
124 setbits32(bcsr, BCSR1_FETH_RST);
125
126 /* FCC1 pins are on port A/C. */
127 /* Configure port A and C pins for FCC1 Ethernet. */
128
129 tempval = in_be32(&io->iop_pdira);
130 tempval &= ~PA1_DIRA0;
131 tempval |= PA1_DIRA1;
132 out_be32(&io->iop_pdira, tempval);
133
134 tempval = in_be32(&io->iop_psora);
135 tempval &= ~PA1_PSORA0;
136 tempval |= PA1_PSORA1;
137 out_be32(&io->iop_psora, tempval);
138
139 setbits32(&io->iop_ppara, PA1_DIRA0 | PA1_DIRA1);
140
141 /* Alter clocks */
142 tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
143
144 clrbits32(&io->iop_psorc, tempval);
145 clrbits32(&io->iop_pdirc, tempval);
146 setbits32(&io->iop_pparc, tempval);
147
148 cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_rx, CPM_CLK_RX);
149 cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_tx, CPM_CLK_TX);
150
151 iounmap(bcsr);
152 iounmap(immap);
153}
154
155static void init_fcc2_ioports(struct fs_platform_info *fpi)
156{
157 cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
158 struct device_node *np;
159 struct resource r;
160 u32 *bcsr;
161
162 struct io_port *io;
163 u32 tempval;
164
165 np = of_find_node_by_type(NULL, "memory");
166 if (!np) {
167 printk(KERN_INFO "No memory node in device tree\n");
168 return;
169 }
170 if (of_address_to_resource(np, 1, &r)) {
171 printk(KERN_INFO "No memory reg property [1] in devicetree\n");
172 return;
173 }
174 of_node_put(np);
175 io = &immap->im_ioport;
176 bcsr = ioremap(r.start + 12, sizeof(u32));
177
178 /* Enable the PHY */
179 clrbits32(bcsr, BCSR3_FETHIEN2);
180 setbits32(bcsr, BCSR3_FETH2_RST);
181
182 /* FCC2 are port B/C. */
183 /* Configure port A and C pins for FCC2 Ethernet. */
184
185 tempval = in_be32(&io->iop_pdirb);
186 tempval &= ~PB2_DIRB0;
187 tempval |= PB2_DIRB1;
188 out_be32(&io->iop_pdirb, tempval);
189
190 tempval = in_be32(&io->iop_psorb);
191 tempval &= ~PB2_PSORB0;
192 tempval |= PB2_PSORB1;
193 out_be32(&io->iop_psorb, tempval);
194
195 setbits32(&io->iop_pparb, PB2_DIRB0 | PB2_DIRB1);
196
197 tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
198
199 /* Alter clocks */
200 clrbits32(&io->iop_psorc, tempval);
201 clrbits32(&io->iop_pdirc, tempval);
202 setbits32(&io->iop_pparc, tempval);
203
204 cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_rx, CPM_CLK_RX);
205 cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_tx, CPM_CLK_TX);
206
207 iounmap(bcsr);
208 iounmap(immap);
209}
210
211void init_fcc_ioports(struct fs_platform_info *fpi)
212{
213 int fcc_no = fs_get_fcc_index(fpi->fs_no);
214
215 switch (fcc_no) {
216 case 0:
217 init_fcc1_ioports(fpi);
218 break;
219 case 1:
220 init_fcc2_ioports(fpi);
221 break;
222 default:
223 printk(KERN_ERR "init_fcc_ioports: invalid FCC number\n");
224 return;
225 }
226}
227
228static void init_scc1_uart_ioports(struct fs_uart_platform_info *data)
229{
230 cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
231
232 /* SCC1 is only on port D */
233 setbits32(&immap->im_ioport.iop_ppard, 0x00000003);
234 clrbits32(&immap->im_ioport.iop_psord, 0x00000001);
235 setbits32(&immap->im_ioport.iop_psord, 0x00000002);
236 clrbits32(&immap->im_ioport.iop_pdird, 0x00000001);
237 setbits32(&immap->im_ioport.iop_pdird, 0x00000002);
238
239 clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
240 clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
241 setbits32(&immap->im_cpmux.cmx_scr,
242 ((data->clk_tx - 1) << (4 - data->clk_tx)));
243 setbits32(&immap->im_cpmux.cmx_scr,
244 ((data->clk_rx - 1) << (4 - data->clk_rx)));
245
246 iounmap(immap);
247}
248
249static void init_scc4_uart_ioports(struct fs_uart_platform_info *data)
250{
251 cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
252
253 setbits32(&immap->im_ioport.iop_ppard, 0x00000600);
254 clrbits32(&immap->im_ioport.iop_psord, 0x00000600);
255 clrbits32(&immap->im_ioport.iop_pdird, 0x00000200);
256 setbits32(&immap->im_ioport.iop_pdird, 0x00000400);
257
258 clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
259 clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
260 setbits32(&immap->im_cpmux.cmx_scr,
261 ((data->clk_tx - 1) << (4 - data->clk_tx)));
262 setbits32(&immap->im_cpmux.cmx_scr,
263 ((data->clk_rx - 1) << (4 - data->clk_rx)));
264
265 iounmap(immap);
266}
267
268void init_scc_ioports(struct fs_uart_platform_info *data)
269{
270 int scc_no = fs_get_scc_index(data->fs_no);
271
272 switch (scc_no) {
273 case 0:
274 init_scc1_uart_ioports(data);
275 data->brg = data->clk_rx;
276 break;
277 case 3:
278 init_scc4_uart_ioports(data);
279 data->brg = data->clk_rx;
280 break;
281 default:
282 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
283 return;
284 }
285}
286
287void __init m82xx_board_setup(void)
288{
289 cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
290 struct device_node *np;
291 struct resource r;
292 u32 *bcsr;
293
294 np = of_find_node_by_type(NULL, "memory");
295 if (!np) {
296 printk(KERN_INFO "No memory node in device tree\n");
297 return;
298 }
299 if (of_address_to_resource(np, 1, &r)) {
300 printk(KERN_INFO "No memory reg property [1] in devicetree\n");
301 return;
302 }
303 of_node_put(np);
304 bcsr = ioremap(r.start + 4, sizeof(u32));
305 /* Enable the 2nd UART port */
306 clrbits32(bcsr, BCSR1_RS232_EN2);
307
308#ifdef CONFIG_SERIAL_CPM_SCC1
309 clrbits32((u32 *) & immap->im_scc[0].scc_sccm,
310 UART_SCCM_TX | UART_SCCM_RX);
311 clrbits32((u32 *) & immap->im_scc[0].scc_gsmrl,
312 SCC_GSMRL_ENR | SCC_GSMRL_ENT);
313#endif
314
315#ifdef CONFIG_SERIAL_CPM_SCC2
316 clrbits32((u32 *) & immap->im_scc[1].scc_sccm,
317 UART_SCCM_TX | UART_SCCM_RX);
318 clrbits32((u32 *) & immap->im_scc[1].scc_gsmrl,
319 SCC_GSMRL_ENR | SCC_GSMRL_ENT);
320#endif
321
322#ifdef CONFIG_SERIAL_CPM_SCC3
323 clrbits32((u32 *) & immap->im_scc[2].scc_sccm,
324 UART_SCCM_TX | UART_SCCM_RX);
325 clrbits32((u32 *) & immap->im_scc[2].scc_gsmrl,
326 SCC_GSMRL_ENR | SCC_GSMRL_ENT);
327#endif
328
329#ifdef CONFIG_SERIAL_CPM_SCC4
330 clrbits32((u32 *) & immap->im_scc[3].scc_sccm,
331 UART_SCCM_TX | UART_SCCM_RX);
332 clrbits32((u32 *) & immap->im_scc[3].scc_gsmrl,
333 SCC_GSMRL_ENR | SCC_GSMRL_ENT);
334#endif
335
336 iounmap(bcsr);
337 iounmap(immap);
338}
339
340#ifdef CONFIG_PCI
341static void m82xx_pci_mask_irq(unsigned int irq)
342{
343 int bit = irq - pci_int_base;
344
345 *pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
346 return;
347}
348
349static void m82xx_pci_unmask_irq(unsigned int irq)
350{
351 int bit = irq - pci_int_base;
352
353 *pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
354 return;
355}
356
357static void m82xx_pci_mask_and_ack(unsigned int irq)
358{
359 int bit = irq - pci_int_base;
360
361 *pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
362 return;
363}
364
365static void m82xx_pci_end_irq(unsigned int irq)
366{
367 int bit = irq - pci_int_base;
368
369 *pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
370 return;
371}
372
373struct hw_interrupt_type m82xx_pci_ic = {
374 .typename = "MPC82xx ADS PCI",
375 .name = "MPC82xx ADS PCI",
376 .enable = m82xx_pci_unmask_irq,
377 .disable = m82xx_pci_mask_irq,
378 .ack = m82xx_pci_mask_and_ack,
379 .end = m82xx_pci_end_irq,
380 .mask = m82xx_pci_mask_irq,
381 .mask_ack = m82xx_pci_mask_and_ack,
382 .unmask = m82xx_pci_unmask_irq,
383 .eoi = m82xx_pci_end_irq,
384};
385
386static void
387m82xx_pci_irq_demux(unsigned int irq, struct irq_desc *desc,
388 struct pt_regs *regs)
389{
390 unsigned long stat, mask, pend;
391 int bit;
392
393 for (;;) {
394 stat = *pci_regs.pci_int_stat_reg;
395 mask = *pci_regs.pci_int_mask_reg;
396 pend = stat & ~mask & 0xf0000000;
397 if (!pend)
398 break;
399 for (bit = 0; pend != 0; ++bit, pend <<= 1) {
400 if (pend & 0x80000000)
401 __do_IRQ(pci_int_base + bit, regs);
402 }
403 }
404}
405
406static int pci_pic_host_match(struct irq_host *h, struct device_node *node)
407{
408 return node == pci_pic_node;
409}
410
411static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
412 irq_hw_number_t hw)
413{
414 get_irq_desc(virq)->status |= IRQ_LEVEL;
415 set_irq_chip(virq, &m82xx_pci_ic);
416 return 0;
417}
418
419static void pci_host_unmap(struct irq_host *h, unsigned int virq)
420{
421 /* remove chip and handler */
422 set_irq_chip(virq, NULL);
423}
424
425static struct irq_host_ops pci_pic_host_ops = {
426 .match = pci_pic_host_match,
427 .map = pci_pic_host_map,
428 .unmap = pci_host_unmap,
429};
430
431void m82xx_pci_init_irq(void)
432{
433 int irq;
434 cpm2_map_t *immap;
435 struct device_node *np;
436 struct resource r;
437 const u32 *regs;
438 unsigned int size;
439 const u32 *irq_map;
440 int i;
441 unsigned int irq_max, irq_min;
442
443 if ((np = of_find_node_by_type(NULL, "soc")) == NULL) {
444 printk(KERN_INFO "No SOC node in device tree\n");
445 return;
446 }
447 memset(&r, 0, sizeof(r));
448 if (of_address_to_resource(np, 0, &r)) {
449 printk(KERN_INFO "No SOC reg property in device tree\n");
450 return;
451 }
452 immap = ioremap(r.start, sizeof(*immap));
453 of_node_put(np);
454
455 /* install the demultiplexer for the PCI cascade interrupt */
456 np = of_find_node_by_type(NULL, "pci");
457 if (!np) {
458 printk(KERN_INFO "No pci node on device tree\n");
459 iounmap(immap);
460 return;
461 }
462 irq_map = get_property(np, "interrupt-map", &size);
463 if ((!irq_map) || (size <= 7)) {
464 printk(KERN_INFO "No interrupt-map property of pci node\n");
465 iounmap(immap);
466 return;
467 }
468 size /= sizeof(irq_map[0]);
469 for (i = 0, irq_max = 0, irq_min = 512; i < size; i += 7, irq_map += 7) {
470 if (irq_map[5] < irq_min)
471 irq_min = irq_map[5];
472 if (irq_map[5] > irq_max)
473 irq_max = irq_map[5];
474 }
475 pci_int_base = irq_min;
476 irq = irq_of_parse_and_map(np, 0);
477 set_irq_chained_handler(irq, m82xx_pci_irq_demux);
478 of_node_put(np);
479 np = of_find_node_by_type(NULL, "pci-pic");
480 if (!np) {
481 printk(KERN_INFO "No pci pic node on device tree\n");
482 iounmap(immap);
483 return;
484 }
485 pci_pic_node = of_node_get(np);
486 /* PCI interrupt controller registers: status and mask */
487 regs = get_property(np, "reg", &size);
488 if ((!regs) || (size <= 2)) {
489 printk(KERN_INFO "No reg property in pci pic node\n");
490 iounmap(immap);
491 return;
492 }
493 pci_regs.pci_int_stat_reg =
494 ioremap(regs[0], sizeof(*pci_regs.pci_int_stat_reg));
495 pci_regs.pci_int_mask_reg =
496 ioremap(regs[1], sizeof(*pci_regs.pci_int_mask_reg));
497 of_node_put(np);
498 /* configure chip select for PCI interrupt controller */
499 immap->im_memctl.memc_br3 = regs[0] | 0x00001801;
500 immap->im_memctl.memc_or3 = 0xffff8010;
501 /* make PCI IRQ level sensitive */
502 immap->im_intctl.ic_siexr &= ~(1 << (14 - (irq - SIU_INT_IRQ1)));
503
504 /* mask all PCI interrupts */
505 *pci_regs.pci_int_mask_reg |= 0xfff00000;
506 iounmap(immap);
507 pci_pic_host =
508 irq_alloc_host(IRQ_HOST_MAP_LINEAR, irq_max - irq_min + 1,
509 &pci_pic_host_ops, irq_max + 1);
510 return;
511}
512
513static int m82xx_pci_exclude_device(u_char bus, u_char devfn)
514{
515 if (bus == 0 && PCI_SLOT(devfn) == 0)
516 return PCIBIOS_DEVICE_NOT_FOUND;
517 else
518 return PCIBIOS_SUCCESSFUL;
519}
520
521static void
522__init mpc82xx_pcibios_fixup(void)
523{
524 struct pci_dev *dev = NULL;
525
526 for_each_pci_dev(dev) {
527 pci_read_irq_line(dev);
528 }
529}
530
531void __init add_bridge(struct device_node *np)
532{
533 int len;
534 struct pci_controller *hose;
535 struct resource r;
536 const int *bus_range;
537 const void *ptr;
538
539 memset(&r, 0, sizeof(r));
540 if (of_address_to_resource(np, 0, &r)) {
541 printk(KERN_INFO "No PCI reg property in device tree\n");
542 return;
543 }
544 if (!(ptr = get_property(np, "clock-frequency", NULL))) {
545 printk(KERN_INFO "No clock-frequency property in PCI node");
546 return;
547 }
548 pci_clk_frq = *(uint *) ptr;
549 of_node_put(np);
550 bus_range = get_property(np, "bus-range", &len);
551 if (bus_range == NULL || len < 2 * sizeof(int)) {
552 printk(KERN_WARNING "Can't get bus-range for %s, assume"
553 " bus 0\n", np->full_name);
554 }
555
556 pci_assign_all_buses = 1;
557
558 hose = pcibios_alloc_controller();
559
560 if (!hose)
561 return;
562
563 hose->arch_data = np;
564 hose->set_cfg_type = 1;
565
566 hose->first_busno = bus_range ? bus_range[0] : 0;
567 hose->last_busno = bus_range ? bus_range[1] : 0xff;
568 hose->bus_offset = 0;
569
570 hose->set_cfg_type = 1;
571
572 setup_indirect_pci(hose,
573 r.start + offsetof(pci_cpm2_t, pci_cfg_addr),
574 r.start + offsetof(pci_cpm2_t, pci_cfg_data));
575
576 pci_process_bridge_OF_ranges(hose, np, 1);
577}
578#endif
579
580/*
581 * Setup the architecture
582 */
583static void __init mpc82xx_ads_setup_arch(void)
584{
585#ifdef CONFIG_PCI
586 struct device_node *np;
587#endif
588
589 if (ppc_md.progress)
590 ppc_md.progress("mpc82xx_ads_setup_arch()", 0);
591 cpm2_reset();
592
593 /* Map I/O region to a 256MB BAT */
594
595 m82xx_board_setup();
596
597#ifdef CONFIG_PCI
598 ppc_md.pci_exclude_device = m82xx_pci_exclude_device;
599 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
600 add_bridge(np);
601
602 of_node_put(np);
603 ppc_md.pci_map_irq = NULL;
604 ppc_md.pcibios_fixup = mpc82xx_pcibios_fixup;
605 ppc_md.pcibios_fixup_bus = NULL;
606#endif
607
608#ifdef CONFIG_ROOT_NFS
609 ROOT_DEV = Root_NFS;
610#else
611 ROOT_DEV = Root_HDA1;
612#endif
613
614 if (ppc_md.progress)
615 ppc_md.progress("mpc82xx_ads_setup_arch(), finish", 0);
616}
617
618/*
619 * Called very early, device-tree isn't unflattened
620 */
621static int __init mpc82xx_ads_probe(void)
622{
623 /* We always match for now, eventually we should look at
624 * the flat dev tree to ensure this is the board we are
625 * supposed to run on
626 */
627 return 1;
628}
629
630#define RMR_CSRE 0x00000001
631static void m82xx_restart(char *cmd)
632{
633 __volatile__ unsigned char dummy;
634
635 local_irq_disable();
636 ((cpm2_map_t *) cpm2_immr)->im_clkrst.car_rmr |= RMR_CSRE;
637
638 /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
639 mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
640 dummy = ((cpm2_map_t *) cpm2_immr)->im_clkrst.res[0];
641 printk("Restart failed\n");
642 while (1) ;
643}
644
645static void m82xx_halt(void)
646{
647 local_irq_disable();
648 while (1) ;
649}
650
651define_machine(mpc82xx_ads)
652{
653 .name = "MPC82xx ADS",
654 .probe = mpc82xx_ads_probe,
655 .setup_arch = mpc82xx_ads_setup_arch,
656 .init_IRQ = mpc82xx_ads_pic_init,
657 .show_cpuinfo = mpc82xx_ads_show_cpuinfo,
658 .get_irq = cpm2_get_irq,
659 .calibrate_decr = m82xx_calibrate_decr,
660 .restart = m82xx_restart,.halt = m82xx_halt,
661};
diff --git a/arch/powerpc/platforms/82xx/pq2ads.h b/arch/powerpc/platforms/82xx/pq2ads.h
new file mode 100644
index 000000000000..a7348213508f
--- /dev/null
+++ b/arch/powerpc/platforms/82xx/pq2ads.h
@@ -0,0 +1,67 @@
1/*
2 * PQ2/mpc8260 board-specific stuff
3 *
4 * A collection of structures, addresses, and values associated with
5 * the Freescale MPC8260ADS/MPC8266ADS-PCI boards.
6 * Copied from the RPX-Classic and SBS8260 stuff.
7 *
8 * Author: Vitaly Bordug <vbordug@ru.mvista.com>
9 *
10 * Originally written by Dan Malek for Motorola MPC8260 family
11 *
12 * Copyright (c) 2001 Dan Malek <dan@embeddedalley.com>
13 * Copyright (c) 2006 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifdef __KERNEL__
22#ifndef __MACH_ADS8260_DEFS
23#define __MACH_ADS8260_DEFS
24
25#include <linux/config.h>
26
27#include <asm/ppcboot.h>
28
29/* For our show_cpuinfo hooks. */
30#define CPUINFO_VENDOR "Freescale Semiconductor"
31#define CPUINFO_MACHINE "PQ2 ADS PowerPC"
32
33/* Backword-compatibility stuff for the drivers */
34#define CPM_MAP_ADDR ((uint)0xf0000000)
35#define CPM_IRQ_OFFSET 0
36
37/* The ADS8260 has 16, 32-bit wide control/status registers, accessed
38 * only on word boundaries.
39 * Not all are used (yet), or are interesting to us (yet).
40 */
41
42/* Things of interest in the CSR.
43 */
44#define BCSR0_LED0 ((uint)0x02000000) /* 0 == on */
45#define BCSR0_LED1 ((uint)0x01000000) /* 0 == on */
46#define BCSR1_FETHIEN ((uint)0x08000000) /* 0 == enable*/
47#define BCSR1_FETH_RST ((uint)0x04000000) /* 0 == reset */
48#define BCSR1_RS232_EN1 ((uint)0x02000000) /* 0 ==enable */
49#define BCSR1_RS232_EN2 ((uint)0x01000000) /* 0 ==enable */
50#define BCSR3_FETHIEN2 ((uint)0x10000000) /* 0 == enable*/
51#define BCSR3_FETH2_RS ((uint)0x80000000) /* 0 == reset */
52
53/* cpm serial driver works with constants below */
54
55#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
56#define SIU_INT_SMC2i ((uint)0x05+CPM_IRQ_OFFSET)
57#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
58#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
59#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
60#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
61
62void m82xx_pci_init_irq(void);
63void mpc82xx_ads_show_cpuinfo(struct seq_file*);
64void m82xx_calibrate_decr(void);
65
66#endif /* __MACH_ADS8260_DEFS */
67#endif /* __KERNEL__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 23:22:00 -0400