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-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt93
-rw-r--r--drivers/pinctrl/Kconfig10
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/core.c41
-rw-r--r--drivers/pinctrl/pinctrl-coh901.c6
-rw-r--r--drivers/pinctrl/pinctrl-imx.c13
-rw-r--r--drivers/pinctrl/pinctrl-nomadik-db8500.c33
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c37
-rw-r--r--drivers/pinctrl/pinctrl-single.c987
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c5
-rw-r--r--drivers/pinctrl/pinctrl-u300.c6
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.c4
-rw-r--r--include/linux/pinctrl/pinctrl.h5
13 files changed, 1160 insertions, 81 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
new file mode 100644
index 000000000000..5187f0dd8b28
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
@@ -0,0 +1,93 @@
1One-register-per-pin type device tree based pinctrl driver
2
3Required properties:
4- compatible : "pinctrl-single"
5
6- reg : offset and length of the register set for the mux registers
7
8- pinctrl-single,register-width : pinmux register access width in bits
9
10- pinctrl-single,function-mask : mask of allowed pinmux function bits
11 in the pinmux register
12
13Optional properties:
14- pinctrl-single,function-off : function off mode for disabled state if
15 available and same for all registers; if not specified, disabling of
16 pin functions is ignored
17
18This driver assumes that there is only one register for each pin,
19and uses the common pinctrl bindings as specified in the pinctrl-bindings.txt
20document in this directory.
21
22The pin configuration nodes for pinctrl-single are specified as pinctrl
23register offset and value pairs using pinctrl-single,pins. Only the bits
24specified in pinctrl-single,function-mask are updated. For example, setting
25a pin for a device could be done with:
26
27 pinctrl-single,pins = <0xdc 0x118>;
28
29Where 0xdc is the offset from the pinctrl register base address for the
30device pinctrl register, and 0x118 contains the desired value of the
31pinctrl register. See the device example and static board pins example
32below for more information.
33
34Example:
35
36/* SoC common file */
37
38/* first controller instance for pins in core domain */
39pmx_core: pinmux@4a100040 {
40 compatible = "pinctrl-single";
41 reg = <0x4a100040 0x0196>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 pinctrl-single,register-width = <16>;
45 pinctrl-single,function-mask = <0xffff>;
46};
47
48/* second controller instance for pins in wkup domain */
49pmx_wkup: pinmux@4a31e040 {
50 compatible = "pinctrl-single;
51 reg = <0x4a31e040 0x0038>;
52 #address-cells = <1>;
53 #size-cells = <0>;
54 pinctrl-single,register-width = <16>;
55 pinctrl-single,function-mask = <0xffff>;
56};
57
58
59/* board specific .dts file */
60
61&pmx_core {
62
63 /*
64 * map all board specific static pins enabled by the pinctrl driver
65 * itself during the boot (or just set them up in the bootloader)
66 */
67 pinctrl-names = "default";
68 pinctrl-0 = <&board_pins>;
69
70 board_pins: pinmux_board_pins {
71 pinctrl-single,pins = <
72 0x6c 0xf
73 0x6e 0xf
74 0x70 0xf
75 0x72 0xf
76 >;
77 };
78
79 /* map uart2 pins */
80 uart2_pins: pinmux_uart2_pins {
81 pinctrl-single,pins = <
82 0xd8 0x118
83 0xda 0
84 0xdc 0x118
85 0xde 0
86 >;
87 };
88};
89
90&uart2 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&uart2_pins>;
93};
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index c6e6ae0aa3b1..54e3588bef62 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -102,6 +102,14 @@ config PINCTRL_PXA910
102 select PINCTRL_PXA3xx 102 select PINCTRL_PXA3xx
103 select PINCONF 103 select PINCONF
104 104
105config PINCTRL_SINGLE
106 tristate "One-register-per-pin type device tree based pinctrl driver"
107 depends on OF
108 select PINMUX
109 select PINCONF
110 help
111 This selects the device tree based generic pinctrl driver.
112
105config PINCTRL_SIRF 113config PINCTRL_SIRF
106 bool "CSR SiRFprimaII pin controller driver" 114 bool "CSR SiRFprimaII pin controller driver"
107 depends on ARCH_PRIMA2 115 depends on ARCH_PRIMA2
@@ -130,7 +138,7 @@ config PINCTRL_U300
130 138
131config PINCTRL_COH901 139config PINCTRL_COH901
132 bool "ST-Ericsson U300 COH 901 335/571 GPIO" 140 bool "ST-Ericsson U300 COH 901 335/571 GPIO"
133 depends on GPIOLIB && ARCH_U300 && PINMUX_U300 141 depends on GPIOLIB && ARCH_U300 && PINCTRL_U300
134 help 142 help
135 Say yes here to support GPIO interface on ST-Ericsson U300. 143 Say yes here to support GPIO interface on ST-Ericsson U300.
136 The names of the two IP block variants supported are 144 The names of the two IP block variants supported are
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 8c074376cdea..f40b1f81ff2c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
22obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o 22obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
23obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o 23obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
24obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o 24obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
25obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
25obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o 26obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o
26obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o 27obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o
27obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o 28obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 0cc053af70bd..fb7f3bebdc69 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -332,19 +332,16 @@ void pinctrl_add_gpio_range(struct pinctrl_dev *pctldev,
332} 332}
333EXPORT_SYMBOL_GPL(pinctrl_add_gpio_range); 333EXPORT_SYMBOL_GPL(pinctrl_add_gpio_range);
334 334
335/** 335void pinctrl_add_gpio_ranges(struct pinctrl_dev *pctldev,
336 * pinctrl_remove_gpio_range() - remove a range of GPIOs fro a pin controller 336 struct pinctrl_gpio_range *ranges,
337 * @pctldev: pin controller device to remove the range from 337 unsigned nranges)
338 * @range: the GPIO range to remove
339 */
340void pinctrl_remove_gpio_range(struct pinctrl_dev *pctldev,
341 struct pinctrl_gpio_range *range)
342{ 338{
343 mutex_lock(&pinctrl_mutex); 339 int i;
344 list_del(&range->node); 340
345 mutex_unlock(&pinctrl_mutex); 341 for (i = 0; i < nranges; i++)
342 pinctrl_add_gpio_range(pctldev, &ranges[i]);
346} 343}
347EXPORT_SYMBOL_GPL(pinctrl_remove_gpio_range); 344EXPORT_SYMBOL_GPL(pinctrl_add_gpio_ranges);
348 345
349/** 346/**
350 * pinctrl_get_group_selector() - returns the group selector for a group 347 * pinctrl_get_group_selector() - returns the group selector for a group
@@ -1395,9 +1392,9 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
1395 struct pinctrl_dev *pctldev; 1392 struct pinctrl_dev *pctldev;
1396 int ret; 1393 int ret;