diff options
-rw-r--r-- | arch/mips/alchemy/common/usb.c | 3 | ||||
-rw-r--r-- | arch/mips/bcm63xx/cpu.c | 4 | ||||
-rw-r--r-- | arch/mips/include/asm/cpu.h | 38 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-au1x00/au1000.h | 4 | ||||
-rw-r--r-- | arch/mips/kernel/cpu-probe.c | 42 | ||||
-rw-r--r-- | arch/mips/mm/c-r4k.c | 11 | ||||
-rw-r--r-- | arch/mips/mti-malta/malta-time.c | 5 | ||||
-rw-r--r-- | arch/mips/mti-sead3/sead3-time.c | 3 | ||||
-rw-r--r-- | arch/mips/netlogic/xlr/fmn-config.c | 3 | ||||
-rw-r--r-- | arch/mips/sibyte/bcm1480/setup.c | 3 | ||||
-rw-r--r-- | arch/mips/sibyte/sb1250/setup.c | 3 | ||||
-rw-r--r-- | arch/mips/sni/setup.c | 3 |
12 files changed, 77 insertions, 45 deletions
diff --git a/arch/mips/alchemy/common/usb.c b/arch/mips/alchemy/common/usb.c index fcc695626117..2adc7edda49c 100644 --- a/arch/mips/alchemy/common/usb.c +++ b/arch/mips/alchemy/common/usb.c | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <linux/module.h> | 14 | #include <linux/module.h> |
15 | #include <linux/spinlock.h> | 15 | #include <linux/spinlock.h> |
16 | #include <linux/syscore_ops.h> | 16 | #include <linux/syscore_ops.h> |
17 | #include <asm/cpu.h> | ||
17 | #include <asm/mach-au1x00/au1000.h> | 18 | #include <asm/mach-au1x00/au1000.h> |
18 | 19 | ||
19 | /* control register offsets */ | 20 | /* control register offsets */ |
@@ -358,7 +359,7 @@ static inline int au1200_coherency_bug(void) | |||
358 | { | 359 | { |
359 | #if defined(CONFIG_DMA_COHERENT) | 360 | #if defined(CONFIG_DMA_COHERENT) |
360 | /* Au1200 AB USB does not support coherent memory */ | 361 | /* Au1200 AB USB does not support coherent memory */ |
361 | if (!(read_c0_prid() & 0xff)) { | 362 | if (!(read_c0_prid() & PRID_REV_MASK)) { |
362 | printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n"); | 363 | printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n"); |
363 | printk(KERN_INFO "Au1200 USB: update your board or re-configure" | 364 | printk(KERN_INFO "Au1200 USB: update your board or re-configure" |
364 | " the kernel\n"); | 365 | " the kernel\n"); |
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index 7e17374a9ae8..b713cd64b087 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c | |||
@@ -306,14 +306,14 @@ void __init bcm63xx_cpu_init(void) | |||
306 | 306 | ||
307 | switch (c->cputype) { | 307 | switch (c->cputype) { |
308 | case CPU_BMIPS3300: | 308 | case CPU_BMIPS3300: |
309 | if ((read_c0_prid() & 0xff00) != PRID_IMP_BMIPS3300_ALT) | 309 | if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT) |
310 | __cpu_name[cpu] = "Broadcom BCM6338"; | 310 | __cpu_name[cpu] = "Broadcom BCM6338"; |
311 | /* fall-through */ | 311 | /* fall-through */ |
312 | case CPU_BMIPS32: | 312 | case CPU_BMIPS32: |
313 | chipid_reg = BCM_6345_PERF_BASE; | 313 | chipid_reg = BCM_6345_PERF_BASE; |
314 | break; | 314 | break; |
315 | case CPU_BMIPS4350: | 315 | case CPU_BMIPS4350: |
316 | switch ((read_c0_prid() & 0xff)) { | 316 | switch ((read_c0_prid() & PRID_REV_MASK)) { |
317 | case 0x04: | 317 | case 0x04: |
318 | chipid_reg = BCM_3368_PERF_BASE; | 318 | chipid_reg = BCM_3368_PERF_BASE; |
319 | break; | 319 | break; |
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 71b9f1998be7..d2035e16502a 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h | |||
@@ -3,15 +3,14 @@ | |||
3 | * various MIPS cpu types. | 3 | * various MIPS cpu types. |
4 | * | 4 | * |
5 | * Copyright (C) 1996 David S. Miller (davem@davemloft.net) | 5 | * Copyright (C) 1996 David S. Miller (davem@davemloft.net) |
6 | * Copyright (C) 2004 Maciej W. Rozycki | 6 | * Copyright (C) 2004, 2013 Maciej W. Rozycki |
7 | */ | 7 | */ |
8 | #ifndef _ASM_CPU_H | 8 | #ifndef _ASM_CPU_H |
9 | #define _ASM_CPU_H | 9 | #define _ASM_CPU_H |
10 | 10 | ||
11 | /* Assigned Company values for bits 23:16 of the PRId Register | 11 | /* |
12 | (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from | 12 | As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0 |
13 | MTI, the PRId register is defined in this (backwards compatible) | 13 | register 15, select 0) is defined in this (backwards compatible) way: |
14 | way: | ||
15 | 14 | ||
16 | +----------------+----------------+----------------+----------------+ | 15 | +----------------+----------------+----------------+----------------+ |
17 | | Company Options| Company ID | Processor ID | Revision | | 16 | | Company Options| Company ID | Processor ID | Revision | |
@@ -23,6 +22,14 @@ | |||
23 | spec. | 22 | spec. |
24 | */ | 23 | */ |
25 | 24 | ||
25 | #define PRID_OPT_MASK 0xff000000 | ||
26 | |||
27 | /* | ||
28 | * Assigned Company values for bits 23:16 of the PRId register. | ||
29 | */ | ||
30 | |||
31 | #define PRID_COMP_MASK 0xff0000 | ||
32 | |||
26 | #define PRID_COMP_LEGACY 0x000000 | 33 | #define PRID_COMP_LEGACY 0x000000 |
27 | #define PRID_COMP_MIPS 0x010000 | 34 | #define PRID_COMP_MIPS 0x010000 |
28 | #define PRID_COMP_BROADCOM 0x020000 | 35 | #define PRID_COMP_BROADCOM 0x020000 |
@@ -38,10 +45,17 @@ | |||
38 | #define PRID_COMP_INGENIC 0xd00000 | 45 | #define PRID_COMP_INGENIC 0xd00000 |
39 | 46 | ||
40 | /* | 47 | /* |
41 | * Assigned values for the product ID register. In order to detect a | 48 | * Assigned Processor ID (implementation) values for bits 15:8 of the PRId |
42 | * certain CPU type exactly eventually additional registers may need to | 49 | * register. In order to detect a certain CPU type exactly eventually |
43 | * be examined. These are valid when 23:16 == PRID_COMP_LEGACY | 50 | * additional registers may need to be examined. |
44 | */ | 51 | */ |
52 | |||
53 | #define PRID_IMP_MASK 0xff00 | ||
54 | |||
55 | /* | ||
56 | * These are valid when 23:16 == PRID_COMP_LEGACY | ||
57 | */ | ||
58 | |||
45 | #define PRID_IMP_R2000 0x0100 | 59 | #define PRID_IMP_R2000 0x0100 |
46 | #define PRID_IMP_AU1_REV1 0x0100 | 60 | #define PRID_IMP_AU1_REV1 0x0100 |
47 | #define PRID_IMP_AU1_REV2 0x0200 | 61 | #define PRID_IMP_AU1_REV2 0x0200 |
@@ -182,11 +196,15 @@ | |||
182 | #define PRID_IMP_NETLOGIC_XLP2XX 0x1200 | 196 | #define PRID_IMP_NETLOGIC_XLP2XX 0x1200 |
183 | 197 | ||
184 | /* | 198 | /* |
185 | * Definitions for 7:0 on legacy processors | 199 | * Particular Revision values for bits 7:0 of the PRId register. |
186 | */ | 200 | */ |
187 | 201 | ||
188 | #define PRID_REV_MASK 0x00ff | 202 | #define PRID_REV_MASK 0x00ff |
189 | 203 | ||
204 | /* | ||
205 | * Definitions for 7:0 on legacy processors | ||
206 | */ | ||
207 | |||
190 | #define PRID_REV_TX4927 0x0022 | 208 | #define PRID_REV_TX4927 0x0022 |
191 | #define PRID_REV_TX4937 0x0030 | 209 | #define PRID_REV_TX4937 0x0030 |
192 | #define PRID_REV_R4400 0x0040 | 210 | #define PRID_REV_R4400 0x0040 |
@@ -227,6 +245,8 @@ | |||
227 | * 31 16 15 8 7 0 | 245 | * 31 16 15 8 7 0 |
228 | */ | 246 | */ |
229 | 247 | ||
248 | #define FPIR_IMP_MASK 0xff00 | ||
249 | |||
230 | #define FPIR_IMP_NONE 0x0000 | 250 | #define FPIR_IMP_NONE 0x0000 |
231 | 251 | ||
232 | enum cpu_type_enum { | 252 | enum cpu_type_enum { |
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 3e11a468cdf8..54f9e84db8ac 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h | |||
@@ -43,6 +43,8 @@ | |||
43 | #include <linux/io.h> | 43 | #include <linux/io.h> |
44 | #include <linux/irq.h> | 44 | #include <linux/irq.h> |
45 | 45 | ||
46 | #include <asm/cpu.h> | ||
47 | |||
46 | /* cpu pipeline flush */ | 48 | /* cpu pipeline flush */ |
47 | void static inline au_sync(void) | 49 | void static inline au_sync(void) |
48 | { | 50 | { |
@@ -140,7 +142,7 @@ static inline int au1xxx_cpu_needs_config_od(void) | |||
140 | 142 | ||
141 | static inline int alchemy_get_cputype(void) | 143 | static inline int alchemy_get_cputype(void) |
142 | { | 144 | { |
143 | switch (read_c0_prid() & 0xffff0000) { | 145 | switch (read_c0_prid() & (PRID_OPT_MASK | PRID_COMP_MASK)) { |
144 | case 0x00030000: | 146 | case 0x00030000: |
145 | return ALCHEMY_CPU_AU1000; | 147 | return ALCHEMY_CPU_AU1000; |
146 | break; | 148 | break; |
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 9ef2b049d3c0..9be68091bdf2 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c | |||
@@ -123,7 +123,7 @@ static inline unsigned long cpu_get_fpu_id(void) | |||
123 | */ | 123 | */ |
124 | static inline int __cpu_has_fpu(void) | 124 | static inline int __cpu_has_fpu(void) |
125 | { | 125 | { |
126 | return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); | 126 | return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE); |
127 | } | 127 | } |
128 | 128 | ||
129 | static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) | 129 | static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) |
@@ -323,7 +323,7 @@ static void decode_configs(struct cpuinfo_mips *c) | |||
323 | 323 | ||
324 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) | 324 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) |
325 | { | 325 | { |
326 | switch (c->processor_id & 0xff00) { | 326 | switch (c->processor_id & PRID_IMP_MASK) { |
327 | case PRID_IMP_R2000: | 327 | case PRID_IMP_R2000: |
328 | c->cputype = CPU_R2000; | 328 | c->cputype = CPU_R2000; |
329 | __cpu_name[cpu] = "R2000"; | 329 | __cpu_name[cpu] = "R2000"; |
@@ -334,7 +334,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) | |||
334 | c->tlbsize = 64; | 334 | c->tlbsize = 64; |
335 | break; | 335 | break; |
336 | case PRID_IMP_R3000: | 336 | case PRID_IMP_R3000: |
337 | if ((c->processor_id & 0xff) == PRID_REV_R3000A) { | 337 | if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { |
338 | if (cpu_has_confreg()) { | 338 | if (cpu_has_confreg()) { |
339 | c->cputype = CPU_R3081E; | 339 | c->cputype = CPU_R3081E; |
340 | __cpu_name[cpu] = "R3081"; | 340 | __cpu_name[cpu] = "R3081"; |
@@ -354,7 +354,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) | |||
354 | break; | 354 | break; |
355 | case PRID_IMP_R4000: | 355 | case PRID_IMP_R4000: |
356 | if (read_c0_config() & CONF_SC) { | 356 | if (read_c0_config() & CONF_SC) { |
357 | if ((c->processor_id & 0xff) >= PRID_REV_R4400) { | 357 | if ((c->processor_id & PRID_REV_MASK) >= |
358 | PRID_REV_R4400) { | ||
358 | c->cputype = CPU_R4400PC; | 359 | c->cputype = CPU_R4400PC; |
359 | __cpu_name[cpu] = "R4400PC"; | 360 | __cpu_name[cpu] = "R4400PC"; |
360 | } else { | 361 | } else { |
@@ -362,7 +363,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) | |||
362 | __cpu_name[cpu] = "R4000PC"; | 363 | __cpu_name[cpu] = "R4000PC"; |
363 | } | 364 | } |
364 | } else { | 365 | } else { |
365 | if ((c->processor_id & 0xff) >= PRID_REV_R4400) { | 366 | if ((c->processor_id & PRID_REV_MASK) >= |
367 | PRID_REV_R4400) { | ||
366 | c->cputype = CPU_R4400SC; | 368 | c->cputype = CPU_R4400SC; |
367 | __cpu_name[cpu] = "R4400SC"; | 369 | __cpu_name[cpu] = "R4400SC"; |
368 | } else { | 370 | } else { |
@@ -455,7 +457,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) | |||
455 | __cpu_name[cpu] = "TX3927"; | 457 | __cpu_name[cpu] = "TX3927"; |
456 | c->tlbsize = 64; | 458 | c->tlbsize = 64; |
457 | } else { | 459 | } else { |
458 | switch (c->processor_id & 0xff) { | 460 | switch (c->processor_id & PRID_REV_MASK) { |
459 | case PRID_REV_TX3912: | 461 | case PRID_REV_TX3912: |
460 | c->cputype = CPU_TX3912; | 462 | c->cputype = CPU_TX3912; |
461 | __cpu_name[cpu] = "TX3912"; | 463 | __cpu_name[cpu] = "TX3912"; |
@@ -641,7 +643,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) | |||
641 | static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) | 643 | static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) |
642 | { | 644 | { |
643 | decode_configs(c); | 645 | decode_configs(c); |
644 | switch (c->processor_id & 0xff00) { | 646 | switch (c->processor_id & PRID_IMP_MASK) { |
645 | case PRID_IMP_4KC: | 647 | case PRID_IMP_4KC: |
646 | c->cputype = CPU_4KC; | 648 | c->cputype = CPU_4KC; |
647 | __cpu_name[cpu] = "MIPS 4Kc"; | 649 | __cpu_name[cpu] = "MIPS 4Kc"; |
@@ -712,7 +714,7 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) | |||
712 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) | 714 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) |
713 | { | 715 | { |
714 | decode_configs(c); | 716 | decode_configs(c); |
715 | switch (c->processor_id & 0xff00) { | 717 | switch (c->processor_id & PRID_IMP_MASK) { |
716 | case PRID_IMP_AU1_REV1: | 718 | case PRID_IMP_AU1_REV1: |
717 | case PRID_IMP_AU1_REV2: | 719 | case PRID_IMP_AU1_REV2: |
718 | c->cputype = CPU_ALCHEMY; | 720 | c->cputype = CPU_ALCHEMY; |
@@ -731,7 +733,7 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) | |||
731 | break; | 733 | break; |
732 | case 4: | 734 | case 4: |
733 | __cpu_name[cpu] = "Au1200"; | 735 | __cpu_name[cpu] = "Au1200"; |
734 | if ((c->processor_id & 0xff) == 2) | 736 | if ((c->processor_id & PRID_REV_MASK) == 2) |
735 | __cpu_name[cpu] = "Au1250"; | 737 | __cpu_name[cpu] = "Au1250"; |
736 | break; | 738 | break; |
737 | case 5: | 739 | case 5: |
@@ -749,12 +751,12 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) | |||
749 | { | 751 | { |
750 | decode_configs(c); | 752 | decode_configs(c); |
751 | 753 | ||
752 | switch (c->processor_id & 0xff00) { | 754 | switch (c->processor_id & PRID_IMP_MASK) { |
753 | case PRID_IMP_SB1: | 755 | case PRID_IMP_SB1: |
754 | c->cputype = CPU_SB1; | 756 | c->cputype = CPU_SB1; |
755 | __cpu_name[cpu] = "SiByte SB1"; | 757 | __cpu_name[cpu] = "SiByte SB1"; |
756 | /* FPU in pass1 is known to have issues. */ | 758 | /* FPU in pass1 is known to have issues. */ |
757 | if ((c->processor_id & 0xff) < 0x02) | 759 | if ((c->processor_id & PRID_REV_MASK) < 0x02) |
758 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); | 760 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); |
759 | break; | 761 | break; |
760 | case PRID_IMP_SB1A: | 762 | case PRID_IMP_SB1A: |
@@ -767,7 +769,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) | |||
767 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) | 769 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) |
768 | { | 770 | { |
769 | decode_configs(c); | 771 | decode_configs(c); |
770 | switch (c->processor_id & 0xff00) { | 772 | switch (c->processor_id & PRID_IMP_MASK) { |
771 | case PRID_IMP_SR71000: | 773 | case PRID_IMP_SR71000: |
772 | c->cputype = CPU_SR71000; | 774 | c->cputype = CPU_SR71000; |
773 | __cpu_name[cpu] = "Sandcraft SR71000"; | 775 | __cpu_name[cpu] = "Sandcraft SR71000"; |
@@ -780,7 +782,7 @@ static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) | |||
780 | static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) | 782 | static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) |
781 | { | 783 | { |
782 | decode_configs(c); | 784 | decode_configs(c); |
783 | switch (c->processor_id & 0xff00) { | 785 | switch (c->processor_id & PRID_IMP_MASK) { |
784 | case PRID_IMP_PR4450: | 786 | case PRID_IMP_PR4450: |
785 | c->cputype = CPU_PR4450; | 787 | c->cputype = CPU_PR4450; |
786 | __cpu_name[cpu] = "Philips PR4450"; | 788 | __cpu_name[cpu] = "Philips PR4450"; |
@@ -792,7 +794,7 @@ static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) | |||
792 | static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) | 794 | static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) |
793 | { | 795 | { |
794 | decode_configs(c); | 796 | decode_configs(c); |
795 | switch (c->processor_id & 0xff00) { | 797 | switch (c->processor_id & PRID_IMP_MASK) { |
796 | case PRID_IMP_BMIPS32_REV4: | 798 | case PRID_IMP_BMIPS32_REV4: |
797 | case PRID_IMP_BMIPS32_REV8: | 799 | case PRID_IMP_BMIPS32_REV8: |
798 | c->cputype = CPU_BMIPS32; | 800 | c->cputype = CPU_BMIPS32; |
@@ -807,7 +809,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) | |||
807 | set_elf_platform(cpu, "bmips3300"); | 809 | set_elf_platform(cpu, "bmips3300"); |
808 | break; | 810 | break; |
809 | case PRID_IMP_BMIPS43XX: { | 811 | case PRID_IMP_BMIPS43XX: { |
810 | int rev = c->processor_id & 0xff; | 812 | int rev = c->processor_id & PRID_REV_MASK; |
811 | 813 | ||
812 | if (rev >= PRID_REV_BMIPS4380_LO && | 814 | if (rev >= PRID_REV_BMIPS4380_LO && |
813 | rev <= PRID_REV_BMIPS4380_HI) { | 815 | rev <= PRID_REV_BMIPS4380_HI) { |
@@ -833,7 +835,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) | |||
833 | static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) | 835 | static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) |
834 | { | 836 | { |
835 | decode_configs(c); | 837 | decode_configs(c); |
836 | switch (c->processor_id & 0xff00) { | 838 | switch (c->processor_id & PRID_IMP_MASK) { |
837 | case PRID_IMP_CAVIUM_CN38XX: | 839 | case PRID_IMP_CAVIUM_CN38XX: |
838 | case PRID_IMP_CAVIUM_CN31XX: | 840 | case PRID_IMP_CAVIUM_CN31XX: |
839 | case PRID_IMP_CAVIUM_CN30XX: | 841 | case PRID_IMP_CAVIUM_CN30XX: |
@@ -876,7 +878,7 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) | |||
876 | decode_configs(c); | 878 | decode_configs(c); |
877 | /* JZRISC does not implement the CP0 counter. */ | 879 | /* JZRISC does not implement the CP0 counter. */ |
878 | c->options &= ~MIPS_CPU_COUNTER; | 880 | c->options &= ~MIPS_CPU_COUNTER; |
879 | switch (c->processor_id & 0xff00) { | 881 | switch (c->processor_id & PRID_IMP_MASK) { |
880 | case PRID_IMP_JZRISC: | 882 | case PRID_IMP_JZRISC: |
881 | c->cputype = CPU_JZRISC; | 883 | c->cputype = CPU_JZRISC; |
882 | __cpu_name[cpu] = "Ingenic JZRISC"; | 884 | __cpu_name[cpu] = "Ingenic JZRISC"; |
@@ -891,7 +893,7 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) | |||
891 | { | 893 | { |
892 | decode_configs(c); | 894 | decode_configs(c); |
893 | 895 | ||
894 | if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) { | 896 | if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { |
895 | c->cputype = CPU_ALCHEMY; | 897 | c->cputype = CPU_ALCHEMY; |
896 | __cpu_name[cpu] = "Au1300"; | 898 | __cpu_name[cpu] = "Au1300"; |
897 | /* following stuff is not for Alchemy */ | 899 | /* following stuff is not for Alchemy */ |
@@ -906,7 +908,7 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) | |||
906 | MIPS_CPU_EJTAG | | 908 | MIPS_CPU_EJTAG | |
907 | MIPS_CPU_LLSC); | 909 | MIPS_CPU_LLSC); |
908 | 910 | ||
909 | switch (c->processor_id & 0xff00) { | 911 | switch (c->processor_id & PRID_IMP_MASK) { |
910 | case PRID_IMP_NETLOGIC_XLP2XX: | 912 | case PRID_IMP_NETLOGIC_XLP2XX: |
911 | c->cputype = CPU_XLP; | 913 | c->cputype = CPU_XLP; |
912 | __cpu_name[cpu] = "Broadcom XLPII"; | 914 | __cpu_name[cpu] = "Broadcom XLPII"; |
@@ -985,7 +987,7 @@ void cpu_probe(void) | |||
985 | c->cputype = CPU_UNKNOWN; | 987 | c->cputype = CPU_UNKNOWN; |
986 | 988 | ||
987 | c->processor_id = read_c0_prid(); | 989 | c->processor_id = read_c0_prid(); |
988 | switch (c->processor_id & 0xff0000) { | 990 | switch (c->processor_id & PRID_COMP_MASK) { |
989 | case PRID_COMP_LEGACY: | 991 | case PRID_COMP_LEGACY: |
990 | cpu_probe_legacy(c, cpu); | 992 | cpu_probe_legacy(c, cpu); |
991 | break; | 993 | break; |
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 73ca8c52e83f..ae500ca76580 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c | |||
@@ -792,12 +792,12 @@ static inline void alias_74k_erratum(struct cpuinfo_mips *c) | |||
792 | * aliases. In this case it is better to treat the cache as always | 792 | * aliases. In this case it is better to treat the cache as always |
793 | * having aliases. | 793 | * having aliases. |
794 | */ | 794 | */ |
795 | if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0)) | 795 | if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_ENCODE_332(2, 4, 0)) |
796 | c->dcache.flags |= MIPS_CACHE_VTAG; | 796 | c->dcache.flags |= MIPS_CACHE_VTAG; |
797 | if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0)) | 797 | if ((c->processor_id & PRID_REV_MASK) == PRID_REV_ENCODE_332(2, 4, 0)) |
798 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); | 798 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); |
799 | if (((c->processor_id & 0xff00) == PRID_IMP_1074K) && | 799 | if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_1074K && |
800 | ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) { | 800 | (c->processor_id & PRID_REV_MASK) <= PRID_REV_ENCODE_332(1, 1, 0)) { |
801 | c->dcache.flags |= MIPS_CACHE_VTAG; | 801 | c->dcache.flags |= MIPS_CACHE_VTAG; |
802 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); | 802 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); |
803 | } | 803 | } |
@@ -1031,7 +1031,8 @@ static void probe_pcache(void) | |||
1031 | * presumably no vendor is shipping his hardware in the "bad" | 1031 | * presumably no vendor is shipping his hardware in the "bad" |
1032 | * configuration. | 1032 | * configuration. |
1033 | */ | 1033 | */ |
1034 | if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 && | 1034 | if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 && |
1035 | (prid & PRID_REV_MASK) < PRID_REV_R4400 && | ||
1035 | !(config & CONF_SC) && c->icache.linesz != 16 && | 1036 | !(config & CONF_SC) && c->icache.linesz != 16 && |
1036 | PAGE_SIZE <= 0x8000) | 1037 | PAGE_SIZE <= 0x8000) |
1037 | panic("Improper R4000SC processor configuration detected"); | 1038 | panic("Improper R4000SC processor configuration detected"); |
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c index 53aad4a35375..a18af5fce67e 100644 --- a/arch/mips/mti-malta/malta-time.c +++ b/arch/mips/mti-malta/malta-time.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #include <linux/timex.h> | 27 | #include <linux/timex.h> |
28 | #include <linux/mc146818rtc.h> | 28 | #include <linux/mc146818rtc.h> |
29 | 29 | ||
30 | #include <asm/cpu.h> | ||
30 | #include <asm/mipsregs.h> | 31 | #include <asm/mipsregs.h> |
31 | #include <asm/mipsmtregs.h> | 32 | #include <asm/mipsmtregs.h> |
32 | #include <asm/hardirq.h> | 33 | #include <asm/hardirq.h> |
@@ -76,7 +77,7 @@ static void __init estimate_frequencies(void) | |||
76 | #endif | 77 | #endif |
77 | 78 | ||
78 | #if defined (CONFIG_KVM_GUEST) && defined (CONFIG_KVM_HOST_FREQ) | 79 | #if defined (CONFIG_KVM_GUEST) && defined (CONFIG_KVM_HOST_FREQ) |
79 | unsigned int prid = read_c0_prid() & 0xffff00; | 80 | unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); |
80 | 81 | ||
81 | /* | 82 | /* |
82 | * XXXKYMA: hardwire the CPU frequency to Host Freq/4 | 83 | * XXXKYMA: hardwire the CPU frequency to Host Freq/4 |
@@ -169,7 +170,7 @@ unsigned int get_c0_compare_int(void) | |||
169 | 170 | ||
170 | void __init plat_time_init(void) | 171 | void __init plat_time_init(void) |
171 | { | 172 | { |
172 | unsigned int prid = read_c0_prid() & 0xffff00; | 173 | unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); |
173 | unsigned int freq; | 174 | unsigned int freq; |
174 | 175 | ||
175 | estimate_frequencies(); | 176 | estimate_frequencies(); |
diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c index a43ea3cc0a3b..552d26c34386 100644 --- a/arch/mips/mti-sead3/sead3-time.c +++ b/arch/mips/mti-sead3/sead3-time.c | |||
@@ -7,6 +7,7 @@ | |||
7 | */ | 7 | */ |
8 | #include <linux/init.h> | 8 | #include <linux/init.h> |
9 | 9 | ||
10 | #include <asm/cpu.h> | ||
10 | #include <asm/setup.h> | 11 | #include <asm/setup.h> |
11 | #include <asm/time.h> | 12 | #include <asm/time.h> |
12 | #include <asm/irq.h> | 13 | #include <asm/irq.h> |
@@ -34,7 +35,7 @@ static void __iomem *status_reg = (void __iomem *)0xbf000410; | |||
34 | */ | 35 | */ |
35 | static unsigned int __init estimate_cpu_frequency(void) | 36 | static unsigned int __init estimate_cpu_frequency(void) |
36 | { | 37 | { |
37 | unsigned int prid = read_c0_prid() & 0xffff00; | 38 | unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); |
38 | unsigned int tick = 0; | 39 | unsigned int tick = 0; |
39 | unsigned int freq; | 40 | unsigned int freq; |
40 | unsigned int orig; | 41 | unsigned int orig; |
diff --git a/arch/mips/netlogic/xlr/fmn-config.c b/arch/mips/netlogic/xlr/fmn-config.c index ed3bf0e3f309..c7622c6e5f67 100644 --- a/arch/mips/netlogic/xlr/fmn-config.c +++ b/arch/mips/netlogic/xlr/fmn-config.c | |||
@@ -36,6 +36,7 @@ | |||
36 | #include <linux/irq.h> | 36 | #include <linux/irq.h> |
37 | #include <linux/interrupt.h> | 37 | #include <linux/interrupt.h> |
38 | 38 | ||
39 | #include <asm/cpu.h> | ||
39 | #include <asm/mipsregs.h> | 40 | #include <asm/mipsregs.h> |
40 | #include <asm/netlogic/xlr/fmn.h> | 41 | #include <asm/netlogic/xlr/fmn.h> |
41 | #include <asm/netlogic/xlr/xlr.h> | 42 | #include <asm/netlogic/xlr/xlr.h> |
@@ -187,7 +188,7 @@ void xlr_board_info_setup(void) | |||
187 | int processor_id, num_core; | 188 | int processor_id, num_core; |
188 | 189 | ||
189 | num_core = hweight32(nlm_current_node()->coremask); | 190 | num_core = hweight32(nlm_current_node()->coremask); |
190 | processor_id = read_c0_prid() & 0xff00; | 191 | processor_id = read_c0_prid() & PRID_IMP_MASK; |
191 | 192 | ||
192 | setup_cpu_fmninfo(cpu, num_core); | 193 | setup_cpu_fmninfo(cpu, num_core); |
193 | switch (processor_id) { | 194 | switch (processor_id) { |
diff --git a/arch/mips/sibyte/bcm1480/setup.c b/arch/mips/sibyte/bcm1480/setup.c index 05ed92c92b69..8e2e04f77870 100644 --- a/arch/mips/sibyte/bcm1480/setup.c +++ b/arch/mips/sibyte/bcm1480/setup.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <linux/string.h> | 22 | #include <linux/string.h> |
23 | 23 | ||
24 | #include <asm/bootinfo.h> | 24 | #include <asm/bootinfo.h> |
25 | #include <asm/cpu.h> | ||
25 | #include <asm/mipsregs.h> | 26 | #include <asm/mipsregs.h> |
26 | #include <asm/io.h> | 27 | #include <asm/io.h> |
27 | #include <asm/sibyte/sb1250.h> | 28 | #include <asm/sibyte/sb1250.h> |
@@ -119,7 +120,7 @@ void __init bcm1480_setup(void) | |||
119 | uint64_t sys_rev; | 120 | uint64_t sys_rev; |
120 | int plldiv; | 121 | int plldiv; |
121 | 122 | ||
122 | sb1_pass = read_c0_prid() & 0xff; | 123 | sb1_pass = read_c0_prid() & PRID_REV_MASK; |
123 | sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); | 124 | sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); |
124 | soc_type = SYS_SOC_TYPE(sys_rev); | 125 | soc_type = SYS_SOC_TYPE(sys_rev); |
125 | part_type = G_SYS_PART(sys_rev); | 126 | part_type = G_SYS_PART(sys_rev); |
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c index a14bd4cb0bc0..3c02b2a77ae9 100644 --- a/arch/mips/sibyte/sb1250/setup.c +++ b/arch/mips/sibyte/sb1250/setup.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <linux/string.h> | 22 | #include <linux/string.h> |
23 | 23 | ||
24 | #include <asm/bootinfo.h> | 24 | #include <asm/bootinfo.h> |
25 | #include <asm/cpu.h> | ||
25 | #include <asm/mipsregs.h> | 26 | #include <asm/mipsregs.h> |
26 | #include <asm/io.h> | 27 | #include <asm/io.h> |
27 | #include <asm/sibyte/sb1250.h> | 28 | #include <asm/sibyte/sb1250.h> |
@@ -182,7 +183,7 @@ void __init sb1250_setup(void) | |||
182 | int plldiv; | 183 | int plldiv; |
183 | int bad_config = 0; | 184 | int bad_config = 0; |
184 | 185 | ||
185 | sb1_pass = read_c0_prid() & 0xff; | 186 | sb1_pass = read_c0_prid() & PRID_REV_MASK; |
186 | sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); | 187 | sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); |
187 | soc_type = SYS_SOC_TYPE(sys_rev); | 188 | soc_type = SYS_SOC_TYPE(sys_rev); |
188 | soc_pass = G_SYS_REVISION(sys_rev); | 189 | soc_pass = G_SYS_REVISION(sys_rev); |
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c index 5b09b3544edd..efad85c8c823 100644 --- a/arch/mips/sni/setup.c +++ b/arch/mips/sni/setup.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #endif | 25 | #endif |
26 | 26 | ||
27 | #include <asm/bootinfo.h> | 27 | #include <asm/bootinfo.h> |
28 | #include <asm/cpu.h> | ||
28 | #include <asm/io.h> | 29 | #include <asm/io.h> |
29 | #include <asm/reboot.h> | 30 | #include <asm/reboot.h> |
30 | #include <asm/sni.h> | 31 | #include <asm/sni.h> |
@@ -173,7 +174,7 @@ void __init plat_mem_setup(void) | |||
173 | system_type = "RM300-Cxx"; | 174 | system_type = "RM300-Cxx"; |
174 | break; | 175 | break; |
175 | case SNI_BRD_PCI_DESKTOP: | 176 | case SNI_BRD_PCI_DESKTOP: |
176 | switch (read_c0_prid() & 0xff00) { | 177 | switch (read_c0_prid() & PRID_IMP_MASK) { |
177 | case PRID_IMP_R4600: | 178 | case PRID_IMP_R4600: |
178 | case PRID_IMP_R4700: | 179 | case PRID_IMP_R4700: |
179 | system_type = "RM200-C20"; | 180 | system_type = "RM200-C20"; |