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-rw-r--r--arch/arm/Makefile3
-rw-r--r--arch/arm/configs/omap3_beagle_defconfig1321
-rw-r--r--arch/arm/configs/omap_ldp_defconfig1044
-rw-r--r--arch/arm/configs/overo_defconfig1885
-rw-r--r--arch/arm/mach-omap1/clock.c10
-rw-r--r--arch/arm/mach-omap1/clock.h6
-rw-r--r--arch/arm/mach-omap1/devices.c2
-rw-r--r--arch/arm/mach-omap1/mcbsp.c45
-rw-r--r--arch/arm/mach-omap1/serial.c12
-rw-r--r--arch/arm/mach-omap2/Kconfig22
-rw-r--r--arch/arm/mach-omap2/Makefile12
-rw-r--r--arch/arm/mach-omap2/board-ldp.c86
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c244
-rw-r--r--arch/arm/mach-omap2/board-overo.c242
-rw-r--r--arch/arm/mach-omap2/clock.c64
-rw-r--r--arch/arm/mach-omap2/clock.h2
-rw-r--r--arch/arm/mach-omap2/clock24xx.h238
-rw-r--r--arch/arm/mach-omap2/clock34xx.c31
-rw-r--r--arch/arm/mach-omap2/clock34xx.h248
-rw-r--r--arch/arm/mach-omap2/clockdomain.c623
-rw-r--r--arch/arm/mach-omap2/clockdomains.h305
-rw-r--r--arch/arm/mach-omap2/cm-regbits-24xx.h24
-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h42
-rw-r--r--arch/arm/mach-omap2/cm.h2
-rw-r--r--arch/arm/mach-omap2/devices.c225
-rw-r--r--arch/arm/mach-omap2/gpmc.c88
-rw-r--r--arch/arm/mach-omap2/id.c39
-rw-r--r--arch/arm/mach-omap2/io.c152
-rw-r--r--arch/arm/mach-omap2/irq.c81
-rw-r--r--arch/arm/mach-omap2/mcbsp.c151
-rw-r--r--arch/arm/mach-omap2/memory.c14
-rw-r--r--arch/arm/mach-omap2/memory.h7
-rw-r--r--arch/arm/mach-omap2/mux.c245
-rw-r--r--arch/arm/mach-omap2/powerdomain.c1113
-rw-r--r--arch/arm/mach-omap2/powerdomains.h187
-rw-r--r--arch/arm/mach-omap2/powerdomains24xx.h200
-rw-r--r--arch/arm/mach-omap2/powerdomains34xx.h327
-rw-r--r--arch/arm/mach-omap2/prcm-common.h3
-rw-r--r--arch/arm/mach-omap2/prm-regbits-24xx.h12
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h11
-rw-r--r--arch/arm/mach-omap2/prm.h5
-rw-r--r--arch/arm/mach-omap2/serial.c116
-rw-r--r--arch/arm/mach-omap2/sleep24xx.S (renamed from arch/arm/mach-omap2/sleep.S)32
-rw-r--r--arch/arm/mach-omap2/sram34xx.S179
-rw-r--r--arch/arm/mach-pxa/cm-x270.c2
-rw-r--r--arch/arm/mach-pxa/viper.c54
-rw-r--r--arch/arm/mach-s3c2410/bast-irq.c2
-rw-r--r--arch/arm/mach-s3c2410/clock.c8
-rw-r--r--arch/arm/mach-s3c2410/dma.c6
-rw-r--r--arch/arm/mach-s3c2410/include/mach/debug-macro.S4
-rw-r--r--arch/arm/mach-s3c2410/include/mach/map.h2
-rw-r--r--arch/arm/mach-s3c2410/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-s3c2410/irq.c4
-rw-r--r--arch/arm/mach-s3c2410/mach-amlm5900.c6
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c8
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c10
-rw-r--r--arch/arm/mach-s3c2410/mach-n30.c10
-rw-r--r--arch/arm/mach-s3c2410/mach-otom.c10
-rw-r--r--arch/arm/mach-s3c2410/mach-qt2410.c10
-rw-r--r--arch/arm/mach-s3c2410/mach-smdk2410.c8
-rw-r--r--arch/arm/mach-s3c2410/mach-tct_hammer.c6
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c8
-rw-r--r--arch/arm/mach-s3c2410/pm.c4
-rw-r--r--arch/arm/mach-s3c2410/s3c2410.c10
-rw-r--r--arch/arm/mach-s3c2410/sleep.S2
-rw-r--r--arch/arm/mach-s3c2410/usb-simtec.c2
-rw-r--r--arch/arm/mach-s3c2412/clock.c8
-rw-r--r--arch/arm/mach-s3c2412/dma.c6
-rw-r--r--arch/arm/mach-s3c2412/irq.c6
-rw-r--r--arch/arm/mach-s3c2412/mach-jive.c10
-rw-r--r--arch/arm/mach-s3c2412/mach-smdk2413.c14
-rw-r--r--arch/arm/mach-s3c2412/mach-vstms.c12
-rw-r--r--arch/arm/mach-s3c2412/pm.c6
-rw-r--r--arch/arm/mach-s3c2412/s3c2412.c12
-rw-r--r--arch/arm/mach-s3c2440/clock.c4
-rw-r--r--arch/arm/mach-s3c2440/dma.c6
-rw-r--r--arch/arm/mach-s3c2440/dsc.c4
-rw-r--r--arch/arm/mach-s3c2440/irq.c6
-rw-r--r--arch/arm/mach-s3c2440/mach-anubis.c8
-rw-r--r--arch/arm/mach-s3c2440/mach-at2440evb.c8
-rw-r--r--arch/arm/mach-s3c2440/mach-nexcoder.c12
-rw-r--r--arch/arm/mach-s3c2440/mach-osiris.c8
-rw-r--r--arch/arm/mach-s3c2440/mach-rx3715.c10
-rw-r--r--arch/arm/mach-s3c2440/mach-smdk2440.c14
-rw-r--r--arch/arm/mach-s3c2440/s3c2440.c6
-rw-r--r--arch/arm/mach-s3c2442/clock.c4
-rw-r--r--arch/arm/mach-s3c2442/s3c2442.c4
-rw-r--r--arch/arm/mach-s3c2443/clock.c6
-rw-r--r--arch/arm/mach-s3c2443/dma.c6
-rw-r--r--arch/arm/mach-s3c2443/irq.c6
-rw-r--r--arch/arm/mach-s3c2443/mach-smdk2443.c14
-rw-r--r--arch/arm/mach-s3c2443/s3c2443.c6
-rw-r--r--arch/arm/mm/Kconfig2
-rw-r--r--arch/arm/plat-omap/Kconfig33
-rw-r--r--arch/arm/plat-omap/Makefile2
-rw-r--r--arch/arm/plat-omap/common.c40
-rw-r--r--arch/arm/plat-omap/devices.c22
-rw-r--r--arch/arm/plat-omap/dma.c8
-rw-r--r--arch/arm/plat-omap/dmtimer.c2
-rw-r--r--arch/arm/plat-omap/gpio.c70
-rw-r--r--arch/arm/plat-omap/include/mach/board-2430sdp.h6
-rw-r--r--arch/arm/plat-omap/include/mach/board-apollon.h6
-rw-r--r--arch/arm/plat-omap/include/mach/board-h4.h5
-rw-r--r--arch/arm/plat-omap/include/mach/board-ldp.h36
-rw-r--r--arch/arm/plat-omap/include/mach/board-omap3beagle.h33
-rw-r--r--arch/arm/plat-omap/include/mach/board-overo.h26
-rw-r--r--arch/arm/plat-omap/include/mach/board.h2
-rw-r--r--arch/arm/plat-omap/include/mach/clock.h3
-rw-r--r--arch/arm/plat-omap/include/mach/clockdomain.h106
-rw-r--r--arch/arm/plat-omap/include/mach/common.h3
-rw-r--r--arch/arm/plat-omap/include/mach/control.h23
-rw-r--r--arch/arm/plat-omap/include/mach/cpu.h5
-rw-r--r--arch/arm/plat-omap/include/mach/debug-macro.S12
-rw-r--r--arch/arm/plat-omap/include/mach/entry-macro.S12
-rw-r--r--arch/arm/plat-omap/include/mach/fpga.h12
-rw-r--r--arch/arm/plat-omap/include/mach/gpio.h4
-rw-r--r--arch/arm/plat-omap/include/mach/gpmc.h12
-rw-r--r--arch/arm/plat-omap/include/mach/hardware.h12
-rw-r--r--arch/arm/plat-omap/include/mach/io.h59
-rw-r--r--arch/arm/plat-omap/include/mach/irqs.h59
-rw-r--r--arch/arm/plat-omap/include/mach/mcbsp.h44
-rw-r--r--arch/arm/plat-omap/include/mach/memory.h2
-rw-r--r--arch/arm/plat-omap/include/mach/mux.h180
-rw-r--r--arch/arm/plat-omap/include/mach/omap1510.h2
-rw-r--r--arch/arm/plat-omap/include/mach/omap16xx.h7
-rw-r--r--arch/arm/plat-omap/include/mach/omap24xx.h2
-rw-r--r--arch/arm/plat-omap/include/mach/omapfb.h3
-rw-r--r--arch/arm/plat-omap/include/mach/pm.h7
-rw-r--r--arch/arm/plat-omap/include/mach/powerdomain.h166
-rw-r--r--arch/arm/plat-omap/include/mach/sdrc.h8
-rw-r--r--arch/arm/plat-omap/include/mach/serial.h18
-rw-r--r--arch/arm/plat-omap/include/mach/sram.h10
-rw-r--r--arch/arm/plat-omap/include/mach/system.h2
-rw-r--r--arch/arm/plat-omap/io.c107
-rw-r--r--arch/arm/plat-omap/mcbsp.c431
-rw-r--r--arch/arm/plat-omap/sram.c53
-rw-r--r--arch/arm/plat-s3c/Makefile3
-rw-r--r--arch/arm/plat-s3c/include/plat/debug-macro.S (renamed from include/asm-arm/plat-s3c/debug-macro.S)2
-rw-r--r--arch/arm/plat-s3c/include/plat/map.h (renamed from include/asm-arm/plat-s3c/map.h)0
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-adc.h (renamed from include/asm-arm/plat-s3c/regs-adc.h)0
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-serial.h (renamed from include/asm-arm/plat-s3c/regs-serial.h)0
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-timer.h (renamed from include/asm-arm/plat-s3c/regs-timer.h)0
-rw-r--r--arch/arm/plat-s3c/include/plat/uncompress.h (renamed from include/asm-arm/plat-s3c/uncompress.h)2
-rw-r--r--arch/arm/plat-s3c24xx/clock.c4
-rw-r--r--arch/arm/plat-s3c24xx/common-smdk.c6
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c22
-rw-r--r--arch/arm/plat-s3c24xx/devs.c6
-rw-r--r--arch/arm/plat-s3c24xx/dma.c2
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/clock.h (renamed from include/asm-arm/plat-s3c24xx/clock.h)0
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/common-smdk.h (renamed from include/asm-arm/plat-s3c24xx/common-smdk.h)0
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/cpu.h (renamed from include/asm-arm/plat-s3c24xx/cpu.h)0
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/devs.h (renamed from include/asm-arm/plat-s3c24xx/devs.h)0
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/dma.h (renamed from include/asm-arm/plat-s3c24xx/dma.h)0
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/irq.h (renamed from include/asm-arm/plat-s3c24xx/irq.h)0
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/pm.h (renamed from include/asm-arm/plat-s3c24xx/pm.h)0
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2400.h (renamed from include/asm-arm/plat-s3c24xx/s3c2400.h)0
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2410.h (renamed from include/asm-arm/plat-s3c24xx/s3c2410.h)0
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2412.h (renamed from include/asm-arm/plat-s3c24xx/s3c2412.h)0
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2440.h (renamed from include/asm-arm/plat-s3c24xx/s3c2440.h)0
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2442.h (renamed from include/asm-arm/plat-s3c24xx/s3c2442.h)0
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2443.h (renamed from include/asm-arm/plat-s3c24xx/s3c2443.h)0
-rw-r--r--arch/arm/plat-s3c24xx/irq.c6
-rw-r--r--arch/arm/plat-s3c24xx/pm-simtec.c2
-rw-r--r--arch/arm/plat-s3c24xx/pm.c4
-rw-r--r--arch/arm/plat-s3c24xx/pwm-clock.c6
-rw-r--r--arch/arm/plat-s3c24xx/pwm.c4
-rw-r--r--arch/arm/plat-s3c24xx/s3c244x-clock.c4
-rw-r--r--arch/arm/plat-s3c24xx/s3c244x-irq.c6
-rw-r--r--arch/arm/plat-s3c24xx/s3c244x.c14
-rw-r--r--arch/arm/plat-s3c24xx/sleep.S2
-rw-r--r--arch/arm/plat-s3c24xx/time.c6
-rw-r--r--drivers/char/hw_random/omap-rng.c33
-rw-r--r--drivers/i2c/busses/i2c-omap.c12
-rw-r--r--drivers/input/keyboard/omap-keypad.c2
-rw-r--r--drivers/mmc/host/omap.c11
-rw-r--r--drivers/pcmcia/Makefile3
-rw-r--r--drivers/serial/8250.c23
-rw-r--r--drivers/serial/s3c2400.c2
-rw-r--r--drivers/serial/s3c2410.c2
-rw-r--r--drivers/serial/s3c2412.c2
-rw-r--r--drivers/serial/s3c2440.c2
-rw-r--r--drivers/serial/samsung.c2
-rw-r--r--drivers/spi/omap2_mcspi.c18
-rw-r--r--drivers/spi/omap_uwire.c23
-rw-r--r--drivers/usb/host/ohci-omap.c14
-rw-r--r--drivers/video/omap/dispc.c21
-rw-r--r--drivers/video/omap/dispc.h2
-rw-r--r--drivers/video/omap/lcd_h4.c4
-rw-r--r--drivers/video/omap/lcdc.c2
-rw-r--r--drivers/video/omap/lcdc.h2
-rw-r--r--drivers/video/omap/omapfb_main.c15
-rw-r--r--drivers/video/omap/rfbi.c9
-rw-r--r--drivers/video/omap/sossi.c8
193 files changed, 10914 insertions, 1140 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index e2274bc0b544..7d5121260fda 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -118,9 +118,10 @@ endif
118 machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx 118 machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
119 machine-$(CONFIG_ARCH_OMAP1) := omap1 119 machine-$(CONFIG_ARCH_OMAP1) := omap1
120 machine-$(CONFIG_ARCH_OMAP2) := omap2 120 machine-$(CONFIG_ARCH_OMAP2) := omap2
121 machine-$(CONFIG_ARCH_OMAP3) := omap2
121 plat-$(CONFIG_ARCH_OMAP) := omap 122 plat-$(CONFIG_ARCH_OMAP) := omap
122 machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 123 machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
123 plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx 124 plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c
124 machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x 125 machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x
125 machine-$(CONFIG_ARCH_VERSATILE) := versatile 126 machine-$(CONFIG_ARCH_VERSATILE) := versatile
126 machine-$(CONFIG_ARCH_IMX) := imx 127 machine-$(CONFIG_ARCH_IMX) := imx
diff --git a/arch/arm/configs/omap3_beagle_defconfig b/arch/arm/configs/omap3_beagle_defconfig
new file mode 100644
index 000000000000..e042d27eae16
--- /dev/null
+++ b/arch/arm/configs/omap3_beagle_defconfig
@@ -0,0 +1,1321 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.27-rc8
4# Wed Oct 1 17:14:22 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
16CONFIG_LOCKDEP_SUPPORT=y
17CONFIG_TRACE_IRQFLAGS_SUPPORT=y
18CONFIG_HARDIRQS_SW_RESEND=y
19CONFIG_GENERIC_IRQ_PROBE=y
20CONFIG_RWSEM_GENERIC_SPINLOCK=y
21# CONFIG_ARCH_HAS_ILOG2_U32 is not set
22# CONFIG_ARCH_HAS_ILOG2_U64 is not set
23CONFIG_GENERIC_HWEIGHT=y
24CONFIG_GENERIC_CALIBRATE_DELAY=y
25CONFIG_ARCH_SUPPORTS_AOUT=y
26CONFIG_ZONE_DMA=y
27CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
28CONFIG_VECTORS_BASE=0xffff0000
29CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
30
31#
32# General setup
33#
34CONFIG_EXPERIMENTAL=y
35CONFIG_BROKEN_ON_SMP=y
36CONFIG_INIT_ENV_ARG_LIMIT=32
37CONFIG_LOCALVERSION=""
38CONFIG_LOCALVERSION_AUTO=y
39CONFIG_SWAP=y
40CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set
43CONFIG_BSD_PROCESS_ACCT=y
44# CONFIG_BSD_PROCESS_ACCT_V3 is not set
45# CONFIG_TASKSTATS is not set
46# CONFIG_AUDIT is not set
47# CONFIG_IKCONFIG is not set
48CONFIG_LOG_BUF_SHIFT=14
49# CONFIG_CGROUPS is not set
50CONFIG_GROUP_SCHED=y
51CONFIG_FAIR_GROUP_SCHED=y
52# CONFIG_RT_GROUP_SCHED is not set
53CONFIG_USER_SCHED=y
54# CONFIG_CGROUP_SCHED is not set
55CONFIG_SYSFS_DEPRECATED=y
56CONFIG_SYSFS_DEPRECATED_V2=y
57# CONFIG_RELAY is not set
58# CONFIG_NAMESPACES is not set
59CONFIG_BLK_DEV_INITRD=y
60CONFIG_INITRAMFS_SOURCE=""
61CONFIG_CC_OPTIMIZE_FOR_SIZE=y
62CONFIG_SYSCTL=y
63CONFIG_EMBEDDED=y
64CONFIG_UID16=y
65# CONFIG_SYSCTL_SYSCALL is not set
66CONFIG_KALLSYMS=y
67# CONFIG_KALLSYMS_ALL is not set
68CONFIG_KALLSYMS_EXTRA_PASS=y
69CONFIG_HOTPLUG=y
70CONFIG_PRINTK=y
71CONFIG_BUG=y
72CONFIG_ELF_CORE=y
73CONFIG_COMPAT_BRK=y
74CONFIG_BASE_FULL=y
75CONFIG_FUTEX=y
76CONFIG_ANON_INODES=y
77CONFIG_EPOLL=y
78CONFIG_SIGNALFD=y
79CONFIG_TIMERFD=y
80CONFIG_EVENTFD=y
81CONFIG_SHMEM=y
82CONFIG_VM_EVENT_COUNTERS=y
83CONFIG_SLAB=y
84# CONFIG_SLUB is not set
85# CONFIG_SLOB is not set
86# CONFIG_PROFILING is not set
87# CONFIG_MARKERS is not set
88CONFIG_HAVE_OPROFILE=y
89# CONFIG_KPROBES is not set
90# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
91# CONFIG_HAVE_IOREMAP_PROT is not set
92CONFIG_HAVE_KPROBES=y
93CONFIG_HAVE_KRETPROBES=y
94# CONFIG_HAVE_ARCH_TRACEHOOK is not set
95# CONFIG_HAVE_DMA_ATTRS is not set
96# CONFIG_USE_GENERIC_SMP_HELPERS is not set
97CONFIG_HAVE_CLK=y
98CONFIG_PROC_PAGE_MONITOR=y
99CONFIG_HAVE_GENERIC_DMA_COHERENT=y
100CONFIG_SLABINFO=y
101CONFIG_RT_MUTEXES=y
102# CONFIG_TINY_SHMEM is not set
103CONFIG_BASE_SMALL=0
104CONFIG_MODULES=y
105# CONFIG_MODULE_FORCE_LOAD is not set
106CONFIG_MODULE_UNLOAD=y
107# CONFIG_MODULE_FORCE_UNLOAD is not set
108CONFIG_MODVERSIONS=y
109CONFIG_MODULE_SRCVERSION_ALL=y
110CONFIG_KMOD=y
111CONFIG_BLOCK=y
112# CONFIG_LBD is not set
113# CONFIG_BLK_DEV_IO_TRACE is not set
114# CONFIG_LSF is not set
115# CONFIG_BLK_DEV_BSG is not set
116# CONFIG_BLK_DEV_INTEGRITY is not set
117
118#
119# IO Schedulers
120#
121CONFIG_IOSCHED_NOOP=y
122CONFIG_IOSCHED_AS=y
123CONFIG_IOSCHED_DEADLINE=y
124CONFIG_IOSCHED_CFQ=y
125CONFIG_DEFAULT_AS=y
126# CONFIG_DEFAULT_DEADLINE is not set
127# CONFIG_DEFAULT_CFQ is not set
128# CONFIG_DEFAULT_NOOP is not set
129CONFIG_DEFAULT_IOSCHED="anticipatory"
130CONFIG_CLASSIC_RCU=y
131
132#
133# System Type
134#
135# CONFIG_ARCH_AAEC2000 is not set
136# CONFIG_ARCH_INTEGRATOR is not set
137# CONFIG_ARCH_REALVIEW is not set
138# CONFIG_ARCH_VERSATILE is not set
139# CONFIG_ARCH_AT91 is not set
140# CONFIG_ARCH_CLPS7500 is not set
141# CONFIG_ARCH_CLPS711X is not set
142# CONFIG_ARCH_EBSA110 is not set
143# CONFIG_ARCH_EP93XX is not set
144# CONFIG_ARCH_FOOTBRIDGE is not set
145# CONFIG_ARCH_NETX is not set
146# CONFIG_ARCH_H720X is not set
147# CONFIG_ARCH_IMX is not set
148# CONFIG_ARCH_IOP13XX is not set
149# CONFIG_ARCH_IOP32X is not set
150# CONFIG_ARCH_IOP33X is not set
151# CONFIG_ARCH_IXP23XX is not set
152# CONFIG_ARCH_IXP2000 is not set
153# CONFIG_ARCH_IXP4XX is not set
154# CONFIG_ARCH_L7200 is not set
155# CONFIG_ARCH_KIRKWOOD is not set
156# CONFIG_ARCH_KS8695 is not set
157# CONFIG_ARCH_NS9XXX is not set
158# CONFIG_ARCH_LOKI is not set
159# CONFIG_ARCH_MV78XX0 is not set
160# CONFIG_ARCH_MXC is not set
161# CONFIG_ARCH_ORION5X is not set
162# CONFIG_ARCH_PNX4008 is not set
163# CONFIG_ARCH_PXA is not set
164# CONFIG_ARCH_RPC is not set
165# CONFIG_ARCH_SA1100 is not set
166# CONFIG_ARCH_S3C2410 is not set
167# CONFIG_ARCH_SHARK is not set
168# CONFIG_ARCH_LH7A40X is not set
169# CONFIG_ARCH_DAVINCI is not set
170CONFIG_ARCH_OMAP=y
171# CONFIG_ARCH_MSM7X00A is not set
172
173#
174# TI OMAP Implementations
175#
176CONFIG_ARCH_OMAP_OTG=y
177# CONFIG_ARCH_OMAP1 is not set
178# CONFIG_ARCH_OMAP2 is not set
179CONFIG_ARCH_OMAP3=y
180
181#
182# OMAP Feature Selections
183#
184# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
185# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
186# CONFIG_OMAP_RESET_CLOCKS is not set
187# CONFIG_OMAP_MUX is not set
188# CONFIG_OMAP_MCBSP is not set
189# CONFIG_OMAP_MPU_TIMER is not set
190CONFIG_OMAP_32K_TIMER=y
191CONFIG_OMAP_32K_TIMER_HZ=128
192CONFIG_OMAP_DM_TIMER=y
193# CONFIG_OMAP_LL_DEBUG_UART1 is not set
194# CONFIG_OMAP_LL_DEBUG_UART2 is not set
195CONFIG_OMAP_LL_DEBUG_UART3=y
196CONFIG_ARCH_OMAP34XX=y
197CONFIG_ARCH_OMAP3430=y
198
199#
200# OMAP Board Type
201#
202CONFIG_MACH_OMAP3_BEAGLE=y
203
204#
205# Boot options
206#
207
208#
209# Power management
210#
211
212#
213# Processor Type
214#
215CONFIG_CPU_32=y
216CONFIG_CPU_32v6K=y
217CONFIG_CPU_V7=y
218CONFIG_CPU_32v7=y
219CONFIG_CPU_ABRT_EV7=y
220CONFIG_CPU_PABRT_IFAR=y
221CONFIG_CPU_CACHE_V7=y
222CONFIG_CPU_CACHE_VIPT=y
223CONFIG_CPU_COPY_V6=y
224CONFIG_CPU_TLB_V7=y
225CONFIG_CPU_HAS_ASID=y
226CONFIG_CPU_CP15=y
227CONFIG_CPU_CP15_MMU=y
228
229#
230# Processor Features
231#
232CONFIG_ARM_THUMB=y
233# CONFIG_ARM_THUMBEE is not set
234# CONFIG_CPU_ICACHE_DISABLE is not set
235# CONFIG_CPU_DCACHE_DISABLE is not set
236# CONFIG_CPU_BPREDICT_DISABLE is not set
237CONFIG_HAS_TLS_REG=y
238# CONFIG_OUTER_CACHE is not set
239
240#
241# Bus support
242#
243# CONFIG_PCI_SYSCALL is not set
244# CONFIG_ARCH_SUPPORTS_MSI is not set
245# CONFIG_PCCARD is not set
246
247#
248# Kernel Features
249#
250CONFIG_TICK_ONESHOT=y
251CONFIG_NO_HZ=y
252CONFIG_HIGH_RES_TIMERS=y
253CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
254CONFIG_VMSPLIT_3G=y
255# CONFIG_VMSPLIT_2G is not set
256# CONFIG_VMSPLIT_1G is not set
257CONFIG_PAGE_OFFSET=0xC0000000
258# CONFIG_PREEMPT is not set
259CONFIG_HZ=128
260CONFIG_AEABI=y
261CONFIG_OABI_COMPAT=y
262CONFIG_ARCH_FLATMEM_HAS_HOLES=y
263# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
264CONFIG_SELECT_MEMORY_MODEL=y
265CONFIG_FLATMEM_MANUAL=y
266# CONFIG_DISCONTIGMEM_MANUAL is not set
267# CONFIG_SPARSEMEM_MANUAL is not set
268CONFIG_FLATMEM=y
269CONFIG_FLAT_NODE_MEM_MAP=y
270# CONFIG_SPARSEMEM_STATIC is not set
271# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
272CONFIG_PAGEFLAGS_EXTENDED=y
273CONFIG_SPLIT_PTLOCK_CPUS=4
274# CONFIG_RESOURCES_64BIT is not set
275CONFIG_ZONE_DMA_FLAG=1
276CONFIG_BOUNCE=y
277CONFIG_VIRT_TO_BUS=y
278# CONFIG_LEDS is not set
279CONFIG_ALIGNMENT_TRAP=y
280
281#
282# Boot options
283#
284CONFIG_ZBOOT_ROM_TEXT=0x0
285CONFIG_ZBOOT_ROM_BSS=0x0
286CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
287# CONFIG_XIP_KERNEL is not set
288# CONFIG_KEXEC is not set
289
290#
291# CPU Power Management
292#
293# CONFIG_CPU_FREQ is not set
294# CONFIG_CPU_IDLE is not set
295
296#
297# Floating point emulation
298#
299
300#
301# At least one emulation must be selected
302#
303CONFIG_FPE_NWFPE=y
304# CONFIG_FPE_NWFPE_XP is not set
305# CONFIG_FPE_FASTFPE is not set
306CONFIG_VFP=y
307CONFIG_VFPv3=y
308# CONFIG_NEON is not set
309
310#
311# Userspace binary formats
312#
313CONFIG_BINFMT_ELF=y
314# CONFIG_BINFMT_AOUT is not set
315CONFIG_BINFMT_MISC=y
316
317#
318# Power management options
319#
320# CONFIG_PM is not set
321CONFIG_ARCH_SUSPEND_POSSIBLE=y
322CONFIG_NET=y
323
324#
325# Networking options
326#
327CONFIG_PACKET=y
328# CONFIG_PACKET_MMAP is not set
329CONFIG_UNIX=y
330CONFIG_XFRM=y
331# CONFIG_XFRM_USER is not set
332# CONFIG_XFRM_SUB_POLICY is not set
333# CONFIG_XFRM_MIGRATE is not set
334# CONFIG_XFRM_STATISTICS is not set
335CONFIG_NET_KEY=y
336# CONFIG_NET_KEY_MIGRATE is not set
337CONFIG_INET=y
338# CONFIG_IP_MULTICAST is not set
339# CONFIG_IP_ADVANCED_ROUTER is not set
340CONFIG_IP_FIB_HASH=y
341CONFIG_IP_PNP=y
342CONFIG_IP_PNP_DHCP=y
343CONFIG_IP_PNP_BOOTP=y
344CONFIG_IP_PNP_RARP=y
345# CONFIG_NET_IPIP is not set
346# CONFIG_NET_IPGRE is not set
347# CONFIG_ARPD is not set
348# CONFIG_SYN_COOKIES is not set
349# CONFIG_INET_AH is not set
350# CONFIG_INET_ESP is not set
351# CONFIG_INET_IPCOMP is not set
352# CONFIG_INET_XFRM_TUNNEL is not set
353# CONFIG_INET_TUNNEL is not set
354CONFIG_INET_XFRM_MODE_TRANSPORT=y
355CONFIG_INET_XFRM_MODE_TUNNEL=y
356CONFIG_INET_XFRM_MODE_BEET=y
357# CONFIG_INET_LRO is not set
358CONFIG_INET_DIAG=y
359CONFIG_INET_TCP_DIAG=y
360# CONFIG_TCP_CONG_ADVANCED is not set
361CONFIG_TCP_CONG_CUBIC=y
362CONFIG_DEFAULT_TCP_CONG="cubic"
363# CONFIG_TCP_MD5SIG is not set
364# CONFIG_IPV6 is not set
365# CONFIG_NETWORK_SECMARK is not set
366# CONFIG_NETFILTER is not set
367# CONFIG_IP_DCCP is not set
368# CONFIG_IP_SCTP is not set
369# CONFIG_TIPC is not set
370# CONFIG_ATM is not set
371# CONFIG_BRIDGE is not set
372# CONFIG_VLAN_8021Q is not set
373# CONFIG_DECNET is not set
374# CONFIG_LLC2 is not set
375# CONFIG_IPX is not set
376# CONFIG_ATALK is not set
377# CONFIG_X25 is not set
378# CONFIG_LAPB is not set
379# CONFIG_ECONET is not set
380# CONFIG_WAN_ROUTER is not set
381# CONFIG_NET_SCHED is not set
382
383#
384# Network testing
385#
386# CONFIG_NET_PKTGEN is not set
387# CONFIG_HAMRADIO is not set
388# CONFIG_CAN is not set
389# CONFIG_IRDA is not set
390# CONFIG_BT is not set
391# CONFIG_AF_RXRPC is not set
392
393#
394# Wireless
395#
396# CONFIG_CFG80211 is not set
397# CONFIG_WIRELESS_EXT is not set
398# CONFIG_MAC80211 is not set
399# CONFIG_IEEE80211 is not set
400# CONFIG_RFKILL is not set
401# CONFIG_NET_9P is not set
402
403#
404# Device Drivers
405#
406
407#
408# Generic Driver Options
409#
410CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
411CONFIG_STANDALONE=y
412CONFIG_PREVENT_FIRMWARE_BUILD=y
413# CONFIG_FW_LOADER is not set
414# CONFIG_DEBUG_DRIVER is not set
415# CONFIG_DEBUG_DEVRES is not set
416# CONFIG_SYS_HYPERVISOR is not set
417# CONFIG_CONNECTOR is not set
418CONFIG_MTD=y
419# CONFIG_MTD_DEBUG is not set
420# CONFIG_MTD_CONCAT is not set
421CONFIG_MTD_PARTITIONS=y
422# CONFIG_MTD_REDBOOT_PARTS is not set
423# CONFIG_MTD_CMDLINE_PARTS is not set
424# CONFIG_MTD_AFS_PARTS is not set
425# CONFIG_MTD_AR7_PARTS is not set
426
427#
428# User Modules And Translation Layers
429#
430CONFIG_MTD_CHAR=y
431CONFIG_MTD_BLKDEVS=y
432CONFIG_MTD_BLOCK=y
433# CONFIG_FTL is not set
434# CONFIG_NFTL is not set
435# CONFIG_INFTL is not set
436# CONFIG_RFD_FTL is not set
437# CONFIG_SSFDC is not set
438# CONFIG_MTD_OOPS is not set
439
440#
441# RAM/ROM/Flash chip drivers
442#
443# CONFIG_MTD_CFI is not set
444# CONFIG_MTD_JEDECPROBE is not set
445CONFIG_MTD_MAP_BANK_WIDTH_1=y
446CONFIG_MTD_MAP_BANK_WIDTH_2=y
447CONFIG_MTD_MAP_BANK_WIDTH_4=y
448# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
449# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
450# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
451CONFIG_MTD_CFI_I1=y
452CONFIG_MTD_CFI_I2=y
453# CONFIG_MTD_CFI_I4 is not set
454# CONFIG_MTD_CFI_I8 is not set
455# CONFIG_MTD_RAM is not set
456# CONFIG_MTD_ROM is not set
457# CONFIG_MTD_ABSENT is not set
458
459#
460# Mapping drivers for chip access
461#
462# CONFIG_MTD_COMPLEX_MAPPINGS is not set
463# CONFIG_MTD_PLATRAM is not set
464
465#
466# Self-contained MTD device drivers
467#
468# CONFIG_MTD_SLRAM is not set
469# CONFIG_MTD_PHRAM is not set
470# CONFIG_MTD_MTDRAM is not set
471# CONFIG_MTD_BLOCK2MTD is not set
472
473#
474# Disk-On-Chip Device Drivers
475#
476# CONFIG_MTD_DOC2000 is not set
477# CONFIG_MTD_DOC2001 is not set
478# CONFIG_MTD_DOC2001PLUS is not set
479CONFIG_MTD_NAND=y
480# CONFIG_MTD_NAND_VERIFY_WRITE is not set
481# CONFIG_MTD_NAND_ECC_SMC is not set
482# CONFIG_MTD_NAND_MUSEUM_IDS is not set
483CONFIG_MTD_NAND_IDS=y
484# CONFIG_MTD_NAND_DISKONCHIP is not set
485# CONFIG_MTD_NAND_NANDSIM is not set
486# CONFIG_MTD_NAND_PLATFORM is not set
487# CONFIG_MTD_ALAUDA is not set
488# CONFIG_MTD_ONENAND is not set
489
490#
491# UBI - Unsorted block images
492#
493# CONFIG_MTD_UBI is not set
494# CONFIG_PARPORT is not set
495CONFIG_BLK_DEV=y
496# CONFIG_BLK_DEV_COW_COMMON is not set
497CONFIG_BLK_DEV_LOOP=y
498# CONFIG_BLK_DEV_CRYPTOLOOP is not set
499# CONFIG_BLK_DEV_NBD is not set
500# CONFIG_BLK_DEV_UB is not set
501CONFIG_BLK_DEV_RAM=y
502CONFIG_BLK_DEV_RAM_COUNT=16
503CONFIG_BLK_DEV_RAM_SIZE=16384
504# CONFIG_BLK_DEV_XIP is not set
505# CONFIG_CDROM_PKTCDVD is not set
506# CONFIG_ATA_OVER_ETH is not set
507# CONFIG_MISC_DEVICES is not set
508CONFIG_HAVE_IDE=y
509# CONFIG_IDE is not set
510
511#
512# SCSI device support
513#
514# CONFIG_RAID_ATTRS is not set
515CONFIG_SCSI=y
516CONFIG_SCSI_DMA=y
517# CONFIG_SCSI_TGT is not set
518# CONFIG_SCSI_NETLINK is not set
519CONFIG_SCSI_PROC_FS=y
520
521#
522# SCSI support type (disk, tape, CD-ROM)
523#
524CONFIG_BLK_DEV_SD=y
525# CONFIG_CHR_DEV_ST is not set
526# CONFIG_CHR_DEV_OSST is not set
527# CONFIG_BLK_DEV_SR is not set
528# CONFIG_CHR_DEV_SG is not set
529# CONFIG_CHR_DEV_SCH is not set
530
531#
532# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
533#
534# CONFIG_SCSI_MULTI_LUN is not set
535# CONFIG_SCSI_CONSTANTS is not set
536# CONFIG_SCSI_LOGGING is not set
537# CONFIG_SCSI_SCAN_ASYNC is not set
538CONFIG_SCSI_WAIT_SCAN=m
539
540#
541# SCSI Transports
542#
543# CONFIG_SCSI_SPI_ATTRS is not set
544# CONFIG_SCSI_FC_ATTRS is not set
545# CONFIG_SCSI_ISCSI_ATTRS is not set
546# CONFIG_SCSI_SAS_LIBSAS is not set
547# CONFIG_SCSI_SRP_ATTRS is not set
548CONFIG_SCSI_LOWLEVEL=y
549# CONFIG_ISCSI_TCP is not set
550# CONFIG_SCSI_DEBUG is not set
551# CONFIG_SCSI_DH is not set
552# CONFIG_ATA is not set
553# CONFIG_MD is not set
554CONFIG_NETDEVICES=y
555# CONFIG_DUMMY is not set
556# CONFIG_BONDING is not set
557# CONFIG_MACVLAN is not set
558# CONFIG_EQUALIZER is not set
559# CONFIG_TUN is not set
560# CONFIG_VETH is not set
561# CONFIG_NET_ETHERNET is not set
562# CONFIG_NETDEV_1000 is not set
563# CONFIG_NETDEV_10000 is not set
564
565#
566# Wireless LAN
567#
568# CONFIG_WLAN_PRE80211 is not set
569# CONFIG_WLAN_80211 is not set
570# CONFIG_IWLWIFI_LEDS is not set
571
572#
573# USB Network Adapters
574#
575# CONFIG_USB_CATC is not set
576# CONFIG_USB_KAWETH is not set
577# CONFIG_USB_PEGASUS is not set
578# CONFIG_USB_RTL8150 is not set
579# CONFIG_USB_USBNET is not set
580# CONFIG_WAN is not set
581# CONFIG_PPP is not set
582# CONFIG_SLIP is not set
583# CONFIG_NETCONSOLE is not set
584# CONFIG_NETPOLL is not set
585# CONFIG_NET_POLL_CONTROLLER is not set
586# CONFIG_ISDN is not set
587
588#
589# Input device support
590#
591CONFIG_INPUT=y
592# CONFIG_INPUT_FF_MEMLESS is not set
593# CONFIG_INPUT_POLLDEV is not set
594
595#
596# Userland interfaces
597#
598# CONFIG_INPUT_MOUSEDEV is not set
599# CONFIG_INPUT_JOYDEV is not set
600# CONFIG_INPUT_EVDEV is not set
601# CONFIG_INPUT_EVBUG is not set
602
603#
604# Input Device Drivers
605#
606# CONFIG_INPUT_KEYBOARD is not set
607# CONFIG_INPUT_MOUSE is not set
608# CONFIG_INPUT_JOYSTICK is not set
609# CONFIG_INPUT_TABLET is not set
610# CONFIG_INPUT_TOUCHSCREEN is not set
611# CONFIG_INPUT_MISC is not set
612
613#
614# Hardware I/O ports
615#
616# CONFIG_SERIO is not set
617# CONFIG_GAMEPORT is not set
618
619#
620# Character devices
621#
622CONFIG_VT=y
623CONFIG_CONSOLE_TRANSLATIONS=y
624CONFIG_VT_CONSOLE=y
625CONFIG_HW_CONSOLE=y
626# CONFIG_VT_HW_CONSOLE_BINDING is not set
627CONFIG_DEVKMEM=y
628# CONFIG_SERIAL_NONSTANDARD is not set
629
630#
631# Serial drivers
632#
633CONFIG_SERIAL_8250=y
634CONFIG_SERIAL_8250_CONSOLE=y
635CONFIG_SERIAL_8250_NR_UARTS=32
636CONFIG_SERIAL_8250_RUNTIME_UARTS=4
637CONFIG_SERIAL_8250_EXTENDED=y
638CONFIG_SERIAL_8250_MANY_PORTS=y
639CONFIG_SERIAL_8250_SHARE_IRQ=y
640CONFIG_SERIAL_8250_DETECT_IRQ=y
641CONFIG_SERIAL_8250_RSA=y
642
643#
644# Non-8250 serial port support
645#
646CONFIG_SERIAL_CORE=y
647CONFIG_SERIAL_CORE_CONSOLE=y
648CONFIG_UNIX98_PTYS=y
649# CONFIG_LEGACY_PTYS is not set
650# CONFIG_IPMI_HANDLER is not set
651CONFIG_HW_RANDOM=y
652# CONFIG_NVRAM is not set
653# CONFIG_R3964 is not set
654# CONFIG_RAW_DRIVER is not set
655# CONFIG_TCG_TPM is not set
656CONFIG_I2C=y
657CONFIG_I2C_BOARDINFO=y
658CONFIG_I2C_CHARDEV=y
659CONFIG_I2C_HELPER_AUTO=y
660
661#
662# I2C Hardware Bus support
663#
664
665#
666# I2C system bus drivers (mostly embedded / system-on-chip)
667#
668# CONFIG_I2C_GPIO is not set
669# CONFIG_I2C_OCORES is not set
670CONFIG_I2C_OMAP=y
671# CONFIG_I2C_SIMTEC is not set
672
673#
674# External I2C/SMBus adapter drivers
675#
676# CONFIG_I2C_PARPORT_LIGHT is not set
677# CONFIG_I2C_TAOS_EVM is not set
678# CONFIG_I2C_TINY_USB is not set
679
680#
681# Other I2C/SMBus bus drivers
682#
683# CONFIG_I2C_PCA_PLATFORM is not set
684# CONFIG_I2C_STUB is not set
685
686#
687# Miscellaneous I2C Chip support
688#
689# CONFIG_DS1682 is not set
690# CONFIG_AT24 is not set
691# CONFIG_SENSORS_EEPROM is not set
692# CONFIG_SENSORS_PCF8574 is not set
693# CONFIG_PCF8575 is not set
694# CONFIG_SENSORS_PCA9539 is not set
695# CONFIG_SENSORS_PCF8591 is not set
696# CONFIG_ISP1301_OMAP is not set
697# CONFIG_TPS65010 is not set
698# CONFIG_SENSORS_MAX6875 is not set
699# CONFIG_SENSORS_TSL2550 is not set
700# CONFIG_I2C_DEBUG_CORE is not set
701# CONFIG_I2C_DEBUG_ALGO is not set
702# CONFIG_I2C_DEBUG_BUS is not set
703# CONFIG_I2C_DEBUG_CHIP is not set
704# CONFIG_SPI is not set
705CONFIG_ARCH_REQUIRE_GPIOLIB=y
706CONFIG_GPIOLIB=y
707# CONFIG_DEBUG_GPIO is not set
708# CONFIG_GPIO_SYSFS is not set
709
710#
711# I2C GPIO expanders:
712#
713# CONFIG_GPIO_MAX732X is not set
714# CONFIG_GPIO_PCA953X is not set
715# CONFIG_GPIO_PCF857X is not set
716
717#
718# PCI GPIO expanders:
719#
720
721#
722# SPI GPIO expanders:
723#
724# CONFIG_W1 is not set
725# CONFIG_POWER_SUPPLY is not set
726# CONFIG_HWMON is not set
727# CONFIG_THERMAL is not set
728# CONFIG_THERMAL_HWMON is not set
729# CONFIG_WATCHDOG is not set
730
731#
732# Sonics Silicon Backplane
733#
734CONFIG_SSB_POSSIBLE=y
735# CONFIG_SSB is not set
736
737#
738# Multifunction device drivers
739#
740# CONFIG_MFD_CORE is not set
741# CONFIG_MFD_SM501 is not set
742# CONFIG_HTC_EGPIO is not set
743# CONFIG_HTC_PASIC3 is not set
744# CONFIG_UCB1400_CORE is not set
745# CONFIG_MFD_TMIO is not set
746# CONFIG_MFD_T7L66XB is not set
747# CONFIG_MFD_TC6387XB is not set
748# CONFIG_MFD_TC6393XB is not set
749
750#
751# Multimedia devices
752#
753
754#
755# Multimedia core support
756#
757# CONFIG_VIDEO_DEV is not set
758# CONFIG_DVB_CORE is not set
759# CONFIG_VIDEO_MEDIA is not set
760
761#
762# Multimedia drivers
763#
764CONFIG_DAB=y
765# CONFIG_USB_DABUSB is not set
766
767#
768# Graphics support
769#
770# CONFIG_VGASTATE is not set
771# CONFIG_VIDEO_OUTPUT_CONTROL is not set
772# CONFIG_FB is not set
773# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
774
775#
776# Display device support
777#
778# CONFIG_DISPLAY_SUPPORT is not set
779
780#
781# Console display driver support
782#
783# CONFIG_VGA_CONSOLE is not set
784CONFIG_DUMMY_CONSOLE=y
785# CONFIG_SOUND is not set
786# CONFIG_HID_SUPPORT is not set
787CONFIG_USB_SUPPORT=y
788CONFIG_USB_ARCH_HAS_HCD=y
789CONFIG_USB_ARCH_HAS_OHCI=y
790# CONFIG_USB_ARCH_HAS_EHCI is not set
791CONFIG_USB=y
792# CONFIG_USB_DEBUG is not set
793# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
794
795#
796# Miscellaneous USB options
797#
798CONFIG_USB_DEVICEFS=y
799CONFIG_USB_DEVICE_CLASS=y
800# CONFIG_USB_DYNAMIC_MINORS is not set
801# CONFIG_USB_OTG is not set
802# CONFIG_USB_OTG_WHITELIST is not set
803# CONFIG_USB_OTG_BLACKLIST_HUB is not set
804CONFIG_USB_MON=y
805
806#
807# USB Host Controller Drivers
808#
809# CONFIG_USB_C67X00_HCD is not set
810# CONFIG_USB_ISP116X_HCD is not set
811# CONFIG_USB_ISP1760_HCD is not set
812# CONFIG_USB_OHCI_HCD is not set
813# CONFIG_USB_SL811_HCD is not set
814# CONFIG_USB_R8A66597_HCD is not set
815CONFIG_USB_MUSB_HDRC=y
816CONFIG_USB_MUSB_SOC=y
817
818#
819# OMAP 343x high speed USB support
820#
821CONFIG_USB_MUSB_HOST=y
822# CONFIG_USB_MUSB_PERIPHERAL is not set
823# CONFIG_USB_MUSB_OTG is not set
824# CONFIG_USB_GADGET_MUSB_HDRC is not set
825CONFIG_USB_MUSB_HDRC_HCD=y
826# CONFIG_MUSB_PIO_ONLY is not set
827CONFIG_USB_INVENTRA_DMA=y
828# CONFIG_USB_TI_CPPI_DMA is not set
829# CONFIG_USB_MUSB_DEBUG is not set
830
831#
832# USB Device Class drivers
833#
834# CONFIG_USB_ACM is not set
835# CONFIG_USB_PRINTER is not set
836# CONFIG_USB_WDM is not set
837
838#
839# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
840#
841
842#
843# may also be needed; see USB_STORAGE Help for more information
844#
845# CONFIG_USB_STORAGE is not set
846# CONFIG_USB_LIBUSUAL is not set
847
848#
849# USB Imaging devices
850#
851# CONFIG_USB_MDC800 is not set
852# CONFIG_USB_MICROTEK is not set
853
854#
855# USB port drivers
856#
857# CONFIG_USB_SERIAL is not set
858
859#
860# USB Miscellaneous drivers
861#
862# CONFIG_USB_EMI62 is not set
863# CONFIG_USB_EMI26 is not set
864# CONFIG_USB_ADUTUX is not set
865# CONFIG_USB_RIO500 is not set
866# CONFIG_USB_LEGOTOWER is not set
867# CONFIG_USB_LCD is not set
868# CONFIG_USB_BERRY_CHARGE is not set
869# CONFIG_USB_LED is not set
870# CONFIG_USB_CYPRESS_CY7C63 is not set
871# CONFIG_USB_CYTHERM is not set
872# CONFIG_USB_PHIDGET is not set
873# CONFIG_USB_IDMOUSE is not set
874# CONFIG_USB_FTDI_ELAN is not set
875# CONFIG_USB_APPLEDISPLAY is not set
876# CONFIG_USB_LD is not set
877# CONFIG_USB_TRANCEVIBRATOR is not set
878# CONFIG_USB_IOWARRIOR is not set
879# CONFIG_USB_TEST is not set
880# CONFIG_USB_ISIGHTFW is not set
881CONFIG_USB_GADGET=y
882# CONFIG_USB_GADGET_DEBUG is not set
883# CONFIG_USB_GADGET_DEBUG_FILES is not set
884CONFIG_USB_GADGET_SELECTED=y
885# CONFIG_USB_GADGET_AMD5536UDC is not set
886# CONFIG_USB_GADGET_ATMEL_USBA is not set
887# CONFIG_USB_GADGET_FSL_USB2 is not set
888# CONFIG_USB_GADGET_NET2280 is not set
889# CONFIG_USB_GADGET_PXA25X is not set
890CONFIG_USB_GADGET_M66592=y
891CONFIG_USB_M66592=y
892# CONFIG_USB_GADGET_PXA27X is not set
893# CONFIG_USB_GADGET_GOKU is not set
894# CONFIG_USB_GADGET_LH7A40X is not set
895# CONFIG_USB_GADGET_OMAP is not set
896# CONFIG_USB_GADGET_S3C2410 is not set
897# CONFIG_USB_GADGET_AT91 is not set
898# CONFIG_USB_GADGET_DUMMY_HCD is not set
899CONFIG_USB_GADGET_DUALSPEED=y
900# CONFIG_USB_ZERO is not set
901CONFIG_USB_ETH=m
902CONFIG_USB_ETH_RNDIS=y
903# CONFIG_USB_GADGETFS is not set
904# CONFIG_USB_FILE_STORAGE is not set
905# CONFIG_USB_G_SERIAL is not set
906# CONFIG_USB_MIDI_GADGET is not set
907# CONFIG_USB_G_PRINTER is not set
908# CONFIG_USB_CDC_COMPOSITE is not set
909CONFIG_MMC=y
910# CONFIG_MMC_DEBUG is not set
911# CONFIG_MMC_UNSAFE_RESUME is not set
912
913#
914# MMC/SD Card Drivers
915#
916CONFIG_MMC_BLOCK=y
917CONFIG_MMC_BLOCK_BOUNCE=y
918# CONFIG_SDIO_UART is not set
919# CONFIG_MMC_TEST is not set
920
921#
922# MMC/SD Host Controller Drivers
923#
924# CONFIG_MMC_SDHCI is not set
925# CONFIG_MMC_OMAP is not set
926# CONFIG_MEMSTICK is not set
927# CONFIG_ACCESSIBILITY is not set
928# CONFIG_NEW_LEDS is not set
929CONFIG_RTC_LIB=y
930CONFIG_RTC_CLASS=y
931CONFIG_RTC_HCTOSYS=y
932CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
933# CONFIG_RTC_DEBUG is not set
934
935#
936# RTC interfaces
937#
938CONFIG_RTC_INTF_SYSFS=y
939CONFIG_RTC_INTF_PROC=y
940CONFIG_RTC_INTF_DEV=y
941# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
942# CONFIG_RTC_DRV_TEST is not set
943
944#
945# I2C RTC drivers
946#
947# CONFIG_RTC_DRV_DS1307 is not set
948# CONFIG_RTC_DRV_DS1374 is not set
949# CONFIG_RTC_DRV_DS1672 is not set
950# CONFIG_RTC_DRV_MAX6900 is not set
951# CONFIG_RTC_DRV_RS5C372 is not set
952# CONFIG_RTC_DRV_ISL1208 is not set
953# CONFIG_RTC_DRV_X1205 is not set
954# CONFIG_RTC_DRV_PCF8563 is not set
955# CONFIG_RTC_DRV_PCF8583 is not set
956# CONFIG_RTC_DRV_M41T80 is not set
957# CONFIG_RTC_DRV_S35390A is not set
958# CONFIG_RTC_DRV_FM3130 is not set
959
960#
961# SPI RTC drivers
962#
963
964#
965# Platform RTC drivers
966#
967# CONFIG_RTC_DRV_CMOS is not set
968# CONFIG_RTC_DRV_DS1511 is not set
969# CONFIG_RTC_DRV_DS1553 is not set
970# CONFIG_RTC_DRV_DS1742 is not set
971# CONFIG_RTC_DRV_STK17TA8 is not set
972# CONFIG_RTC_DRV_M48T86 is not set
973# CONFIG_RTC_DRV_M48T59 is not set
974# CONFIG_RTC_DRV_V3020 is not set
975
976#
977# on-CPU RTC drivers
978#
979# CONFIG_DMADEVICES is not set
980
981#
982# Voltage and Current regulators
983#
984# CONFIG_REGULATOR is not set
985# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
986# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
987# CONFIG_REGULATOR_BQ24022 is not set
988# CONFIG_UIO is not set
989
990#
991# File systems
992#
993CONFIG_EXT2_FS=y
994# CONFIG_EXT2_FS_XATTR is not set
995# CONFIG_EXT2_FS_XIP is not set
996CONFIG_EXT3_FS=y
997# CONFIG_EXT3_FS_XATTR is not set
998# CONFIG_EXT4DEV_FS is not set
999CONFIG_JBD=y
1000# CONFIG_REISERFS_FS is not set
1001# CONFIG_JFS_FS is not set
1002# CONFIG_FS_POSIX_ACL is not set
1003# CONFIG_XFS_FS is not set
1004# CONFIG_OCFS2_FS is not set
1005CONFIG_DNOTIFY=y
1006CONFIG_INOTIFY=y
1007CONFIG_INOTIFY_USER=y
1008CONFIG_QUOTA=y
1009# CONFIG_QUOTA_NETLINK_INTERFACE is not set
1010CONFIG_PRINT_QUOTA_WARNING=y
1011# CONFIG_QFMT_V1 is not set
1012CONFIG_QFMT_V2=y
1013CONFIG_QUOTACTL=y
1014# CONFIG_AUTOFS_FS is not set
1015# CONFIG_AUTOFS4_FS is not set
1016# CONFIG_FUSE_FS is not set
1017
1018#
1019# CD-ROM/DVD Filesystems
1020#
1021# CONFIG_ISO9660_FS is not set
1022# CONFIG_UDF_FS is not set
1023
1024#
1025# DOS/FAT/NT Filesystems
1026#
1027CONFIG_FAT_FS=y
1028CONFIG_MSDOS_FS=y
1029CONFIG_VFAT_FS=y
1030CONFIG_FAT_DEFAULT_CODEPAGE=437
1031CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1032# CONFIG_NTFS_FS is not set
1033
1034#
1035# Pseudo filesystems
1036#
1037CONFIG_PROC_FS=y
1038CONFIG_PROC_SYSCTL=y
1039CONFIG_SYSFS=y
1040CONFIG_TMPFS=y
1041# CONFIG_TMPFS_POSIX_ACL is not set
1042# CONFIG_HUGETLB_PAGE is not set
1043# CONFIG_CONFIGFS_FS is not set
1044
1045#
1046# Miscellaneous filesystems
1047#
1048# CONFIG_ADFS_FS is not set
1049# CONFIG_AFFS_FS is not set
1050# CONFIG_HFS_FS is not set
1051# CONFIG_HFSPLUS_FS is not set
1052# CONFIG_BEFS_FS is not set
1053# CONFIG_BFS_FS is not set
1054# CONFIG_EFS_FS is not set
1055CONFIG_JFFS2_FS=y
1056CONFIG_JFFS2_FS_DEBUG=0
1057CONFIG_JFFS2_FS_WRITEBUFFER=y
1058# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1059# CONFIG_JFFS2_SUMMARY is not set
1060# CONFIG_JFFS2_FS_XATTR is not set
1061# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1062CONFIG_JFFS2_ZLIB=y
1063# CONFIG_JFFS2_LZO is not set
1064CONFIG_JFFS2_RTIME=y
1065# CONFIG_JFFS2_RUBIN is not set
1066# CONFIG_CRAMFS is not set
1067# CONFIG_VXFS_FS is not set
1068# CONFIG_MINIX_FS is not set
1069# CONFIG_OMFS_FS is not set
1070# CONFIG_HPFS_FS is not set
1071# CONFIG_QNX4FS_FS is not set
1072# CONFIG_ROMFS_FS is not set
1073# CONFIG_SYSV_FS is not set
1074# CONFIG_UFS_FS is not set
1075CONFIG_NETWORK_FILESYSTEMS=y
1076CONFIG_NFS_FS=y
1077CONFIG_NFS_V3=y
1078# CONFIG_NFS_V3_ACL is not set
1079CONFIG_NFS_V4=y
1080CONFIG_ROOT_NFS=y
1081# CONFIG_NFSD is not set
1082CONFIG_LOCKD=y
1083CONFIG_LOCKD_V4=y
1084CONFIG_NFS_COMMON=y
1085CONFIG_SUNRPC=y
1086CONFIG_SUNRPC_GSS=y
1087CONFIG_RPCSEC_GSS_KRB5=y
1088# CONFIG_RPCSEC_GSS_SPKM3 is not set
1089# CONFIG_SMB_FS is not set
1090# CONFIG_CIFS is not set
1091# CONFIG_NCP_FS is not set
1092# CONFIG_CODA_FS is not set
1093# CONFIG_AFS_FS is not set
1094
1095#
1096# Partition Types
1097#
1098CONFIG_PARTITION_ADVANCED=y
1099# CONFIG_ACORN_PARTITION is not set
1100# CONFIG_OSF_PARTITION is not set
1101# CONFIG_AMIGA_PARTITION is not set
1102# CONFIG_ATARI_PARTITION is not set
1103# CONFIG_MAC_PARTITION is not set
1104CONFIG_MSDOS_PARTITION=y
1105# CONFIG_BSD_DISKLABEL is not set
1106# CONFIG_MINIX_SUBPARTITION is not set
1107# CONFIG_SOLARIS_X86_PARTITION is not set
1108# CONFIG_UNIXWARE_DISKLABEL is not set
1109# CONFIG_LDM_PARTITION is not set
1110# CONFIG_SGI_PARTITION is not set
1111# CONFIG_ULTRIX_PARTITION is not set
1112# CONFIG_SUN_PARTITION is not set
1113# CONFIG_KARMA_PARTITION is not set
1114# CONFIG_EFI_PARTITION is not set
1115# CONFIG_SYSV68_PARTITION is not set
1116CONFIG_NLS=y
1117CONFIG_NLS_DEFAULT="iso8859-1"
1118CONFIG_NLS_CODEPAGE_437=y
1119# CONFIG_NLS_CODEPAGE_737 is not set
1120# CONFIG_NLS_CODEPAGE_775 is not set
1121# CONFIG_NLS_CODEPAGE_850 is not set
1122# CONFIG_NLS_CODEPAGE_852 is not set
1123# CONFIG_NLS_CODEPAGE_855 is not set
1124# CONFIG_NLS_CODEPAGE_857 is not set
1125# CONFIG_NLS_CODEPAGE_860 is not set
1126# CONFIG_NLS_CODEPAGE_861 is not set
1127# CONFIG_NLS_CODEPAGE_862 is not set
1128# CONFIG_NLS_CODEPAGE_863 is not set
1129# CONFIG_NLS_CODEPAGE_864 is not set
1130# CONFIG_NLS_CODEPAGE_865 is not set
1131# CONFIG_NLS_CODEPAGE_866 is not set
1132# CONFIG_NLS_CODEPAGE_869 is not set
1133# CONFIG_NLS_CODEPAGE_936 is not set
1134# CONFIG_NLS_CODEPAGE_950 is not set
1135# CONFIG_NLS_CODEPAGE_932 is not set
1136# CONFIG_NLS_CODEPAGE_949 is not set
1137# CONFIG_NLS_CODEPAGE_874 is not set
1138# CONFIG_NLS_ISO8859_8 is not set
1139# CONFIG_NLS_CODEPAGE_1250 is not set
1140# CONFIG_NLS_CODEPAGE_1251 is not set
1141# CONFIG_NLS_ASCII is not set
1142CONFIG_NLS_ISO8859_1=y
1143# CONFIG_NLS_ISO8859_2 is not set
1144# CONFIG_NLS_ISO8859_3 is not set
1145# CONFIG_NLS_ISO8859_4 is not set
1146# CONFIG_NLS_ISO8859_5 is not set
1147# CONFIG_NLS_ISO8859_6 is not set
1148# CONFIG_NLS_ISO8859_7 is not set
1149# CONFIG_NLS_ISO8859_9 is not set
1150# CONFIG_NLS_ISO8859_13 is not set
1151# CONFIG_NLS_ISO8859_14 is not set
1152# CONFIG_NLS_ISO8859_15 is not set
1153# CONFIG_NLS_KOI8_R is not set
1154# CONFIG_NLS_KOI8_U is not set
1155# CONFIG_NLS_UTF8 is not set
1156# CONFIG_DLM is not set
1157
1158#
1159# Kernel hacking
1160#
1161# CONFIG_PRINTK_TIME is not set
1162CONFIG_ENABLE_WARN_DEPRECATED=y
1163CONFIG_ENABLE_MUST_CHECK=y
1164CONFIG_FRAME_WARN=1024
1165CONFIG_MAGIC_SYSRQ=y
1166# CONFIG_UNUSED_SYMBOLS is not set
1167# CONFIG_DEBUG_FS is not set
1168# CONFIG_HEADERS_CHECK is not set
1169CONFIG_DEBUG_KERNEL=y
1170# CONFIG_DEBUG_SHIRQ is not set
1171CONFIG_DETECT_SOFTLOCKUP=y
1172# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1173CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1174CONFIG_SCHED_DEBUG=y
1175# CONFIG_SCHEDSTATS is not set
1176# CONFIG_TIMER_STATS is not set
1177# CONFIG_DEBUG_OBJECTS is not set
1178# CONFIG_DEBUG_SLAB is not set
1179# CONFIG_DEBUG_RT_MUTEXES is not set
1180# CONFIG_RT_MUTEX_TESTER is not set
1181# CONFIG_DEBUG_SPINLOCK is not set
1182CONFIG_DEBUG_MUTEXES=y
1183# CONFIG_DEBUG_LOCK_ALLOC is not set
1184# CONFIG_PROVE_LOCKING is not set
1185# CONFIG_LOCK_STAT is not set
1186# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1187# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1188# CONFIG_DEBUG_KOBJECT is not set
1189# CONFIG_DEBUG_BUGVERBOSE is not set
1190CONFIG_DEBUG_INFO=y
1191# CONFIG_DEBUG_VM is not set
1192# CONFIG_DEBUG_WRITECOUNT is not set
1193# CONFIG_DEBUG_MEMORY_INIT is not set
1194# CONFIG_DEBUG_LIST is not set
1195# CONFIG_DEBUG_SG is not set
1196CONFIG_FRAME_POINTER=y
1197# CONFIG_BOOT_PRINTK_DELAY is not set
1198# CONFIG_RCU_TORTURE_TEST is not set
1199# CONFIG_BACKTRACE_SELF_TEST is not set
1200# CONFIG_FAULT_INJECTION is not set
1201# CONFIG_LATENCYTOP is not set
1202CONFIG_HAVE_FTRACE=y
1203CONFIG_HAVE_DYNAMIC_FTRACE=y
1204# CONFIG_FTRACE is not set
1205# CONFIG_IRQSOFF_TRACER is not set
1206# CONFIG_SCHED_TRACER is not set
1207# CONFIG_CONTEXT_SWITCH_TRACER is not set
1208# CONFIG_SAMPLES is not set
1209CONFIG_HAVE_ARCH_KGDB=y
1210# CONFIG_KGDB is not set
1211# CONFIG_DEBUG_USER is not set
1212# CONFIG_DEBUG_ERRORS is not set
1213# CONFIG_DEBUG_STACK_USAGE is not set
1214# CONFIG_DEBUG_LL is not set
1215
1216#
1217# Security options
1218#
1219# CONFIG_KEYS is not set
1220# CONFIG_SECURITY is not set
1221# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1222CONFIG_CRYPTO=y
1223
1224#
1225# Crypto core or helper
1226#
1227CONFIG_CRYPTO_ALGAPI=y
1228CONFIG_CRYPTO_BLKCIPHER=y
1229CONFIG_CRYPTO_MANAGER=y
1230# CONFIG_CRYPTO_GF128MUL is not set
1231# CONFIG_CRYPTO_NULL is not set
1232# CONFIG_CRYPTO_CRYPTD is not set
1233# CONFIG_CRYPTO_AUTHENC is not set
1234# CONFIG_CRYPTO_TEST is not set
1235
1236#
1237# Authenticated Encryption with Associated Data
1238#
1239# CONFIG_CRYPTO_CCM is not set
1240# CONFIG_CRYPTO_GCM is not set
1241# CONFIG_CRYPTO_SEQIV is not set
1242
1243#
1244# Block modes
1245#
1246CONFIG_CRYPTO_CBC=y
1247# CONFIG_CRYPTO_CTR is not set
1248# CONFIG_CRYPTO_CTS is not set
1249CONFIG_CRYPTO_ECB=m
1250# CONFIG_CRYPTO_LRW is not set
1251CONFIG_CRYPTO_PCBC=m
1252# CONFIG_CRYPTO_XTS is not set
1253
1254#
1255# Hash modes
1256#
1257# CONFIG_CRYPTO_HMAC is not set
1258# CONFIG_CRYPTO_XCBC is not set
1259
1260#
1261# Digest
1262#
1263# CONFIG_CRYPTO_CRC32C is not set
1264# CONFIG_CRYPTO_MD4 is not set
1265CONFIG_CRYPTO_MD5=y
1266# CONFIG_CRYPTO_MICHAEL_MIC is not set
1267# CONFIG_CRYPTO_RMD128 is not set
1268# CONFIG_CRYPTO_RMD160 is not set
1269# CONFIG_CRYPTO_RMD256 is not set
1270# CONFIG_CRYPTO_RMD320 is not set
1271# CONFIG_CRYPTO_SHA1 is not set
1272# CONFIG_CRYPTO_SHA256 is not set
1273# CONFIG_CRYPTO_SHA512 is not set
1274# CONFIG_CRYPTO_TGR192 is not set
1275# CONFIG_CRYPTO_WP512 is not set
1276
1277#
1278# Ciphers
1279#
1280# CONFIG_CRYPTO_AES is not set
1281# CONFIG_CRYPTO_ANUBIS is not set
1282# CONFIG_CRYPTO_ARC4 is not set
1283# CONFIG_CRYPTO_BLOWFISH is not set
1284# CONFIG_CRYPTO_CAMELLIA is not set
1285# CONFIG_CRYPTO_CAST5 is not set
1286# CONFIG_CRYPTO_CAST6 is not set
1287CONFIG_CRYPTO_DES=y
1288# CONFIG_CRYPTO_FCRYPT is not set
1289# CONFIG_CRYPTO_KHAZAD is not set
1290# CONFIG_CRYPTO_SALSA20 is not set
1291# CONFIG_CRYPTO_SEED is not set
1292# CONFIG_CRYPTO_SERPENT is not set
1293# CONFIG_CRYPTO_TEA is not set
1294# CONFIG_CRYPTO_TWOFISH is not set
1295
1296#
1297# Compression
1298#
1299# CONFIG_CRYPTO_DEFLATE is not set
1300# CONFIG_CRYPTO_LZO is not set
1301CONFIG_CRYPTO_HW=y
1302
1303#
1304# Library routines
1305#
1306CONFIG_BITREVERSE=y
1307# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1308# CONFIG_GENERIC_FIND_NEXT_BIT is not set
1309CONFIG_CRC_CCITT=y
1310# CONFIG_CRC16 is not set
1311# CONFIG_CRC_T10DIF is not set
1312# CONFIG_CRC_ITU_T is not set
1313CONFIG_CRC32=y
1314# CONFIG_CRC7 is not set
1315CONFIG_LIBCRC32C=y
1316CONFIG_ZLIB_INFLATE=y
1317CONFIG_ZLIB_DEFLATE=y
1318CONFIG_PLIST=y
1319CONFIG_HAS_IOMEM=y
1320CONFIG_HAS_IOPORT=y
1321CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/omap_ldp_defconfig b/arch/arm/configs/omap_ldp_defconfig
new file mode 100644
index 000000000000..948a212fb1cc
--- /dev/null
+++ b/arch/arm/configs/omap_ldp_defconfig
@@ -0,0 +1,1044 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.27-rc5
4# Fri Oct 10 11:49:41 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
16CONFIG_LOCKDEP_SUPPORT=y
17CONFIG_TRACE_IRQFLAGS_SUPPORT=y
18CONFIG_HARDIRQS_SW_RESEND=y
19CONFIG_GENERIC_IRQ_PROBE=y
20CONFIG_RWSEM_GENERIC_SPINLOCK=y
21# CONFIG_ARCH_HAS_ILOG2_U32 is not set
22# CONFIG_ARCH_HAS_ILOG2_U64 is not set
23CONFIG_GENERIC_HWEIGHT=y
24CONFIG_GENERIC_CALIBRATE_DELAY=y
25CONFIG_ARCH_SUPPORTS_AOUT=y
26CONFIG_ZONE_DMA=y
27CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
28CONFIG_VECTORS_BASE=0xffff0000
29CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
30
31#
32# General setup
33#
34CONFIG_EXPERIMENTAL=y
35CONFIG_BROKEN_ON_SMP=y
36CONFIG_INIT_ENV_ARG_LIMIT=32
37CONFIG_LOCALVERSION=""
38CONFIG_LOCALVERSION_AUTO=y
39CONFIG_SWAP=y
40CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y
42CONFIG_BSD_PROCESS_ACCT=y
43# CONFIG_BSD_PROCESS_ACCT_V3 is not set
44# CONFIG_IKCONFIG is not set
45CONFIG_LOG_BUF_SHIFT=14
46# CONFIG_CGROUPS is not set
47CONFIG_GROUP_SCHED=y
48CONFIG_FAIR_GROUP_SCHED=y
49# CONFIG_RT_GROUP_SCHED is not set
50CONFIG_USER_SCHED=y
51# CONFIG_CGROUP_SCHED is not set
52CONFIG_SYSFS_DEPRECATED=y
53CONFIG_SYSFS_DEPRECATED_V2=y
54# CONFIG_RELAY is not set
55# CONFIG_NAMESPACES is not set
56CONFIG_BLK_DEV_INITRD=y
57CONFIG_INITRAMFS_SOURCE=""
58CONFIG_CC_OPTIMIZE_FOR_SIZE=y
59CONFIG_SYSCTL=y
60CONFIG_EMBEDDED=y
61CONFIG_UID16=y
62# CONFIG_SYSCTL_SYSCALL is not set
63CONFIG_KALLSYMS=y
64# CONFIG_KALLSYMS_ALL is not set
65CONFIG_KALLSYMS_EXTRA_PASS=y
66CONFIG_HOTPLUG=y
67CONFIG_PRINTK=y
68CONFIG_BUG=y
69CONFIG_ELF_CORE=y
70CONFIG_COMPAT_BRK=y
71CONFIG_BASE_FULL=y
72CONFIG_FUTEX=y
73CONFIG_ANON_INODES=y
74CONFIG_EPOLL=y
75CONFIG_SIGNALFD=y
76CONFIG_TIMERFD=y
77CONFIG_EVENTFD=y
78CONFIG_SHMEM=y
79CONFIG_VM_EVENT_COUNTERS=y
80CONFIG_SLAB=y
81# CONFIG_SLUB is not set
82# CONFIG_SLOB is not set
83# CONFIG_PROFILING is not set
84# CONFIG_MARKERS is not set
85CONFIG_HAVE_OPROFILE=y
86# CONFIG_KPROBES is not set
87# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
88# CONFIG_HAVE_IOREMAP_PROT is not set
89CONFIG_HAVE_KPROBES=y
90CONFIG_HAVE_KRETPROBES=y
91# CONFIG_HAVE_ARCH_TRACEHOOK is not set
92# CONFIG_HAVE_DMA_ATTRS is not set
93# CONFIG_USE_GENERIC_SMP_HELPERS is not set
94CONFIG_HAVE_CLK=y
95CONFIG_PROC_PAGE_MONITOR=y
96CONFIG_HAVE_GENERIC_DMA_COHERENT=y
97CONFIG_SLABINFO=y
98CONFIG_RT_MUTEXES=y
99# CONFIG_TINY_SHMEM is not set
100CONFIG_BASE_SMALL=0
101CONFIG_MODULES=y
102# CONFIG_MODULE_FORCE_LOAD is not set
103CONFIG_MODULE_UNLOAD=y
104# CONFIG_MODULE_FORCE_UNLOAD is not set
105CONFIG_MODVERSIONS=y
106CONFIG_MODULE_SRCVERSION_ALL=y
107CONFIG_KMOD=y
108CONFIG_BLOCK=y
109# CONFIG_LBD is not set
110# CONFIG_BLK_DEV_IO_TRACE is not set
111# CONFIG_LSF is not set
112# CONFIG_BLK_DEV_BSG is not set
113# CONFIG_BLK_DEV_INTEGRITY is not set
114
115#
116# IO Schedulers
117#
118CONFIG_IOSCHED_NOOP=y
119CONFIG_IOSCHED_AS=y
120CONFIG_IOSCHED_DEADLINE=y
121CONFIG_IOSCHED_CFQ=y
122CONFIG_DEFAULT_AS=y
123# CONFIG_DEFAULT_DEADLINE is not set
124# CONFIG_DEFAULT_CFQ is not set
125# CONFIG_DEFAULT_NOOP is not set
126CONFIG_DEFAULT_IOSCHED="anticipatory"
127CONFIG_CLASSIC_RCU=y
128
129#
130# System Type
131#
132# CONFIG_ARCH_AAEC2000 is not set
133# CONFIG_ARCH_INTEGRATOR is not set
134# CONFIG_ARCH_REALVIEW is not set
135# CONFIG_ARCH_VERSATILE is not set
136# CONFIG_ARCH_AT91 is not set
137# CONFIG_ARCH_CLPS7500 is not set
138# CONFIG_ARCH_CLPS711X is not set
139# CONFIG_ARCH_EBSA110 is not set
140# CONFIG_ARCH_EP93XX is not set
141# CONFIG_ARCH_FOOTBRIDGE is not set
142# CONFIG_ARCH_NETX is not set
143# CONFIG_ARCH_H720X is not set
144# CONFIG_ARCH_IMX is not set
145# CONFIG_ARCH_IOP13XX is not set
146# CONFIG_ARCH_IOP32X is not set
147# CONFIG_ARCH_IOP33X is not set
148# CONFIG_ARCH_IXP23XX is not set
149# CONFIG_ARCH_IXP2000 is not set
150# CONFIG_ARCH_IXP4XX is not set
151# CONFIG_ARCH_L7200 is not set
152# CONFIG_ARCH_KIRKWOOD is not set
153# CONFIG_ARCH_KS8695 is not set
154# CONFIG_ARCH_NS9XXX is not set
155# CONFIG_ARCH_LOKI is not set
156# CONFIG_ARCH_MV78XX0 is not set
157# CONFIG_ARCH_MXC is not set
158# CONFIG_ARCH_ORION5X is not set
159# CONFIG_ARCH_PNX4008 is not set
160# CONFIG_ARCH_PXA is not set
161# CONFIG_ARCH_RPC is not set
162# CONFIG_ARCH_SA1100 is not set
163# CONFIG_ARCH_S3C2410 is not set
164# CONFIG_ARCH_SHARK is not set
165# CONFIG_ARCH_LH7A40X is not set
166# CONFIG_ARCH_DAVINCI is not set
167CONFIG_ARCH_OMAP=y
168# CONFIG_ARCH_MSM7X00A is not set
169
170#
171# TI OMAP Implementations
172#
173CONFIG_ARCH_OMAP_OTG=y
174# CONFIG_ARCH_OMAP1 is not set
175# CONFIG_ARCH_OMAP2 is not set
176CONFIG_ARCH_OMAP3=y
177
178#
179# OMAP Feature Selections
180#
181# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
182# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
183# CONFIG_OMAP_RESET_CLOCKS is not set
184CONFIG_OMAP_MUX=y
185CONFIG_OMAP_MUX_DEBUG=y
186CONFIG_OMAP_MUX_WARNINGS=y
187CONFIG_OMAP_MCBSP=y
188# CONFIG_OMAP_MPU_TIMER is not set
189CONFIG_OMAP_32K_TIMER=y
190CONFIG_OMAP_32K_TIMER_HZ=128
191CONFIG_OMAP_DM_TIMER=y
192# CONFIG_OMAP_LL_DEBUG_UART1 is not set
193# CONFIG_OMAP_LL_DEBUG_UART2 is not set
194CONFIG_OMAP_LL_DEBUG_UART3=y
195CONFIG_OMAP_SERIAL_WAKE=y
196CONFIG_ARCH_OMAP34XX=y
197CONFIG_ARCH_OMAP3430=y
198
199#
200# OMAP Board Type
201#
202# CONFIG_MACH_OMAP3_BEAGLE is not set
203CONFIG_MACH_OMAP_LDP=y
204# CONFIG_MACH_OVERO is not set
205
206#
207# Boot options
208#
209
210#
211# Power management
212#
213
214#
215# Processor Type
216#
217CONFIG_CPU_32=y
218CONFIG_CPU_32v6K=y
219CONFIG_CPU_V7=y
220CONFIG_CPU_32v7=y
221CONFIG_CPU_ABRT_EV7=y
222CONFIG_CPU_PABRT_IFAR=y
223CONFIG_CPU_CACHE_V7=y
224CONFIG_CPU_CACHE_VIPT=y
225CONFIG_CPU_COPY_V6=y
226CONFIG_CPU_TLB_V7=y
227CONFIG_CPU_HAS_ASID=y
228CONFIG_CPU_CP15=y
229CONFIG_CPU_CP15_MMU=y
230
231#
232# Processor Features
233#
234CONFIG_ARM_THUMB=y
235# CONFIG_ARM_THUMBEE is not set
236# CONFIG_CPU_ICACHE_DISABLE is not set
237# CONFIG_CPU_DCACHE_DISABLE is not set
238# CONFIG_CPU_BPREDICT_DISABLE is not set
239CONFIG_HAS_TLS_REG=y
240# CONFIG_OUTER_CACHE is not set
241
242#
243# Bus support
244#
245# CONFIG_PCI_SYSCALL is not set
246# CONFIG_ARCH_SUPPORTS_MSI is not set
247# CONFIG_PCCARD is not set
248
249#
250# Kernel Features
251#
252CONFIG_TICK_ONESHOT=y
253CONFIG_NO_HZ=y
254CONFIG_HIGH_RES_TIMERS=y
255CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
256# CONFIG_PREEMPT is not set
257CONFIG_HZ=128
258CONFIG_AEABI=y
259CONFIG_OABI_COMPAT=y
260CONFIG_ARCH_FLATMEM_HAS_HOLES=y
261# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
262CONFIG_SELECT_MEMORY_MODEL=y
263CONFIG_FLATMEM_MANUAL=y
264# CONFIG_DISCONTIGMEM_MANUAL is not set
265# CONFIG_SPARSEMEM_MANUAL is not set
266CONFIG_FLATMEM=y
267CONFIG_FLAT_NODE_MEM_MAP=y
268# CONFIG_SPARSEMEM_STATIC is not set
269# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
270CONFIG_PAGEFLAGS_EXTENDED=y
271CONFIG_SPLIT_PTLOCK_CPUS=4
272# CONFIG_RESOURCES_64BIT is not set
273CONFIG_ZONE_DMA_FLAG=1
274CONFIG_BOUNCE=y
275CONFIG_VIRT_TO_BUS=y
276# CONFIG_LEDS is not set
277CONFIG_ALIGNMENT_TRAP=y
278
279#
280# Boot options
281#
282CONFIG_ZBOOT_ROM_TEXT=0x0
283CONFIG_ZBOOT_ROM_BSS=0x0
284CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
285# CONFIG_XIP_KERNEL is not set
286# CONFIG_KEXEC is not set
287
288#
289# CPU Frequency scaling
290#
291# CONFIG_CPU_FREQ is not set
292
293#
294# Floating point emulation
295#
296
297#
298# At least one emulation must be selected
299#
300CONFIG_FPE_NWFPE=y
301# CONFIG_FPE_NWFPE_XP is not set
302# CONFIG_FPE_FASTFPE is not set
303CONFIG_VFP=y
304CONFIG_VFPv3=y
305# CONFIG_NEON is not set
306
307#
308# Userspace binary formats
309#
310CONFIG_BINFMT_ELF=y
311# CONFIG_BINFMT_AOUT is not set
312CONFIG_BINFMT_MISC=y
313
314#
315# Power management options
316#
317# CONFIG_PM is not set
318CONFIG_ARCH_SUSPEND_POSSIBLE=y
319# CONFIG_NET is not set
320
321#
322# Device Drivers
323#
324
325#
326# Generic Driver Options
327#
328CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
329CONFIG_STANDALONE=y
330CONFIG_PREVENT_FIRMWARE_BUILD=y
331# CONFIG_FW_LOADER is not set
332# CONFIG_DEBUG_DRIVER is not set
333# CONFIG_DEBUG_DEVRES is not set
334# CONFIG_SYS_HYPERVISOR is not set
335# CONFIG_MTD is not set
336# CONFIG_PARPORT is not set
337CONFIG_BLK_DEV=y
338# CONFIG_BLK_DEV_COW_COMMON is not set
339CONFIG_BLK_DEV_LOOP=y
340# CONFIG_BLK_DEV_CRYPTOLOOP is not set
341CONFIG_BLK_DEV_RAM=y
342CONFIG_BLK_DEV_RAM_COUNT=16
343CONFIG_BLK_DEV_RAM_SIZE=16384
344# CONFIG_BLK_DEV_XIP is not set
345# CONFIG_CDROM_PKTCDVD is not set
346CONFIG_MISC_DEVICES=y
347# CONFIG_EEPROM_93CX6 is not set
348# CONFIG_ENCLOSURE_SERVICES is not set
349CONFIG_HAVE_IDE=y
350# CONFIG_IDE is not set
351
352#
353# SCSI device support
354#
355# CONFIG_RAID_ATTRS is not set
356CONFIG_SCSI=y
357CONFIG_SCSI_DMA=y
358# CONFIG_SCSI_TGT is not set
359# CONFIG_SCSI_NETLINK is not set
360CONFIG_SCSI_PROC_FS=y
361
362#
363# SCSI support type (disk, tape, CD-ROM)
364#
365CONFIG_BLK_DEV_SD=y
366# CONFIG_CHR_DEV_ST is not set
367# CONFIG_CHR_DEV_OSST is not set
368# CONFIG_BLK_DEV_SR is not set
369# CONFIG_CHR_DEV_SG is not set
370# CONFIG_CHR_DEV_SCH is not set
371
372#
373# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
374#
375# CONFIG_SCSI_MULTI_LUN is not set
376# CONFIG_SCSI_CONSTANTS is not set
377# CONFIG_SCSI_LOGGING is not set
378# CONFIG_SCSI_SCAN_ASYNC is not set
379CONFIG_SCSI_WAIT_SCAN=m
380
381#
382# SCSI Transports
383#
384# CONFIG_SCSI_SPI_ATTRS is not set
385# CONFIG_SCSI_FC_ATTRS is not set
386# CONFIG_SCSI_SAS_LIBSAS is not set
387# CONFIG_SCSI_SRP_ATTRS is not set
388CONFIG_SCSI_LOWLEVEL=y
389# CONFIG_SCSI_DEBUG is not set
390# CONFIG_SCSI_DH is not set
391# CONFIG_ATA is not set
392# CONFIG_MD is not set
393
394#
395# Input device support
396#
397CONFIG_INPUT=y
398# CONFIG_INPUT_FF_MEMLESS is not set
399# CONFIG_INPUT_POLLDEV is not set
400
401#
402# Userland interfaces
403#
404# CONFIG_INPUT_MOUSEDEV is not set
405# CONFIG_INPUT_JOYDEV is not set
406CONFIG_INPUT_EVDEV=y
407# CONFIG_INPUT_EVBUG is not set
408
409#
410# Input Device Drivers
411#
412# CONFIG_INPUT_KEYBOARD is not set
413# CONFIG_INPUT_MOUSE is not set
414# CONFIG_INPUT_JOYSTICK is not set
415# CONFIG_INPUT_TABLET is not set
416CONFIG_INPUT_TOUCHSCREEN=y
417CONFIG_TOUCHSCREEN_ADS7846=y
418# CONFIG_TOUCHSCREEN_FUJITSU is not set
419# CONFIG_TOUCHSCREEN_GUNZE is not set
420# CONFIG_TOUCHSCREEN_ELO is not set
421# CONFIG_TOUCHSCREEN_MTOUCH is not set
422# CONFIG_TOUCHSCREEN_INEXIO is not set
423# CONFIG_TOUCHSCREEN_MK712 is not set
424# CONFIG_TOUCHSCREEN_PENMOUNT is not set
425# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
426# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
427# CONFIG_TOUCHSCREEN_UCB1400 is not set
428# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
429# CONFIG_INPUT_MISC is not set
430
431#
432# Hardware I/O ports
433#
434# CONFIG_SERIO is not set
435# CONFIG_GAMEPORT is not set
436
437#
438# Character devices
439#
440CONFIG_VT=y
441CONFIG_CONSOLE_TRANSLATIONS=y
442CONFIG_VT_CONSOLE=y
443CONFIG_HW_CONSOLE=y
444# CONFIG_VT_HW_CONSOLE_BINDING is not set
445CONFIG_DEVKMEM=y
446# CONFIG_SERIAL_NONSTANDARD is not set
447
448#
449# Serial drivers
450#
451CONFIG_SERIAL_8250=y
452CONFIG_SERIAL_8250_CONSOLE=y
453CONFIG_SERIAL_8250_NR_UARTS=32
454CONFIG_SERIAL_8250_RUNTIME_UARTS=4
455CONFIG_SERIAL_8250_EXTENDED=y
456CONFIG_SERIAL_8250_MANY_PORTS=y
457CONFIG_SERIAL_8250_SHARE_IRQ=y
458CONFIG_SERIAL_8250_DETECT_IRQ=y
459CONFIG_SERIAL_8250_RSA=y
460
461#
462# Non-8250 serial port support
463#
464CONFIG_SERIAL_CORE=y
465CONFIG_SERIAL_CORE_CONSOLE=y
466CONFIG_UNIX98_PTYS=y
467# CONFIG_LEGACY_PTYS is not set
468# CONFIG_IPMI_HANDLER is not set
469CONFIG_HW_RANDOM=y
470# CONFIG_NVRAM is not set
471# CONFIG_R3964 is not set
472# CONFIG_RAW_DRIVER is not set
473# CONFIG_TCG_TPM is not set
474CONFIG_I2C=y
475CONFIG_I2C_BOARDINFO=y
476CONFIG_I2C_CHARDEV=y
477CONFIG_I2C_HELPER_AUTO=y
478
479#
480# I2C Hardware Bus support
481#
482
483#
484# I2C system bus drivers (mostly embedded / system-on-chip)
485#
486# CONFIG_I2C_GPIO is not set
487# CONFIG_I2C_OCORES is not set
488CONFIG_I2C_OMAP=y
489# CONFIG_I2C_SIMTEC is not set
490
491#
492# External I2C/SMBus adapter drivers
493#
494# CONFIG_I2C_PARPORT_LIGHT is not set
495# CONFIG_I2C_TAOS_EVM is not set
496
497#
498# Other I2C/SMBus bus drivers
499#
500# CONFIG_I2C_PCA_PLATFORM is not set
501# CONFIG_I2C_STUB is not set
502
503#
504# Miscellaneous I2C Chip support
505#
506# CONFIG_DS1682 is not set
507# CONFIG_AT24 is not set
508# CONFIG_SENSORS_EEPROM is not set
509# CONFIG_SENSORS_PCF8574 is not set
510# CONFIG_PCF8575 is not set
511# CONFIG_SENSORS_PCA9539 is not set
512# CONFIG_SENSORS_PCF8591 is not set
513# CONFIG_ISP1301_OMAP is not set
514# CONFIG_TPS65010 is not set
515# CONFIG_SENSORS_MAX6875 is not set
516# CONFIG_SENSORS_TSL2550 is not set
517# CONFIG_I2C_DEBUG_CORE is not set
518# CONFIG_I2C_DEBUG_ALGO is not set
519# CONFIG_I2C_DEBUG_BUS is not set
520# CONFIG_I2C_DEBUG_CHIP is not set
521CONFIG_SPI=y
522# CONFIG_SPI_DEBUG is not set
523CONFIG_SPI_MASTER=y
524
525#
526# SPI Master Controller Drivers
527#
528# CONFIG_SPI_BITBANG is not set
529CONFIG_SPI_OMAP24XX=y
530
531#
532# SPI Protocol Masters
533#
534# CONFIG_SPI_AT25 is not set
535# CONFIG_SPI_SPIDEV is not set
536# CONFIG_SPI_TLE62X0 is not set
537CONFIG_ARCH_REQUIRE_GPIOLIB=y
538CONFIG_GPIOLIB=y
539# CONFIG_DEBUG_GPIO is not set
540# CONFIG_GPIO_SYSFS is not set
541
542#
543# I2C GPIO expanders:
544#
545# CONFIG_GPIO_MAX732X is not set
546# CONFIG_GPIO_PCA953X is not set
547# CONFIG_GPIO_PCF857X is not set
548
549#
550# PCI GPIO expanders:
551#
552
553#
554# SPI GPIO expanders:
555#
556# CONFIG_GPIO_MAX7301 is not set
557# CONFIG_GPIO_MCP23S08 is not set
558CONFIG_W1=y
559
560#
561# 1-wire Bus Masters
562#
563# CONFIG_W1_MASTER_DS2482 is not set
564# CONFIG_W1_MASTER_DS1WM is not set
565# CONFIG_W1_MASTER_GPIO is not set
566
567#
568# 1-wire Slaves
569#
570# CONFIG_W1_SLAVE_THERM is not set
571# CONFIG_W1_SLAVE_SMEM is not set
572# CONFIG_W1_SLAVE_DS2433 is not set
573# CONFIG_W1_SLAVE_DS2760 is not set
574CONFIG_POWER_SUPPLY=y
575# CONFIG_POWER_SUPPLY_DEBUG is not set
576# CONFIG_PDA_POWER is not set
577# CONFIG_BATTERY_DS2760 is not set
578# CONFIG_HWMON is not set
579CONFIG_WATCHDOG=y
580CONFIG_WATCHDOG_NOWAYOUT=y
581
582#
583# Watchdog Device Drivers
584#
585# CONFIG_SOFT_WATCHDOG is not set
586
587#
588# Sonics Silicon Backplane
589#
590CONFIG_SSB_POSSIBLE=y
591# CONFIG_SSB is not set
592
593#
594# Multifunction device drivers
595#
596# CONFIG_MFD_CORE is not set
597# CONFIG_MFD_SM501 is not set
598# CONFIG_HTC_EGPIO is not set
599# CONFIG_HTC_PASIC3 is not set
600# CONFIG_MFD_TMIO is not set
601# CONFIG_MFD_T7L66XB is not set
602# CONFIG_MFD_TC6387XB is not set
603# CONFIG_MFD_TC6393XB is not set
604
605#
606# Multimedia devices
607#
608
609#
610# Multimedia core support
611#
612# CONFIG_VIDEO_DEV is not set
613# CONFIG_VIDEO_MEDIA is not set
614
615#
616# Multimedia drivers
617#
618CONFIG_DAB=y
619
620#
621# Graphics support
622#
623# CONFIG_VGASTATE is not set
624CONFIG_VIDEO_OUTPUT_CONTROL=m
625# CONFIG_FB is not set
626# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
627
628#
629# Display device support
630#
631# CONFIG_DISPLAY_SUPPORT is not set
632
633#
634# Console display driver support
635#
636# CONFIG_VGA_CONSOLE is not set
637CONFIG_DUMMY_CONSOLE=y
638CONFIG_SOUND=y
639CONFIG_SND=y
640# CONFIG_SND_SEQUENCER is not set
641# CONFIG_SND_MIXER_OSS is not set
642# CONFIG_SND_PCM_OSS is not set
643# CONFIG_SND_DYNAMIC_MINORS is not set
644CONFIG_SND_SUPPORT_OLD_API=y
645CONFIG_SND_VERBOSE_PROCFS=y
646# CONFIG_SND_VERBOSE_PRINTK is not set
647# CONFIG_SND_DEBUG is not set
648CONFIG_SND_DRIVERS=y
649# CONFIG_SND_DUMMY is not set
650# CONFIG_SND_MTPAV is not set
651# CONFIG_SND_SERIAL_U16550 is not set
652# CONFIG_SND_MPU401 is not set
653CONFIG_SND_ARM=y
654CONFIG_SND_SPI=y
655# CONFIG_SND_SOC is not set
656# CONFIG_SOUND_PRIME is not set
657CONFIG_HID_SUPPORT=y
658CONFIG_HID=y
659# CONFIG_HID_DEBUG is not set
660# CONFIG_HIDRAW is not set
661# CONFIG_USB_SUPPORT is not set
662CONFIG_MMC=y
663# CONFIG_MMC_DEBUG is not set
664# CONFIG_MMC_UNSAFE_RESUME is not set
665
666#
667# MMC/SD Card Drivers
668#
669CONFIG_MMC_BLOCK=y
670CONFIG_MMC_BLOCK_BOUNCE=y
671# CONFIG_SDIO_UART is not set
672# CONFIG_MMC_TEST is not set
673
674#
675# MMC/SD Host Controller Drivers
676#
677# CONFIG_MMC_SDHCI is not set
678# CONFIG_MMC_OMAP is not set
679# CONFIG_MMC_SPI is not set
680# CONFIG_NEW_LEDS is not set
681CONFIG_RTC_LIB=y
682CONFIG_RTC_CLASS=y
683CONFIG_RTC_HCTOSYS=y
684CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
685# CONFIG_RTC_DEBUG is not set
686
687#
688# RTC interfaces
689#
690CONFIG_RTC_INTF_SYSFS=y
691CONFIG_RTC_INTF_PROC=y
692CONFIG_RTC_INTF_DEV=y
693# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
694# CONFIG_RTC_DRV_TEST is not set
695
696#
697# I2C RTC drivers
698#
699# CONFIG_RTC_DRV_DS1307 is not set
700# CONFIG_RTC_DRV_DS1374 is not set
701# CONFIG_RTC_DRV_DS1672 is not set
702# CONFIG_RTC_DRV_MAX6900 is not set
703# CONFIG_RTC_DRV_RS5C372 is not set
704# CONFIG_RTC_DRV_ISL1208 is not set
705# CONFIG_RTC_DRV_X1205 is not set
706# CONFIG_RTC_DRV_PCF8563 is not set
707# CONFIG_RTC_DRV_PCF8583 is not set
708# CONFIG_RTC_DRV_M41T80 is not set
709# CONFIG_RTC_DRV_S35390A is not set
710# CONFIG_RTC_DRV_FM3130 is not set
711
712#
713# SPI RTC drivers
714#
715# CONFIG_RTC_DRV_M41T94 is not set
716# CONFIG_RTC_DRV_DS1305 is not set
717# CONFIG_RTC_DRV_MAX6902 is not set
718# CONFIG_RTC_DRV_R9701 is not set
719# CONFIG_RTC_DRV_RS5C348 is not set
720
721#
722# Platform RTC drivers
723#
724# CONFIG_RTC_DRV_CMOS is not set
725# CONFIG_RTC_DRV_DS1511 is not set
726# CONFIG_RTC_DRV_DS1553 is not set
727# CONFIG_RTC_DRV_DS1742 is not set
728# CONFIG_RTC_DRV_STK17TA8 is not set
729# CONFIG_RTC_DRV_M48T86 is not set
730# CONFIG_RTC_DRV_M48T59 is not set
731# CONFIG_RTC_DRV_V3020 is not set
732
733#
734# on-CPU RTC drivers
735#
736# CONFIG_DMADEVICES is not set
737
738#
739# Voltage and Current regulators
740#
741# CONFIG_REGULATOR is not set
742# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
743# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
744# CONFIG_REGULATOR_BQ24022 is not set
745# CONFIG_UIO is not set
746
747#
748# File systems
749#
750CONFIG_EXT2_FS=y
751# CONFIG_EXT2_FS_XATTR is not set
752# CONFIG_EXT2_FS_XIP is not set
753CONFIG_EXT3_FS=y
754# CONFIG_EXT3_FS_XATTR is not set
755# CONFIG_EXT4DEV_FS is not set
756CONFIG_JBD=y
757# CONFIG_REISERFS_FS is not set
758# CONFIG_JFS_FS is not set
759# CONFIG_FS_POSIX_ACL is not set
760# CONFIG_XFS_FS is not set
761CONFIG_DNOTIFY=y
762CONFIG_INOTIFY=y
763CONFIG_INOTIFY_USER=y
764CONFIG_QUOTA=y
765CONFIG_PRINT_QUOTA_WARNING=y
766# CONFIG_QFMT_V1 is not set
767CONFIG_QFMT_V2=y
768CONFIG_QUOTACTL=y
769# CONFIG_AUTOFS_FS is not set
770# CONFIG_AUTOFS4_FS is not set
771# CONFIG_FUSE_FS is not set
772
773#
774# CD-ROM/DVD Filesystems
775#
776# CONFIG_ISO9660_FS is not set
777# CONFIG_UDF_FS is not set
778
779#
780# DOS/FAT/NT Filesystems
781#
782CONFIG_FAT_FS=y
783CONFIG_MSDOS_FS=y
784CONFIG_VFAT_FS=y
785CONFIG_FAT_DEFAULT_CODEPAGE=437
786CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
787# CONFIG_NTFS_FS is not set
788
789#
790# Pseudo filesystems
791#
792CONFIG_PROC_FS=y
793CONFIG_PROC_SYSCTL=y
794CONFIG_SYSFS=y
795CONFIG_TMPFS=y
796# CONFIG_TMPFS_POSIX_ACL is not set
797# CONFIG_HUGETLB_PAGE is not set
798# CONFIG_CONFIGFS_FS is not set
799
800#
801# Miscellaneous filesystems
802#
803# CONFIG_ADFS_FS is not set
804# CONFIG_AFFS_FS is not set
805# CONFIG_HFS_FS is not set
806# CONFIG_HFSPLUS_FS is not set
807# CONFIG_BEFS_FS is not set
808# CONFIG_BFS_FS is not set
809# CONFIG_EFS_FS is not set
810# CONFIG_CRAMFS is not set
811# CONFIG_VXFS_FS is not set
812# CONFIG_MINIX_FS is not set
813# CONFIG_OMFS_FS is not set
814# CONFIG_HPFS_FS is not set
815# CONFIG_QNX4FS_FS is not set
816# CONFIG_ROMFS_FS is not set
817# CONFIG_SYSV_FS is not set
818# CONFIG_UFS_FS is not set
819
820#
821# Partition Types
822#
823CONFIG_PARTITION_ADVANCED=y
824# CONFIG_ACORN_PARTITION is not set
825# CONFIG_OSF_PARTITION is not set
826# CONFIG_AMIGA_PARTITION is not set
827# CONFIG_ATARI_PARTITION is not set
828# CONFIG_MAC_PARTITION is not set
829CONFIG_MSDOS_PARTITION=y
830# CONFIG_BSD_DISKLABEL is not set
831# CONFIG_MINIX_SUBPARTITION is not set
832# CONFIG_SOLARIS_X86_PARTITION is not set
833# CONFIG_UNIXWARE_DISKLABEL is not set
834# CONFIG_LDM_PARTITION is not set
835# CONFIG_SGI_PARTITION is not set
836# CONFIG_ULTRIX_PARTITION is not set
837# CONFIG_SUN_PARTITION is not set
838# CONFIG_KARMA_PARTITION is not set
839# CONFIG_EFI_PARTITION is not set
840# CONFIG_SYSV68_PARTITION is not set
841CONFIG_NLS=y
842CONFIG_NLS_DEFAULT="iso8859-1"
843CONFIG_NLS_CODEPAGE_437=y
844# CONFIG_NLS_CODEPAGE_737 is not set
845# CONFIG_NLS_CODEPAGE_775 is not set
846# CONFIG_NLS_CODEPAGE_850 is not set
847# CONFIG_NLS_CODEPAGE_852 is not set
848# CONFIG_NLS_CODEPAGE_855 is not set
849# CONFIG_NLS_CODEPAGE_857 is not set
850# CONFIG_NLS_CODEPAGE_860 is not set
851# CONFIG_NLS_CODEPAGE_861 is not set
852# CONFIG_NLS_CODEPAGE_862 is not set
853# CONFIG_NLS_CODEPAGE_863 is not set
854# CONFIG_NLS_CODEPAGE_864 is not set
855# CONFIG_NLS_CODEPAGE_865 is not set
856# CONFIG_NLS_CODEPAGE_866 is not set
857# CONFIG_NLS_CODEPAGE_869 is not set
858# CONFIG_NLS_CODEPAGE_936 is not set
859# CONFIG_NLS_CODEPAGE_950 is not set
860# CONFIG_NLS_CODEPAGE_932 is not set
861# CONFIG_NLS_CODEPAGE_949 is not set
862# CONFIG_NLS_CODEPAGE_874 is not set
863# CONFIG_NLS_ISO8859_8 is not set
864# CONFIG_NLS_CODEPAGE_1250 is not set
865# CONFIG_NLS_CODEPAGE_1251 is not set
866# CONFIG_NLS_ASCII is not set
867CONFIG_NLS_ISO8859_1=y
868# CONFIG_NLS_ISO8859_2 is not set
869# CONFIG_NLS_ISO8859_3 is not set
870# CONFIG_NLS_ISO8859_4 is not set
871# CONFIG_NLS_ISO8859_5 is not set
872# CONFIG_NLS_ISO8859_6 is not set
873# CONFIG_NLS_ISO8859_7 is not set
874# CONFIG_NLS_ISO8859_9 is not set
875# CONFIG_NLS_ISO8859_13 is not set
876# CONFIG_NLS_ISO8859_14 is not set
877# CONFIG_NLS_ISO8859_15 is not set
878# CONFIG_NLS_KOI8_R is not set
879# CONFIG_NLS_KOI8_U is not set
880# CONFIG_NLS_UTF8 is not set
881
882#
883# Kernel hacking
884#
885# CONFIG_PRINTK_TIME is not set
886CONFIG_ENABLE_WARN_DEPRECATED=y
887CONFIG_ENABLE_MUST_CHECK=y
888CONFIG_FRAME_WARN=1024
889CONFIG_MAGIC_SYSRQ=y
890# CONFIG_UNUSED_SYMBOLS is not set
891# CONFIG_DEBUG_FS is not set
892# CONFIG_HEADERS_CHECK is not set
893CONFIG_DEBUG_KERNEL=y
894# CONFIG_DEBUG_SHIRQ is not set
895CONFIG_DETECT_SOFTLOCKUP=y
896# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
897CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
898CONFIG_SCHED_DEBUG=y
899# CONFIG_SCHEDSTATS is not set
900# CONFIG_TIMER_STATS is not set
901# CONFIG_DEBUG_OBJECTS is not set
902# CONFIG_DEBUG_SLAB is not set
903# CONFIG_DEBUG_RT_MUTEXES is not set
904# CONFIG_RT_MUTEX_TESTER is not set
905# CONFIG_DEBUG_SPINLOCK is not set
906CONFIG_DEBUG_MUTEXES=y
907# CONFIG_DEBUG_LOCK_ALLOC is not set
908# CONFIG_PROVE_LOCKING is not set
909# CONFIG_LOCK_STAT is not set
910# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
911# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
912# CONFIG_DEBUG_KOBJECT is not set
913# CONFIG_DEBUG_BUGVERBOSE is not set
914CONFIG_DEBUG_INFO=y
915# CONFIG_DEBUG_VM is not set
916# CONFIG_DEBUG_WRITECOUNT is not set
917# CONFIG_DEBUG_MEMORY_INIT is not set
918# CONFIG_DEBUG_LIST is not set
919# CONFIG_DEBUG_SG is not set
920CONFIG_FRAME_POINTER=y
921# CONFIG_BOOT_PRINTK_DELAY is not set
922# CONFIG_RCU_TORTURE_TEST is not set
923# CONFIG_BACKTRACE_SELF_TEST is not set
924# CONFIG_FAULT_INJECTION is not set
925# CONFIG_LATENCYTOP is not set
926CONFIG_HAVE_FTRACE=y
927CONFIG_HAVE_DYNAMIC_FTRACE=y
928# CONFIG_FTRACE is not set
929# CONFIG_IRQSOFF_TRACER is not set
930# CONFIG_SCHED_TRACER is not set
931# CONFIG_CONTEXT_SWITCH_TRACER is not set
932# CONFIG_SAMPLES is not set
933CONFIG_HAVE_ARCH_KGDB=y
934# CONFIG_KGDB is not set
935# CONFIG_DEBUG_USER is not set
936# CONFIG_DEBUG_ERRORS is not set
937# CONFIG_DEBUG_STACK_USAGE is not set
938CONFIG_DEBUG_LL=y
939# CONFIG_DEBUG_ICEDCC is not set
940
941#
942# Security options
943#
944# CONFIG_KEYS is not set
945# CONFIG_SECURITY is not set
946# CONFIG_SECURITY_FILE_CAPABILITIES is not set
947CONFIG_CRYPTO=y
948
949#
950# Crypto core or helper
951#
952CONFIG_CRYPTO_ALGAPI=y
953CONFIG_CRYPTO_BLKCIPHER=y
954CONFIG_CRYPTO_MANAGER=y
955# CONFIG_CRYPTO_GF128MUL is not set
956# CONFIG_CRYPTO_NULL is not set
957# CONFIG_CRYPTO_CRYPTD is not set
958# CONFIG_CRYPTO_AUTHENC is not set
959# CONFIG_CRYPTO_TEST is not set
960
961#
962# Authenticated Encryption with Associated Data
963#
964# CONFIG_CRYPTO_CCM is not set
965# CONFIG_CRYPTO_GCM is not set
966# CONFIG_CRYPTO_SEQIV is not set
967
968#
969# Block modes
970#
971CONFIG_CRYPTO_CBC=y
972# CONFIG_CRYPTO_CTR is not set
973# CONFIG_CRYPTO_CTS is not set
974CONFIG_CRYPTO_ECB=m
975# CONFIG_CRYPTO_LRW is not set
976CONFIG_CRYPTO_PCBC=m
977# CONFIG_CRYPTO_XTS is not set
978
979#
980# Hash modes
981#
982# CONFIG_CRYPTO_HMAC is not set
983# CONFIG_CRYPTO_XCBC is not set
984
985#
986# Digest
987#
988# CONFIG_CRYPTO_CRC32C is not set
989# CONFIG_CRYPTO_MD4 is not set
990CONFIG_CRYPTO_MD5=y
991# CONFIG_CRYPTO_MICHAEL_MIC is not set
992# CONFIG_CRYPTO_RMD128 is not set
993# CONFIG_CRYPTO_RMD160 is not set
994# CONFIG_CRYPTO_RMD256 is not set
995# CONFIG_CRYPTO_RMD320 is not set
996# CONFIG_CRYPTO_SHA1 is not set
997# CONFIG_CRYPTO_SHA256 is not set
998# CONFIG_CRYPTO_SHA512 is not set
999# CONFIG_CRYPTO_TGR192 is not set
1000# CONFIG_CRYPTO_WP512 is not set
1001
1002#
1003# Ciphers
1004#
1005# CONFIG_CRYPTO_AES is not set
1006# CONFIG_CRYPTO_ANUBIS is not set
1007# CONFIG_CRYPTO_ARC4 is not set
1008# CONFIG_CRYPTO_BLOWFISH is not set
1009# CONFIG_CRYPTO_CAMELLIA is not set
1010# CONFIG_CRYPTO_CAST5 is not set
1011# CONFIG_CRYPTO_CAST6 is not set
1012CONFIG_CRYPTO_DES=y
1013# CONFIG_CRYPTO_FCRYPT is not set
1014# CONFIG_CRYPTO_KHAZAD is not set
1015# CONFIG_CRYPTO_SALSA20 is not set
1016# CONFIG_CRYPTO_SEED is not set
1017# CONFIG_CRYPTO_SERPENT is not set
1018# CONFIG_CRYPTO_TEA is not set
1019# CONFIG_CRYPTO_TWOFISH is not set
1020
1021#
1022# Compression
1023#
1024# CONFIG_CRYPTO_DEFLATE is not set
1025# CONFIG_CRYPTO_LZO is not set
1026CONFIG_CRYPTO_HW=y
1027
1028#
1029# Library routines
1030#
1031CONFIG_BITREVERSE=y
1032# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1033# CONFIG_GENERIC_FIND_NEXT_BIT is not set
1034CONFIG_CRC_CCITT=y
1035# CONFIG_CRC16 is not set
1036CONFIG_CRC_T10DIF=y
1037# CONFIG_CRC_ITU_T is not set
1038CONFIG_CRC32=y
1039# CONFIG_CRC7 is not set
1040CONFIG_LIBCRC32C=y
1041CONFIG_PLIST=y
1042CONFIG_HAS_IOMEM=y
1043CONFIG_HAS_IOPORT=y
1044CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/overo_defconfig b/arch/arm/configs/overo_defconfig
new file mode 100644
index 000000000000..49200967a153
--- /dev/null
+++ b/arch/arm/configs/overo_defconfig
@@ -0,0 +1,1885 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.27-rc8
4# Fri Oct 3 11:50:34 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
16CONFIG_LOCKDEP_SUPPORT=y
17CONFIG_TRACE_IRQFLAGS_SUPPORT=y
18CONFIG_HARDIRQS_SW_RESEND=y
19CONFIG_GENERIC_IRQ_PROBE=y
20CONFIG_RWSEM_GENERIC_SPINLOCK=y
21# CONFIG_ARCH_HAS_ILOG2_U32 is not set
22# CONFIG_ARCH_HAS_ILOG2_U64 is not set
23CONFIG_GENERIC_HWEIGHT=y
24CONFIG_GENERIC_CALIBRATE_DELAY=y
25CONFIG_ARCH_SUPPORTS_AOUT=y
26CONFIG_ZONE_DMA=y
27CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
28CONFIG_OPROFILE_ARMV7=y
29CONFIG_VECTORS_BASE=0xffff0000
30CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
31
32#
33# General setup
34#
35CONFIG_EXPERIMENTAL=y
36CONFIG_BROKEN_ON_SMP=y
37CONFIG_INIT_ENV_ARG_LIMIT=32
38CONFIG_LOCALVERSION=""
39CONFIG_LOCALVERSION_AUTO=y
40CONFIG_SWAP=y
41CONFIG_SYSVIPC=y
42CONFIG_SYSVIPC_SYSCTL=y
43# CONFIG_POSIX_MQUEUE is not set
44CONFIG_BSD_PROCESS_ACCT=y
45# CONFIG_BSD_PROCESS_ACCT_V3 is not set
46# CONFIG_TASKSTATS is not set
47# CONFIG_AUDIT is not set
48CONFIG_IKCONFIG=y
49CONFIG_IKCONFIG_PROC=y
50CONFIG_LOG_BUF_SHIFT=14
51# CONFIG_CGROUPS is not set
52CONFIG_GROUP_SCHED=y
53CONFIG_FAIR_GROUP_SCHED=y
54# CONFIG_RT_GROUP_SCHED is not set
55CONFIG_USER_SCHED=y
56# CONFIG_CGROUP_SCHED is not set
57CONFIG_SYSFS_DEPRECATED=y
58CONFIG_SYSFS_DEPRECATED_V2=y
59# CONFIG_RELAY is not set
60# CONFIG_NAMESPACES is not set
61CONFIG_BLK_DEV_INITRD=y
62CONFIG_INITRAMFS_SOURCE=""
63CONFIG_CC_OPTIMIZE_FOR_SIZE=y
64CONFIG_SYSCTL=y
65CONFIG_EMBEDDED=y
66CONFIG_UID16=y
67# CONFIG_SYSCTL_SYSCALL is not set
68CONFIG_KALLSYMS=y
69# CONFIG_KALLSYMS_ALL is not set
70# CONFIG_KALLSYMS_EXTRA_PASS is not set
71CONFIG_HOTPLUG=y
72CONFIG_PRINTK=y
73CONFIG_BUG=y
74# CONFIG_ELF_CORE is not set
75# CONFIG_COMPAT_BRK is not set
76CONFIG_BASE_FULL=y
77CONFIG_FUTEX=y
78CONFIG_ANON_INODES=y
79CONFIG_EPOLL=y
80CONFIG_SIGNALFD=y
81CONFIG_TIMERFD=y
82CONFIG_EVENTFD=y
83CONFIG_SHMEM=y
84CONFIG_VM_EVENT_COUNTERS=y
85CONFIG_SLUB_DEBUG=y
86# CONFIG_SLAB is not set
87CONFIG_SLUB=y
88# CONFIG_SLOB is not set
89CONFIG_PROFILING=y
90# CONFIG_MARKERS is not set
91CONFIG_OPROFILE=y
92CONFIG_HAVE_OPROFILE=y
93# CONFIG_KPROBES is not set
94# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
95# CONFIG_HAVE_IOREMAP_PROT is not set
96CONFIG_HAVE_KPROBES=y
97CONFIG_HAVE_KRETPROBES=y
98# CONFIG_HAVE_ARCH_TRACEHOOK is not set
99# CONFIG_HAVE_DMA_ATTRS is not set
100# CONFIG_USE_GENERIC_SMP_HELPERS is not set
101CONFIG_HAVE_CLK=y
102CONFIG_PROC_PAGE_MONITOR=y
103CONFIG_HAVE_GENERIC_DMA_COHERENT=y
104CONFIG_SLABINFO=y
105CONFIG_RT_MUTEXES=y
106# CONFIG_TINY_SHMEM is not set
107CONFIG_BASE_SMALL=0
108CONFIG_MODULES=y
109# CONFIG_MODULE_FORCE_LOAD is not set
110CONFIG_MODULE_UNLOAD=y
111CONFIG_MODULE_FORCE_UNLOAD=y
112CONFIG_MODVERSIONS=y
113CONFIG_MODULE_SRCVERSION_ALL=y
114CONFIG_KMOD=y
115CONFIG_BLOCK=y
116CONFIG_LBD=y
117# CONFIG_BLK_DEV_IO_TRACE is not set
118CONFIG_LSF=y
119# CONFIG_BLK_DEV_BSG is not set
120# CONFIG_BLK_DEV_INTEGRITY is not set
121
122#
123# IO Schedulers
124#
125CONFIG_IOSCHED_NOOP=y
126CONFIG_IOSCHED_AS=y
127CONFIG_IOSCHED_DEADLINE=y
128CONFIG_IOSCHED_CFQ=y
129# CONFIG_DEFAULT_AS is not set
130# CONFIG_DEFAULT_DEADLINE is not set
131CONFIG_DEFAULT_CFQ=y
132# CONFIG_DEFAULT_NOOP is not set
133CONFIG_DEFAULT_IOSCHED="cfq"
134CONFIG_CLASSIC_RCU=y
135
136#
137# System Type
138#
139# CONFIG_ARCH_AAEC2000 is not set
140# CONFIG_ARCH_INTEGRATOR is not set
141# CONFIG_ARCH_REALVIEW is not set
142# CONFIG_ARCH_VERSATILE is not set
143# CONFIG_ARCH_AT91 is not set
144# CONFIG_ARCH_CLPS7500 is not set
145# CONFIG_ARCH_CLPS711X is not set
146# CONFIG_ARCH_EBSA110 is not set
147# CONFIG_ARCH_EP93XX is not set
148# CONFIG_ARCH_FOOTBRIDGE is not set
149# CONFIG_ARCH_NETX is not set
150# CONFIG_ARCH_H720X is not set
151# CONFIG_ARCH_IMX is not set
152# CONFIG_ARCH_IOP13XX is not set
153# CONFIG_ARCH_IOP32X is not set
154# CONFIG_ARCH_IOP33X is not set
155# CONFIG_ARCH_IXP23XX is not set
156# CONFIG_ARCH_IXP2000 is not set
157# CONFIG_ARCH_IXP4XX is not set
158# CONFIG_ARCH_L7200 is not set
159# CONFIG_ARCH_KIRKWOOD is not set
160# CONFIG_ARCH_KS8695 is not set
161# CONFIG_ARCH_NS9XXX is not set
162# CONFIG_ARCH_LOKI is not set
163# CONFIG_ARCH_MV78XX0 is not set
164# CONFIG_ARCH_MXC is not set
165# CONFIG_ARCH_ORION5X is not set
166# CONFIG_ARCH_PNX4008 is not set
167# CONFIG_ARCH_PXA is not set
168# CONFIG_ARCH_RPC is not set
169# CONFIG_ARCH_SA1100 is not set
170# CONFIG_ARCH_S3C2410 is not set
171# CONFIG_ARCH_SHARK is not set
172# CONFIG_ARCH_LH7A40X is not set
173# CONFIG_ARCH_DAVINCI is not set
174CONFIG_ARCH_OMAP=y
175# CONFIG_ARCH_MSM7X00A is not set
176
177#
178# TI OMAP Implementations
179#
180CONFIG_ARCH_OMAP_OTG=y
181# CONFIG_ARCH_OMAP1 is not set
182# CONFIG_ARCH_OMAP2 is not set
183CONFIG_ARCH_OMAP3=y
184
185#
186# OMAP Feature Selections
187#
188# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
189# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
190# CONFIG_OMAP_RESET_CLOCKS is not set
191# CONFIG_OMAP_MUX is not set
192CONFIG_OMAP_MCBSP=y
193# CONFIG_OMAP_MPU_TIMER is not set
194CONFIG_OMAP_32K_TIMER=y
195CONFIG_OMAP_32K_TIMER_HZ=128
196CONFIG_OMAP_DM_TIMER=y
197# CONFIG_OMAP_LL_DEBUG_UART1 is not set
198# CONFIG_OMAP_LL_DEBUG_UART2 is not set
199CONFIG_OMAP_LL_DEBUG_UART3=y
200CONFIG_ARCH_OMAP34XX=y
201CONFIG_ARCH_OMAP3430=y
202
203#
204# OMAP Board Type
205#
206# CONFIG_MACH_OMAP3_BEAGLE is not set
207CONFIG_MACH_OVERO=y
208
209#
210# Boot options
211#
212
213#
214# Power management
215#
216
217#
218# Processor Type
219#
220CONFIG_CPU_32=y
221CONFIG_CPU_32v6K=y
222CONFIG_CPU_V7=y
223CONFIG_CPU_32v7=y
224CONFIG_CPU_ABRT_EV7=y
225CONFIG_CPU_PABRT_IFAR=y
226CONFIG_CPU_CACHE_V7=y
227CONFIG_CPU_CACHE_VIPT=y
228CONFIG_CPU_COPY_V6=y
229CONFIG_CPU_TLB_V7=y
230CONFIG_CPU_HAS_ASID=y
231CONFIG_CPU_CP15=y
232CONFIG_CPU_CP15_MMU=y
233
234#
235# Processor Features
236#
237CONFIG_ARM_THUMB=y
238CONFIG_ARM_THUMBEE=y
239# CONFIG_CPU_ICACHE_DISABLE is not set
240# CONFIG_CPU_DCACHE_DISABLE is not set
241# CONFIG_CPU_BPREDICT_DISABLE is not set
242CONFIG_HAS_TLS_REG=y
243# CONFIG_OUTER_CACHE is not set
244
245#
246# Bus support
247#
248# CONFIG_PCI_SYSCALL is not set
249# CONFIG_ARCH_SUPPORTS_MSI is not set
250# CONFIG_PCCARD is not set
251
252#
253# Kernel Features
254#
255CONFIG_TICK_ONESHOT=y
256CONFIG_NO_HZ=y
257CONFIG_HIGH_RES_TIMERS=y
258CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
259CONFIG_VMSPLIT_3G=y
260# CONFIG_VMSPLIT_2G is not set
261# CONFIG_VMSPLIT_1G is not set
262CONFIG_PAGE_OFFSET=0xC0000000
263# CONFIG_PREEMPT is not set
264CONFIG_HZ=128
265CONFIG_AEABI=y
266# CONFIG_OABI_COMPAT is not set
267CONFIG_ARCH_FLATMEM_HAS_HOLES=y
268# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
269CONFIG_SELECT_MEMORY_MODEL=y
270CONFIG_FLATMEM_MANUAL=y
271# CONFIG_DISCONTIGMEM_MANUAL is not set
272# CONFIG_SPARSEMEM_MANUAL is not set
273CONFIG_FLATMEM=y
274CONFIG_FLAT_NODE_MEM_MAP=y
275# CONFIG_SPARSEMEM_STATIC is not set
276# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
277CONFIG_PAGEFLAGS_EXTENDED=y
278CONFIG_SPLIT_PTLOCK_CPUS=4
279# CONFIG_RESOURCES_64BIT is not set
280CONFIG_ZONE_DMA_FLAG=1
281CONFIG_BOUNCE=y
282CONFIG_VIRT_TO_BUS=y
283CONFIG_LEDS=y
284CONFIG_ALIGNMENT_TRAP=y
285
286#
287# Boot options
288#
289CONFIG_ZBOOT_ROM_TEXT=0x0
290CONFIG_ZBOOT_ROM_BSS=0x0
291CONFIG_CMDLINE=" debug "
292# CONFIG_XIP_KERNEL is not set
293CONFIG_KEXEC=y
294CONFIG_ATAGS_PROC=y
295
296#
297# CPU Power Management
298#
299CONFIG_CPU_FREQ=y
300CONFIG_CPU_FREQ_TABLE=y
301# CONFIG_CPU_FREQ_DEBUG is not set
302CONFIG_CPU_FREQ_STAT=y
303CONFIG_CPU_FREQ_STAT_DETAILS=y
304CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
305# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
306# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
307# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
308# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
309CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
310# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
311CONFIG_CPU_FREQ_GOV_USERSPACE=y
312CONFIG_CPU_FREQ_GOV_ONDEMAND=y
313# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
314# CONFIG_CPU_IDLE is not set
315
316#
317# Floating point emulation
318#
319
320#
321# At least one emulation must be selected
322#
323CONFIG_VFP=y
324CONFIG_VFPv3=y
325CONFIG_NEON=y
326
327#
328# Userspace binary formats
329#
330CONFIG_BINFMT_ELF=y
331CONFIG_BINFMT_AOUT=m
332CONFIG_BINFMT_MISC=y
333
334#
335# Power management options
336#
337# CONFIG_PM is not set
338CONFIG_ARCH_SUSPEND_POSSIBLE=y
339CONFIG_NET=y
340
341#
342# Networking options
343#
344CONFIG_PACKET=y
345CONFIG_PACKET_MMAP=y
346CONFIG_UNIX=y
347CONFIG_XFRM=y
348# CONFIG_XFRM_USER is not set
349# CONFIG_XFRM_SUB_POLICY is not set
350# CONFIG_XFRM_MIGRATE is not set
351# CONFIG_XFRM_STATISTICS is not set
352CONFIG_NET_KEY=y
353# CONFIG_NET_KEY_MIGRATE is not set
354CONFIG_INET=y
355# CONFIG_IP_MULTICAST is not set
356# CONFIG_IP_ADVANCED_ROUTER is not set
357CONFIG_IP_FIB_HASH=y
358CONFIG_IP_PNP=y
359CONFIG_IP_PNP_DHCP=y
360CONFIG_IP_PNP_BOOTP=y
361CONFIG_IP_PNP_RARP=y
362# CONFIG_NET_IPIP is not set
363# CONFIG_NET_IPGRE is not set
364# CONFIG_ARPD is not set
365# CONFIG_SYN_COOKIES is not set
366# CONFIG_INET_AH is not set
367# CONFIG_INET_ESP is not set
368# CONFIG_INET_IPCOMP is not set
369# CONFIG_INET_XFRM_TUNNEL is not set
370CONFIG_INET_TUNNEL=m
371CONFIG_INET_XFRM_MODE_TRANSPORT=y
372CONFIG_INET_XFRM_MODE_TUNNEL=y
373CONFIG_INET_XFRM_MODE_BEET=y
374# CONFIG_INET_LRO is not set
375CONFIG_INET_DIAG=y
376CONFIG_INET_TCP_DIAG=y
377# CONFIG_TCP_CONG_ADVANCED is not set
378CONFIG_TCP_CONG_CUBIC=y
379CONFIG_DEFAULT_TCP_CONG="cubic"
380# CONFIG_TCP_MD5SIG is not set
381CONFIG_IPV6=m
382# CONFIG_IPV6_PRIVACY is not set
383# CONFIG_IPV6_ROUTER_PREF is not set
384# CONFIG_IPV6_OPTIMISTIC_DAD is not set
385# CONFIG_INET6_AH is not set
386# CONFIG_INET6_ESP is not set
387# CONFIG_INET6_IPCOMP is not set
388# CONFIG_IPV6_MIP6 is not set
389# CONFIG_INET6_XFRM_TUNNEL is not set
390# CONFIG_INET6_TUNNEL is not set
391CONFIG_INET6_XFRM_MODE_TRANSPORT=m
392CONFIG_INET6_XFRM_MODE_TUNNEL=m
393CONFIG_INET6_XFRM_MODE_BEET=m
394# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
395CONFIG_IPV6_SIT=m
396CONFIG_IPV6_NDISC_NODETYPE=y
397# CONFIG_IPV6_TUNNEL is not set
398# CONFIG_IPV6_MULTIPLE_TABLES is not set
399# CONFIG_IPV6_MROUTE is not set
400# CONFIG_NETWORK_SECMARK is not set
401# CONFIG_NETFILTER is not set
402# CONFIG_IP_DCCP is not set
403# CONFIG_IP_SCTP is not set
404# CONFIG_TIPC is not set
405# CONFIG_ATM is not set
406# CONFIG_BRIDGE is not set
407# CONFIG_VLAN_8021Q is not set
408# CONFIG_DECNET is not set
409# CONFIG_LLC2 is not set
410# CONFIG_IPX is not set
411# CONFIG_ATALK is not set
412# CONFIG_X25 is not set
413# CONFIG_LAPB is not set
414# CONFIG_ECONET is not set
415# CONFIG_WAN_ROUTER is not set
416# CONFIG_NET_SCHED is not set
417
418#
419# Network testing
420#
421# CONFIG_NET_PKTGEN is not set
422# CONFIG_HAMRADIO is not set
423# CONFIG_CAN is not set
424# CONFIG_IRDA is not set
425CONFIG_BT=y
426CONFIG_BT_L2CAP=y
427CONFIG_BT_SCO=y
428CONFIG_BT_RFCOMM=y
429CONFIG_BT_RFCOMM_TTY=y
430CONFIG_BT_BNEP=y
431CONFIG_BT_BNEP_MC_FILTER=y
432CONFIG_BT_BNEP_PROTO_FILTER=y
433CONFIG_BT_HIDP=y
434
435#
436# Bluetooth device drivers
437#
438CONFIG_BT_HCIUSB=m
439CONFIG_BT_HCIUSB_SCO=y
440# CONFIG_BT_HCIBTUSB is not set
441# CONFIG_BT_HCIBTSDIO is not set
442CONFIG_BT_HCIUART=y
443CONFIG_BT_HCIUART_H4=y
444CONFIG_BT_HCIUART_BCSP=y
445# CONFIG_BT_HCIUART_LL is not set
446CONFIG_BT_HCIBCM203X=y
447CONFIG_BT_HCIBPA10X=y
448# CONFIG_BT_HCIBFUSB is not set
449# CONFIG_BT_HCIVHCI is not set
450# CONFIG_AF_RXRPC is not set
451
452#
453# Wireless
454#
455CONFIG_CFG80211=y
456CONFIG_NL80211=y
457CONFIG_WIRELESS_EXT=y
458CONFIG_WIRELESS_EXT_SYSFS=y
459CONFIG_MAC80211=y
460
461#
462# Rate control algorithm selection
463#
464CONFIG_MAC80211_RC_PID=y
465CONFIG_MAC80211_RC_DEFAULT_PID=y
466CONFIG_MAC80211_RC_DEFAULT="pid"
467# CONFIG_MAC80211_MESH is not set
468CONFIG_MAC80211_LEDS=y
469# CONFIG_MAC80211_DEBUGFS is not set
470# CONFIG_MAC80211_DEBUG_MENU is not set
471CONFIG_IEEE80211=y
472# CONFIG_IEEE80211_DEBUG is not set
473CONFIG_IEEE80211_CRYPT_WEP=y
474CONFIG_IEEE80211_CRYPT_CCMP=y
475CONFIG_IEEE80211_CRYPT_TKIP=y
476# CONFIG_RFKILL is not set
477# CONFIG_NET_9P is not set
478
479#
480# Device Drivers
481#
482
483#
484# Generic Driver Options
485#
486CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
487CONFIG_STANDALONE=y
488CONFIG_PREVENT_FIRMWARE_BUILD=y
489CONFIG_FW_LOADER=y
490CONFIG_FIRMWARE_IN_KERNEL=y
491CONFIG_EXTRA_FIRMWARE=""
492# CONFIG_DEBUG_DRIVER is not set
493# CONFIG_DEBUG_DEVRES is not set
494# CONFIG_SYS_HYPERVISOR is not set
495# CONFIG_CONNECTOR is not set
496CONFIG_MTD=y
497# CONFIG_MTD_DEBUG is not set
498CONFIG_MTD_CONCAT=y
499CONFIG_MTD_PARTITIONS=y
500# CONFIG_MTD_REDBOOT_PARTS is not set
501# CONFIG_MTD_CMDLINE_PARTS is not set
502# CONFIG_MTD_AFS_PARTS is not set
503# CONFIG_MTD_AR7_PARTS is not set
504
505#
506# User Modules And Translation Layers
507#
508CONFIG_MTD_CHAR=y
509CONFIG_MTD_BLKDEVS=y
510CONFIG_MTD_BLOCK=y
511# CONFIG_FTL is not set
512# CONFIG_NFTL is not set
513# CONFIG_INFTL is not set
514# CONFIG_RFD_FTL is not set
515# CONFIG_SSFDC is not set
516# CONFIG_MTD_OOPS is not set
517
518#
519# RAM/ROM/Flash chip drivers
520#
521# CONFIG_MTD_CFI is not set
522# CONFIG_MTD_JEDECPROBE is not set
523CONFIG_MTD_MAP_BANK_WIDTH_1=y
524CONFIG_MTD_MAP_BANK_WIDTH_2=y
525CONFIG_MTD_MAP_BANK_WIDTH_4=y
526# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
527# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
528# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
529CONFIG_MTD_CFI_I1=y
530CONFIG_MTD_CFI_I2=y
531# CONFIG_MTD_CFI_I4 is not set
532# CONFIG_MTD_CFI_I8 is not set
533# CONFIG_MTD_RAM is not set
534# CONFIG_MTD_ROM is not set
535# CONFIG_MTD_ABSENT is not set
536
537#
538# Mapping drivers for chip access
539#
540# CONFIG_MTD_COMPLEX_MAPPINGS is not set
541# CONFIG_MTD_PLATRAM is not set
542
543#
544# Self-contained MTD device drivers
545#
546# CONFIG_MTD_DATAFLASH is not set
547# CONFIG_MTD_M25P80 is not set
548# CONFIG_MTD_SLRAM is not set
549# CONFIG_MTD_PHRAM is not set
550# CONFIG_MTD_MTDRAM is not set
551# CONFIG_MTD_BLOCK2MTD is not set
552
553#
554# Disk-On-Chip Device Drivers
555#
556# CONFIG_MTD_DOC2000 is not set
557# CONFIG_MTD_DOC2001 is not set
558# CONFIG_MTD_DOC2001PLUS is not set
559CONFIG_MTD_NAND=y
560# CONFIG_MTD_NAND_VERIFY_WRITE is not set
561# CONFIG_MTD_NAND_ECC_SMC is not set
562# CONFIG_MTD_NAND_MUSEUM_IDS is not set
563CONFIG_MTD_NAND_IDS=y
564# CONFIG_MTD_NAND_DISKONCHIP is not set
565# CONFIG_MTD_NAND_NANDSIM is not set
566# CONFIG_MTD_NAND_PLATFORM is not set
567# CONFIG_MTD_ALAUDA is not set
568# CONFIG_MTD_ONENAND is not set
569
570#
571# UBI - Unsorted block images
572#
573# CONFIG_MTD_UBI is not set
574# CONFIG_PARPORT is not set
575CONFIG_BLK_DEV=y
576# CONFIG_BLK_DEV_COW_COMMON is not set
577CONFIG_BLK_DEV_LOOP=y
578CONFIG_BLK_DEV_CRYPTOLOOP=m
579# CONFIG_BLK_DEV_NBD is not set
580# CONFIG_BLK_DEV_UB is not set
581CONFIG_BLK_DEV_RAM=y
582CONFIG_BLK_DEV_RAM_COUNT=16
583CONFIG_BLK_DEV_RAM_SIZE=16384
584# CONFIG_BLK_DEV_XIP is not set
585CONFIG_CDROM_PKTCDVD=m
586CONFIG_CDROM_PKTCDVD_BUFFERS=8
587# CONFIG_CDROM_PKTCDVD_WCACHE is not set
588# CONFIG_ATA_OVER_ETH is not set
589CONFIG_MISC_DEVICES=y
590CONFIG_EEPROM_93CX6=m
591# CONFIG_ENCLOSURE_SERVICES is not set
592CONFIG_HAVE_IDE=y
593# CONFIG_IDE is not set
594
595#
596# SCSI device support
597#
598CONFIG_RAID_ATTRS=m
599CONFIG_SCSI=y
600CONFIG_SCSI_DMA=y
601# CONFIG_SCSI_TGT is not set
602# CONFIG_SCSI_NETLINK is not set
603CONFIG_SCSI_PROC_FS=y
604
605#
606# SCSI support type (disk, tape, CD-ROM)
607#
608CONFIG_BLK_DEV_SD=y
609# CONFIG_CHR_DEV_ST is not set
610# CONFIG_CHR_DEV_OSST is not set
611# CONFIG_BLK_DEV_SR is not set
612CONFIG_CHR_DEV_SG=m
613# CONFIG_CHR_DEV_SCH is not set
614
615#
616# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
617#
618CONFIG_SCSI_MULTI_LUN=y
619# CONFIG_SCSI_CONSTANTS is not set
620# CONFIG_SCSI_LOGGING is not set
621# CONFIG_SCSI_SCAN_ASYNC is not set
622CONFIG_SCSI_WAIT_SCAN=m
623
624#
625# SCSI Transports
626#
627# CONFIG_SCSI_SPI_ATTRS is not set
628# CONFIG_SCSI_FC_ATTRS is not set
629# CONFIG_SCSI_ISCSI_ATTRS is not set
630# CONFIG_SCSI_SAS_LIBSAS is not set
631# CONFIG_SCSI_SRP_ATTRS is not set
632CONFIG_SCSI_LOWLEVEL=y
633# CONFIG_ISCSI_TCP is not set
634# CONFIG_SCSI_DEBUG is not set
635# CONFIG_SCSI_DH is not set
636# CONFIG_ATA is not set
637CONFIG_MD=y
638CONFIG_BLK_DEV_MD=m
639CONFIG_MD_LINEAR=m
640CONFIG_MD_RAID0=m
641CONFIG_MD_RAID1=m
642CONFIG_MD_RAID10=m
643CONFIG_MD_RAID456=m
644CONFIG_MD_RAID5_RESHAPE=y
645CONFIG_MD_MULTIPATH=m
646CONFIG_MD_FAULTY=m
647CONFIG_BLK_DEV_DM=m
648# CONFIG_DM_DEBUG is not set
649CONFIG_DM_CRYPT=m
650CONFIG_DM_SNAPSHOT=m
651CONFIG_DM_MIRROR=m
652CONFIG_DM_ZERO=m
653CONFIG_DM_MULTIPATH=m
654CONFIG_DM_DELAY=m
655# CONFIG_DM_UEVENT is not set
656CONFIG_NETDEVICES=y
657CONFIG_DUMMY=m
658# CONFIG_BONDING is not set
659# CONFIG_MACVLAN is not set
660# CONFIG_EQUALIZER is not set
661CONFIG_TUN=m
662# CONFIG_VETH is not set
663# CONFIG_NET_ETHERNET is not set
664CONFIG_MII=y
665# CONFIG_NETDEV_1000 is not set
666# CONFIG_NETDEV_10000 is not set
667
668#
669# Wireless LAN
670#
671# CONFIG_WLAN_PRE80211 is not set
672CONFIG_WLAN_80211=y
673CONFIG_LIBERTAS=y
674CONFIG_LIBERTAS_USB=y
675CONFIG_LIBERTAS_SDIO=y
676CONFIG_LIBERTAS_DEBUG=y
677CONFIG_USB_ZD1201=m
678# CONFIG_USB_NET_RNDIS_WLAN is not set
679CONFIG_RTL8187=m
680# CONFIG_MAC80211_HWSIM is not set
681CONFIG_P54_COMMON=m
682CONFIG_P54_USB=m
683# CONFIG_IWLWIFI_LEDS is not set
684CONFIG_HOSTAP=m
685CONFIG_HOSTAP_FIRMWARE=y
686CONFIG_HOSTAP_FIRMWARE_NVRAM=y
687# CONFIG_B43 is not set
688# CONFIG_B43LEGACY is not set
689# CONFIG_ZD1211RW is not set
690# CONFIG_RT2X00 is not set
691
692#
693# USB Network Adapters
694#
695CONFIG_USB_CATC=m
696CONFIG_USB_KAWETH=m
697CONFIG_USB_PEGASUS=m
698CONFIG_USB_RTL8150=m
699CONFIG_USB_USBNET=y
700CONFIG_USB_NET_AX8817X=y
701CONFIG_USB_NET_CDCETHER=y
702CONFIG_USB_NET_DM9601=m
703CONFIG_USB_NET_GL620A=m
704CONFIG_USB_NET_NET1080=m
705CONFIG_USB_NET_PLUSB=m
706CONFIG_USB_NET_MCS7830=m
707CONFIG_USB_NET_RNDIS_HOST=m
708CONFIG_USB_NET_CDC_SUBSET=m
709CONFIG_USB_ALI_M5632=y
710CONFIG_USB_AN2720=y
711CONFIG_USB_BELKIN=y
712CONFIG_USB_ARMLINUX=y
713CONFIG_USB_EPSON2888=y
714CONFIG_USB_KC2190=y
715CONFIG_USB_NET_ZAURUS=m
716# CONFIG_WAN is not set
717CONFIG_PPP=m
718# CONFIG_PPP_MULTILINK is not set
719# CONFIG_PPP_FILTER is not set
720CONFIG_PPP_ASYNC=m
721CONFIG_PPP_SYNC_TTY=m
722CONFIG_PPP_DEFLATE=m
723CONFIG_PPP_BSDCOMP=m
724CONFIG_PPP_MPPE=m
725CONFIG_PPPOE=m
726# CONFIG_PPPOL2TP is not set
727# CONFIG_SLIP is not set
728CONFIG_SLHC=m
729# CONFIG_NETCONSOLE is not set
730# CONFIG_NETPOLL is not set
731# CONFIG_NET_POLL_CONTROLLER is not set
732# CONFIG_ISDN is not set
733
734#
735# Input device support
736#
737CONFIG_INPUT=y
738# CONFIG_INPUT_FF_MEMLESS is not set
739# CONFIG_INPUT_POLLDEV is not set
740
741#
742# Userland interfaces
743#
744CONFIG_INPUT_MOUSEDEV=y
745CONFIG_INPUT_MOUSEDEV_PSAUX=y
746CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
747CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
748# CONFIG_INPUT_JOYDEV is not set
749CONFIG_INPUT_EVDEV=y
750# CONFIG_INPUT_EVBUG is not set
751
752#
753# Input Device Drivers
754#
755CONFIG_INPUT_KEYBOARD=y
756# CONFIG_KEYBOARD_ATKBD is not set
757# CONFIG_KEYBOARD_SUNKBD is not set
758# CONFIG_KEYBOARD_LKKBD is not set
759# CONFIG_KEYBOARD_XTKBD is not set
760# CONFIG_KEYBOARD_NEWTON is not set
761# CONFIG_KEYBOARD_STOWAWAY is not set
762# CONFIG_KEYBOARD_GPIO is not set
763CONFIG_INPUT_MOUSE=y
764CONFIG_MOUSE_PS2=y
765CONFIG_MOUSE_PS2_ALPS=y
766CONFIG_MOUSE_PS2_LOGIPS2PP=y
767CONFIG_MOUSE_PS2_SYNAPTICS=y
768CONFIG_MOUSE_PS2_LIFEBOOK=y
769CONFIG_MOUSE_PS2_TRACKPOINT=y
770# CONFIG_MOUSE_PS2_TOUCHKIT is not set
771# CONFIG_MOUSE_SERIAL is not set
772# CONFIG_MOUSE_APPLETOUCH is not set
773# CONFIG_MOUSE_BCM5974 is not set
774# CONFIG_MOUSE_VSXXXAA is not set
775# CONFIG_MOUSE_GPIO is not set
776# CONFIG_INPUT_JOYSTICK is not set
777# CONFIG_INPUT_TABLET is not set
778# CONFIG_INPUT_TOUCHSCREEN is not set
779# CONFIG_INPUT_MISC is not set
780
781#
782# Hardware I/O ports
783#
784CONFIG_SERIO=y
785CONFIG_SERIO_SERPORT=y
786CONFIG_SERIO_LIBPS2=y
787# CONFIG_SERIO_RAW is not set
788# CONFIG_GAMEPORT is not set
789
790#
791# Character devices
792#
793CONFIG_VT=y
794CONFIG_CONSOLE_TRANSLATIONS=y
795CONFIG_VT_CONSOLE=y
796CONFIG_HW_CONSOLE=y
797CONFIG_VT_HW_CONSOLE_BINDING=y
798CONFIG_DEVKMEM=y
799# CONFIG_SERIAL_NONSTANDARD is not set
800
801#
802# Serial drivers
803#
804CONFIG_SERIAL_8250=y
805CONFIG_SERIAL_8250_CONSOLE=y
806CONFIG_SERIAL_8250_NR_UARTS=32
807CONFIG_SERIAL_8250_RUNTIME_UARTS=4
808CONFIG_SERIAL_8250_EXTENDED=y
809CONFIG_SERIAL_8250_MANY_PORTS=y
810CONFIG_SERIAL_8250_SHARE_IRQ=y
811CONFIG_SERIAL_8250_DETECT_IRQ=y
812CONFIG_SERIAL_8250_RSA=y
813
814#
815# Non-8250 serial port support
816#
817CONFIG_SERIAL_CORE=y
818CONFIG_SERIAL_CORE_CONSOLE=y
819CONFIG_UNIX98_PTYS=y
820# CONFIG_LEGACY_PTYS is not set
821# CONFIG_IPMI_HANDLER is not set
822CONFIG_HW_RANDOM=y
823# CONFIG_NVRAM is not set
824# CONFIG_R3964 is not set
825# CONFIG_RAW_DRIVER is not set
826# CONFIG_TCG_TPM is not set
827CONFIG_I2C=y
828CONFIG_I2C_BOARDINFO=y
829CONFIG_I2C_CHARDEV=y
830CONFIG_I2C_HELPER_AUTO=y
831
832#
833# I2C Hardware Bus support
834#
835
836#
837# I2C system bus drivers (mostly embedded / system-on-chip)
838#
839# CONFIG_I2C_GPIO is not set
840# CONFIG_I2C_OCORES is not set
841CONFIG_I2C_OMAP=y
842# CONFIG_I2C_SIMTEC is not set
843
844#
845# External I2C/SMBus adapter drivers
846#
847# CONFIG_I2C_PARPORT_LIGHT is not set
848# CONFIG_I2C_TAOS_EVM is not set
849# CONFIG_I2C_TINY_USB is not set
850
851#
852# Other I2C/SMBus bus drivers
853#
854# CONFIG_I2C_PCA_PLATFORM is not set
855# CONFIG_I2C_STUB is not set
856
857#
858# Miscellaneous I2C Chip support
859#
860# CONFIG_DS1682 is not set
861# CONFIG_AT24 is not set
862CONFIG_SENSORS_EEPROM=y
863# CONFIG_SENSORS_PCF8574 is not set
864# CONFIG_PCF8575 is not set
865# CONFIG_SENSORS_PCA9539 is not set
866# CONFIG_SENSORS_PCF8591 is not set
867# CONFIG_ISP1301_OMAP is not set
868# CONFIG_TPS65010 is not set
869# CONFIG_SENSORS_MAX6875 is not set
870# CONFIG_SENSORS_TSL2550 is not set
871# CONFIG_I2C_DEBUG_CORE is not set
872# CONFIG_I2C_DEBUG_ALGO is not set
873# CONFIG_I2C_DEBUG_BUS is not set
874# CONFIG_I2C_DEBUG_CHIP is not set
875CONFIG_SPI=y
876# CONFIG_SPI_DEBUG is not set
877CONFIG_SPI_MASTER=y
878
879#
880# SPI Master Controller Drivers
881#
882# CONFIG_SPI_BITBANG is not set
883CONFIG_SPI_OMAP24XX=y
884
885#
886# SPI Protocol Masters
887#
888# CONFIG_SPI_AT25 is not set
889# CONFIG_SPI_SPIDEV is not set
890# CONFIG_SPI_TLE62X0 is not set
891CONFIG_ARCH_REQUIRE_GPIOLIB=y
892CONFIG_GPIOLIB=y
893CONFIG_DEBUG_GPIO=y
894CONFIG_GPIO_SYSFS=y
895
896#
897# I2C GPIO expanders:
898#
899# CONFIG_GPIO_MAX732X is not set
900# CONFIG_GPIO_PCA953X is not set
901# CONFIG_GPIO_PCF857X is not set
902
903#
904# PCI GPIO expanders:
905#
906
907#
908# SPI GPIO expanders:
909#
910# CONFIG_GPIO_MAX7301 is not set
911# CONFIG_GPIO_MCP23S08 is not set
912# CONFIG_W1 is not set
913CONFIG_POWER_SUPPLY=m
914# CONFIG_POWER_SUPPLY_DEBUG is not set
915# CONFIG_PDA_POWER is not set
916# CONFIG_BATTERY_DS2760 is not set
917CONFIG_HWMON=y
918# CONFIG_HWMON_VID is not set
919# CONFIG_SENSORS_AD7414 is not set
920# CONFIG_SENSORS_AD7418 is not set
921# CONFIG_SENSORS_ADCXX is not set
922# CONFIG_SENSORS_ADM1021 is not set
923# CONFIG_SENSORS_ADM1025 is not set
924# CONFIG_SENSORS_ADM1026 is not set
925# CONFIG_SENSORS_ADM1029 is not set
926# CONFIG_SENSORS_ADM1031 is not set
927# CONFIG_SENSORS_ADM9240 is not set
928# CONFIG_SENSORS_ADT7470 is not set
929# CONFIG_SENSORS_ADT7473 is not set
930# CONFIG_SENSORS_ATXP1 is not set
931# CONFIG_SENSORS_DS1621 is not set
932# CONFIG_SENSORS_F71805F is not set
933# CONFIG_SENSORS_F71882FG is not set
934# CONFIG_SENSORS_F75375S is not set
935# CONFIG_SENSORS_GL518SM is not set
936# CONFIG_SENSORS_GL520SM is not set
937# CONFIG_SENSORS_IT87 is not set
938# CONFIG_SENSORS_LM63 is not set
939# CONFIG_SENSORS_LM70 is not set
940# CONFIG_SENSORS_LM75 is not set
941# CONFIG_SENSORS_LM77 is not set
942# CONFIG_SENSORS_LM78 is not set
943# CONFIG_SENSORS_LM80 is not set
944# CONFIG_SENSORS_LM83 is not set
945# CONFIG_SENSORS_LM85 is not set
946# CONFIG_SENSORS_LM87 is not set
947# CONFIG_SENSORS_LM90 is not set
948# CONFIG_SENSORS_LM92 is not set
949# CONFIG_SENSORS_LM93 is not set
950# CONFIG_SENSORS_MAX1111 is not set
951# CONFIG_SENSORS_MAX1619 is not set
952# CONFIG_SENSORS_MAX6650 is not set
953# CONFIG_SENSORS_PC87360 is not set
954# CONFIG_SENSORS_PC87427 is not set
955# CONFIG_SENSORS_DME1737 is not set
956# CONFIG_SENSORS_SMSC47M1 is not set
957# CONFIG_SENSORS_SMSC47M192 is not set
958# CONFIG_SENSORS_SMSC47B397 is not set
959# CONFIG_SENSORS_ADS7828 is not set
960# CONFIG_SENSORS_THMC50 is not set
961# CONFIG_SENSORS_VT1211 is not set
962# CONFIG_SENSORS_W83781D is not set
963# CONFIG_SENSORS_W83791D is not set
964# CONFIG_SENSORS_W83792D is not set
965# CONFIG_SENSORS_W83793 is not set
966# CONFIG_SENSORS_W83L785TS is not set
967# CONFIG_SENSORS_W83L786NG is not set
968# CONFIG_SENSORS_W83627HF is not set
969# CONFIG_SENSORS_W83627EHF is not set
970# CONFIG_HWMON_DEBUG_CHIP is not set
971# CONFIG_THERMAL is not set
972# CONFIG_THERMAL_HWMON is not set
973CONFIG_WATCHDOG=y
974CONFIG_WATCHDOG_NOWAYOUT=y
975
976#
977# Watchdog Device Drivers
978#
979# CONFIG_SOFT_WATCHDOG is not set
980
981#
982# USB-based Watchdog Cards
983#
984# CONFIG_USBPCWATCHDOG is not set
985
986#
987# Sonics Silicon Backplane
988#
989CONFIG_SSB_POSSIBLE=y
990# CONFIG_SSB is not set
991
992#
993# Multifunction device drivers
994#
995# CONFIG_MFD_CORE is not set
996# CONFIG_MFD_SM501 is not set
997# CONFIG_HTC_EGPIO is not set
998# CONFIG_HTC_PASIC3 is not set
999# CONFIG_UCB1400_CORE is not set
1000# CONFIG_MFD_TMIO is not set
1001# CONFIG_MFD_T7L66XB is not set
1002# CONFIG_MFD_TC6387XB is not set
1003# CONFIG_MFD_TC6393XB is not set
1004
1005#
1006# Multimedia devices
1007#
1008
1009#
1010# Multimedia core support
1011#
1012CONFIG_VIDEO_DEV=m
1013CONFIG_VIDEO_V4L2_COMMON=m
1014CONFIG_VIDEO_ALLOW_V4L1=y
1015CONFIG_VIDEO_V4L1_COMPAT=y
1016CONFIG_DVB_CORE=m
1017CONFIG_VIDEO_MEDIA=m
1018
1019#
1020# Multimedia drivers
1021#
1022CONFIG_MEDIA_ATTACH=y
1023CONFIG_MEDIA_TUNER=m
1024# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
1025CONFIG_MEDIA_TUNER_SIMPLE=m
1026CONFIG_MEDIA_TUNER_TDA8290=m
1027CONFIG_MEDIA_TUNER_TDA827X=m
1028CONFIG_MEDIA_TUNER_TDA18271=m
1029CONFIG_MEDIA_TUNER_TDA9887=m
1030CONFIG_MEDIA_TUNER_TEA5761=m
1031CONFIG_MEDIA_TUNER_TEA5767=m
1032CONFIG_MEDIA_TUNER_MT20XX=m
1033CONFIG_MEDIA_TUNER_MT2060=m
1034CONFIG_MEDIA_TUNER_MT2266=m
1035CONFIG_MEDIA_TUNER_QT1010=m
1036CONFIG_MEDIA_TUNER_XC2028=m
1037CONFIG_MEDIA_TUNER_XC5000=m
1038CONFIG_MEDIA_TUNER_MXL5005S=m
1039CONFIG_VIDEO_V4L2=m
1040CONFIG_VIDEO_V4L1=m
1041CONFIG_VIDEO_TVEEPROM=m
1042CONFIG_VIDEO_TUNER=m
1043CONFIG_VIDEO_CAPTURE_DRIVERS=y
1044# CONFIG_VIDEO_ADV_DEBUG is not set
1045CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
1046CONFIG_VIDEO_MSP3400=m
1047CONFIG_VIDEO_CS53L32A=m
1048CONFIG_VIDEO_WM8775=m
1049CONFIG_VIDEO_SAA711X=m
1050CONFIG_VIDEO_CX25840=m
1051CONFIG_VIDEO_CX2341X=m
1052# CONFIG_VIDEO_VIVI is not set
1053# CONFIG_VIDEO_CPIA is not set
1054# CONFIG_VIDEO_CPIA2 is not set
1055# CONFIG_VIDEO_SAA5246A is not set
1056# CONFIG_VIDEO_SAA5249 is not set
1057# CONFIG_TUNER_3036 is not set
1058# CONFIG_VIDEO_AU0828 is not set
1059CONFIG_V4L_USB_DRIVERS=y
1060CONFIG_USB_VIDEO_CLASS=m
1061CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
1062# CONFIG_USB_GSPCA is not set
1063CONFIG_VIDEO_PVRUSB2=m
1064CONFIG_VIDEO_PVRUSB2_SYSFS=y
1065CONFIG_VIDEO_PVRUSB2_DVB=y
1066# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
1067# CONFIG_VIDEO_EM28XX is not set
1068CONFIG_VIDEO_USBVISION=m
1069CONFIG_VIDEO_USBVIDEO=m
1070CONFIG_USB_VICAM=m
1071CONFIG_USB_IBMCAM=m
1072CONFIG_USB_KONICAWC=m
1073CONFIG_USB_QUICKCAM_MESSENGER=m
1074# CONFIG_USB_ET61X251 is not set
1075CONFIG_VIDEO_OVCAMCHIP=m
1076CONFIG_USB_W9968CF=m
1077CONFIG_USB_OV511=m
1078CONFIG_USB_SE401=m
1079CONFIG_USB_SN9C102=m
1080CONFIG_USB_STV680=m
1081# CONFIG_USB_ZC0301 is not set
1082CONFIG_USB_PWC=m
1083# CONFIG_USB_PWC_DEBUG is not set
1084CONFIG_USB_ZR364XX=m
1085# CONFIG_USB_STKWEBCAM is not set
1086# CONFIG_USB_S2255 is not set
1087# CONFIG_SOC_CAMERA is not set
1088# CONFIG_VIDEO_SH_MOBILE_CEU is not set
1089CONFIG_RADIO_ADAPTERS=y
1090# CONFIG_USB_DSBR is not set
1091# CONFIG_USB_SI470X is not set
1092CONFIG_DVB_CAPTURE_DRIVERS=y
1093# CONFIG_TTPCI_EEPROM is not set
1094
1095#
1096# Supported USB Adapters
1097#
1098CONFIG_DVB_USB=m
1099# CONFIG_DVB_USB_DEBUG is not set
1100CONFIG_DVB_USB_A800=m
1101CONFIG_DVB_USB_DIBUSB_MB=m
1102# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
1103CONFIG_DVB_USB_DIBUSB_MC=m
1104CONFIG_DVB_USB_DIB0700=m
1105CONFIG_DVB_USB_UMT_010=m
1106CONFIG_DVB_USB_CXUSB=m
1107CONFIG_DVB_USB_M920X=m
1108CONFIG_DVB_USB_GL861=m
1109CONFIG_DVB_USB_AU6610=m
1110CONFIG_DVB_USB_DIGITV=m
1111CONFIG_DVB_USB_VP7045=m
1112CONFIG_DVB_USB_VP702X=m
1113CONFIG_DVB_USB_GP8PSK=m
1114CONFIG_DVB_USB_NOVA_T_USB2=m
1115CONFIG_DVB_USB_TTUSB2=m
1116CONFIG_DVB_USB_DTT200U=m
1117CONFIG_DVB_USB_OPERA1=m
1118CONFIG_DVB_USB_AF9005=m
1119CONFIG_DVB_USB_AF9005_REMOTE=m
1120# CONFIG_DVB_USB_DW2102 is not set
1121# CONFIG_DVB_USB_ANYSEE is not set
1122CONFIG_DVB_TTUSB_BUDGET=m
1123CONFIG_DVB_TTUSB_DEC=m
1124CONFIG_DVB_CINERGYT2=m
1125# CONFIG_DVB_CINERGYT2_TUNING is not set
1126# CONFIG_DVB_SIANO_SMS1XXX is not set
1127
1128#
1129# Supported FlexCopII (B2C2) Adapters
1130#
1131# CONFIG_DVB_B2C2_FLEXCOP is not set
1132
1133#
1134# Supported DVB Frontends
1135#
1136
1137#
1138# Customise DVB Frontends
1139#
1140# CONFIG_DVB_FE_CUSTOMISE is not set
1141
1142#
1143# DVB-S (satellite) frontends
1144#
1145CONFIG_DVB_CX24110=m
1146CONFIG_DVB_CX24123=m
1147CONFIG_DVB_MT312=m
1148CONFIG_DVB_S5H1420=m
1149CONFIG_DVB_STV0299=m
1150CONFIG_DVB_TDA8083=m
1151CONFIG_DVB_TDA10086=m
1152CONFIG_DVB_VES1X93=m
1153CONFIG_DVB_TUNER_ITD1000=m
1154CONFIG_DVB_TDA826X=m
1155CONFIG_DVB_TUA6100=m
1156
1157#
1158# DVB-T (terrestrial) frontends
1159#
1160CONFIG_DVB_SP8870=m
1161CONFIG_DVB_SP887X=m
1162CONFIG_DVB_CX22700=m
1163CONFIG_DVB_CX22702=m
1164# CONFIG_DVB_DRX397XD is not set
1165CONFIG_DVB_L64781=m
1166CONFIG_DVB_TDA1004X=m
1167CONFIG_DVB_NXT6000=m
1168CONFIG_DVB_MT352=m
1169CONFIG_DVB_ZL10353=m
1170CONFIG_DVB_DIB3000MB=m
1171CONFIG_DVB_DIB3000MC=m
1172CONFIG_DVB_DIB7000M=m
1173CONFIG_DVB_DIB7000P=m
1174CONFIG_DVB_TDA10048=m
1175
1176#
1177# DVB-C (cable) frontends
1178#
1179CONFIG_DVB_VES1820=m
1180CONFIG_DVB_TDA10021=m
1181CONFIG_DVB_TDA10023=m
1182CONFIG_DVB_STV0297=m
1183
1184#
1185# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
1186#
1187CONFIG_DVB_NXT200X=m
1188# CONFIG_DVB_OR51211 is not set
1189# CONFIG_DVB_OR51132 is not set
1190CONFIG_DVB_BCM3510=m
1191CONFIG_DVB_LGDT330X=m
1192CONFIG_DVB_S5H1409=m
1193CONFIG_DVB_AU8522=m
1194CONFIG_DVB_S5H1411=m
1195
1196#
1197# Digital terrestrial only tuners/PLL
1198#
1199CONFIG_DVB_PLL=m
1200CONFIG_DVB_TUNER_DIB0070=m
1201
1202#
1203# SEC control devices for DVB-S
1204#
1205CONFIG_DVB_LNBP21=m
1206# CONFIG_DVB_ISL6405 is not set
1207CONFIG_DVB_ISL6421=m
1208# CONFIG_DAB is not set
1209
1210#
1211# Graphics support
1212#
1213# CONFIG_VGASTATE is not set
1214# CONFIG_VIDEO_OUTPUT_CONTROL is not set
1215# CONFIG_FB is not set
1216# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1217
1218#
1219# Display device support
1220#
1221CONFIG_DISPLAY_SUPPORT=y
1222
1223#
1224# Display hardware drivers
1225#
1226
1227#
1228# Console display driver support
1229#
1230# CONFIG_VGA_CONSOLE is not set
1231CONFIG_DUMMY_CONSOLE=y
1232CONFIG_SOUND=y
1233CONFIG_SND=y
1234CONFIG_SND_TIMER=y
1235CONFIG_SND_PCM=y
1236CONFIG_SND_HWDEP=y
1237CONFIG_SND_RAWMIDI=y
1238CONFIG_SND_SEQUENCER=m
1239# CONFIG_SND_SEQ_DUMMY is not set
1240CONFIG_SND_OSSEMUL=y
1241CONFIG_SND_MIXER_OSS=y
1242CONFIG_SND_PCM_OSS=y
1243CONFIG_SND_PCM_OSS_PLUGINS=y
1244CONFIG_SND_SEQUENCER_OSS=y
1245# CONFIG_SND_DYNAMIC_MINORS is not set
1246CONFIG_SND_SUPPORT_OLD_API=y
1247CONFIG_SND_VERBOSE_PROCFS=y
1248CONFIG_SND_VERBOSE_PRINTK=y
1249CONFIG_SND_DEBUG=y
1250# CONFIG_SND_DEBUG_VERBOSE is not set
1251# CONFIG_SND_PCM_XRUN_DEBUG is not set
1252CONFIG_SND_DRIVERS=y
1253# CONFIG_SND_DUMMY is not set
1254# CONFIG_SND_VIRMIDI is not set
1255# CONFIG_SND_MTPAV is not set
1256# CONFIG_SND_SERIAL_U16550 is not set
1257# CONFIG_SND_MPU401 is not set
1258CONFIG_SND_ARM=y
1259CONFIG_SND_SPI=y
1260CONFIG_SND_USB=y
1261CONFIG_SND_USB_AUDIO=y
1262CONFIG_SND_USB_CAIAQ=m
1263CONFIG_SND_USB_CAIAQ_INPUT=y
1264CONFIG_SND_SOC=y
1265CONFIG_SND_OMAP_SOC=y
1266# CONFIG_SOUND_PRIME is not set
1267CONFIG_HID_SUPPORT=y
1268CONFIG_HID=y
1269CONFIG_HID_DEBUG=y
1270# CONFIG_HIDRAW is not set
1271
1272#
1273# USB Input Devices
1274#
1275CONFIG_USB_HID=y
1276# CONFIG_USB_HIDINPUT_POWERBOOK is not set
1277# CONFIG_HID_FF is not set
1278# CONFIG_USB_HIDDEV is not set
1279CONFIG_USB_SUPPORT=y
1280CONFIG_USB_ARCH_HAS_HCD=y
1281CONFIG_USB_ARCH_HAS_OHCI=y
1282# CONFIG_USB_ARCH_HAS_EHCI is not set
1283CONFIG_USB=y
1284CONFIG_USB_DEBUG=y
1285CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1286
1287#
1288# Miscellaneous USB options
1289#
1290CONFIG_USB_DEVICEFS=y
1291CONFIG_USB_DEVICE_CLASS=y
1292# CONFIG_USB_DYNAMIC_MINORS is not set
1293# CONFIG_USB_OTG is not set
1294# CONFIG_USB_OTG_WHITELIST is not set
1295# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1296CONFIG_USB_MON=y
1297
1298#
1299# USB Host Controller Drivers
1300#
1301# CONFIG_USB_C67X00_HCD is not set
1302# CONFIG_USB_ISP116X_HCD is not set
1303# CONFIG_USB_ISP1760_HCD is not set
1304# CONFIG_USB_OHCI_HCD is not set
1305# CONFIG_USB_SL811_HCD is not set
1306# CONFIG_USB_R8A66597_HCD is not set
1307CONFIG_USB_MUSB_HDRC=y
1308CONFIG_USB_MUSB_SOC=y
1309
1310#
1311# OMAP 343x high speed USB support
1312#
1313CONFIG_USB_MUSB_HOST=y
1314# CONFIG_USB_MUSB_PERIPHERAL is not set
1315# CONFIG_USB_MUSB_OTG is not set
1316CONFIG_USB_MUSB_HDRC_HCD=y
1317CONFIG_MUSB_PIO_ONLY=y
1318# CONFIG_USB_MUSB_DEBUG is not set
1319
1320#
1321# USB Device Class drivers
1322#
1323CONFIG_USB_ACM=m
1324CONFIG_USB_PRINTER=m
1325CONFIG_USB_WDM=y
1326
1327#
1328# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1329#
1330
1331#
1332# may also be needed; see USB_STORAGE Help for more information
1333#
1334CONFIG_USB_STORAGE=y
1335# CONFIG_USB_STORAGE_DEBUG is not set
1336# CONFIG_USB_STORAGE_DATAFAB is not set
1337# CONFIG_USB_STORAGE_FREECOM is not set
1338# CONFIG_USB_STORAGE_ISD200 is not set
1339# CONFIG_USB_STORAGE_DPCM is not set
1340# CONFIG_USB_STORAGE_USBAT is not set
1341# CONFIG_USB_STORAGE_SDDR09 is not set
1342# CONFIG_USB_STORAGE_SDDR55 is not set
1343# CONFIG_USB_STORAGE_JUMPSHOT is not set
1344# CONFIG_USB_STORAGE_ALAUDA is not set
1345# CONFIG_USB_STORAGE_ONETOUCH is not set
1346# CONFIG_USB_STORAGE_KARMA is not set
1347# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1348# CONFIG_USB_LIBUSUAL is not set
1349
1350#
1351# USB Imaging devices
1352#
1353# CONFIG_USB_MDC800 is not set
1354# CONFIG_USB_MICROTEK is not set
1355
1356#
1357# USB port drivers
1358#
1359CONFIG_USB_SERIAL=m
1360# CONFIG_USB_EZUSB is not set
1361# CONFIG_USB_SERIAL_GENERIC is not set
1362# CONFIG_USB_SERIAL_AIRCABLE is not set
1363# CONFIG_USB_SERIAL_ARK3116 is not set
1364# CONFIG_USB_SERIAL_BELKIN is not set
1365# CONFIG_USB_SERIAL_CH341 is not set
1366# CONFIG_USB_SERIAL_WHITEHEAT is not set
1367# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
1368# CONFIG_USB_SERIAL_CP2101 is not set
1369# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
1370# CONFIG_USB_SERIAL_EMPEG is not set
1371# CONFIG_USB_SERIAL_FTDI_SIO is not set
1372# CONFIG_USB_SERIAL_FUNSOFT is not set
1373# CONFIG_USB_SERIAL_VISOR is not set
1374# CONFIG_USB_SERIAL_IPAQ is not set
1375# CONFIG_USB_SERIAL_IR is not set
1376# CONFIG_USB_SERIAL_EDGEPORT is not set
1377# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
1378# CONFIG_USB_SERIAL_GARMIN is not set
1379# CONFIG_USB_SERIAL_IPW is not set
1380# CONFIG_USB_SERIAL_IUU is not set
1381# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
1382# CONFIG_USB_SERIAL_KEYSPAN is not set
1383# CONFIG_USB_SERIAL_KLSI is not set
1384# CONFIG_USB_SERIAL_KOBIL_SCT is not set
1385# CONFIG_USB_SERIAL_MCT_U232 is not set
1386# CONFIG_USB_SERIAL_MOS7720 is not set
1387# CONFIG_USB_SERIAL_MOS7840 is not set
1388# CONFIG_USB_SERIAL_MOTOROLA is not set
1389# CONFIG_USB_SERIAL_NAVMAN is not set
1390# CONFIG_USB_SERIAL_PL2303 is not set
1391# CONFIG_USB_SERIAL_OTI6858 is not set
1392# CONFIG_USB_SERIAL_SPCP8X5 is not set
1393# CONFIG_USB_SERIAL_HP4X is not set
1394# CONFIG_USB_SERIAL_SAFE is not set
1395# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
1396# CONFIG_USB_SERIAL_TI is not set
1397# CONFIG_USB_SERIAL_CYBERJACK is not set
1398# CONFIG_USB_SERIAL_XIRCOM is not set
1399# CONFIG_USB_SERIAL_OPTION is not set
1400# CONFIG_USB_SERIAL_OMNINET is not set
1401# CONFIG_USB_SERIAL_DEBUG is not set
1402
1403#
1404# USB Miscellaneous drivers
1405#
1406CONFIG_USB_EMI62=m
1407CONFIG_USB_EMI26=m
1408# CONFIG_USB_ADUTUX is not set
1409# CONFIG_USB_RIO500 is not set
1410CONFIG_USB_LEGOTOWER=m
1411CONFIG_USB_LCD=m
1412# CONFIG_USB_BERRY_CHARGE is not set
1413CONFIG_USB_LED=m
1414# CONFIG_USB_CYPRESS_CY7C63 is not set
1415# CONFIG_USB_CYTHERM is not set
1416# CONFIG_USB_PHIDGET is not set
1417# CONFIG_USB_IDMOUSE is not set
1418# CONFIG_USB_FTDI_ELAN is not set
1419# CONFIG_USB_APPLEDISPLAY is not set
1420# CONFIG_USB_LD is not set
1421# CONFIG_USB_TRANCEVIBRATOR is not set
1422# CONFIG_USB_IOWARRIOR is not set
1423# CONFIG_USB_TEST is not set
1424# CONFIG_USB_ISIGHTFW is not set
1425# CONFIG_USB_GADGET is not set
1426CONFIG_MMC=y
1427# CONFIG_MMC_DEBUG is not set
1428CONFIG_MMC_UNSAFE_RESUME=y
1429
1430#
1431# MMC/SD Card Drivers
1432#
1433CONFIG_MMC_BLOCK=y
1434CONFIG_MMC_BLOCK_BOUNCE=y
1435CONFIG_SDIO_UART=y
1436# CONFIG_MMC_TEST is not set
1437
1438#
1439# MMC/SD Host Controller Drivers
1440#
1441# CONFIG_MMC_SDHCI is not set
1442# CONFIG_MMC_OMAP is not set
1443# CONFIG_MMC_SPI is not set
1444# CONFIG_MEMSTICK is not set
1445# CONFIG_ACCESSIBILITY is not set
1446CONFIG_NEW_LEDS=y
1447CONFIG_LEDS_CLASS=y
1448
1449#
1450# LED drivers
1451#
1452# CONFIG_LEDS_PCA9532 is not set
1453CONFIG_LEDS_GPIO=y
1454# CONFIG_LEDS_PCA955X is not set
1455
1456#
1457# LED Triggers
1458#
1459CONFIG_LEDS_TRIGGERS=y
1460CONFIG_LEDS_TRIGGER_TIMER=y
1461CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1462# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
1463CONFIG_RTC_LIB=y
1464CONFIG_RTC_CLASS=y
1465CONFIG_RTC_HCTOSYS=y
1466CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1467# CONFIG_RTC_DEBUG is not set
1468
1469#
1470# RTC interfaces
1471#
1472CONFIG_RTC_INTF_SYSFS=y
1473CONFIG_RTC_INTF_PROC=y
1474CONFIG_RTC_INTF_DEV=y
1475# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1476# CONFIG_RTC_DRV_TEST is not set
1477
1478#
1479# I2C RTC drivers
1480#
1481# CONFIG_RTC_DRV_DS1307 is not set
1482# CONFIG_RTC_DRV_DS1374 is not set
1483# CONFIG_RTC_DRV_DS1672 is not set
1484# CONFIG_RTC_DRV_MAX6900 is not set
1485# CONFIG_RTC_DRV_RS5C372 is not set
1486# CONFIG_RTC_DRV_ISL1208 is not set
1487# CONFIG_RTC_DRV_X1205 is not set
1488# CONFIG_RTC_DRV_PCF8563 is not set
1489# CONFIG_RTC_DRV_PCF8583 is not set
1490# CONFIG_RTC_DRV_M41T80 is not set
1491# CONFIG_RTC_DRV_S35390A is not set
1492# CONFIG_RTC_DRV_FM3130 is not set
1493
1494#
1495# SPI RTC drivers
1496#
1497# CONFIG_RTC_DRV_M41T94 is not set
1498# CONFIG_RTC_DRV_DS1305 is not set
1499# CONFIG_RTC_DRV_MAX6902 is not set
1500# CONFIG_RTC_DRV_R9701 is not set
1501# CONFIG_RTC_DRV_RS5C348 is not set
1502
1503#
1504# Platform RTC drivers
1505#
1506# CONFIG_RTC_DRV_CMOS is not set
1507# CONFIG_RTC_DRV_DS1511 is not set
1508# CONFIG_RTC_DRV_DS1553 is not set
1509# CONFIG_RTC_DRV_DS1742 is not set
1510# CONFIG_RTC_DRV_STK17TA8 is not set
1511# CONFIG_RTC_DRV_M48T86 is not set
1512# CONFIG_RTC_DRV_M48T59 is not set
1513# CONFIG_RTC_DRV_V3020 is not set
1514
1515#
1516# on-CPU RTC drivers
1517#
1518# CONFIG_DMADEVICES is not set
1519
1520#
1521# Voltage and Current regulators
1522#
1523# CONFIG_REGULATOR is not set
1524# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
1525# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
1526# CONFIG_REGULATOR_BQ24022 is not set
1527# CONFIG_UIO is not set
1528
1529#
1530# File systems
1531#
1532CONFIG_EXT2_FS=y
1533# CONFIG_EXT2_FS_XATTR is not set
1534# CONFIG_EXT2_FS_XIP is not set
1535CONFIG_EXT3_FS=y
1536# CONFIG_EXT3_FS_XATTR is not set
1537# CONFIG_EXT4DEV_FS is not set
1538CONFIG_JBD=y
1539# CONFIG_JBD_DEBUG is not set
1540# CONFIG_REISERFS_FS is not set
1541# CONFIG_JFS_FS is not set
1542CONFIG_FS_POSIX_ACL=y
1543CONFIG_XFS_FS=m
1544# CONFIG_XFS_QUOTA is not set
1545# CONFIG_XFS_POSIX_ACL is not set
1546# CONFIG_XFS_RT is not set
1547# CONFIG_XFS_DEBUG is not set
1548# CONFIG_GFS2_FS is not set
1549# CONFIG_OCFS2_FS is not set
1550CONFIG_DNOTIFY=y
1551CONFIG_INOTIFY=y
1552CONFIG_INOTIFY_USER=y
1553CONFIG_QUOTA=y
1554# CONFIG_QUOTA_NETLINK_INTERFACE is not set
1555CONFIG_PRINT_QUOTA_WARNING=y
1556# CONFIG_QFMT_V1 is not set
1557CONFIG_QFMT_V2=y
1558CONFIG_QUOTACTL=y
1559# CONFIG_AUTOFS_FS is not set
1560# CONFIG_AUTOFS4_FS is not set
1561CONFIG_FUSE_FS=m
1562
1563#
1564# CD-ROM/DVD Filesystems
1565#
1566CONFIG_ISO9660_FS=m
1567CONFIG_JOLIET=y
1568CONFIG_ZISOFS=y
1569CONFIG_UDF_FS=m
1570CONFIG_UDF_NLS=y
1571
1572#
1573# DOS/FAT/NT Filesystems
1574#
1575CONFIG_FAT_FS=y
1576CONFIG_MSDOS_FS=y
1577CONFIG_VFAT_FS=y
1578CONFIG_FAT_DEFAULT_CODEPAGE=437
1579CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1580# CONFIG_NTFS_FS is not set
1581
1582#
1583# Pseudo filesystems
1584#
1585CONFIG_PROC_FS=y
1586CONFIG_PROC_SYSCTL=y
1587CONFIG_SYSFS=y
1588CONFIG_TMPFS=y
1589# CONFIG_TMPFS_POSIX_ACL is not set
1590# CONFIG_HUGETLB_PAGE is not set
1591# CONFIG_CONFIGFS_FS is not set
1592
1593#
1594# Miscellaneous filesystems
1595#
1596# CONFIG_ADFS_FS is not set
1597# CONFIG_AFFS_FS is not set
1598# CONFIG_HFS_FS is not set
1599# CONFIG_HFSPLUS_FS is not set
1600# CONFIG_BEFS_FS is not set
1601# CONFIG_BFS_FS is not set
1602# CONFIG_EFS_FS is not set
1603CONFIG_JFFS2_FS=y
1604CONFIG_JFFS2_FS_DEBUG=0
1605CONFIG_JFFS2_FS_WRITEBUFFER=y
1606# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1607CONFIG_JFFS2_SUMMARY=y
1608CONFIG_JFFS2_FS_XATTR=y
1609CONFIG_JFFS2_FS_POSIX_ACL=y
1610CONFIG_JFFS2_FS_SECURITY=y
1611CONFIG_JFFS2_COMPRESSION_OPTIONS=y
1612CONFIG_JFFS2_ZLIB=y
1613CONFIG_JFFS2_LZO=y
1614CONFIG_JFFS2_RTIME=y
1615CONFIG_JFFS2_RUBIN=y
1616# CONFIG_JFFS2_CMODE_NONE is not set
1617CONFIG_JFFS2_CMODE_PRIORITY=y
1618# CONFIG_JFFS2_CMODE_SIZE is not set
1619# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
1620# CONFIG_CRAMFS is not set
1621# CONFIG_VXFS_FS is not set
1622# CONFIG_MINIX_FS is not set
1623# CONFIG_OMFS_FS is not set
1624# CONFIG_HPFS_FS is not set
1625# CONFIG_QNX4FS_FS is not set
1626# CONFIG_ROMFS_FS is not set
1627# CONFIG_SYSV_FS is not set
1628# CONFIG_UFS_FS is not set
1629CONFIG_NETWORK_FILESYSTEMS=y
1630CONFIG_NFS_FS=y
1631CONFIG_NFS_V3=y
1632# CONFIG_NFS_V3_ACL is not set
1633CONFIG_NFS_V4=y
1634CONFIG_ROOT_NFS=y
1635# CONFIG_NFSD is not set
1636CONFIG_LOCKD=y
1637CONFIG_LOCKD_V4=y
1638CONFIG_NFS_COMMON=y
1639CONFIG_SUNRPC=y
1640CONFIG_SUNRPC_GSS=y
1641CONFIG_RPCSEC_GSS_KRB5=y
1642# CONFIG_RPCSEC_GSS_SPKM3 is not set
1643# CONFIG_SMB_FS is not set
1644# CONFIG_CIFS is not set
1645# CONFIG_NCP_FS is not set
1646# CONFIG_CODA_FS is not set
1647# CONFIG_AFS_FS is not set
1648
1649#
1650# Partition Types
1651#
1652CONFIG_PARTITION_ADVANCED=y
1653# CONFIG_ACORN_PARTITION is not set
1654# CONFIG_OSF_PARTITION is not set
1655# CONFIG_AMIGA_PARTITION is not set
1656# CONFIG_ATARI_PARTITION is not set
1657# CONFIG_MAC_PARTITION is not set
1658CONFIG_MSDOS_PARTITION=y
1659# CONFIG_BSD_DISKLABEL is not set
1660# CONFIG_MINIX_SUBPARTITION is not set
1661# CONFIG_SOLARIS_X86_PARTITION is not set
1662# CONFIG_UNIXWARE_DISKLABEL is not set
1663# CONFIG_LDM_PARTITION is not set
1664# CONFIG_SGI_PARTITION is not set
1665# CONFIG_ULTRIX_PARTITION is not set
1666# CONFIG_SUN_PARTITION is not set
1667# CONFIG_KARMA_PARTITION is not set
1668# CONFIG_EFI_PARTITION is not set
1669# CONFIG_SYSV68_PARTITION is not set
1670CONFIG_NLS=y
1671CONFIG_NLS_DEFAULT="iso8859-1"
1672CONFIG_NLS_CODEPAGE_437=y
1673# CONFIG_NLS_CODEPAGE_737 is not set
1674# CONFIG_NLS_CODEPAGE_775 is not set
1675# CONFIG_NLS_CODEPAGE_850 is not set
1676# CONFIG_NLS_CODEPAGE_852 is not set
1677# CONFIG_NLS_CODEPAGE_855 is not set
1678# CONFIG_NLS_CODEPAGE_857 is not set
1679# CONFIG_NLS_CODEPAGE_860 is not set
1680# CONFIG_NLS_CODEPAGE_861 is not set
1681# CONFIG_NLS_CODEPAGE_862 is not set
1682# CONFIG_NLS_CODEPAGE_863 is not set
1683# CONFIG_NLS_CODEPAGE_864 is not set
1684# CONFIG_NLS_CODEPAGE_865 is not set
1685# CONFIG_NLS_CODEPAGE_866 is not set
1686# CONFIG_NLS_CODEPAGE_869 is not set
1687# CONFIG_NLS_CODEPAGE_936 is not set
1688# CONFIG_NLS_CODEPAGE_950 is not set
1689# CONFIG_NLS_CODEPAGE_932 is not set
1690# CONFIG_NLS_CODEPAGE_949 is not set
1691# CONFIG_NLS_CODEPAGE_874 is not set
1692# CONFIG_NLS_ISO8859_8 is not set
1693# CONFIG_NLS_CODEPAGE_1250 is not set
1694# CONFIG_NLS_CODEPAGE_1251 is not set
1695# CONFIG_NLS_ASCII is not set
1696CONFIG_NLS_ISO8859_1=y
1697# CONFIG_NLS_ISO8859_2 is not set
1698# CONFIG_NLS_ISO8859_3 is not set
1699# CONFIG_NLS_ISO8859_4 is not set
1700# CONFIG_NLS_ISO8859_5 is not set
1701# CONFIG_NLS_ISO8859_6 is not set
1702# CONFIG_NLS_ISO8859_7 is not set
1703# CONFIG_NLS_ISO8859_9 is not set
1704# CONFIG_NLS_ISO8859_13 is not set
1705# CONFIG_NLS_ISO8859_14 is not set
1706# CONFIG_NLS_ISO8859_15 is not set
1707# CONFIG_NLS_KOI8_R is not set
1708# CONFIG_NLS_KOI8_U is not set
1709# CONFIG_NLS_UTF8 is not set
1710# CONFIG_DLM is not set
1711
1712#
1713# Kernel hacking
1714#
1715# CONFIG_PRINTK_TIME is not set
1716CONFIG_ENABLE_WARN_DEPRECATED=y
1717CONFIG_ENABLE_MUST_CHECK=y
1718CONFIG_FRAME_WARN=1024
1719CONFIG_MAGIC_SYSRQ=y
1720# CONFIG_UNUSED_SYMBOLS is not set
1721CONFIG_DEBUG_FS=y
1722# CONFIG_HEADERS_CHECK is not set
1723CONFIG_DEBUG_KERNEL=y
1724# CONFIG_DEBUG_SHIRQ is not set
1725CONFIG_DETECT_SOFTLOCKUP=y
1726# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1727CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1728CONFIG_SCHED_DEBUG=y
1729CONFIG_SCHEDSTATS=y
1730CONFIG_TIMER_STATS=y
1731# CONFIG_DEBUG_OBJECTS is not set
1732# CONFIG_SLUB_DEBUG_ON is not set
1733# CONFIG_SLUB_STATS is not set
1734# CONFIG_DEBUG_RT_MUTEXES is not set
1735# CONFIG_RT_MUTEX_TESTER is not set
1736# CONFIG_DEBUG_SPINLOCK is not set
1737CONFIG_DEBUG_MUTEXES=y
1738# CONFIG_DEBUG_LOCK_ALLOC is not set
1739# CONFIG_PROVE_LOCKING is not set
1740# CONFIG_LOCK_STAT is not set
1741# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1742# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1743# CONFIG_DEBUG_KOBJECT is not set
1744# CONFIG_DEBUG_BUGVERBOSE is not set
1745# CONFIG_DEBUG_INFO is not set
1746# CONFIG_DEBUG_VM is not set
1747# CONFIG_DEBUG_WRITECOUNT is not set
1748# CONFIG_DEBUG_MEMORY_INIT is not set
1749# CONFIG_DEBUG_LIST is not set
1750# CONFIG_DEBUG_SG is not set
1751CONFIG_FRAME_POINTER=y
1752# CONFIG_BOOT_PRINTK_DELAY is not set
1753# CONFIG_RCU_TORTURE_TEST is not set
1754# CONFIG_BACKTRACE_SELF_TEST is not set
1755# CONFIG_FAULT_INJECTION is not set
1756# CONFIG_LATENCYTOP is not set
1757CONFIG_HAVE_FTRACE=y
1758CONFIG_HAVE_DYNAMIC_FTRACE=y
1759# CONFIG_FTRACE is not set
1760# CONFIG_IRQSOFF_TRACER is not set
1761# CONFIG_SCHED_TRACER is not set
1762# CONFIG_CONTEXT_SWITCH_TRACER is not set
1763# CONFIG_SAMPLES is not set
1764CONFIG_HAVE_ARCH_KGDB=y
1765# CONFIG_KGDB is not set
1766# CONFIG_DEBUG_USER is not set
1767# CONFIG_DEBUG_ERRORS is not set
1768# CONFIG_DEBUG_STACK_USAGE is not set
1769# CONFIG_DEBUG_LL is not set
1770
1771#
1772# Security options
1773#
1774# CONFIG_KEYS is not set
1775# CONFIG_SECURITY is not set
1776# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1777CONFIG_XOR_BLOCKS=m
1778CONFIG_ASYNC_CORE=m
1779CONFIG_ASYNC_MEMCPY=m
1780CONFIG_ASYNC_XOR=m
1781CONFIG_CRYPTO=y
1782
1783#
1784# Crypto core or helper
1785#
1786CONFIG_CRYPTO_ALGAPI=y
1787CONFIG_CRYPTO_AEAD=m
1788CONFIG_CRYPTO_BLKCIPHER=y
1789CONFIG_CRYPTO_HASH=m
1790CONFIG_CRYPTO_MANAGER=y
1791CONFIG_CRYPTO_GF128MUL=m
1792CONFIG_CRYPTO_NULL=m
1793CONFIG_CRYPTO_CRYPTD=m
1794# CONFIG_CRYPTO_AUTHENC is not set
1795CONFIG_CRYPTO_TEST=m
1796
1797#
1798# Authenticated Encryption with Associated Data
1799#
1800# CONFIG_CRYPTO_CCM is not set
1801# CONFIG_CRYPTO_GCM is not set
1802# CONFIG_CRYPTO_SEQIV is not set
1803
1804#
1805# Block modes
1806#
1807CONFIG_CRYPTO_CBC=y
1808# CONFIG_CRYPTO_CTR is not set
1809# CONFIG_CRYPTO_CTS is not set
1810CONFIG_CRYPTO_ECB=y
1811CONFIG_CRYPTO_LRW=m
1812CONFIG_CRYPTO_PCBC=m
1813# CONFIG_CRYPTO_XTS is not set
1814
1815#
1816# Hash modes
1817#
1818CONFIG_CRYPTO_HMAC=m
1819CONFIG_CRYPTO_XCBC=m
1820
1821#
1822# Digest
1823#
1824CONFIG_CRYPTO_CRC32C=m
1825CONFIG_CRYPTO_MD4=m
1826CONFIG_CRYPTO_MD5=y
1827CONFIG_CRYPTO_MICHAEL_MIC=y
1828# CONFIG_CRYPTO_RMD128 is not set
1829# CONFIG_CRYPTO_RMD160 is not set
1830# CONFIG_CRYPTO_RMD256 is not set
1831# CONFIG_CRYPTO_RMD320 is not set
1832CONFIG_CRYPTO_SHA1=m
1833CONFIG_CRYPTO_SHA256=m
1834CONFIG_CRYPTO_SHA512=m
1835CONFIG_CRYPTO_TGR192=m
1836CONFIG_CRYPTO_WP512=m
1837
1838#
1839# Ciphers
1840#
1841CONFIG_CRYPTO_AES=y
1842CONFIG_CRYPTO_ANUBIS=m
1843CONFIG_CRYPTO_ARC4=y
1844CONFIG_CRYPTO_BLOWFISH=m
1845CONFIG_CRYPTO_CAMELLIA=m
1846CONFIG_CRYPTO_CAST5=m
1847CONFIG_CRYPTO_CAST6=m
1848CONFIG_CRYPTO_DES=y
1849CONFIG_CRYPTO_FCRYPT=m
1850CONFIG_CRYPTO_KHAZAD=m
1851# CONFIG_CRYPTO_SALSA20 is not set
1852# CONFIG_CRYPTO_SEED is not set
1853CONFIG_CRYPTO_SERPENT=m
1854CONFIG_CRYPTO_TEA=m
1855CONFIG_CRYPTO_TWOFISH=m
1856CONFIG_CRYPTO_TWOFISH_COMMON=m
1857
1858#
1859# Compression
1860#
1861CONFIG_CRYPTO_DEFLATE=m
1862# CONFIG_CRYPTO_LZO is not set
1863CONFIG_CRYPTO_HW=y
1864
1865#
1866# Library routines
1867#
1868CONFIG_BITREVERSE=y
1869# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1870# CONFIG_GENERIC_FIND_NEXT_BIT is not set
1871CONFIG_CRC_CCITT=y
1872CONFIG_CRC16=m
1873CONFIG_CRC_T10DIF=y
1874CONFIG_CRC_ITU_T=y
1875CONFIG_CRC32=y
1876CONFIG_CRC7=y
1877CONFIG_LIBCRC32C=y
1878CONFIG_ZLIB_INFLATE=y
1879CONFIG_ZLIB_DEFLATE=y
1880CONFIG_LZO_COMPRESS=y
1881CONFIG_LZO_DECOMPRESS=y
1882CONFIG_PLIST=y
1883CONFIG_HAS_IOMEM=y
1884CONFIG_HAS_IOPORT=y
1885CONFIG_HAS_DMA=y
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 478c2c9a22cb..5fba20731710 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -201,7 +201,7 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate)
201 return -EINVAL; 201 return -EINVAL;
202 202
203 parent = clk->parent; 203 parent = clk->parent;
204 if (unlikely(parent == 0)) 204 if (unlikely(parent == NULL))
205 return -EIO; 205 return -EIO;
206 206
207 realrate = parent->rate; 207 realrate = parent->rate;
@@ -499,7 +499,7 @@ static int omap1_clk_enable_generic(struct clk *clk)
499 if (clk->flags & ALWAYS_ENABLED) 499 if (clk->flags & ALWAYS_ENABLED)
500 return 0; 500 return 0;
501 501
502 if (unlikely(clk->enable_reg == 0)) { 502 if (unlikely(clk->enable_reg == NULL)) {
503 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 503 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
504 clk->name); 504 clk->name);
505 return -EINVAL; 505 return -EINVAL;
@@ -535,7 +535,7 @@ static void omap1_clk_disable_generic(struct clk *clk)
535 __u16 regval16; 535 __u16 regval16;
536 __u32 regval32; 536 __u32 regval32;
537 537
538 if (clk->enable_reg == 0) 538 if (clk->enable_reg == NULL)
539 return; 539 return;
540 540
541 if (clk->flags & ENABLE_REG_32BIT) { 541 if (clk->flags & ENABLE_REG_32BIT) {
@@ -577,7 +577,7 @@ static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
577 return clk->parent->rate / (1 << dsor_exp); 577 return clk->parent->rate / (1 << dsor_exp);
578 } 578 }
579 579
580 if(clk->round_rate != 0) 580 if (clk->round_rate != NULL)
581 return clk->round_rate(clk, rate); 581 return clk->round_rate(clk, rate);
582 582
583 return clk->rate; 583 return clk->rate;
@@ -625,7 +625,7 @@ static void __init omap1_clk_disable_unused(struct clk *clk)
625 625
626 /* Clocks in the DSP domain need api_ck. Just assume bootloader 626 /* Clocks in the DSP domain need api_ck. Just assume bootloader
627 * has not enabled any DSP clocks */ 627 * has not enabled any DSP clocks */
628 if ((u32)clk->enable_reg == DSP_IDLECT2) { 628 if (clk->enable_reg == DSP_IDLECT2) {
629 printk(KERN_INFO "Skipping reset check for DSP domain " 629 printk(KERN_INFO "Skipping reset check for DSP domain "
630 "clock \"%s\"\n", clk->name); 630 "clock \"%s\"\n", clk->name);
631 return; 631 return;
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index 6eadf72828d8..5635b511ab6f 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -324,7 +324,7 @@ static struct clk dspper_ck = {
324 .parent = &ck_dpll1, 324 .parent = &ck_dpll1,
325 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 325 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
326 RATE_CKCTL | VIRTUAL_IO_ADDRESS, 326 RATE_CKCTL | VIRTUAL_IO_ADDRESS,
327 .enable_reg = (void __iomem *)DSP_IDLECT2, 327 .enable_reg = DSP_IDLECT2,
328 .enable_bit = EN_PERCK, 328 .enable_bit = EN_PERCK,
329 .rate_offset = CKCTL_PERDIV_OFFSET, 329 .rate_offset = CKCTL_PERDIV_OFFSET,
330 .recalc = &omap1_ckctl_recalc_dsp_domain, 330 .recalc = &omap1_ckctl_recalc_dsp_domain,
@@ -338,7 +338,7 @@ static struct clk dspxor_ck = {
338 .parent = &ck_ref, 338 .parent = &ck_ref,
339 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 339 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
340 VIRTUAL_IO_ADDRESS, 340 VIRTUAL_IO_ADDRESS,
341 .enable_reg = (void __iomem *)DSP_IDLECT2, 341 .enable_reg = DSP_IDLECT2,
342 .enable_bit = EN_XORPCK, 342 .enable_bit = EN_XORPCK,
343 .recalc = &followparent_recalc, 343 .recalc = &followparent_recalc,
344 .enable = &omap1_clk_enable_dsp_domain, 344 .enable = &omap1_clk_enable_dsp_domain,
@@ -350,7 +350,7 @@ static struct clk dsptim_ck = {
350 .parent = &ck_ref, 350 .parent = &ck_ref,
351 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 351 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
352 VIRTUAL_IO_ADDRESS, 352 VIRTUAL_IO_ADDRESS,
353 .enable_reg = (void __iomem *)DSP_IDLECT2, 353 .enable_reg = DSP_IDLECT2,
354 .enable_bit = EN_DSPTIMCK, 354 .enable_bit = EN_DSPTIMCK,
355 .recalc = &followparent_recalc, 355 .recalc = &followparent_recalc,
356 .enable = &omap1_clk_enable_dsp_domain, 356 .enable = &omap1_clk_enable_dsp_domain,
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 99982d3380c9..e382b438c64e 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -101,7 +101,7 @@ static inline void omap_init_mbox(void) { }
101 101
102#if defined(CONFIG_OMAP_STI) 102#if defined(CONFIG_OMAP_STI)
103 103
104#define OMAP1_STI_BASE IO_ADDRESS(0xfffea000) 104#define OMAP1_STI_BASE 0xfffea000
105#define OMAP1_STI_CHANNEL_BASE (OMAP1_STI_BASE + 0x400) 105#define OMAP1_STI_CHANNEL_BASE (OMAP1_STI_BASE + 0x400)
106 106
107static struct resource sti_resources[] = { 107static struct resource sti_resources[] = {
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index 2baeaeb0c900..7de7c6915584 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -103,30 +103,6 @@ static inline void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
103{ } 103{ }
104#endif 104#endif
105 105
106static int omap1_mcbsp_check(unsigned int id)
107{
108 /* REVISIT: Check correctly for number of registered McBSPs */
109 if (cpu_is_omap730()) {
110 if (id > OMAP_MAX_MCBSP_COUNT - 2) {
111 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
112 id + 1);
113 return -ENODEV;
114 }
115 return 0;
116 }
117
118 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
119 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
120 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
121 id + 1);
122 return -ENODEV;
123 }
124 return 0;
125 }
126
127 return -ENODEV;
128}
129
130static void omap1_mcbsp_request(unsigned int id) 106static void omap1_mcbsp_request(unsigned int id)
131{ 107{
132 /* 108 /*
@@ -151,7 +127,6 @@ static void omap1_mcbsp_free(unsigned int id)
151} 127}
152 128
153static struct omap_mcbsp_ops omap1_mcbsp_ops = { 129static struct omap_mcbsp_ops omap1_mcbsp_ops = {
154 .check = omap1_mcbsp_check,
155 .request = omap1_mcbsp_request, 130 .request = omap1_mcbsp_request,
156 .free = omap1_mcbsp_free, 131 .free = omap1_mcbsp_free,
157}; 132};
@@ -160,7 +135,6 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
160static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = { 135static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
161 { 136 {
162 .phys_base = OMAP730_MCBSP1_BASE, 137 .phys_base = OMAP730_MCBSP1_BASE,
163 .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
164 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 138 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
165 .dma_tx_sync = OMAP_DMA_MCBSP1_TX, 139 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
166 .rx_irq = INT_730_McBSP1RX, 140 .rx_irq = INT_730_McBSP1RX,
@@ -169,7 +143,6 @@ static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
169 }, 143 },
170 { 144 {
171 .phys_base = OMAP730_MCBSP2_BASE, 145 .phys_base = OMAP730_MCBSP2_BASE,
172 .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
173 .dma_rx_sync = OMAP_DMA_MCBSP3_RX, 146 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
174 .dma_tx_sync = OMAP_DMA_MCBSP3_TX, 147 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
175 .rx_irq = INT_730_McBSP2RX, 148 .rx_irq = INT_730_McBSP2RX,
@@ -187,7 +160,6 @@ static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
187static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { 160static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
188 { 161 {
189 .phys_base = OMAP1510_MCBSP1_BASE, 162 .phys_base = OMAP1510_MCBSP1_BASE,
190 .virt_base = OMAP1510_MCBSP1_BASE,
191 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 163 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
192 .dma_tx_sync = OMAP_DMA_MCBSP1_TX, 164 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
193 .rx_irq = INT_McBSP1RX, 165 .rx_irq = INT_McBSP1RX,
@@ -197,7 +169,6 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
197 }, 169 },
198 { 170 {
199 .phys_base = OMAP1510_MCBSP2_BASE, 171 .phys_base = OMAP1510_MCBSP2_BASE,
200 .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
201 .dma_rx_sync = OMAP_DMA_MCBSP2_RX, 172 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
202 .dma_tx_sync = OMAP_DMA_MCBSP2_TX, 173 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
203 .rx_irq = INT_1510_SPI_RX, 174 .rx_irq = INT_1510_SPI_RX,
@@ -206,7 +177,6 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
206 }, 177 },
207 { 178 {
208 .phys_base = OMAP1510_MCBSP3_BASE, 179 .phys_base = OMAP1510_MCBSP3_BASE,
209 .virt_base = OMAP1510_MCBSP3_BASE,
210 .dma_rx_sync = OMAP_DMA_MCBSP3_RX, 180 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
211 .dma_tx_sync = OMAP_DMA_MCBSP3_TX, 181 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
212 .rx_irq = INT_McBSP3RX, 182 .rx_irq = INT_McBSP3RX,
@@ -225,7 +195,6 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
225static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { 195static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
226 { 196 {
227 .phys_base = OMAP1610_MCBSP1_BASE, 197 .phys_base = OMAP1610_MCBSP1_BASE,
228 .virt_base = OMAP1610_MCBSP1_BASE,
229 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 198 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
230 .dma_tx_sync = OMAP_DMA_MCBSP1_TX, 199 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
231 .rx_irq = INT_McBSP1RX, 200 .rx_irq = INT_McBSP1RX,
@@ -235,7 +204,6 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
235 }, 204 },
236 { 205 {
237 .phys_base = OMAP1610_MCBSP2_BASE, 206 .phys_base = OMAP1610_MCBSP2_BASE,
238 .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
239 .dma_rx_sync = OMAP_DMA_MCBSP2_RX, 207 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
240 .dma_tx_sync = OMAP_DMA_MCBSP2_TX, 208 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
241 .rx_irq = INT_1610_McBSP2_RX, 209 .rx_irq = INT_1610_McBSP2_RX,
@@ -244,7 +212,6 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
244 }, 212 },
245 { 213 {
246 .phys_base = OMAP1610_MCBSP3_BASE, 214 .phys_base = OMAP1610_MCBSP3_BASE,
247 .virt_base = OMAP1610_MCBSP3_BASE,
248 .dma_rx_sync = OMAP_DMA_MCBSP3_RX, 215 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
249 .dma_tx_sync = OMAP_DMA_MCBSP3_TX, 216 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
250 .rx_irq = INT_McBSP3RX, 217 .rx_irq = INT_McBSP3RX,
@@ -271,6 +238,18 @@ int __init omap1_mcbsp_init(void)
271 } 238 }
272 239
273 if (cpu_is_omap730()) 240 if (cpu_is_omap730())
241 omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ;
242 if (cpu_is_omap15xx())
243 omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
244 if (cpu_is_omap16xx())
245 omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ;
246
247 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
248 GFP_KERNEL);
249 if (!mcbsp_ptr)
250 return -ENOMEM;
251
252 if (cpu_is_omap730())
274 omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata, 253 omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata,
275 OMAP730_MCBSP_PDATA_SZ); 254 OMAP730_MCBSP_PDATA_SZ);
276 255
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index aefc967fc003..528691d5cb51 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -67,8 +67,8 @@ static void __init omap_serial_reset(struct plat_serial8250_port *p)
67 67
68static struct plat_serial8250_port serial_platform_data[] = { 68static struct plat_serial8250_port serial_platform_data[] = {
69 { 69 {
70 .membase = (char*)IO_ADDRESS(OMAP_UART1_BASE), 70 .membase = IO_ADDRESS(OMAP_UART1_BASE),
71 .mapbase = (unsigned long)OMAP_UART1_BASE, 71 .mapbase = OMAP_UART1_BASE,
72 .irq = INT_UART1, 72 .irq = INT_UART1,
73 .flags = UPF_BOOT_AUTOCONF, 73 .flags = UPF_BOOT_AUTOCONF,
74 .iotype = UPIO_MEM, 74 .iotype = UPIO_MEM,
@@ -76,8 +76,8 @@ static struct plat_serial8250_port serial_platform_data[] = {
76 .uartclk = OMAP16XX_BASE_BAUD * 16, 76 .uartclk = OMAP16XX_BASE_BAUD * 16,
77 }, 77 },
78 { 78 {
79 .membase = (char*)IO_ADDRESS(OMAP_UART2_BASE), 79 .membase = IO_ADDRESS(OMAP_UART2_BASE),
80 .mapbase = (unsigned long)OMAP_UART2_BASE, 80 .mapbase = OMAP_UART2_BASE,
81 .irq = INT_UART2, 81 .irq = INT_UART2,
82 .flags = UPF_BOOT_AUTOCONF, 82 .flags = UPF_BOOT_AUTOCONF,
83 .iotype = UPIO_MEM, 83 .iotype = UPIO_MEM,
@@ -85,8 +85,8 @@ static struct plat_serial8250_port serial_platform_data[] = {
85 .uartclk = OMAP16XX_BASE_BAUD * 16, 85 .uartclk = OMAP16XX_BASE_BAUD * 16,
86 }, 86 },
87 { 87 {
88 .membase = (char*)IO_ADDRESS(OMAP_UART3_BASE), 88 .membase = IO_ADDRESS(OMAP_UART3_BASE),
89 .mapbase = (unsigned long)OMAP_UART3_BASE, 89 .mapbase = OMAP_UART3_BASE,
90 .irq = INT_UART3, 90 .irq = INT_UART3,
91 .flags = UPF_BOOT_AUTOCONF, 91 .flags = UPF_BOOT_AUTOCONF,
92 .iotype = UPIO_MEM, 92 .iotype = UPIO_MEM,
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 7069c9d536f1..4832fcc7d04a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -15,8 +15,17 @@ config ARCH_OMAP2430
15 bool "OMAP2430 support" 15 bool "OMAP2430 support"
16 depends on ARCH_OMAP24XX 16 depends on ARCH_OMAP24XX
17 17
18config ARCH_OMAP34XX
19 bool "OMAP34xx Based System"
20 depends on ARCH_OMAP3
21
22config ARCH_OMAP3430
23 bool "OMAP3430 support"
24 depends on ARCH_OMAP3 && ARCH_OMAP34XX
25 select ARCH_OMAP_OTG
26
18comment "OMAP Board Type" 27comment "OMAP Board Type"
19 depends on ARCH_OMAP2 28 depends on ARCH_OMAP2 || ARCH_OMAP3
20 29
21config MACH_OMAP_GENERIC 30config MACH_OMAP_GENERIC
22 bool "Generic OMAP board" 31 bool "Generic OMAP board"
@@ -35,3 +44,14 @@ config MACH_OMAP_2430SDP
35 bool "OMAP 2430 SDP board" 44 bool "OMAP 2430 SDP board"
36 depends on ARCH_OMAP2 && ARCH_OMAP24XX 45 depends on ARCH_OMAP2 && ARCH_OMAP24XX
37 46
47config MACH_OMAP3_BEAGLE
48 bool "OMAP3 BEAGLE board"
49 depends on ARCH_OMAP3 && ARCH_OMAP34XX
50
51config MACH_OMAP_LDP
52 bool "OMAP3 LDP board"
53 depends on ARCH_OMAP3 && ARCH_OMAP34XX
54
55config MACH_OVERO
56 bool "Gumstix Overo board"
57 depends on ARCH_OMAP3 && ARCH_OMAP34XX
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 93ee990618ef..c69392372c99 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,16 +4,21 @@
4 4
5# Common support 5# Common support
6obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \ 6obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \
7 devices.o serial.o gpmc.o timer-gp.o 7 devices.o serial.o gpmc.o timer-gp.o powerdomain.o \
8 clockdomain.o
8 9
9obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o 10obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
10 11
11# Functions loaded to SRAM 12# Functions loaded to SRAM
12obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o 13obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
13obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o 14obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
15obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
14 16
15# Power Management 17# Power Management
16obj-$(CONFIG_PM) += pm.o sleep.o 18ifeq ($(CONFIG_PM),y)
19obj-y += pm.o
20obj-$(CONFIG_ARCH_OMAP24XX) += sleep24xx.o
21endif
17 22
18# Clock framework 23# Clock framework
19obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o 24obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
@@ -24,4 +29,7 @@ obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
24obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o 29obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
25obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o 30obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o
26obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o 31obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o
32obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
33obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
34obj-$(CONFIG_MACH_OVERO) += board-overo.o
27 35
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
new file mode 100644
index 000000000000..1ea59986aa7a
--- /dev/null
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -0,0 +1,86 @@
1/*
2 * linux/arch/arm/mach-omap2/board-ldp.c
3 *
4 * Copyright (C) 2008 Texas Instruments Inc.
5 * Nishant Kamat <nskamat@ti.com>
6 *
7 * Modified from mach-omap2/board-3430sdp.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/delay.h>
18#include <linux/input.h>
19#include <linux/workqueue.h>
20#include <linux/err.h>
21#include <linux/clk.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/ads7846.h>
24
25#include <mach/hardware.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29
30#include <mach/board-ldp.h>
31#include <mach/mcspi.h>
32#include <mach/gpio.h>
33#include <mach/board.h>
34#include <mach/common.h>
35#include <mach/gpmc.h>
36
37#include <asm/io.h>
38#include <asm/delay.h>
39#include <mach/control.h>
40
41static void __init omap_ldp_init_irq(void)
42{
43 omap2_init_common_hw();
44 omap_init_irq();
45 omap_gpio_init();
46}
47
48static struct omap_uart_config ldp_uart_config __initdata = {
49 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
50};
51
52static struct omap_board_config_kernel ldp_config[] __initdata = {
53 { OMAP_TAG_UART, &ldp_uart_config },
54};
55
56static int __init omap_i2c_init(void)
57{
58 omap_register_i2c_bus(1, 2600, NULL, 0);
59 omap_register_i2c_bus(2, 400, NULL, 0);
60 omap_register_i2c_bus(3, 400, NULL, 0);
61 return 0;
62}
63
64static void __init omap_ldp_init(void)
65{
66 omap_i2c_init();
67 omap_board_config = ldp_config;
68 omap_board_config_size = ARRAY_SIZE(ldp_config);
69 omap_serial_init();
70}
71
72static void __init omap_ldp_map_io(void)
73{
74 omap2_set_globals_343x();
75 omap2_map_common_io();
76}
77
78MACHINE_START(OMAP_LDP, "OMAP LDP board")
79 .phys_io = 0x48000000,
80 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
81 .boot_params = 0x80000100,
82 .map_io = omap_ldp_map_io,
83 .init_irq = omap_ldp_init_irq,
84 .init_machine = omap_ldp_init,
85 .timer = &omap_timer,
86MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
new file mode 100644
index 000000000000..baa79674e9d5
--- /dev/null
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -0,0 +1,244 @@
1/*
2 * linux/arch/arm/mach-omap2/board-omap3beagle.c
3 *
4 * Copyright (C) 2008 Texas Instruments
5 *
6 * Modified from mach-omap2/board-3430sdp.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/leds.h>
23#include <linux/gpio.h>
24#include <linux/input.h>
25#include <linux/gpio_keys.h>
26
27#include <linux/mtd/mtd.h>
28#include <linux/mtd/partitions.h>
29#include <linux/mtd/nand.h>
30
31#include <mach/hardware.h>
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/flash.h>
36
37#include <mach/board.h>
38#include <mach/common.h>
39#include <mach/gpmc.h>
40#include <mach/nand.h>
41
42
43#define GPMC_CS0_BASE 0x60
44#define GPMC_CS_SIZE 0x30
45
46#define NAND_BLOCK_SIZE SZ_128K
47
48static struct mtd_partition omap3beagle_nand_partitions[] = {
49 /* All the partition sizes are listed in terms of NAND block size */
50 {
51 .name = "X-Loader",
52 .offset = 0,
53 .size = 4 * NAND_BLOCK_SIZE,
54 .mask_flags = MTD_WRITEABLE, /* force read-only */
55 },
56 {
57 .name = "U-Boot",
58 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
59 .size = 15 * NAND_BLOCK_SIZE,
60 .mask_flags = MTD_WRITEABLE, /* force read-only */
61 },
62 {
63 .name = "U-Boot Env",
64 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
65 .size = 1 * NAND_BLOCK_SIZE,
66 },
67 {
68 .name = "Kernel",
69 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
70 .size = 32 * NAND_BLOCK_SIZE,
71 },
72 {
73 .name = "File System",
74 .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
75 .size = MTDPART_SIZ_FULL,
76 },
77};
78
79static struct omap_nand_platform_data omap3beagle_nand_data = {
80 .options = NAND_BUSWIDTH_16,
81 .parts = omap3beagle_nand_partitions,
82 .nr_parts = ARRAY_SIZE(omap3beagle_nand_partitions),
83 .dma_channel = -1, /* disable DMA in OMAP NAND driver */
84 .nand_setup = NULL,
85 .dev_ready = NULL,
86};
87
88static struct resource omap3beagle_nand_resource = {
89 .flags = IORESOURCE_MEM,
90};
91
92static struct platform_device omap3beagle_nand_device = {
93 .name = "omap2-nand",
94 .id = -1,
95 .dev = {
96 .platform_data = &omap3beagle_nand_data,
97 },
98 .num_resources = 1,
99 .resource = &omap3beagle_nand_resource,
100};
101
102static struct omap_uart_config omap3_beagle_uart_config __initdata = {
103 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
104};
105
106static void __init omap3_beagle_init_irq(void)
107{
108 omap2_init_common_hw();
109 omap_init_irq();
110 omap_gpio_init();
111}
112
113static struct platform_device omap3_beagle_lcd_device = {
114 .name = "omap3beagle_lcd",
115 .id = -1,
116};
117
118static struct omap_lcd_config omap3_beagle_lcd_config __initdata = {
119 .ctrl_name = "internal",
120};
121
122static struct gpio_led gpio_leds[] = {
123 {
124 .name = "beagleboard::usr0",
125 .default_trigger = "heartbeat",
126 .gpio = 150,
127 },
128 {
129 .name = "beagleboard::usr1",
130 .default_trigger = "mmc0",
131 .gpio = 149,
132 },
133};
134
135static struct gpio_led_platform_data gpio_led_info = {
136 .leds = gpio_leds,
137 .num_leds = ARRAY_SIZE(gpio_leds),
138};
139
140static struct platform_device leds_gpio = {
141 .name = "leds-gpio",
142 .id = -1,
143 .dev = {
144 .platform_data = &gpio_led_info,
145 },
146};
147
148static struct gpio_keys_button gpio_buttons[] = {
149 {
150 .code = BTN_EXTRA,
151 .gpio = 7,
152 .desc = "user",
153 .wakeup = 1,
154 },
155};
156
157static struct gpio_keys_platform_data gpio_key_info = {
158 .buttons = gpio_buttons,
159 .nbuttons = ARRAY_SIZE(gpio_buttons),
160};
161
162static struct platform_device keys_gpio = {
163 .name = "gpio-keys",
164 .id = -1,
165 .dev = {
166 .platform_data = &gpio_key_info,
167 },
168};
169
170static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
171 { OMAP_TAG_UART, &omap3_beagle_uart_config },
172 { OMAP_TAG_LCD, &omap3_beagle_lcd_config },
173};
174
175static struct platform_device *omap3_beagle_devices[] __initdata = {
176 &omap3_beagle_lcd_device,
177 &leds_gpio,
178 &keys_gpio,
179};
180
181static void __init omap3beagle_flash_init(void)
182{
183 u8 cs = 0;
184 u8 nandcs = GPMC_CS_NUM + 1;
185
186 u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
187
188 /* find out the chip-select on which NAND exists */
189 while (cs < GPMC_CS_NUM) {
190 u32 ret = 0;
191 ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
192
193 if ((ret & 0xC00) == 0x800) {
194 printk(KERN_INFO "Found NAND on CS%d\n", cs);
195 if (nandcs > GPMC_CS_NUM)
196 nandcs = cs;
197 }
198 cs++;
199 }
200
201 if (nandcs > GPMC_CS_NUM) {
202 printk(KERN_INFO "NAND: Unable to find configuration "
203 "in GPMC\n ");
204 return;
205 }
206
207 if (nandcs < GPMC_CS_NUM) {
208 omap3beagle_nand_data.cs = nandcs;
209 omap3beagle_nand_data.gpmc_cs_baseaddr = (void *)
210 (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
211 omap3beagle_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add);
212
213 printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
214 if (platform_device_register(&omap3beagle_nand_device) < 0)
215 printk(KERN_ERR "Unable to register NAND device\n");
216 }
217}
218
219static void __init omap3_beagle_init(void)
220{
221 platform_add_devices(omap3_beagle_devices,
222 ARRAY_SIZE(omap3_beagle_devices));
223 omap_board_config = omap3_beagle_config;
224 omap_board_config_size = ARRAY_SIZE(omap3_beagle_config);
225 omap_serial_init();
226 omap3beagle_flash_init();
227}
228
229static void __init omap3_beagle_map_io(void)
230{
231 omap2_set_globals_343x();
232 omap2_map_common_io();
233}
234
235MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
236 /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
237 .phys_io = 0x48000000,
238 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
239 .boot_params = 0x80000100,
240 .map_io = omap3_beagle_map_io,
241 .init_irq = omap3_beagle_init_irq,
242 .init_machine = omap3_beagle_init,
243 .timer = &omap_timer,
244MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
new file mode 100644
index 000000000000..e09aa59a399c
--- /dev/null
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -0,0 +1,242 @@
1/*
2 * board-overo.c (Gumstix Overo)
3 *
4 * Initial code: Steve Sakoman <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/init.h>
26#include <linux/io.h>
27#include <linux/kernel.h>
28#include <linux/platform_device.h>
29
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h>
32#include <linux/mtd/partitions.h>
33
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/flash.h>
37#include <asm/mach/map.h>
38
39#include <mach/board-overo.h>
40#include <mach/board.h>
41#include <mach/common.h>
42#include <mach/gpio.h>
43#include <mach/gpmc.h>
44#include <mach/hardware.h>
45#include <mach/nand.h>
46
47#define NAND_BLOCK_SIZE SZ_128K
48#define GPMC_CS0_BASE 0x60
49#define GPMC_CS_SIZE 0x30
50
51static struct mtd_partition overo_nand_partitions[] = {
52 {
53 .name = "xloader",
54 .offset = 0, /* Offset = 0x00000 */
55 .size = 4 * NAND_BLOCK_SIZE,
56 .mask_flags = MTD_WRITEABLE
57 },
58 {
59 .name = "uboot",
60 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
61 .size = 14 * NAND_BLOCK_SIZE,
62 },
63 {
64 .name = "uboot environment",
65 .offset = MTDPART_OFS_APPEND, /* Offset = 0x240000 */
66 .size = 2 * NAND_BLOCK_SIZE,
67 },
68 {
69 .name = "linux",
70 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
71 .size = 32 * NAND_BLOCK_SIZE,
72 },
73 {
74 .name = "rootfs",
75 .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
76 .size = MTDPART_SIZ_FULL,
77 },
78};
79
80static struct omap_nand_platform_data overo_nand_data = {
81 .parts = overo_nand_partitions,
82 .nr_parts = ARRAY_SIZE(overo_nand_partitions),
83 .dma_channel = -1, /* disable DMA in OMAP NAND driver */
84};
85
86static struct resource overo_nand_resource = {
87 .flags = IORESOURCE_MEM,
88};
89
90static struct platform_device overo_nand_device = {
91 .name = "omap2-nand",
92 .id = -1,
93 .dev = {
94 .platform_data = &overo_nand_data,
95 },
96 .num_resources = 1,
97 .resource = &overo_nand_resource,
98};
99
100
101static void __init overo_flash_init(void)
102{
103 u8 cs = 0;
104 u8 nandcs = GPMC_CS_NUM + 1;
105
106 u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
107
108 /* find out the chip-select on which NAND exists */
109 while (cs < GPMC_CS_NUM) {
110 u32 ret = 0;
111 ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
112
113 if ((ret & 0xC00) == 0x800) {
114 printk(KERN_INFO "Found NAND on CS%d\n", cs);
115 if (nandcs > GPMC_CS_NUM)
116 nandcs = cs;
117 }
118 cs++;
119 }
120
121 if (nandcs > GPMC_CS_NUM) {
122 printk(KERN_INFO "NAND: Unable to find configuration "
123 "in GPMC\n ");
124 return;
125 }
126
127 if (nandcs < GPMC_CS_NUM) {
128 overo_nand_data.cs = nandcs;
129 overo_nand_data.gpmc_cs_baseaddr = (void *)
130 (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
131 overo_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add);
132
133 printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
134 if (platform_device_register(&overo_nand_device) < 0)
135 printk(KERN_ERR "Unable to register NAND device\n");
136 }
137}
138static struct omap_uart_config overo_uart_config __initdata = {
139 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
140};
141
142static int __init overo_i2c_init(void)
143{
144 /* i2c2 pins are used for gpio */
145 omap_register_i2c_bus(3, 400, NULL, 0);
146 return 0;
147}
148
149static void __init overo_init_irq(void)
150{
151 omap2_init_common_hw();
152 omap_init_irq();
153 omap_gpio_init();
154}
155
156static struct platform_device overo_lcd_device = {
157 .name = "overo_lcd",
158 .id = -1,
159};
160
161static struct omap_lcd_config overo_lcd_config __initdata = {
162 .ctrl_name = "internal",
163};
164
165static struct omap_board_config_kernel overo_config[] __initdata = {
166 { OMAP_TAG_UART, &overo_uart_config },
167 { OMAP_TAG_LCD, &overo_lcd_config },
168};
169
170static struct platform_device *overo_devices[] __initdata = {
171 &overo_lcd_device,
172};
173
174static void __init overo_init(void)
175{
176 overo_i2c_init();
177 platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
178 omap_board_config = overo_config;
179 omap_board_config_size = ARRAY_SIZE(overo_config);
180 omap_serial_init();
181 overo_flash_init();
182
183 if ((gpio_request(OVERO_GPIO_W2W_NRESET,
184 "OVERO_GPIO_W2W_NRESET") == 0) &&
185 (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
186 gpio_export(OVERO_GPIO_W2W_NRESET, 0);
187 gpio_set_value(OVERO_GPIO_W2W_NRESET, 0);
188 udelay(10);
189 gpio_set_value(OVERO_GPIO_W2W_NRESET, 1);
190 } else {
191 printk(KERN_ERR "could not obtain gpio for "
192 "OVERO_GPIO_W2W_NRESET\n");
193 }
194
195 if ((gpio_request(OVERO_GPIO_BT_XGATE, "OVERO_GPIO_BT_XGATE") == 0) &&
196 (gpio_direction_output(OVERO_GPIO_BT_XGATE, 0) == 0))
197 gpio_export(OVERO_GPIO_BT_XGATE, 0);
198 else
199 printk(KERN_ERR "could not obtain gpio for OVERO_GPIO_BT_XGATE\n");
200
201 if ((gpio_request(OVERO_GPIO_BT_NRESET, "OVERO_GPIO_BT_NRESET") == 0) &&
202 (gpio_direction_output(OVERO_GPIO_BT_NRESET, 1) == 0)) {
203 gpio_export(OVERO_GPIO_BT_NRESET, 0);
204 gpio_set_value(OVERO_GPIO_BT_NRESET, 0);
205 mdelay(6);
206 gpio_set_value(OVERO_GPIO_BT_NRESET, 1);
207 } else {
208 printk(KERN_ERR "could not obtain gpio for "
209 "OVERO_GPIO_BT_NRESET\n");
210 }
211
212 if ((gpio_request(OVERO_GPIO_USBH_CPEN, "OVERO_GPIO_USBH_CPEN") == 0) &&
213 (gpio_direction_output(OVERO_GPIO_USBH_CPEN, 1) == 0))
214 gpio_export(OVERO_GPIO_USBH_CPEN, 0);
215 else
216 printk(KERN_ERR "could not obtain gpio for "
217 "OVERO_GPIO_USBH_CPEN\n");
218
219 if ((gpio_request(OVERO_GPIO_USBH_NRESET,
220 "OVERO_GPIO_USBH_NRESET") == 0) &&
221 (gpio_direction_output(OVERO_GPIO_USBH_NRESET, 1) == 0))
222 gpio_export(OVERO_GPIO_USBH_NRESET, 0);
223 else
224 printk(KERN_ERR "could not obtain gpio for "
225 "OVERO_GPIO_USBH_NRESET\n");
226}
227
228static void __init overo_map_io(void)
229{
230 omap2_set_globals_343x();
231 omap2_map_common_io();
232}
233
234MACHINE_START(OVERO, "Gumstix Overo")
235 .phys_io = 0x48000000,
236 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
237 .boot_params = 0x80000100,
238 .map_io = overo_map_io,
239 .init_irq = overo_init_irq,
240 .init_machine = overo_init,
241 .timer = &omap_timer,
242MACHINE_END
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 97cde3d3611d..ad721e0cbf7a 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -25,6 +25,7 @@
25#include <linux/bitops.h> 25#include <linux/bitops.h>
26 26
27#include <mach/clock.h> 27#include <mach/clock.h>
28#include <mach/clockdomain.h>
28#include <mach/sram.h> 29#include <mach/sram.h>
29#include <mach/cpu.h> 30#include <mach/cpu.h>
30#include <asm/div64.h> 31#include <asm/div64.h>
@@ -61,10 +62,36 @@
61u8 cpu_mask; 62u8 cpu_mask;
62 63
63/*------------------------------------------------------------------------- 64/*-------------------------------------------------------------------------
64 * Omap2 specific clock functions 65 * OMAP2/3 specific clock functions
65 *-------------------------------------------------------------------------*/ 66 *-------------------------------------------------------------------------*/
66 67
67/** 68/**
69 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
70 * @clk: OMAP clock struct ptr to use
71 *
72 * Convert a clockdomain name stored in a struct clk 'clk' into a
73 * clockdomain pointer, and save it into the struct clk. Intended to be
74 * called during clk_register(). No return value.
75 */
76void omap2_init_clk_clkdm(struct clk *clk)
77{
78 struct clockdomain *clkdm;
79
80 if (!clk->clkdm_name)
81 return;
82
83 clkdm = clkdm_lookup(clk->clkdm_name);
84 if (clkdm) {
85 pr_debug("clock: associated clk %s to clkdm %s\n",
86 clk->name, clk->clkdm_name);
87 clk->clkdm = clkdm;
88 } else {
89 pr_debug("clock: could not associate clk %s to "
90 "clkdm %s\n", clk->name, clk->clkdm_name);
91 }
92}
93
94/**
68 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware 95 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
69 * @clk: OMAP clock struct ptr to use 96 * @clk: OMAP clock struct ptr to use
70 * 97 *
@@ -250,7 +277,7 @@ int _omap2_clk_enable(struct clk *clk)
250 if (clk->enable) 277 if (clk->enable)
251 return clk->enable(clk); 278 return clk->enable(clk);
252 279
253 if (unlikely(clk->enable_reg == 0)) { 280 if (unlikely(clk->enable_reg == NULL)) {
254 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 281 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
255 clk->name); 282 clk->name);
256 return 0; /* REVISIT: -EINVAL */ 283 return 0; /* REVISIT: -EINVAL */
@@ -282,7 +309,7 @@ void _omap2_clk_disable(struct clk *clk)
282 return; 309 return;
283 } 310 }
284 311
285 if (clk->enable_reg == 0) { 312 if (clk->enable_reg == NULL) {
286 /* 313 /*
287 * 'Independent' here refers to a clock which is not 314 * 'Independent' here refers to a clock which is not
288 * controlled by its parent. 315 * controlled by its parent.
@@ -307,6 +334,9 @@ void omap2_clk_disable(struct clk *clk)
307 _omap2_clk_disable(clk); 334 _omap2_clk_disable(clk);
308 if (likely((u32)clk->parent)) 335 if (likely((u32)clk->parent))
309 omap2_clk_disable(clk->parent); 336 omap2_clk_disable(clk->parent);
337 if (clk->clkdm)
338 omap2_clkdm_clk_disable(clk->clkdm, clk);
339
310 } 340 }
311} 341}
312 342
@@ -323,11 +353,19 @@ int omap2_clk_enable(struct clk *clk)
323 return ret; 353 return ret;
324 } 354 }
325 355
356 if (clk->clkdm)
357 omap2_clkdm_clk_enable(clk->clkdm, clk);
358
326 ret = _omap2_clk_enable(clk); 359 ret = _omap2_clk_enable(clk);
327 360
328 if (unlikely(ret != 0) && clk->parent) { 361 if (unlikely(ret != 0)) {
329 omap2_clk_disable(clk->parent); 362 if (clk->clkdm)
330 clk->usecount--; 363 omap2_clkdm_clk_disable(clk->clkdm, clk);
364
365 if (clk->parent) {
366 omap2_clk_disable(clk->parent);
367 clk->usecount--;
368 }
331 } 369 }
332 } 370 }
333 371
@@ -476,7 +514,7 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
476/* Given a clock and a rate apply a clock specific rounding function */ 514/* Given a clock and a rate apply a clock specific rounding function */
477long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 515long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
478{ 516{
479 if (clk->round_rate != 0) 517 if (clk->round_rate != NULL)
480 return clk->round_rate(clk, rate); 518 return clk->round_rate(clk, rate);
481 519
482 if (clk->flags & RATE_FIXED) 520 if (clk->flags & RATE_FIXED)
@@ -565,7 +603,7 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
565 */ 603 */
566void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) 604void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
567{ 605{
568 if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0))) 606 if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
569 return NULL; 607 return NULL;
570 608
571 *field_mask = clk->clksel_mask; 609 *field_mask = clk->clksel_mask;
@@ -585,7 +623,7 @@ u32 omap2_clksel_get_divisor(struct clk *clk)
585 void __iomem *div_addr; 623 void __iomem *div_addr;
586 624
587 div_addr = omap2_get_clksel(clk, &field_mask); 625 div_addr = omap2_get_clksel(clk, &field_mask);
588 if (div_addr == 0) 626 if (div_addr == NULL)
589 return 0; 627 return 0;
590 628
591 field_val = __raw_readl(div_addr) & field_mask; 629 field_val = __raw_readl(div_addr) & field_mask;
@@ -604,7 +642,7 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
604 return -EINVAL; 642 return -EINVAL;
605 643
606 div_addr = omap2_get_clksel(clk, &field_mask); 644 div_addr = omap2_get_clksel(clk, &field_mask);
607 if (div_addr == 0) 645 if (div_addr == NULL)
608 return -EINVAL; 646 return -EINVAL;
609 647
610 field_val = omap2_divisor_to_clksel(clk, new_div); 648 field_val = omap2_divisor_to_clksel(clk, new_div);
@@ -642,7 +680,7 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
642 return -EINVAL; 680 return -EINVAL;
643 681
644 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ 682 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
645 if (clk->set_rate != 0) 683 if (clk->set_rate != NULL)
646 ret = clk->set_rate(clk, rate); 684 ret = clk->set_rate(clk, rate);
647 685
648 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) 686 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
@@ -663,7 +701,7 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
663 const struct clksel_rate *clkr; 701 const struct clksel_rate *clkr;
664 702
665 *parent_div = 0; 703 *parent_div = 0;
666 *src_addr = 0; 704 *src_addr = NULL;
667 705
668 clks = omap2_get_clksel_by_parent(clk, src_clk); 706 clks = omap2_get_clksel_by_parent(clk, src_clk);
669 if (clks == NULL) 707 if (clks == NULL)
@@ -704,7 +742,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
704 742
705 field_val = omap2_clksel_get_src_field(&src_addr, new_parent, 743 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
706 &field_mask, clk, &parent_div); 744 &field_mask, clk, &parent_div);
707 if (src_addr == 0) 745 if (src_addr == NULL)
708 return -EINVAL; 746 return -EINVAL;
709 747
710 if (clk->usecount > 0) 748 if (clk->usecount > 0)
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 626e5fa93b6a..1fb330e0847d 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
21/* The maximum error between a target DPLL rate and the rounded rate in Hz */ 21/* The maximum error between a target DPLL rate and the rounded rate in Hz */
22#define DEFAULT_DPLL_RATE_TOLERANCE 50000 22#define DEFAULT_DPLL_RATE_TOLERANCE 50000
23 23
24int omap2_clk_init(void);
24int omap2_clk_enable(struct clk *clk); 25int omap2_clk_enable(struct clk *clk);
25void omap2_clk_disable(struct clk *clk); 26void omap2_clk_disable(struct clk *clk);
26long omap2_clk_round_rate(struct clk *clk, unsigned long rate); 27long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
@@ -36,6 +37,7 @@ void omap2_clk_disable_unused(struct clk *clk);
36#endif 37#endif
37 38
38void omap2_clksel_recalc(struct clk *clk); 39void omap2_clksel_recalc(struct clk *clk);
40void omap2_init_clk_clkdm(struct clk *clk);
39void omap2_init_clksel_parent(struct clk *clk); 41void omap2_init_clksel_parent(struct clk *clk);
40u32 omap2_clksel_get_divisor(struct clk *clk); 42u32 omap2_clksel_get_divisor(struct clk *clk);
41u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 43u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index be4e25554e05..242a19d86ccd 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -626,6 +626,7 @@ static struct clk func_32k_ck = {
626 .rate = 32000, 626 .rate = 32000,
627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
628 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, 628 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
629 .clkdm_name = "wkup_clkdm",
629 .recalc = &propagate_rate, 630 .recalc = &propagate_rate,
630}; 631};
631 632
@@ -634,17 +635,19 @@ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
634 .name = "osc_ck", 635 .name = "osc_ck",
635 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 636 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
636 RATE_PROPAGATES, 637 RATE_PROPAGATES,
638 .clkdm_name = "wkup_clkdm",
637 .enable = &omap2_enable_osc_ck, 639 .enable = &omap2_enable_osc_ck,
638 .disable = &omap2_disable_osc_ck, 640 .disable = &omap2_disable_osc_ck,
639 .recalc = &omap2_osc_clk_recalc, 641 .recalc = &omap2_osc_clk_recalc,
640}; 642};
641 643
642/* With out modem likely 12MHz, with modem likely 13MHz */ 644/* Without modem likely 12MHz, with modem likely 13MHz */
643static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ 645static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
644 .name = "sys_ck", /* ~ ref_clk also */ 646 .name = "sys_ck", /* ~ ref_clk also */
645 .parent = &osc_ck, 647 .parent = &osc_ck,
646 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 648 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
647 ALWAYS_ENABLED | RATE_PROPAGATES, 649 ALWAYS_ENABLED | RATE_PROPAGATES,
650 .clkdm_name = "wkup_clkdm",
648 .recalc = &omap2_sys_clk_recalc, 651 .recalc = &omap2_sys_clk_recalc,
649}; 652};
650 653
@@ -653,6 +656,7 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
653 .rate = 54000000, 656 .rate = 54000000,
654 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 657 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
655 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, 658 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
659 .clkdm_name = "wkup_clkdm",
656 .recalc = &propagate_rate, 660 .recalc = &propagate_rate,
657}; 661};
658 662
@@ -684,6 +688,7 @@ static struct clk dpll_ck = {
684 .dpll_data = &dpll_dd, 688 .dpll_data = &dpll_dd,
685 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 689 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
686 RATE_PROPAGATES | ALWAYS_ENABLED, 690 RATE_PROPAGATES | ALWAYS_ENABLED,
691 .clkdm_name = "wkup_clkdm",
687 .recalc = &omap2_dpllcore_recalc, 692 .recalc = &omap2_dpllcore_recalc,
688 .set_rate = &omap2_reprogram_dpllcore, 693 .set_rate = &omap2_reprogram_dpllcore,
689}; 694};
@@ -694,6 +699,7 @@ static struct clk apll96_ck = {
694 .rate = 96000000, 699 .rate = 96000000,
695 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 700 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
696 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, 701 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
702 .clkdm_name = "wkup_clkdm",
697 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 703 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
698 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, 704 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
699 .enable = &omap2_clk_fixed_enable, 705 .enable = &omap2_clk_fixed_enable,
@@ -707,6 +713,7 @@ static struct clk apll54_ck = {
707 .rate = 54000000, 713 .rate = 54000000,
708 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 714 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
709 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, 715 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
716 .clkdm_name = "wkup_clkdm",
710 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 717 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
711 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, 718 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
712 .enable = &omap2_clk_fixed_enable, 719 .enable = &omap2_clk_fixed_enable,
@@ -741,6 +748,7 @@ static struct clk func_54m_ck = {
741 .parent = &apll54_ck, /* can also be alt_clk */ 748 .parent = &apll54_ck, /* can also be alt_clk */
742 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 749 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
743 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, 750 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
751 .clkdm_name = "wkup_clkdm",
744 .init = &omap2_init_clksel_parent, 752 .init = &omap2_init_clksel_parent,
745 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 753 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
746 .clksel_mask = OMAP24XX_54M_SOURCE, 754 .clksel_mask = OMAP24XX_54M_SOURCE,
@@ -753,6 +761,7 @@ static struct clk core_ck = {
753 .parent = &dpll_ck, /* can also be 32k */ 761 .parent = &dpll_ck, /* can also be 32k */
754 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 762 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
755 ALWAYS_ENABLED | RATE_PROPAGATES, 763 ALWAYS_ENABLED | RATE_PROPAGATES,
764 .clkdm_name = "wkup_clkdm",
756 .recalc = &followparent_recalc, 765 .recalc = &followparent_recalc,
757}; 766};
758 767
@@ -779,6 +788,7 @@ static struct clk func_96m_ck = {
779 .parent = &apll96_ck, 788 .parent = &apll96_ck,
780 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 789 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
781 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, 790 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
791 .clkdm_name = "wkup_clkdm",
782 .init = &omap2_init_clksel_parent, 792 .init = &omap2_init_clksel_parent,
783 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 793 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
784 .clksel_mask = OMAP2430_96M_SOURCE, 794 .clksel_mask = OMAP2430_96M_SOURCE,
@@ -811,6 +821,7 @@ static struct clk func_48m_ck = {
811 .parent = &apll96_ck, /* 96M or Alt */ 821 .parent = &apll96_ck, /* 96M or Alt */
812 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 822 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
813 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, 823 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
824 .clkdm_name = "wkup_clkdm",
814 .init = &omap2_init_clksel_parent, 825 .init = &omap2_init_clksel_parent,
815 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 826 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
816 .clksel_mask = OMAP24XX_48M_SOURCE, 827 .clksel_mask = OMAP24XX_48M_SOURCE,
@@ -826,6 +837,7 @@ static struct clk func_12m_ck = {
826 .fixed_div = 4, 837 .fixed_div = 4,
827 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 838 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
828 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, 839 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
840 .clkdm_name = "wkup_clkdm",
829 .recalc = &omap2_fixed_divisor_recalc, 841 .recalc = &omap2_fixed_divisor_recalc,
830}; 842};
831 843
@@ -878,6 +890,7 @@ static struct clk sys_clkout_src = {
878 .parent = &func_54m_ck, 890 .parent = &func_54m_ck,
879 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 891 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
880 RATE_PROPAGATES, 892 RATE_PROPAGATES,
893 .clkdm_name = "wkup_clkdm",
881 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 894 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
882 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, 895 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
883 .init = &omap2_init_clksel_parent, 896 .init = &omap2_init_clksel_parent,
@@ -908,6 +921,7 @@ static struct clk sys_clkout = {
908 .parent = &sys_clkout_src, 921 .parent = &sys_clkout_src,
909 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 922 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
910 PARENT_CONTROLS_CLOCK, 923 PARENT_CONTROLS_CLOCK,
924 .clkdm_name = "wkup_clkdm",
911 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 925 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
912 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, 926 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
913 .clksel = sys_clkout_clksel, 927 .clksel = sys_clkout_clksel,
@@ -921,6 +935,7 @@ static struct clk sys_clkout2_src = {
921 .name = "sys_clkout2_src", 935 .name = "sys_clkout2_src",
922 .parent = &func_54m_ck, 936 .parent = &func_54m_ck,
923 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES, 937 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
938 .clkdm_name = "wkup_clkdm",
924 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 939 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
925 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, 940 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
926 .init = &omap2_init_clksel_parent, 941 .init = &omap2_init_clksel_parent,
@@ -942,6 +957,7 @@ static struct clk sys_clkout2 = {
942 .name = "sys_clkout2", 957 .name = "sys_clkout2",
943 .parent = &sys_clkout2_src, 958 .parent = &sys_clkout2_src,
944 .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK, 959 .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
960 .clkdm_name = "wkup_clkdm",
945 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 961 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
946 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, 962 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
947 .clksel = sys_clkout2_clksel, 963 .clksel = sys_clkout2_clksel,
@@ -954,6 +970,7 @@ static struct clk emul_ck = {
954 .name = "emul_ck", 970 .name = "emul_ck",
955 .parent = &func_54m_ck, 971 .parent = &func_54m_ck,
956 .flags = CLOCK_IN_OMAP242X, 972 .flags = CLOCK_IN_OMAP242X,
973 .clkdm_name = "wkup_clkdm",
957 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, 974 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
958 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, 975 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
959 .recalc = &followparent_recalc, 976 .recalc = &followparent_recalc,
@@ -990,12 +1007,13 @@ static struct clk mpu_ck = { /* Control cpu */
990 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
991 ALWAYS_ENABLED | DELAYED_APP | 1008 ALWAYS_ENABLED | DELAYED_APP |
992 CONFIG_PARTICIPANT | RATE_PROPAGATES, 1009 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1010 .clkdm_name = "mpu_clkdm",
993 .init = &omap2_init_clksel_parent, 1011 .init = &omap2_init_clksel_parent,
994 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), 1012 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
995 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, 1013 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
996 .clksel = mpu_clksel, 1014 .clksel = mpu_clksel,
997 .recalc = &omap2_clksel_recalc, 1015 .recalc = &omap2_clksel_recalc,
998 .round_rate = &omap2_clksel_round_rate, 1016 .round_rate = &omap2_clksel_round_rate,
999 .set_rate = &omap2_clksel_set_rate 1017 .set_rate = &omap2_clksel_set_rate
1000}; 1018};
1001 1019
@@ -1031,6 +1049,7 @@ static struct clk dsp_fck = {
1031 .parent = &core_ck, 1049 .parent = &core_ck,
1032 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | 1050 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1033 CONFIG_PARTICIPANT | RATE_PROPAGATES, 1051 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1052 .clkdm_name = "dsp_clkdm",
1034 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1053 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1035 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 1054 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1036 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), 1055 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
@@ -1054,10 +1073,7 @@ static const struct clksel dsp_irate_ick_clksel[] = {
1054 { .parent = NULL } 1073 { .parent = NULL }
1055}; 1074};
1056 1075
1057/* 1076/* This clock does not exist as such in the TRM. */
1058 * This clock does not exist as such in the TRM, but is added to
1059 * separate source selection from XXX
1060 */
1061static struct clk dsp_irate_ick = { 1077static struct clk dsp_irate_ick = {
1062 .name = "dsp_irate_ick", 1078 .name = "dsp_irate_ick",
1063 .parent = &dsp_fck, 1079 .parent = &dsp_fck,
@@ -1089,11 +1105,17 @@ static struct clk iva2_1_ick = {
1089 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 1105 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1090}; 1106};
1091 1107
1108/*
1109 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1110 * the C54x, but which is contained in the DSP powerdomain. Does not
1111 * exist on later OMAPs.
1112 */
1092static struct clk iva1_ifck = { 1113static struct clk iva1_ifck = {
1093 .name = "iva1_ifck", 1114 .name = "iva1_ifck",
1094 .parent = &core_ck, 1115 .parent = &core_ck,
1095 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | 1116 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1096 RATE_PROPAGATES | DELAYED_APP, 1117 RATE_PROPAGATES | DELAYED_APP,
1118 .clkdm_name = "iva1_clkdm",
1097 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1119 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1098 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, 1120 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
1099 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), 1121 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
@@ -1109,6 +1131,7 @@ static struct clk iva1_mpu_int_ifck = {
1109 .name = "iva1_mpu_int_ifck", 1131 .name = "iva1_mpu_int_ifck",
1110 .parent = &iva1_ifck, 1132 .parent = &iva1_ifck,
1111 .flags = CLOCK_IN_OMAP242X, 1133 .flags = CLOCK_IN_OMAP242X,
1134 .clkdm_name = "iva1_clkdm",
1112 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1135 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1113 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, 1136 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1114 .fixed_div = 2, 1137 .fixed_div = 2,
@@ -1156,6 +1179,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1156 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1179 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1157 ALWAYS_ENABLED | DELAYED_APP | 1180 ALWAYS_ENABLED | DELAYED_APP |
1158 CONFIG_PARTICIPANT | RATE_PROPAGATES, 1181 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1182 .clkdm_name = "core_l3_clkdm",
1159 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1183 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1160 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, 1184 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
1161 .clksel = core_l3_clksel, 1185 .clksel = core_l3_clksel,
@@ -1177,11 +1201,13 @@ static const struct clksel usb_l4_ick_clksel[] = {
1177 { .parent = NULL }, 1201 { .parent = NULL },
1178}; 1202};
1179 1203
1204/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1180static struct clk usb_l4_ick = { /* FS-USB interface clock */ 1205static struct clk usb_l4_ick = { /* FS-USB interface clock */
1181 .name = "usb_l4_ick", 1206 .name = "usb_l4_ick",
1182 .parent = &core_l3_ck, 1207 .parent = &core_l3_ck,
1183 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1208 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1184 DELAYED_APP | CONFIG_PARTICIPANT, 1209 DELAYED_APP | CONFIG_PARTICIPANT,
1210 .clkdm_name = "core_l4_clkdm",
1185 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1211 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1186 .enable_bit = OMAP24XX_EN_USB_SHIFT, 1212 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1187 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1213 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
@@ -1193,10 +1219,42 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
1193}; 1219};
1194 1220
1195/* 1221/*
1222 * L4 clock management domain
1223 *
1224 * This domain contains lots of interface clocks from the L4 interface, some
1225 * functional clocks. Fixed APLL functional source clocks are managed in
1226 * this domain.
1227 */
1228static const struct clksel_rate l4_core_l3_rates[] = {
1229 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1230 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1231 { .div = 0 }
1232};
1233
1234static const struct clksel l4_clksel[] = {
1235 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1236 { .parent = NULL }
1237};
1238
1239static struct clk l4_ck = { /* used both as an ick and fck */
1240 .name = "l4_ck",
1241 .parent = &core_l3_ck,
1242 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1243 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1244 .clkdm_name = "core_l4_clkdm",
1245 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1246 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
1247 .clksel = l4_clksel,
1248 .recalc = &omap2_clksel_recalc,
1249 .round_rate = &omap2_clksel_round_rate,
1250 .set_rate = &omap2_clksel_set_rate
1251};
1252
1253/*
1196 * SSI is in L3 management domain, its direct parent is core not l3, 1254 * SSI is in L3 management domain, its direct parent is core not l3,
1197 * many core power domain entities are grouped into the L3 clock 1255 * many core power domain entities are grouped into the L3 clock
1198 * domain. 1256 * domain.
1199 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK 1257 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1200 * 1258 *
1201 * ssr = core/1/2/3/4/5, sst = 1/2 ssr. 1259 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1202 */ 1260 */
@@ -1221,6 +1279,7 @@ static struct clk ssi_ssr_sst_fck = {
1221 .parent = &core_ck, 1279 .parent = &core_ck,
1222 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1280 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1223 DELAYED_APP, 1281 DELAYED_APP,
1282 .clkdm_name = "core_l3_clkdm",
1224 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1283 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1225 .enable_bit = OMAP24XX_EN_SSI_SHIFT, 1284 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1226 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1285 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
@@ -1231,6 +1290,7 @@ static struct clk ssi_ssr_sst_fck = {
1231 .set_rate = &omap2_clksel_set_rate 1290 .set_rate = &omap2_clksel_set_rate
1232}; 1291};
1233 1292
1293
1234/* 1294/*
1235 * GFX clock domain 1295 * GFX clock domain
1236 * Clocks: 1296 * Clocks:
@@ -1254,6 +1314,7 @@ static struct clk gfx_3d_fck = {
1254 .name = "gfx_3d_fck", 1314 .name = "gfx_3d_fck",
1255 .parent = &core_l3_ck, 1315 .parent = &core_l3_ck,
1256 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1316 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1317 .clkdm_name = "gfx_clkdm",
1257 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1318 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1258 .enable_bit = OMAP24XX_EN_3D_SHIFT, 1319 .enable_bit = OMAP24XX_EN_3D_SHIFT,
1259 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), 1320 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
@@ -1268,6 +1329,7 @@ static struct clk gfx_2d_fck = {
1268 .name = "gfx_2d_fck", 1329 .name = "gfx_2d_fck",
1269 .parent = &core_l3_ck, 1330 .parent = &core_l3_ck,
1270 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1331 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1332 .clkdm_name = "gfx_clkdm",
1271 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1333 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1272 .enable_bit = OMAP24XX_EN_2D_SHIFT, 1334 .enable_bit = OMAP24XX_EN_2D_SHIFT,
1273 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), 1335 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
@@ -1282,6 +1344,7 @@ static struct clk gfx_ick = {
1282 .name = "gfx_ick", /* From l3 */ 1344 .name = "gfx_ick", /* From l3 */
1283 .parent = &core_l3_ck, 1345 .parent = &core_l3_ck,
1284 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1346 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1347 .clkdm_name = "gfx_clkdm",
1285 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1348 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1286 .enable_bit = OMAP_EN_GFX_SHIFT, 1349 .enable_bit = OMAP_EN_GFX_SHIFT,
1287 .recalc = &followparent_recalc, 1350 .recalc = &followparent_recalc,
@@ -1311,6 +1374,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
1311 .name = "mdm_ick", 1374 .name = "mdm_ick",
1312 .parent = &core_ck, 1375 .parent = &core_ck,
1313 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, 1376 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1377 .clkdm_name = "mdm_clkdm",
1314 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), 1378 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1315 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, 1379 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1316 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), 1380 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
@@ -1325,52 +1389,13 @@ static struct clk mdm_osc_ck = {
1325 .name = "mdm_osc_ck", 1389 .name = "mdm_osc_ck",
1326 .parent = &osc_ck, 1390 .parent = &osc_ck,
1327 .flags = CLOCK_IN_OMAP243X, 1391 .flags = CLOCK_IN_OMAP243X,
1392 .clkdm_name = "mdm_clkdm",
1328 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), 1393 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1329 .enable_bit = OMAP2430_EN_OSC_SHIFT, 1394 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1330 .recalc = &followparent_recalc, 1395 .recalc = &followparent_recalc,
1331}; 1396};
1332 1397
1333/* 1398/*
1334 * L4 clock management domain
1335 *
1336 * This domain contains lots of interface clocks from the L4 interface, some
1337 * functional clocks. Fixed APLL functional source clocks are managed in
1338 * this domain.
1339 */
1340static const struct clksel_rate l4_core_l3_rates[] = {
1341 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1342 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1343 { .div = 0 }
1344};
1345
1346static const struct clksel l4_clksel[] = {
1347 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1348 { .parent = NULL }
1349};
1350
1351static struct clk l4_ck = { /* used both as an ick and fck */
1352 .name = "l4_ck",
1353 .parent = &core_l3_ck,
1354 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1355 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1356 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1357 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
1358 .clksel = l4_clksel,
1359 .recalc = &omap2_clksel_recalc,
1360 .round_rate = &omap2_clksel_round_rate,
1361 .set_rate = &omap2_clksel_set_rate
1362};
1363
1364static struct clk ssi_l4_ick = {
1365 .name = "ssi_l4_ick",
1366 .parent = &l4_ck,
1367 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1368 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1369 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1370 .recalc = &followparent_recalc,
1371};
1372
1373/*
1374 * DSS clock domain 1399 * DSS clock domain
1375 * CLOCKs: 1400 * CLOCKs:
1376 * DSS_L4_ICLK, DSS_L3_ICLK, 1401 * DSS_L4_ICLK, DSS_L3_ICLK,
@@ -1409,6 +1434,7 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1409 .name = "dss_ick", 1434 .name = "dss_ick",
1410 .parent = &l4_ck, /* really both l3 and l4 */ 1435 .parent = &l4_ck, /* really both l3 and l4 */
1411 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1436 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1437 .clkdm_name = "dss_clkdm",
1412 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1438 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1413 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 1439 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1414 .recalc = &followparent_recalc, 1440 .recalc = &followparent_recalc,
@@ -1419,6 +1445,7 @@ static struct clk dss1_fck = {
1419 .parent = &core_ck, /* Core or sys */ 1445 .parent = &core_ck, /* Core or sys */
1420 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1446 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1421 DELAYED_APP, 1447 DELAYED_APP,
1448 .clkdm_name = "dss_clkdm",
1422 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1449 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1423 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 1450 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1424 .init = &omap2_init_clksel_parent, 1451 .init = &omap2_init_clksel_parent,
@@ -1451,6 +1478,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
1451 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ 1478 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1452 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1479 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1453 DELAYED_APP, 1480 DELAYED_APP,
1481 .clkdm_name = "dss_clkdm",
1454 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1482 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1455 .enable_bit = OMAP24XX_EN_DSS2_SHIFT, 1483 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
1456 .init = &omap2_init_clksel_parent, 1484 .init = &omap2_init_clksel_parent,
@@ -1464,6 +1492,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
1464 .name = "dss_54m_fck", /* 54m tv clk */ 1492 .name = "dss_54m_fck", /* 54m tv clk */
1465 .parent = &func_54m_ck, 1493 .parent = &func_54m_ck,
1466 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1494 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1495 .clkdm_name = "dss_clkdm",
1467 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1468 .enable_bit = OMAP24XX_EN_TV_SHIFT, 1497 .enable_bit = OMAP24XX_EN_TV_SHIFT,
1469 .recalc = &followparent_recalc, 1498 .recalc = &followparent_recalc,
@@ -1491,6 +1520,7 @@ static struct clk gpt1_ick = {
1491 .name = "gpt1_ick", 1520 .name = "gpt1_ick",
1492 .parent = &l4_ck, 1521 .parent = &l4_ck,
1493 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1522 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1523 .clkdm_name = "core_l4_clkdm",
1494 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1524 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1495 .enable_bit = OMAP24XX_EN_GPT1_SHIFT, 1525 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1496 .recalc = &followparent_recalc, 1526 .recalc = &followparent_recalc,
@@ -1500,6 +1530,7 @@ static struct clk gpt1_fck = {
1500 .name = "gpt1_fck", 1530 .name = "gpt1_fck",
1501 .parent = &func_32k_ck, 1531 .parent = &func_32k_ck,
1502 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1532 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1533 .clkdm_name = "core_l4_clkdm",
1503 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 1534 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1504 .enable_bit = OMAP24XX_EN_GPT1_SHIFT, 1535 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1505 .init = &omap2_init_clksel_parent, 1536 .init = &omap2_init_clksel_parent,
@@ -1515,6 +1546,7 @@ static struct clk gpt2_ick = {
1515 .name = "gpt2_ick", 1546 .name = "gpt2_ick",
1516 .parent = &l4_ck, 1547 .parent = &l4_ck,
1517 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1548 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1549 .clkdm_name = "core_l4_clkdm",
1518 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1550 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1519 .enable_bit = OMAP24XX_EN_GPT2_SHIFT, 1551 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1520 .recalc = &followparent_recalc, 1552 .recalc = &followparent_recalc,
@@ -1524,6 +1556,7 @@ static struct clk gpt2_fck = {
1524 .name = "gpt2_fck", 1556 .name = "gpt2_fck",
1525 .parent = &func_32k_ck, 1557 .parent = &func_32k_ck,
1526 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1558 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1559 .clkdm_name = "core_l4_clkdm",
1527 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1560 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1528 .enable_bit = OMAP24XX_EN_GPT2_SHIFT, 1561 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1529 .init = &omap2_init_clksel_parent, 1562 .init = &omap2_init_clksel_parent,
@@ -1537,6 +1570,7 @@ static struct clk gpt3_ick = {
1537 .name = "gpt3_ick", 1570 .name = "gpt3_ick",
1538 .parent = &l4_ck, 1571 .parent = &l4_ck,
1539 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1572 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1573 .clkdm_name = "core_l4_clkdm",
1540 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1574 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1541 .enable_bit = OMAP24XX_EN_GPT3_SHIFT, 1575 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1542 .recalc = &followparent_recalc, 1576 .recalc = &followparent_recalc,
@@ -1546,6 +1580,7 @@ static struct clk gpt3_fck = {
1546 .name = "gpt3_fck", 1580 .name = "gpt3_fck",
1547 .parent = &func_32k_ck, 1581 .parent = &func_32k_ck,
1548 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1582 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1583 .clkdm_name = "core_l4_clkdm",
1549 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1584 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1550 .enable_bit = OMAP24XX_EN_GPT3_SHIFT, 1585 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1551 .init = &omap2_init_clksel_parent, 1586 .init = &omap2_init_clksel_parent,
@@ -1559,6 +1594,7 @@ static struct clk gpt4_ick = {
1559 .name = "gpt4_ick", 1594 .name = "gpt4_ick",
1560 .parent = &l4_ck, 1595 .parent = &l4_ck,
1561 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1596 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1597 .clkdm_name = "core_l4_clkdm",
1562 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1598 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1563 .enable_bit = OMAP24XX_EN_GPT4_SHIFT, 1599 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1564 .recalc = &followparent_recalc, 1600 .recalc = &followparent_recalc,
@@ -1568,6 +1604,7 @@ static struct clk gpt4_fck = {
1568 .name = "gpt4_fck", 1604 .name = "gpt4_fck",
1569 .parent = &func_32k_ck, 1605 .parent = &func_32k_ck,
1570 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1606 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1607 .clkdm_name = "core_l4_clkdm",
1571 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1608 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1572 .enable_bit = OMAP24XX_EN_GPT4_SHIFT, 1609 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1573 .init = &omap2_init_clksel_parent, 1610 .init = &omap2_init_clksel_parent,
@@ -1581,6 +1618,7 @@ static struct clk gpt5_ick = {
1581 .name = "gpt5_ick", 1618 .name = "gpt5_ick",
1582 .parent = &l4_ck, 1619 .parent = &l4_ck,
1583 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1620 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1621 .clkdm_name = "core_l4_clkdm",
1584 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1622 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1585 .enable_bit = OMAP24XX_EN_GPT5_SHIFT, 1623 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1586 .recalc = &followparent_recalc, 1624 .recalc = &followparent_recalc,
@@ -1590,6 +1628,7 @@ static struct clk gpt5_fck = {
1590 .name = "gpt5_fck", 1628 .name = "gpt5_fck",
1591 .parent = &func_32k_ck, 1629 .parent = &func_32k_ck,
1592 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1630 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1631 .clkdm_name = "core_l4_clkdm",
1593 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1632 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1594 .enable_bit = OMAP24XX_EN_GPT5_SHIFT, 1633 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1595 .init = &omap2_init_clksel_parent, 1634 .init = &omap2_init_clksel_parent,
@@ -1603,6 +1642,7 @@ static struct clk gpt6_ick = {
1603 .name = "gpt6_ick", 1642 .name = "gpt6_ick",
1604 .parent = &l4_ck, 1643 .parent = &l4_ck,
1605 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1644 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1645 .clkdm_name = "core_l4_clkdm",
1606 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1646 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1607 .enable_bit = OMAP24XX_EN_GPT6_SHIFT, 1647 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1608 .recalc = &followparent_recalc, 1648 .recalc = &followparent_recalc,
@@ -1612,6 +1652,7 @@ static struct clk gpt6_fck = {
1612 .name = "gpt6_fck", 1652 .name = "gpt6_fck",
1613 .parent = &func_32k_ck, 1653 .parent = &func_32k_ck,
1614 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1654 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1655 .clkdm_name = "core_l4_clkdm",
1615 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1656 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1616 .enable_bit = OMAP24XX_EN_GPT6_SHIFT, 1657 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1617 .init = &omap2_init_clksel_parent, 1658 .init = &omap2_init_clksel_parent,
@@ -1634,6 +1675,7 @@ static struct clk gpt7_fck = {
1634 .name = "gpt7_fck", 1675 .name = "gpt7_fck",
1635 .parent = &func_32k_ck, 1676 .parent = &func_32k_ck,
1636 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1677 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1678 .clkdm_name = "core_l4_clkdm",
1637 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1679 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1638 .enable_bit = OMAP24XX_EN_GPT7_SHIFT, 1680 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1639 .init = &omap2_init_clksel_parent, 1681 .init = &omap2_init_clksel_parent,
@@ -1647,6 +1689,7 @@ static struct clk gpt8_ick = {
1647 .name = "gpt8_ick", 1689 .name = "gpt8_ick",
1648 .parent = &l4_ck, 1690 .parent = &l4_ck,
1649 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1691 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1692 .clkdm_name = "core_l4_clkdm",
1650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1693 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1651 .enable_bit = OMAP24XX_EN_GPT8_SHIFT, 1694 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1652 .recalc = &followparent_recalc, 1695 .recalc = &followparent_recalc,
@@ -1656,6 +1699,7 @@ static struct clk gpt8_fck = {
1656 .name = "gpt8_fck", 1699 .name = "gpt8_fck",
1657 .parent = &func_32k_ck, 1700 .parent = &func_32k_ck,
1658 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1701 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1702 .clkdm_name = "core_l4_clkdm",
1659 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1703 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1660 .enable_bit = OMAP24XX_EN_GPT8_SHIFT, 1704 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1661 .init = &omap2_init_clksel_parent, 1705 .init = &omap2_init_clksel_parent,
@@ -1669,6 +1713,7 @@ static struct clk gpt9_ick = {
1669 .name = "gpt9_ick", 1713 .name = "gpt9_ick",
1670 .parent = &l4_ck, 1714 .parent = &l4_ck,
1671 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1715 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1716 .clkdm_name = "core_l4_clkdm",
1672 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1717 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1673 .enable_bit = OMAP24XX_EN_GPT9_SHIFT, 1718 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1674 .recalc = &followparent_recalc, 1719 .recalc = &followparent_recalc,
@@ -1678,6 +1723,7 @@ static struct clk gpt9_fck = {
1678 .name = "gpt9_fck", 1723 .name = "gpt9_fck",
1679 .parent = &func_32k_ck, 1724 .parent = &func_32k_ck,
1680 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1725 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1726 .clkdm_name = "core_l4_clkdm",
1681 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1682 .enable_bit = OMAP24XX_EN_GPT9_SHIFT, 1728 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1683 .init = &omap2_init_clksel_parent, 1729 .init = &omap2_init_clksel_parent,
@@ -1691,6 +1737,7 @@ static struct clk gpt10_ick = {
1691 .name = "gpt10_ick", 1737 .name = "gpt10_ick",
1692 .parent = &l4_ck, 1738 .parent = &l4_ck,
1693 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1739 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1740 .clkdm_name = "core_l4_clkdm",
1694 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1695 .enable_bit = OMAP24XX_EN_GPT10_SHIFT, 1742 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1696 .recalc = &followparent_recalc, 1743 .recalc = &followparent_recalc,
@@ -1700,6 +1747,7 @@ static struct clk gpt10_fck = {
1700 .name = "gpt10_fck", 1747 .name = "gpt10_fck",
1701 .parent = &func_32k_ck, 1748 .parent = &func_32k_ck,
1702 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1749 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1750 .clkdm_name = "core_l4_clkdm",
1703 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1751 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1704 .enable_bit = OMAP24XX_EN_GPT10_SHIFT, 1752 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1705 .init = &omap2_init_clksel_parent, 1753 .init = &omap2_init_clksel_parent,
@@ -1713,6 +1761,7 @@ static struct clk gpt11_ick = {
1713 .name = "gpt11_ick", 1761 .name = "gpt11_ick",
1714 .parent = &l4_ck, 1762 .parent = &l4_ck,
1715 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1763 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1764 .clkdm_name = "core_l4_clkdm",
1716 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1765 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1717 .enable_bit = OMAP24XX_EN_GPT11_SHIFT, 1766 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1718 .recalc = &followparent_recalc, 1767 .recalc = &followparent_recalc,
@@ -1722,6 +1771,7 @@ static struct clk gpt11_fck = {
1722 .name = "gpt11_fck", 1771 .name = "gpt11_fck",
1723 .parent = &func_32k_ck, 1772 .parent = &func_32k_ck,
1724 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1773 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1774 .clkdm_name = "core_l4_clkdm",
1725 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1775 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1726 .enable_bit = OMAP24XX_EN_GPT11_SHIFT, 1776 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1727 .init = &omap2_init_clksel_parent, 1777 .init = &omap2_init_clksel_parent,
@@ -1735,6 +1785,7 @@ static struct clk gpt12_ick = {
1735 .name = "gpt12_ick", 1785 .name = "gpt12_ick",
1736 .parent = &l4_ck, 1786 .parent = &l4_ck,
1737 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1787 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1788 .clkdm_name = "core_l4_clkdm",
1738 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1739 .enable_bit = OMAP24XX_EN_GPT12_SHIFT, 1790 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1740 .recalc = &followparent_recalc, 1791 .recalc = &followparent_recalc,
@@ -1744,6 +1795,7 @@ static struct clk gpt12_fck = {
1744 .name = "gpt12_fck", 1795 .name = "gpt12_fck",
1745 .parent = &func_32k_ck, 1796 .parent = &func_32k_ck,
1746 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1797 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1798 .clkdm_name = "core_l4_clkdm",
1747 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1799 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1748 .enable_bit = OMAP24XX_EN_GPT12_SHIFT, 1800 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1749 .init = &omap2_init_clksel_parent, 1801 .init = &omap2_init_clksel_parent,
@@ -1758,6 +1810,7 @@ static struct clk mcbsp1_ick = {
1758 .id = 1, 1810 .id = 1,
1759 .parent = &l4_ck, 1811 .parent = &l4_ck,
1760 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1812 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1813 .clkdm_name = "core_l4_clkdm",
1761 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1814 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1762 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1815 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1763 .recalc = &followparent_recalc, 1816 .recalc = &followparent_recalc,
@@ -1768,6 +1821,7 @@ static struct clk mcbsp1_fck = {
1768 .id = 1, 1821 .id = 1,
1769 .parent = &func_96m_ck, 1822 .parent = &func_96m_ck,
1770 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1823 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1824 .clkdm_name = "core_l4_clkdm",
1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1825 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1772 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1826 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1773 .recalc = &followparent_recalc, 1827 .recalc = &followparent_recalc,
@@ -1778,6 +1832,7 @@ static struct clk mcbsp2_ick = {
1778 .id = 2, 1832 .id = 2,
1779 .parent = &l4_ck, 1833 .parent = &l4_ck,
1780 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1834 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1835 .clkdm_name = "core_l4_clkdm",
1781 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1836 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1782 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1837 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1783 .recalc = &followparent_recalc, 1838 .recalc = &followparent_recalc,
@@ -1788,6 +1843,7 @@ static struct clk mcbsp2_fck = {
1788 .id = 2, 1843 .id = 2,
1789 .parent = &func_96m_ck, 1844 .parent = &func_96m_ck,
1790 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1845 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1846 .clkdm_name = "core_l4_clkdm",
1791 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1792 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1848 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1793 .recalc = &followparent_recalc, 1849 .recalc = &followparent_recalc,
@@ -1798,6 +1854,7 @@ static struct clk mcbsp3_ick = {
1798 .id = 3, 1854 .id = 3,
1799 .parent = &l4_ck, 1855 .parent = &l4_ck,
1800 .flags = CLOCK_IN_OMAP243X, 1856 .flags = CLOCK_IN_OMAP243X,
1857 .clkdm_name = "core_l4_clkdm",
1801 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1858 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1802 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, 1859 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1803 .recalc = &followparent_recalc, 1860 .recalc = &followparent_recalc,
@@ -1808,6 +1865,7 @@ static struct clk mcbsp3_fck = {
1808 .id = 3, 1865 .id = 3,
1809 .parent = &func_96m_ck, 1866 .parent = &func_96m_ck,
1810 .flags = CLOCK_IN_OMAP243X, 1867 .flags = CLOCK_IN_OMAP243X,
1868 .clkdm_name = "core_l4_clkdm",
1811 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1869 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1812 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, 1870 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1813 .recalc = &followparent_recalc, 1871 .recalc = &followparent_recalc,
@@ -1818,6 +1876,7 @@ static struct clk mcbsp4_ick = {
1818 .id = 4, 1876 .id = 4,
1819 .parent = &l4_ck, 1877 .parent = &l4_ck,
1820 .flags = CLOCK_IN_OMAP243X, 1878 .flags = CLOCK_IN_OMAP243X,
1879 .clkdm_name = "core_l4_clkdm",
1821 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1822 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, 1881 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1823 .recalc = &followparent_recalc, 1882 .recalc = &followparent_recalc,
@@ -1828,6 +1887,7 @@ static struct clk mcbsp4_fck = {
1828 .id = 4, 1887 .id = 4,
1829 .parent = &func_96m_ck, 1888 .parent = &func_96m_ck,
1830 .flags = CLOCK_IN_OMAP243X, 1889 .flags = CLOCK_IN_OMAP243X,
1890 .clkdm_name = "core_l4_clkdm",
1831 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1832 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, 1892 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1833 .recalc = &followparent_recalc, 1893 .recalc = &followparent_recalc,
@@ -1838,6 +1898,7 @@ static struct clk mcbsp5_ick = {
1838 .id = 5, 1898 .id = 5,
1839 .parent = &l4_ck, 1899 .parent = &l4_ck,
1840 .flags = CLOCK_IN_OMAP243X, 1900 .flags = CLOCK_IN_OMAP243X,
1901 .clkdm_name = "core_l4_clkdm",
1841 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1902 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1842 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, 1903 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1843 .recalc = &followparent_recalc, 1904 .recalc = &followparent_recalc,
@@ -1848,6 +1909,7 @@ static struct clk mcbsp5_fck = {
1848 .id = 5, 1909 .id = 5,
1849 .parent = &func_96m_ck, 1910 .parent = &func_96m_ck,
1850 .flags = CLOCK_IN_OMAP243X, 1911 .flags = CLOCK_IN_OMAP243X,
1912 .clkdm_name = "core_l4_clkdm",
1851 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1913 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1852 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, 1914 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1853 .recalc = &followparent_recalc, 1915 .recalc = &followparent_recalc,
@@ -1857,6 +1919,7 @@ static struct clk mcspi1_ick = {
1857 .name = "mcspi_ick", 1919 .name = "mcspi_ick",
1858 .id = 1, 1920 .id = 1,
1859 .parent = &l4_ck, 1921 .parent = &l4_ck,
1922 .clkdm_name = "core_l4_clkdm",
1860 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1923 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1861 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1924 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1862 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1925 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
@@ -1868,6 +1931,7 @@ static struct clk mcspi1_fck = {
1868 .id = 1, 1931 .id = 1,
1869 .parent = &func_48m_ck, 1932 .parent = &func_48m_ck,
1870 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1933 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1934 .clkdm_name = "core_l4_clkdm",
1871 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1935 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1872 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1936 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1873 .recalc = &followparent_recalc, 1937 .recalc = &followparent_recalc,
@@ -1878,6 +1942,7 @@ static struct clk mcspi2_ick = {
1878 .id = 2, 1942 .id = 2,
1879 .parent = &l4_ck, 1943 .parent = &l4_ck,
1880 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1944 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1945 .clkdm_name = "core_l4_clkdm",
1881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1946 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1882 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1947 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1883 .recalc = &followparent_recalc, 1948 .recalc = &followparent_recalc,
@@ -1888,6 +1953,7 @@ static struct clk mcspi2_fck = {
1888 .id = 2, 1953 .id = 2,
1889 .parent = &func_48m_ck, 1954 .parent = &func_48m_ck,
1890 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1955 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1956 .clkdm_name = "core_l4_clkdm",
1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1957 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1892 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1958 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1893 .recalc = &followparent_recalc, 1959 .recalc = &followparent_recalc,
@@ -1898,6 +1964,7 @@ static struct clk mcspi3_ick = {
1898 .id = 3, 1964 .id = 3,
1899 .parent = &l4_ck, 1965 .parent = &l4_ck,
1900 .flags = CLOCK_IN_OMAP243X, 1966 .flags = CLOCK_IN_OMAP243X,
1967 .clkdm_name = "core_l4_clkdm",
1901 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1968 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1902 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, 1969 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1903 .recalc = &followparent_recalc, 1970 .recalc = &followparent_recalc,
@@ -1908,6 +1975,7 @@ static struct clk mcspi3_fck = {
1908 .id = 3, 1975 .id = 3,
1909 .parent = &func_48m_ck, 1976 .parent = &func_48m_ck,
1910 .flags = CLOCK_IN_OMAP243X, 1977 .flags = CLOCK_IN_OMAP243X,
1978 .clkdm_name = "core_l4_clkdm",
1911 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1979 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1912 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, 1980 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1913 .recalc = &followparent_recalc, 1981 .recalc = &followparent_recalc,
@@ -1917,6 +1985,7 @@ static struct clk uart1_ick = {
1917 .name = "uart1_ick", 1985 .name = "uart1_ick",
1918 .parent = &l4_ck, 1986 .parent = &l4_ck,
1919 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1987 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1988 .clkdm_name = "core_l4_clkdm",
1920 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1989 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1921 .enable_bit = OMAP24XX_EN_UART1_SHIFT, 1990 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1922 .recalc = &followparent_recalc, 1991 .recalc = &followparent_recalc,
@@ -1926,6 +1995,7 @@ static struct clk uart1_fck = {
1926 .name = "uart1_fck", 1995 .name = "uart1_fck",
1927 .parent = &func_48m_ck, 1996 .parent = &func_48m_ck,
1928 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1997 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1998 .clkdm_name = "core_l4_clkdm",
1929 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1999 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1930 .enable_bit = OMAP24XX_EN_UART1_SHIFT, 2000 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1931 .recalc = &followparent_recalc, 2001 .recalc = &followparent_recalc,
@@ -1935,6 +2005,7 @@ static struct clk uart2_ick = {
1935 .name = "uart2_ick", 2005 .name = "uart2_ick",
1936 .parent = &l4_ck, 2006 .parent = &l4_ck,
1937 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2008 .clkdm_name = "core_l4_clkdm",
1938 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2009 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1939 .enable_bit = OMAP24XX_EN_UART2_SHIFT, 2010 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1940 .recalc = &followparent_recalc, 2011 .recalc = &followparent_recalc,
@@ -1944,6 +2015,7 @@ static struct clk uart2_fck = {
1944 .name = "uart2_fck", 2015 .name = "uart2_fck",
1945 .parent = &func_48m_ck, 2016 .parent = &func_48m_ck,
1946 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2017 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2018 .clkdm_name = "core_l4_clkdm",
1947 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2019 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1948 .enable_bit = OMAP24XX_EN_UART2_SHIFT, 2020 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1949 .recalc = &followparent_recalc, 2021 .recalc = &followparent_recalc,
@@ -1953,6 +2025,7 @@ static struct clk uart3_ick = {
1953 .name = "uart3_ick", 2025 .name = "uart3_ick",
1954 .parent = &l4_ck, 2026 .parent = &l4_ck,
1955 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2027 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2028 .clkdm_name = "core_l4_clkdm",
1956 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2029 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1957 .enable_bit = OMAP24XX_EN_UART3_SHIFT, 2030 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1958 .recalc = &followparent_recalc, 2031 .recalc = &followparent_recalc,
@@ -1962,6 +2035,7 @@ static struct clk uart3_fck = {
1962 .name = "uart3_fck", 2035 .name = "uart3_fck",
1963 .parent = &func_48m_ck, 2036 .parent = &func_48m_ck,
1964 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2037 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2038 .clkdm_name = "core_l4_clkdm",
1965 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2039 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1966 .enable_bit = OMAP24XX_EN_UART3_SHIFT, 2040 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1967 .recalc = &followparent_recalc, 2041 .recalc = &followparent_recalc,
@@ -1971,6 +2045,7 @@ static struct clk gpios_ick = {
1971 .name = "gpios_ick", 2045 .name = "gpios_ick",
1972 .parent = &l4_ck, 2046 .parent = &l4_ck,
1973 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2047 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2048 .clkdm_name = "core_l4_clkdm",
1974 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2049 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1975 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, 2050 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1976 .recalc = &followparent_recalc, 2051 .recalc = &followparent_recalc,
@@ -1980,6 +2055,7 @@ static struct clk gpios_fck = {
1980 .name = "gpios_fck", 2055 .name = "gpios_fck",
1981 .parent = &func_32k_ck, 2056 .parent = &func_32k_ck,
1982 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2057 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2058 .clkdm_name = "wkup_clkdm",
1983 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2059 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1984 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, 2060 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1985 .recalc = &followparent_recalc, 2061 .recalc = &followparent_recalc,
@@ -1989,6 +2065,7 @@ static struct clk mpu_wdt_ick = {
1989 .name = "mpu_wdt_ick", 2065 .name = "mpu_wdt_ick",
1990 .parent = &l4_ck, 2066 .parent = &l4_ck,
1991 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2067 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2068 .clkdm_name = "core_l4_clkdm",
1992 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2069 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1993 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 2070 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1994 .recalc = &followparent_recalc, 2071 .recalc = &followparent_recalc,
@@ -1998,6 +2075,7 @@ static struct clk mpu_wdt_fck = {
1998 .name = "mpu_wdt_fck", 2075 .name = "mpu_wdt_fck",
1999 .parent = &func_32k_ck, 2076 .parent = &func_32k_ck,
2000 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2077 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2078 .clkdm_name = "wkup_clkdm",
2001 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2079 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2002 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 2080 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2003 .recalc = &followparent_recalc, 2081 .recalc = &followparent_recalc,
@@ -2006,31 +2084,40 @@ static struct clk mpu_wdt_fck = {
2006static struct clk sync_32k_ick = { 2084static struct clk sync_32k_ick = {
2007 .name = "sync_32k_ick", 2085 .name = "sync_32k_ick",
2008 .parent = &l4_ck, 2086 .parent = &l4_ck,
2009 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, 2087 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2088 ENABLE_ON_INIT,
2089 .clkdm_name = "core_l4_clkdm",
2010 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2090 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2011 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, 2091 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
2012 .recalc = &followparent_recalc, 2092 .recalc = &followparent_recalc,
2013}; 2093};
2094
2014static struct clk wdt1_ick = { 2095static struct clk wdt1_ick = {
2015 .name = "wdt1_ick", 2096 .name = "wdt1_ick",
2016 .parent = &l4_ck, 2097 .parent = &l4_ck,
2017 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2098 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2099 .clkdm_name = "core_l4_clkdm",
2018 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2100 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2019 .enable_bit = OMAP24XX_EN_WDT1_SHIFT, 2101 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
2020 .recalc = &followparent_recalc, 2102 .recalc = &followparent_recalc,
2021}; 2103};
2104
2022static struct clk omapctrl_ick = { 2105static struct clk omapctrl_ick = {
2023 .name = "omapctrl_ick", 2106 .name = "omapctrl_ick",
2024 .parent = &l4_ck, 2107 .parent = &l4_ck,
2025 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, 2108 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2109 ENABLE_ON_INIT,
2110 .clkdm_name = "core_l4_clkdm",
2026 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2111 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2027 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, 2112 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
2028 .recalc = &followparent_recalc, 2113 .recalc = &followparent_recalc,
2029}; 2114};
2115
2030static struct clk icr_ick = { 2116static struct clk icr_ick = {
2031 .name = "icr_ick", 2117 .name = "icr_ick",
2032 .parent = &l4_ck, 2118 .parent = &l4_ck,
2033 .flags = CLOCK_IN_OMAP243X, 2119 .flags = CLOCK_IN_OMAP243X,
2120 .clkdm_name = "core_l4_clkdm",
2034 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2121 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2035 .enable_bit = OMAP2430_EN_ICR_SHIFT, 2122 .enable_bit = OMAP2430_EN_ICR_SHIFT,
2036 .recalc = &followparent_recalc, 2123 .recalc = &followparent_recalc,
@@ -2040,15 +2127,22 @@ static struct clk cam_ick = {
2040 .name = "cam_ick", 2127 .name = "cam_ick",
2041 .parent = &l4_ck, 2128 .parent = &l4_ck,
2042 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2129 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2130 .clkdm_name = "core_l4_clkdm",
2043 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2131 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2044 .enable_bit = OMAP24XX_EN_CAM_SHIFT, 2132 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2045 .recalc = &followparent_recalc, 2133 .recalc = &followparent_recalc,
2046}; 2134};
2047 2135
2136/*
2137 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
2138 * split into two separate clocks, since the parent clocks are different
2139 * and the clockdomains are also different.
2140 */
2048static struct clk cam_fck = { 2141static struct clk cam_fck = {
2049 .name = "cam_fck", 2142 .name = "cam_fck",
2050 .parent = &func_96m_ck, 2143 .parent = &func_96m_ck,
2051 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2144 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2145 .clkdm_name = "core_l3_clkdm",
2052 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2146 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2053 .enable_bit = OMAP24XX_EN_CAM_SHIFT, 2147 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2054 .recalc = &followparent_recalc, 2148 .recalc = &followparent_recalc,
@@ -2058,6 +2152,7 @@ static struct clk mailboxes_ick = {
2058 .name = "mailboxes_ick", 2152 .name = "mailboxes_ick",
2059 .parent = &l4_ck, 2153 .parent = &l4_ck,
2060 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2154 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2155 .clkdm_name = "core_l4_clkdm",
2061 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2156 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2062 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, 2157 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2063 .recalc = &followparent_recalc, 2158 .recalc = &followparent_recalc,
@@ -2067,6 +2162,7 @@ static struct clk wdt4_ick = {
2067 .name = "wdt4_ick", 2162 .name = "wdt4_ick",
2068 .parent = &l4_ck, 2163 .parent = &l4_ck,
2069 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2164 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2165 .clkdm_name = "core_l4_clkdm",
2070 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2166 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2071 .enable_bit = OMAP24XX_EN_WDT4_SHIFT, 2167 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2072 .recalc = &followparent_recalc, 2168 .recalc = &followparent_recalc,
@@ -2076,6 +2172,7 @@ static struct clk wdt4_fck = {
2076 .name = "wdt4_fck", 2172 .name = "wdt4_fck",
2077 .parent = &func_32k_ck, 2173 .parent = &func_32k_ck,
2078 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2174 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2175 .clkdm_name = "core_l4_clkdm",
2079 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2176 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2080 .enable_bit = OMAP24XX_EN_WDT4_SHIFT, 2177 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2081 .recalc = &followparent_recalc, 2178 .recalc = &followparent_recalc,
@@ -2085,6 +2182,7 @@ static struct clk wdt3_ick = {
2085 .name = "wdt3_ick", 2182 .name = "wdt3_ick",
2086 .parent = &l4_ck, 2183 .parent = &l4_ck,
2087 .flags = CLOCK_IN_OMAP242X, 2184 .flags = CLOCK_IN_OMAP242X,
2185 .clkdm_name = "core_l4_clkdm",
2088 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2186 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2089 .enable_bit = OMAP2420_EN_WDT3_SHIFT, 2187 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2090 .recalc = &followparent_recalc, 2188 .recalc = &followparent_recalc,
@@ -2094,6 +2192,7 @@ static struct clk wdt3_fck = {
2094 .name = "wdt3_fck", 2192 .name = "wdt3_fck",
2095 .parent = &func_32k_ck, 2193 .parent = &func_32k_ck,
2096 .flags = CLOCK_IN_OMAP242X, 2194 .flags = CLOCK_IN_OMAP242X,
2195 .clkdm_name = "core_l4_clkdm",
2097 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2196 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2098 .enable_bit = OMAP2420_EN_WDT3_SHIFT, 2197 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2099 .recalc = &followparent_recalc, 2198 .recalc = &followparent_recalc,
@@ -2103,6 +2202,7 @@ static struct clk mspro_ick = {
2103 .name = "mspro_ick", 2202 .name = "mspro_ick",
2104 .parent = &l4_ck, 2203 .parent = &l4_ck,
2105 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2204 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2205 .clkdm_name = "core_l4_clkdm",
2106 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2206 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2107 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, 2207 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2108 .recalc = &followparent_recalc, 2208 .recalc = &followparent_recalc,
@@ -2112,6 +2212,7 @@ static struct clk mspro_fck = {
2112 .name = "mspro_fck", 2212 .name = "mspro_fck",
2113 .parent = &func_96m_ck, 2213 .parent = &func_96m_ck,
2114 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2214 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2215 .clkdm_name = "core_l4_clkdm",
2115 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2116 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, 2217 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2117 .recalc = &followparent_recalc, 2218 .recalc = &followparent_recalc,
@@ -2121,6 +2222,7 @@ static struct clk mmc_ick = {
2121 .name = "mmc_ick", 2222 .name = "mmc_ick",
2122 .parent = &l4_ck, 2223 .parent = &l4_ck,
2123 .flags = CLOCK_IN_OMAP242X, 2224 .flags = CLOCK_IN_OMAP242X,
2225 .clkdm_name = "core_l4_clkdm",
2124 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2226 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2125 .enable_bit = OMAP2420_EN_MMC_SHIFT, 2227 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2126 .recalc = &followparent_recalc, 2228 .recalc = &followparent_recalc,
@@ -2130,6 +2232,7 @@ static struct clk mmc_fck = {
2130 .name = "mmc_fck", 2232 .name = "mmc_fck",
2131 .parent = &func_96m_ck, 2233 .parent = &func_96m_ck,
2132 .flags = CLOCK_IN_OMAP242X, 2234 .flags = CLOCK_IN_OMAP242X,
2235 .clkdm_name = "core_l4_clkdm",
2133 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2236 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2134 .enable_bit = OMAP2420_EN_MMC_SHIFT, 2237 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2135 .recalc = &followparent_recalc, 2238 .recalc = &followparent_recalc,
@@ -2139,6 +2242,7 @@ static struct clk fac_ick = {
2139 .name = "fac_ick", 2242 .name = "fac_ick",
2140 .parent = &l4_ck, 2243 .parent = &l4_ck,
2141 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2244 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2245 .clkdm_name = "core_l4_clkdm",
2142 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2246 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2143 .enable_bit = OMAP24XX_EN_FAC_SHIFT, 2247 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2144 .recalc = &followparent_recalc, 2248 .recalc = &followparent_recalc,
@@ -2148,6 +2252,7 @@ static struct clk fac_fck = {
2148 .name = "fac_fck", 2252 .name = "fac_fck",
2149 .parent = &func_12m_ck, 2253 .parent = &func_12m_ck,
2150 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2254 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2255 .clkdm_name = "core_l4_clkdm",
2151 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2152 .enable_bit = OMAP24XX_EN_FAC_SHIFT, 2257 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2153 .recalc = &followparent_recalc, 2258 .recalc = &followparent_recalc,
@@ -2157,6 +2262,7 @@ static struct clk eac_ick = {
2157 .name = "eac_ick", 2262 .name = "eac_ick",
2158 .parent = &l4_ck, 2263 .parent = &l4_ck,
2159 .flags = CLOCK_IN_OMAP242X, 2264 .flags = CLOCK_IN_OMAP242X,
2265 .clkdm_name = "core_l4_clkdm",
2160 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2266 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2161 .enable_bit = OMAP2420_EN_EAC_SHIFT, 2267 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2162 .recalc = &followparent_recalc, 2268 .recalc = &followparent_recalc,
@@ -2166,6 +2272,7 @@ static struct clk eac_fck = {
2166 .name = "eac_fck", 2272 .name = "eac_fck",
2167 .parent = &func_96m_ck, 2273 .parent = &func_96m_ck,
2168 .flags = CLOCK_IN_OMAP242X, 2274 .flags = CLOCK_IN_OMAP242X,
2275 .clkdm_name = "core_l4_clkdm",
2169 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2170 .enable_bit = OMAP2420_EN_EAC_SHIFT, 2277 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2171 .recalc = &followparent_recalc, 2278 .recalc = &followparent_recalc,
@@ -2175,6 +2282,7 @@ static struct clk hdq_ick = {
2175 .name = "hdq_ick", 2282 .name = "hdq_ick",
2176 .parent = &l4_ck, 2283 .parent = &l4_ck,
2177 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2284 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2285 .clkdm_name = "core_l4_clkdm",
2178 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2286 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2179 .enable_bit = OMAP24XX_EN_HDQ_SHIFT, 2287 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2180 .recalc = &followparent_recalc, 2288 .recalc = &followparent_recalc,
@@ -2184,6 +2292,7 @@ static struct clk hdq_fck = {
2184 .name = "hdq_fck", 2292 .name = "hdq_fck",
2185 .parent = &func_12m_ck, 2293 .parent = &func_12m_ck,
2186 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2294 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2295 .clkdm_name = "core_l4_clkdm",
2187 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2296 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2188 .enable_bit = OMAP24XX_EN_HDQ_SHIFT, 2297 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2189 .recalc = &followparent_recalc, 2298 .recalc = &followparent_recalc,
@@ -2194,6 +2303,7 @@ static struct clk i2c2_ick = {
2194 .id = 2, 2303 .id = 2,
2195 .parent = &l4_ck, 2304 .parent = &l4_ck,
2196 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2305 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2306 .clkdm_name = "core_l4_clkdm",
2197 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2307 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2198 .enable_bit = OMAP2420_EN_I2C2_SHIFT, 2308 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2199 .recalc = &followparent_recalc, 2309 .recalc = &followparent_recalc,
@@ -2204,6 +2314,7 @@ static struct clk i2c2_fck = {
2204 .id = 2, 2314 .id = 2,
2205 .parent = &func_12m_ck, 2315 .parent = &func_12m_ck,
2206 .flags = CLOCK_IN_OMAP242X, 2316 .flags = CLOCK_IN_OMAP242X,
2317 .clkdm_name = "core_l4_clkdm",
2207 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2208 .enable_bit = OMAP2420_EN_I2C2_SHIFT, 2319 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2209 .recalc = &followparent_recalc, 2320 .recalc = &followparent_recalc,
@@ -2214,6 +2325,7 @@ static struct clk i2chs2_fck = {
2214 .id = 2, 2325 .id = 2,
2215 .parent = &func_96m_ck, 2326 .parent = &func_96m_ck,
2216 .flags = CLOCK_IN_OMAP243X, 2327 .flags = CLOCK_IN_OMAP243X,
2328 .clkdm_name = "core_l4_clkdm",
2217 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2329 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2218 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, 2330 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
2219 .recalc = &followparent_recalc, 2331 .recalc = &followparent_recalc,
@@ -2224,6 +2336,7 @@ static struct clk i2c1_ick = {
2224 .id = 1, 2336 .id = 1,
2225 .parent = &l4_ck, 2337 .parent = &l4_ck,
2226 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2338 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2339 .clkdm_name = "core_l4_clkdm",
2227 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2340 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2228 .enable_bit = OMAP2420_EN_I2C1_SHIFT, 2341 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2229 .recalc = &followparent_recalc, 2342 .recalc = &followparent_recalc,
@@ -2234,6 +2347,7 @@ static struct clk i2c1_fck = {
2234 .id = 1, 2347 .id = 1,
2235 .parent = &func_12m_ck, 2348 .parent = &func_12m_ck,
2236 .flags = CLOCK_IN_OMAP242X, 2349 .flags = CLOCK_IN_OMAP242X,
2350 .clkdm_name = "core_l4_clkdm",
2237 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2238 .enable_bit = OMAP2420_EN_I2C1_SHIFT, 2352 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2239 .recalc = &followparent_recalc, 2353 .recalc = &followparent_recalc,
@@ -2244,6 +2358,7 @@ static struct clk i2chs1_fck = {
2244 .id = 1, 2358 .id = 1,
2245 .parent = &func_96m_ck, 2359 .parent = &func_96m_ck,
2246 .flags = CLOCK_IN_OMAP243X, 2360 .flags = CLOCK_IN_OMAP243X,
2361 .clkdm_name = "core_l4_clkdm",
2247 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2362 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2248 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, 2363 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
2249 .recalc = &followparent_recalc, 2364 .recalc = &followparent_recalc,
@@ -2252,7 +2367,9 @@ static struct clk i2chs1_fck = {
2252static struct clk gpmc_fck = { 2367static struct clk gpmc_fck = {
2253 .name = "gpmc_fck", 2368 .name = "gpmc_fck",
2254 .parent = &core_l3_ck, 2369 .parent = &core_l3_ck,
2255 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, 2370 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2371 ENABLE_ON_INIT,
2372 .clkdm_name = "core_l3_clkdm",
2256 .recalc = &followparent_recalc, 2373 .recalc = &followparent_recalc,
2257}; 2374};
2258 2375
@@ -2260,6 +2377,7 @@ static struct clk sdma_fck = {
2260 .name = "sdma_fck", 2377 .name = "sdma_fck",
2261 .parent = &core_l3_ck, 2378 .parent = &core_l3_ck,
2262 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2379 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2380 .clkdm_name = "core_l3_clkdm",
2263 .recalc = &followparent_recalc, 2381 .recalc = &followparent_recalc,
2264}; 2382};
2265 2383
@@ -2267,6 +2385,7 @@ static struct clk sdma_ick = {
2267 .name = "sdma_ick", 2385 .name = "sdma_ick",
2268 .parent = &l4_ck, 2386 .parent = &l4_ck,
2269 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2387 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2388 .clkdm_name = "core_l3_clkdm",
2270 .recalc = &followparent_recalc, 2389 .recalc = &followparent_recalc,
2271}; 2390};
2272 2391
@@ -2274,6 +2393,7 @@ static struct clk vlynq_ick = {
2274 .name = "vlynq_ick", 2393 .name = "vlynq_ick",
2275 .parent = &core_l3_ck, 2394 .parent = &core_l3_ck,
2276 .flags = CLOCK_IN_OMAP242X, 2395 .flags = CLOCK_IN_OMAP242X,
2396 .clkdm_name = "core_l3_clkdm",
2277 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2397 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2278 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, 2398 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2279 .recalc = &followparent_recalc, 2399 .recalc = &followparent_recalc,
@@ -2308,6 +2428,7 @@ static struct clk vlynq_fck = {
2308 .name = "vlynq_fck", 2428 .name = "vlynq_fck",
2309 .parent = &func_96m_ck, 2429 .parent = &func_96m_ck,
2310 .flags = CLOCK_IN_OMAP242X | DELAYED_APP, 2430 .flags = CLOCK_IN_OMAP242X | DELAYED_APP,
2431 .clkdm_name = "core_l3_clkdm",
2311 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2432 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2312 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, 2433 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2313 .init = &omap2_init_clksel_parent, 2434 .init = &omap2_init_clksel_parent,
@@ -2323,6 +2444,7 @@ static struct clk sdrc_ick = {
2323 .name = "sdrc_ick", 2444 .name = "sdrc_ick",
2324 .parent = &l4_ck, 2445 .parent = &l4_ck,
2325 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, 2446 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2447 .clkdm_name = "core_l4_clkdm",
2326 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 2448 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2327 .enable_bit = OMAP2430_EN_SDRC_SHIFT, 2449 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
2328 .recalc = &followparent_recalc, 2450 .recalc = &followparent_recalc,
@@ -2332,6 +2454,7 @@ static struct clk des_ick = {
2332 .name = "des_ick", 2454 .name = "des_ick",
2333 .parent = &l4_ck, 2455 .parent = &l4_ck,
2334 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2456 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2457 .clkdm_name = "core_l4_clkdm",
2335 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2336 .enable_bit = OMAP24XX_EN_DES_SHIFT, 2459 .enable_bit = OMAP24XX_EN_DES_SHIFT,
2337 .recalc = &followparent_recalc, 2460 .recalc = &followparent_recalc,
@@ -2341,6 +2464,7 @@ static struct clk sha_ick = {
2341 .name = "sha_ick", 2464 .name = "sha_ick",
2342 .parent = &l4_ck, 2465 .parent = &l4_ck,
2343 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2466 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2467 .clkdm_name = "core_l4_clkdm",
2344 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2468 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2345 .enable_bit = OMAP24XX_EN_SHA_SHIFT, 2469 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
2346 .recalc = &followparent_recalc, 2470 .recalc = &followparent_recalc,
@@ -2350,6 +2474,7 @@ static struct clk rng_ick = {
2350 .name = "rng_ick", 2474 .name = "rng_ick",
2351 .parent = &l4_ck, 2475 .parent = &l4_ck,
2352 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2476 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2477 .clkdm_name = "core_l4_clkdm",
2353 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2478 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2354 .enable_bit = OMAP24XX_EN_RNG_SHIFT, 2479 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
2355 .recalc = &followparent_recalc, 2480 .recalc = &followparent_recalc,
@@ -2359,6 +2484,7 @@ static struct clk aes_ick = {
2359 .name = "aes_ick", 2484 .name = "aes_ick",
2360 .parent = &l4_ck, 2485 .parent = &l4_ck,
2361 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2486 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2487 .clkdm_name = "core_l4_clkdm",
2362 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2488 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2363 .enable_bit = OMAP24XX_EN_AES_SHIFT, 2489 .enable_bit = OMAP24XX_EN_AES_SHIFT,
2364 .recalc = &followparent_recalc, 2490 .recalc = &followparent_recalc,
@@ -2368,6 +2494,7 @@ static struct clk pka_ick = {
2368 .name = "pka_ick", 2494 .name = "pka_ick",
2369 .parent = &l4_ck, 2495 .parent = &l4_ck,
2370 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2496 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2497 .clkdm_name = "core_l4_clkdm",
2371 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2498 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2372 .enable_bit = OMAP24XX_EN_PKA_SHIFT, 2499 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
2373 .recalc = &followparent_recalc, 2500 .recalc = &followparent_recalc,
@@ -2377,6 +2504,7 @@ static struct clk usb_fck = {
2377 .name = "usb_fck", 2504 .name = "usb_fck",
2378 .parent = &func_48m_ck, 2505 .parent = &func_48m_ck,
2379 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2506 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2507 .clkdm_name = "core_l3_clkdm",
2380 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2508 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2381 .enable_bit = OMAP24XX_EN_USB_SHIFT, 2509 .enable_bit = OMAP24XX_EN_USB_SHIFT,
2382 .recalc = &followparent_recalc, 2510 .recalc = &followparent_recalc,
@@ -2386,6 +2514,7 @@ static struct clk usbhs_ick = {
2386 .name = "usbhs_ick", 2514 .name = "usbhs_ick",
2387 .parent = &core_l3_ck, 2515 .parent = &core_l3_ck,
2388 .flags = CLOCK_IN_OMAP243X, 2516 .flags = CLOCK_IN_OMAP243X,
2517 .clkdm_name = "core_l3_clkdm",
2389 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2518 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2390 .enable_bit = OMAP2430_EN_USBHS_SHIFT, 2519 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
2391 .recalc = &followparent_recalc, 2520 .recalc = &followparent_recalc,
@@ -2396,6 +2525,7 @@ static struct clk mmchs1_ick = {
2396 .id = 1, 2525 .id = 1,
2397 .parent = &l4_ck, 2526 .parent = &l4_ck,
2398 .flags = CLOCK_IN_OMAP243X, 2527 .flags = CLOCK_IN_OMAP243X,
2528 .clkdm_name = "core_l4_clkdm",
2399 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2529 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2400 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, 2530 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2401 .recalc = &followparent_recalc, 2531 .recalc = &followparent_recalc,
@@ -2406,6 +2536,7 @@ static struct clk mmchs1_fck = {
2406 .id = 1, 2536 .id = 1,
2407 .parent = &func_96m_ck, 2537 .parent = &func_96m_ck,
2408 .flags = CLOCK_IN_OMAP243X, 2538 .flags = CLOCK_IN_OMAP243X,
2539 .clkdm_name = "core_l3_clkdm",
2409 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2540 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2410 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, 2541 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2411 .recalc = &followparent_recalc, 2542 .recalc = &followparent_recalc,
@@ -2416,6 +2547,7 @@ static struct clk mmchs2_ick = {
2416 .id = 2, 2547 .id = 2,
2417 .parent = &l4_ck, 2548 .parent = &l4_ck,
2418 .flags = CLOCK_IN_OMAP243X, 2549 .flags = CLOCK_IN_OMAP243X,
2550 .clkdm_name = "core_l4_clkdm",
2419 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2551 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2420 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, 2552 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2421 .recalc = &followparent_recalc, 2553 .recalc = &followparent_recalc,
@@ -2435,6 +2567,7 @@ static struct clk gpio5_ick = {
2435 .name = "gpio5_ick", 2567 .name = "gpio5_ick",
2436 .parent = &l4_ck, 2568 .parent = &l4_ck,
2437 .flags = CLOCK_IN_OMAP243X, 2569 .flags = CLOCK_IN_OMAP243X,
2570 .clkdm_name = "core_l4_clkdm",
2438 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2571 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2439 .enable_bit = OMAP2430_EN_GPIO5_SHIFT, 2572 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2440 .recalc = &followparent_recalc, 2573 .recalc = &followparent_recalc,
@@ -2444,6 +2577,7 @@ static struct clk gpio5_fck = {
2444 .name = "gpio5_fck", 2577 .name = "gpio5_fck",
2445 .parent = &func_32k_ck, 2578 .parent = &func_32k_ck,
2446 .flags = CLOCK_IN_OMAP243X, 2579 .flags = CLOCK_IN_OMAP243X,
2580 .clkdm_name = "core_l4_clkdm",
2447 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2581 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2448 .enable_bit = OMAP2430_EN_GPIO5_SHIFT, 2582 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2449 .recalc = &followparent_recalc, 2583 .recalc = &followparent_recalc,
@@ -2453,6 +2587,7 @@ static struct clk mdm_intc_ick = {
2453 .name = "mdm_intc_ick", 2587 .name = "mdm_intc_ick",
2454 .parent = &l4_ck, 2588 .parent = &l4_ck,
2455 .flags = CLOCK_IN_OMAP243X, 2589 .flags = CLOCK_IN_OMAP243X,
2590 .clkdm_name = "core_l4_clkdm",
2456 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2591 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2457 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, 2592 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
2458 .recalc = &followparent_recalc, 2593 .recalc = &followparent_recalc,
@@ -2463,6 +2598,7 @@ static struct clk mmchsdb1_fck = {
2463 .id = 1, 2598 .id = 1,
2464 .parent = &func_32k_ck, 2599 .parent = &func_32k_ck,
2465 .flags = CLOCK_IN_OMAP243X, 2600 .flags = CLOCK_IN_OMAP243X,
2601 .clkdm_name = "core_l4_clkdm",
2466 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2602 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2467 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, 2603 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
2468 .recalc = &followparent_recalc, 2604 .recalc = &followparent_recalc,
@@ -2473,6 +2609,7 @@ static struct clk mmchsdb2_fck = {
2473 .id = 2, 2609 .id = 2,
2474 .parent = &func_32k_ck, 2610 .parent = &func_32k_ck,
2475 .flags = CLOCK_IN_OMAP243X, 2611 .flags = CLOCK_IN_OMAP243X,
2612 .clkdm_name = "core_l4_clkdm",
2476 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2613 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2477 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, 2614 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
2478 .recalc = &followparent_recalc, 2615 .recalc = &followparent_recalc,
@@ -2551,7 +2688,6 @@ static struct clk *onchip_24xx_clks[] __initdata = {
2551 &usb_l4_ick, 2688 &usb_l4_ick,
2552 /* L4 domain clocks */ 2689 /* L4 domain clocks */
2553 &l4_ck, /* used as both core_l4 and wu_l4 */ 2690 &l4_ck, /* used as both core_l4 and wu_l4 */
2554 &ssi_l4_ick,
2555 /* virtual meta-group clock */ 2691 /* virtual meta-group clock */
2556 &virt_prcm_set, 2692 &virt_prcm_set,
2557 /* general l4 interface ck, multi-parent functional clk */ 2693 /* general l4 interface ck, multi-parent functional clk */
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index e5b475f21081..084e11082f80 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -62,11 +62,14 @@ static void omap3_dpll_recalc(struct clk *clk)
62static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) 62static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
63{ 63{
64 const struct dpll_data *dd; 64 const struct dpll_data *dd;
65 u32 v;
65 66
66 dd = clk->dpll_data; 67 dd = clk->dpll_data;
67 68
68 cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask), 69 v = __raw_readl(dd->control_reg);
69 dd->control_reg); 70 v &= ~dd->enable_mask;
71 v |= clken_bits << __ffs(dd->enable_mask);
72 __raw_writel(v, dd->control_reg);
70} 73}
71 74
72/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ 75/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
@@ -82,7 +85,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
82 state <<= dd->idlest_bit; 85 state <<= dd->idlest_bit;
83 idlest_mask = 1 << dd->idlest_bit; 86 idlest_mask = 1 << dd->idlest_bit;
84 87
85 while (((cm_read_reg(dd->idlest_reg) & idlest_mask) != state) && 88 while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&
86 i < MAX_DPLL_WAIT_TRIES) { 89 i < MAX_DPLL_WAIT_TRIES) {
87 i++; 90 i++;
88 udelay(1); 91 udelay(1);
@@ -285,7 +288,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
285 288
286 dd = clk->dpll_data; 289 dd = clk->dpll_data;
287 290
288 v = cm_read_reg(dd->autoidle_reg); 291 v = __raw_readl(dd->autoidle_reg);
289 v &= dd->autoidle_mask; 292 v &= dd->autoidle_mask;
290 v >>= __ffs(dd->autoidle_mask); 293 v >>= __ffs(dd->autoidle_mask);
291 294
@@ -304,6 +307,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
304static void omap3_dpll_allow_idle(struct clk *clk) 307static void omap3_dpll_allow_idle(struct clk *clk)
305{ 308{
306 const struct dpll_data *dd; 309 const struct dpll_data *dd;
310 u32 v;
307 311
308 if (!clk || !clk->dpll_data) 312 if (!clk || !clk->dpll_data)
309 return; 313 return;
@@ -315,9 +319,10 @@ static void omap3_dpll_allow_idle(struct clk *clk)
315 * by writing 0x5 instead of 0x1. Add some mechanism to 319 * by writing 0x5 instead of 0x1. Add some mechanism to
316 * optionally enter this mode. 320 * optionally enter this mode.
317 */ 321 */
318 cm_rmw_reg_bits(dd->autoidle_mask, 322 v = __raw_readl(dd->autoidle_reg);
319 DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask), 323 v &= ~dd->autoidle_mask;
320 dd->autoidle_reg); 324 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
325 __raw_writel(v, dd->autoidle_reg);
321} 326}
322 327
323/** 328/**
@@ -329,15 +334,17 @@ static void omap3_dpll_allow_idle(struct clk *clk)
329static void omap3_dpll_deny_idle(struct clk *clk) 334static void omap3_dpll_deny_idle(struct clk *clk)
330{ 335{
331 const struct dpll_data *dd; 336 const struct dpll_data *dd;
337 u32 v;
332 338
333 if (!clk || !clk->dpll_data) 339 if (!clk || !clk->dpll_data)
334 return; 340 return;
335 341
336 dd = clk->dpll_data; 342 dd = clk->dpll_data;
337 343
338 cm_rmw_reg_bits(dd->autoidle_mask, 344 v = __raw_readl(dd->autoidle_reg);
339 DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask), 345 v &= ~dd->autoidle_mask;
340 dd->autoidle_reg); 346 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
347 __raw_writel(v, dd->autoidle_reg);
341} 348}
342 349
343/* Clock control for DPLL outputs */ 350/* Clock control for DPLL outputs */
@@ -482,8 +489,10 @@ int __init omap2_clk_init(void)
482 for (clkp = onchip_34xx_clks; 489 for (clkp = onchip_34xx_clks;
483 clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks); 490 clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
484 clkp++) { 491 clkp++) {
485 if ((*clkp)->flags & cpu_clkflg) 492 if ((*clkp)->flags & cpu_clkflg) {
486 clk_register(*clkp); 493 clk_register(*clkp);
494 omap2_init_clk_clkdm(*clkp);
495 }
487 } 496 }
488 497
489 /* REVISIT: Not yet ready for OMAP3 */ 498 /* REVISIT: Not yet ready for OMAP3 */
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index ec664457a11a..c38a8a09692f 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -478,7 +478,7 @@ static struct clk dpll3_m2_ck = {
478}; 478};
479 479
480static const struct clksel core_ck_clksel[] = { 480static const struct clksel core_ck_clksel[] = {
481 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 481 { .parent = &sys_ck, .rates = dpll_bypass_rates },
482 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, 482 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
483 { .parent = NULL } 483 { .parent = NULL }
484}; 484};
@@ -495,7 +495,7 @@ static struct clk core_ck = {
495}; 495};
496 496
497static const struct clksel dpll3_m2x2_ck_clksel[] = { 497static const struct clksel dpll3_m2x2_ck_clksel[] = {
498 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 498 { .parent = &sys_ck, .rates = dpll_bypass_rates },
499 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, 499 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
500 { .parent = NULL } 500 { .parent = NULL }
501}; 501};
@@ -541,7 +541,7 @@ static struct clk dpll3_m3x2_ck = {
541}; 541};
542 542
543static const struct clksel emu_core_alwon_ck_clksel[] = { 543static const struct clksel emu_core_alwon_ck_clksel[] = {
544 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 544 { .parent = &sys_ck, .rates = dpll_bypass_rates },
545 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, 545 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
546 { .parent = NULL } 546 { .parent = NULL }
547}; 547};
@@ -633,7 +633,7 @@ static struct clk dpll4_m2x2_ck = {
633}; 633};
634 634
635static const struct clksel omap_96m_alwon_fck_clksel[] = { 635static const struct clksel omap_96m_alwon_fck_clksel[] = {
636 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 636 { .parent = &sys_ck, .rates = dpll_bypass_rates },
637 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, 637 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
638 { .parent = NULL } 638 { .parent = NULL }
639}; 639};
@@ -659,7 +659,7 @@ static struct clk omap_96m_fck = {
659}; 659};
660 660
661static const struct clksel cm_96m_fck_clksel[] = { 661static const struct clksel cm_96m_fck_clksel[] = {
662 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 662 { .parent = &sys_ck, .rates = dpll_bypass_rates },
663 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, 663 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
664 { .parent = NULL } 664 { .parent = NULL }
665}; 665};
@@ -701,7 +701,7 @@ static struct clk dpll4_m3x2_ck = {
701}; 701};
702 702
703static const struct clksel virt_omap_54m_fck_clksel[] = { 703static const struct clksel virt_omap_54m_fck_clksel[] = {
704 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 704 { .parent = &sys_ck, .rates = dpll_bypass_rates },
705 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, 705 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
706 { .parent = NULL } 706 { .parent = NULL }
707}; 707};
@@ -911,7 +911,7 @@ static struct clk dpll5_m2_ck = {
911}; 911};
912 912
913static const struct clksel omap_120m_fck_clksel[] = { 913static const struct clksel omap_120m_fck_clksel[] = {
914 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 914 { .parent = &sys_ck, .rates = dpll_bypass_rates },
915 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, 915 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
916 { .parent = NULL } 916 { .parent = NULL }
917}; 917};
@@ -919,13 +919,13 @@ static const struct clksel omap_120m_fck_clksel[] = {
919static struct clk omap_120m_fck = { 919static struct clk omap_120m_fck = {
920 .name = "omap_120m_fck", 920 .name = "omap_120m_fck",
921 .parent = &dpll5_m2_ck, 921 .parent = &dpll5_m2_ck,
922 .init = &omap2_init_clksel_parent, 922 .init = &omap2_init_clksel_parent,
923 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), 923 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
924 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, 924 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
925 .clksel = omap_120m_fck_clksel, 925 .clksel = omap_120m_fck_clksel,
926 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | 926 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
927 PARENT_CONTROLS_CLOCK, 927 PARENT_CONTROLS_CLOCK,
928 .recalc = &omap2_clksel_recalc, 928 .recalc = &omap2_clksel_recalc,
929}; 929};
930 930
931/* CM EXTERNAL CLOCK OUTPUTS */ 931/* CM EXTERNAL CLOCK OUTPUTS */
@@ -1034,7 +1034,7 @@ static struct clk dpll1_fck = {
1034 * called 'dpll1_fck' 1034 * called 'dpll1_fck'
1035 */ 1035 */
1036static const struct clksel mpu_clksel[] = { 1036static const struct clksel mpu_clksel[] = {
1037 { .parent = &dpll1_fck, .rates = dpll_bypass_rates }, 1037 { .parent = &dpll1_fck, .rates = dpll_bypass_rates },
1038 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, 1038 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1039 { .parent = NULL } 1039 { .parent = NULL }
1040}; 1040};
@@ -1048,6 +1048,7 @@ static struct clk mpu_ck = {
1048 .clksel = mpu_clksel, 1048 .clksel = mpu_clksel,
1049 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1049 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1050 PARENT_CONTROLS_CLOCK, 1050 PARENT_CONTROLS_CLOCK,
1051 .clkdm_name = "mpu_clkdm",
1051 .recalc = &omap2_clksel_recalc, 1052 .recalc = &omap2_clksel_recalc,
1052}; 1053};
1053 1054
@@ -1075,6 +1076,8 @@ static struct clk arm_fck = {
1075 .recalc = &omap2_clksel_recalc, 1076 .recalc = &omap2_clksel_recalc,
1076}; 1077};
1077 1078
1079/* XXX What about neon_clkdm ? */
1080
1078/* 1081/*
1079 * REVISIT: This clock is never specifically defined in the 3430 TRM, 1082 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1080 * although it is referenced - so this is a guess 1083 * although it is referenced - so this is a guess
@@ -1107,7 +1110,7 @@ static struct clk dpll2_fck = {
1107 */ 1110 */
1108 1111
1109static const struct clksel iva2_clksel[] = { 1112static const struct clksel iva2_clksel[] = {
1110 { .parent = &dpll2_fck, .rates = dpll_bypass_rates }, 1113 { .parent = &dpll2_fck, .rates = dpll_bypass_rates },
1111 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, 1114 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1112 { .parent = NULL } 1115 { .parent = NULL }
1113}; 1116};
@@ -1123,6 +1126,7 @@ static struct clk iva2_ck = {
1123 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, 1126 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
1124 .clksel = iva2_clksel, 1127 .clksel = iva2_clksel,
1125 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1128 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1129 .clkdm_name = "iva2_clkdm",
1126 .recalc = &omap2_clksel_recalc, 1130 .recalc = &omap2_clksel_recalc,
1127}; 1131};
1128 1132
@@ -1137,6 +1141,7 @@ static struct clk l3_ick = {
1137 .clksel = div2_core_clksel, 1141 .clksel = div2_core_clksel,
1138 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1142 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1139 PARENT_CONTROLS_CLOCK, 1143 PARENT_CONTROLS_CLOCK,
1144 .clkdm_name = "core_l3_clkdm",
1140 .recalc = &omap2_clksel_recalc, 1145 .recalc = &omap2_clksel_recalc,
1141}; 1146};
1142 1147
@@ -1154,6 +1159,7 @@ static struct clk l4_ick = {
1154 .clksel = div2_l3_clksel, 1159 .clksel = div2_l3_clksel,
1155 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1160 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1156 PARENT_CONTROLS_CLOCK, 1161 PARENT_CONTROLS_CLOCK,
1162 .clkdm_name = "core_l4_clkdm",
1157 .recalc = &omap2_clksel_recalc, 1163 .recalc = &omap2_clksel_recalc,
1158 1164
1159}; 1165};
@@ -1183,43 +1189,57 @@ static const struct clksel gfx_l3_clksel[] = {
1183 { .parent = NULL } 1189 { .parent = NULL }
1184}; 1190};
1185 1191
1186static struct clk gfx_l3_fck = { 1192/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1187 .name = "gfx_l3_fck", 1193static struct clk gfx_l3_ck = {
1194 .name = "gfx_l3_ck",
1188 .parent = &l3_ick, 1195 .parent = &l3_ick,
1189 .init = &omap2_init_clksel_parent, 1196 .init = &omap2_init_clksel_parent,
1190 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1197 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1191 .enable_bit = OMAP_EN_GFX_SHIFT, 1198 .enable_bit = OMAP_EN_GFX_SHIFT,
1199 .flags = CLOCK_IN_OMAP3430ES1,
1200 .recalc = &followparent_recalc,
1201};
1202
1203static struct clk gfx_l3_fck = {
1204 .name = "gfx_l3_fck",
1205 .parent = &gfx_l3_ck,
1206 .init = &omap2_init_clksel_parent,
1192 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), 1207 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1193 .clksel_mask = OMAP_CLKSEL_GFX_MASK, 1208 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1194 .clksel = gfx_l3_clksel, 1209 .clksel = gfx_l3_clksel,
1195 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES, 1210 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1211 PARENT_CONTROLS_CLOCK,
1212 .clkdm_name = "gfx_3430es1_clkdm",
1196 .recalc = &omap2_clksel_recalc, 1213 .recalc = &omap2_clksel_recalc,
1197}; 1214};
1198 1215
1199static struct clk gfx_l3_ick = { 1216static struct clk gfx_l3_ick = {
1200 .name = "gfx_l3_ick", 1217 .name = "gfx_l3_ick",
1201 .parent = &l3_ick, 1218 .parent = &gfx_l3_ck,
1202 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1219 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1203 .enable_bit = OMAP_EN_GFX_SHIFT, 1220 .clkdm_name = "gfx_3430es1_clkdm",
1204 .flags = CLOCK_IN_OMAP3430ES1,
1205 .recalc = &followparent_recalc, 1221 .recalc = &followparent_recalc,
1206}; 1222};
1207 1223
1208static struct clk gfx_cg1_ck = { 1224static struct clk gfx_cg1_ck = {
1209 .name = "gfx_cg1_ck", 1225 .name = "gfx_cg1_ck",
1210 .parent = &gfx_l3_fck, /* REVISIT: correct? */ 1226 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1227 .init = &omap2_init_clk_clkdm,
1211 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1228 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1212 .enable_bit = OMAP3430ES1_EN_2D_SHIFT, 1229 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1213 .flags = CLOCK_IN_OMAP3430ES1, 1230 .flags = CLOCK_IN_OMAP3430ES1,
1231 .clkdm_name = "gfx_3430es1_clkdm",
1214 .recalc = &followparent_recalc, 1232 .recalc = &followparent_recalc,
1215}; 1233};
1216 1234
1217static struct clk gfx_cg2_ck = { 1235static struct clk gfx_cg2_ck = {
1218 .name = "gfx_cg2_ck", 1236 .name = "gfx_cg2_ck",
1219 .parent = &gfx_l3_fck, /* REVISIT: correct? */ 1237 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1238 .init = &omap2_init_clk_clkdm,
1220 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1239 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1221 .enable_bit = OMAP3430ES1_EN_3D_SHIFT, 1240 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1222 .flags = CLOCK_IN_OMAP3430ES1, 1241 .flags = CLOCK_IN_OMAP3430ES1,
1242 .clkdm_name = "gfx_3430es1_clkdm",
1223 .recalc = &followparent_recalc, 1243 .recalc = &followparent_recalc,
1224}; 1244};
1225 1245
@@ -1252,15 +1272,18 @@ static struct clk sgx_fck = {
1252 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, 1272 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1253 .clksel = sgx_clksel, 1273 .clksel = sgx_clksel,
1254 .flags = CLOCK_IN_OMAP3430ES2, 1274 .flags = CLOCK_IN_OMAP3430ES2,
1275 .clkdm_name = "sgx_clkdm",
1255 .recalc = &omap2_clksel_recalc, 1276 .recalc = &omap2_clksel_recalc,
1256}; 1277};
1257 1278
1258static struct clk sgx_ick = { 1279static struct clk sgx_ick = {
1259 .name = "sgx_ick", 1280 .name = "sgx_ick",
1260 .parent = &l3_ick, 1281 .parent = &l3_ick,
1282 .init = &omap2_init_clk_clkdm,
1261 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), 1283 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1262 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, 1284 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
1263 .flags = CLOCK_IN_OMAP3430ES2, 1285 .flags = CLOCK_IN_OMAP3430ES2,
1286 .clkdm_name = "sgx_clkdm",
1264 .recalc = &followparent_recalc, 1287 .recalc = &followparent_recalc,
1265}; 1288};
1266 1289
@@ -1269,9 +1292,11 @@ static struct clk sgx_ick = {
1269static struct clk d2d_26m_fck = { 1292static struct clk d2d_26m_fck = {
1270 .name = "d2d_26m_fck", 1293 .name = "d2d_26m_fck",
1271 .parent = &sys_ck, 1294 .parent = &sys_ck,
1295 .init = &omap2_init_clk_clkdm,
1272 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1296 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1273 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, 1297 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1274 .flags = CLOCK_IN_OMAP3430ES1, 1298 .flags = CLOCK_IN_OMAP3430ES1,
1299 .clkdm_name = "d2d_clkdm",
1275 .recalc = &followparent_recalc, 1300 .recalc = &followparent_recalc,
1276}; 1301};
1277 1302
@@ -1291,6 +1316,7 @@ static struct clk gpt10_fck = {
1291 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, 1316 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1292 .clksel = omap343x_gpt_clksel, 1317 .clksel = omap343x_gpt_clksel,
1293 .flags = CLOCK_IN_OMAP343X, 1318 .flags = CLOCK_IN_OMAP343X,
1319 .clkdm_name = "core_l4_clkdm",
1294 .recalc = &omap2_clksel_recalc, 1320 .recalc = &omap2_clksel_recalc,
1295}; 1321};
1296 1322
@@ -1304,6 +1330,7 @@ static struct clk gpt11_fck = {
1304 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, 1330 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1305 .clksel = omap343x_gpt_clksel, 1331 .clksel = omap343x_gpt_clksel,
1306 .flags = CLOCK_IN_OMAP343X, 1332 .flags = CLOCK_IN_OMAP343X,
1333 .clkdm_name = "core_l4_clkdm",
1307 .recalc = &omap2_clksel_recalc, 1334 .recalc = &omap2_clksel_recalc,
1308}; 1335};
1309 1336
@@ -1341,6 +1368,7 @@ static struct clk core_96m_fck = {
1341 .parent = &omap_96m_fck, 1368 .parent = &omap_96m_fck,
1342 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1369 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1343 PARENT_CONTROLS_CLOCK, 1370 PARENT_CONTROLS_CLOCK,
1371 .clkdm_name = "core_l4_clkdm",
1344 .recalc = &followparent_recalc, 1372 .recalc = &followparent_recalc,
1345}; 1373};
1346 1374
@@ -1351,6 +1379,7 @@ static struct clk mmchs3_fck = {
1351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1379 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1352 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1380 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1353 .flags = CLOCK_IN_OMAP3430ES2, 1381 .flags = CLOCK_IN_OMAP3430ES2,
1382 .clkdm_name = "core_l4_clkdm",
1354 .recalc = &followparent_recalc, 1383 .recalc = &followparent_recalc,
1355}; 1384};
1356 1385
@@ -1361,6 +1390,7 @@ static struct clk mmchs2_fck = {
1361 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1390 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1362 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1391 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1363 .flags = CLOCK_IN_OMAP343X, 1392 .flags = CLOCK_IN_OMAP343X,
1393 .clkdm_name = "core_l4_clkdm",
1364 .recalc = &followparent_recalc, 1394 .recalc = &followparent_recalc,
1365}; 1395};
1366 1396
@@ -1370,6 +1400,7 @@ static struct clk mspro_fck = {
1370 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1400 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1371 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1401 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1372 .flags = CLOCK_IN_OMAP343X, 1402 .flags = CLOCK_IN_OMAP343X,
1403 .clkdm_name = "core_l4_clkdm",
1373 .recalc = &followparent_recalc, 1404 .recalc = &followparent_recalc,
1374}; 1405};
1375 1406
@@ -1380,6 +1411,7 @@ static struct clk mmchs1_fck = {
1380 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1411 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1381 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1412 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1382 .flags = CLOCK_IN_OMAP343X, 1413 .flags = CLOCK_IN_OMAP343X,
1414 .clkdm_name = "core_l4_clkdm",
1383 .recalc = &followparent_recalc, 1415 .recalc = &followparent_recalc,
1384}; 1416};
1385 1417
@@ -1390,16 +1422,18 @@ static struct clk i2c3_fck = {
1390 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1422 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1391 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1423 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1392 .flags = CLOCK_IN_OMAP343X, 1424 .flags = CLOCK_IN_OMAP343X,
1425 .clkdm_name = "core_l4_clkdm",
1393 .recalc = &followparent_recalc, 1426 .recalc = &followparent_recalc,
1394}; 1427};
1395 1428
1396static struct clk i2c2_fck = { 1429static struct clk i2c2_fck = {
1397 .name = "i2c_fck", 1430 .name = "i2c_fck",
1398 .id = 2, 1431 .id = 2,
1399 .parent = &core_96m_fck, 1432 .parent = &core_96m_fck,
1400 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1433 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1401 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1434 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1402 .flags = CLOCK_IN_OMAP343X, 1435 .flags = CLOCK_IN_OMAP343X,
1436 .clkdm_name = "core_l4_clkdm",
1403 .recalc = &followparent_recalc, 1437 .recalc = &followparent_recalc,
1404}; 1438};
1405 1439
@@ -1410,6 +1444,7 @@ static struct clk i2c1_fck = {
1410 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1444 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1411 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1445 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1412 .flags = CLOCK_IN_OMAP343X, 1446 .flags = CLOCK_IN_OMAP343X,
1447 .clkdm_name = "core_l4_clkdm",
1413 .recalc = &followparent_recalc, 1448 .recalc = &followparent_recalc,
1414}; 1449};
1415 1450
@@ -1443,6 +1478,7 @@ static struct clk mcbsp5_fck = {
1443 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, 1478 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1444 .clksel = mcbsp_15_clksel, 1479 .clksel = mcbsp_15_clksel,
1445 .flags = CLOCK_IN_OMAP343X, 1480 .flags = CLOCK_IN_OMAP343X,
1481 .clkdm_name = "core_l4_clkdm",
1446 .recalc = &omap2_clksel_recalc, 1482 .recalc = &omap2_clksel_recalc,
1447}; 1483};
1448 1484
@@ -1456,6 +1492,7 @@ static struct clk mcbsp1_fck = {
1456 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, 1492 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1457 .clksel = mcbsp_15_clksel, 1493 .clksel = mcbsp_15_clksel,
1458 .flags = CLOCK_IN_OMAP343X, 1494 .flags = CLOCK_IN_OMAP343X,
1495 .clkdm_name = "core_l4_clkdm",
1459 .recalc = &omap2_clksel_recalc, 1496 .recalc = &omap2_clksel_recalc,
1460}; 1497};
1461 1498
@@ -1466,6 +1503,7 @@ static struct clk core_48m_fck = {
1466 .parent = &omap_48m_fck, 1503 .parent = &omap_48m_fck,
1467 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1504 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1468 PARENT_CONTROLS_CLOCK, 1505 PARENT_CONTROLS_CLOCK,
1506 .clkdm_name = "core_l4_clkdm",
1469 .recalc = &followparent_recalc, 1507 .recalc = &followparent_recalc,
1470}; 1508};
1471 1509
@@ -1543,6 +1581,7 @@ static struct clk core_12m_fck = {
1543 .parent = &omap_12m_fck, 1581 .parent = &omap_12m_fck,
1544 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1582 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1545 PARENT_CONTROLS_CLOCK, 1583 PARENT_CONTROLS_CLOCK,
1584 .clkdm_name = "core_l4_clkdm",
1546 .recalc = &followparent_recalc, 1585 .recalc = &followparent_recalc,
1547}; 1586};
1548 1587
@@ -1581,6 +1620,7 @@ static struct clk ssi_ssr_fck = {
1581 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, 1620 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1582 .clksel = ssi_ssr_clksel, 1621 .clksel = ssi_ssr_clksel,
1583 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1622 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1623 .clkdm_name = "core_l4_clkdm",
1584 .recalc = &omap2_clksel_recalc, 1624 .recalc = &omap2_clksel_recalc,
1585}; 1625};
1586 1626
@@ -1596,11 +1636,17 @@ static struct clk ssi_sst_fck = {
1596 1636
1597/* CORE_L3_ICK based clocks */ 1637/* CORE_L3_ICK based clocks */
1598 1638
1639/*
1640 * XXX must add clk_enable/clk_disable for these if standard code won't
1641 * handle it
1642 */
1599static struct clk core_l3_ick = { 1643static struct clk core_l3_ick = {
1600 .name = "core_l3_ick", 1644 .name = "core_l3_ick",
1601 .parent = &l3_ick, 1645 .parent = &l3_ick,
1646 .init = &omap2_init_clk_clkdm,
1602 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1647 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1603 PARENT_CONTROLS_CLOCK, 1648 PARENT_CONTROLS_CLOCK,
1649 .clkdm_name = "core_l3_clkdm",
1604 .recalc = &followparent_recalc, 1650 .recalc = &followparent_recalc,
1605}; 1651};
1606 1652
@@ -1610,6 +1656,7 @@ static struct clk hsotgusb_ick = {
1610 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1656 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1611 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1657 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1612 .flags = CLOCK_IN_OMAP343X, 1658 .flags = CLOCK_IN_OMAP343X,
1659 .clkdm_name = "core_l3_clkdm",
1613 .recalc = &followparent_recalc, 1660 .recalc = &followparent_recalc,
1614}; 1661};
1615 1662
@@ -1619,6 +1666,7 @@ static struct clk sdrc_ick = {
1619 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1666 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1620 .enable_bit = OMAP3430_EN_SDRC_SHIFT, 1667 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1621 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, 1668 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1669 .clkdm_name = "core_l3_clkdm",
1622 .recalc = &followparent_recalc, 1670 .recalc = &followparent_recalc,
1623}; 1671};
1624 1672
@@ -1627,6 +1675,7 @@ static struct clk gpmc_fck = {
1627 .parent = &core_l3_ick, 1675 .parent = &core_l3_ick,
1628 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | 1676 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1629 ENABLE_ON_INIT, 1677 ENABLE_ON_INIT,
1678 .clkdm_name = "core_l3_clkdm",
1630 .recalc = &followparent_recalc, 1679 .recalc = &followparent_recalc,
1631}; 1680};
1632 1681
@@ -1654,8 +1703,10 @@ static struct clk pka_ick = {
1654static struct clk core_l4_ick = { 1703static struct clk core_l4_ick = {
1655 .name = "core_l4_ick", 1704 .name = "core_l4_ick",
1656 .parent = &l4_ick, 1705 .parent = &l4_ick,
1706 .init = &omap2_init_clk_clkdm,
1657 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1707 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1658 PARENT_CONTROLS_CLOCK, 1708 PARENT_CONTROLS_CLOCK,
1709 .clkdm_name = "core_l4_clkdm",
1659 .recalc = &followparent_recalc, 1710 .recalc = &followparent_recalc,
1660}; 1711};
1661 1712
@@ -1665,6 +1716,7 @@ static struct clk usbtll_ick = {
1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1716 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1666 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1717 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1667 .flags = CLOCK_IN_OMAP3430ES2, 1718 .flags = CLOCK_IN_OMAP3430ES2,
1719 .clkdm_name = "core_l4_clkdm",
1668 .recalc = &followparent_recalc, 1720 .recalc = &followparent_recalc,
1669}; 1721};
1670 1722
@@ -1675,6 +1727,7 @@ static struct clk mmchs3_ick = {
1675 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1676 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1728 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1677 .flags = CLOCK_IN_OMAP3430ES2, 1729 .flags = CLOCK_IN_OMAP3430ES2,
1730 .clkdm_name = "core_l4_clkdm",
1678 .recalc = &followparent_recalc, 1731 .recalc = &followparent_recalc,
1679}; 1732};
1680 1733
@@ -1685,6 +1738,7 @@ static struct clk icr_ick = {
1685 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1738 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1686 .enable_bit = OMAP3430_EN_ICR_SHIFT, 1739 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1687 .flags = CLOCK_IN_OMAP343X, 1740 .flags = CLOCK_IN_OMAP343X,
1741 .clkdm_name = "core_l4_clkdm",
1688 .recalc = &followparent_recalc, 1742 .recalc = &followparent_recalc,
1689}; 1743};
1690 1744
@@ -1694,6 +1748,7 @@ static struct clk aes2_ick = {
1694 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1748 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1695 .enable_bit = OMAP3430_EN_AES2_SHIFT, 1749 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1696 .flags = CLOCK_IN_OMAP343X, 1750 .flags = CLOCK_IN_OMAP343X,
1751 .clkdm_name = "core_l4_clkdm",
1697 .recalc = &followparent_recalc, 1752 .recalc = &followparent_recalc,
1698}; 1753};
1699 1754
@@ -1703,6 +1758,7 @@ static struct clk sha12_ick = {
1703 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1758 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1704 .enable_bit = OMAP3430_EN_SHA12_SHIFT, 1759 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1705 .flags = CLOCK_IN_OMAP343X, 1760 .flags = CLOCK_IN_OMAP343X,
1761 .clkdm_name = "core_l4_clkdm",
1706 .recalc = &followparent_recalc, 1762 .recalc = &followparent_recalc,
1707}; 1763};
1708 1764
@@ -1712,6 +1768,7 @@ static struct clk des2_ick = {
1712 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1768 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1713 .enable_bit = OMAP3430_EN_DES2_SHIFT, 1769 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1714 .flags = CLOCK_IN_OMAP343X, 1770 .flags = CLOCK_IN_OMAP343X,
1771 .clkdm_name = "core_l4_clkdm",
1715 .recalc = &followparent_recalc, 1772 .recalc = &followparent_recalc,
1716}; 1773};
1717 1774
@@ -1722,6 +1779,7 @@ static struct clk mmchs2_ick = {
1722 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1779 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1723 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1780 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1724 .flags = CLOCK_IN_OMAP343X, 1781 .flags = CLOCK_IN_OMAP343X,
1782 .clkdm_name = "core_l4_clkdm",
1725 .recalc = &followparent_recalc, 1783 .recalc = &followparent_recalc,
1726}; 1784};
1727 1785
@@ -1732,6 +1790,7 @@ static struct clk mmchs1_ick = {
1732 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1790 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1733 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1791 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1734 .flags = CLOCK_IN_OMAP343X, 1792 .flags = CLOCK_IN_OMAP343X,
1793 .clkdm_name = "core_l4_clkdm",
1735 .recalc = &followparent_recalc, 1794 .recalc = &followparent_recalc,
1736}; 1795};
1737 1796
@@ -1741,6 +1800,7 @@ static struct clk mspro_ick = {
1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1800 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1742 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1801 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1743 .flags = CLOCK_IN_OMAP343X, 1802 .flags = CLOCK_IN_OMAP343X,
1803 .clkdm_name = "core_l4_clkdm",
1744 .recalc = &followparent_recalc, 1804 .recalc = &followparent_recalc,
1745}; 1805};
1746 1806
@@ -1750,6 +1810,7 @@ static struct clk hdq_ick = {
1750 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1751 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1811 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1752 .flags = CLOCK_IN_OMAP343X, 1812 .flags = CLOCK_IN_OMAP343X,
1813 .clkdm_name = "core_l4_clkdm",
1753 .recalc = &followparent_recalc, 1814 .recalc = &followparent_recalc,
1754}; 1815};
1755 1816
@@ -1760,6 +1821,7 @@ static struct clk mcspi4_ick = {
1760 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1821 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1761 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1822 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1762 .flags = CLOCK_IN_OMAP343X, 1823 .flags = CLOCK_IN_OMAP343X,
1824 .clkdm_name = "core_l4_clkdm",
1763 .recalc = &followparent_recalc, 1825 .recalc = &followparent_recalc,
1764}; 1826};
1765 1827
@@ -1770,6 +1832,7 @@ static struct clk mcspi3_ick = {
1770 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1832 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1771 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1833 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1772 .flags = CLOCK_IN_OMAP343X, 1834 .flags = CLOCK_IN_OMAP343X,
1835 .clkdm_name = "core_l4_clkdm",
1773 .recalc = &followparent_recalc, 1836 .recalc = &followparent_recalc,
1774}; 1837};
1775 1838
@@ -1780,6 +1843,7 @@ static struct clk mcspi2_ick = {
1780 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1843 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1781 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1844 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1782 .flags = CLOCK_IN_OMAP343X, 1845 .flags = CLOCK_IN_OMAP343X,
1846 .clkdm_name = "core_l4_clkdm",
1783 .recalc = &followparent_recalc, 1847 .recalc = &followparent_recalc,
1784}; 1848};
1785 1849
@@ -1790,6 +1854,7 @@ static struct clk mcspi1_ick = {
1790 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1854 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1791 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1855 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1792 .flags = CLOCK_IN_OMAP343X, 1856 .flags = CLOCK_IN_OMAP343X,
1857 .clkdm_name = "core_l4_clkdm",
1793 .recalc = &followparent_recalc, 1858 .recalc = &followparent_recalc,
1794}; 1859};
1795 1860
@@ -1800,6 +1865,7 @@ static struct clk i2c3_ick = {
1800 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1865 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1801 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1866 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1802 .flags = CLOCK_IN_OMAP343X, 1867 .flags = CLOCK_IN_OMAP343X,
1868 .clkdm_name = "core_l4_clkdm",
1803 .recalc = &followparent_recalc, 1869 .recalc = &followparent_recalc,
1804}; 1870};
1805 1871
@@ -1810,6 +1876,7 @@ static struct clk i2c2_ick = {
1810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1876 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1811 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1877 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1812 .flags = CLOCK_IN_OMAP343X, 1878 .flags = CLOCK_IN_OMAP343X,
1879 .clkdm_name = "core_l4_clkdm",
1813 .recalc = &followparent_recalc, 1880 .recalc = &followparent_recalc,
1814}; 1881};
1815 1882
@@ -1820,6 +1887,7 @@ static struct clk i2c1_ick = {
1820 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1887 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1821 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1888 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1822 .flags = CLOCK_IN_OMAP343X, 1889 .flags = CLOCK_IN_OMAP343X,
1890 .clkdm_name = "core_l4_clkdm",
1823 .recalc = &followparent_recalc, 1891 .recalc = &followparent_recalc,
1824}; 1892};
1825 1893
@@ -1829,6 +1897,7 @@ static struct clk uart2_ick = {
1829 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1897 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1830 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1898 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1831 .flags = CLOCK_IN_OMAP343X, 1899 .flags = CLOCK_IN_OMAP343X,
1900 .clkdm_name = "core_l4_clkdm",
1832 .recalc = &followparent_recalc, 1901 .recalc = &followparent_recalc,
1833}; 1902};
1834 1903
@@ -1838,6 +1907,7 @@ static struct clk uart1_ick = {
1838 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1907 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1839 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1908 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1840 .flags = CLOCK_IN_OMAP343X, 1909 .flags = CLOCK_IN_OMAP343X,
1910 .clkdm_name = "core_l4_clkdm",
1841 .recalc = &followparent_recalc, 1911 .recalc = &followparent_recalc,
1842}; 1912};
1843 1913
@@ -1847,6 +1917,7 @@ static struct clk gpt11_ick = {
1847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1917 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1848 .enable_bit = OMAP3430_EN_GPT11_SHIFT, 1918 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1849 .flags = CLOCK_IN_OMAP343X, 1919 .flags = CLOCK_IN_OMAP343X,
1920 .clkdm_name = "core_l4_clkdm",
1850 .recalc = &followparent_recalc, 1921 .recalc = &followparent_recalc,
1851}; 1922};
1852 1923
@@ -1856,6 +1927,7 @@ static struct clk gpt10_ick = {
1856 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1927 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1857 .enable_bit = OMAP3430_EN_GPT10_SHIFT, 1928 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1858 .flags = CLOCK_IN_OMAP343X, 1929 .flags = CLOCK_IN_OMAP343X,
1930 .clkdm_name = "core_l4_clkdm",
1859 .recalc = &followparent_recalc, 1931 .recalc = &followparent_recalc,
1860}; 1932};
1861 1933
@@ -1866,6 +1938,7 @@ static struct clk mcbsp5_ick = {
1866 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1938 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1867 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, 1939 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1868 .flags = CLOCK_IN_OMAP343X, 1940 .flags = CLOCK_IN_OMAP343X,
1941 .clkdm_name = "core_l4_clkdm",
1869 .recalc = &followparent_recalc, 1942 .recalc = &followparent_recalc,
1870}; 1943};
1871 1944
@@ -1876,6 +1949,7 @@ static struct clk mcbsp1_ick = {
1876 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1949 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1877 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, 1950 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1878 .flags = CLOCK_IN_OMAP343X, 1951 .flags = CLOCK_IN_OMAP343X,
1952 .clkdm_name = "core_l4_clkdm",
1879 .recalc = &followparent_recalc, 1953 .recalc = &followparent_recalc,
1880}; 1954};
1881 1955
@@ -1885,6 +1959,7 @@ static struct clk fac_ick = {
1885 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1959 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1886 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, 1960 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1887 .flags = CLOCK_IN_OMAP3430ES1, 1961 .flags = CLOCK_IN_OMAP3430ES1,
1962 .clkdm_name = "core_l4_clkdm",
1888 .recalc = &followparent_recalc, 1963 .recalc = &followparent_recalc,
1889}; 1964};
1890 1965
@@ -1894,6 +1969,7 @@ static struct clk mailboxes_ick = {
1894 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1969 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1895 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, 1970 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1896 .flags = CLOCK_IN_OMAP343X, 1971 .flags = CLOCK_IN_OMAP343X,
1972 .clkdm_name = "core_l4_clkdm",
1897 .recalc = &followparent_recalc, 1973 .recalc = &followparent_recalc,
1898}; 1974};
1899 1975
@@ -1913,6 +1989,7 @@ static struct clk ssi_l4_ick = {
1913 .parent = &l4_ick, 1989 .parent = &l4_ick,
1914 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1990 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1915 PARENT_CONTROLS_CLOCK, 1991 PARENT_CONTROLS_CLOCK,
1992 .clkdm_name = "core_l4_clkdm",
1916 .recalc = &followparent_recalc, 1993 .recalc = &followparent_recalc,
1917}; 1994};
1918 1995
@@ -1922,6 +1999,7 @@ static struct clk ssi_ick = {
1922 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1999 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923 .enable_bit = OMAP3430_EN_SSI_SHIFT, 2000 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1924 .flags = CLOCK_IN_OMAP343X, 2001 .flags = CLOCK_IN_OMAP343X,
2002 .clkdm_name = "core_l4_clkdm",
1925 .recalc = &followparent_recalc, 2003 .recalc = &followparent_recalc,
1926}; 2004};
1927 2005
@@ -1996,7 +2074,7 @@ static struct clk des1_ick = {
1996 2074
1997/* DSS */ 2075/* DSS */
1998static const struct clksel dss1_alwon_fck_clksel[] = { 2076static const struct clksel dss1_alwon_fck_clksel[] = {
1999 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 2077 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2000 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, 2078 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2001 { .parent = NULL } 2079 { .parent = NULL }
2002}; 2080};
@@ -2011,33 +2089,40 @@ static struct clk dss1_alwon_fck = {
2011 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, 2089 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
2012 .clksel = dss1_alwon_fck_clksel, 2090 .clksel = dss1_alwon_fck_clksel,
2013 .flags = CLOCK_IN_OMAP343X, 2091 .flags = CLOCK_IN_OMAP343X,
2092 .clkdm_name = "dss_clkdm",
2014 .recalc = &omap2_clksel_recalc, 2093 .recalc = &omap2_clksel_recalc,
2015}; 2094};
2016 2095
2017static struct clk dss_tv_fck = { 2096static struct clk dss_tv_fck = {
2018 .name = "dss_tv_fck", 2097 .name = "dss_tv_fck",
2019 .parent = &omap_54m_fck, 2098 .parent = &omap_54m_fck,
2099 .init = &omap2_init_clk_clkdm,
2020 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2100 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2021 .enable_bit = OMAP3430_EN_TV_SHIFT, 2101 .enable_bit = OMAP3430_EN_TV_SHIFT,
2022 .flags = CLOCK_IN_OMAP343X, 2102 .flags = CLOCK_IN_OMAP343X,
2103 .clkdm_name = "dss_clkdm",
2023 .recalc = &followparent_recalc, 2104 .recalc = &followparent_recalc,
2024}; 2105};
2025 2106
2026static struct clk dss_96m_fck = { 2107static struct clk dss_96m_fck = {
2027 .name = "dss_96m_fck", 2108 .name = "dss_96m_fck",
2028 .parent = &omap_96m_fck, 2109 .parent = &omap_96m_fck,
2110 .init = &omap2_init_clk_clkdm,
2029 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2111 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2030 .enable_bit = OMAP3430_EN_TV_SHIFT, 2112 .enable_bit = OMAP3430_EN_TV_SHIFT,
2031 .flags = CLOCK_IN_OMAP343X, 2113 .flags = CLOCK_IN_OMAP343X,
2114 .clkdm_name = "dss_clkdm",
2032 .recalc = &followparent_recalc, 2115 .recalc = &followparent_recalc,
2033}; 2116};
2034 2117
2035static struct clk dss2_alwon_fck = { 2118static struct clk dss2_alwon_fck = {
2036 .name = "dss2_alwon_fck", 2119 .name = "dss2_alwon_fck",
2037 .parent = &sys_ck, 2120 .parent = &sys_ck,
2121 .init = &omap2_init_clk_clkdm,
2038 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2122 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2039 .enable_bit = OMAP3430_EN_DSS2_SHIFT, 2123 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2040 .flags = CLOCK_IN_OMAP343X, 2124 .flags = CLOCK_IN_OMAP343X,
2125 .clkdm_name = "dss_clkdm",
2041 .recalc = &followparent_recalc, 2126 .recalc = &followparent_recalc,
2042}; 2127};
2043 2128
@@ -2045,16 +2130,18 @@ static struct clk dss_ick = {
2045 /* Handles both L3 and L4 clocks */ 2130 /* Handles both L3 and L4 clocks */
2046 .name = "dss_ick", 2131 .name = "dss_ick",
2047 .parent = &l4_ick, 2132 .parent = &l4_ick,
2133 .init = &omap2_init_clk_clkdm,
2048 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), 2134 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2049 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, 2135 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2050 .flags = CLOCK_IN_OMAP343X, 2136 .flags = CLOCK_IN_OMAP343X,
2137 .clkdm_name = "dss_clkdm",
2051 .recalc = &followparent_recalc, 2138 .recalc = &followparent_recalc,
2052}; 2139};
2053 2140
2054/* CAM */ 2141/* CAM */
2055 2142
2056static const struct clksel cam_mclk_clksel[] = { 2143static const struct clksel cam_mclk_clksel[] = {
2057 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 2144 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2058 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, 2145 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2059 { .parent = NULL } 2146 { .parent = NULL }
2060}; 2147};
@@ -2069,24 +2156,19 @@ static struct clk cam_mclk = {
2069 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), 2156 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2070 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2157 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2071 .flags = CLOCK_IN_OMAP343X, 2158 .flags = CLOCK_IN_OMAP343X,
2159 .clkdm_name = "cam_clkdm",
2072 .recalc = &omap2_clksel_recalc, 2160 .recalc = &omap2_clksel_recalc,
2073}; 2161};
2074 2162
2075static struct clk cam_l3_ick = { 2163static struct clk cam_ick = {
2076 .name = "cam_l3_ick", 2164 /* Handles both L3 and L4 clocks */
2077 .parent = &l3_ick, 2165 .name = "cam_ick",
2078 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2079 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2080 .flags = CLOCK_IN_OMAP343X,
2081 .recalc = &followparent_recalc,
2082};
2083
2084static struct clk cam_l4_ick = {
2085 .name = "cam_l4_ick",
2086 .parent = &l4_ick, 2166 .parent = &l4_ick,
2167 .init = &omap2_init_clk_clkdm,
2087 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), 2168 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2088 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2169 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2089 .flags = CLOCK_IN_OMAP343X, 2170 .flags = CLOCK_IN_OMAP343X,
2171 .clkdm_name = "cam_clkdm",
2090 .recalc = &followparent_recalc, 2172 .recalc = &followparent_recalc,
2091}; 2173};
2092 2174
@@ -2095,45 +2177,45 @@ static struct clk cam_l4_ick = {
2095static struct clk usbhost_120m_fck = { 2177static struct clk usbhost_120m_fck = {
2096 .name = "usbhost_120m_fck", 2178 .name = "usbhost_120m_fck",
2097 .parent = &omap_120m_fck, 2179 .parent = &omap_120m_fck,
2180 .init = &omap2_init_clk_clkdm,
2098 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), 2181 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2099 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, 2182 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2100 .flags = CLOCK_IN_OMAP3430ES2, 2183 .flags = CLOCK_IN_OMAP3430ES2,
2184 .clkdm_name = "usbhost_clkdm",
2101 .recalc = &followparent_recalc, 2185 .recalc = &followparent_recalc,
2102}; 2186};
2103 2187
2104static struct clk usbhost_48m_fck = { 2188static struct clk usbhost_48m_fck = {
2105 .name = "usbhost_48m_fck", 2189 .name = "usbhost_48m_fck",
2106 .parent = &omap_48m_fck, 2190 .parent = &omap_48m_fck,
2191 .init = &omap2_init_clk_clkdm,
2107 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), 2192 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2108 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, 2193 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2109 .flags = CLOCK_IN_OMAP3430ES2, 2194 .flags = CLOCK_IN_OMAP3430ES2,
2195 .clkdm_name = "usbhost_clkdm",
2110 .recalc = &followparent_recalc, 2196 .recalc = &followparent_recalc,
2111}; 2197};
2112 2198
2113static struct clk usbhost_l3_ick = { 2199static struct clk usbhost_ick = {
2114 .name = "usbhost_l3_ick", 2200 /* Handles both L3 and L4 clocks */
2115 .parent = &l3_ick, 2201 .name = "usbhost_ick",
2116 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2117 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2118 .flags = CLOCK_IN_OMAP3430ES2,
2119 .recalc = &followparent_recalc,
2120};
2121
2122static struct clk usbhost_l4_ick = {
2123 .name = "usbhost_l4_ick",
2124 .parent = &l4_ick, 2202 .parent = &l4_ick,
2203 .init = &omap2_init_clk_clkdm,
2125 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), 2204 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2126 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, 2205 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2127 .flags = CLOCK_IN_OMAP3430ES2, 2206 .flags = CLOCK_IN_OMAP3430ES2,
2207 .clkdm_name = "usbhost_clkdm",
2128 .recalc = &followparent_recalc, 2208 .recalc = &followparent_recalc,
2129}; 2209};
2130 2210
2131static struct clk usbhost_sar_fck = { 2211static struct clk usbhost_sar_fck = {
2132 .name = "usbhost_sar_fck", 2212 .name = "usbhost_sar_fck",
2133 .parent = &osc_sys_ck, 2213 .parent = &osc_sys_ck,
2214 .init = &omap2_init_clk_clkdm,
2134 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), 2215 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2135 .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, 2216 .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2136 .flags = CLOCK_IN_OMAP3430ES2, 2217 .flags = CLOCK_IN_OMAP3430ES2,
2218 .clkdm_name = "usbhost_clkdm",
2137 .recalc = &followparent_recalc, 2219 .recalc = &followparent_recalc,
2138}; 2220};
2139 2221
@@ -2175,6 +2257,7 @@ static struct clk usim_fck = {
2175 .recalc = &omap2_clksel_recalc, 2257 .recalc = &omap2_clksel_recalc,
2176}; 2258};
2177 2259
2260/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2178static struct clk gpt1_fck = { 2261static struct clk gpt1_fck = {
2179 .name = "gpt1_fck", 2262 .name = "gpt1_fck",
2180 .init = &omap2_init_clksel_parent, 2263 .init = &omap2_init_clksel_parent,
@@ -2184,13 +2267,16 @@ static struct clk gpt1_fck = {
2184 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, 2267 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2185 .clksel = omap343x_gpt_clksel, 2268 .clksel = omap343x_gpt_clksel,
2186 .flags = CLOCK_IN_OMAP343X, 2269 .flags = CLOCK_IN_OMAP343X,
2270 .clkdm_name = "wkup_clkdm",
2187 .recalc = &omap2_clksel_recalc, 2271 .recalc = &omap2_clksel_recalc,
2188}; 2272};
2189 2273
2190static struct clk wkup_32k_fck = { 2274static struct clk wkup_32k_fck = {
2191 .name = "wkup_32k_fck", 2275 .name = "wkup_32k_fck",
2276 .init = &omap2_init_clk_clkdm,
2192 .parent = &omap_32k_fck, 2277 .parent = &omap_32k_fck,
2193 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2278 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2279 .clkdm_name = "wkup_clkdm",
2194 .recalc = &followparent_recalc, 2280 .recalc = &followparent_recalc,
2195}; 2281};
2196 2282
@@ -2200,6 +2286,7 @@ static struct clk gpio1_fck = {
2200 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2286 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2201 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2287 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2202 .flags = CLOCK_IN_OMAP343X, 2288 .flags = CLOCK_IN_OMAP343X,
2289 .clkdm_name = "wkup_clkdm",
2203 .recalc = &followparent_recalc, 2290 .recalc = &followparent_recalc,
2204}; 2291};
2205 2292
@@ -2209,6 +2296,7 @@ static struct clk wdt2_fck = {
2209 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2296 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2210 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2297 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2211 .flags = CLOCK_IN_OMAP343X, 2298 .flags = CLOCK_IN_OMAP343X,
2299 .clkdm_name = "wkup_clkdm",
2212 .recalc = &followparent_recalc, 2300 .recalc = &followparent_recalc,
2213}; 2301};
2214 2302
@@ -2216,6 +2304,7 @@ static struct clk wkup_l4_ick = {
2216 .name = "wkup_l4_ick", 2304 .name = "wkup_l4_ick",
2217 .parent = &sys_ck, 2305 .parent = &sys_ck,
2218 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2306 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2307 .clkdm_name = "wkup_clkdm",
2219 .recalc = &followparent_recalc, 2308 .recalc = &followparent_recalc,
2220}; 2309};
2221 2310
@@ -2227,6 +2316,7 @@ static struct clk usim_ick = {
2227 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2316 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2228 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, 2317 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2229 .flags = CLOCK_IN_OMAP3430ES2, 2318 .flags = CLOCK_IN_OMAP3430ES2,
2319 .clkdm_name = "wkup_clkdm",
2230 .recalc = &followparent_recalc, 2320 .recalc = &followparent_recalc,
2231}; 2321};
2232 2322
@@ -2236,6 +2326,7 @@ static struct clk wdt2_ick = {
2236 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2326 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2237 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2327 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2238 .flags = CLOCK_IN_OMAP343X, 2328 .flags = CLOCK_IN_OMAP343X,
2329 .clkdm_name = "wkup_clkdm",
2239 .recalc = &followparent_recalc, 2330 .recalc = &followparent_recalc,
2240}; 2331};
2241 2332
@@ -2245,6 +2336,7 @@ static struct clk wdt1_ick = {
2245 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2336 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2246 .enable_bit = OMAP3430_EN_WDT1_SHIFT, 2337 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2247 .flags = CLOCK_IN_OMAP343X, 2338 .flags = CLOCK_IN_OMAP343X,
2339 .clkdm_name = "wkup_clkdm",
2248 .recalc = &followparent_recalc, 2340 .recalc = &followparent_recalc,
2249}; 2341};
2250 2342
@@ -2254,6 +2346,7 @@ static struct clk gpio1_ick = {
2254 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2346 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2255 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2347 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2256 .flags = CLOCK_IN_OMAP343X, 2348 .flags = CLOCK_IN_OMAP343X,
2349 .clkdm_name = "wkup_clkdm",
2257 .recalc = &followparent_recalc, 2350 .recalc = &followparent_recalc,
2258}; 2351};
2259 2352
@@ -2263,15 +2356,18 @@ static struct clk omap_32ksync_ick = {
2263 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2356 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2264 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, 2357 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2265 .flags = CLOCK_IN_OMAP343X, 2358 .flags = CLOCK_IN_OMAP343X,
2359 .clkdm_name = "wkup_clkdm",
2266 .recalc = &followparent_recalc, 2360 .recalc = &followparent_recalc,
2267}; 2361};
2268 2362
2363/* XXX This clock no longer exists in 3430 TRM rev F */
2269static struct clk gpt12_ick = { 2364static struct clk gpt12_ick = {
2270 .name = "gpt12_ick", 2365 .name = "gpt12_ick",
2271 .parent = &wkup_l4_ick, 2366 .parent = &wkup_l4_ick,
2272 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2367 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2273 .enable_bit = OMAP3430_EN_GPT12_SHIFT, 2368 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2274 .flags = CLOCK_IN_OMAP343X, 2369 .flags = CLOCK_IN_OMAP343X,
2370 .clkdm_name = "wkup_clkdm",
2275 .recalc = &followparent_recalc, 2371 .recalc = &followparent_recalc,
2276}; 2372};
2277 2373
@@ -2281,6 +2377,7 @@ static struct clk gpt1_ick = {
2281 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2377 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2282 .enable_bit = OMAP3430_EN_GPT1_SHIFT, 2378 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2283 .flags = CLOCK_IN_OMAP343X, 2379 .flags = CLOCK_IN_OMAP343X,
2380 .clkdm_name = "wkup_clkdm",
2284 .recalc = &followparent_recalc, 2381 .recalc = &followparent_recalc,
2285}; 2382};
2286 2383
@@ -2291,16 +2388,20 @@ static struct clk gpt1_ick = {
2291static struct clk per_96m_fck = { 2388static struct clk per_96m_fck = {
2292 .name = "per_96m_fck", 2389 .name = "per_96m_fck",
2293 .parent = &omap_96m_alwon_fck, 2390 .parent = &omap_96m_alwon_fck,
2391 .init = &omap2_init_clk_clkdm,
2294 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 2392 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2295 PARENT_CONTROLS_CLOCK, 2393 PARENT_CONTROLS_CLOCK,
2394 .clkdm_name = "per_clkdm",
2296 .recalc = &followparent_recalc, 2395 .recalc = &followparent_recalc,
2297}; 2396};
2298 2397
2299static struct clk per_48m_fck = { 2398static struct clk per_48m_fck = {
2300 .name = "per_48m_fck", 2399 .name = "per_48m_fck",
2301 .parent = &omap_48m_fck, 2400 .parent = &omap_48m_fck,
2401 .init = &omap2_init_clk_clkdm,
2302 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 2402 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2303 PARENT_CONTROLS_CLOCK, 2403 PARENT_CONTROLS_CLOCK,
2404 .clkdm_name = "per_clkdm",
2304 .recalc = &followparent_recalc, 2405 .recalc = &followparent_recalc,
2305}; 2406};
2306 2407
@@ -2310,6 +2411,7 @@ static struct clk uart3_fck = {
2310 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2411 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2311 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2412 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2312 .flags = CLOCK_IN_OMAP343X, 2413 .flags = CLOCK_IN_OMAP343X,
2414 .clkdm_name = "per_clkdm",
2313 .recalc = &followparent_recalc, 2415 .recalc = &followparent_recalc,
2314}; 2416};
2315 2417
@@ -2322,6 +2424,7 @@ static struct clk gpt2_fck = {
2322 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, 2424 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2323 .clksel = omap343x_gpt_clksel, 2425 .clksel = omap343x_gpt_clksel,
2324 .flags = CLOCK_IN_OMAP343X, 2426 .flags = CLOCK_IN_OMAP343X,
2427 .clkdm_name = "per_clkdm",
2325 .recalc = &omap2_clksel_recalc, 2428 .recalc = &omap2_clksel_recalc,
2326}; 2429};
2327 2430
@@ -2334,6 +2437,7 @@ static struct clk gpt3_fck = {
2334 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, 2437 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2335 .clksel = omap343x_gpt_clksel, 2438 .clksel = omap343x_gpt_clksel,
2336 .flags = CLOCK_IN_OMAP343X, 2439 .flags = CLOCK_IN_OMAP343X,
2440 .clkdm_name = "per_clkdm",
2337 .recalc = &omap2_clksel_recalc, 2441 .recalc = &omap2_clksel_recalc,
2338}; 2442};
2339 2443
@@ -2346,6 +2450,7 @@ static struct clk gpt4_fck = {
2346 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, 2450 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2347 .clksel = omap343x_gpt_clksel, 2451 .clksel = omap343x_gpt_clksel,
2348 .flags = CLOCK_IN_OMAP343X, 2452 .flags = CLOCK_IN_OMAP343X,
2453 .clkdm_name = "per_clkdm",
2349 .recalc = &omap2_clksel_recalc, 2454 .recalc = &omap2_clksel_recalc,
2350}; 2455};
2351 2456
@@ -2358,6 +2463,7 @@ static struct clk gpt5_fck = {
2358 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, 2463 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2359 .clksel = omap343x_gpt_clksel, 2464 .clksel = omap343x_gpt_clksel,
2360 .flags = CLOCK_IN_OMAP343X, 2465 .flags = CLOCK_IN_OMAP343X,
2466 .clkdm_name = "per_clkdm",
2361 .recalc = &omap2_clksel_recalc, 2467 .recalc = &omap2_clksel_recalc,
2362}; 2468};
2363 2469
@@ -2370,6 +2476,7 @@ static struct clk gpt6_fck = {
2370 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, 2476 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2371 .clksel = omap343x_gpt_clksel, 2477 .clksel = omap343x_gpt_clksel,
2372 .flags = CLOCK_IN_OMAP343X, 2478 .flags = CLOCK_IN_OMAP343X,
2479 .clkdm_name = "per_clkdm",
2373 .recalc = &omap2_clksel_recalc, 2480 .recalc = &omap2_clksel_recalc,
2374}; 2481};
2375 2482
@@ -2382,6 +2489,7 @@ static struct clk gpt7_fck = {
2382 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, 2489 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2383 .clksel = omap343x_gpt_clksel, 2490 .clksel = omap343x_gpt_clksel,
2384 .flags = CLOCK_IN_OMAP343X, 2491 .flags = CLOCK_IN_OMAP343X,
2492 .clkdm_name = "per_clkdm",
2385 .recalc = &omap2_clksel_recalc, 2493 .recalc = &omap2_clksel_recalc,
2386}; 2494};
2387 2495
@@ -2394,6 +2502,7 @@ static struct clk gpt8_fck = {
2394 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, 2502 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2395 .clksel = omap343x_gpt_clksel, 2503 .clksel = omap343x_gpt_clksel,
2396 .flags = CLOCK_IN_OMAP343X, 2504 .flags = CLOCK_IN_OMAP343X,
2505 .clkdm_name = "per_clkdm",
2397 .recalc = &omap2_clksel_recalc, 2506 .recalc = &omap2_clksel_recalc,
2398}; 2507};
2399 2508
@@ -2406,12 +2515,14 @@ static struct clk gpt9_fck = {
2406 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, 2515 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2407 .clksel = omap343x_gpt_clksel, 2516 .clksel = omap343x_gpt_clksel,
2408 .flags = CLOCK_IN_OMAP343X, 2517 .flags = CLOCK_IN_OMAP343X,
2518 .clkdm_name = "per_clkdm",
2409 .recalc = &omap2_clksel_recalc, 2519 .recalc = &omap2_clksel_recalc,
2410}; 2520};
2411 2521
2412static struct clk per_32k_alwon_fck = { 2522static struct clk per_32k_alwon_fck = {
2413 .name = "per_32k_alwon_fck", 2523 .name = "per_32k_alwon_fck",
2414 .parent = &omap_32k_fck, 2524 .parent = &omap_32k_fck,
2525 .clkdm_name = "per_clkdm",
2415 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2526 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2416 .recalc = &followparent_recalc, 2527 .recalc = &followparent_recalc,
2417}; 2528};
@@ -2422,6 +2533,7 @@ static struct clk gpio6_fck = {
2422 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2533 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2423 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2534 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2424 .flags = CLOCK_IN_OMAP343X, 2535 .flags = CLOCK_IN_OMAP343X,
2536 .clkdm_name = "per_clkdm",
2425 .recalc = &followparent_recalc, 2537 .recalc = &followparent_recalc,
2426}; 2538};
2427 2539
@@ -2431,6 +2543,7 @@ static struct clk gpio5_fck = {
2431 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2543 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2432 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2544 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2433 .flags = CLOCK_IN_OMAP343X, 2545 .flags = CLOCK_IN_OMAP343X,
2546 .clkdm_name = "per_clkdm",
2434 .recalc = &followparent_recalc, 2547 .recalc = &followparent_recalc,
2435}; 2548};
2436 2549
@@ -2440,6 +2553,7 @@ static struct clk gpio4_fck = {
2440 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2553 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2441 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2554 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2442 .flags = CLOCK_IN_OMAP343X, 2555 .flags = CLOCK_IN_OMAP343X,
2556 .clkdm_name = "per_clkdm",
2443 .recalc = &followparent_recalc, 2557 .recalc = &followparent_recalc,
2444}; 2558};
2445 2559
@@ -2449,6 +2563,7 @@ static struct clk gpio3_fck = {
2449 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2563 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2450 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2564 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2451 .flags = CLOCK_IN_OMAP343X, 2565 .flags = CLOCK_IN_OMAP343X,
2566 .clkdm_name = "per_clkdm",
2452 .recalc = &followparent_recalc, 2567 .recalc = &followparent_recalc,
2453}; 2568};
2454 2569
@@ -2458,6 +2573,7 @@ static struct clk gpio2_fck = {
2458 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2573 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2459 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2574 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2460 .flags = CLOCK_IN_OMAP343X, 2575 .flags = CLOCK_IN_OMAP343X,
2576 .clkdm_name = "per_clkdm",
2461 .recalc = &followparent_recalc, 2577 .recalc = &followparent_recalc,
2462}; 2578};
2463 2579
@@ -2467,6 +2583,7 @@ static struct clk wdt3_fck = {
2467 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2583 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2468 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2584 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2469 .flags = CLOCK_IN_OMAP343X, 2585 .flags = CLOCK_IN_OMAP343X,
2586 .clkdm_name = "per_clkdm",
2470 .recalc = &followparent_recalc, 2587 .recalc = &followparent_recalc,
2471}; 2588};
2472 2589
@@ -2475,6 +2592,7 @@ static struct clk per_l4_ick = {
2475 .parent = &l4_ick, 2592 .parent = &l4_ick,
2476 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 2593 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2477 PARENT_CONTROLS_CLOCK, 2594 PARENT_CONTROLS_CLOCK,
2595 .clkdm_name = "per_clkdm",
2478 .recalc = &followparent_recalc, 2596 .recalc = &followparent_recalc,
2479}; 2597};
2480 2598
@@ -2484,6 +2602,7 @@ static struct clk gpio6_ick = {
2484 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2602 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2485 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2603 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2486 .flags = CLOCK_IN_OMAP343X, 2604 .flags = CLOCK_IN_OMAP343X,
2605 .clkdm_name = "per_clkdm",
2487 .recalc = &followparent_recalc, 2606 .recalc = &followparent_recalc,
2488}; 2607};
2489 2608
@@ -2493,6 +2612,7 @@ static struct clk gpio5_ick = {
2493 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2612 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2494 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2613 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2495 .flags = CLOCK_IN_OMAP343X, 2614 .flags = CLOCK_IN_OMAP343X,
2615 .clkdm_name = "per_clkdm",
2496 .recalc = &followparent_recalc, 2616 .recalc = &followparent_recalc,
2497}; 2617};
2498 2618
@@ -2502,6 +2622,7 @@ static struct clk gpio4_ick = {
2502 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2622 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2503 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2623 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2504 .flags = CLOCK_IN_OMAP343X, 2624 .flags = CLOCK_IN_OMAP343X,
2625 .clkdm_name = "per_clkdm",
2505 .recalc = &followparent_recalc, 2626 .recalc = &followparent_recalc,
2506}; 2627};
2507 2628
@@ -2511,6 +2632,7 @@ static struct clk gpio3_ick = {
2511 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2632 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2512 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2633 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2513 .flags = CLOCK_IN_OMAP343X, 2634 .flags = CLOCK_IN_OMAP343X,
2635 .clkdm_name = "per_clkdm",
2514 .recalc = &followparent_recalc, 2636 .recalc = &followparent_recalc,
2515}; 2637};
2516 2638
@@ -2520,6 +2642,7 @@ static struct clk gpio2_ick = {
2520 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2642 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2521 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2643 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2522 .flags = CLOCK_IN_OMAP343X, 2644 .flags = CLOCK_IN_OMAP343X,
2645 .clkdm_name = "per_clkdm",
2523 .recalc = &followparent_recalc, 2646 .recalc = &followparent_recalc,
2524}; 2647};
2525 2648
@@ -2529,6 +2652,7 @@ static struct clk wdt3_ick = {
2529 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2652 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2530 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2653 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2531 .flags = CLOCK_IN_OMAP343X, 2654 .flags = CLOCK_IN_OMAP343X,
2655 .clkdm_name = "per_clkdm",
2532 .recalc = &followparent_recalc, 2656 .recalc = &followparent_recalc,
2533}; 2657};
2534 2658
@@ -2538,6 +2662,7 @@ static struct clk uart3_ick = {
2538 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2662 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2539 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2663 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2540 .flags = CLOCK_IN_OMAP343X, 2664 .flags = CLOCK_IN_OMAP343X,
2665 .clkdm_name = "per_clkdm",
2541 .recalc = &followparent_recalc, 2666 .recalc = &followparent_recalc,
2542}; 2667};
2543 2668
@@ -2547,6 +2672,7 @@ static struct clk gpt9_ick = {
2547 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2672 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2548 .enable_bit = OMAP3430_EN_GPT9_SHIFT, 2673 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2549 .flags = CLOCK_IN_OMAP343X, 2674 .flags = CLOCK_IN_OMAP343X,
2675 .clkdm_name = "per_clkdm",
2550 .recalc = &followparent_recalc, 2676 .recalc = &followparent_recalc,
2551}; 2677};
2552 2678
@@ -2556,6 +2682,7 @@ static struct clk gpt8_ick = {
2556 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2682 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2557 .enable_bit = OMAP3430_EN_GPT8_SHIFT, 2683 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2558 .flags = CLOCK_IN_OMAP343X, 2684 .flags = CLOCK_IN_OMAP343X,
2685 .clkdm_name = "per_clkdm",
2559 .recalc = &followparent_recalc, 2686 .recalc = &followparent_recalc,
2560}; 2687};
2561 2688
@@ -2565,6 +2692,7 @@ static struct clk gpt7_ick = {
2565 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2692 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2566 .enable_bit = OMAP3430_EN_GPT7_SHIFT, 2693 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2567 .flags = CLOCK_IN_OMAP343X, 2694 .flags = CLOCK_IN_OMAP343X,
2695 .clkdm_name = "per_clkdm",
2568 .recalc = &followparent_recalc, 2696 .recalc = &followparent_recalc,
2569}; 2697};
2570 2698
@@ -2574,6 +2702,7 @@ static struct clk gpt6_ick = {
2574 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2702 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2575 .enable_bit = OMAP3430_EN_GPT6_SHIFT, 2703 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2576 .flags = CLOCK_IN_OMAP343X, 2704 .flags = CLOCK_IN_OMAP343X,
2705 .clkdm_name = "per_clkdm",
2577 .recalc = &followparent_recalc, 2706 .recalc = &followparent_recalc,
2578}; 2707};
2579 2708
@@ -2583,6 +2712,7 @@ static struct clk gpt5_ick = {
2583 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2712 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2584 .enable_bit = OMAP3430_EN_GPT5_SHIFT, 2713 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2585 .flags = CLOCK_IN_OMAP343X, 2714 .flags = CLOCK_IN_OMAP343X,
2715 .clkdm_name = "per_clkdm",
2586 .recalc = &followparent_recalc, 2716 .recalc = &followparent_recalc,
2587}; 2717};
2588 2718
@@ -2592,6 +2722,7 @@ static struct clk gpt4_ick = {
2592 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2722 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2593 .enable_bit = OMAP3430_EN_GPT4_SHIFT, 2723 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2594 .flags = CLOCK_IN_OMAP343X, 2724 .flags = CLOCK_IN_OMAP343X,
2725 .clkdm_name = "per_clkdm",
2595 .recalc = &followparent_recalc, 2726 .recalc = &followparent_recalc,
2596}; 2727};
2597 2728
@@ -2601,6 +2732,7 @@ static struct clk gpt3_ick = {
2601 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2732 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2602 .enable_bit = OMAP3430_EN_GPT3_SHIFT, 2733 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2603 .flags = CLOCK_IN_OMAP343X, 2734 .flags = CLOCK_IN_OMAP343X,
2735 .clkdm_name = "per_clkdm",
2604 .recalc = &followparent_recalc, 2736 .recalc = &followparent_recalc,
2605}; 2737};
2606 2738
@@ -2610,6 +2742,7 @@ static struct clk gpt2_ick = {
2610 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2742 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2611 .enable_bit = OMAP3430_EN_GPT2_SHIFT, 2743 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2612 .flags = CLOCK_IN_OMAP343X, 2744 .flags = CLOCK_IN_OMAP343X,
2745 .clkdm_name = "per_clkdm",
2613 .recalc = &followparent_recalc, 2746 .recalc = &followparent_recalc,
2614}; 2747};
2615 2748
@@ -2620,6 +2753,7 @@ static struct clk mcbsp2_ick = {
2620 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2753 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2621 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, 2754 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2622 .flags = CLOCK_IN_OMAP343X, 2755 .flags = CLOCK_IN_OMAP343X,
2756 .clkdm_name = "per_clkdm",
2623 .recalc = &followparent_recalc, 2757 .recalc = &followparent_recalc,
2624}; 2758};
2625 2759
@@ -2630,6 +2764,7 @@ static struct clk mcbsp3_ick = {
2630 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2764 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2631 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, 2765 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2632 .flags = CLOCK_IN_OMAP343X, 2766 .flags = CLOCK_IN_OMAP343X,
2767 .clkdm_name = "per_clkdm",
2633 .recalc = &followparent_recalc, 2768 .recalc = &followparent_recalc,
2634}; 2769};
2635 2770
@@ -2640,12 +2775,13 @@ static struct clk mcbsp4_ick = {
2640 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2775 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2641 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, 2776 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2642 .flags = CLOCK_IN_OMAP343X, 2777 .flags = CLOCK_IN_OMAP343X,
2778 .clkdm_name = "per_clkdm",
2643 .recalc = &followparent_recalc, 2779 .recalc = &followparent_recalc,
2644}; 2780};
2645 2781
2646static const struct clksel mcbsp_234_clksel[] = { 2782static const struct clksel mcbsp_234_clksel[] = {
2647 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, 2783 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2648 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, 2784 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2649 { .parent = NULL } 2785 { .parent = NULL }
2650}; 2786};
2651 2787
@@ -2659,6 +2795,7 @@ static struct clk mcbsp2_fck = {
2659 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, 2795 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2660 .clksel = mcbsp_234_clksel, 2796 .clksel = mcbsp_234_clksel,
2661 .flags = CLOCK_IN_OMAP343X, 2797 .flags = CLOCK_IN_OMAP343X,
2798 .clkdm_name = "per_clkdm",
2662 .recalc = &omap2_clksel_recalc, 2799 .recalc = &omap2_clksel_recalc,
2663}; 2800};
2664 2801
@@ -2672,6 +2809,7 @@ static struct clk mcbsp3_fck = {
2672 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, 2809 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2673 .clksel = mcbsp_234_clksel, 2810 .clksel = mcbsp_234_clksel,
2674 .flags = CLOCK_IN_OMAP343X, 2811 .flags = CLOCK_IN_OMAP343X,
2812 .clkdm_name = "per_clkdm",
2675 .recalc = &omap2_clksel_recalc, 2813 .recalc = &omap2_clksel_recalc,
2676}; 2814};
2677 2815
@@ -2685,6 +2823,7 @@ static struct clk mcbsp4_fck = {
2685 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, 2823 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2686 .clksel = mcbsp_234_clksel, 2824 .clksel = mcbsp_234_clksel,
2687 .flags = CLOCK_IN_OMAP343X, 2825 .flags = CLOCK_IN_OMAP343X,
2826 .clkdm_name = "per_clkdm",
2688 .recalc = &omap2_clksel_recalc, 2827 .recalc = &omap2_clksel_recalc,
2689}; 2828};
2690 2829
@@ -2732,6 +2871,7 @@ static struct clk emu_src_ck = {
2732 .clksel_mask = OMAP3430_MUX_CTRL_MASK, 2871 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2733 .clksel = emu_src_clksel, 2872 .clksel = emu_src_clksel,
2734 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2873 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2874 .clkdm_name = "emu_clkdm",
2735 .recalc = &omap2_clksel_recalc, 2875 .recalc = &omap2_clksel_recalc,
2736}; 2876};
2737 2877
@@ -2755,6 +2895,7 @@ static struct clk pclk_fck = {
2755 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, 2895 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2756 .clksel = pclk_emu_clksel, 2896 .clksel = pclk_emu_clksel,
2757 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2897 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2898 .clkdm_name = "emu_clkdm",
2758 .recalc = &omap2_clksel_recalc, 2899 .recalc = &omap2_clksel_recalc,
2759}; 2900};
2760 2901
@@ -2777,6 +2918,7 @@ static struct clk pclkx2_fck = {
2777 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, 2918 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2778 .clksel = pclkx2_emu_clksel, 2919 .clksel = pclkx2_emu_clksel,
2779 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2920 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2921 .clkdm_name = "emu_clkdm",
2780 .recalc = &omap2_clksel_recalc, 2922 .recalc = &omap2_clksel_recalc,
2781}; 2923};
2782 2924
@@ -2792,6 +2934,7 @@ static struct clk atclk_fck = {
2792 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, 2934 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2793 .clksel = atclk_emu_clksel, 2935 .clksel = atclk_emu_clksel,
2794 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2936 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2937 .clkdm_name = "emu_clkdm",
2795 .recalc = &omap2_clksel_recalc, 2938 .recalc = &omap2_clksel_recalc,
2796}; 2939};
2797 2940
@@ -2802,6 +2945,7 @@ static struct clk traceclk_src_fck = {
2802 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, 2945 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2803 .clksel = emu_src_clksel, 2946 .clksel = emu_src_clksel,
2804 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2947 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2948 .clkdm_name = "emu_clkdm",
2805 .recalc = &omap2_clksel_recalc, 2949 .recalc = &omap2_clksel_recalc,
2806}; 2950};
2807 2951
@@ -2824,6 +2968,7 @@ static struct clk traceclk_fck = {
2824 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, 2968 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2825 .clksel = traceclk_clksel, 2969 .clksel = traceclk_clksel,
2826 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, 2970 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2971 .clkdm_name = "emu_clkdm",
2827 .recalc = &omap2_clksel_recalc, 2972 .recalc = &omap2_clksel_recalc,
2828}; 2973};
2829 2974
@@ -2853,11 +2998,13 @@ static struct clk sr_l4_ick = {
2853 .name = "sr_l4_ick", 2998 .name = "sr_l4_ick",
2854 .parent = &l4_ick, 2999 .parent = &l4_ick,
2855 .flags = CLOCK_IN_OMAP343X, 3000 .flags = CLOCK_IN_OMAP343X,
3001 .clkdm_name = "core_l4_clkdm",
2856 .recalc = &followparent_recalc, 3002 .recalc = &followparent_recalc,
2857}; 3003};
2858 3004
2859/* SECURE_32K_FCK clocks */ 3005/* SECURE_32K_FCK clocks */
2860 3006
3007/* XXX This clock no longer exists in 3430 TRM rev F */
2861static struct clk gpt12_fck = { 3008static struct clk gpt12_fck = {
2862 .name = "gpt12_fck", 3009 .name = "gpt12_fck",
2863 .parent = &secure_32k_fck, 3010 .parent = &secure_32k_fck,
@@ -2933,6 +3080,7 @@ static struct clk *onchip_34xx_clks[] __initdata = {
2933 &l3_ick, 3080 &l3_ick,
2934 &l4_ick, 3081 &l4_ick,
2935 &rm_ick, 3082 &rm_ick,
3083 &gfx_l3_ck,
2936 &gfx_l3_fck, 3084 &gfx_l3_fck,
2937 &gfx_l3_ick, 3085 &gfx_l3_ick,
2938 &gfx_cg1_ck, 3086 &gfx_cg1_ck,
@@ -3014,12 +3162,10 @@ static struct clk *onchip_34xx_clks[] __initdata = {
3014 &dss2_alwon_fck, 3162 &dss2_alwon_fck,
3015 &dss_ick, 3163 &dss_ick,
3016 &cam_mclk, 3164 &cam_mclk,
3017 &cam_l3_ick, 3165 &cam_ick,
3018 &cam_l4_ick,
3019 &usbhost_120m_fck, 3166 &usbhost_120m_fck,
3020 &usbhost_48m_fck, 3167 &usbhost_48m_fck,
3021 &usbhost_l3_ick, 3168 &usbhost_ick,
3022 &usbhost_l4_ick,
3023 &usbhost_sar_fck, 3169 &usbhost_sar_fck,
3024 &usim_fck, 3170 &usim_fck,
3025 &gpt1_fck, 3171 &gpt1_fck,
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
new file mode 100644
index 000000000000..4c3ce9cfd948
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -0,0 +1,623 @@
1/*
2 * OMAP2/3 clockdomain framework functions
3 *
4 * Copyright (C) 2008 Texas Instruments, Inc.
5 * Copyright (C) 2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley and Jouni Högander
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifdef CONFIG_OMAP_DEBUG_CLOCKDOMAIN
14# define DEBUG
15#endif
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/device.h>
20#include <linux/list.h>
21#include <linux/errno.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/limits.h>
25
26#include <linux/io.h>
27
28#include <linux/bitops.h>
29
30#include <mach/clock.h>
31
32#include "prm.h"
33#include "prm-regbits-24xx.h"
34#include "cm.h"
35
36#include <mach/powerdomain.h>
37#include <mach/clockdomain.h>
38
39/* clkdm_list contains all registered struct clockdomains */
40static LIST_HEAD(clkdm_list);
41
42/* clkdm_mutex protects clkdm_list add and del ops */
43static DEFINE_MUTEX(clkdm_mutex);
44
45/* array of powerdomain deps to be added/removed when clkdm in hwsup mode */
46static struct clkdm_pwrdm_autodep *autodeps;
47
48
49/* Private functions */
50
51/*
52 * _autodep_lookup - resolve autodep pwrdm names to pwrdm pointers; store
53 * @autodep: struct clkdm_pwrdm_autodep * to resolve
54 *
55 * Resolve autodep powerdomain names to powerdomain pointers via
56 * pwrdm_lookup() and store the pointers in the autodep structure. An
57 * "autodep" is a powerdomain sleep/wakeup dependency that is
58 * automatically added and removed whenever clocks in the associated
59 * clockdomain are enabled or disabled (respectively) when the
60 * clockdomain is in hardware-supervised mode. Meant to be called
61 * once at clockdomain layer initialization, since these should remain
62 * fixed for a particular architecture. No return value.
63 */
64static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep)
65{
66 struct powerdomain *pwrdm;
67
68 if (!autodep)
69 return;
70
71 if (!omap_chip_is(autodep->omap_chip))
72 return;
73
74 pwrdm = pwrdm_lookup(autodep->pwrdm_name);
75 if (!pwrdm) {
76 pr_debug("clockdomain: _autodep_lookup: powerdomain %s "
77 "does not exist\n", autodep->pwrdm_name);
78 WARN_ON(1);
79 return;
80 }
81 autodep->pwrdm = pwrdm;
82
83 return;
84}
85
86/*
87 * _clkdm_add_autodeps - add auto sleepdeps/wkdeps to clkdm upon clock enable
88 * @clkdm: struct clockdomain *
89 *
90 * Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm'
91 * in hardware-supervised mode. Meant to be called from clock framework
92 * when a clock inside clockdomain 'clkdm' is enabled. No return value.
93 */
94static void _clkdm_add_autodeps(struct clockdomain *clkdm)
95{
96 struct clkdm_pwrdm_autodep *autodep;
97
98 for (autodep = autodeps; autodep->pwrdm_name; autodep++) {
99 if (!autodep->pwrdm)
100 continue;
101
102 pr_debug("clockdomain: adding %s sleepdep/wkdep for "
103 "pwrdm %s\n", autodep->pwrdm_name,
104 clkdm->pwrdm->name);
105
106 pwrdm_add_sleepdep(clkdm->pwrdm, autodep->pwrdm);
107 pwrdm_add_wkdep(clkdm->pwrdm, autodep->pwrdm);
108 }
109}
110
111/*
112 * _clkdm_add_autodeps - remove auto sleepdeps/wkdeps from clkdm
113 * @clkdm: struct clockdomain *
114 *
115 * Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm'
116 * in hardware-supervised mode. Meant to be called from clock framework
117 * when a clock inside clockdomain 'clkdm' is disabled. No return value.
118 */
119static void _clkdm_del_autodeps(struct clockdomain *clkdm)
120{
121 struct clkdm_pwrdm_autodep *autodep;
122
123 for (autodep = autodeps; autodep->pwrdm_name; autodep++) {
124 if (!autodep->pwrdm)
125 continue;
126
127 pr_debug("clockdomain: removing %s sleepdep/wkdep for "
128 "pwrdm %s\n", autodep->pwrdm_name,
129 clkdm->pwrdm->name);
130
131 pwrdm_del_sleepdep(clkdm->pwrdm, autodep->pwrdm);
132 pwrdm_del_wkdep(clkdm->pwrdm, autodep->pwrdm);
133 }
134}
135
136
137static struct clockdomain *_clkdm_lookup(const char *name)
138{
139 struct clockdomain *clkdm, *temp_clkdm;
140
141 if (!name)
142 return NULL;
143
144 clkdm = NULL;
145
146 list_for_each_entry(temp_clkdm, &clkdm_list, node) {
147 if (!strcmp(name, temp_clkdm->name)) {
148 clkdm = temp_clkdm;
149 break;
150 }
151 }
152
153 return clkdm;
154}
155
156
157/* Public functions */
158
159/**
160 * clkdm_init - set up the clockdomain layer
161 * @clkdms: optional pointer to an array of clockdomains to register
162 * @init_autodeps: optional pointer to an array of autodeps to register
163 *
164 * Set up internal state. If a pointer to an array of clockdomains
165 * was supplied, loop through the list of clockdomains, register all
166 * that are available on the current platform. Similarly, if a
167 * pointer to an array of clockdomain-powerdomain autodependencies was
168 * provided, register those. No return value.
169 */
170void clkdm_init(struct clockdomain **clkdms,
171 struct clkdm_pwrdm_autodep *init_autodeps)
172{
173 struct clockdomain **c = NULL;
174 struct clkdm_pwrdm_autodep *autodep = NULL;
175
176 if (clkdms)
177 for (c = clkdms; *c; c++)
178 clkdm_register(*c);
179
180 autodeps = init_autodeps;
181 if (autodeps)
182 for (autodep = autodeps; autodep->pwrdm_name; autodep++)
183 _autodep_lookup(autodep);
184}
185
186/**
187 * clkdm_register - register a clockdomain
188 * @clkdm: struct clockdomain * to register
189 *
190 * Adds a clockdomain to the internal clockdomain list.
191 * Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is
192 * already registered by the provided name, or 0 upon success.
193 */
194int clkdm_register(struct clockdomain *clkdm)
195{
196 int ret = -EINVAL;
197 struct powerdomain *pwrdm;
198
199 if (!clkdm || !clkdm->name)
200 return -EINVAL;
201
202 if (!omap_chip_is(clkdm->omap_chip))
203 return -EINVAL;
204
205 pwrdm = pwrdm_lookup(clkdm->pwrdm_name);
206 if (!pwrdm) {
207 pr_debug("clockdomain: clkdm_register %s: powerdomain %s "
208 "does not exist\n", clkdm->name, clkdm->pwrdm_name);
209 return -EINVAL;
210 }
211 clkdm->pwrdm = pwrdm;
212
213 mutex_lock(&clkdm_mutex);
214 /* Verify that the clockdomain is not already registered */
215 if (_clkdm_lookup(clkdm->name)) {
216 ret = -EEXIST;
217 goto cr_unlock;
218 };
219
220 list_add(&clkdm->node, &clkdm_list);
221
222 pwrdm_add_clkdm(pwrdm, clkdm);
223
224 pr_debug("clockdomain: registered %s\n", clkdm->name);
225 ret = 0;
226
227cr_unlock:
228 mutex_unlock(&clkdm_mutex);
229
230 return ret;
231}
232
233/**
234 * clkdm_unregister - unregister a clockdomain
235 * @clkdm: struct clockdomain * to unregister
236 *
237 * Removes a clockdomain from the internal clockdomain list. Returns
238 * -EINVAL if clkdm argument is NULL.
239 */
240int clkdm_unregister(struct clockdomain *clkdm)
241{
242 if (!clkdm)
243 return -EINVAL;
244
245 pwrdm_del_clkdm(clkdm->pwrdm, clkdm);
246
247 mutex_lock(&clkdm_mutex);
248 list_del(&clkdm->node);
249 mutex_unlock(&clkdm_mutex);
250
251 pr_debug("clockdomain: unregistered %s\n", clkdm->name);
252
253 return 0;
254}
255
256/**
257 * clkdm_lookup - look up a clockdomain by name, return a pointer
258 * @name: name of clockdomain
259 *
260 * Find a registered clockdomain by its name. Returns a pointer to the
261 * struct clockdomain if found, or NULL otherwise.
262 */
263struct clockdomain *clkdm_lookup(const char *name)
264{
265 struct clockdomain *clkdm, *temp_clkdm;
266
267 if (!name)
268 return NULL;
269
270 clkdm = NULL;
271
272 mutex_lock(&clkdm_mutex);
273 list_for_each_entry(temp_clkdm, &clkdm_list, node) {
274 if (!strcmp(name, temp_clkdm->name)) {
275 clkdm = temp_clkdm;
276 break;
277 }
278 }
279 mutex_unlock(&clkdm_mutex);
280
281 return clkdm;
282}
283
284/**
285 * clkdm_for_each - call function on each registered clockdomain
286 * @fn: callback function *
287 *
288 * Call the supplied function for each registered clockdomain.
289 * The callback function can return anything but 0 to bail
290 * out early from the iterator. The callback function is called with
291 * the clkdm_mutex held, so no clockdomain structure manipulation
292 * functions should be called from the callback, although hardware
293 * clockdomain control functions are fine. Returns the last return
294 * value of the callback function, which should be 0 for success or
295 * anything else to indicate failure; or -EINVAL if the function pointer
296 * is null.
297 */
298int clkdm_for_each(int (*fn)(struct clockdomain *clkdm))
299{
300 struct clockdomain *clkdm;
301 int ret = 0;
302
303 if (!fn)
304 return -EINVAL;
305
306 mutex_lock(&clkdm_mutex);
307 list_for_each_entry(clkdm, &clkdm_list, node) {
308 ret = (*fn)(clkdm);
309 if (ret)
310 break;
311 }
312 mutex_unlock(&clkdm_mutex);
313
314 return ret;
315}
316
317
318/**
319 * clkdm_get_pwrdm - return a ptr to the pwrdm that this clkdm resides in
320 * @clkdm: struct clockdomain *
321 *
322 * Return a pointer to the struct powerdomain that the specified clockdomain
323 * 'clkdm' exists in, or returns NULL if clkdm argument is NULL.
324 */
325struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
326{
327 if (!clkdm)
328 return NULL;
329
330 return clkdm->pwrdm;
331}
332
333
334/* Hardware clockdomain control */
335
336/**
337 * omap2_clkdm_clktrctrl_read - read the clkdm's current state transition mode
338 * @clk: struct clk * of a clockdomain
339 *
340 * Return the clockdomain's current state transition mode from the
341 * corresponding domain CM_CLKSTCTRL register. Returns -EINVAL if clk
342 * is NULL or the current mode upon success.
343 */
344static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
345{
346 u32 v;
347
348 if (!clkdm)
349 return -EINVAL;
350
351 v = cm_read_mod_reg(clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
352 v &= clkdm->clktrctrl_mask;
353 v >>= __ffs(clkdm->clktrctrl_mask);
354
355 return v;
356}
357
358/**
359 * omap2_clkdm_sleep - force clockdomain sleep transition
360 * @clkdm: struct clockdomain *
361 *
362 * Instruct the CM to force a sleep transition on the specified
363 * clockdomain 'clkdm'. Returns -EINVAL if clk is NULL or if
364 * clockdomain does not support software-initiated sleep; 0 upon
365 * success.
366 */
367int omap2_clkdm_sleep(struct clockdomain *clkdm)
368{
369 if (!clkdm)
370 return -EINVAL;
371
372 if (!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
373 pr_debug("clockdomain: %s does not support forcing "
374 "sleep via software\n", clkdm->name);
375 return -EINVAL;
376 }
377
378 pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
379
380 if (cpu_is_omap24xx()) {
381
382 cm_set_mod_reg_bits(OMAP24XX_FORCESTATE,
383 clkdm->pwrdm->prcm_offs, PM_PWSTCTRL);
384
385 } else if (cpu_is_omap34xx()) {
386
387 u32 v = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP <<
388 __ffs(clkdm->clktrctrl_mask));
389
390 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
391 clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
392
393 } else {
394 BUG();
395 };
396
397 return 0;
398}
399
400/**
401 * omap2_clkdm_wakeup - force clockdomain wakeup transition
402 * @clkdm: struct clockdomain *
403 *
404 * Instruct the CM to force a wakeup transition on the specified
405 * clockdomain 'clkdm'. Returns -EINVAL if clkdm is NULL or if the
406 * clockdomain does not support software-controlled wakeup; 0 upon
407 * success.
408 */
409int omap2_clkdm_wakeup(struct clockdomain *clkdm)
410{
411 if (!clkdm)
412 return -EINVAL;
413
414 if (!(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
415 pr_debug("clockdomain: %s does not support forcing "
416 "wakeup via software\n", clkdm->name);
417 return -EINVAL;
418 }
419
420 pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
421
422 if (cpu_is_omap24xx()) {
423
424 cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE,
425 clkdm->pwrdm->prcm_offs, PM_PWSTCTRL);
426
427 } else if (cpu_is_omap34xx()) {
428
429 u32 v = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP <<
430 __ffs(clkdm->clktrctrl_mask));
431
432 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
433 clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
434
435 } else {
436 BUG();
437 };
438
439 return 0;
440}
441
442/**
443 * omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm
444 * @clkdm: struct clockdomain *
445 *
446 * Allow the hardware to automatically switch the clockdomain into
447 * active or idle states, as needed by downstream clocks. If the
448 * clockdomain has any downstream clocks enabled in the clock
449 * framework, wkdep/sleepdep autodependencies are added; this is so
450 * device drivers can read and write to the device. No return value.
451 */
452void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
453{
454 u32 v;
455
456 if (!clkdm)
457 return;
458
459 if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) {
460 pr_debug("clock: automatic idle transitions cannot be enabled "
461 "on clockdomain %s\n", clkdm->name);
462 return;
463 }
464
465 pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
466 clkdm->name);
467
468 if (atomic_read(&clkdm->usecount) > 0)
469 _clkdm_add_autodeps(clkdm);
470
471 if (cpu_is_omap24xx())
472 v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
473 else if (cpu_is_omap34xx())
474 v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
475 else
476 BUG();
477
478
479 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
480 v << __ffs(clkdm->clktrctrl_mask),
481 clkdm->pwrdm->prcm_offs,
482 CM_CLKSTCTRL);
483}
484
485/**
486 * omap2_clkdm_deny_idle - disable hwsup idle transitions for clkdm
487 * @clkdm: struct clockdomain *
488 *
489 * Prevent the hardware from automatically switching the clockdomain
490 * into inactive or idle states. If the clockdomain has downstream
491 * clocks enabled in the clock framework, wkdep/sleepdep
492 * autodependencies are removed. No return value.
493 */
494void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
495{
496 u32 v;
497
498 if (!clkdm)
499 return;
500
501 if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) {
502 pr_debug("clockdomain: automatic idle transitions cannot be "
503 "disabled on %s\n", clkdm->name);
504 return;
505 }
506
507 pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
508 clkdm->name);
509
510 if (cpu_is_omap24xx())
511 v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
512 else if (cpu_is_omap34xx())
513 v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
514 else
515 BUG();
516
517 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
518 v << __ffs(clkdm->clktrctrl_mask),
519 clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
520
521 if (atomic_read(&clkdm->usecount) > 0)
522 _clkdm_del_autodeps(clkdm);
523}
524
525
526/* Clockdomain-to-clock framework interface code */
527
528/**
529 * omap2_clkdm_clk_enable - add an enabled downstream clock to this clkdm
530 * @clkdm: struct clockdomain *
531 * @clk: struct clk * of the enabled downstream clock
532 *
533 * Increment the usecount of this clockdomain 'clkdm' and ensure that
534 * it is awake. Intended to be called by clk_enable() code. If the
535 * clockdomain is in software-supervised idle mode, force the
536 * clockdomain to wake. If the clockdomain is in hardware-supervised
537 * idle mode, add clkdm-pwrdm autodependencies, to ensure that devices
538 * in the clockdomain can be read from/written to by on-chip processors.
539 * Returns -EINVAL if passed null pointers; returns 0 upon success or
540 * if the clockdomain is in hwsup idle mode.
541 */
542int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
543{
544 int v;
545
546 /*
547 * XXX Rewrite this code to maintain a list of enabled
548 * downstream clocks for debugging purposes?
549 */
550
551 if (!clkdm || !clk)
552 return -EINVAL;
553
554 if (atomic_inc_return(&clkdm->usecount) > 1)
555 return 0;
556
557 /* Clockdomain now has one enabled downstream clock */
558
559 pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name,
560 clk->name);
561
562 v = omap2_clkdm_clktrctrl_read(clkdm);
563
564 if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
565 (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
566 _clkdm_add_autodeps(clkdm);
567 else
568 omap2_clkdm_wakeup(clkdm);
569
570 return 0;
571}
572
573/**
574 * omap2_clkdm_clk_disable - remove an enabled downstream clock from this clkdm
575 * @clkdm: struct clockdomain *
576 * @clk: struct clk * of the disabled downstream clock
577 *
578 * Decrement the usecount of this clockdomain 'clkdm'. Intended to be
579 * called by clk_disable() code. If the usecount goes to 0, put the
580 * clockdomain to sleep (software-supervised mode) or remove the
581 * clkdm-pwrdm autodependencies (hardware-supervised mode). Returns
582 * -EINVAL if passed null pointers; -ERANGE if the clkdm usecount
583 * underflows and debugging is enabled; or returns 0 upon success or
584 * if the clockdomain is in hwsup idle mode.
585 */
586int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
587{
588 int v;
589
590 /*
591 * XXX Rewrite this code to maintain a list of enabled
592 * downstream clocks for debugging purposes?
593 */
594
595 if (!clkdm || !clk)
596 return -EINVAL;
597
598#ifdef DEBUG
599 if (atomic_read(&clkdm->usecount) == 0) {
600 WARN_ON(1); /* underflow */
601 return -ERANGE;
602 }
603#endif
604
605 if (atomic_dec_return(&clkdm->usecount) > 0)
606 return 0;
607
608 /* All downstream clocks of this clockdomain are now disabled */
609
610 pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name,
611 clk->name);
612
613 v = omap2_clkdm_clktrctrl_read(clkdm);
614
615 if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
616 (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
617 _clkdm_del_autodeps(clkdm);
618 else
619 omap2_clkdm_sleep(clkdm);
620
621 return 0;
622}
623
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
new file mode 100644
index 000000000000..cd86dcc7b424
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -0,0 +1,305 @@
1/*
2 * OMAP2/3 clockdomains
3 *
4 * Copyright (C) 2008 Texas Instruments, Inc.
5 * Copyright (C) 2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 */
9
10#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
11#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
12
13#include <mach/clockdomain.h>
14
15/*
16 * OMAP2/3-common clockdomains
17 */
18
19/* This is an implicit clockdomain - it is never defined as such in TRM */
20static struct clockdomain wkup_clkdm = {
21 .name = "wkup_clkdm",
22 .pwrdm_name = "wkup_pwrdm",
23 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
24};
25
26/*
27 * 2420-only clockdomains
28 */
29
30#if defined(CONFIG_ARCH_OMAP2420)
31
32static struct clockdomain mpu_2420_clkdm = {
33 .name = "mpu_clkdm",
34 .pwrdm_name = "mpu_pwrdm",
35 .flags = CLKDM_CAN_HWSUP,
36 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
37 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
38};
39
40static struct clockdomain iva1_2420_clkdm = {
41 .name = "iva1_clkdm",
42 .pwrdm_name = "dsp_pwrdm",
43 .flags = CLKDM_CAN_HWSUP_SWSUP,
44 .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
45 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
46};
47
48#endif /* CONFIG_ARCH_OMAP2420 */
49
50
51/*
52 * 2430-only clockdomains
53 */
54
55#if defined(CONFIG_ARCH_OMAP2430)
56
57static struct clockdomain mpu_2430_clkdm = {
58 .name = "mpu_clkdm",
59 .pwrdm_name = "mpu_pwrdm",
60 .flags = CLKDM_CAN_HWSUP_SWSUP,
61 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
63};
64
65static struct clockdomain mdm_clkdm = {
66 .name = "mdm_clkdm",
67 .pwrdm_name = "mdm_pwrdm",
68 .flags = CLKDM_CAN_HWSUP_SWSUP,
69 .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
70 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
71};
72
73#endif /* CONFIG_ARCH_OMAP2430 */
74
75
76/*
77 * 24XX-only clockdomains
78 */
79
80#if defined(CONFIG_ARCH_OMAP24XX)
81
82static struct clockdomain dsp_clkdm = {
83 .name = "dsp_clkdm",
84 .pwrdm_name = "dsp_pwrdm",
85 .flags = CLKDM_CAN_HWSUP_SWSUP,
86 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
87 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
88};
89
90static struct clockdomain gfx_24xx_clkdm = {
91 .name = "gfx_clkdm",
92 .pwrdm_name = "gfx_pwrdm",
93 .flags = CLKDM_CAN_HWSUP_SWSUP,
94 .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
95 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
96};
97
98static struct clockdomain core_l3_24xx_clkdm = {
99 .name = "core_l3_clkdm",
100 .pwrdm_name = "core_pwrdm",
101 .flags = CLKDM_CAN_HWSUP,
102 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
103 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
104};
105
106static struct clockdomain core_l4_24xx_clkdm = {
107 .name = "core_l4_clkdm",
108 .pwrdm_name = "core_pwrdm",
109 .flags = CLKDM_CAN_HWSUP,
110 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
111 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
112};
113
114static struct clockdomain dss_24xx_clkdm = {
115 .name = "dss_clkdm",
116 .pwrdm_name = "core_pwrdm",
117 .flags = CLKDM_CAN_HWSUP,
118 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
119 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
120};
121
122#endif /* CONFIG_ARCH_OMAP24XX */
123
124
125/*
126 * 34xx clockdomains
127 */
128
129#if defined(CONFIG_ARCH_OMAP34XX)
130
131static struct clockdomain mpu_34xx_clkdm = {
132 .name = "mpu_clkdm",
133 .pwrdm_name = "mpu_pwrdm",
134 .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
135 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
137};
138
139static struct clockdomain neon_clkdm = {
140 .name = "neon_clkdm",
141 .pwrdm_name = "neon_pwrdm",
142 .flags = CLKDM_CAN_HWSUP_SWSUP,
143 .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
144 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
145};
146
147static struct clockdomain iva2_clkdm = {
148 .name = "iva2_clkdm",
149 .pwrdm_name = "iva2_pwrdm",
150 .flags = CLKDM_CAN_HWSUP_SWSUP,
151 .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
152 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
153};
154
155static struct clockdomain gfx_3430es1_clkdm = {
156 .name = "gfx_clkdm",
157 .pwrdm_name = "gfx_pwrdm",
158 .flags = CLKDM_CAN_HWSUP_SWSUP,
159 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
160 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
161};
162
163static struct clockdomain sgx_clkdm = {
164 .name = "sgx_clkdm",
165 .pwrdm_name = "sgx_pwrdm",
166 .flags = CLKDM_CAN_HWSUP_SWSUP,
167 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
168 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
169};
170
171/*
172 * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
173 * then that information was removed from the 34xx ES2+ TRM. It is
174 * unclear whether the core is still there, but the clockdomain logic
175 * is there, and must be programmed to an appropriate state if the
176 * CORE clockdomain is to become inactive.
177 */
178static struct clockdomain d2d_clkdm = {
179 .name = "d2d_clkdm",
180 .pwrdm_name = "core_pwrdm",
181 .flags = CLKDM_CAN_HWSUP,
182 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
183 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
184};
185
186static struct clockdomain core_l3_34xx_clkdm = {
187 .name = "core_l3_clkdm",
188 .pwrdm_name = "core_pwrdm",
189 .flags = CLKDM_CAN_HWSUP,
190 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
191 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
192};
193
194static struct clockdomain core_l4_34xx_clkdm = {
195 .name = "core_l4_clkdm",
196 .pwrdm_name = "core_pwrdm",
197 .flags = CLKDM_CAN_HWSUP,
198 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
199 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
200};
201
202static struct clockdomain dss_34xx_clkdm = {
203 .name = "dss_clkdm",
204 .pwrdm_name = "dss_pwrdm",
205 .flags = CLKDM_CAN_HWSUP_SWSUP,
206 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
207 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
208};
209
210static struct clockdomain cam_clkdm = {
211 .name = "cam_clkdm",
212 .pwrdm_name = "cam_pwrdm",
213 .flags = CLKDM_CAN_HWSUP_SWSUP,
214 .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
216};
217
218static struct clockdomain usbhost_clkdm = {
219 .name = "usbhost_clkdm",
220 .pwrdm_name = "usbhost_pwrdm",
221 .flags = CLKDM_CAN_HWSUP_SWSUP,
222 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
223 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
224};
225
226static struct clockdomain per_clkdm = {
227 .name = "per_clkdm",
228 .pwrdm_name = "per_pwrdm",
229 .flags = CLKDM_CAN_HWSUP_SWSUP,
230 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
231 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
232};
233
234static struct clockdomain emu_clkdm = {
235 .name = "emu_clkdm",
236 .pwrdm_name = "emu_pwrdm",
237 .flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP,
238 .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
239 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
240};
241
242#endif /* CONFIG_ARCH_OMAP34XX */
243
244/*
245 * Clockdomain-powerdomain hwsup dependencies (34XX only)
246 */
247
248static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
249 {
250 .pwrdm_name = "mpu_pwrdm",
251 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
252 },
253 {
254 .pwrdm_name = "iva2_pwrdm",
255 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
256 },
257 { NULL }
258};
259
260/*
261 *
262 */
263
264static struct clockdomain *clockdomains_omap[] = {
265
266 &wkup_clkdm,
267
268#ifdef CONFIG_ARCH_OMAP2420
269 &mpu_2420_clkdm,
270 &iva1_2420_clkdm,
271#endif
272
273#ifdef CONFIG_ARCH_OMAP2430
274 &mpu_2430_clkdm,
275 &mdm_clkdm,
276#endif
277
278#ifdef CONFIG_ARCH_OMAP24XX
279 &dsp_clkdm,
280 &gfx_24xx_clkdm,
281 &core_l3_24xx_clkdm,
282 &core_l4_24xx_clkdm,
283 &dss_24xx_clkdm,
284#endif
285
286#ifdef CONFIG_ARCH_OMAP34XX
287 &mpu_34xx_clkdm,
288 &neon_clkdm,
289 &iva2_clkdm,
290 &gfx_3430es1_clkdm,
291 &sgx_clkdm,
292 &d2d_clkdm,
293 &core_l3_34xx_clkdm,
294 &core_l4_34xx_clkdm,
295 &dss_34xx_clkdm,
296 &cam_clkdm,
297 &usbhost_clkdm,
298 &per_clkdm,
299 &emu_clkdm,
300#endif
301
302 NULL,
303};
304
305#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 20ac38100678..1098ecfab861 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -63,7 +63,8 @@
63#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) 63#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
64 64
65/* CM_CLKSTCTRL_MPU */ 65/* CM_CLKSTCTRL_MPU */
66#define OMAP24XX_AUTOSTATE_MPU (1 << 0) 66#define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
67#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
67 68
68/* CM_FCLKEN1_CORE specific bits*/ 69/* CM_FCLKEN1_CORE specific bits*/
69#define OMAP24XX_EN_TV_SHIFT 2 70#define OMAP24XX_EN_TV_SHIFT 2
@@ -238,9 +239,12 @@
238#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) 239#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
239 240
240/* CM_CLKSTCTRL_CORE */ 241/* CM_CLKSTCTRL_CORE */
241#define OMAP24XX_AUTOSTATE_DSS (1 << 2) 242#define OMAP24XX_AUTOSTATE_DSS_SHIFT 2
242#define OMAP24XX_AUTOSTATE_L4 (1 << 1) 243#define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
243#define OMAP24XX_AUTOSTATE_L3 (1 << 0) 244#define OMAP24XX_AUTOSTATE_L4_SHIFT 1
245#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
246#define OMAP24XX_AUTOSTATE_L3_SHIFT 0
247#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
244 248
245/* CM_FCLKEN_GFX */ 249/* CM_FCLKEN_GFX */
246#define OMAP24XX_EN_3D_SHIFT 2 250#define OMAP24XX_EN_3D_SHIFT 2
@@ -255,7 +259,8 @@
255/* CM_CLKSEL_GFX specific bits */ 259/* CM_CLKSEL_GFX specific bits */
256 260
257/* CM_CLKSTCTRL_GFX */ 261/* CM_CLKSTCTRL_GFX */
258#define OMAP24XX_AUTOSTATE_GFX (1 << 0) 262#define OMAP24XX_AUTOSTATE_GFX_SHIFT 0
263#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
259 264
260/* CM_FCLKEN_WKUP specific bits */ 265/* CM_FCLKEN_WKUP specific bits */
261 266
@@ -367,8 +372,10 @@
367#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) 372#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
368 373
369/* CM_CLKSTCTRL_DSP */ 374/* CM_CLKSTCTRL_DSP */
370#define OMAP2420_AUTOSTATE_IVA (1 << 8) 375#define OMAP2420_AUTOSTATE_IVA_SHIFT 8
371#define OMAP24XX_AUTOSTATE_DSP (1 << 0) 376#define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
377#define OMAP24XX_AUTOSTATE_DSP_SHIFT 0
378#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
372 379
373/* CM_FCLKEN_MDM */ 380/* CM_FCLKEN_MDM */
374/* 2430 only */ 381/* 2430 only */
@@ -396,6 +403,7 @@
396 403
397/* CM_CLKSTCTRL_MDM */ 404/* CM_CLKSTCTRL_MDM */
398/* 2430 only */ 405/* 2430 only */
399#define OMAP2430_AUTOSTATE_MDM (1 << 0) 406#define OMAP2430_AUTOSTATE_MDM_SHIFT 0
407#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
400 408
401#endif 409#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index ee4c0ca1a708..219f5c8d9659 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -96,7 +96,8 @@
96#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) 96#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
97 97
98/* CM_CLKSTST_IVA2 */ 98/* CM_CLKSTST_IVA2 */
99#define OMAP3430_CLKACTIVITY_IVA2 (1 << 0) 99#define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0
100#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
100 101
101/* CM_REVISION specific bits */ 102/* CM_REVISION specific bits */
102 103
@@ -140,7 +141,8 @@
140#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) 141#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
141 142
142/* CM_CLKSTST_MPU */ 143/* CM_CLKSTST_MPU */
143#define OMAP3430_CLKACTIVITY_MPU (1 << 0) 144#define OMAP3430_CLKACTIVITY_MPU_SHIFT 0
145#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)
144 146
145/* CM_FCLKEN1_CORE specific bits */ 147/* CM_FCLKEN1_CORE specific bits */
146 148
@@ -300,9 +302,12 @@
300#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) 302#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
301 303
302/* CM_CLKSTST_CORE */ 304/* CM_CLKSTST_CORE */
303#define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2) 305#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2
304#define OMAP3430_CLKACTIVITY_L4 (1 << 1) 306#define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2)
305#define OMAP3430_CLKACTIVITY_L3 (1 << 0) 307#define OMAP3430_CLKACTIVITY_L4_SHIFT 1
308#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1)
309#define OMAP3430_CLKACTIVITY_L3_SHIFT 0
310#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)
306 311
307/* CM_FCLKEN_GFX */ 312/* CM_FCLKEN_GFX */
308#define OMAP3430ES1_EN_3D (1 << 2) 313#define OMAP3430ES1_EN_3D (1 << 2)
@@ -323,7 +328,8 @@
323#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) 328#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
324 329
325/* CM_CLKSTST_GFX */ 330/* CM_CLKSTST_GFX */
326#define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0) 331#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0
332#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)
327 333
328/* CM_FCLKEN_SGX */ 334/* CM_FCLKEN_SGX */
329#define OMAP3430ES2_EN_SGX_SHIFT 1 335#define OMAP3430ES2_EN_SGX_SHIFT 1
@@ -333,6 +339,14 @@
333#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 339#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
334#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) 340#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
335 341
342/* CM_CLKSTCTRL_SGX */
343#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0
344#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
345
346/* CM_CLKSTST_SGX */
347#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0
348#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0)
349
336/* CM_FCLKEN_WKUP specific bits */ 350/* CM_FCLKEN_WKUP specific bits */
337#define OMAP3430ES2_EN_USIMOCP_SHIFT 9 351#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
338 352
@@ -498,7 +512,8 @@
498#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) 512#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
499 513
500/* CM_CLKSTST_DSS */ 514/* CM_CLKSTST_DSS */
501#define OMAP3430_CLKACTIVITY_DSS (1 << 0) 515#define OMAP3430_CLKACTIVITY_DSS_SHIFT 0
516#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)
502 517
503/* CM_FCLKEN_CAM specific bits */ 518/* CM_FCLKEN_CAM specific bits */
504 519
@@ -522,7 +537,8 @@
522#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) 537#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
523 538
524/* CM_CLKSTST_CAM */ 539/* CM_CLKSTST_CAM */
525#define OMAP3430_CLKACTIVITY_CAM (1 << 0) 540#define OMAP3430_CLKACTIVITY_CAM_SHIFT 0
541#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0)
526 542
527/* CM_FCLKEN_PER specific bits */ 543/* CM_FCLKEN_PER specific bits */
528 544
@@ -598,7 +614,8 @@
598#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) 614#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
599 615
600/* CM_CLKSTST_PER */ 616/* CM_CLKSTST_PER */
601#define OMAP3430_CLKACTIVITY_PER (1 << 0) 617#define OMAP3430_CLKACTIVITY_PER_SHIFT 0
618#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0)
602 619
603/* CM_CLKSEL1_EMU */ 620/* CM_CLKSEL1_EMU */
604#define OMAP3430_DIV_DPLL4_SHIFT 24 621#define OMAP3430_DIV_DPLL4_SHIFT 24
@@ -623,7 +640,8 @@
623#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) 640#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
624 641
625/* CM_CLKSTST_EMU */ 642/* CM_CLKSTST_EMU */
626#define OMAP3430_CLKACTIVITY_EMU (1 << 0) 643#define OMAP3430_CLKACTIVITY_EMU_SHIFT 0
644#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0)
627 645
628/* CM_CLKSEL2_EMU specific bits */ 646/* CM_CLKSEL2_EMU specific bits */
629#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 647#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
@@ -673,6 +691,8 @@
673#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 691#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
674#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) 692#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
675 693
676 694/* CM_CLKSTST_USBHOST */
695#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0
696#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0)
677 697
678#endif 698#endif
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 87a44c715aa4..65fdf78c91e1 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -18,7 +18,7 @@
18 18
19#ifndef __ASSEMBLER__ 19#ifndef __ASSEMBLER__
20#define OMAP_CM_REGADDR(module, reg) \ 20#define OMAP_CM_REGADDR(module, reg) \
21 (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg)) 21 IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg))
22#else 22#else
23#define OMAP2420_CM_REGADDR(module, reg) \ 23#define OMAP2420_CM_REGADDR(module, reg) \
24 IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) 24 IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 2ee954a0bc7c..90af2ac469aa 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -23,50 +23,7 @@
23#include <mach/board.h> 23#include <mach/board.h>
24#include <mach/mux.h> 24#include <mach/mux.h>
25#include <mach/gpio.h> 25#include <mach/gpio.h>
26 26#include <mach/eac.h>
27#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
28
29#define OMAP2_I2C_BASE2 0x48072000
30#define OMAP2_I2C_INT2 57
31
32static struct resource i2c_resources2[] = {
33 {
34 .start = OMAP2_I2C_BASE2,
35 .end = OMAP2_I2C_BASE2 + 0x3f,
36 .flags = IORESOURCE_MEM,
37 },
38 {
39 .start = OMAP2_I2C_INT2,
40 .flags = IORESOURCE_IRQ,
41 },
42};
43
44static struct platform_device omap_i2c_device2 = {
45 .name = "i2c_omap",
46 .id = 2,
47 .num_resources = ARRAY_SIZE(i2c_resources2),
48 .resource = i2c_resources2,
49};
50
51/* See also arch/arm/plat-omap/devices.c for first I2C on 24xx */
52static void omap_init_i2c(void)
53{
54 /* REVISIT: Second I2C not in use on H4? */
55 if (machine_is_omap_h4())
56 return;
57
58 if (!cpu_is_omap2430()) {
59 omap_cfg_reg(J15_24XX_I2C2_SCL);
60 omap_cfg_reg(H19_24XX_I2C2_SDA);
61 }
62 (void) platform_device_register(&omap_i2c_device2);
63}
64
65#else
66
67static void omap_init_i2c(void) {}
68
69#endif
70 27
71#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) 28#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
72#define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE) 29#define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE)
@@ -104,7 +61,9 @@ static inline void omap_init_mbox(void) { }
104 61
105#if defined(CONFIG_OMAP_STI) 62#if defined(CONFIG_OMAP_STI)
106 63
107#define OMAP2_STI_BASE IO_ADDRESS(0x48068000) 64#if defined(CONFIG_ARCH_OMAP2)
65
66#define OMAP2_STI_BASE 0x48068000
108#define OMAP2_STI_CHANNEL_BASE 0x54000000 67#define OMAP2_STI_CHANNEL_BASE 0x54000000
109#define OMAP2_STI_IRQ 4 68#define OMAP2_STI_IRQ 4
110 69
@@ -124,6 +83,25 @@ static struct resource sti_resources[] = {
124 .flags = IORESOURCE_IRQ, 83 .flags = IORESOURCE_IRQ,
125 } 84 }
126}; 85};
86#elif defined(CONFIG_ARCH_OMAP3)
87
88#define OMAP3_SDTI_BASE 0x54500000
89#define OMAP3_SDTI_CHANNEL_BASE 0x54600000
90
91static struct resource sti_resources[] = {
92 {
93 .start = OMAP3_SDTI_BASE,
94 .end = OMAP3_SDTI_BASE + 0xFFF,
95 .flags = IORESOURCE_MEM,
96 },
97 {
98 .start = OMAP3_SDTI_CHANNEL_BASE,
99 .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
100 .flags = IORESOURCE_MEM,
101 }
102};
103
104#endif
127 105
128static struct platform_device sti_device = { 106static struct platform_device sti_device = {
129 .name = "sti", 107 .name = "sti",
@@ -140,12 +118,14 @@ static inline void omap_init_sti(void)
140static inline void omap_init_sti(void) {} 118static inline void omap_init_sti(void) {}
141#endif 119#endif
142 120
143#if defined(CONFIG_SPI_OMAP24XX) 121#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
144 122
145#include <mach/mcspi.h> 123#include <mach/mcspi.h>
146 124
147#define OMAP2_MCSPI1_BASE 0x48098000 125#define OMAP2_MCSPI1_BASE 0x48098000
148#define OMAP2_MCSPI2_BASE 0x4809a000 126#define OMAP2_MCSPI2_BASE 0x4809a000
127#define OMAP2_MCSPI3_BASE 0x480b8000
128#define OMAP2_MCSPI4_BASE 0x480ba000
149 129
150static struct omap2_mcspi_platform_config omap2_mcspi1_config = { 130static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
151 .num_cs = 4, 131 .num_cs = 4,
@@ -159,7 +139,7 @@ static struct resource omap2_mcspi1_resources[] = {
159 }, 139 },
160}; 140};
161 141
162struct platform_device omap2_mcspi1 = { 142static struct platform_device omap2_mcspi1 = {
163 .name = "omap2_mcspi", 143 .name = "omap2_mcspi",
164 .id = 1, 144 .id = 1,
165 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources), 145 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
@@ -181,7 +161,7 @@ static struct resource omap2_mcspi2_resources[] = {
181 }, 161 },
182}; 162};
183 163
184struct platform_device omap2_mcspi2 = { 164static struct platform_device omap2_mcspi2 = {
185 .name = "omap2_mcspi", 165 .name = "omap2_mcspi",
186 .id = 2, 166 .id = 2,
187 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources), 167 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
@@ -191,16 +171,162 @@ struct platform_device omap2_mcspi2 = {
191 }, 171 },
192}; 172};
193 173
174#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
175static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
176 .num_cs = 2,
177};
178
179static struct resource omap2_mcspi3_resources[] = {
180 {
181 .start = OMAP2_MCSPI3_BASE,
182 .end = OMAP2_MCSPI3_BASE + 0xff,
183 .flags = IORESOURCE_MEM,
184 },
185};
186
187static struct platform_device omap2_mcspi3 = {
188 .name = "omap2_mcspi",
189 .id = 3,
190 .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
191 .resource = omap2_mcspi3_resources,
192 .dev = {
193 .platform_data = &omap2_mcspi3_config,
194 },
195};
196#endif
197
198#ifdef CONFIG_ARCH_OMAP3
199static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
200 .num_cs = 1,
201};
202
203static struct resource omap2_mcspi4_resources[] = {
204 {
205 .start = OMAP2_MCSPI4_BASE,
206 .end = OMAP2_MCSPI4_BASE + 0xff,
207 .flags = IORESOURCE_MEM,
208 },
209};
210
211static struct platform_device omap2_mcspi4 = {
212 .name = "omap2_mcspi",
213 .id = 4,
214 .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
215 .resource = omap2_mcspi4_resources,
216 .dev = {
217 .platform_data = &omap2_mcspi4_config,
218 },
219};
220#endif
221
194static void omap_init_mcspi(void) 222static void omap_init_mcspi(void)
195{ 223{
196 platform_device_register(&omap2_mcspi1); 224 platform_device_register(&omap2_mcspi1);
197 platform_device_register(&omap2_mcspi2); 225 platform_device_register(&omap2_mcspi2);
226#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
227 platform_device_register(&omap2_mcspi3);
228#endif
229#ifdef CONFIG_ARCH_OMAP3
230 platform_device_register(&omap2_mcspi4);
231#endif
198} 232}
199 233
200#else 234#else
201static inline void omap_init_mcspi(void) {} 235static inline void omap_init_mcspi(void) {}
202#endif 236#endif
203 237
238#ifdef CONFIG_SND_OMAP24XX_EAC
239
240#define OMAP2_EAC_BASE 0x48090000
241
242static struct resource omap2_eac_resources[] = {
243 {
244 .start = OMAP2_EAC_BASE,
245 .end = OMAP2_EAC_BASE + 0x109,
246 .flags = IORESOURCE_MEM,
247 },
248};
249
250static struct platform_device omap2_eac_device = {
251 .name = "omap24xx-eac",
252 .id = -1,
253 .num_resources = ARRAY_SIZE(omap2_eac_resources),
254 .resource = omap2_eac_resources,
255 .dev = {
256 .platform_data = NULL,
257 },
258};
259
260void omap_init_eac(struct eac_platform_data *pdata)
261{
262 omap2_eac_device.dev.platform_data = pdata;
263 platform_device_register(&omap2_eac_device);
264}
265
266#else
267void omap_init_eac(struct eac_platform_data *pdata) {}
268#endif
269
270#ifdef CONFIG_OMAP_SHA1_MD5
271static struct resource sha1_md5_resources[] = {
272 {
273 .start = OMAP24XX_SEC_SHA1MD5_BASE,
274 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
275 .flags = IORESOURCE_MEM,
276 },
277 {
278 .start = INT_24XX_SHA1MD5,
279 .flags = IORESOURCE_IRQ,
280 }
281};
282
283static struct platform_device sha1_md5_device = {
284 .name = "OMAP SHA1/MD5",
285 .id = -1,
286 .num_resources = ARRAY_SIZE(sha1_md5_resources),
287 .resource = sha1_md5_resources,
288};
289
290static void omap_init_sha1_md5(void)
291{
292 platform_device_register(&sha1_md5_device);
293}
294#else
295static inline void omap_init_sha1_md5(void) { }
296#endif
297
298#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
299#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
300#define OMAP_HDQ_BASE 0x480B2000
301#endif
302static struct resource omap_hdq_resources[] = {
303 {
304 .start = OMAP_HDQ_BASE,
305 .end = OMAP_HDQ_BASE + 0x1C,
306 .flags = IORESOURCE_MEM,
307 },
308 {
309 .start = INT_24XX_HDQ_IRQ,
310 .flags = IORESOURCE_IRQ,
311 },
312};
313static struct platform_device omap_hdq_dev = {
314 .name = "omap_hdq",
315 .id = 0,
316 .dev = {
317 .platform_data = NULL,
318 },
319 .num_resources = ARRAY_SIZE(omap_hdq_resources),
320 .resource = omap_hdq_resources,
321};
322static inline void omap_hdq_init(void)
323{
324 (void) platform_device_register(&omap_hdq_dev);
325}
326#else
327static inline void omap_hdq_init(void) {}
328#endif
329
204/*-------------------------------------------------------------------------*/ 330/*-------------------------------------------------------------------------*/
205 331
206static int __init omap2_init_devices(void) 332static int __init omap2_init_devices(void)
@@ -208,10 +334,11 @@ static int __init omap2_init_devices(void)
208 /* please keep these calls, and their implementations above, 334 /* please keep these calls, and their implementations above,
209 * in alphabetical order so they're easier to sort through. 335 * in alphabetical order so they're easier to sort through.
210 */ 336 */
211 omap_init_i2c();
212 omap_init_mbox(); 337 omap_init_mbox();
213 omap_init_mcspi(); 338 omap_init_mcspi();
339 omap_hdq_init();
214 omap_init_sti(); 340 omap_init_sti();
341 omap_init_sha1_md5();
215 342
216 return 0; 343 return 0;
217} 344}
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index af1081a0b27c..763bdbeaf681 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -9,6 +9,8 @@
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12#undef DEBUG
13
12#include <linux/kernel.h> 14#include <linux/kernel.h>
13#include <linux/init.h> 15#include <linux/init.h>
14#include <linux/err.h> 16#include <linux/err.h>
@@ -16,20 +18,14 @@
16#include <linux/ioport.h> 18#include <linux/ioport.h>
17#include <linux/spinlock.h> 19#include <linux/spinlock.h>
18#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/module.h>
19 22
20#include <asm/mach-types.h> 23#include <asm/mach-types.h>
21#include <mach/gpmc.h> 24#include <mach/gpmc.h>
22 25
23#undef DEBUG 26#include <mach/sdrc.h>
24
25#ifdef CONFIG_ARCH_OMAP2420
26#define GPMC_BASE 0x6800a000
27#endif
28
29#ifdef CONFIG_ARCH_OMAP2430
30#define GPMC_BASE 0x6E000000
31#endif
32 27
28/* GPMC register offsets */
33#define GPMC_REVISION 0x00 29#define GPMC_REVISION 0x00
34#define GPMC_SYSCONFIG 0x10 30#define GPMC_SYSCONFIG 0x10
35#define GPMC_SYSSTATUS 0x14 31#define GPMC_SYSSTATUS 0x14
@@ -51,7 +47,6 @@
51#define GPMC_CS0 0x60 47#define GPMC_CS0 0x60
52#define GPMC_CS_SIZE 0x30 48#define GPMC_CS_SIZE 0x30
53 49
54#define GPMC_CS_NUM 8
55#define GPMC_MEM_START 0x00000000 50#define GPMC_MEM_START 0x00000000
56#define GPMC_MEM_END 0x3FFFFFFF 51#define GPMC_MEM_END 0x3FFFFFFF
57#define BOOT_ROM_SPACE 0x100000 /* 1MB */ 52#define BOOT_ROM_SPACE 0x100000 /* 1MB */
@@ -64,12 +59,9 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM];
64static DEFINE_SPINLOCK(gpmc_mem_lock); 59static DEFINE_SPINLOCK(gpmc_mem_lock);
65static unsigned gpmc_cs_map; 60static unsigned gpmc_cs_map;
66 61
67static void __iomem *gpmc_base = 62static void __iomem *gpmc_base;
68 (void __iomem *) IO_ADDRESS(GPMC_BASE);
69static void __iomem *gpmc_cs_base =
70 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
71 63
72static struct clk *gpmc_fck; 64static struct clk *gpmc_l3_clk;
73 65
74static void gpmc_write_reg(int idx, u32 val) 66static void gpmc_write_reg(int idx, u32 val)
75{ 67{
@@ -85,19 +77,32 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
85{ 77{
86 void __iomem *reg_addr; 78 void __iomem *reg_addr;
87 79
88 reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx; 80 reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
89 __raw_writel(val, reg_addr); 81 __raw_writel(val, reg_addr);
90} 82}
91 83
92u32 gpmc_cs_read_reg(int cs, int idx) 84u32 gpmc_cs_read_reg(int cs, int idx)
93{ 85{
94 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx); 86 void __iomem *reg_addr;
87
88 reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
89 return __raw_readl(reg_addr);
95} 90}
96 91
92/* TODO: Add support for gpmc_fck to clock framework and use it */
97unsigned long gpmc_get_fclk_period(void) 93unsigned long gpmc_get_fclk_period(void)
98{ 94{
99 /* In picoseconds */ 95 unsigned long rate = clk_get_rate(gpmc_l3_clk);
100 return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000); 96
97 if (rate == 0) {
98 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
99 return 0;
100 }
101
102 rate /= 1000;
103 rate = 1000000000 / rate; /* In picoseconds */
104
105 return rate;
101} 106}
102 107
103unsigned int gpmc_ns_to_ticks(unsigned int time_ns) 108unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
@@ -110,6 +115,11 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
110 return (time_ns * 1000 + tick_ps - 1) / tick_ps; 115 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
111} 116}
112 117
118unsigned int gpmc_ticks_to_ns(unsigned int ticks)
119{
120 return ticks * gpmc_get_fclk_period() / 1000;
121}
122
113unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns) 123unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
114{ 124{
115 unsigned long ticks = gpmc_ns_to_ticks(time_ns); 125 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
@@ -210,6 +220,11 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
210 220
211 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); 221 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
212 222
223 if (cpu_is_omap34xx()) {
224 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
225 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
226 }
227
213 /* caller is expected to have initialized CONFIG1 to cover 228 /* caller is expected to have initialized CONFIG1 to cover
214 * at least sync vs async 229 * at least sync vs async
215 */ 230 */
@@ -350,6 +365,7 @@ out:
350 spin_unlock(&gpmc_mem_lock); 365 spin_unlock(&gpmc_mem_lock);
351 return r; 366 return r;
352} 367}
368EXPORT_SYMBOL(gpmc_cs_request);
353 369
354void gpmc_cs_free(int cs) 370void gpmc_cs_free(int cs)
355{ 371{
@@ -365,8 +381,9 @@ void gpmc_cs_free(int cs)
365 gpmc_cs_set_reserved(cs, 0); 381 gpmc_cs_set_reserved(cs, 0);
366 spin_unlock(&gpmc_mem_lock); 382 spin_unlock(&gpmc_mem_lock);
367} 383}
384EXPORT_SYMBOL(gpmc_cs_free);
368 385
369void __init gpmc_mem_init(void) 386static void __init gpmc_mem_init(void)
370{ 387{
371 int cs; 388 int cs;
372 unsigned long boot_rom_space = 0; 389 unsigned long boot_rom_space = 0;
@@ -396,12 +413,33 @@ void __init gpmc_mem_init(void)
396void __init gpmc_init(void) 413void __init gpmc_init(void)
397{ 414{
398 u32 l; 415 u32 l;
416 char *ck;
417
418 if (cpu_is_omap24xx()) {
419 ck = "core_l3_ck";
420 if (cpu_is_omap2420())
421 l = OMAP2420_GPMC_BASE;
422 else
423 l = OMAP34XX_GPMC_BASE;
424 } else if (cpu_is_omap34xx()) {
425 ck = "gpmc_fck";
426 l = OMAP34XX_GPMC_BASE;
427 }
399 428
400 gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ 429 gpmc_l3_clk = clk_get(NULL, ck);
401 if (IS_ERR(gpmc_fck)) 430 if (IS_ERR(gpmc_l3_clk)) {
402 WARN_ON(1); 431 printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
403 else 432 return -ENODEV;
404 clk_enable(gpmc_fck); 433 }
434
435 gpmc_base = ioremap(l, SZ_4K);
436 if (!gpmc_base) {
437 clk_put(gpmc_l3_clk);
438 printk(KERN_ERR "Could not get GPMC register memory\n");
439 return -ENOMEM;
440 }
441
442 BUG_ON(IS_ERR(gpmc_l3_clk));
405 443
406 l = gpmc_read_reg(GPMC_REVISION); 444 l = gpmc_read_reg(GPMC_REVISION);
407 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); 445 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 209177c7f22f..bf45ff39a7b5 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -18,24 +18,15 @@
18 18
19#include <asm/cputype.h> 19#include <asm/cputype.h>
20 20
21#include <mach/common.h>
21#include <mach/control.h> 22#include <mach/control.h>
22#include <mach/cpu.h> 23#include <mach/cpu.h>
23 24
24#if defined(CONFIG_ARCH_OMAP2420) 25static u32 class;
25#define TAP_BASE io_p2v(0x48014000) 26static void __iomem *tap_base;
26#elif defined(CONFIG_ARCH_OMAP2430) 27static u16 tap_prod_id;
27#define TAP_BASE io_p2v(0x4900A000)
28#elif defined(CONFIG_ARCH_OMAP34XX)
29#define TAP_BASE io_p2v(0x4830A000)
30#endif
31 28
32#define OMAP_TAP_IDCODE 0x0204 29#define OMAP_TAP_IDCODE 0x0204
33#if defined(CONFIG_ARCH_OMAP34XX)
34#define OMAP_TAP_PROD_ID 0x0210
35#else
36#define OMAP_TAP_PROD_ID 0x0208
37#endif
38
39#define OMAP_TAP_DIE_ID_0 0x0218 30#define OMAP_TAP_DIE_ID_0 0x0218
40#define OMAP_TAP_DIE_ID_1 0x021C 31#define OMAP_TAP_DIE_ID_1 0x021C
41#define OMAP_TAP_DIE_ID_2 0x0220 32#define OMAP_TAP_DIE_ID_2 0x0220
@@ -94,18 +85,24 @@ static u32 __init read_tap_reg(int reg)
94 * it means its Cortex r0p0 which is 3430 ES1 85 * it means its Cortex r0p0 which is 3430 ES1
95 */ 86 */
96 if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) { 87 if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
88
89 if (reg == tap_prod_id) {
90 regval = 0x000F00F0;
91 goto out;
92 }
93
97 switch (reg) { 94 switch (reg) {
98 case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break; 95 case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break;
99 /* Making DevType as 0xF in ES1 to differ from ES2 */ 96 /* Making DevType as 0xF in ES1 to differ from ES2 */
100 case OMAP_TAP_PROD_ID : regval = 0x000F00F0; break;
101 case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break; 97 case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
102 case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break; 98 case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
103 case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break; 99 case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
104 case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break; 100 case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
105 } 101 }
106 } else 102 } else
107 regval = __raw_readl(TAP_BASE + reg); 103 regval = __raw_readl(tap_base + reg);
108 104
105out:
109 return regval; 106 return regval;
110 107
111} 108}
@@ -204,7 +201,7 @@ void __init omap2_check_revision(void)
204 u8 rev; 201 u8 rev;
205 202
206 idcode = read_tap_reg(OMAP_TAP_IDCODE); 203 idcode = read_tap_reg(OMAP_TAP_IDCODE);
207 prod_id = read_tap_reg(OMAP_TAP_PROD_ID); 204 prod_id = read_tap_reg(tap_prod_id);
208 hawkeye = (idcode >> 12) & 0xffff; 205 hawkeye = (idcode >> 12) & 0xffff;
209 rev = (idcode >> 28) & 0x0f; 206 rev = (idcode >> 28) & 0x0f;
210 dev_type = (prod_id >> 16) & 0x0f; 207 dev_type = (prod_id >> 16) & 0x0f;
@@ -269,3 +266,13 @@ void __init omap2_check_revision(void)
269 266
270} 267}
271 268
269void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
270{
271 class = omap2_globals->class;
272 tap_base = omap2_globals->tap;
273
274 if (class == 0x3430)
275 tap_prod_id = 0x0210;
276 else
277 tap_prod_id = 0x0208;
278}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 7c3d6289c05f..5ea64f926ed5 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -4,8 +4,11 @@
4 * OMAP2 I/O mapping code 4 * OMAP2 I/O mapping code
5 * 5 *
6 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Juha Yrjölä <juha.yrjola@nokia.com> 7 * Copyright (C) 2007 Texas Instruments
8 * Updated map desc to add 2430 support : <x0khasim@ti.com> 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
9 * 12 *
10 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 14 * it under the terms of the GNU General Public License version 2 as
@@ -23,19 +26,26 @@
23 26
24#include <mach/mux.h> 27#include <mach/mux.h>
25#include <mach/omapfb.h> 28#include <mach/omapfb.h>
29#include <mach/sram.h>
30
31#include "memory.h"
32
33#include "clock.h"
34
35#include <mach/powerdomain.h>
36
37#include "powerdomains.h"
26 38
27extern void omap_sram_init(void); 39#include <mach/clockdomain.h>
28extern int omap2_clk_init(void); 40#include "clockdomains.h"
29extern void omap2_check_revision(void);
30extern void omap2_init_memory(void);
31extern void gpmc_init(void);
32extern void omapfb_reserve_sdram(void);
33 41
34/* 42/*
35 * The machine specific code may provide the extra mapping besides the 43 * The machine specific code may provide the extra mapping besides the
36 * default mapping provided here. 44 * default mapping provided here.
37 */ 45 */
38static struct map_desc omap2_io_desc[] __initdata = { 46
47#ifdef CONFIG_ARCH_OMAP24XX
48static struct map_desc omap24xx_io_desc[] __initdata = {
39 { 49 {
40 .virtual = L3_24XX_VIRT, 50 .virtual = L3_24XX_VIRT,
41 .pfn = __phys_to_pfn(L3_24XX_PHYS), 51 .pfn = __phys_to_pfn(L3_24XX_PHYS),
@@ -43,12 +53,39 @@ static struct map_desc omap2_io_desc[] __initdata = {
43 .type = MT_DEVICE 53 .type = MT_DEVICE
44 }, 54 },
45 { 55 {
46 .virtual = L4_24XX_VIRT, 56 .virtual = L4_24XX_VIRT,
47 .pfn = __phys_to_pfn(L4_24XX_PHYS), 57 .pfn = __phys_to_pfn(L4_24XX_PHYS),
48 .length = L4_24XX_SIZE, 58 .length = L4_24XX_SIZE,
49 .type = MT_DEVICE 59 .type = MT_DEVICE
50 }, 60 },
61};
62
63#ifdef CONFIG_ARCH_OMAP2420
64static struct map_desc omap242x_io_desc[] __initdata = {
65 {
66 .virtual = DSP_MEM_24XX_VIRT,
67 .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS),
68 .length = DSP_MEM_24XX_SIZE,
69 .type = MT_DEVICE
70 },
71 {
72 .virtual = DSP_IPI_24XX_VIRT,
73 .pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS),
74 .length = DSP_IPI_24XX_SIZE,
75 .type = MT_DEVICE
76 },
77 {
78 .virtual = DSP_MMU_24XX_VIRT,
79 .pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS),
80 .length = DSP_MMU_24XX_SIZE,
81 .type = MT_DEVICE
82 },
83};
84
85#endif
86
51#ifdef CONFIG_ARCH_OMAP2430 87#ifdef CONFIG_ARCH_OMAP2430
88static struct map_desc omap243x_io_desc[] __initdata = {
52 { 89 {
53 .virtual = L4_WK_243X_VIRT, 90 .virtual = L4_WK_243X_VIRT,
54 .pfn = __phys_to_pfn(L4_WK_243X_PHYS), 91 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
@@ -61,30 +98,90 @@ static struct map_desc omap2_io_desc[] __initdata = {
61 .length = OMAP243X_GPMC_SIZE, 98 .length = OMAP243X_GPMC_SIZE,
62 .type = MT_DEVICE 99 .type = MT_DEVICE
63 }, 100 },
101 {
102 .virtual = OMAP243X_SDRC_VIRT,
103 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
104 .length = OMAP243X_SDRC_SIZE,
105 .type = MT_DEVICE
106 },
107 {
108 .virtual = OMAP243X_SMS_VIRT,
109 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
110 .length = OMAP243X_SMS_SIZE,
111 .type = MT_DEVICE
112 },
113};
114#endif
64#endif 115#endif
116
117#ifdef CONFIG_ARCH_OMAP34XX
118static struct map_desc omap34xx_io_desc[] __initdata = {
65 { 119 {
66 .virtual = DSP_MEM_24XX_VIRT, 120 .virtual = L3_34XX_VIRT,
67 .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS), 121 .pfn = __phys_to_pfn(L3_34XX_PHYS),
68 .length = DSP_MEM_24XX_SIZE, 122 .length = L3_34XX_SIZE,
69 .type = MT_DEVICE 123 .type = MT_DEVICE
70 }, 124 },
71 { 125 {
72 .virtual = DSP_IPI_24XX_VIRT, 126 .virtual = L4_34XX_VIRT,
73 .pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS), 127 .pfn = __phys_to_pfn(L4_34XX_PHYS),
74 .length = DSP_IPI_24XX_SIZE, 128 .length = L4_34XX_SIZE,
75 .type = MT_DEVICE 129 .type = MT_DEVICE
76 }, 130 },
77 { 131 {
78 .virtual = DSP_MMU_24XX_VIRT, 132 .virtual = L4_WK_34XX_VIRT,
79 .pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS), 133 .pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
80 .length = DSP_MMU_24XX_SIZE, 134 .length = L4_WK_34XX_SIZE,
135 .type = MT_DEVICE
136 },
137 {
138 .virtual = OMAP34XX_GPMC_VIRT,
139 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
140 .length = OMAP34XX_GPMC_SIZE,
81 .type = MT_DEVICE 141 .type = MT_DEVICE
82 } 142 },
143 {
144 .virtual = OMAP343X_SMS_VIRT,
145 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
146 .length = OMAP343X_SMS_SIZE,
147 .type = MT_DEVICE
148 },
149 {
150 .virtual = OMAP343X_SDRC_VIRT,
151 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
152 .length = OMAP343X_SDRC_SIZE,
153 .type = MT_DEVICE
154 },
155 {
156 .virtual = L4_PER_34XX_VIRT,
157 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
158 .length = L4_PER_34XX_SIZE,
159 .type = MT_DEVICE
160 },
161 {
162 .virtual = L4_EMU_34XX_VIRT,
163 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
164 .length = L4_EMU_34XX_SIZE,
165 .type = MT_DEVICE
166 },
83}; 167};
168#endif
84 169
85void __init omap2_map_common_io(void) 170void __init omap2_map_common_io(void)
86{ 171{
87 iotable_init(omap2_io_desc, ARRAY_SIZE(omap2_io_desc)); 172#if defined(CONFIG_ARCH_OMAP2420)
173 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
174 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
175#endif
176
177#if defined(CONFIG_ARCH_OMAP2430)
178 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
179 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
180#endif
181
182#if defined(CONFIG_ARCH_OMAP34XX)
183 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
184#endif
88 185
89 /* Normally devicemaps_init() would flush caches and tlb after 186 /* Normally devicemaps_init() would flush caches and tlb after
90 * mdesc->map_io(), but we must also do it here because of the CPU 187 * mdesc->map_io(), but we must also do it here because of the CPU
@@ -101,12 +198,9 @@ void __init omap2_map_common_io(void)
101void __init omap2_init_common_hw(void) 198void __init omap2_init_common_hw(void)
102{ 199{
103 omap2_mux_init(); 200 omap2_mux_init();
201 pwrdm_init(powerdomains_omap);
202 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
104 omap2_clk_init(); 203 omap2_clk_init();
105/*
106 * Need to Fix this for 2430
107 */
108#ifndef CONFIG_ARCH_OMAP2430
109 omap2_init_memory(); 204 omap2_init_memory();
110#endif
111 gpmc_init(); 205 gpmc_init();
112} 206}
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 196a9565a8dc..d354e0fe4477 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -16,14 +16,20 @@
16#include <linux/io.h> 16#include <linux/io.h>
17#include <mach/hardware.h> 17#include <mach/hardware.h>
18#include <asm/mach/irq.h> 18#include <asm/mach/irq.h>
19#include <asm/irq.h>
20 19
21#define INTC_REVISION 0x0000 20
22#define INTC_SYSCONFIG 0x0010 21/* selected INTC register offsets */
23#define INTC_SYSSTATUS 0x0014 22
24#define INTC_CONTROL 0x0048 23#define INTC_REVISION 0x0000
25#define INTC_MIR_CLEAR0 0x0088 24#define INTC_SYSCONFIG 0x0010
26#define INTC_MIR_SET0 0x008c 25#define INTC_SYSSTATUS 0x0014
26#define INTC_CONTROL 0x0048
27#define INTC_MIR_CLEAR0 0x0088
28#define INTC_MIR_SET0 0x008c
29#define INTC_PENDING_IRQ0 0x0098
30
31/* Number of IRQ state bits in each MIR register */
32#define IRQ_BITS_PER_REG 32
27 33
28/* 34/*
29 * OMAP2 has a number of different interrupt controllers, each interrupt 35 * OMAP2 has a number of different interrupt controllers, each interrupt
@@ -32,48 +38,50 @@
32 * for each bank.. when in doubt, consult the TRM. 38 * for each bank.. when in doubt, consult the TRM.
33 */ 39 */
34static struct omap_irq_bank { 40static struct omap_irq_bank {
35 unsigned long base_reg; 41 void __iomem *base_reg;
36 unsigned int nr_irqs; 42 unsigned int nr_irqs;
37} __attribute__ ((aligned(4))) irq_banks[] = { 43} __attribute__ ((aligned(4))) irq_banks[] = {
38 { 44 {
39 /* MPU INTC */ 45 /* MPU INTC */
40 .base_reg = IO_ADDRESS(OMAP24XX_IC_BASE), 46 .base_reg = 0,
41 .nr_irqs = 96, 47 .nr_irqs = 96,
42 }, { 48 },
43 /* XXX: DSP INTC */
44 }
45}; 49};
46 50
51/* INTC bank register get/set */
52
53static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
54{
55 __raw_writel(val, bank->base_reg + reg);
56}
57
58static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
59{
60 return __raw_readl(bank->base_reg + reg);
61}
62
47/* XXX: FIQ and additional INTC support (only MPU at the moment) */ 63/* XXX: FIQ and additional INTC support (only MPU at the moment) */
48static void omap_ack_irq(unsigned int irq) 64static void omap_ack_irq(unsigned int irq)
49{ 65{
50 __raw_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL); 66 intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
51} 67}
52 68
53static void omap_mask_irq(unsigned int irq) 69static void omap_mask_irq(unsigned int irq)
54{ 70{
55 int offset = (irq >> 5) << 5; 71 int offset = irq & (~(IRQ_BITS_PER_REG - 1));
56 72
57 if (irq >= 64) { 73 irq &= (IRQ_BITS_PER_REG - 1);
58 irq %= 64;
59 } else if (irq >= 32) {
60 irq %= 32;
61 }
62 74
63 __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset); 75 intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
64} 76}
65 77
66static void omap_unmask_irq(unsigned int irq) 78static void omap_unmask_irq(unsigned int irq)
67{ 79{
68 int offset = (irq >> 5) << 5; 80 int offset = irq & (~(IRQ_BITS_PER_REG - 1));
69 81
70 if (irq >= 64) { 82 irq &= (IRQ_BITS_PER_REG - 1);
71 irq %= 64;
72 } else if (irq >= 32) {
73 irq %= 32;
74 }
75 83
76 __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset); 84 intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
77} 85}
78 86
79static void omap_mask_ack_irq(unsigned int irq) 87static void omap_mask_ack_irq(unsigned int irq)
@@ -93,20 +101,20 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
93{ 101{
94 unsigned long tmp; 102 unsigned long tmp;
95 103
96 tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff; 104 tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
97 printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx " 105 printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
98 "(revision %ld.%ld) with %d interrupts\n", 106 "(revision %ld.%ld) with %d interrupts\n",
99 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); 107 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
100 108
101 tmp = __raw_readl(bank->base_reg + INTC_SYSCONFIG); 109 tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
102 tmp |= 1 << 1; /* soft reset */ 110 tmp |= 1 << 1; /* soft reset */
103 __raw_writel(tmp, bank->base_reg + INTC_SYSCONFIG); 111 intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
104 112
105 while (!(__raw_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1)) 113 while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
106 /* Wait for reset to complete */; 114 /* Wait for reset to complete */;
107 115
108 /* Enable autoidle */ 116 /* Enable autoidle */
109 __raw_writel(1 << 0, bank->base_reg + INTC_SYSCONFIG); 117 intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
110} 118}
111 119
112void __init omap_init_irq(void) 120void __init omap_init_irq(void)
@@ -118,9 +126,10 @@ void __init omap_init_irq(void)
118 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { 126 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
119 struct omap_irq_bank *bank = irq_banks + i; 127 struct omap_irq_bank *bank = irq_banks + i;
120 128
121 /* XXX */ 129 if (cpu_is_omap24xx())
122 if (!bank->base_reg) 130 bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
123 continue; 131 else if (cpu_is_omap34xx())
132 bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE);
124 133
125 omap_irq_bank_init_one(bank); 134 omap_irq_bank_init_one(bank);
126 135
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index b261f1f80b5e..cae3ebe249b3 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -89,6 +89,30 @@ static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
89 .disable = omap_mcbsp_clk_disable, 89 .disable = omap_mcbsp_clk_disable,
90 }, 90 },
91 }, 91 },
92 {
93 .clk = {
94 .name = "mcbsp_clk",
95 .id = 3,
96 .enable = omap_mcbsp_clk_enable,
97 .disable = omap_mcbsp_clk_disable,
98 },
99 },
100 {
101 .clk = {
102 .name = "mcbsp_clk",
103 .id = 4,
104 .enable = omap_mcbsp_clk_enable,
105 .disable = omap_mcbsp_clk_disable,
106 },
107 },
108 {
109 .clk = {
110 .name = "mcbsp_clk",
111 .id = 5,
112 .enable = omap_mcbsp_clk_enable,
113 .disable = omap_mcbsp_clk_disable,
114 },
115 },
92}; 116};
93 117
94#define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks) 118#define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks)
@@ -117,25 +141,14 @@ static void omap2_mcbsp_request(unsigned int id)
117 omap2_mcbsp2_mux_setup(); 141 omap2_mcbsp2_mux_setup();
118} 142}
119 143
120static int omap2_mcbsp_check(unsigned int id)
121{
122 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
123 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
124 return -ENODEV;
125 }
126 return 0;
127}
128
129static struct omap_mcbsp_ops omap2_mcbsp_ops = { 144static struct omap_mcbsp_ops omap2_mcbsp_ops = {
130 .request = omap2_mcbsp_request, 145 .request = omap2_mcbsp_request,
131 .check = omap2_mcbsp_check,
132}; 146};
133 147
134#ifdef CONFIG_ARCH_OMAP24XX 148#ifdef CONFIG_ARCH_OMAP2420
135static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = { 149static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
136 { 150 {
137 .phys_base = OMAP24XX_MCBSP1_BASE, 151 .phys_base = OMAP24XX_MCBSP1_BASE,
138 .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
139 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, 152 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
140 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 153 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
141 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 154 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
@@ -145,7 +158,6 @@ static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = {
145 }, 158 },
146 { 159 {
147 .phys_base = OMAP24XX_MCBSP2_BASE, 160 .phys_base = OMAP24XX_MCBSP2_BASE,
148 .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
149 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, 161 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
150 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, 162 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
151 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 163 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
@@ -154,17 +166,70 @@ static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = {
154 .clk_name = "mcbsp_clk", 166 .clk_name = "mcbsp_clk",
155 }, 167 },
156}; 168};
157#define OMAP24XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap24xx_mcbsp_pdata) 169#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
158#else 170#else
159#define omap24xx_mcbsp_pdata NULL 171#define omap2420_mcbsp_pdata NULL
160#define OMAP24XX_MCBSP_PDATA_SZ 0 172#define OMAP2420_MCBSP_PDATA_SZ 0
173#endif
174
175#ifdef CONFIG_ARCH_OMAP2430
176static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
177 {
178 .phys_base = OMAP24XX_MCBSP1_BASE,
179 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
180 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
181 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
182 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
183 .ops = &omap2_mcbsp_ops,
184 .clk_name = "mcbsp_clk",
185 },
186 {
187 .phys_base = OMAP24XX_MCBSP2_BASE,
188 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
189 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
190 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
191 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
192 .ops = &omap2_mcbsp_ops,
193 .clk_name = "mcbsp_clk",
194 },
195 {
196 .phys_base = OMAP2430_MCBSP3_BASE,
197 .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
198 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
199 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
200 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
201 .ops = &omap2_mcbsp_ops,
202 .clk_name = "mcbsp_clk",
203 },
204 {
205 .phys_base = OMAP2430_MCBSP4_BASE,
206 .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
207 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
208 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
209 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
210 .ops = &omap2_mcbsp_ops,
211 .clk_name = "mcbsp_clk",
212 },
213 {
214 .phys_base = OMAP2430_MCBSP5_BASE,
215 .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
216 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
217 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
218 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
219 .ops = &omap2_mcbsp_ops,
220 .clk_name = "mcbsp_clk",
221 },
222};
223#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
224#else
225#define omap2430_mcbsp_pdata NULL
226#define OMAP2430_MCBSP_PDATA_SZ 0
161#endif 227#endif
162 228
163#ifdef CONFIG_ARCH_OMAP34XX 229#ifdef CONFIG_ARCH_OMAP34XX
164static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { 230static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
165 { 231 {
166 .phys_base = OMAP34XX_MCBSP1_BASE, 232 .phys_base = OMAP34XX_MCBSP1_BASE,
167 .virt_base = IO_ADDRESS(OMAP34XX_MCBSP1_BASE),
168 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, 233 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
169 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 234 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
170 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 235 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
@@ -174,7 +239,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
174 }, 239 },
175 { 240 {
176 .phys_base = OMAP34XX_MCBSP2_BASE, 241 .phys_base = OMAP34XX_MCBSP2_BASE,
177 .virt_base = IO_ADDRESS(OMAP34XX_MCBSP2_BASE),
178 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, 242 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
179 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, 243 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
180 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 244 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
@@ -182,6 +246,33 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
182 .ops = &omap2_mcbsp_ops, 246 .ops = &omap2_mcbsp_ops,
183 .clk_name = "mcbsp_clk", 247 .clk_name = "mcbsp_clk",
184 }, 248 },
249 {
250 .phys_base = OMAP34XX_MCBSP3_BASE,
251 .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
252 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
253 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
254 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
255 .ops = &omap2_mcbsp_ops,
256 .clk_name = "mcbsp_clk",
257 },
258 {
259 .phys_base = OMAP34XX_MCBSP4_BASE,
260 .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
261 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
262 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
263 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
264 .ops = &omap2_mcbsp_ops,
265 .clk_name = "mcbsp_clk",
266 },
267 {
268 .phys_base = OMAP34XX_MCBSP5_BASE,
269 .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
270 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
271 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
272 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
273 .ops = &omap2_mcbsp_ops,
274 .clk_name = "mcbsp_clk",
275 },
185}; 276};
186#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) 277#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
187#else 278#else
@@ -189,7 +280,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
189#define OMAP34XX_MCBSP_PDATA_SZ 0 280#define OMAP34XX_MCBSP_PDATA_SZ 0
190#endif 281#endif
191 282
192int __init omap2_mcbsp_init(void) 283static int __init omap2_mcbsp_init(void)
193{ 284{
194 int i; 285 int i;
195 286
@@ -199,10 +290,24 @@ int __init omap2_mcbsp_init(void)
199 clk_register(&omap_mcbsp_clks[i].clk); 290 clk_register(&omap_mcbsp_clks[i].clk);
200 } 291 }
201 292
202 if (cpu_is_omap24xx()) 293 if (cpu_is_omap2420())
203 omap_mcbsp_register_board_cfg(omap24xx_mcbsp_pdata, 294 omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
204 OMAP24XX_MCBSP_PDATA_SZ); 295 if (cpu_is_omap2430())
296 omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
297 if (cpu_is_omap34xx())
298 omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
299
300 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
301 GFP_KERNEL);
302 if (!mcbsp_ptr)
303 return -ENOMEM;
205 304
305 if (cpu_is_omap2420())
306 omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
307 OMAP2420_MCBSP_PDATA_SZ);
308 if (cpu_is_omap2430())
309 omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
310 OMAP2430_MCBSP_PDATA_SZ);
206 if (cpu_is_omap34xx()) 311 if (cpu_is_omap34xx())
207 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata, 312 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
208 OMAP34XX_MCBSP_PDATA_SZ); 313 OMAP34XX_MCBSP_PDATA_SZ);
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index ab1462b02e6e..882c70224292 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -101,6 +101,17 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
101 return prev; 101 return prev;
102} 102}
103 103
104#if !defined(CONFIG_ARCH_OMAP2)
105void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
106 u32 base_cs, u32 force_unlock)
107{
108}
109void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
110 u32 mem_type)
111{
112}
113#endif
114
104void omap2_init_memory_params(u32 force_lock_to_unlock_mode) 115void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
105{ 116{
106 unsigned long dll_cnt; 117 unsigned long dll_cnt;
@@ -165,6 +176,9 @@ void __init omap2_init_memory(void)
165{ 176{
166 u32 l; 177 u32 l;
167 178
179 if (!cpu_is_omap2420())
180 return;
181
168 l = sms_read_reg(SMS_SYSCONFIG); 182 l = sms_read_reg(SMS_SYSCONFIG);
169 l &= ~(0x3 << 3); 183 l &= ~(0x3 << 3);
170 l |= (0x2 << 3); 184 l |= (0x2 << 3);
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h
index 9a280b50a893..bb3db80a7c46 100644
--- a/arch/arm/mach-omap2/memory.h
+++ b/arch/arm/mach-omap2/memory.h
@@ -14,6 +14,9 @@
14 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
15 */ 15 */
16 16
17#ifndef ARCH_ARM_MACH_OMAP2_MEMORY_H
18#define ARCH_ARM_MACH_OMAP2_MEMORY_H
19
17/* Memory timings */ 20/* Memory timings */
18#define M_DDR 1 21#define M_DDR 1
19#define M_LOCK_CTRL (1 << 2) 22#define M_LOCK_CTRL (1 << 2)
@@ -34,3 +37,7 @@ extern u32 omap2_memory_get_fast_dll_ctrl(void);
34extern u32 omap2_memory_get_type(void); 37extern u32 omap2_memory_get_type(void);
35u32 omap2_dll_force_needed(void); 38u32 omap2_dll_force_needed(void);
36u32 omap2_reprogram_sdrc(u32 level, u32 force); 39u32 omap2_reprogram_sdrc(u32 level, u32 force);
40void __init omap2_init_memory(void);
41void __init gpmc_init(void);
42
43#endif
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 6b7d672058b9..b1393673d95d 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/mux.c 2 * linux/arch/arm/mach-omap2/mux.c
3 * 3 *
4 * OMAP2 pin multiplexing configurations 4 * OMAP2 and OMAP3 pin multiplexing configurations
5 * 5 *
6 * Copyright (C) 2004 - 2008 Texas Instruments Inc. 6 * Copyright (C) 2004 - 2008 Texas Instruments Inc.
7 * Copyright (C) 2003 - 2008 Nokia Corporation 7 * Copyright (C) 2003 - 2008 Nokia Corporation
@@ -220,16 +220,222 @@ MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
220#define OMAP24XX_PINS_SZ 0 220#define OMAP24XX_PINS_SZ 0
221#endif /* CONFIG_ARCH_OMAP24XX */ 221#endif /* CONFIG_ARCH_OMAP24XX */
222 222
223#define OMAP24XX_PULL_ENA (1 << 3) 223#ifdef CONFIG_ARCH_OMAP34XX
224#define OMAP24XX_PULL_UP (1 << 4) 224static struct pin_config __initdata_or_module omap34xx_pins[] = {
225/*
226 * Name, reg-offset,
227 * mux-mode | [active-mode | off-mode]
228 */
229
230/* 34xx I2C */
231MUX_CFG_34XX("K21_34XX_I2C1_SCL", 0x1ba,
232 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
233MUX_CFG_34XX("J21_34XX_I2C1_SDA", 0x1bc,
234 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
235MUX_CFG_34XX("AF15_34XX_I2C2_SCL", 0x1be,
236 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
237MUX_CFG_34XX("AE15_34XX_I2C2_SDA", 0x1c0,
238 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
239MUX_CFG_34XX("AF14_34XX_I2C3_SCL", 0x1c2,
240 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
241MUX_CFG_34XX("AG14_34XX_I2C3_SDA", 0x1c4,
242 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
243MUX_CFG_34XX("AD26_34XX_I2C4_SCL", 0xa00,
244 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
245MUX_CFG_34XX("AE26_34XX_I2C4_SDA", 0xa02,
246 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
247
248/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
249MUX_CFG_34XX("Y8_3430_USB1HS_PHY_CLK", 0x5da,
250 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
251MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8,
252 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
253MUX_CFG_34XX("AA14_3430_USB1HS_PHY_DIR", 0x5ec,
254 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
255MUX_CFG_34XX("AA11_3430_USB1HS_PHY_NXT", 0x5ee,
256 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
257MUX_CFG_34XX("W13_3430_USB1HS_PHY_D0", 0x5dc,
258 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
259MUX_CFG_34XX("W12_3430_USB1HS_PHY_D1", 0x5de,
260 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
261MUX_CFG_34XX("W11_3430_USB1HS_PHY_D2", 0x5e0,
262 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
263MUX_CFG_34XX("Y11_3430_USB1HS_PHY_D3", 0x5ea,
264 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
265MUX_CFG_34XX("W9_3430_USB1HS_PHY_D4", 0x5e4,
266 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
267MUX_CFG_34XX("Y12_3430_USB1HS_PHY_D5", 0x5e6,
268 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
269MUX_CFG_34XX("W8_3430_USB1HS_PHY_D6", 0x5e8,
270 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
271MUX_CFG_34XX("Y13_3430_USB1HS_PHY_D7", 0x5e2,
272 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
273
274/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
275MUX_CFG_34XX("AA8_3430_USB2HS_PHY_CLK", 0x5f0,
276 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
277MUX_CFG_34XX("AA10_3430_USB2HS_PHY_STP", 0x5f2,
278 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
279MUX_CFG_34XX("AA9_3430_USB2HS_PHY_DIR", 0x5f4,
280 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
281MUX_CFG_34XX("AB11_3430_USB2HS_PHY_NXT", 0x5f6,
282 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
283MUX_CFG_34XX("AB10_3430_USB2HS_PHY_D0", 0x5f8,
284 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
285MUX_CFG_34XX("AB9_3430_USB2HS_PHY_D1", 0x5fa,
286 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
287MUX_CFG_34XX("W3_3430_USB2HS_PHY_D2", 0x1d4,
288 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
289MUX_CFG_34XX("T4_3430_USB2HS_PHY_D3", 0x1de,
290 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
291MUX_CFG_34XX("T3_3430_USB2HS_PHY_D4", 0x1d8,
292 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
293MUX_CFG_34XX("R3_3430_USB2HS_PHY_D5", 0x1da,
294 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
295MUX_CFG_34XX("R4_3430_USB2HS_PHY_D6", 0x1dc,
296 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
297MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6,
298 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
299
300/* TLL - HSUSB: 12-pin TLL Port 1*/
301MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da,
302 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
303MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
304 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
305MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec,
306 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
307MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee,
308 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
309MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc,
310 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
311MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de,
312 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
313MUX_CFG_34XX("W11_3430_USB1HS_TLL_D2", 0x5e0,
314 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
315MUX_CFG_34XX("Y11_3430_USB1HS_TLL_D3", 0x5ea,
316 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
317MUX_CFG_34XX("W9_3430_USB1HS_TLL_D4", 0x5e4,
318 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
319MUX_CFG_34XX("Y12_3430_USB1HS_TLL_D5", 0x5e6,
320 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
321MUX_CFG_34XX("W8_3430_USB1HS_TLL_D6", 0x5e8,
322 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
323MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2,
324 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
325
326/* TLL - HSUSB: 12-pin TLL Port 2*/
327MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0,
328 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
329MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
330 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
331MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4,
332 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
333MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6,
334 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
335MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8,
336 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
337MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa,
338 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
339MUX_CFG_34XX("W3_3430_USB2HS_TLL_D2", 0x1d4,
340 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
341MUX_CFG_34XX("T4_3430_USB2HS_TLL_D3", 0x1de,
342 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
343MUX_CFG_34XX("T3_3430_USB2HS_TLL_D4", 0x1d8,
344 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
345MUX_CFG_34XX("R3_3430_USB2HS_TLL_D5", 0x1da,
346 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
347MUX_CFG_34XX("R4_3430_USB2HS_TLL_D6", 0x1dc,
348 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
349MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6,
350 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
351
352/* TLL - HSUSB: 12-pin TLL Port 3*/
353MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180,
354 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
355MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
356 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLUP)
357MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168,
358 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
359MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a,
360 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
361MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186,
362 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
363MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184,
364 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
365MUX_CFG_34XX("Y5_3430_USB3HS_TLL_D2", 0x188,
366 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
367MUX_CFG_34XX("W5_3430_USB3HS_TLL_D3", 0x18a,
368 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
369MUX_CFG_34XX("AB12_3430_USB3HS_TLL_D4", 0x16c,
370 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
371MUX_CFG_34XX("AB13_3430_USB3HS_TLL_D5", 0x16e,
372 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
373MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170,
374 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
375MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172,
376 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
377
378/* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
379MUX_CFG_34XX("AF10_3430_USB1FS_PHY_MM1_RXDP", 0x5d8,
380 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
381MUX_CFG_34XX("AG9_3430_USB1FS_PHY_MM1_RXDM", 0x5ee,
382 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
383MUX_CFG_34XX("W13_3430_USB1FS_PHY_MM1_RXRCV", 0x5dc,
384 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
385MUX_CFG_34XX("W12_3430_USB1FS_PHY_MM1_TXSE0", 0x5de,
386 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
387MUX_CFG_34XX("W11_3430_USB1FS_PHY_MM1_TXDAT", 0x5e0,
388 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
389MUX_CFG_34XX("Y11_3430_USB1FS_PHY_MM1_TXEN_N", 0x5ea,
390 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
391
392/* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
393MUX_CFG_34XX("AF7_3430_USB2FS_PHY_MM2_RXDP", 0x5f2,
394 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
395MUX_CFG_34XX("AH7_3430_USB2FS_PHY_MM2_RXDM", 0x5f6,
396 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
397MUX_CFG_34XX("AB10_3430_USB2FS_PHY_MM2_RXRCV", 0x5f8,
398 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
399MUX_CFG_34XX("AB9_3430_USB2FS_PHY_MM2_TXSE0", 0x5fa,
400 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
401MUX_CFG_34XX("W3_3430_USB2FS_PHY_MM2_TXDAT", 0x1d4,
402 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
403MUX_CFG_34XX("T4_3430_USB2FS_PHY_MM2_TXEN_N", 0x1de,
404 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
405
406/* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
407MUX_CFG_34XX("AH3_3430_USB3FS_PHY_MM3_RXDP", 0x166,
408 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
409MUX_CFG_34XX("AE3_3430_USB3FS_PHY_MM3_RXDM", 0x16a,
410 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
411MUX_CFG_34XX("AD1_3430_USB3FS_PHY_MM3_RXRCV", 0x186,
412 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
413MUX_CFG_34XX("AE1_3430_USB3FS_PHY_MM3_TXSE0", 0x184,
414 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
415MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188,
416 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
417MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a,
418 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
419
420};
421
422#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
423
424#else
425#define omap34xx_pins NULL
426#define OMAP34XX_PINS_SZ 0
427#endif /* CONFIG_ARCH_OMAP34XX */
225 428
226#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) 429#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
227void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg) 430static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
228{ 431{
229 u16 orig; 432 u16 orig;
230 u8 warn = 0, debug = 0; 433 u8 warn = 0, debug = 0;
231 434
232 orig = omap_ctrl_readb(cfg->mux_reg); 435 if (cpu_is_omap24xx())
436 orig = omap_ctrl_readb(cfg->mux_reg);
437 else
438 orig = omap_ctrl_readw(cfg->mux_reg);
233 439
234#ifdef CONFIG_OMAP_MUX_DEBUG 440#ifdef CONFIG_OMAP_MUX_DEBUG
235 debug = cfg->debug; 441 debug = cfg->debug;
@@ -255,9 +461,9 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
255 spin_lock_irqsave(&mux_spin_lock, flags); 461 spin_lock_irqsave(&mux_spin_lock, flags);
256 reg |= cfg->mask & 0x7; 462 reg |= cfg->mask & 0x7;
257 if (cfg->pull_val) 463 if (cfg->pull_val)
258 reg |= OMAP24XX_PULL_ENA; 464 reg |= OMAP2_PULL_ENA;
259 if (cfg->pu_pd_val) 465 if (cfg->pu_pd_val)
260 reg |= OMAP24XX_PULL_UP; 466 reg |= OMAP2_PULL_UP;
261 omap2_cfg_debug(cfg, reg); 467 omap2_cfg_debug(cfg, reg);
262 omap_ctrl_writeb(reg, cfg->mux_reg); 468 omap_ctrl_writeb(reg, cfg->mux_reg);
263 spin_unlock_irqrestore(&mux_spin_lock, flags); 469 spin_unlock_irqrestore(&mux_spin_lock, flags);
@@ -265,7 +471,26 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
265 return 0; 471 return 0;
266} 472}
267#else 473#else
268#define omap24xx_cfg_reg 0 474#define omap24xx_cfg_reg NULL
475#endif
476
477#ifdef CONFIG_ARCH_OMAP34XX
478static int __init_or_module omap34xx_cfg_reg(const struct pin_config *cfg)
479{
480 static DEFINE_SPINLOCK(mux_spin_lock);
481 unsigned long flags;
482 u16 reg = 0;
483
484 spin_lock_irqsave(&mux_spin_lock, flags);
485 reg |= cfg->mux_val;
486 omap2_cfg_debug(cfg, reg);
487 omap_ctrl_writew(reg, cfg->mux_reg);
488 spin_unlock_irqrestore(&mux_spin_lock, flags);
489
490 return 0;
491}
492#else
493#define omap34xx_cfg_reg NULL
269#endif 494#endif
270 495
271int __init omap2_mux_init(void) 496int __init omap2_mux_init(void)
@@ -274,6 +499,10 @@ int __init omap2_mux_init(void)
274 arch_mux_cfg.pins = omap24xx_pins; 499 arch_mux_cfg.pins = omap24xx_pins;
275 arch_mux_cfg.size = OMAP24XX_PINS_SZ; 500 arch_mux_cfg.size = OMAP24XX_PINS_SZ;
276 arch_mux_cfg.cfg_reg = omap24xx_cfg_reg; 501 arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
502 } else if (cpu_is_omap34xx()) {
503 arch_mux_cfg.pins = omap34xx_pins;
504 arch_mux_cfg.size = OMAP34XX_PINS_SZ;
505 arch_mux_cfg.cfg_reg = omap34xx_cfg_reg;
277 } 506 }
278 507
279 return omap_mux_register(&arch_mux_cfg); 508 return omap_mux_register(&arch_mux_cfg);
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
new file mode 100644
index 000000000000..73e2971b1757
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -0,0 +1,1113 @@
1/*
2 * OMAP powerdomain control
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifdef CONFIG_OMAP_DEBUG_POWERDOMAIN
14# define DEBUG
15#endif
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/types.h>
20#include <linux/delay.h>
21#include <linux/spinlock.h>
22#include <linux/list.h>
23#include <linux/errno.h>
24#include <linux/err.h>
25#include <linux/io.h>
26
27#include <asm/atomic.h>
28
29#include "cm.h"
30#include "cm-regbits-34xx.h"
31#include "prm.h"
32#include "prm-regbits-34xx.h"
33
34#include <mach/cpu.h>
35#include <mach/powerdomain.h>
36#include <mach/clockdomain.h>
37
38/* pwrdm_list contains all registered struct powerdomains */
39static LIST_HEAD(pwrdm_list);
40
41/*
42 * pwrdm_rwlock protects pwrdm_list add and del ops - also reused to
43 * protect pwrdm_clkdms[] during clkdm add/del ops
44 */
45static DEFINE_RWLOCK(pwrdm_rwlock);
46
47
48/* Private functions */
49
50static u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
51{
52 u32 v;
53
54 v = prm_read_mod_reg(domain, idx);
55 v &= mask;
56 v >>= __ffs(mask);
57
58 return v;
59}
60
61static struct powerdomain *_pwrdm_lookup(const char *name)
62{
63 struct powerdomain *pwrdm, *temp_pwrdm;
64
65 pwrdm = NULL;
66
67 list_for_each_entry(temp_pwrdm, &pwrdm_list, node) {
68 if (!strcmp(name, temp_pwrdm->name)) {
69 pwrdm = temp_pwrdm;
70 break;
71 }
72 }
73
74 return pwrdm;
75}
76
77/* _pwrdm_deps_lookup - look up the specified powerdomain in a pwrdm list */
78static struct powerdomain *_pwrdm_deps_lookup(struct powerdomain *pwrdm,
79 struct pwrdm_dep *deps)
80{
81 struct pwrdm_dep *pd;
82
83 if (!pwrdm || !deps || !omap_chip_is(pwrdm->omap_chip))
84 return ERR_PTR(-EINVAL);
85
86 for (pd = deps; pd; pd++) {
87
88 if (!omap_chip_is(pd->omap_chip))
89 continue;
90
91 if (!pd->pwrdm && pd->pwrdm_name)
92 pd->pwrdm = pwrdm_lookup(pd->pwrdm_name);
93
94 if (pd->pwrdm == pwrdm)
95 break;
96
97 }
98
99 if (!pd)
100 return ERR_PTR(-ENOENT);
101
102 return pd->pwrdm;
103}
104
105
106/* Public functions */
107
108/**
109 * pwrdm_init - set up the powerdomain layer
110 *
111 * Loop through the list of powerdomains, registering all that are
112 * available on the current CPU. If pwrdm_list is supplied and not
113 * null, all of the referenced powerdomains will be registered. No
114 * return value.
115 */
116void pwrdm_init(struct powerdomain **pwrdm_list)
117{
118 struct powerdomain **p = NULL;
119
120 if (pwrdm_list)
121 for (p = pwrdm_list; *p; p++)
122 pwrdm_register(*p);
123}
124
125/**
126 * pwrdm_register - register a powerdomain
127 * @pwrdm: struct powerdomain * to register
128 *
129 * Adds a powerdomain to the internal powerdomain list. Returns
130 * -EINVAL if given a null pointer, -EEXIST if a powerdomain is
131 * already registered by the provided name, or 0 upon success.
132 */
133int pwrdm_register(struct powerdomain *pwrdm)
134{
135 unsigned long flags;
136 int ret = -EINVAL;
137
138 if (!pwrdm)
139 return -EINVAL;
140
141 if (!omap_chip_is(pwrdm->omap_chip))
142 return -EINVAL;
143
144 write_lock_irqsave(&pwrdm_rwlock, flags);
145 if (_pwrdm_lookup(pwrdm->name)) {
146 ret = -EEXIST;
147 goto pr_unlock;
148 }
149
150 list_add(&pwrdm->node, &pwrdm_list);
151
152 pr_debug("powerdomain: registered %s\n", pwrdm->name);
153 ret = 0;
154
155pr_unlock:
156 write_unlock_irqrestore(&pwrdm_rwlock, flags);
157
158 return ret;
159}
160
161/**
162 * pwrdm_unregister - unregister a powerdomain
163 * @pwrdm: struct powerdomain * to unregister
164 *
165 * Removes a powerdomain from the internal powerdomain list. Returns
166 * -EINVAL if pwrdm argument is NULL.
167 */
168int pwrdm_unregister(struct powerdomain *pwrdm)
169{
170 unsigned long flags;
171
172 if (!pwrdm)
173 return -EINVAL;
174
175 write_lock_irqsave(&pwrdm_rwlock, flags);
176 list_del(&pwrdm->node);
177 write_unlock_irqrestore(&pwrdm_rwlock, flags);
178
179 pr_debug("powerdomain: unregistered %s\n", pwrdm->name);
180
181 return 0;
182}
183
184/**
185 * pwrdm_lookup - look up a powerdomain by name, return a pointer
186 * @name: name of powerdomain
187 *
188 * Find a registered powerdomain by its name. Returns a pointer to the
189 * struct powerdomain if found, or NULL otherwise.
190 */
191struct powerdomain *pwrdm_lookup(const char *name)
192{
193 struct powerdomain *pwrdm;
194 unsigned long flags;
195
196 if (!name)
197 return NULL;
198
199 read_lock_irqsave(&pwrdm_rwlock, flags);
200 pwrdm = _pwrdm_lookup(name);
201 read_unlock_irqrestore(&pwrdm_rwlock, flags);
202
203 return pwrdm;
204}
205
206/**
207 * pwrdm_for_each - call function on each registered clockdomain
208 * @fn: callback function *
209 *
210 * Call the supplied function for each registered powerdomain. The
211 * callback function can return anything but 0 to bail out early from
212 * the iterator. The callback function is called with the pwrdm_rwlock
213 * held for reading, so no powerdomain structure manipulation
214 * functions should be called from the callback, although hardware
215 * powerdomain control functions are fine. Returns the last return
216 * value of the callback function, which should be 0 for success or
217 * anything else to indicate failure; or -EINVAL if the function
218 * pointer is null.
219 */
220int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm))
221{
222 struct powerdomain *temp_pwrdm;
223 unsigned long flags;
224 int ret = 0;
225
226 if (!fn)
227 return -EINVAL;
228
229 read_lock_irqsave(&pwrdm_rwlock, flags);
230 list_for_each_entry(temp_pwrdm, &pwrdm_list, node) {
231 ret = (*fn)(temp_pwrdm);
232 if (ret)
233 break;
234 }
235 read_unlock_irqrestore(&pwrdm_rwlock, flags);
236
237 return ret;
238}
239
240/**
241 * pwrdm_add_clkdm - add a clockdomain to a powerdomain
242 * @pwrdm: struct powerdomain * to add the clockdomain to
243 * @clkdm: struct clockdomain * to associate with a powerdomain
244 *
245 * Associate the clockdomain 'clkdm' with a powerdomain 'pwrdm'. This
246 * enables the use of pwrdm_for_each_clkdm(). Returns -EINVAL if
247 * presented with invalid pointers; -ENOMEM if memory could not be allocated;
248 * or 0 upon success.
249 */
250int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
251{
252 unsigned long flags;
253 int i;
254 int ret = -EINVAL;
255
256 if (!pwrdm || !clkdm)
257 return -EINVAL;
258
259 pr_debug("powerdomain: associating clockdomain %s with powerdomain "
260 "%s\n", clkdm->name, pwrdm->name);
261
262 write_lock_irqsave(&pwrdm_rwlock, flags);
263
264 for (i = 0; i < PWRDM_MAX_CLKDMS; i++) {
265 if (!pwrdm->pwrdm_clkdms[i])
266 break;
267#ifdef DEBUG
268 if (pwrdm->pwrdm_clkdms[i] == clkdm) {
269 ret = -EINVAL;
270 goto pac_exit;
271 }
272#endif
273 }
274
275 if (i == PWRDM_MAX_CLKDMS) {
276 pr_debug("powerdomain: increase PWRDM_MAX_CLKDMS for "
277 "pwrdm %s clkdm %s\n", pwrdm->name, clkdm->name);
278 WARN_ON(1);
279 ret = -ENOMEM;
280 goto pac_exit;
281 }
282
283 pwrdm->pwrdm_clkdms[i] = clkdm;
284
285 ret = 0;
286
287pac_exit:
288 write_unlock_irqrestore(&pwrdm_rwlock, flags);
289
290 return ret;
291}
292
293/**
294 * pwrdm_del_clkdm - remove a clockdomain from a powerdomain
295 * @pwrdm: struct powerdomain * to add the clockdomain to
296 * @clkdm: struct clockdomain * to associate with a powerdomain
297 *
298 * Dissociate the clockdomain 'clkdm' from the powerdomain
299 * 'pwrdm'. Returns -EINVAL if presented with invalid pointers;
300 * -ENOENT if the clkdm was not associated with the powerdomain, or 0
301 * upon success.
302 */
303int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
304{
305 unsigned long flags;
306 int ret = -EINVAL;
307 int i;
308
309 if (!pwrdm || !clkdm)
310 return -EINVAL;
311
312 pr_debug("powerdomain: dissociating clockdomain %s from powerdomain "
313 "%s\n", clkdm->name, pwrdm->name);
314
315 write_lock_irqsave(&pwrdm_rwlock, flags);
316
317 for (i = 0; i < PWRDM_MAX_CLKDMS; i++)
318 if (pwrdm->pwrdm_clkdms[i] == clkdm)
319 break;
320
321 if (i == PWRDM_MAX_CLKDMS) {
322 pr_debug("powerdomain: clkdm %s not associated with pwrdm "
323 "%s ?!\n", clkdm->name, pwrdm->name);
324 ret = -ENOENT;
325 goto pdc_exit;
326 }
327
328 pwrdm->pwrdm_clkdms[i] = NULL;
329
330 ret = 0;
331
332pdc_exit:
333 write_unlock_irqrestore(&pwrdm_rwlock, flags);
334
335 return ret;
336}
337
338/**
339 * pwrdm_for_each_clkdm - call function on each clkdm in a pwrdm
340 * @pwrdm: struct powerdomain * to iterate over
341 * @fn: callback function *
342 *
343 * Call the supplied function for each clockdomain in the powerdomain
344 * 'pwrdm'. The callback function can return anything but 0 to bail
345 * out early from the iterator. The callback function is called with
346 * the pwrdm_rwlock held for reading, so no powerdomain structure
347 * manipulation functions should be called from the callback, although
348 * hardware powerdomain control functions are fine. Returns -EINVAL
349 * if presented with invalid pointers; or passes along the last return
350 * value of the callback function, which should be 0 for success or
351 * anything else to indicate failure.
352 */
353int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
354 int (*fn)(struct powerdomain *pwrdm,
355 struct clockdomain *clkdm))
356{
357 unsigned long flags;
358 int ret = 0;
359 int i;
360
361 if (!fn)
362 return -EINVAL;
363
364 read_lock_irqsave(&pwrdm_rwlock, flags);
365
366 for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++)
367 ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]);
368
369 read_unlock_irqrestore(&pwrdm_rwlock, flags);
370
371 return ret;
372}
373
374
375/**
376 * pwrdm_add_wkdep - add a wakeup dependency from pwrdm2 to pwrdm1
377 * @pwrdm1: wake this struct powerdomain * up (dependent)
378 * @pwrdm2: when this struct powerdomain * wakes up (source)
379 *
380 * When the powerdomain represented by pwrdm2 wakes up (due to an
381 * interrupt), wake up pwrdm1. Implemented in hardware on the OMAP,
382 * this feature is designed to reduce wakeup latency of the dependent
383 * powerdomain. Returns -EINVAL if presented with invalid powerdomain
384 * pointers, -ENOENT if pwrdm2 cannot wake up pwrdm1 in hardware, or
385 * 0 upon success.
386 */
387int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
388{
389 struct powerdomain *p;
390
391 if (!pwrdm1)
392 return -EINVAL;
393
394 p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs);
395 if (IS_ERR(p)) {
396 pr_debug("powerdomain: hardware cannot set/clear wake up of "
397 "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
398 return IS_ERR(p);
399 }
400
401 pr_debug("powerdomain: hardware will wake up %s when %s wakes up\n",
402 pwrdm1->name, pwrdm2->name);
403
404 prm_set_mod_reg_bits((1 << pwrdm2->dep_bit),
405 pwrdm1->prcm_offs, PM_WKDEP);
406
407 return 0;
408}
409
410/**
411 * pwrdm_del_wkdep - remove a wakeup dependency from pwrdm2 to pwrdm1
412 * @pwrdm1: wake this struct powerdomain * up (dependent)
413 * @pwrdm2: when this struct powerdomain * wakes up (source)
414 *
415 * Remove a wakeup dependency that causes pwrdm1 to wake up when pwrdm2
416 * wakes up. Returns -EINVAL if presented with invalid powerdomain
417 * pointers, -ENOENT if pwrdm2 cannot wake up pwrdm1 in hardware, or
418 * 0 upon success.
419 */
420int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
421{
422 struct powerdomain *p;
423
424 if (!pwrdm1)
425 return -EINVAL;
426
427 p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs);
428 if (IS_ERR(p)) {
429 pr_debug("powerdomain: hardware cannot set/clear wake up of "
430 "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
431 return IS_ERR(p);
432 }
433
434 pr_debug("powerdomain: hardware will no longer wake up %s after %s "
435 "wakes up\n", pwrdm1->name, pwrdm2->name);
436
437 prm_clear_mod_reg_bits((1 << pwrdm2->dep_bit),
438 pwrdm1->prcm_offs, PM_WKDEP);
439
440 return 0;
441}
442
443/**
444 * pwrdm_read_wkdep - read wakeup dependency state from pwrdm2 to pwrdm1
445 * @pwrdm1: wake this struct powerdomain * up (dependent)
446 * @pwrdm2: when this struct powerdomain * wakes up (source)
447 *
448 * Return 1 if a hardware wakeup dependency exists wherein pwrdm1 will be
449 * awoken when pwrdm2 wakes up; 0 if dependency is not set; -EINVAL
450 * if either powerdomain pointer is invalid; or -ENOENT if the hardware
451 * is incapable.
452 *
453 * REVISIT: Currently this function only represents software-controllable
454 * wakeup dependencies. Wakeup dependencies fixed in hardware are not
455 * yet handled here.
456 */
457int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
458{
459 struct powerdomain *p;
460
461 if (!pwrdm1)
462 return -EINVAL;
463
464 p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs);
465 if (IS_ERR(p)) {
466 pr_debug("powerdomain: hardware cannot set/clear wake up of "
467 "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
468 return IS_ERR(p);
469 }
470
471 return prm_read_mod_bits_shift(pwrdm1->prcm_offs, PM_WKDEP,
472 (1 << pwrdm2->dep_bit));
473}
474
475/**
476 * pwrdm_add_sleepdep - add a sleep dependency from pwrdm2 to pwrdm1
477 * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent)
478 * @pwrdm2: when this struct powerdomain * is active (source)
479 *
480 * Prevent pwrdm1 from automatically going inactive (and then to
481 * retention or off) if pwrdm2 is still active. Returns -EINVAL if
482 * presented with invalid powerdomain pointers or called on a machine
483 * that does not support software-configurable hardware sleep dependencies,
484 * -ENOENT if the specified dependency cannot be set in hardware, or
485 * 0 upon success.
486 */
487int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
488{
489 struct powerdomain *p;
490
491 if (!pwrdm1)
492 return -EINVAL;
493
494 if (!cpu_is_omap34xx())
495 return -EINVAL;
496
497 p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
498 if (IS_ERR(p)) {
499 pr_debug("powerdomain: hardware cannot set/clear sleep "
500 "dependency affecting %s from %s\n", pwrdm1->name,
501 pwrdm2->name);
502 return IS_ERR(p);
503 }
504
505 pr_debug("powerdomain: will prevent %s from sleeping if %s is active\n",
506 pwrdm1->name, pwrdm2->name);
507
508 cm_set_mod_reg_bits((1 << pwrdm2->dep_bit),
509 pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP);
510
511 return 0;
512}
513
514/**
515 * pwrdm_del_sleepdep - remove a sleep dependency from pwrdm2 to pwrdm1
516 * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent)
517 * @pwrdm2: when this struct powerdomain * is active (source)
518 *
519 * Allow pwrdm1 to automatically go inactive (and then to retention or
520 * off), independent of the activity state of pwrdm2. Returns -EINVAL
521 * if presented with invalid powerdomain pointers or called on a machine
522 * that does not support software-configurable hardware sleep dependencies,
523 * -ENOENT if the specified dependency cannot be cleared in hardware, or
524 * 0 upon success.
525 */
526int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
527{
528 struct powerdomain *p;
529
530 if (!pwrdm1)
531 return -EINVAL;
532
533 if (!cpu_is_omap34xx())
534 return -EINVAL;
535
536 p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
537 if (IS_ERR(p)) {
538 pr_debug("powerdomain: hardware cannot set/clear sleep "
539 "dependency affecting %s from %s\n", pwrdm1->name,
540 pwrdm2->name);
541 return IS_ERR(p);
542 }
543
544 pr_debug("powerdomain: will no longer prevent %s from sleeping if "
545 "%s is active\n", pwrdm1->name, pwrdm2->name);
546
547 cm_clear_mod_reg_bits((1 << pwrdm2->dep_bit),
548 pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP);
549
550 return 0;
551}
552
553/**
554 * pwrdm_read_sleepdep - read sleep dependency state from pwrdm2 to pwrdm1
555 * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent)
556 * @pwrdm2: when this struct powerdomain * is active (source)
557 *
558 * Return 1 if a hardware sleep dependency exists wherein pwrdm1 will
559 * not be allowed to automatically go inactive if pwrdm2 is active;
560 * 0 if pwrdm1's automatic power state inactivity transition is independent
561 * of pwrdm2's; -EINVAL if either powerdomain pointer is invalid or called
562 * on a machine that does not support software-configurable hardware sleep
563 * dependencies; or -ENOENT if the hardware is incapable.
564 *
565 * REVISIT: Currently this function only represents software-controllable
566 * sleep dependencies. Sleep dependencies fixed in hardware are not
567 * yet handled here.
568 */
569int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
570{
571 struct powerdomain *p;
572
573 if (!pwrdm1)
574 return -EINVAL;
575
576 if (!cpu_is_omap34xx())
577 return -EINVAL;
578
579 p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
580 if (IS_ERR(p)) {
581 pr_debug("powerdomain: hardware cannot set/clear sleep "
582 "dependency affecting %s from %s\n", pwrdm1->name,
583 pwrdm2->name);
584 return IS_ERR(p);
585 }
586
587 return prm_read_mod_bits_shift(pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP,
588 (1 << pwrdm2->dep_bit));
589}
590
591/**
592 * pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain
593 * @pwrdm: struct powerdomain *
594 *
595 * Return the number of controllable memory banks in powerdomain pwrdm,
596 * starting with 1. Returns -EINVAL if the powerdomain pointer is null.
597 */
598int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm)
599{
600 if (!pwrdm)
601 return -EINVAL;
602
603 return pwrdm->banks;
604}
605
606/**
607 * pwrdm_set_next_pwrst - set next powerdomain power state
608 * @pwrdm: struct powerdomain * to set
609 * @pwrst: one of the PWRDM_POWER_* macros
610 *
611 * Set the powerdomain pwrdm's next power state to pwrst. The powerdomain
612 * may not enter this state immediately if the preconditions for this state
613 * have not been satisfied. Returns -EINVAL if the powerdomain pointer is
614 * null or if the power state is invalid for the powerdomin, or returns 0
615 * upon success.
616 */
617int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
618{
619 if (!pwrdm)
620 return -EINVAL;
621
622 if (!(pwrdm->pwrsts & (1 << pwrst)))
623 return -EINVAL;
624
625 pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
626 pwrdm->name, pwrst);
627
628 prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
629 (pwrst << OMAP_POWERSTATE_SHIFT),
630 pwrdm->prcm_offs, PM_PWSTCTRL);
631
632 return 0;
633}
634
635/**
636 * pwrdm_read_next_pwrst - get next powerdomain power state
637 * @pwrdm: struct powerdomain * to get power state
638 *
639 * Return the powerdomain pwrdm's next power state. Returns -EINVAL
640 * if the powerdomain pointer is null or returns the next power state
641 * upon success.
642 */
643int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
644{
645 if (!pwrdm)
646 return -EINVAL;
647
648 return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTCTRL,
649 OMAP_POWERSTATE_MASK);
650}
651
652/**
653 * pwrdm_read_pwrst - get current powerdomain power state
654 * @pwrdm: struct powerdomain * to get power state
655 *
656 * Return the powerdomain pwrdm's current power state. Returns -EINVAL
657 * if the powerdomain pointer is null or returns the current power state
658 * upon success.
659 */
660int pwrdm_read_pwrst(struct powerdomain *pwrdm)
661{
662 if (!pwrdm)
663 return -EINVAL;
664
665 return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST,
666 OMAP_POWERSTATEST_MASK);
667}
668
669/**
670 * pwrdm_read_prev_pwrst - get previous powerdomain power state
671 * @pwrdm: struct powerdomain * to get previous power state
672 *
673 * Return the powerdomain pwrdm's previous power state. Returns -EINVAL
674 * if the powerdomain pointer is null or returns the previous power state
675 * upon success.
676 */
677int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
678{
679 if (!pwrdm)
680 return -EINVAL;
681
682 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST,
683 OMAP3430_LASTPOWERSTATEENTERED_MASK);
684}
685
686/**
687 * pwrdm_set_logic_retst - set powerdomain logic power state upon retention
688 * @pwrdm: struct powerdomain * to set
689 * @pwrst: one of the PWRDM_POWER_* macros
690 *
691 * Set the next power state that the logic portion of the powerdomain
692 * pwrdm will enter when the powerdomain enters retention. This will
693 * be either RETENTION or OFF, if supported. Returns -EINVAL if the
694 * powerdomain pointer is null or the target power state is not not
695 * supported, or returns 0 upon success.
696 */
697int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
698{
699 if (!pwrdm)
700 return -EINVAL;
701
702 if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst)))
703 return -EINVAL;
704
705 pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n",
706 pwrdm->name, pwrst);
707
708 /*
709 * The register bit names below may not correspond to the
710 * actual names of the bits in each powerdomain's register,
711 * but the type of value returned is the same for each
712 * powerdomain.
713 */
714 prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE,
715 (pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)),
716 pwrdm->prcm_offs, PM_PWSTCTRL);
717
718 return 0;
719}
720
721/**
722 * pwrdm_set_mem_onst - set memory power state while powerdomain ON
723 * @pwrdm: struct powerdomain * to set
724 * @bank: memory bank number to set (0-3)
725 * @pwrst: one of the PWRDM_POWER_* macros
726 *
727 * Set the next power state that memory bank x of the powerdomain
728 * pwrdm will enter when the powerdomain enters the ON state. Bank
729 * will be a number from 0 to 3, and represents different types of
730 * memory, depending on the powerdomain. Returns -EINVAL if the
731 * powerdomain pointer is null or the target power state is not not
732 * supported for this memory bank, -EEXIST if the target memory bank
733 * does not exist or is not controllable, or returns 0 upon success.
734 */
735int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
736{
737 u32 m;
738
739 if (!pwrdm)
740 return -EINVAL;
741
742 if (pwrdm->banks < (bank + 1))
743 return -EEXIST;
744
745 if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst)))
746 return -EINVAL;
747
748 pr_debug("powerdomain: setting next memory powerstate for domain %s "
749 "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst);
750
751 /*
752 * The register bit names below may not correspond to the
753 * actual names of the bits in each powerdomain's register,
754 * but the type of value returned is the same for each
755 * powerdomain.
756 */
757 switch (bank) {
758 case 0:
759 m = OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK;
760 break;
761 case 1:
762 m = OMAP3430_L1FLATMEMONSTATE_MASK;
763 break;
764 case 2:
765 m = OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK;
766 break;
767 case 3:
768 m = OMAP3430_L2FLATMEMONSTATE_MASK;
769 break;
770 default:
771 WARN_ON(1); /* should never happen */
772 return -EEXIST;
773 }
774
775 prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)),
776 pwrdm->prcm_offs, PM_PWSTCTRL);
777
778 return 0;
779}
780
781/**
782 * pwrdm_set_mem_retst - set memory power state while powerdomain in RET
783 * @pwrdm: struct powerdomain * to set
784 * @bank: memory bank number to set (0-3)
785 * @pwrst: one of the PWRDM_POWER_* macros
786 *
787 * Set the next power state that memory bank x of the powerdomain
788 * pwrdm will enter when the powerdomain enters the RETENTION state.
789 * Bank will be a number from 0 to 3, and represents different types
790 * of memory, depending on the powerdomain. pwrst will be either
791 * RETENTION or OFF, if supported. Returns -EINVAL if the powerdomain
792 * pointer is null or the target power state is not not supported for
793 * this memory bank, -EEXIST if the target memory bank does not exist
794 * or is not controllable, or returns 0 upon success.
795 */
796int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
797{
798 u32 m;
799
800 if (!pwrdm)
801 return -EINVAL;
802
803 if (pwrdm->banks < (bank + 1))
804 return -EEXIST;
805
806 if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst)))
807 return -EINVAL;
808
809 pr_debug("powerdomain: setting next memory powerstate for domain %s "
810 "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst);
811
812 /*
813 * The register bit names below may not correspond to the
814 * actual names of the bits in each powerdomain's register,
815 * but the type of value returned is the same for each
816 * powerdomain.
817 */
818 switch (bank) {
819 case 0:
820 m = OMAP3430_SHAREDL1CACHEFLATRETSTATE;
821 break;
822 case 1:
823 m = OMAP3430_L1FLATMEMRETSTATE;
824 break;
825 case 2:
826 m = OMAP3430_SHAREDL2CACHEFLATRETSTATE;
827 break;
828 case 3:
829 m = OMAP3430_L2FLATMEMRETSTATE;
830 break;
831 default:
832 WARN_ON(1); /* should never happen */
833 return -EEXIST;
834 }
835
836 prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
837 PM_PWSTCTRL);
838
839 return 0;
840}
841
842/**
843 * pwrdm_read_logic_pwrst - get current powerdomain logic retention power state
844 * @pwrdm: struct powerdomain * to get current logic retention power state
845 *
846 * Return the current power state that the logic portion of
847 * powerdomain pwrdm will enter
848 * Returns -EINVAL if the powerdomain pointer is null or returns the
849 * current logic retention power state upon success.
850 */
851int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
852{
853 if (!pwrdm)
854 return -EINVAL;
855
856 return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST,
857 OMAP3430_LOGICSTATEST);
858}
859
860/**
861 * pwrdm_read_prev_logic_pwrst - get previous powerdomain logic power state
862 * @pwrdm: struct powerdomain * to get previous logic power state
863 *
864 * Return the powerdomain pwrdm's logic power state. Returns -EINVAL
865 * if the powerdomain pointer is null or returns the previous logic
866 * power state upon success.
867 */
868int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
869{
870 if (!pwrdm)
871 return -EINVAL;
872
873 /*
874 * The register bit names below may not correspond to the
875 * actual names of the bits in each powerdomain's register,
876 * but the type of value returned is the same for each
877 * powerdomain.
878 */
879 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST,
880 OMAP3430_LASTLOGICSTATEENTERED);
881}
882
883/**
884 * pwrdm_read_mem_pwrst - get current memory bank power state
885 * @pwrdm: struct powerdomain * to get current memory bank power state
886 * @bank: memory bank number (0-3)
887 *
888 * Return the powerdomain pwrdm's current memory power state for bank
889 * x. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
890 * the target memory bank does not exist or is not controllable, or
891 * returns the current memory power state upon success.
892 */
893int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
894{
895 u32 m;
896
897 if (!pwrdm)
898 return -EINVAL;
899
900 if (pwrdm->banks < (bank + 1))
901 return -EEXIST;
902
903 /*
904 * The register bit names below may not correspond to the
905 * actual names of the bits in each powerdomain's register,
906 * but the type of value returned is the same for each
907 * powerdomain.
908 */
909 switch (bank) {
910 case 0:
911 m = OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK;
912 break;
913 case 1:
914 m = OMAP3430_L1FLATMEMSTATEST_MASK;
915 break;
916 case 2:
917 m = OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK;
918 break;
919 case 3:
920 m = OMAP3430_L2FLATMEMSTATEST_MASK;
921 break;
922 default:
923 WARN_ON(1); /* should never happen */
924 return -EEXIST;
925 }
926
927 return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, m);
928}
929
930/**
931 * pwrdm_read_prev_mem_pwrst - get previous memory bank power state
932 * @pwrdm: struct powerdomain * to get previous memory bank power state
933 * @bank: memory bank number (0-3)
934 *
935 * Return the powerdomain pwrdm's previous memory power state for bank
936 * x. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
937 * the target memory bank does not exist or is not controllable, or
938 * returns the previous memory power state upon success.
939 */
940int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
941{
942 u32 m;
943
944 if (!pwrdm)
945 return -EINVAL;
946
947 if (pwrdm->banks < (bank + 1))
948 return -EEXIST;
949
950 /*
951 * The register bit names below may not correspond to the
952 * actual names of the bits in each powerdomain's register,
953 * but the type of value returned is the same for each
954 * powerdomain.
955 */
956 switch (bank) {
957 case 0:
958 m = OMAP3430_LASTMEM1STATEENTERED_MASK;
959 break;
960 case 1:
961 m = OMAP3430_LASTMEM2STATEENTERED_MASK;
962 break;
963 case 2:
964 m = OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
965 break;
966 case 3:
967 m = OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
968 break;
969 default:
970 WARN_ON(1); /* should never happen */
971 return -EEXIST;
972 }
973
974 return prm_read_mod_bits_shift(pwrdm->prcm_offs,
975 OMAP3430_PM_PREPWSTST, m);
976}
977
978/**
979 * pwrdm_clear_all_prev_pwrst - clear previous powerstate register for a pwrdm
980 * @pwrdm: struct powerdomain * to clear
981 *
982 * Clear the powerdomain's previous power state register. Clears the
983 * entire register, including logic and memory bank previous power states.
984 * Returns -EINVAL if the powerdomain pointer is null, or returns 0 upon
985 * success.
986 */
987int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
988{
989 if (!pwrdm)
990 return -EINVAL;
991
992 /*
993 * XXX should get the powerdomain's current state here;
994 * warn & fail if it is not ON.
995 */
996
997 pr_debug("powerdomain: clearing previous power state reg for %s\n",
998 pwrdm->name);
999
1000 prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
1001
1002 return 0;
1003}
1004
1005/**
1006 * pwrdm_enable_hdwr_sar - enable automatic hardware SAR for a pwrdm
1007 * @pwrdm: struct powerdomain *
1008 *
1009 * Enable automatic context save-and-restore upon power state change
1010 * for some devices in a powerdomain. Warning: this only affects a
1011 * subset of devices in a powerdomain; check the TRM closely. Returns
1012 * -EINVAL if the powerdomain pointer is null or if the powerdomain
1013 * does not support automatic save-and-restore, or returns 0 upon
1014 * success.
1015 */
1016int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
1017{
1018 if (!pwrdm)
1019 return -EINVAL;
1020
1021 if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
1022 return -EINVAL;
1023
1024 pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
1025 pwrdm->name);
1026
1027 prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
1028 pwrdm->prcm_offs, PM_PWSTCTRL);
1029
1030 return 0;
1031}
1032
1033/**
1034 * pwrdm_disable_hdwr_sar - disable automatic hardware SAR for a pwrdm
1035 * @pwrdm: struct powerdomain *
1036 *
1037 * Disable automatic context save-and-restore upon power state change
1038 * for some devices in a powerdomain. Warning: this only affects a
1039 * subset of devices in a powerdomain; check the TRM closely. Returns
1040 * -EINVAL if the powerdomain pointer is null or if the powerdomain
1041 * does not support automatic save-and-restore, or returns 0 upon
1042 * success.
1043 */
1044int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
1045{
1046 if (!pwrdm)
1047 return -EINVAL;
1048
1049 if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
1050 return -EINVAL;
1051
1052 pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
1053 pwrdm->name);
1054
1055 prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0,
1056 pwrdm->prcm_offs, PM_PWSTCTRL);
1057
1058 return 0;
1059}
1060
1061/**
1062 * pwrdm_has_hdwr_sar - test whether powerdomain supports hardware SAR
1063 * @pwrdm: struct powerdomain *
1064 *
1065 * Returns 1 if powerdomain 'pwrdm' supports hardware save-and-restore
1066 * for some devices, or 0 if it does not.
1067 */
1068bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
1069{
1070 return (pwrdm && pwrdm->flags & PWRDM_HAS_HDWR_SAR) ? 1 : 0;
1071}
1072
1073/**
1074 * pwrdm_wait_transition - wait for powerdomain power transition to finish
1075 * @pwrdm: struct powerdomain * to wait for
1076 *
1077 * If the powerdomain pwrdm is in the process of a state transition,
1078 * spin until it completes the power transition, or until an iteration
1079 * bailout value is reached. Returns -EINVAL if the powerdomain
1080 * pointer is null, -EAGAIN if the bailout value was reached, or
1081 * returns 0 upon success.
1082 */
1083int pwrdm_wait_transition(struct powerdomain *pwrdm)
1084{
1085 u32 c = 0;
1086
1087 if (!pwrdm)
1088 return -EINVAL;
1089
1090 /*
1091 * REVISIT: pwrdm_wait_transition() may be better implemented
1092 * via a callback and a periodic timer check -- how long do we expect
1093 * powerdomain transitions to take?
1094 */
1095
1096 /* XXX Is this udelay() value meaningful? */
1097 while ((prm_read_mod_reg(pwrdm->prcm_offs, PM_PWSTST) &
1098 OMAP_INTRANSITION) &&
1099 (c++ < PWRDM_TRANSITION_BAILOUT))
1100 udelay(1);
1101
1102 if (c >= PWRDM_TRANSITION_BAILOUT) {
1103 printk(KERN_ERR "powerdomain: waited too long for "
1104 "powerdomain %s to complete transition\n", pwrdm->name);
1105 return -EAGAIN;
1106 }
1107
1108 pr_debug("powerdomain: completed transition in %d loops\n", c);
1109
1110 return 0;
1111}
1112
1113
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h
new file mode 100644
index 000000000000..1e151faebbd3
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains.h
@@ -0,0 +1,187 @@
1/*
2 * OMAP2/3 common powerdomain definitions
3 *
4 * Copyright (C) 2007-8 Texas Instruments, Inc.
5 * Copyright (C) 2007-8 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Debugging and integration fixes by Jouni Högander
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS
16#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS
17
18/*
19 * This file contains all of the powerdomains that have some element
20 * of software control for the OMAP24xx and OMAP34XX chips.
21 *
22 * A few notes:
23 *
24 * This is not an exhaustive listing of powerdomains on the chips; only
25 * powerdomains that can be controlled in software.
26 *
27 * A useful validation rule for struct powerdomain:
28 * Any powerdomain referenced by a wkdep_srcs or sleepdep_srcs array
29 * must have a dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really
30 * just software-controllable dependencies. Non-software-controllable
31 * dependencies do exist, but they are not encoded below (yet).
32 *
33 * 24xx does not support programmable sleep dependencies (SLEEPDEP)
34 *
35 */
36
37/*
38 * The names for the DSP/IVA2 powerdomains are confusing.
39 *
40 * Most OMAP chips have an on-board DSP.
41 *
42 * On the 2420, this is a 'C55 DSP called, simply, the DSP. Its
43 * powerdomain is called the "DSP power domain." On the 2430, the
44 * on-board DSP is a 'C64 DSP, now called the IVA2 or IVA2.1. Its
45 * powerdomain is still called the "DSP power domain." On the 3430,
46 * the DSP is a 'C64 DSP like the 2430, also known as the IVA2; but
47 * its powerdomain is now called the "IVA2 power domain."
48 *
49 * The 2420 also has something called the IVA, which is a separate ARM
50 * core, and has nothing to do with the DSP/IVA2.
51 *
52 * Ideally the DSP/IVA2 could just be the same powerdomain, but the PRCM
53 * address offset is different between the C55 and C64 DSPs.
54 *
55 * The overly-specific dep_bit names are due to a bit name collision
56 * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
57 * value are the same for all powerdomains: 2
58 */
59
60/*
61 * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
62 * sanity check?
63 * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
64 */
65
66#include <mach/powerdomain.h>
67
68#include "prcm-common.h"
69#include "prm.h"
70#include "cm.h"
71
72/* OMAP2/3-common powerdomains and wakeup dependencies */
73
74/*
75 * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
76 * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
77 * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
78 */
79static struct pwrdm_dep gfx_sgx_wkdeps[] = {
80 {
81 .pwrdm_name = "core_pwrdm",
82 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
83 },
84 {
85 .pwrdm_name = "iva2_pwrdm",
86 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
87 },
88 {
89 .pwrdm_name = "mpu_pwrdm",
90 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
91 CHIP_IS_OMAP3430)
92 },
93 {
94 .pwrdm_name = "wkup_pwrdm",
95 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
96 CHIP_IS_OMAP3430)
97 },
98 { NULL },
99};
100
101/*
102 * 3430: CM_SLEEPDEP_CAM: MPU
103 * 3430ES1: CM_SLEEPDEP_GFX: MPU
104 * 3430ES2: CM_SLEEPDEP_SGX: MPU
105 */
106static struct pwrdm_dep cam_gfx_sleepdeps[] = {
107 {
108 .pwrdm_name = "mpu_pwrdm",
109 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
110 },
111 { NULL },
112};
113
114
115#include "powerdomains24xx.h"
116#include "powerdomains34xx.h"
117
118
119/*
120 * OMAP2/3 common powerdomains
121 */
122
123/*
124 * The GFX powerdomain is not present on 3430ES2, but currently we do not
125 * have a macro to filter it out at compile-time.
126 */
127static struct powerdomain gfx_pwrdm = {
128 .name = "gfx_pwrdm",
129 .prcm_offs = GFX_MOD,
130 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
131 CHIP_IS_OMAP3430ES1),
132 .wkdep_srcs = gfx_sgx_wkdeps,
133 .sleepdep_srcs = cam_gfx_sleepdeps,
134 .pwrsts = PWRSTS_OFF_RET_ON,
135 .pwrsts_logic_ret = PWRDM_POWER_RET,
136 .banks = 1,
137 .pwrsts_mem_ret = {
138 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
139 },
140 .pwrsts_mem_on = {
141 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
142 },
143};
144
145static struct powerdomain wkup_pwrdm = {
146 .name = "wkup_pwrdm",
147 .prcm_offs = WKUP_MOD,
148 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
149 .dep_bit = OMAP_EN_WKUP_SHIFT,
150};
151
152
153
154/* As powerdomains are added or removed above, this list must also be changed */
155static struct powerdomain *powerdomains_omap[] __initdata = {
156
157 &gfx_pwrdm,
158 &wkup_pwrdm,
159
160#ifdef CONFIG_ARCH_OMAP24XX
161 &dsp_pwrdm,
162 &mpu_24xx_pwrdm,
163 &core_24xx_pwrdm,
164#endif
165
166#ifdef CONFIG_ARCH_OMAP2430
167 &mdm_pwrdm,
168#endif
169
170#ifdef CONFIG_ARCH_OMAP34XX
171 &iva2_pwrdm,
172 &mpu_34xx_pwrdm,
173 &neon_pwrdm,
174 &core_34xx_pwrdm,
175 &cam_pwrdm,
176 &dss_pwrdm,
177 &per_pwrdm,
178 &emu_pwrdm,
179 &sgx_pwrdm,
180 &usbhost_pwrdm,
181#endif
182
183 NULL
184};
185
186
187#endif
diff --git a/arch/arm/mach-omap2/powerdomains24xx.h b/arch/arm/mach-omap2/powerdomains24xx.h
new file mode 100644
index 000000000000..9f08dc3f7fd2
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains24xx.h
@@ -0,0 +1,200 @@
1/*
2 * OMAP24XX powerdomain definitions
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Debugging and integration fixes by Jouni Högander
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX
16#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX
17
18/*
19 * N.B. If powerdomains are added or removed from this file, update
20 * the array in mach-omap2/powerdomains.h.
21 */
22
23#include <mach/powerdomain.h>
24
25#include "prcm-common.h"
26#include "prm.h"
27#include "prm-regbits-24xx.h"
28#include "cm.h"
29#include "cm-regbits-24xx.h"
30
31/* 24XX powerdomains and dependencies */
32
33#ifdef CONFIG_ARCH_OMAP24XX
34
35
36/* Wakeup dependency source arrays */
37
38/*
39 * 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP
40 * 2430 PM_WKDEP_MDM: same as above
41 */
42static struct pwrdm_dep dsp_mdm_24xx_wkdeps[] = {
43 {
44 .pwrdm_name = "core_pwrdm",
45 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
46 },
47 {
48 .pwrdm_name = "mpu_pwrdm",
49 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
50 },
51 {
52 .pwrdm_name = "wkup_pwrdm",
53 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
54 },
55 { NULL },
56};
57
58/*
59 * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
60 * 2430 adds MDM
61 */
62static struct pwrdm_dep mpu_24xx_wkdeps[] = {
63 {
64 .pwrdm_name = "core_pwrdm",
65 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
66 },
67 {
68 .pwrdm_name = "dsp_pwrdm",
69 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
70 },
71 {
72 .pwrdm_name = "wkup_pwrdm",
73 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
74 },
75 {
76 .pwrdm_name = "mdm_pwrdm",
77 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
78 },
79 { NULL },
80};
81
82/*
83 * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
84 * 2430 adds MDM
85 */
86static struct pwrdm_dep core_24xx_wkdeps[] = {
87 {
88 .pwrdm_name = "dsp_pwrdm",
89 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
90 },
91 {
92 .pwrdm_name = "gfx_pwrdm",
93 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
94 },
95 {
96 .pwrdm_name = "mpu_pwrdm",
97 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
98 },
99 {
100 .pwrdm_name = "wkup_pwrdm",
101 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
102 },
103 {
104 .pwrdm_name = "mdm_pwrdm",
105 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
106 },
107 { NULL },
108};
109
110
111/* Powerdomains */
112
113static struct powerdomain dsp_pwrdm = {
114 .name = "dsp_pwrdm",
115 .prcm_offs = OMAP24XX_DSP_MOD,
116 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
117 .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
118 .wkdep_srcs = dsp_mdm_24xx_wkdeps,
119 .pwrsts = PWRSTS_OFF_RET_ON,
120 .pwrsts_logic_ret = PWRDM_POWER_RET,
121 .banks = 1,
122 .pwrsts_mem_ret = {
123 [0] = PWRDM_POWER_RET,
124 },
125 .pwrsts_mem_on = {
126 [0] = PWRDM_POWER_ON,
127 },
128};
129
130static struct powerdomain mpu_24xx_pwrdm = {
131 .name = "mpu_pwrdm",
132 .prcm_offs = MPU_MOD,
133 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
134 .dep_bit = OMAP24XX_EN_MPU_SHIFT,
135 .wkdep_srcs = mpu_24xx_wkdeps,
136 .pwrsts = PWRSTS_OFF_RET_ON,
137 .pwrsts_logic_ret = PWRSTS_OFF_RET,
138 .banks = 1,
139 .pwrsts_mem_ret = {
140 [0] = PWRDM_POWER_RET,
141 },
142 .pwrsts_mem_on = {
143 [0] = PWRDM_POWER_ON,
144 },
145};
146
147static struct powerdomain core_24xx_pwrdm = {
148 .name = "core_pwrdm",
149 .prcm_offs = CORE_MOD,
150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
151 .wkdep_srcs = core_24xx_wkdeps,
152 .pwrsts = PWRSTS_OFF_RET_ON,
153 .dep_bit = OMAP24XX_EN_CORE_SHIFT,
154 .banks = 3,
155 .pwrsts_mem_ret = {
156 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
157 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
158 [2] = PWRSTS_OFF_RET, /* MEM3RETSTATE */
159 },
160 .pwrsts_mem_on = {
161 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
162 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
163 [2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */
164 },
165};
166
167#endif /* CONFIG_ARCH_OMAP24XX */
168
169
170
171/*
172 * 2430-specific powerdomains
173 */
174
175#ifdef CONFIG_ARCH_OMAP2430
176
177/* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */
178
179/* Another case of bit name collisions between several registers: EN_MDM */
180static struct powerdomain mdm_pwrdm = {
181 .name = "mdm_pwrdm",
182 .prcm_offs = OMAP2430_MDM_MOD,
183 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
184 .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
185 .wkdep_srcs = dsp_mdm_24xx_wkdeps,
186 .pwrsts = PWRSTS_OFF_RET_ON,
187 .pwrsts_logic_ret = PWRDM_POWER_RET,
188 .banks = 1,
189 .pwrsts_mem_ret = {
190 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
191 },
192 .pwrsts_mem_on = {
193 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
194 },
195};
196
197#endif /* CONFIG_ARCH_OMAP2430 */
198
199
200#endif
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
new file mode 100644
index 000000000000..f573f7108398
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -0,0 +1,327 @@
1/*
2 * OMAP34XX powerdomain definitions
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Debugging and integration fixes by Jouni Högander
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
16#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
17
18/*
19 * N.B. If powerdomains are added or removed from this file, update
20 * the array in mach-omap2/powerdomains.h.
21 */
22
23#include <mach/powerdomain.h>
24
25#include "prcm-common.h"
26#include "prm.h"
27#include "prm-regbits-34xx.h"
28#include "cm.h"
29#include "cm-regbits-34xx.h"
30
31/*
32 * 34XX-specific powerdomains, dependencies
33 */
34
35#ifdef CONFIG_ARCH_OMAP34XX
36
37/*
38 * 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP
39 * (USBHOST is ES2 only)
40 */
41static struct pwrdm_dep per_usbhost_wkdeps[] = {
42 {
43 .pwrdm_name = "core_pwrdm",
44 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
45 },
46 {
47 .pwrdm_name = "iva2_pwrdm",
48 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
49 },
50 {
51 .pwrdm_name = "mpu_pwrdm",
52 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
53 },
54 {
55 .pwrdm_name = "wkup_pwrdm",
56 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
57 },
58 { NULL },
59};
60
61/*
62 * 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER
63 */
64static struct pwrdm_dep mpu_34xx_wkdeps[] = {
65 {
66 .pwrdm_name = "core_pwrdm",
67 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
68 },
69 {
70 .pwrdm_name = "iva2_pwrdm",
71 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
72 },
73 {
74 .pwrdm_name = "dss_pwrdm",
75 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
76 },
77 {
78 .pwrdm_name = "per_pwrdm",
79 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
80 },
81 { NULL },
82};
83
84/*
85 * 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER
86 */
87static struct pwrdm_dep iva2_wkdeps[] = {
88 {
89 .pwrdm_name = "core_pwrdm",
90 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
91 },
92 {
93 .pwrdm_name = "mpu_pwrdm",
94 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
95 },
96 {
97 .pwrdm_name = "wkup_pwrdm",
98 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
99 },
100 {
101 .pwrdm_name = "dss_pwrdm",
102 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
103 },
104 {
105 .pwrdm_name = "per_pwrdm",
106 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
107 },
108 { NULL },
109};
110
111
112/* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */
113static struct pwrdm_dep cam_dss_wkdeps[] = {
114 {
115 .pwrdm_name = "iva2_pwrdm",
116 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
117 },
118 {
119 .pwrdm_name = "mpu_pwrdm",
120 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
121 },
122 {
123 .pwrdm_name = "wkup_pwrdm",
124 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
125 },
126 { NULL },
127};
128
129/* 3430: PM_WKDEP_NEON: MPU */
130static struct pwrdm_dep neon_wkdeps[] = {
131 {
132 .pwrdm_name = "mpu_pwrdm",
133 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
134 },
135 { NULL },
136};
137
138
139/* Sleep dependency source arrays for 34xx-specific pwrdms - 34XX only */
140
141/*
142 * 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA
143 * 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA
144 */
145static struct pwrdm_dep dss_per_usbhost_sleepdeps[] = {
146 {
147 .pwrdm_name = "mpu_pwrdm",
148 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
149 },
150 {
151 .pwrdm_name = "iva2_pwrdm",
152 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
153 },
154 { NULL },
155};
156
157
158/*
159 * Powerdomains
160 */
161
162static struct powerdomain iva2_pwrdm = {
163 .name = "iva2_pwrdm",
164 .prcm_offs = OMAP3430_IVA2_MOD,
165 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
166 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
167 .wkdep_srcs = iva2_wkdeps,
168 .pwrsts = PWRSTS_OFF_RET_ON,
169 .pwrsts_logic_ret = PWRSTS_OFF_RET,
170 .banks = 4,
171 .pwrsts_mem_ret = {
172 [0] = PWRSTS_OFF_RET,
173 [1] = PWRSTS_OFF_RET,
174 [2] = PWRSTS_OFF_RET,
175 [3] = PWRSTS_OFF_RET,
176 },
177 .pwrsts_mem_on = {
178 [0] = PWRDM_POWER_ON,
179 [1] = PWRDM_POWER_ON,
180 [2] = PWRSTS_OFF_ON,
181 [3] = PWRDM_POWER_ON,
182 },
183};
184
185static struct powerdomain mpu_34xx_pwrdm = {
186 .name = "mpu_pwrdm",
187 .prcm_offs = MPU_MOD,
188 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
189 .dep_bit = OMAP3430_EN_MPU_SHIFT,
190 .wkdep_srcs = mpu_34xx_wkdeps,
191 .pwrsts = PWRSTS_OFF_RET_ON,
192 .pwrsts_logic_ret = PWRSTS_OFF_RET,
193 .banks = 1,
194 .pwrsts_mem_ret = {
195 [0] = PWRSTS_OFF_RET,
196 },
197 .pwrsts_mem_on = {
198 [0] = PWRSTS_OFF_ON,
199 },
200};
201
202/* No wkdeps or sleepdeps for 34xx core apparently */
203static struct powerdomain core_34xx_pwrdm = {
204 .name = "core_pwrdm",
205 .prcm_offs = CORE_MOD,
206 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
207 .pwrsts = PWRSTS_OFF_RET_ON,
208 .dep_bit = OMAP3430_EN_CORE_SHIFT,
209 .banks = 2,
210 .pwrsts_mem_ret = {
211 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
212 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
213 },
214 .pwrsts_mem_on = {
215 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
216 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
217 },
218};
219
220/* Another case of bit name collisions between several registers: EN_DSS */
221static struct powerdomain dss_pwrdm = {
222 .name = "dss_pwrdm",
223 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
224 .prcm_offs = OMAP3430_DSS_MOD,
225 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
226 .wkdep_srcs = cam_dss_wkdeps,
227 .sleepdep_srcs = dss_per_usbhost_sleepdeps,
228 .pwrsts = PWRSTS_OFF_RET_ON,
229 .pwrsts_logic_ret = PWRDM_POWER_RET,
230 .banks = 1,
231 .pwrsts_mem_ret = {
232 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
233 },
234 .pwrsts_mem_on = {
235 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
236 },
237};
238
239static struct powerdomain sgx_pwrdm = {
240 .name = "sgx_pwrdm",
241 .prcm_offs = OMAP3430ES2_SGX_MOD,
242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
243 .wkdep_srcs = gfx_sgx_wkdeps,
244 .sleepdep_srcs = cam_gfx_sleepdeps,
245 /* XXX This is accurate for 3430 SGX, but what about GFX? */
246 .pwrsts = PWRSTS_OFF_RET_ON,
247 .pwrsts_logic_ret = PWRDM_POWER_RET,
248 .banks = 1,
249 .pwrsts_mem_ret = {
250 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
251 },
252 .pwrsts_mem_on = {
253 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
254 },
255};
256
257static struct powerdomain cam_pwrdm = {
258 .name = "cam_pwrdm",
259 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
260 .prcm_offs = OMAP3430_CAM_MOD,
261 .wkdep_srcs = cam_dss_wkdeps,
262 .sleepdep_srcs = cam_gfx_sleepdeps,
263 .pwrsts = PWRSTS_OFF_RET_ON,
264 .pwrsts_logic_ret = PWRDM_POWER_RET,
265 .banks = 1,
266 .pwrsts_mem_ret = {
267 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
268 },
269 .pwrsts_mem_on = {
270 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
271 },
272};
273
274static struct powerdomain per_pwrdm = {
275 .name = "per_pwrdm",
276 .prcm_offs = OMAP3430_PER_MOD,
277 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
278 .dep_bit = OMAP3430_EN_PER_SHIFT,
279 .wkdep_srcs = per_usbhost_wkdeps,
280 .sleepdep_srcs = dss_per_usbhost_sleepdeps,
281 .pwrsts = PWRSTS_OFF_RET_ON,
282 .pwrsts_logic_ret = PWRSTS_OFF_RET,
283 .banks = 1,
284 .pwrsts_mem_ret = {
285 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
286 },
287 .pwrsts_mem_on = {
288 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
289 },
290};
291
292static struct powerdomain emu_pwrdm = {
293 .name = "emu_pwrdm",
294 .prcm_offs = OMAP3430_EMU_MOD,
295 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
296};
297
298static struct powerdomain neon_pwrdm = {
299 .name = "neon_pwrdm",
300 .prcm_offs = OMAP3430_NEON_MOD,
301 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
302 .wkdep_srcs = neon_wkdeps,
303 .pwrsts = PWRSTS_OFF_RET_ON,
304 .pwrsts_logic_ret = PWRDM_POWER_RET,
305};
306
307static struct powerdomain usbhost_pwrdm = {
308 .name = "usbhost_pwrdm",
309 .prcm_offs = OMAP3430ES2_USBHOST_MOD,
310 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
311 .wkdep_srcs = per_usbhost_wkdeps,
312 .sleepdep_srcs = dss_per_usbhost_sleepdeps,
313 .pwrsts = PWRSTS_OFF_RET_ON,
314 .pwrsts_logic_ret = PWRDM_POWER_RET,
315 .banks = 1,
316 .pwrsts_mem_ret = {
317 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
318 },
319 .pwrsts_mem_on = {
320 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
321 },
322};
323
324#endif /* CONFIG_ARCH_OMAP34XX */
325
326
327#endif
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 54c32f482131..4a32822ff3fc 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -312,7 +312,8 @@
312#define OMAP3430_ST_GPT2 (1 << 3) 312#define OMAP3430_ST_GPT2 (1 << 3)
313 313
314/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ 314/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
315#define OMAP3430_EN_CORE (1 << 0) 315#define OMAP3430_EN_CORE_SHIFT 0
316#define OMAP3430_EN_CORE_MASK (1 << 0)
316 317
317#endif 318#endif
318 319
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index c6d17a3378ec..4002051c20b9 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -29,8 +29,10 @@
29#define OMAP24XX_WKUP1_EN (1 << 0) 29#define OMAP24XX_WKUP1_EN (1 << 0)
30 30
31/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */ 31/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
32#define OMAP24XX_EN_MPU (1 << 1) 32#define OMAP24XX_EN_MPU_SHIFT 1
33#define OMAP24XX_EN_CORE (1 << 0) 33#define OMAP24XX_EN_MPU_MASK (1 << 1)
34#define OMAP24XX_EN_CORE_SHIFT 0
35#define OMAP24XX_EN_CORE_MASK (1 << 0)
34 36
35/* 37/*
36 * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM 38 * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
@@ -140,8 +142,10 @@
140/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */ 142/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
141 143
142/* PM_WKDEP_MPU specific bits */ 144/* PM_WKDEP_MPU specific bits */
143#define OMAP2430_PM_WKDEP_MPU_EN_MDM (1 << 5) 145#define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5
144#define OMAP24XX_PM_WKDEP_MPU_EN_DSP (1 << 2) 146#define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK (1 << 5)
147#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2
148#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK (1 << 2)
145 149
146/* PM_EVGENCTRL_MPU specific bits */ 150/* PM_EVGENCTRL_MPU specific bits */
147 151
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index b4686bc345ca..5b5ecfe6c999 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -68,7 +68,8 @@
68#define OMAP3430_VPINIDLE (1 << 0) 68#define OMAP3430_VPINIDLE (1 << 0)
69 69
70/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ 70/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
71#define OMAP3430_EN_PER (1 << 7) 71#define OMAP3430_EN_PER_SHIFT 7
72#define OMAP3430_EN_PER_MASK (1 << 7)
72 73
73/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ 74/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
74#define OMAP3430_MEMORYCHANGE (1 << 3) 75#define OMAP3430_MEMORYCHANGE (1 << 3)
@@ -77,7 +78,7 @@
77#define OMAP3430_LOGICSTATEST (1 << 2) 78#define OMAP3430_LOGICSTATEST (1 << 2)
78 79
79/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ 80/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
80#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2) 81#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2)
81 82
82/* 83/*
83 * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, 84 * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
@@ -278,8 +279,10 @@
278#define OMAP3430_EMULATION_MPU_RST (1 << 11) 279#define OMAP3430_EMULATION_MPU_RST (1 << 11)
279 280
280/* PM_WKDEP_MPU specific bits */ 281/* PM_WKDEP_MPU specific bits */
281#define OMAP3430_PM_WKDEP_MPU_EN_DSS (1 << 5) 282#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5
282#define OMAP3430_PM_WKDEP_MPU_EN_IVA2 (1 << 2) 283#define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5)
284#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2
285#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2)
283 286
284/* PM_EVGENCTRL_MPU */ 287/* PM_EVGENCTRL_MPU */
285#define OMAP3430_OFFLOADMODE_SHIFT 3 288#define OMAP3430_OFFLOADMODE_SHIFT 3
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index bbf41fc8e9a9..e4dc4b17881d 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -18,7 +18,7 @@
18 18
19#ifndef __ASSEMBLER__ 19#ifndef __ASSEMBLER__
20#define OMAP_PRM_REGADDR(module, reg) \ 20#define OMAP_PRM_REGADDR(module, reg) \
21 (void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg)) 21 IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
22#else 22#else
23#define OMAP2420_PRM_REGADDR(module, reg) \ 23#define OMAP2420_PRM_REGADDR(module, reg) \
24 IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) 24 IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
@@ -305,7 +305,8 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
305 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, 305 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
306 * PM_WKDEP_PER 306 * PM_WKDEP_PER
307 */ 307 */
308#define OMAP_EN_WKUP (1 << 4) 308#define OMAP_EN_WKUP_SHIFT 4
309#define OMAP_EN_WKUP_MASK (1 << 4)
309 310
310/* 311/*
311 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, 312 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 7d9444adc5df..4dcf39c285b9 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * OMAP2 serial support. 4 * OMAP2 serial support.
5 * 5 *
6 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com> 7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 * 8 *
9 * Based off of arch/arm/mach-omap/omap1/serial.c 9 * Based off of arch/arm/mach-omap/omap1/serial.c
@@ -22,38 +22,34 @@
22#include <mach/common.h> 22#include <mach/common.h>
23#include <mach/board.h> 23#include <mach/board.h>
24 24
25static struct clk * uart1_ick = NULL; 25static struct clk *uart_ick[OMAP_MAX_NR_PORTS];
26static struct clk * uart1_fck = NULL; 26static struct clk *uart_fck[OMAP_MAX_NR_PORTS];
27static struct clk * uart2_ick = NULL;
28static struct clk * uart2_fck = NULL;
29static struct clk * uart3_ick = NULL;
30static struct clk * uart3_fck = NULL;
31 27
32static struct plat_serial8250_port serial_platform_data[] = { 28static struct plat_serial8250_port serial_platform_data[] = {
33 { 29 {
34 .membase = (char *)IO_ADDRESS(OMAP_UART1_BASE), 30 .membase = IO_ADDRESS(OMAP_UART1_BASE),
35 .mapbase = (unsigned long)OMAP_UART1_BASE, 31 .mapbase = OMAP_UART1_BASE,
36 .irq = 72, 32 .irq = 72,
37 .flags = UPF_BOOT_AUTOCONF, 33 .flags = UPF_BOOT_AUTOCONF,
38 .iotype = UPIO_MEM, 34 .iotype = UPIO_MEM,
39 .regshift = 2, 35 .regshift = 2,
40 .uartclk = OMAP16XX_BASE_BAUD * 16, 36 .uartclk = OMAP24XX_BASE_BAUD * 16,
41 }, { 37 }, {
42 .membase = (char *)IO_ADDRESS(OMAP_UART2_BASE), 38 .membase = IO_ADDRESS(OMAP_UART2_BASE),
43 .mapbase = (unsigned long)OMAP_UART2_BASE, 39 .mapbase = OMAP_UART2_BASE,
44 .irq = 73, 40 .irq = 73,
45 .flags = UPF_BOOT_AUTOCONF, 41 .flags = UPF_BOOT_AUTOCONF,
46 .iotype = UPIO_MEM, 42 .iotype = UPIO_MEM,
47 .regshift = 2, 43 .regshift = 2,
48 .uartclk = OMAP16XX_BASE_BAUD * 16, 44 .uartclk = OMAP24XX_BASE_BAUD * 16,
49 }, { 45 }, {
50 .membase = (char *)IO_ADDRESS(OMAP_UART3_BASE), 46 .membase = IO_ADDRESS(OMAP_UART3_BASE),
51 .mapbase = (unsigned long)OMAP_UART3_BASE, 47 .mapbase = OMAP_UART3_BASE,
52 .irq = 74, 48 .irq = 74,
53 .flags = UPF_BOOT_AUTOCONF, 49 .flags = UPF_BOOT_AUTOCONF,
54 .iotype = UPIO_MEM, 50 .iotype = UPIO_MEM,
55 .regshift = 2, 51 .regshift = 2,
56 .uartclk = OMAP16XX_BASE_BAUD * 16, 52 .uartclk = OMAP24XX_BASE_BAUD * 16,
57 }, { 53 }, {
58 .flags = 0 54 .flags = 0
59 } 55 }
@@ -70,7 +66,7 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
70 int value) 66 int value)
71{ 67{
72 offset <<= p->regshift; 68 offset <<= p->regshift;
73 __raw_writeb(value, (unsigned long)(p->membase + offset)); 69 __raw_writeb(value, p->membase + offset);
74} 70}
75 71
76/* 72/*
@@ -86,10 +82,27 @@ static inline void __init omap_serial_reset(struct plat_serial8250_port *p)
86 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0)); 82 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
87} 83}
88 84
89void __init omap_serial_init() 85void omap_serial_enable_clocks(int enable)
86{
87 int i;
88 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
89 if (uart_ick[i] && uart_fck[i]) {
90 if (enable) {
91 clk_enable(uart_ick[i]);
92 clk_enable(uart_fck[i]);
93 } else {
94 clk_disable(uart_ick[i]);
95 clk_disable(uart_fck[i]);
96 }
97 }
98 }
99}
100
101void __init omap_serial_init(void)
90{ 102{
91 int i; 103 int i;
92 const struct omap_uart_config *info; 104 const struct omap_uart_config *info;
105 char name[16];
93 106
94 /* 107 /*
95 * Make sure the serial ports are muxed on at this point. 108 * Make sure the serial ports are muxed on at this point.
@@ -97,8 +110,7 @@ void __init omap_serial_init()
97 * if not needed. 110 * if not needed.
98 */ 111 */
99 112
100 info = omap_get_config(OMAP_TAG_UART, 113 info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
101 struct omap_uart_config);
102 114
103 if (info == NULL) 115 if (info == NULL)
104 return; 116 return;
@@ -107,58 +119,26 @@ void __init omap_serial_init()
107 struct plat_serial8250_port *p = serial_platform_data + i; 119 struct plat_serial8250_port *p = serial_platform_data + i;
108 120
109 if (!(info->enabled_uarts & (1 << i))) { 121 if (!(info->enabled_uarts & (1 << i))) {
110 p->membase = 0; 122 p->membase = NULL;
111 p->mapbase = 0; 123 p->mapbase = 0;
112 continue; 124 continue;
113 } 125 }
114 126
115 switch (i) { 127 sprintf(name, "uart%d_ick", i+1);
116 case 0: 128 uart_ick[i] = clk_get(NULL, name);
117 uart1_ick = clk_get(NULL, "uart1_ick"); 129 if (IS_ERR(uart_ick[i])) {
118 if (IS_ERR(uart1_ick)) 130 printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
119 printk("Could not get uart1_ick\n"); 131 uart_ick[i] = NULL;
120 else { 132 } else
121 clk_enable(uart1_ick); 133 clk_enable(uart_ick[i]);
122 } 134
123 135 sprintf(name, "uart%d_fck", i+1);
124 uart1_fck = clk_get(NULL, "uart1_fck"); 136 uart_fck[i] = clk_get(NULL, name);
125 if (IS_ERR(uart1_fck)) 137 if (IS_ERR(uart_fck[i])) {
126 printk("Could not get uart1_fck\n"); 138 printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
127 else { 139 uart_fck[i] = NULL;
128 clk_enable(uart1_fck); 140 } else
129 } 141 clk_enable(uart_fck[i]);
130 break;
131 case 1:
132 uart2_ick = clk_get(NULL, "uart2_ick");
133 if (IS_ERR(uart2_ick))
134 printk("Could not get uart2_ick\n");
135 else {
136 clk_enable(uart2_ick);
137 }
138
139 uart2_fck = clk_get(NULL, "uart2_fck");
140 if (IS_ERR(uart2_fck))
141 printk("Could not get uart2_fck\n");
142 else {
143 clk_enable(uart2_fck);
144 }
145 break;
146 case 2:
147 uart3_ick = clk_get(NULL, "uart3_ick");
148 if (IS_ERR(uart3_ick))
149 printk("Could not get uart3_ick\n");
150 else {
151 clk_enable(uart3_ick);
152 }
153
154 uart3_fck = clk_get(NULL, "uart3_fck");
155 if (IS_ERR(uart3_fck))
156 printk("Could not get uart3_fck\n");
157 else {
158 clk_enable(uart3_fck);
159 }
160 break;
161 }
162 142
163 omap_serial_reset(p); 143 omap_serial_reset(p);
164 } 144 }
diff --git a/arch/arm/mach-omap2/sleep.S b/arch/arm/mach-omap2/sleep24xx.S
index 87a706fd5f82..43336b93b21c 100644
--- a/arch/arm/mach-omap2/sleep.S
+++ b/arch/arm/mach-omap2/sleep24xx.S
@@ -5,6 +5,10 @@
5 * Texas Instruments, <www.ti.com> 5 * Texas Instruments, <www.ti.com>
6 * Richard Woodruff <r-woodruff2@ti.com> 6 * Richard Woodruff <r-woodruff2@ti.com>
7 * 7 *
8 * (C) Copyright 2006 Nokia Corporation
9 * Fixed idle loop sleep
10 * Igor Stoppa <igor.stoppa@nokia.com>
11 *
8 * This program is free software; you can redistribute it and/or 12 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 13 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 14 * published by the Free Software Foundation; either version 2 of
@@ -26,6 +30,8 @@
26#include <mach/io.h> 30#include <mach/io.h>
27#include <mach/pm.h> 31#include <mach/pm.h>
28 32
33#include <mach/omap24xx.h>
34
29#include "sdrc.h" 35#include "sdrc.h"
30 36
31/* First address of reserved address space? apparently valid for OMAP2 & 3 */ 37/* First address of reserved address space? apparently valid for OMAP2 & 3 */
@@ -52,15 +58,14 @@ ENTRY(omap24xx_idle_loop_suspend_sz)
52 .word . - omap24xx_idle_loop_suspend 58 .word . - omap24xx_idle_loop_suspend
53 59
54/* 60/*
55 * omap242x_cpu_suspend() - Forces OMAP into deep sleep state by completing 61 * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
56 * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore 62 * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
57 * SDRC. 63 * SDRC.
58 * 64 *
59 * Input: 65 * Input:
60 * R0 : DLL ctrl value pre-Sleep 66 * R0 : DLL ctrl value pre-Sleep
61 * R1 : Processor+Revision 67 * R1 : SDRC_DLLA_CTRL
62 * 2420: 0x21 = 242xES1, 0x26 = 242xES2.2 68 * R2 : SDRC_POWER
63 * 2430: 0x31 = 2430ES1, 0x32 = 2430ES2
64 * 69 *
65 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on 70 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
66 * when we get called, but the DLL probably isn't. We will wait a bit more in 71 * when we get called, but the DLL probably isn't. We will wait a bit more in
@@ -80,15 +85,14 @@ ENTRY(omap24xx_idle_loop_suspend_sz)
80 */ 85 */
81ENTRY(omap24xx_cpu_suspend) 86ENTRY(omap24xx_cpu_suspend)
82 stmfd sp!, {r0 - r12, lr} @ save registers on stack 87 stmfd sp!, {r0 - r12, lr} @ save registers on stack
83 mov r3, #0x0 @ clear for mrc call 88 mov r3, #0x0 @ clear for mcr call
84 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished 89 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
85 nop 90 nop
86 nop 91 nop
87 ldr r3, A_SDRC_POWER @ addr of sdrc power 92 ldr r4, [r2] @ read SDRC_POWER
88 ldr r4, [r3] @ value of sdrc power
89 orr r4, r4, #0x40 @ enable self refresh on idle req 93 orr r4, r4, #0x40 @ enable self refresh on idle req
90 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock) 94 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
91 str r4, [r3] @ make it so 95 str r4, [r2] @ make it so
92 mov r2, #0 96 mov r2, #0
93 nop 97 nop
94 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt 98 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
@@ -97,14 +101,13 @@ loop:
97 subs r5, r5, #0x1 @ awake, wait just a bit 101 subs r5, r5, #0x1 @ awake, wait just a bit
98 bne loop 102 bne loop
99 103
100 /* The DPLL has on before we take the DDR out of self refresh */ 104 /* The DPLL has to be on before we take the DDR out of self refresh */
101 bic r4, r4, #0x40 @ now clear self refresh bit. 105 bic r4, r4, #0x40 @ now clear self refresh bit.
102 str r4, [r3] @ put vlaue back. 106 str r4, [r2] @ write to SDRC_POWER
103 ldr r4, A_SDRC0 @ make a clock happen 107 ldr r4, A_SDRC0 @ make a clock happen
104 ldr r4, [r4] 108 ldr r4, [r4] @ read A_SDRC0
105 nop @ start auto refresh only after clk ok 109 nop @ start auto refresh only after clk ok
106 movs r0, r0 @ see if DDR or SDR 110 movs r0, r0 @ see if DDR or SDR
107 ldrne r1, A_SDRC_DLLA_CTRL_S @ get addr of DLL ctrl
108 strne r0, [r1] @ rewrite DLLA to force DLL reload 111 strne r0, [r1] @ rewrite DLLA to force DLL reload
109 addne r1, r1, #0x8 @ move to DLLB 112 addne r1, r1, #0x8 @ move to DLLB
110 strne r0, [r1] @ rewrite DLLB to force DLL reload 113 strne r0, [r1] @ rewrite DLLB to force DLL reload
@@ -116,13 +119,8 @@ loop2:
116 /* resume*/ 119 /* resume*/
117 ldmfd sp!, {r0 - r12, pc} @ restore regs and return 120 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
118 121
119A_SDRC_POWER:
120 .word OMAP242X_SDRC_REGADDR(SDRC_POWER)
121A_SDRC0: 122A_SDRC0:
122 .word A_SDRC0_V 123 .word A_SDRC0_V
123A_SDRC_DLLA_CTRL_S:
124 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
125 124
126ENTRY(omap24xx_cpu_suspend_sz) 125ENTRY(omap24xx_cpu_suspend_sz)
127 .word . - omap24xx_cpu_suspend 126 .word . - omap24xx_cpu_suspend
128
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
new file mode 100644
index 000000000000..2c7146136342
--- /dev/null
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -0,0 +1,179 @@
1/*
2 * linux/arch/arm/mach-omap3/sram.S
3 *
4 * Omap3 specific functions that need to be run in internal SRAM
5 *
6 * (C) Copyright 2007
7 * Texas Instruments Inc.
8 * Rajendra Nayak <rnayak@ti.com>
9 *
10 * (C) Copyright 2004
11 * Texas Instruments, <www.ti.com>
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29#include <linux/linkage.h>
30#include <asm/assembler.h>
31#include <mach/hardware.h>
32
33#include <mach/io.h>
34
35#include "sdrc.h"
36#include "cm.h"
37
38 .text
39
40/*
41 * Change frequency of core dpll
42 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
43 */
44ENTRY(omap3_sram_configure_core_dpll)
45 stmfd sp!, {r1-r12, lr} @ store regs to stack
46 cmp r3, #0x2
47 blne configure_sdrc
48 cmp r3, #0x2
49 blne lock_dll
50 cmp r3, #0x1
51 blne unlock_dll
52 bl sdram_in_selfrefresh @ put the SDRAM in self refresh
53 bl configure_core_dpll
54 bl enable_sdrc
55 cmp r3, #0x1
56 blne wait_dll_unlock
57 cmp r3, #0x2
58 blne wait_dll_lock
59 cmp r3, #0x1
60 blne configure_sdrc
61 mov r0, #0 @ return value
62 ldmfd sp!, {r1-r12, pc} @ restore regs and return
63unlock_dll:
64 ldr r4, omap3_sdrc_dlla_ctrl
65 ldr r5, [r4]
66 orr r5, r5, #0x4
67 str r5, [r4]
68 bx lr
69lock_dll:
70 ldr r4, omap3_sdrc_dlla_ctrl
71 ldr r5, [r4]
72 bic r5, r5, #0x4
73 str r5, [r4]
74 bx lr
75sdram_in_selfrefresh:
76 mov r5, #0x0 @ Move 0 to R5
77 mcr p15, 0, r5, c7, c10, 5 @ memory barrier
78 ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
79 ldr r5, [r4] @ read the contents of SDRC_POWER
80 orr r5, r5, #0x40 @ enable self refresh on idle req
81 str r5, [r4] @ write back to SDRC_POWER register
82 ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
83 ldr r5, [r4]
84 bic r5, r5, #0x2 @ disable iclk bit for SRDC
85 str r5, [r4]
86wait_sdrc_idle:
87 ldr r4, omap3_cm_idlest1_core
88 ldr r5, [r4]
89 and r5, r5, #0x2 @ check for SDRC idle
90 cmp r5, #2
91 bne wait_sdrc_idle
92 bx lr
93configure_core_dpll:
94 ldr r4, omap3_cm_clksel1_pll
95 ldr r5, [r4]
96 ldr r6, core_m2_mask_val @ modify m2 for core dpll
97 and r5, r5, r6
98 orr r5, r5, r3, lsl #0x1B @ r3 contains the M2 val
99 str r5, [r4]
100 mov r5, #0x800 @ wait for the clock to stabilise
101 cmp r3, #2
102 bne wait_clk_stable
103 bx lr
104wait_clk_stable:
105 subs r5, r5, #1
106 bne wait_clk_stable
107 nop
108 nop
109 nop
110 nop
111 nop
112 nop
113 nop
114 nop
115 nop
116 nop
117 bx lr
118enable_sdrc:
119 ldr r4, omap3_cm_iclken1_core
120 ldr r5, [r4]
121 orr r5, r5, #0x2 @ enable iclk bit for SDRC
122 str r5, [r4]
123wait_sdrc_idle1:
124 ldr r4, omap3_cm_idlest1_core
125 ldr r5, [r4]
126 and r5, r5, #0x2
127 cmp r5, #0
128 bne wait_sdrc_idle1
129 ldr r4, omap3_sdrc_power
130 ldr r5, [r4]
131 bic r5, r5, #0x40
132 str r5, [r4]
133 bx lr
134wait_dll_lock:
135 ldr r4, omap3_sdrc_dlla_status
136 ldr r5, [r4]
137 and r5, r5, #0x4
138 cmp r5, #0x4
139 bne wait_dll_lock
140 bx lr
141wait_dll_unlock:
142 ldr r4, omap3_sdrc_dlla_status
143 ldr r5, [r4]
144 and r5, r5, #0x4
145 cmp r5, #0x0
146 bne wait_dll_unlock
147 bx lr
148configure_sdrc:
149 ldr r4, omap3_sdrc_rfr_ctrl
150 str r0, [r4]
151 ldr r4, omap3_sdrc_actim_ctrla
152 str r1, [r4]
153 ldr r4, omap3_sdrc_actim_ctrlb
154 str r2, [r4]
155 bx lr
156
157omap3_sdrc_power:
158 .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
159omap3_cm_clksel1_pll:
160 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
161omap3_cm_idlest1_core:
162 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
163omap3_cm_iclken1_core:
164 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
165omap3_sdrc_rfr_ctrl:
166 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
167omap3_sdrc_actim_ctrla:
168 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
169omap3_sdrc_actim_ctrlb:
170 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
171omap3_sdrc_dlla_status:
172 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
173omap3_sdrc_dlla_ctrl:
174 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
175core_m2_mask_val:
176 .word 0x07FFFFFF
177
178ENTRY(omap3_sram_configure_core_dpll_sz)
179 .word . - omap3_sram_configure_core_dpll
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index a82dad1a8cc8..df83b97f303f 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -162,7 +162,7 @@ static void __init cmx270_init_rtc(void)
162 platform_device_register(&cmx270_rtc_device); 162 platform_device_register(&cmx270_rtc_device);
163} 163}
164#else 164#else
165static inline void cmx2xx_init_rtc(void) {} 165static inline void cmx270_init_rtc(void) {}
166#endif 166#endif
167 167
168/* 2700G graphics */ 168/* 2700G graphics */
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index d7632f63603c..4b3120dbc049 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -204,25 +204,54 @@ static void viper_set_core_cpu_voltage(unsigned long khz, int force)
204 204
205/* Interrupt handling */ 205/* Interrupt handling */
206static unsigned long viper_irq_enabled_mask; 206static unsigned long viper_irq_enabled_mask;
207static const int viper_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, 9, 14, 15 };
208static const int viper_isa_irq_map[] = {
209 0, /* ISA irq #0, invalid */
210 0, /* ISA irq #1, invalid */
211 0, /* ISA irq #2, invalid */
212 1 << 0, /* ISA irq #3 */
213 1 << 1, /* ISA irq #4 */
214 1 << 2, /* ISA irq #5 */
215 1 << 3, /* ISA irq #6 */
216 1 << 4, /* ISA irq #7 */
217 0, /* ISA irq #8, invalid */
218 1 << 8, /* ISA irq #9 */
219 1 << 5, /* ISA irq #10 */
220 1 << 6, /* ISA irq #11 */
221 1 << 7, /* ISA irq #12 */
222 0, /* ISA irq #13, invalid */
223 1 << 9, /* ISA irq #14 */
224 1 << 10, /* ISA irq #15 */
225};
226
227static inline int viper_irq_to_bitmask(unsigned int irq)
228{
229 return viper_isa_irq_map[irq - PXA_ISA_IRQ(0)];
230}
231
232static inline int viper_bit_to_irq(int bit)
233{
234 return viper_isa_irqs[bit] + PXA_ISA_IRQ(0);
235}
207 236
208static void viper_ack_irq(unsigned int irq) 237static void viper_ack_irq(unsigned int irq)
209{ 238{
210 int viper_irq = irq - PXA_ISA_IRQ(0); 239 int viper_irq = viper_irq_to_bitmask(irq);
211 240
212 if (viper_irq < 8) 241 if (viper_irq & 0xff)
213 VIPER_LO_IRQ_STATUS = 1 << viper_irq; 242 VIPER_LO_IRQ_STATUS = viper_irq;
214 else 243 else
215 VIPER_HI_IRQ_STATUS = 1 << (viper_irq - 8); 244 VIPER_HI_IRQ_STATUS = (viper_irq >> 8);
216} 245}
217 246
218static void viper_mask_irq(unsigned int irq) 247static void viper_mask_irq(unsigned int irq)
219{ 248{
220 viper_irq_enabled_mask &= ~(1 << (irq - PXA_ISA_IRQ(0))); 249 viper_irq_enabled_mask &= ~(viper_irq_to_bitmask(irq));
221} 250}
222 251
223static void viper_unmask_irq(unsigned int irq) 252static void viper_unmask_irq(unsigned int irq)
224{ 253{
225 viper_irq_enabled_mask |= (1 << (irq - PXA_ISA_IRQ(0))); 254 viper_irq_enabled_mask |= viper_irq_to_bitmask(irq);
226} 255}
227 256
228static inline unsigned long viper_irq_pending(void) 257static inline unsigned long viper_irq_pending(void)
@@ -237,8 +266,12 @@ static void viper_irq_handler(unsigned int irq, struct irq_desc *desc)
237 266
238 pending = viper_irq_pending(); 267 pending = viper_irq_pending();
239 do { 268 do {
269 /* we're in a chained irq handler,
270 * so ack the interrupt by hand */
271 GEDR(VIPER_CPLD_GPIO) = GPIO_bit(VIPER_CPLD_GPIO);
272
240 if (likely(pending)) { 273 if (likely(pending)) {
241 irq = PXA_ISA_IRQ(0) + __ffs(pending); 274 irq = viper_bit_to_irq(__ffs(pending));
242 generic_handle_irq(irq); 275 generic_handle_irq(irq);
243 } 276 }
244 pending = viper_irq_pending(); 277 pending = viper_irq_pending();
@@ -254,15 +287,14 @@ static struct irq_chip viper_irq_chip = {
254 287
255static void __init viper_init_irq(void) 288static void __init viper_init_irq(void)
256{ 289{
257 const int isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, 9, 14, 15 }; 290 int level;
258 int irq;
259 int isa_irq; 291 int isa_irq;
260 292
261 pxa25x_init_irq(); 293 pxa25x_init_irq();
262 294
263 /* setup ISA IRQs */ 295 /* setup ISA IRQs */
264 for (irq = 0; irq < ARRAY_SIZE(isa_irqs); irq++) { 296 for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) {
265 isa_irq = isa_irqs[irq]; 297 isa_irq = viper_bit_to_irq(level);
266 set_irq_chip(isa_irq, &viper_irq_chip); 298 set_irq_chip(isa_irq, &viper_irq_chip);
267 set_irq_handler(isa_irq, handle_edge_irq); 299 set_irq_handler(isa_irq, handle_edge_irq);
268 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); 300 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 75738000272b..9a37c87152b0 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -38,7 +38,7 @@
38#include <mach/bast-map.h> 38#include <mach/bast-map.h>
39#include <mach/bast-irq.h> 39#include <mach/bast-irq.h>
40 40
41#include <asm/plat-s3c24xx/irq.h> 41#include <plat/irq.h>
42 42
43#if 0 43#if 0
44#include <asm/debug-ll.h> 44#include <asm/debug-ll.h>
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
index fef646c36b54..4e07943c1e29 100644
--- a/arch/arm/mach-s3c2410/clock.c
+++ b/arch/arm/mach-s3c2410/clock.c
@@ -37,13 +37,13 @@
37 37
38#include <mach/hardware.h> 38#include <mach/hardware.h>
39 39
40#include <asm/plat-s3c/regs-serial.h> 40#include <plat/regs-serial.h>
41#include <mach/regs-clock.h> 41#include <mach/regs-clock.h>
42#include <mach/regs-gpio.h> 42#include <mach/regs-gpio.h>
43 43
44#include <asm/plat-s3c24xx/s3c2410.h> 44#include <plat/s3c2410.h>
45#include <asm/plat-s3c24xx/clock.h> 45#include <plat/clock.h>
46#include <asm/plat-s3c24xx/cpu.h> 46#include <plat/cpu.h>
47 47
48int s3c2410_clkcon_enable(struct clk *clk, int enable) 48int s3c2410_clkcon_enable(struct clk *clk, int enable)
49{ 49{
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 8730797749e3..7d914a470b6c 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -20,10 +20,10 @@
20#include <asm/dma.h> 20#include <asm/dma.h>
21#include <mach/dma.h> 21#include <mach/dma.h>
22 22
23#include <asm/plat-s3c24xx/cpu.h> 23#include <plat/cpu.h>
24#include <asm/plat-s3c24xx/dma.h> 24#include <plat/dma.h>
25 25
26#include <asm/plat-s3c/regs-serial.h> 26#include <plat/regs-serial.h>
27#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
28#include <asm/plat-s3c/regs-ac97.h> 28#include <asm/plat-s3c/regs-ac97.h>
29#include <mach/regs-mem.h> 29#include <mach/regs-mem.h>
diff --git a/arch/arm/mach-s3c2410/include/mach/debug-macro.S b/arch/arm/mach-s3c2410/include/mach/debug-macro.S
index 682df23087ab..4c29a89ad077 100644
--- a/arch/arm/mach-s3c2410/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c2410/include/mach/debug-macro.S
@@ -14,7 +14,7 @@
14 14
15#include <mach/map.h> 15#include <mach/map.h>
16#include <mach/regs-gpio.h> 16#include <mach/regs-gpio.h>
17#include <asm/plat-s3c/regs-serial.h> 17#include <plat/regs-serial.h>
18 18
19#define S3C2410_UART1_OFF (0x4000) 19#define S3C2410_UART1_OFF (0x4000)
20#define SHIFT_2440TXF (14-9) 20#define SHIFT_2440TXF (14-9)
@@ -99,4 +99,4 @@
99 99
100/* include the reset of the code which will do the work */ 100/* include the reset of the code which will do the work */
101 101
102#include <asm/plat-s3c/debug-macro.S> 102#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index 64bf7e94a5bf..23c470c2e5b1 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -13,7 +13,7 @@
13#ifndef __ASM_ARCH_MAP_H 13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H 14#define __ASM_ARCH_MAP_H
15 15
16#include <asm/plat-s3c/map.h> 16#include <plat/map.h>
17 17
18#define S3C2410_ADDR(x) S3C_ADDR(x) 18#define S3C2410_ADDR(x) S3C_ADDR(x)
19 19
diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c2410/include/mach/uncompress.h
index 708e47459ffc..ab39491beee2 100644
--- a/arch/arm/mach-s3c2410/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c2410/include/mach/uncompress.h
@@ -21,7 +21,7 @@
21#undef S3C2410_GPIOREG 21#undef S3C2410_GPIOREG
22#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x))) 22#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
23 23
24#include <asm/plat-s3c/uncompress.h> 24#include <plat/uncompress.h>
25 25
26static inline int is_arm926(void) 26static inline int is_arm926(void)
27{ 27{
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index f5c5c53e1cc1..92150399563b 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -25,8 +25,8 @@
25#include <linux/ioport.h> 25#include <linux/ioport.h>
26#include <linux/sysdev.h> 26#include <linux/sysdev.h>
27 27
28#include <asm/plat-s3c24xx/cpu.h> 28#include <plat/cpu.h>
29#include <asm/plat-s3c24xx/pm.h> 29#include <plat/pm.h>
30 30
31static int s3c2410_irq_add(struct sys_device *sysdev) 31static int s3c2410_irq_add(struct sys_device *sysdev)
32{ 32{
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 527f88a288ec..d061fea01900 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -48,12 +48,12 @@
48#include <asm/mach-types.h> 48#include <asm/mach-types.h>
49#include <mach/fb.h> 49#include <mach/fb.h>
50 50
51#include <asm/plat-s3c/regs-serial.h> 51#include <plat/regs-serial.h>
52#include <mach/regs-lcd.h> 52#include <mach/regs-lcd.h>
53#include <mach/regs-gpio.h> 53#include <mach/regs-gpio.h>
54 54
55#include <asm/plat-s3c24xx/devs.h> 55#include <plat/devs.h>
56#include <asm/plat-s3c24xx/cpu.h> 56#include <plat/cpu.h>
57 57
58#ifdef CONFIG_MTD_PARTITIONS 58#ifdef CONFIG_MTD_PARTITIONS
59 59
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index e4368e6e7e6c..8db9c700e3c2 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -39,7 +39,7 @@
39#include <asm/mach-types.h> 39#include <asm/mach-types.h>
40 40
41//#include <asm/debug-ll.h> 41//#include <asm/debug-ll.h>
42#include <asm/plat-s3c/regs-serial.h> 42#include <plat/regs-serial.h>
43#include <mach/regs-gpio.h> 43#include <mach/regs-gpio.h>
44#include <mach/regs-mem.h> 44#include <mach/regs-mem.h>
45#include <mach/regs-lcd.h> 45#include <mach/regs-lcd.h>
@@ -55,9 +55,9 @@
55 55
56#include <linux/serial_8250.h> 56#include <linux/serial_8250.h>
57 57
58#include <asm/plat-s3c24xx/clock.h> 58#include <plat/clock.h>
59#include <asm/plat-s3c24xx/devs.h> 59#include <plat/devs.h>
60#include <asm/plat-s3c24xx/cpu.h> 60#include <plat/cpu.h>
61 61
62#include "usb-simtec.h" 62#include "usb-simtec.h"
63#include "nor-simtec.h" 63#include "nor-simtec.h"
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 85e710f2863b..98716d0108e9 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -30,7 +30,7 @@
30#include <asm/irq.h> 30#include <asm/irq.h>
31#include <asm/mach-types.h> 31#include <asm/mach-types.h>
32 32
33#include <asm/plat-s3c/regs-serial.h> 33#include <plat/regs-serial.h>
34#include <mach/regs-lcd.h> 34#include <mach/regs-lcd.h>
35#include <mach/regs-gpio.h> 35#include <mach/regs-gpio.h>
36#include <mach/regs-clock.h> 36#include <mach/regs-clock.h>
@@ -40,10 +40,10 @@
40#include <mach/fb.h> 40#include <mach/fb.h>
41#include <asm/plat-s3c24xx/udc.h> 41#include <asm/plat-s3c24xx/udc.h>
42 42
43#include <asm/plat-s3c24xx/clock.h> 43#include <plat/clock.h>
44#include <asm/plat-s3c24xx/devs.h> 44#include <plat/devs.h>
45#include <asm/plat-s3c24xx/cpu.h> 45#include <plat/cpu.h>
46#include <asm/plat-s3c24xx/pm.h> 46#include <plat/pm.h>
47 47
48static struct map_desc h1940_iodesc[] __initdata = { 48static struct map_desc h1940_iodesc[] __initdata = {
49 [0] = { 49 [0] = {
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 3ece2d04934e..82505517846c 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -41,12 +41,12 @@
41#include <asm/mach/map.h> 41#include <asm/mach/map.h>
42 42
43#include <asm/plat-s3c/iic.h> 43#include <asm/plat-s3c/iic.h>
44#include <asm/plat-s3c/regs-serial.h> 44#include <plat/regs-serial.h>
45 45
46#include <asm/plat-s3c24xx/clock.h> 46#include <plat/clock.h>
47#include <asm/plat-s3c24xx/cpu.h> 47#include <plat/cpu.h>
48#include <asm/plat-s3c24xx/devs.h> 48#include <plat/devs.h>
49#include <asm/plat-s3c24xx/s3c2410.h> 49#include <plat/s3c2410.h>
50#include <asm/plat-s3c24xx/udc.h> 50#include <asm/plat-s3c24xx/udc.h>
51 51
52static struct map_desc n30_iodesc[] __initdata = { 52static struct map_desc n30_iodesc[] __initdata = {
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c
index c4dfe3eabe1d..d8255cf87e44 100644
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c2410/mach-otom.c
@@ -29,13 +29,13 @@
29#include <asm/irq.h> 29#include <asm/irq.h>
30#include <asm/mach-types.h> 30#include <asm/mach-types.h>
31 31
32#include <asm/plat-s3c/regs-serial.h> 32#include <plat/regs-serial.h>
33#include <mach/regs-gpio.h> 33#include <mach/regs-gpio.h>
34 34
35#include <asm/plat-s3c24xx/s3c2410.h> 35#include <plat/s3c2410.h>
36#include <asm/plat-s3c24xx/clock.h> 36#include <plat/clock.h>
37#include <asm/plat-s3c24xx/devs.h> 37#include <plat/devs.h>
38#include <asm/plat-s3c24xx/cpu.h> 38#include <plat/cpu.h>
39 39
40static struct map_desc otom11_iodesc[] __initdata = { 40static struct map_desc otom11_iodesc[] __initdata = {
41 /* Device area */ 41 /* Device area */
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 97c13192315b..661807e14e8a 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -48,17 +48,17 @@
48 48
49#include <mach/regs-gpio.h> 49#include <mach/regs-gpio.h>
50#include <mach/leds-gpio.h> 50#include <mach/leds-gpio.h>
51#include <asm/plat-s3c/regs-serial.h> 51#include <plat/regs-serial.h>
52#include <mach/fb.h> 52#include <mach/fb.h>
53#include <asm/plat-s3c/nand.h> 53#include <asm/plat-s3c/nand.h>
54#include <asm/plat-s3c24xx/udc.h> 54#include <asm/plat-s3c24xx/udc.h>
55#include <mach/spi.h> 55#include <mach/spi.h>
56#include <mach/spi-gpio.h> 56#include <mach/spi-gpio.h>
57 57
58#include <asm/plat-s3c24xx/common-smdk.h> 58#include <plat/common-smdk.h>
59#include <asm/plat-s3c24xx/devs.h> 59#include <plat/devs.h>
60#include <asm/plat-s3c24xx/cpu.h> 60#include <plat/cpu.h>
61#include <asm/plat-s3c24xx/pm.h> 61#include <plat/pm.h>
62 62
63static struct map_desc qt2410_iodesc[] __initdata = { 63static struct map_desc qt2410_iodesc[] __initdata = {
64 { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE } 64 { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c
index d49e58acb03b..152527bb2872 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
@@ -46,12 +46,12 @@
46#include <asm/irq.h> 46#include <asm/irq.h>
47#include <asm/mach-types.h> 47#include <asm/mach-types.h>
48 48
49#include <asm/plat-s3c/regs-serial.h> 49#include <plat/regs-serial.h>
50 50
51#include <asm/plat-s3c24xx/devs.h> 51#include <plat/devs.h>
52#include <asm/plat-s3c24xx/cpu.h> 52#include <plat/cpu.h>
53 53
54#include <asm/plat-s3c24xx/common-smdk.h> 54#include <plat/common-smdk.h>
55 55
56static struct map_desc smdk2410_iodesc[] __initdata = { 56static struct map_desc smdk2410_iodesc[] __initdata = {
57 /* nothing here yet */ 57 /* nothing here yet */
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c
index cc2e79fe4f9f..309dcf4c870a 100644
--- a/arch/arm/mach-s3c2410/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c
@@ -44,9 +44,9 @@
44#include <asm/irq.h> 44#include <asm/irq.h>
45#include <asm/mach-types.h> 45#include <asm/mach-types.h>
46 46
47#include <asm/plat-s3c/regs-serial.h> 47#include <plat/regs-serial.h>
48#include <asm/plat-s3c24xx/devs.h> 48#include <plat/devs.h>
49#include <asm/plat-s3c24xx/cpu.h> 49#include <plat/cpu.h>
50 50
51#ifdef CONFIG_MTD_PARTITIONS 51#ifdef CONFIG_MTD_PARTITIONS
52 52
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index ed3acb05c855..941353af16dc 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -40,13 +40,13 @@
40#include <asm/irq.h> 40#include <asm/irq.h>
41#include <asm/mach-types.h> 41#include <asm/mach-types.h>
42 42
43#include <asm/plat-s3c/regs-serial.h> 43#include <plat/regs-serial.h>
44#include <mach/regs-gpio.h> 44#include <mach/regs-gpio.h>
45#include <mach/leds-gpio.h> 45#include <mach/leds-gpio.h>
46 46
47#include <asm/plat-s3c24xx/clock.h> 47#include <plat/clock.h>
48#include <asm/plat-s3c24xx/devs.h> 48#include <plat/devs.h>
49#include <asm/plat-s3c24xx/cpu.h> 49#include <plat/cpu.h>
50 50
51#include "usb-simtec.h" 51#include "usb-simtec.h"
52#include "nor-simtec.h" 52#include "nor-simtec.h"
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index 733f8a227775..a6970f613192 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -34,8 +34,8 @@
34#include <mach/regs-gpio.h> 34#include <mach/regs-gpio.h>
35#include <mach/h1940.h> 35#include <mach/h1940.h>
36 36
37#include <asm/plat-s3c24xx/cpu.h> 37#include <plat/cpu.h>
38#include <asm/plat-s3c24xx/pm.h> 38#include <plat/pm.h>
39 39
40#ifdef CONFIG_S3C2410_PM_DEBUG 40#ifdef CONFIG_S3C2410_PM_DEBUG
41extern void pm_dbg(const char *fmt, ...); 41extern void pm_dbg(const char *fmt, ...);
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index b1e658c917a0..ac79b536c4c3 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -29,12 +29,12 @@
29#include <asm/irq.h> 29#include <asm/irq.h>
30 30
31#include <mach/regs-clock.h> 31#include <mach/regs-clock.h>
32#include <asm/plat-s3c/regs-serial.h> 32#include <plat/regs-serial.h>
33 33
34#include <asm/plat-s3c24xx/s3c2410.h> 34#include <plat/s3c2410.h>
35#include <asm/plat-s3c24xx/cpu.h> 35#include <plat/cpu.h>
36#include <asm/plat-s3c24xx/devs.h> 36#include <plat/devs.h>
37#include <asm/plat-s3c24xx/clock.h> 37#include <plat/clock.h>
38 38
39/* Initial IO mappings */ 39/* Initial IO mappings */
40 40
diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
index be37f221a177..dd5b6388a5a5 100644
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c2410/sleep.S
@@ -32,7 +32,7 @@
32#include <mach/regs-gpio.h> 32#include <mach/regs-gpio.h>
33#include <mach/regs-clock.h> 33#include <mach/regs-clock.h>
34#include <mach/regs-mem.h> 34#include <mach/regs-mem.h>
35#include <asm/plat-s3c/regs-serial.h> 35#include <plat/regs-serial.h>
36 36
37 /* s3c2410_cpu_suspend 37 /* s3c2410_cpu_suspend
38 * 38 *
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c
index eb6fc0bfd47e..6078f09b7df5 100644
--- a/arch/arm/mach-s3c2410/usb-simtec.c
+++ b/arch/arm/mach-s3c2410/usb-simtec.c
@@ -35,7 +35,7 @@
35#include <mach/hardware.h> 35#include <mach/hardware.h>
36#include <asm/irq.h> 36#include <asm/irq.h>
37 37
38#include <asm/plat-s3c24xx/devs.h> 38#include <plat/devs.h>
39#include "usb-simtec.h" 39#include "usb-simtec.h"
40 40
41/* control power and monitor over-current events on various Simtec 41/* control power and monitor over-current events on various Simtec
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 5fbaac6054f8..96d9eb15424f 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -37,13 +37,13 @@
37 37
38#include <mach/hardware.h> 38#include <mach/hardware.h>
39 39
40#include <asm/plat-s3c/regs-serial.h> 40#include <plat/regs-serial.h>
41#include <mach/regs-clock.h> 41#include <mach/regs-clock.h>
42#include <mach/regs-gpio.h> 42#include <mach/regs-gpio.h>
43 43
44#include <asm/plat-s3c24xx/s3c2412.h> 44#include <plat/s3c2412.h>
45#include <asm/plat-s3c24xx/clock.h> 45#include <plat/clock.h>
46#include <asm/plat-s3c24xx/cpu.h> 46#include <plat/cpu.h>
47 47
48/* We currently have to assume that the system is running 48/* We currently have to assume that the system is running
49 * from the XTPll input, and that all ***REFCLKs are being 49 * from the XTPll input, and that all ***REFCLKs are being
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index dcfff6b8b958..ba0591e71f32 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -21,10 +21,10 @@
21#include <asm/dma.h> 21#include <asm/dma.h>
22#include <mach/dma.h> 22#include <mach/dma.h>
23 23
24#include <asm/plat-s3c24xx/dma.h> 24#include <plat/dma.h>
25#include <asm/plat-s3c24xx/cpu.h> 25#include <plat/cpu.h>
26 26
27#include <asm/plat-s3c/regs-serial.h> 27#include <plat/regs-serial.h>
28#include <mach/regs-gpio.h> 28#include <mach/regs-gpio.h>
29#include <asm/plat-s3c/regs-ac97.h> 29#include <asm/plat-s3c/regs-ac97.h>
30#include <mach/regs-mem.h> 30#include <mach/regs-mem.h>
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
index 41720f2c1fea..6000ca9d1815 100644
--- a/arch/arm/mach-s3c2412/irq.c
+++ b/arch/arm/mach-s3c2412/irq.c
@@ -35,9 +35,9 @@
35#include <mach/regs-gpio.h> 35#include <mach/regs-gpio.h>
36#include <mach/regs-power.h> 36#include <mach/regs-power.h>
37 37
38#include <asm/plat-s3c24xx/cpu.h> 38#include <plat/cpu.h>
39#include <asm/plat-s3c24xx/irq.h> 39#include <plat/irq.h>
40#include <asm/plat-s3c24xx/pm.h> 40#include <plat/pm.h>
41 41
42#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1) 42#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
43#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0)))) 43#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index ad980a1690c2..b08f18c8c47a 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -30,7 +30,7 @@
30#include <asm/mach/map.h> 30#include <asm/mach/map.h>
31#include <asm/mach/irq.h> 31#include <asm/mach/irq.h>
32 32
33#include <asm/plat-s3c/regs-serial.h> 33#include <plat/regs-serial.h>
34#include <asm/plat-s3c/nand.h> 34#include <asm/plat-s3c/nand.h>
35#include <asm/plat-s3c/iic.h> 35#include <asm/plat-s3c/iic.h>
36 36
@@ -48,10 +48,10 @@
48#include <linux/mtd/nand_ecc.h> 48#include <linux/mtd/nand_ecc.h>
49#include <linux/mtd/partitions.h> 49#include <linux/mtd/partitions.h>
50 50
51#include <asm/plat-s3c24xx/clock.h> 51#include <plat/clock.h>
52#include <asm/plat-s3c24xx/devs.h> 52#include <plat/devs.h>
53#include <asm/plat-s3c24xx/cpu.h> 53#include <plat/cpu.h>
54#include <asm/plat-s3c24xx/pm.h> 54#include <plat/pm.h>
55#include <asm/plat-s3c24xx/udc.h> 55#include <asm/plat-s3c24xx/udc.h>
56 56
57static struct map_desc jive_iodesc[] __initdata = { 57static struct map_desc jive_iodesc[] __initdata = {
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index 8f8d9117b968..c719b5a740a9 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -32,7 +32,7 @@
32#include <asm/mach-types.h> 32#include <asm/mach-types.h>
33 33
34//#include <asm/debug-ll.h> 34//#include <asm/debug-ll.h>
35#include <asm/plat-s3c/regs-serial.h> 35#include <plat/regs-serial.h>
36#include <mach/regs-gpio.h> 36#include <mach/regs-gpio.h>
37#include <mach/regs-lcd.h> 37#include <mach/regs-lcd.h>
38 38
@@ -40,13 +40,13 @@
40#include <asm/plat-s3c24xx/udc.h> 40#include <asm/plat-s3c24xx/udc.h>
41#include <mach/fb.h> 41#include <mach/fb.h>
42 42
43#include <asm/plat-s3c24xx/s3c2410.h> 43#include <plat/s3c2410.h>
44#include <asm/plat-s3c24xx/s3c2412.h> 44#include <plat/s3c2412.h>
45#include <asm/plat-s3c24xx/clock.h> 45#include <plat/clock.h>
46#include <asm/plat-s3c24xx/devs.h> 46#include <plat/devs.h>
47#include <asm/plat-s3c24xx/cpu.h> 47#include <plat/cpu.h>
48 48
49#include <asm/plat-s3c24xx/common-smdk.h> 49#include <plat/common-smdk.h>
50 50
51static struct map_desc smdk2413_iodesc[] __initdata = { 51static struct map_desc smdk2413_iodesc[] __initdata = {
52}; 52};
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index bb9bf63b2e02..4cfa19ad9be0 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -32,7 +32,7 @@
32#include <asm/irq.h> 32#include <asm/irq.h>
33#include <asm/mach-types.h> 33#include <asm/mach-types.h>
34 34
35#include <asm/plat-s3c/regs-serial.h> 35#include <plat/regs-serial.h>
36#include <mach/regs-gpio.h> 36#include <mach/regs-gpio.h>
37#include <mach/regs-lcd.h> 37#include <mach/regs-lcd.h>
38 38
@@ -41,11 +41,11 @@
41 41
42#include <asm/plat-s3c/nand.h> 42#include <asm/plat-s3c/nand.h>
43 43
44#include <asm/plat-s3c24xx/s3c2410.h> 44#include <plat/s3c2410.h>
45#include <asm/plat-s3c24xx/s3c2412.h> 45#include <plat/s3c2412.h>
46#include <asm/plat-s3c24xx/clock.h> 46#include <plat/clock.h>
47#include <asm/plat-s3c24xx/devs.h> 47#include <plat/devs.h>
48#include <asm/plat-s3c24xx/cpu.h> 48#include <plat/cpu.h>
49 49
50 50
51static struct map_desc vstms_iodesc[] __initdata = { 51static struct map_desc vstms_iodesc[] __initdata = {
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
index 9540ef752f73..217e9e4ed45f 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -28,10 +28,10 @@
28#include <mach/regs-gpio.h> 28#include <mach/regs-gpio.h>
29#include <mach/regs-dsc.h> 29#include <mach/regs-dsc.h>
30 30
31#include <asm/plat-s3c24xx/cpu.h> 31#include <plat/cpu.h>
32#include <asm/plat-s3c24xx/pm.h> 32#include <plat/pm.h>
33 33
34#include <asm/plat-s3c24xx/s3c2412.h> 34#include <plat/s3c2412.h>
35 35
36extern void s3c2412_sleep_enter(void); 36extern void s3c2412_sleep_enter(void);
37 37
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index 42440fc55681..313759c3da69 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -34,7 +34,7 @@
34#include <mach/idle.h> 34#include <mach/idle.h>
35 35
36#include <mach/regs-clock.h> 36#include <mach/regs-clock.h>
37#include <asm/plat-s3c/regs-serial.h> 37#include <plat/regs-serial.h>
38#include <mach/regs-power.h> 38#include <mach/regs-power.h>
39#include <mach/regs-gpio.h> 39#include <mach/regs-gpio.h>
40#include <mach/regs-gpioj.h> 40#include <mach/regs-gpioj.h>
@@ -42,11 +42,11 @@
42#include <asm/plat-s3c24xx/regs-spi.h> 42#include <asm/plat-s3c24xx/regs-spi.h>
43#include <mach/regs-s3c2412.h> 43#include <mach/regs-s3c2412.h>
44 44
45#include <asm/plat-s3c24xx/s3c2412.h> 45#include <plat/s3c2412.h>
46#include <asm/plat-s3c24xx/cpu.h> 46#include <plat/cpu.h>
47#include <asm/plat-s3c24xx/devs.h> 47#include <plat/devs.h>
48#include <asm/plat-s3c24xx/clock.h> 48#include <plat/clock.h>
49#include <asm/plat-s3c24xx/pm.h> 49#include <plat/pm.h>
50 50
51#ifndef CONFIG_CPU_S3C2412_ONLY 51#ifndef CONFIG_CPU_S3C2412_ONLY
52void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO; 52void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index 40503a65bacf..d1c29b2537cd 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -41,8 +41,8 @@
41 41
42#include <mach/regs-clock.h> 42#include <mach/regs-clock.h>
43 43
44#include <asm/plat-s3c24xx/clock.h> 44#include <plat/clock.h>
45#include <asm/plat-s3c24xx/cpu.h> 45#include <plat/cpu.h>
46 46
47/* S3C2440 extended clock support */ 47/* S3C2440 extended clock support */
48 48
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index cdd4e6e79ac0..32303f6a8321 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -20,10 +20,10 @@
20#include <asm/dma.h> 20#include <asm/dma.h>
21#include <mach/dma.h> 21#include <mach/dma.h>
22 22
23#include <asm/plat-s3c24xx/dma.h> 23#include <plat/dma.h>
24#include <asm/plat-s3c24xx/cpu.h> 24#include <plat/cpu.h>
25 25
26#include <asm/plat-s3c/regs-serial.h> 26#include <plat/regs-serial.h>
27#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
28#include <asm/plat-s3c/regs-ac97.h> 28#include <asm/plat-s3c/regs-ac97.h>
29#include <mach/regs-mem.h> 29#include <mach/regs-mem.h>
diff --git a/arch/arm/mach-s3c2440/dsc.c b/arch/arm/mach-s3c2440/dsc.c
index 4f7d06baf0d3..554044272771 100644
--- a/arch/arm/mach-s3c2440/dsc.c
+++ b/arch/arm/mach-s3c2440/dsc.c
@@ -27,8 +27,8 @@
27#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
28#include <mach/regs-dsc.h> 28#include <mach/regs-dsc.h>
29 29
30#include <asm/plat-s3c24xx/cpu.h> 30#include <plat/cpu.h>
31#include <asm/plat-s3c24xx/s3c2440.h> 31#include <plat/s3c2440.h>
32 32
33int s3c2440_set_dsc(unsigned int pin, unsigned int value) 33int s3c2440_set_dsc(unsigned int pin, unsigned int value)
34{ 34{
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
index 33e3ede0a2b3..63c5ab65727f 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -34,9 +34,9 @@
34#include <mach/regs-irq.h> 34#include <mach/regs-irq.h>
35#include <mach/regs-gpio.h> 35#include <mach/regs-gpio.h>
36 36
37#include <asm/plat-s3c24xx/cpu.h> 37#include <plat/cpu.h>
38#include <asm/plat-s3c24xx/pm.h> 38#include <plat/pm.h>
39#include <asm/plat-s3c24xx/irq.h> 39#include <plat/irq.h>
40 40
41/* WDT/AC97 */ 41/* WDT/AC97 */
42 42
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 19eb0e5269ac..e2beca470484 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -35,7 +35,7 @@
35#include <asm/irq.h> 35#include <asm/irq.h>
36#include <asm/mach-types.h> 36#include <asm/mach-types.h>
37 37
38#include <asm/plat-s3c/regs-serial.h> 38#include <plat/regs-serial.h>
39#include <mach/regs-gpio.h> 39#include <mach/regs-gpio.h>
40#include <mach/regs-mem.h> 40#include <mach/regs-mem.h>
41#include <mach/regs-lcd.h> 41#include <mach/regs-lcd.h>
@@ -48,9 +48,9 @@
48 48
49#include <net/ax88796.h> 49#include <net/ax88796.h>
50 50
51#include <asm/plat-s3c24xx/clock.h> 51#include <plat/clock.h>
52#include <asm/plat-s3c24xx/devs.h> 52#include <plat/devs.h>
53#include <asm/plat-s3c24xx/cpu.h> 53#include <plat/cpu.h>
54 54
55#define COPYRIGHT ", (c) 2005 Simtec Electronics" 55#define COPYRIGHT ", (c) 2005 Simtec Electronics"
56 56
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index f0f0cc6afcf4..66876c6f2f1c 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -31,7 +31,7 @@
31#include <asm/irq.h> 31#include <asm/irq.h>
32#include <asm/mach-types.h> 32#include <asm/mach-types.h>
33 33
34#include <asm/plat-s3c/regs-serial.h> 34#include <plat/regs-serial.h>
35#include <mach/regs-gpio.h> 35#include <mach/regs-gpio.h>
36#include <mach/regs-mem.h> 36#include <mach/regs-mem.h>
37#include <mach/regs-lcd.h> 37#include <mach/regs-lcd.h>
@@ -42,9 +42,9 @@
42#include <linux/mtd/nand_ecc.h> 42#include <linux/mtd/nand_ecc.h>
43#include <linux/mtd/partitions.h> 43#include <linux/mtd/partitions.h>
44 44
45#include <asm/plat-s3c24xx/clock.h> 45#include <plat/clock.h>
46#include <asm/plat-s3c24xx/devs.h> 46#include <plat/devs.h>
47#include <asm/plat-s3c24xx/cpu.h> 47#include <plat/cpu.h>
48 48
49static struct map_desc at2440evb_iodesc[] __initdata = { 49static struct map_desc at2440evb_iodesc[] __initdata = {
50 /* Nothing here */ 50 /* Nothing here */
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 49e828d1d4d8..a546307fd53d 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -36,13 +36,13 @@
36 36
37//#include <asm/debug-ll.h> 37//#include <asm/debug-ll.h>
38#include <mach/regs-gpio.h> 38#include <mach/regs-gpio.h>
39#include <asm/plat-s3c/regs-serial.h> 39#include <plat/regs-serial.h>
40 40
41#include <asm/plat-s3c24xx/s3c2410.h> 41#include <plat/s3c2410.h>
42#include <asm/plat-s3c24xx/s3c2440.h> 42#include <plat/s3c2440.h>
43#include <asm/plat-s3c24xx/clock.h> 43#include <plat/clock.h>
44#include <asm/plat-s3c24xx/devs.h> 44#include <plat/devs.h>
45#include <asm/plat-s3c24xx/cpu.h> 45#include <plat/cpu.h>
46 46
47static struct map_desc nexcoder_iodesc[] __initdata = { 47static struct map_desc nexcoder_iodesc[] __initdata = {
48 /* nothing here yet */ 48 /* nothing here yet */
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 85144aa52c27..2361d606abc5 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -33,7 +33,7 @@
33#include <asm/irq.h> 33#include <asm/irq.h>
34#include <asm/mach-types.h> 34#include <asm/mach-types.h>
35 35
36#include <asm/plat-s3c/regs-serial.h> 36#include <plat/regs-serial.h>
37#include <mach/regs-gpio.h> 37#include <mach/regs-gpio.h>
38#include <mach/regs-mem.h> 38#include <mach/regs-mem.h>
39#include <mach/regs-lcd.h> 39#include <mach/regs-lcd.h>
@@ -44,9 +44,9 @@
44#include <linux/mtd/nand_ecc.h> 44#include <linux/mtd/nand_ecc.h>
45#include <linux/mtd/partitions.h> 45#include <linux/mtd/partitions.h>
46 46
47#include <asm/plat-s3c24xx/clock.h> 47#include <plat/clock.h>
48#include <asm/plat-s3c24xx/devs.h> 48#include <plat/devs.h>
49#include <asm/plat-s3c24xx/cpu.h> 49#include <plat/cpu.h>
50 50
51/* onboard perihperal map */ 51/* onboard perihperal map */
52 52
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index a4c690456d19..4d14c7cff892 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -37,7 +37,7 @@
37#include <asm/irq.h> 37#include <asm/irq.h>
38#include <asm/mach-types.h> 38#include <asm/mach-types.h>
39 39
40#include <asm/plat-s3c/regs-serial.h> 40#include <plat/regs-serial.h>
41#include <mach/regs-gpio.h> 41#include <mach/regs-gpio.h>
42#include <mach/regs-lcd.h> 42#include <mach/regs-lcd.h>
43 43
@@ -45,10 +45,10 @@
45#include <asm/plat-s3c/nand.h> 45#include <asm/plat-s3c/nand.h>
46#include <mach/fb.h> 46#include <mach/fb.h>
47 47
48#include <asm/plat-s3c24xx/clock.h> 48#include <plat/clock.h>
49#include <asm/plat-s3c24xx/devs.h> 49#include <plat/devs.h>
50#include <asm/plat-s3c24xx/cpu.h> 50#include <plat/cpu.h>
51#include <asm/plat-s3c24xx/pm.h> 51#include <plat/pm.h>
52 52
53static struct map_desc rx3715_iodesc[] __initdata = { 53static struct map_desc rx3715_iodesc[] __initdata = {
54 /* dump ISA space somewhere unused */ 54 /* dump ISA space somewhere unused */
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index 7ac60b869e7f..fefeaaa4155f 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -31,20 +31,20 @@
31#include <asm/irq.h> 31#include <asm/irq.h>
32#include <asm/mach-types.h> 32#include <asm/mach-types.h>
33 33
34#include <asm/plat-s3c/regs-serial.h> 34#include <plat/regs-serial.h>
35#include <mach/regs-gpio.h> 35#include <mach/regs-gpio.h>
36#include <mach/regs-lcd.h> 36#include <mach/regs-lcd.h>
37 37
38#include <mach/idle.h> 38#include <mach/idle.h>
39#include <mach/fb.h> 39#include <mach/fb.h>
40 40
41#include <asm/plat-s3c24xx/s3c2410.h> 41#include <plat/s3c2410.h>
42#include <asm/plat-s3c24xx/s3c2440.h> 42#include <plat/s3c2440.h>
43#include <asm/plat-s3c24xx/clock.h> 43#include <plat/clock.h>
44#include <asm/plat-s3c24xx/devs.h> 44#include <plat/devs.h>
45#include <asm/plat-s3c24xx/cpu.h> 45#include <plat/cpu.h>
46 46
47#include <asm/plat-s3c24xx/common-smdk.h> 47#include <plat/common-smdk.h>
48 48
49static struct map_desc smdk2440_iodesc[] __initdata = { 49static struct map_desc smdk2440_iodesc[] __initdata = {
50 /* ISA IO Space map (memory space selected by A24) */ 50 /* ISA IO Space map (memory space selected by A24) */
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c
index c81cdb330712..ac1f7ea5f405 100644
--- a/arch/arm/mach-s3c2440/s3c2440.c
+++ b/arch/arm/mach-s3c2440/s3c2440.c
@@ -29,9 +29,9 @@
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30#include <asm/irq.h> 30#include <asm/irq.h>
31 31
32#include <asm/plat-s3c24xx/s3c2440.h> 32#include <plat/s3c2440.h>
33#include <asm/plat-s3c24xx/devs.h> 33#include <plat/devs.h>
34#include <asm/plat-s3c24xx/cpu.h> 34#include <plat/cpu.h>
35 35
36static struct sys_device s3c2440_sysdev = { 36static struct sys_device s3c2440_sysdev = {
37 .cls = &s3c2440_sysclass, 37 .cls = &s3c2440_sysclass,
diff --git a/arch/arm/mach-s3c2442/clock.c b/arch/arm/mach-s3c2442/clock.c
index 18f2ce4d7b23..ea1aa1f5157a 100644
--- a/arch/arm/mach-s3c2442/clock.c
+++ b/arch/arm/mach-s3c2442/clock.c
@@ -41,8 +41,8 @@
41 41
42#include <mach/regs-clock.h> 42#include <mach/regs-clock.h>
43 43
44#include <asm/plat-s3c24xx/clock.h> 44#include <plat/clock.h>
45#include <asm/plat-s3c24xx/cpu.h> 45#include <plat/cpu.h>
46 46
47/* S3C2442 extended clock support */ 47/* S3C2442 extended clock support */
48 48
diff --git a/arch/arm/mach-s3c2442/s3c2442.c b/arch/arm/mach-s3c2442/s3c2442.c
index fbf8264249da..4663bdc7fff6 100644
--- a/arch/arm/mach-s3c2442/s3c2442.c
+++ b/arch/arm/mach-s3c2442/s3c2442.c
@@ -19,8 +19,8 @@
19#include <linux/serial_core.h> 19#include <linux/serial_core.h>
20#include <linux/sysdev.h> 20#include <linux/sysdev.h>
21 21
22#include <asm/plat-s3c24xx/s3c2442.h> 22#include <plat/s3c2442.h>
23#include <asm/plat-s3c24xx/cpu.h> 23#include <plat/cpu.h>
24 24
25static struct sys_device s3c2442_sysdev = { 25static struct sys_device s3c2442_sysdev = {
26 .cls = &s3c2442_sysclass, 26 .cls = &s3c2442_sysclass,
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 603b5ea1deab..2f60bf6b8d43 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -39,9 +39,9 @@
39 39
40#include <mach/regs-s3c2443-clock.h> 40#include <mach/regs-s3c2443-clock.h>
41 41
42#include <asm/plat-s3c24xx/s3c2443.h> 42#include <plat/s3c2443.h>
43#include <asm/plat-s3c24xx/clock.h> 43#include <plat/clock.h>
44#include <asm/plat-s3c24xx/cpu.h> 44#include <plat/cpu.h>
45 45
46/* We currently have to assume that the system is running 46/* We currently have to assume that the system is running
47 * from the XTPll input, and that all ***REFCLKs are being 47 * from the XTPll input, and that all ***REFCLKs are being
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index 5d9ee772659b..f73ccb25ff94 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -21,10 +21,10 @@
21#include <asm/dma.h> 21#include <asm/dma.h>
22#include <mach/dma.h> 22#include <mach/dma.h>
23 23
24#include <asm/plat-s3c24xx/dma.h> 24#include <plat/dma.h>
25#include <asm/plat-s3c24xx/cpu.h> 25#include <plat/cpu.h>
26 26
27#include <asm/plat-s3c/regs-serial.h> 27#include <plat/regs-serial.h>
28#include <mach/regs-gpio.h> 28#include <mach/regs-gpio.h>
29#include <asm/plat-s3c/regs-ac97.h> 29#include <asm/plat-s3c/regs-ac97.h>
30#include <mach/regs-mem.h> 30#include <mach/regs-mem.h>
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c
index e44341d7dfef..0e0d693f3974 100644
--- a/arch/arm/mach-s3c2443/irq.c
+++ b/arch/arm/mach-s3c2443/irq.c
@@ -34,9 +34,9 @@
34#include <mach/regs-irq.h> 34#include <mach/regs-irq.h>
35#include <mach/regs-gpio.h> 35#include <mach/regs-gpio.h>
36 36
37#include <asm/plat-s3c24xx/cpu.h> 37#include <plat/cpu.h>
38#include <asm/plat-s3c24xx/pm.h> 38#include <plat/pm.h>
39#include <asm/plat-s3c24xx/irq.h> 39#include <plat/irq.h>
40 40
41#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1) 41#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
42 42
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index f0d119dc0409..a7fe65f3dcc1 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -31,20 +31,20 @@
31#include <asm/irq.h> 31#include <asm/irq.h>
32#include <asm/mach-types.h> 32#include <asm/mach-types.h>
33 33
34#include <asm/plat-s3c/regs-serial.h> 34#include <plat/regs-serial.h>
35#include <mach/regs-gpio.h> 35#include <mach/regs-gpio.h>
36#include <mach/regs-lcd.h> 36#include <mach/regs-lcd.h>
37 37
38#include <mach/idle.h> 38#include <mach/idle.h>
39#include <mach/fb.h> 39#include <mach/fb.h>
40 40
41#include <asm/plat-s3c24xx/s3c2410.h> 41#include <plat/s3c2410.h>
42#include <asm/plat-s3c24xx/s3c2440.h> 42#include <plat/s3c2440.h>
43#include <asm/plat-s3c24xx/clock.h> 43#include <plat/clock.h>
44#include <asm/plat-s3c24xx/devs.h> 44#include <plat/devs.h>
45#include <asm/plat-s3c24xx/cpu.h> 45#include <plat/cpu.h>
46 46
47#include <asm/plat-s3c24xx/common-smdk.h> 47#include <plat/common-smdk.h>
48 48
49static struct map_desc smdk2443_iodesc[] __initdata = { 49static struct map_desc smdk2443_iodesc[] __initdata = {
50 /* ISA IO Space map (memory space selected by A24) */ 50 /* ISA IO Space map (memory space selected by A24) */
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c
index c973b68cc735..bbeddf9ddcb1 100644
--- a/arch/arm/mach-s3c2443/s3c2443.c
+++ b/arch/arm/mach-s3c2443/s3c2443.c
@@ -32,9 +32,9 @@
32#include <mach/regs-s3c2443-clock.h> 32#include <mach/regs-s3c2443-clock.h>
33#include <mach/reset.h> 33#include <mach/reset.h>
34 34
35#include <asm/plat-s3c24xx/s3c2443.h> 35#include <plat/s3c2443.h>
36#include <asm/plat-s3c24xx/devs.h> 36#include <plat/devs.h>
37#include <asm/plat-s3c24xx/cpu.h> 37#include <plat/cpu.h>
38 38
39static struct map_desc s3c2443_iodesc[] __initdata = { 39static struct map_desc s3c2443_iodesc[] __initdata = {
40 IODESC_ENT(WATCHDOG), 40 IODESC_ENT(WATCHDOG),
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 330814d1ee25..d1193884d76d 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -428,7 +428,7 @@ config CPU_32v6K
428# ARMv7 428# ARMv7
429config CPU_V7 429config CPU_V7
430 bool "Support ARM V7 processor" 430 bool "Support ARM V7 processor"
431 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB 431 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP3
432 select CPU_32v6K 432 select CPU_32v6K
433 select CPU_32v7 433 select CPU_32v7
434 select CPU_ABRT_EV7 434 select CPU_ABRT_EV7
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index b917206ee906..a94f0c44ebc8 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -15,6 +15,9 @@ config ARCH_OMAP1
15config ARCH_OMAP2 15config ARCH_OMAP2
16 bool "TI OMAP2" 16 bool "TI OMAP2"
17 17
18config ARCH_OMAP3
19 bool "TI OMAP3"
20
18endchoice 21endchoice
19 22
20comment "OMAP Feature Selections" 23comment "OMAP Feature Selections"
@@ -29,6 +32,30 @@ config OMAP_DEBUG_LEDS
29 depends on OMAP_DEBUG_DEVICES 32 depends on OMAP_DEBUG_DEVICES
30 default y if LEDS || LEDS_OMAP_DEBUG 33 default y if LEDS || LEDS_OMAP_DEBUG
31 34
35config OMAP_DEBUG_POWERDOMAIN
36 bool "Emit debug messages from powerdomain layer"
37 depends on ARCH_OMAP2 || ARCH_OMAP3
38 default n
39 help
40 Say Y here if you want to compile in powerdomain layer
41 debugging messages for OMAP2/3. These messages can
42 provide more detail as to why some powerdomain calls
43 may be failing, and will also emit a descriptive message
44 for every powerdomain register write. However, the
45 extra detail costs some memory.
46
47config OMAP_DEBUG_CLOCKDOMAIN
48 bool "Emit debug messages from clockdomain layer"
49 depends on ARCH_OMAP2 || ARCH_OMAP3
50 default n
51 help
52 Say Y here if you want to compile in clockdomain layer
53 debugging messages for OMAP2/3. These messages can
54 provide more detail as to why some clockdomain calls
55 may be failing, and will also emit a descriptive message
56 for every clockdomain register write. However, the
57 extra detail costs some memory.
58
32config OMAP_RESET_CLOCKS 59config OMAP_RESET_CLOCKS
33 bool "Reset unused clocks during boot" 60 bool "Reset unused clocks during boot"
34 depends on ARCH_OMAP 61 depends on ARCH_OMAP
@@ -88,13 +115,13 @@ config OMAP_MPU_TIMER
88 115
89config OMAP_32K_TIMER 116config OMAP_32K_TIMER
90 bool "Use 32KHz timer" 117 bool "Use 32KHz timer"
91 depends on ARCH_OMAP16XX || ARCH_OMAP24XX 118 depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
92 help 119 help
93 Select this option if you want to enable the OMAP 32KHz timer. 120 Select this option if you want to enable the OMAP 32KHz timer.
94 This timer saves power compared to the OMAP_MPU_TIMER, and has 121 This timer saves power compared to the OMAP_MPU_TIMER, and has
95 support for no tick during idle. The 32KHz timer provides less 122 support for no tick during idle. The 32KHz timer provides less
96 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is 123 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
97 currently only available for OMAP16XX and 24XX. 124 currently only available for OMAP16XX, 24XX and 34XX.
98 125
99endchoice 126endchoice
100 127
@@ -109,7 +136,7 @@ config OMAP_32K_TIMER_HZ
109 136
110config OMAP_DM_TIMER 137config OMAP_DM_TIMER
111 bool "Use dual-mode timer" 138 bool "Use dual-mode timer"
112 depends on ARCH_OMAP16XX || ARCH_OMAP24XX 139 depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
113 help 140 help
114 Select this option if you want to use OMAP Dual-Mode timers. 141 Select this option if you want to use OMAP Dual-Mode timers.
115 142
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 2c4051cc79a1..deaff58878a2 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -4,7 +4,7 @@
4 4
5# Common support 5# Common support
6obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \ 6obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
7 usb.o fb.o 7 usb.o fb.o io.o
8obj-m := 8obj-m :=
9obj-n := 9obj-n :=
10obj- := 10obj- :=
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 8bdf0ead0cf3..0843b8882f93 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -248,6 +248,7 @@ static struct omap_globals *omap2_globals;
248 248
249static void __init __omap2_set_globals(void) 249static void __init __omap2_set_globals(void)
250{ 250{
251 omap2_set_globals_tap(omap2_globals);
251 omap2_set_globals_memory(omap2_globals); 252 omap2_set_globals_memory(omap2_globals);
252 omap2_set_globals_control(omap2_globals); 253 omap2_set_globals_control(omap2_globals);
253 omap2_set_globals_prcm(omap2_globals); 254 omap2_set_globals_prcm(omap2_globals);
@@ -258,12 +259,13 @@ static void __init __omap2_set_globals(void)
258#if defined(CONFIG_ARCH_OMAP2420) 259#if defined(CONFIG_ARCH_OMAP2420)
259 260
260static struct omap_globals omap242x_globals = { 261static struct omap_globals omap242x_globals = {
261 .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x48014000), 262 .class = OMAP242X_CLASS,
262 .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE), 263 .tap = OMAP2_IO_ADDRESS(0x48014000),
263 .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE), 264 .sdrc = OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
264 .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE), 265 .sms = OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
265 .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE), 266 .ctrl = OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
266 .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CM_BASE), 267 .prm = OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
268 .cm = OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
267}; 269};
268 270
269void __init omap2_set_globals_242x(void) 271void __init omap2_set_globals_242x(void)
@@ -276,12 +278,13 @@ void __init omap2_set_globals_242x(void)
276#if defined(CONFIG_ARCH_OMAP2430) 278#if defined(CONFIG_ARCH_OMAP2430)
277 279
278static struct omap_globals omap243x_globals = { 280static struct omap_globals omap243x_globals = {
279 .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4900a000), 281 .class = OMAP243X_CLASS,
280 .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE), 282 .tap = OMAP2_IO_ADDRESS(0x4900a000),
281 .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE), 283 .sdrc = OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
282 .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE), 284 .sms = OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
283 .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE), 285 .ctrl = OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE),
284 .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_CM_BASE), 286 .prm = OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE),
287 .cm = OMAP2_IO_ADDRESS(OMAP2430_CM_BASE),
285}; 288};
286 289
287void __init omap2_set_globals_243x(void) 290void __init omap2_set_globals_243x(void)
@@ -294,12 +297,13 @@ void __init omap2_set_globals_243x(void)
294#if defined(CONFIG_ARCH_OMAP3430) 297#if defined(CONFIG_ARCH_OMAP3430)
295 298
296static struct omap_globals omap343x_globals = { 299static struct omap_globals omap343x_globals = {
297 .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4830A000), 300 .class = OMAP343X_CLASS,
298 .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE), 301 .tap = OMAP2_IO_ADDRESS(0x4830A000),
299 .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE), 302 .sdrc = OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
300 .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE), 303 .sms = OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
301 .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE), 304 .ctrl = OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE),
302 .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_CM_BASE), 305 .prm = OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE),
306 .cm = OMAP2_IO_ADDRESS(OMAP3430_CM_BASE),
303}; 307};
304 308
305void __init omap2_set_globals_343x(void) 309void __init omap2_set_globals_343x(void)
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 97187fa0ae52..0cb2b22388e9 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -20,17 +20,17 @@
20#include <asm/mach/map.h> 20#include <asm/mach/map.h>
21 21
22#include <mach/tc.h> 22#include <mach/tc.h>
23#include <mach/control.h>
23#include <mach/board.h> 24#include <mach/board.h>
24#include <mach/mmc.h> 25#include <mach/mmc.h>
25#include <mach/mux.h> 26#include <mach/mux.h>
26#include <mach/gpio.h> 27#include <mach/gpio.h>
27#include <mach/menelaus.h> 28#include <mach/menelaus.h>
28#include <mach/mcbsp.h> 29#include <mach/mcbsp.h>
30#include <mach/dsp_common.h>
29 31
30#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) 32#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
31 33
32#include "../plat-omap/dsp/dsp_common.h"
33
34static struct dsp_platform_data dsp_pdata = { 34static struct dsp_platform_data dsp_pdata = {
35 .kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list), 35 .kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list),
36}; 36};
@@ -76,7 +76,7 @@ int dsp_kfunc_device_register(struct dsp_kfunc_device *kdev)
76{ 76{
77 static DEFINE_MUTEX(dsp_pdata_lock); 77 static DEFINE_MUTEX(dsp_pdata_lock);
78 78
79 mutex_init(&kdev->lock); 79 spin_lock_init(&kdev->lock);
80 80
81 mutex_lock(&dsp_pdata_lock); 81 mutex_lock(&dsp_pdata_lock);
82 list_add_tail(&kdev->entry, &dsp_pdata.kdev_list); 82 list_add_tail(&kdev->entry, &dsp_pdata.kdev_list);
@@ -95,6 +95,10 @@ static inline void omap_init_dsp(void) { }
95 95
96static void omap_init_kp(void) 96static void omap_init_kp(void)
97{ 97{
98 /* 2430 and 34xx keypad is on TWL4030 */
99 if (cpu_is_omap2430() || cpu_is_omap34xx())
100 return;
101
98 if (machine_is_omap_h2() || machine_is_omap_h3()) { 102 if (machine_is_omap_h2() || machine_is_omap_h3()) {
99 omap_cfg_reg(F18_1610_KBC0); 103 omap_cfg_reg(F18_1610_KBC0);
100 omap_cfg_reg(D20_1610_KBC1); 104 omap_cfg_reg(D20_1610_KBC1);
@@ -156,13 +160,6 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
156{ 160{
157 int i; 161 int i;
158 162
159 if (size > OMAP_MAX_MCBSP_COUNT) {
160 printk(KERN_WARNING "Registered too many McBSPs platform_data."
161 " Using maximum (%d) available.\n",
162 OMAP_MAX_MCBSP_COUNT);
163 size = OMAP_MAX_MCBSP_COUNT;
164 }
165
166 omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *), 163 omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *),
167 GFP_KERNEL); 164 GFP_KERNEL);
168 if (!omap_mcbsp_devices) { 165 if (!omap_mcbsp_devices) {
@@ -530,10 +527,6 @@ static inline void omap_init_rng(void) {}
530 */ 527 */
531static int __init omap_init_devices(void) 528static int __init omap_init_devices(void)
532{ 529{
533/*
534 * Need to enable relevant once for 2430 SDP
535 */
536#ifndef CONFIG_MACH_OMAP_2430SDP
537 /* please keep these calls, and their implementations above, 530 /* please keep these calls, and their implementations above,
538 * in alphabetical order so they're easier to sort through. 531 * in alphabetical order so they're easier to sort through.
539 */ 532 */
@@ -543,7 +536,6 @@ static int __init omap_init_devices(void)
543 omap_init_uwire(); 536 omap_init_uwire();
544 omap_init_wdt(); 537 omap_init_wdt();
545 omap_init_rng(); 538 omap_init_rng();
546#endif
547 return 0; 539 return 0;
548} 540}
549arch_initcall(omap_init_devices); 541arch_initcall(omap_init_devices);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index a63b644ad305..50f8b4ad9a09 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1233,7 +1233,7 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
1233 /* request and reserve DMA channels for the chain */ 1233 /* request and reserve DMA channels for the chain */
1234 for (i = 0; i < no_of_chans; i++) { 1234 for (i = 0; i < no_of_chans; i++) {
1235 err = omap_request_dma(dev_id, dev_name, 1235 err = omap_request_dma(dev_id, dev_name,
1236 callback, 0, &channels[i]); 1236 callback, NULL, &channels[i]);
1237 if (err < 0) { 1237 if (err < 0) {
1238 int j; 1238 int j;
1239 for (j = 0; j < i; j++) 1239 for (j = 0; j < i; j++)
@@ -2297,13 +2297,13 @@ static int __init omap_init_dma(void)
2297 int ch, r; 2297 int ch, r;
2298 2298
2299 if (cpu_class_is_omap1()) { 2299 if (cpu_class_is_omap1()) {
2300 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP1_DMA_BASE); 2300 omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
2301 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; 2301 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2302 } else if (cpu_is_omap24xx()) { 2302 } else if (cpu_is_omap24xx()) {
2303 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP24XX_DMA4_BASE); 2303 omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
2304 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; 2304 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2305 } else if (cpu_is_omap34xx()) { 2305 } else if (cpu_is_omap34xx()) {
2306 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP34XX_DMA4_BASE); 2306 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
2307 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; 2307 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2308 } else { 2308 } else {
2309 pr_err("DMA init failed for unsupported omap\n"); 2309 pr_err("DMA init failed for unsupported omap\n");
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 606fcffdcefc..963c31cd1541 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -693,7 +693,7 @@ int __init omap_dm_timer_init(void)
693 693
694 for (i = 0; i < dm_timer_count; i++) { 694 for (i = 0; i < dm_timer_count; i++) {
695 timer = &dm_timers[i]; 695 timer = &dm_timers[i];
696 timer->io_base = (void __iomem *)io_p2v(timer->phys_base); 696 timer->io_base = IO_ADDRESS(timer->phys_base);
697#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 697#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
698 if (cpu_class_is_omap2()) { 698 if (cpu_class_is_omap2()) {
699 char clk_name[16]; 699 char clk_name[16];
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 5935ae4e550b..8679fbca6bbe 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -28,7 +28,7 @@
28/* 28/*
29 * OMAP1510 GPIO registers 29 * OMAP1510 GPIO registers
30 */ 30 */
31#define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000 31#define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
32#define OMAP1510_GPIO_DATA_INPUT 0x00 32#define OMAP1510_GPIO_DATA_INPUT 0x00
33#define OMAP1510_GPIO_DATA_OUTPUT 0x04 33#define OMAP1510_GPIO_DATA_OUTPUT 0x04
34#define OMAP1510_GPIO_DIR_CONTROL 0x08 34#define OMAP1510_GPIO_DIR_CONTROL 0x08
@@ -42,10 +42,10 @@
42/* 42/*
43 * OMAP1610 specific GPIO registers 43 * OMAP1610 specific GPIO registers
44 */ 44 */
45#define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400 45#define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
46#define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00 46#define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
47#define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400 47#define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
48#define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00 48#define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
49#define OMAP1610_GPIO_REVISION 0x0000 49#define OMAP1610_GPIO_REVISION 0x0000
50#define OMAP1610_GPIO_SYSCONFIG 0x0010 50#define OMAP1610_GPIO_SYSCONFIG 0x0010
51#define OMAP1610_GPIO_SYSSTATUS 0x0014 51#define OMAP1610_GPIO_SYSSTATUS 0x0014
@@ -67,12 +67,12 @@
67/* 67/*
68 * OMAP730 specific GPIO registers 68 * OMAP730 specific GPIO registers
69 */ 69 */
70#define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000 70#define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
71#define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800 71#define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
72#define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000 72#define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
73#define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800 73#define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
74#define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000 74#define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
75#define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800 75#define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
76#define OMAP730_GPIO_DATA_INPUT 0x00 76#define OMAP730_GPIO_DATA_INPUT 0x00
77#define OMAP730_GPIO_DATA_OUTPUT 0x04 77#define OMAP730_GPIO_DATA_OUTPUT 0x04
78#define OMAP730_GPIO_DIR_CONTROL 0x08 78#define OMAP730_GPIO_DIR_CONTROL 0x08
@@ -83,16 +83,16 @@
83/* 83/*
84 * omap24xx specific GPIO registers 84 * omap24xx specific GPIO registers
85 */ 85 */
86#define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000 86#define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
87#define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000 87#define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
88#define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000 88#define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
89#define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000 89#define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
90 90
91#define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000 91#define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
92#define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000 92#define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
93#define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000 93#define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
94#define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000 94#define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
95#define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000 95#define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
96 96
97#define OMAP24XX_GPIO_REVISION 0x0000 97#define OMAP24XX_GPIO_REVISION 0x0000
98#define OMAP24XX_GPIO_SYSCONFIG 0x0010 98#define OMAP24XX_GPIO_SYSCONFIG 0x0010
@@ -122,13 +122,14 @@
122 * omap34xx specific GPIO registers 122 * omap34xx specific GPIO registers
123 */ 123 */
124 124
125#define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000 125#define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
126#define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000 126#define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
127#define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000 127#define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
128#define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000 128#define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
129#define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000 129#define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
130#define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000 130#define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
131 131
132#define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
132 133
133struct gpio_bank { 134struct gpio_bank {
134 void __iomem *base; 135 void __iomem *base;
@@ -160,7 +161,7 @@ struct gpio_bank {
160 161
161#ifdef CONFIG_ARCH_OMAP16XX 162#ifdef CONFIG_ARCH_OMAP16XX
162static struct gpio_bank gpio_bank_1610[5] = { 163static struct gpio_bank gpio_bank_1610[5] = {
163 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, 164 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
164 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, 165 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
165 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, 166 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
166 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, 167 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
@@ -170,14 +171,14 @@ static struct gpio_bank gpio_bank_1610[5] = {
170 171
171#ifdef CONFIG_ARCH_OMAP15XX 172#ifdef CONFIG_ARCH_OMAP15XX
172static struct gpio_bank gpio_bank_1510[2] = { 173static struct gpio_bank gpio_bank_1510[2] = {
173 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 174 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
174 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } 175 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
175}; 176};
176#endif 177#endif
177 178
178#ifdef CONFIG_ARCH_OMAP730 179#ifdef CONFIG_ARCH_OMAP730
179static struct gpio_bank gpio_bank_730[7] = { 180static struct gpio_bank gpio_bank_730[7] = {
180 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 181 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
181 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, 182 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
182 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, 183 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
183 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, 184 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
@@ -1389,7 +1390,7 @@ static int __init _omap_gpio_init(void)
1389 1390
1390 gpio_bank_count = 5; 1391 gpio_bank_count = 5;
1391 gpio_bank = gpio_bank_1610; 1392 gpio_bank = gpio_bank_1610;
1392 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); 1393 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1393 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", 1394 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1394 (rev >> 4) & 0x0f, rev & 0x0f); 1395 (rev >> 4) & 0x0f, rev & 0x0f);
1395 } 1396 }
@@ -1408,7 +1409,7 @@ static int __init _omap_gpio_init(void)
1408 1409
1409 gpio_bank_count = 4; 1410 gpio_bank_count = 4;
1410 gpio_bank = gpio_bank_242x; 1411 gpio_bank = gpio_bank_242x;
1411 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1412 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1412 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n", 1413 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1413 (rev >> 4) & 0x0f, rev & 0x0f); 1414 (rev >> 4) & 0x0f, rev & 0x0f);
1414 } 1415 }
@@ -1417,7 +1418,7 @@ static int __init _omap_gpio_init(void)
1417 1418
1418 gpio_bank_count = 5; 1419 gpio_bank_count = 5;
1419 gpio_bank = gpio_bank_243x; 1420 gpio_bank = gpio_bank_243x;
1420 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1421 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1421 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n", 1422 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1422 (rev >> 4) & 0x0f, rev & 0x0f); 1423 (rev >> 4) & 0x0f, rev & 0x0f);
1423 } 1424 }
@@ -1428,7 +1429,7 @@ static int __init _omap_gpio_init(void)
1428 1429
1429 gpio_bank_count = OMAP34XX_NR_GPIOS; 1430 gpio_bank_count = OMAP34XX_NR_GPIOS;
1430 gpio_bank = gpio_bank_34xx; 1431 gpio_bank = gpio_bank_34xx;
1431 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1432 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1432 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n", 1433 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1433 (rev >> 4) & 0x0f, rev & 0x0f); 1434 (rev >> 4) & 0x0f, rev & 0x0f);
1434 } 1435 }
@@ -1437,10 +1438,9 @@ static int __init _omap_gpio_init(void)
1437 int j, gpio_count = 16; 1438 int j, gpio_count = 16;
1438 1439
1439 bank = &gpio_bank[i]; 1440 bank = &gpio_bank[i];
1440 bank->base = IO_ADDRESS(bank->base);
1441 spin_lock_init(&bank->lock); 1441 spin_lock_init(&bank->lock);
1442 if (bank_is_mpuio(bank)) 1442 if (bank_is_mpuio(bank))
1443 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT); 1443 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1444 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { 1444 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1445 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); 1445 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1446 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); 1446 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
diff --git a/arch/arm/plat-omap/include/mach/board-2430sdp.h b/arch/arm/plat-omap/include/mach/board-2430sdp.h
index cf1dc0223949..10d449ea7ed0 100644
--- a/arch/arm/plat-omap/include/mach/board-2430sdp.h
+++ b/arch/arm/plat-omap/include/mach/board-2430sdp.h
@@ -30,10 +30,12 @@
30#define __ASM_ARCH_OMAP_2430SDP_H 30#define __ASM_ARCH_OMAP_2430SDP_H
31 31
32/* Placeholder for 2430SDP specific defines */ 32/* Placeholder for 2430SDP specific defines */
33#define OMAP24XX_ETHR_START 0x08000300 33#define OMAP24XX_ETHR_START 0x08000300
34#define OMAP24XX_ETHR_GPIO_IRQ 149 34#define OMAP24XX_ETHR_GPIO_IRQ 149
35#define SDP2430_CS0_BASE 0x04000000 35#define SDP2430_CS0_BASE 0x04000000
36 36
37#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ 37/* Function prototypes */
38extern void sdp2430_flash_init(void);
39extern void sdp2430_usb_init(void);
38 40
39#endif /* __ASM_ARCH_OMAP_2430SDP_H */ 41#endif /* __ASM_ARCH_OMAP_2430SDP_H */
diff --git a/arch/arm/plat-omap/include/mach/board-apollon.h b/arch/arm/plat-omap/include/mach/board-apollon.h
index d6f2a8e963d5..731c858cf3fe 100644
--- a/arch/arm/plat-omap/include/mach/board-apollon.h
+++ b/arch/arm/plat-omap/include/mach/board-apollon.h
@@ -31,6 +31,12 @@
31 31
32extern void apollon_mmc_init(void); 32extern void apollon_mmc_init(void);
33 33
34static inline int apollon_plus(void)
35{
36 /* The apollon plus has IDCODE revision 5 */
37 return system_rev & 0xc0;
38}
39
34/* Placeholder for APOLLON specific defines */ 40/* Placeholder for APOLLON specific defines */
35#define APOLLON_ETHR_GPIO_IRQ 74 41#define APOLLON_ETHR_GPIO_IRQ 74
36 42
diff --git a/arch/arm/plat-omap/include/mach/board-h4.h b/arch/arm/plat-omap/include/mach/board-h4.h
index 1470cd3e519b..7c3fa0f0a65e 100644
--- a/arch/arm/plat-omap/include/mach/board-h4.h
+++ b/arch/arm/plat-omap/include/mach/board-h4.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/plat-omap/include/mach/board-h4.h 2 * arch/arm/plat-omap/include/mach/board-h4.h
3 * 3 *
4 * Hardware definitions for TI OMAP1610 H4 board. 4 * Hardware definitions for TI OMAP2420 H4 board.
5 * 5 *
6 * Initial creation by Dirk Behme <dirk.behme@de.bosch.com> 6 * Initial creation by Dirk Behme <dirk.behme@de.bosch.com>
7 * 7 *
@@ -29,6 +29,9 @@
29#ifndef __ASM_ARCH_OMAP_H4_H 29#ifndef __ASM_ARCH_OMAP_H4_H
30#define __ASM_ARCH_OMAP_H4_H 30#define __ASM_ARCH_OMAP_H4_H
31 31
32/* MMC Prototypes */
33extern void h4_mmc_init(void);
34
32/* Placeholder for H4 specific defines */ 35/* Placeholder for H4 specific defines */
33#define OMAP24XX_ETHR_GPIO_IRQ 92 36#define OMAP24XX_ETHR_GPIO_IRQ 92
34#endif /* __ASM_ARCH_OMAP_H4_H */ 37#endif /* __ASM_ARCH_OMAP_H4_H */
diff --git a/arch/arm/plat-omap/include/mach/board-ldp.h b/arch/arm/plat-omap/include/mach/board-ldp.h
new file mode 100644
index 000000000000..66e2746c04ca
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-ldp.h
@@ -0,0 +1,36 @@
1/*
2 * arch/arm/plat-omap/include/mach/board-ldp.h
3 *
4 * Hardware definitions for TI OMAP3 LDP.
5 *
6 * Copyright (C) 2008 Texas Instruments Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_OMAP_LDP_H
30#define __ASM_ARCH_OMAP_LDP_H
31
32extern void twl4030_bci_battery_init(void);
33
34#define TWL4030_IRQNUM INT_34XX_SYS_NIRQ
35
36#endif /* __ASM_ARCH_OMAP_LDP_H */
diff --git a/arch/arm/plat-omap/include/mach/board-omap3beagle.h b/arch/arm/plat-omap/include/mach/board-omap3beagle.h
new file mode 100644
index 000000000000..3080d52d877a
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-omap3beagle.h
@@ -0,0 +1,33 @@
1/*
2 * arch/arm/plat-omap/include/mach/board-omap3beagle.h
3 *
4 * Hardware definitions for TI OMAP3 BEAGLE.
5 *
6 * Initial creation by Syed Mohammed Khasim <khasim@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_OMAP3_BEAGLE_H
30#define __ASM_ARCH_OMAP3_BEAGLE_H
31
32#endif /* __ASM_ARCH_OMAP3_BEAGLE_H */
33
diff --git a/arch/arm/plat-omap/include/mach/board-overo.h b/arch/arm/plat-omap/include/mach/board-overo.h
new file mode 100644
index 000000000000..7ecae66966d1
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-overo.h
@@ -0,0 +1,26 @@
1/*
2 * board-overo.h (Gumstix Overo)
3 *
4 * Initial code: Steve Sakoman <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * You should have received a copy of the GNU General Public License along
12 * with this program; if not, write to the Free Software Foundation, Inc.,
13 * 675 Mass Ave, Cambridge, MA 02139, USA.
14 */
15
16#ifndef __ASM_ARCH_OVERO_H
17#define __ASM_ARCH_OVERO_H
18
19#define OVERO_GPIO_BT_XGATE 15
20#define OVERO_GPIO_W2W_NRESET 16
21#define OVERO_GPIO_BT_NRESET 164
22#define OVERO_GPIO_USBH_CPEN 168
23#define OVERO_GPIO_USBH_NRESET 183
24
25#endif /* ____ASM_ARCH_OVERO_H */
26
diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/mach/board.h
index 54445642f35d..c23c12ccb353 100644
--- a/arch/arm/plat-omap/include/mach/board.h
+++ b/arch/arm/plat-omap/include/mach/board.h
@@ -45,6 +45,8 @@ struct omap_mmc_conf {
45 unsigned cover:1; 45 unsigned cover:1;
46 /* 4 wire signaling is optional, and is only used for SD/SDIO */ 46 /* 4 wire signaling is optional, and is only used for SD/SDIO */
47 unsigned wire4:1; 47 unsigned wire4:1;
48 /* use the internal clock */
49 unsigned internal_clock:1;
48 s16 power_pin; 50 s16 power_pin;
49 s16 switch_pin; 51 s16 switch_pin;
50 s16 wp_pin; 52 s16 wp_pin;
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 92f7c7238fcd..719298554ed7 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -15,6 +15,7 @@
15 15
16struct module; 16struct module;
17struct clk; 17struct clk;
18struct clockdomain;
18 19
19#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 20#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
20 21
@@ -79,6 +80,8 @@ struct clk {
79 u32 clksel_mask; 80 u32 clksel_mask;
80 const struct clksel *clksel; 81 const struct clksel *clksel;
81 struct dpll_data *dpll_data; 82 struct dpll_data *dpll_data;
83 const char *clkdm_name;
84 struct clockdomain *clkdm;
82#else 85#else
83 __u8 rate_offset; 86 __u8 rate_offset;
84 __u8 src_offset; 87 __u8 src_offset;
diff --git a/arch/arm/plat-omap/include/mach/clockdomain.h b/arch/arm/plat-omap/include/mach/clockdomain.h
new file mode 100644
index 000000000000..1f51f0173784
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/clockdomain.h
@@ -0,0 +1,106 @@
1/*
2 * linux/include/asm-arm/arch-omap/clockdomain.h
3 *
4 * OMAP2/3 clockdomain framework functions
5 *
6 * Copyright (C) 2008 Texas Instruments, Inc.
7 * Copyright (C) 2008 Nokia Corporation
8 *
9 * Written by Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
17#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
18
19#include <mach/powerdomain.h>
20#include <mach/clock.h>
21#include <mach/cpu.h>
22
23/* Clockdomain capability flags */
24#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
25#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
26#define CLKDM_CAN_ENABLE_AUTO (1 << 2)
27#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
28
29#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
30#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
31#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
32
33/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
34#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
35#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
36
37/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
38#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
39#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
40#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
41#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
42
43/*
44 * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps
45 * and sleepdeps added when a powerdomain should stay active in hwsup mode;
46 * and conversely, removed when the powerdomain should be allowed to go
47 * inactive in hwsup mode.
48 */
49struct clkdm_pwrdm_autodep {
50
51 /* Name of the powerdomain to add a wkdep/sleepdep on */
52 const char *pwrdm_name;
53
54 /* Powerdomain pointer (looked up at clkdm_init() time) */
55 struct powerdomain *pwrdm;
56
57 /* OMAP chip types that this clockdomain dep is valid on */
58 const struct omap_chip_id omap_chip;
59
60};
61
62struct clockdomain {
63
64 /* Clockdomain name */
65 const char *name;
66
67 /* Powerdomain enclosing this clockdomain */
68 const char *pwrdm_name;
69
70 /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
71 const u16 clktrctrl_mask;
72
73 /* Clockdomain capability flags */
74 const u8 flags;
75
76 /* OMAP chip types that this clockdomain is valid on */
77 const struct omap_chip_id omap_chip;
78
79 /* Usecount tracking */
80 atomic_t usecount;
81
82 /* Powerdomain pointer assigned at clkdm_register() */
83 struct powerdomain *pwrdm;
84
85 struct list_head node;
86
87};
88
89void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps);
90int clkdm_register(struct clockdomain *clkdm);
91int clkdm_unregister(struct clockdomain *clkdm);
92struct clockdomain *clkdm_lookup(const char *name);
93
94int clkdm_for_each(int (*fn)(struct clockdomain *clkdm));
95struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
96
97void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
98void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
99
100int omap2_clkdm_wakeup(struct clockdomain *clkdm);
101int omap2_clkdm_sleep(struct clockdomain *clkdm);
102
103int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
104int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
105
106#endif
diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/mach/common.h
index 06093112b665..ef70e2b0f054 100644
--- a/arch/arm/plat-omap/include/mach/common.h
+++ b/arch/arm/plat-omap/include/mach/common.h
@@ -34,6 +34,7 @@ struct sys_timer;
34extern void omap_map_common_io(void); 34extern void omap_map_common_io(void);
35extern struct sys_timer omap_timer; 35extern struct sys_timer omap_timer;
36extern void omap_serial_init(void); 36extern void omap_serial_init(void);
37extern void omap_serial_enable_clocks(int enable);
37#ifdef CONFIG_I2C_OMAP 38#ifdef CONFIG_I2C_OMAP
38extern int omap_register_i2c_bus(int bus_id, u32 clkrate, 39extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
39 struct i2c_board_info const *info, 40 struct i2c_board_info const *info,
@@ -49,6 +50,7 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
49 50
50/* IO bases for various OMAP processors */ 51/* IO bases for various OMAP processors */
51struct omap_globals { 52struct omap_globals {
53 u32 class; /* OMAP class to detect */
52 void __iomem *tap; /* Control module ID code */ 54 void __iomem *tap; /* Control module ID code */
53 void __iomem *sdrc; /* SDRAM Controller */ 55 void __iomem *sdrc; /* SDRAM Controller */
54 void __iomem *sms; /* SDRAM Memory Scheduler */ 56 void __iomem *sms; /* SDRAM Memory Scheduler */
@@ -62,6 +64,7 @@ void omap2_set_globals_243x(void);
62void omap2_set_globals_343x(void); 64void omap2_set_globals_343x(void);
63 65
64/* These get called from omap2_set_globals_xxxx(), do not call these */ 66/* These get called from omap2_set_globals_xxxx(), do not call these */
67void omap2_set_globals_tap(struct omap_globals *);
65void omap2_set_globals_memory(struct omap_globals *); 68void omap2_set_globals_memory(struct omap_globals *);
66void omap2_set_globals_control(struct omap_globals *); 69void omap2_set_globals_control(struct omap_globals *);
67void omap2_set_globals_prcm(struct omap_globals *); 70void omap2_set_globals_prcm(struct omap_globals *);
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h
index e3fd62d9a995..dc9886760577 100644
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/mach/control.h
@@ -1,13 +1,10 @@
1#ifndef __ASM_ARCH_CONTROL_H
2#define __ASM_ARCH_CONTROL_H
3
4/* 1/*
5 * arch/arm/plat-omap/include/mach/control.h 2 * arch/arm/plat-omap/include/mach/control.h
6 * 3 *
7 * OMAP2/3 System Control Module definitions 4 * OMAP2/3 System Control Module definitions
8 * 5 *
9 * Copyright (C) 2007 Texas Instruments, Inc. 6 * Copyright (C) 2007-2008 Texas Instruments, Inc.
10 * Copyright (C) 2007 Nokia Corporation 7 * Copyright (C) 2007-2008 Nokia Corporation
11 * 8 *
12 * Written by Paul Walmsley 9 * Written by Paul Walmsley
13 * 10 *
@@ -16,14 +13,23 @@
16 * the Free Software Foundation. 13 * the Free Software Foundation.
17 */ 14 */
18 15
16#ifndef __ASM_ARCH_CONTROL_H
17#define __ASM_ARCH_CONTROL_H
18
19#include <mach/io.h> 19#include <mach/io.h>
20 20
21#ifndef __ASSEMBLY__
21#define OMAP242X_CTRL_REGADDR(reg) \ 22#define OMAP242X_CTRL_REGADDR(reg) \
22 (void __iomem *)IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 23 IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
23#define OMAP243X_CTRL_REGADDR(reg) \ 24#define OMAP243X_CTRL_REGADDR(reg) \
24 (void __iomem *)IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 25 IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
25#define OMAP343X_CTRL_REGADDR(reg) \ 26#define OMAP343X_CTRL_REGADDR(reg) \
26 (void __iomem *)IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 27 IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
28#else
29#define OMAP242X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
30#define OMAP243X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
31#define OMAP343X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
32#endif /* __ASSEMBLY__ */
27 33
28/* 34/*
29 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for 35 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
@@ -134,6 +140,7 @@
134#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) 140#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
135#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 141#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
136#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 142#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
143#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4)
137 144
138/* 145/*
139 * REVISIT: This list of registers is not comprehensive - there are more 146 * REVISIT: This list of registers is not comprehensive - there are more
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
index 05aee0eda34f..e0464187209d 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -346,9 +346,14 @@ IS_OMAP_TYPE(3430, 0x3430)
346 get_sil_revision(system_rev) 346 get_sil_revision(system_rev)
347 347
348/* Various silicon macros defined here */ 348/* Various silicon macros defined here */
349#define OMAP242X_CLASS 0x24200000
349#define OMAP2420_REV_ES1_0 0x24200000 350#define OMAP2420_REV_ES1_0 0x24200000
350#define OMAP2420_REV_ES2_0 0x24201000 351#define OMAP2420_REV_ES2_0 0x24201000
352
353#define OMAP243X_CLASS 0x24300000
351#define OMAP2430_REV_ES1_0 0x24300000 354#define OMAP2430_REV_ES1_0 0x24300000
355
356#define OMAP343X_CLASS 0x34300000
352#define OMAP3430_REV_ES1_0 0x34300000 357#define OMAP3430_REV_ES1_0 0x34300000
353#define OMAP3430_REV_ES2_0 0x34301000 358#define OMAP3430_REV_ES2_0 0x34301000
354#define OMAP3430_REV_ES2_1 0x34302000 359#define OMAP3430_REV_ES2_1 0x34302000
diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/plat-omap/include/mach/debug-macro.S
index 1b0039bdeb4e..1b11f5c6a2d9 100644
--- a/arch/arm/plat-omap/include/mach/debug-macro.S
+++ b/arch/arm/plat-omap/include/mach/debug-macro.S
@@ -35,6 +35,18 @@
35#ifdef CONFIG_OMAP_LL_DEBUG_UART3 35#ifdef CONFIG_OMAP_LL_DEBUG_UART3
36 add \rx, \rx, #0x00004000 @ UART 3 36 add \rx, \rx, #0x00004000 @ UART 3
37#endif 37#endif
38
39#elif CONFIG_ARCH_OMAP3
40 moveq \rx, #0x48000000 @ physical base address
41 movne \rx, #0xd8000000 @ virtual base
42 orr \rx, \rx, #0x0006a000
43#ifdef CONFIG_OMAP_LL_DEBUG_UART2
44 add \rx, \rx, #0x00002000 @ UART 2
45#endif
46#ifdef CONFIG_OMAP_LL_DEBUG_UART3
47 add \rx, \rx, #0x00fb0000 @ UART 3
48 add \rx, \rx, #0x00006000
49#endif
38#endif 50#endif
39 .endm 51 .endm
40 52
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
index d4e9043bf201..030118ee204a 100644
--- a/arch/arm/plat-omap/include/mach/entry-macro.S
+++ b/arch/arm/plat-omap/include/mach/entry-macro.S
@@ -55,9 +55,17 @@
551510: 551510:
56 .endm 56 .endm
57 57
58#elif defined(CONFIG_ARCH_OMAP24XX) 58#endif
59#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
59 60
61#if defined(CONFIG_ARCH_OMAP24XX)
60#include <mach/omap24xx.h> 62#include <mach/omap24xx.h>
63#endif
64#if defined(CONFIG_ARCH_OMAP34XX)
65#include <mach/omap34xx.h>
66#endif
67
68#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt number */
61 69
62 .macro disable_fiq 70 .macro disable_fiq
63 .endm 71 .endm
@@ -79,7 +87,7 @@
79 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ 87 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
80 cmp \irqnr, #0x0 88 cmp \irqnr, #0x0
812222: 892222:
82 ldrne \irqnr, [\base, #IRQ_SIR_IRQ] 90 ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
83 91
84 .endm 92 .endm
85 93
diff --git a/arch/arm/plat-omap/include/mach/fpga.h b/arch/arm/plat-omap/include/mach/fpga.h
index c92e4b42b289..f1864a652f7a 100644
--- a/arch/arm/plat-omap/include/mach/fpga.h
+++ b/arch/arm/plat-omap/include/mach/fpga.h
@@ -34,9 +34,9 @@ extern void omap1510_fpga_init_irq(void);
34 * --------------------------------------------------------------------------- 34 * ---------------------------------------------------------------------------
35 */ 35 */
36/* maps in the FPGA registers and the ETHR registers */ 36/* maps in the FPGA registers and the ETHR registers */
37#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ 37#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */
38#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ 38#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
39#define H2P2_DBG_FPGA_START 0x04000000 /* PA */ 39#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
40 40
41#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) 41#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
42#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ 42#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
@@ -85,9 +85,9 @@ struct h2p2_dbg_fpga {
85 * OMAP-1510 FPGA 85 * OMAP-1510 FPGA
86 * --------------------------------------------------------------------------- 86 * ---------------------------------------------------------------------------
87 */ 87 */
88#define OMAP1510_FPGA_BASE 0xE8000000 /* Virtual */ 88#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */
89#define OMAP1510_FPGA_SIZE SZ_4K 89#define OMAP1510_FPGA_SIZE SZ_4K
90#define OMAP1510_FPGA_START 0x08000000 /* Physical */ 90#define OMAP1510_FPGA_START 0x08000000 /* PA */
91 91
92/* Revision */ 92/* Revision */
93#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0) 93#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h
index 8c71e288860f..98e9008b7e9d 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/mach/gpio.h
@@ -29,7 +29,7 @@
29#include <linux/io.h> 29#include <linux/io.h>
30#include <mach/irqs.h> 30#include <mach/irqs.h>
31 31
32#define OMAP_MPUIO_BASE (void __iomem *)0xfffb5000 32#define OMAP_MPUIO_BASE 0xfffb5000
33 33
34#ifdef CONFIG_ARCH_OMAP730 34#ifdef CONFIG_ARCH_OMAP730
35#define OMAP_MPUIO_INPUT_LATCH 0x00 35#define OMAP_MPUIO_INPUT_LATCH 0x00
@@ -76,6 +76,8 @@ extern void omap_free_gpio(int gpio);
76extern void omap_set_gpio_direction(int gpio, int is_input); 76extern void omap_set_gpio_direction(int gpio, int is_input);
77extern void omap_set_gpio_dataout(int gpio, int enable); 77extern void omap_set_gpio_dataout(int gpio, int enable);
78extern int omap_get_gpio_datain(int gpio); 78extern int omap_get_gpio_datain(int gpio);
79extern void omap2_gpio_prepare_for_retention(void);
80extern void omap2_gpio_resume_after_retention(void);
79extern void omap_set_gpio_debounce(int gpio, int enable); 81extern void omap_set_gpio_debounce(int gpio, int enable);
80extern void omap_set_gpio_debounce_time(int gpio, int enable); 82extern void omap_set_gpio_debounce_time(int gpio, int enable);
81 83
diff --git a/arch/arm/plat-omap/include/mach/gpmc.h b/arch/arm/plat-omap/include/mach/gpmc.h
index 6a8e07ffc2d0..45b678439bb7 100644
--- a/arch/arm/plat-omap/include/mach/gpmc.h
+++ b/arch/arm/plat-omap/include/mach/gpmc.h
@@ -11,6 +11,9 @@
11#ifndef __OMAP2_GPMC_H 11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H 12#define __OMAP2_GPMC_H
13 13
14/* Maximum Number of Chip Selects */
15#define GPMC_CS_NUM 8
16
14#define GPMC_CS_CONFIG1 0x00 17#define GPMC_CS_CONFIG1 0x00
15#define GPMC_CS_CONFIG2 0x04 18#define GPMC_CS_CONFIG2 0x04
16#define GPMC_CS_CONFIG3 0x08 19#define GPMC_CS_CONFIG3 0x08
@@ -22,6 +25,9 @@
22#define GPMC_CS_NAND_ADDRESS 0x20 25#define GPMC_CS_NAND_ADDRESS 0x20
23#define GPMC_CS_NAND_DATA 0x24 26#define GPMC_CS_NAND_DATA 0x24
24 27
28#define GPMC_CONFIG 0x50
29#define GPMC_STATUS 0x54
30
25#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) 31#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
26#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) 32#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
27#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) 33#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
@@ -78,9 +84,14 @@ struct gpmc_timings {
78 u16 access; /* Start-cycle to first data valid delay */ 84 u16 access; /* Start-cycle to first data valid delay */
79 u16 rd_cycle; /* Total read cycle time */ 85 u16 rd_cycle; /* Total read cycle time */
80 u16 wr_cycle; /* Total write cycle time */ 86 u16 wr_cycle; /* Total write cycle time */
87
88 /* The following are only on OMAP3430 */
89 u16 wr_access; /* WRACCESSTIME */
90 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
81}; 91};
82 92
83extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); 93extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
94extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
84extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); 95extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
85extern unsigned long gpmc_get_fclk_period(void); 96extern unsigned long gpmc_get_fclk_period(void);
86 97
@@ -92,5 +103,6 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
92extern void gpmc_cs_free(int cs); 103extern void gpmc_cs_free(int cs);
93extern int gpmc_cs_set_reserved(int cs, int reserved); 104extern int gpmc_cs_set_reserved(int cs, int reserved);
94extern int gpmc_cs_reserved(int cs); 105extern int gpmc_cs_reserved(int cs);
106extern void gpmc_init(void);
95 107
96#endif 108#endif
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h
index 07f5d7f21528..6589ddbb63b2 100644
--- a/arch/arm/plat-omap/include/mach/hardware.h
+++ b/arch/arm/plat-omap/include/mach/hardware.h
@@ -89,7 +89,7 @@
89#define DPLL_CTL (0xfffecf00) 89#define DPLL_CTL (0xfffecf00)
90 90
91/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ 91/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
92#define DSP_CONFIG_REG_BASE (0xe1008000) 92#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
93#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) 93#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
94#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) 94#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
95#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) 95#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
@@ -282,8 +282,8 @@
282 282
283#include "omap730.h" 283#include "omap730.h"
284#include "omap1510.h" 284#include "omap1510.h"
285#include "omap24xx.h"
286#include "omap16xx.h" 285#include "omap16xx.h"
286#include "omap24xx.h"
287#include "omap34xx.h" 287#include "omap34xx.h"
288 288
289#ifndef __ASSEMBLER__ 289#ifndef __ASSEMBLER__
@@ -322,6 +322,14 @@
322#include "board-2430sdp.h" 322#include "board-2430sdp.h"
323#endif 323#endif
324 324
325#ifdef CONFIG_MACH_OMAP3_BEAGLE
326#include "board-omap3beagle.h"
327#endif
328
329#ifdef CONFIG_MACH_OMAP_LDP
330#include "board-ldp.h"
331#endif
332
325#ifdef CONFIG_MACH_OMAP_APOLLON 333#ifdef CONFIG_MACH_OMAP_APOLLON
326#include "board-apollon.h" 334#include "board-apollon.h"
327#endif 335#endif
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index 2a30b7d88cde..adc83b7b8205 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -55,14 +55,13 @@
55 55
56#if defined(CONFIG_ARCH_OMAP1) 56#if defined(CONFIG_ARCH_OMAP1)
57 57
58#define IO_PHYS 0xFFFB0000 58#define IO_PHYS 0xFFFB0000
59#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ 59#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
60#define IO_SIZE 0x40000 60#define IO_SIZE 0x40000
61#define IO_VIRT (IO_PHYS - IO_OFFSET) 61#define IO_VIRT (IO_PHYS - IO_OFFSET)
62#define IO_ADDRESS(pa) ((pa) - IO_OFFSET) 62#define __IO_ADDRESS(pa) ((pa) - IO_OFFSET)
63#define OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET) 63#define __OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET)
64#define io_p2v(pa) ((pa) - IO_OFFSET) 64#define io_v2p(va) ((va) + IO_OFFSET)
65#define io_v2p(va) ((va) + IO_OFFSET)
66 65
67#elif defined(CONFIG_ARCH_OMAP2) 66#elif defined(CONFIG_ARCH_OMAP2)
68 67
@@ -74,7 +73,6 @@
74#define L4_24XX_VIRT 0xd8000000 73#define L4_24XX_VIRT 0xd8000000
75#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ 74#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
76 75
77#ifdef CONFIG_ARCH_OMAP2430
78#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */ 76#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */
79#define L4_WK_243X_VIRT 0xd9000000 77#define L4_WK_243X_VIRT 0xd9000000
80#define L4_WK_243X_SIZE SZ_1M 78#define L4_WK_243X_SIZE SZ_1M
@@ -88,13 +86,10 @@
88#define OMAP243X_SMS_VIRT 0xFC000000 86#define OMAP243X_SMS_VIRT 0xFC000000
89#define OMAP243X_SMS_SIZE SZ_1M 87#define OMAP243X_SMS_SIZE SZ_1M
90 88
91#endif 89#define IO_OFFSET 0x90000000
92 90#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
93#define IO_OFFSET 0x90000000 91#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
94#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 92#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
95#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
96#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
97#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
98 93
99/* DSP */ 94/* DSP */
100#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */ 95#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
@@ -149,9 +144,8 @@
149 144
150 145
151#define IO_OFFSET 0x90000000 146#define IO_OFFSET 0x90000000
152#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ 147#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
153#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ 148#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
154#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
155#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */ 149#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
156 150
157/* DSP */ 151/* DSP */
@@ -167,7 +161,14 @@
167 161
168#endif 162#endif
169 163
170#ifndef __ASSEMBLER__ 164#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
165#define OMAP1_IO_ADDRESS(pa) IOMEM(__OMAP1_IO_ADDRESS(pa))
166#define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa))
167
168#ifdef __ASSEMBLER__
169#define IOMEM(x) x
170#else
171#define IOMEM(x) ((void __force __iomem *)(x))
171 172
172/* 173/*
173 * Functions to access the OMAP IO region 174 * Functions to access the OMAP IO region
@@ -178,13 +179,13 @@
178 * - DO NOT use hardcoded virtual addresses to allow changing the 179 * - DO NOT use hardcoded virtual addresses to allow changing the
179 * IO address space again if needed 180 * IO address space again if needed
180 */ 181 */
181#define omap_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) 182#define omap_readb(a) __raw_readb(IO_ADDRESS(a))
182#define omap_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) 183#define omap_readw(a) __raw_readw(IO_ADDRESS(a))
183#define omap_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) 184#define omap_readl(a) __raw_readl(IO_ADDRESS(a))
184 185
185#define omap_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) 186#define omap_writeb(v,a) __raw_writeb(v, IO_ADDRESS(a))
186#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) 187#define omap_writew(v,a) __raw_writew(v, IO_ADDRESS(a))
187#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) 188#define omap_writel(v,a) __raw_writel(v, IO_ADDRESS(a))
188 189
189extern void omap1_map_common_io(void); 190extern void omap1_map_common_io(void);
190extern void omap1_init_common_hw(void); 191extern void omap1_init_common_hw(void);
@@ -192,6 +193,12 @@ extern void omap1_init_common_hw(void);
192extern void omap2_map_common_io(void); 193extern void omap2_map_common_io(void);
193extern void omap2_init_common_hw(void); 194extern void omap2_init_common_hw(void);
194 195
196#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
197#define __arch_iounmap(v) omap_iounmap(v)
198
199void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
200void omap_iounmap(volatile void __iomem *addr);
201
195#endif 202#endif
196 203
197#endif 204#endif
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index 62aa7dfb9464..a2929ac8c687 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -125,6 +125,7 @@
125#define INT_UART2 (15 + IH2_BASE) 125#define INT_UART2 (15 + IH2_BASE)
126#define INT_BT_MCSI1TX (16 + IH2_BASE) 126#define INT_BT_MCSI1TX (16 + IH2_BASE)
127#define INT_BT_MCSI1RX (17 + IH2_BASE) 127#define INT_BT_MCSI1RX (17 + IH2_BASE)
128#define INT_SOSSI_MATCH (19 + IH2_BASE)
128#define INT_USB_W2FC (20 + IH2_BASE) 129#define INT_USB_W2FC (20 + IH2_BASE)
129#define INT_1WIRE (21 + IH2_BASE) 130#define INT_1WIRE (21 + IH2_BASE)
130#define INT_OS_TIMER (22 + IH2_BASE) 131#define INT_OS_TIMER (22 + IH2_BASE)
@@ -176,6 +177,7 @@
176#define INT_1610_DMA_CH14 (61 + IH2_BASE) 177#define INT_1610_DMA_CH14 (61 + IH2_BASE)
177#define INT_1610_DMA_CH15 (62 + IH2_BASE) 178#define INT_1610_DMA_CH15 (62 + IH2_BASE)
178#define INT_1610_NAND (63 + IH2_BASE) 179#define INT_1610_NAND (63 + IH2_BASE)
180#define INT_1610_SHA1MD5 (91 + IH2_BASE)
179 181
180/* 182/*
181 * OMAP-730 specific IRQ numbers for interrupt handler 2 183 * OMAP-730 specific IRQ numbers for interrupt handler 2
@@ -263,12 +265,18 @@
263#define INT_24XX_GPTIMER10 46 265#define INT_24XX_GPTIMER10 46
264#define INT_24XX_GPTIMER11 47 266#define INT_24XX_GPTIMER11 47
265#define INT_24XX_GPTIMER12 48 267#define INT_24XX_GPTIMER12 48
268#define INT_24XX_SHA1MD5 51
269#define INT_24XX_MCBSP4_IRQ_TX 54
270#define INT_24XX_MCBSP4_IRQ_RX 55
266#define INT_24XX_I2C1_IRQ 56 271#define INT_24XX_I2C1_IRQ 56
267#define INT_24XX_I2C2_IRQ 57 272#define INT_24XX_I2C2_IRQ 57
273#define INT_24XX_HDQ_IRQ 58
268#define INT_24XX_MCBSP1_IRQ_TX 59 274#define INT_24XX_MCBSP1_IRQ_TX 59
269#define INT_24XX_MCBSP1_IRQ_RX 60 275#define INT_24XX_MCBSP1_IRQ_RX 60
270#define INT_24XX_MCBSP2_IRQ_TX 62 276#define INT_24XX_MCBSP2_IRQ_TX 62
271#define INT_24XX_MCBSP2_IRQ_RX 63 277#define INT_24XX_MCBSP2_IRQ_RX 63
278#define INT_24XX_SPI1_IRQ 65
279#define INT_24XX_SPI2_IRQ 66
272#define INT_24XX_UART1_IRQ 72 280#define INT_24XX_UART1_IRQ 72
273#define INT_24XX_UART2_IRQ 73 281#define INT_24XX_UART2_IRQ 73
274#define INT_24XX_UART3_IRQ 74 282#define INT_24XX_UART3_IRQ 74
@@ -278,7 +286,58 @@
278#define INT_24XX_USB_IRQ_HGEN 78 286#define INT_24XX_USB_IRQ_HGEN 78
279#define INT_24XX_USB_IRQ_HSOF 79 287#define INT_24XX_USB_IRQ_HSOF 79
280#define INT_24XX_USB_IRQ_OTG 80 288#define INT_24XX_USB_IRQ_OTG 80
289#define INT_24XX_MCBSP5_IRQ_TX 81
290#define INT_24XX_MCBSP5_IRQ_RX 82
281#define INT_24XX_MMC_IRQ 83 291#define INT_24XX_MMC_IRQ 83
292#define INT_24XX_MMC2_IRQ 86
293#define INT_24XX_MCBSP3_IRQ_TX 89
294#define INT_24XX_MCBSP3_IRQ_RX 90
295#define INT_24XX_SPI3_IRQ 91
296
297#define INT_243X_MCBSP2_IRQ 16
298#define INT_243X_MCBSP3_IRQ 17
299#define INT_243X_MCBSP4_IRQ 18
300#define INT_243X_MCBSP5_IRQ 19
301#define INT_243X_MCBSP1_IRQ 64
302#define INT_243X_HS_USB_MC 92
303#define INT_243X_HS_USB_DMA 93
304#define INT_243X_CARKIT_IRQ 94
305
306#define INT_34XX_BENCH_MPU_EMUL 3
307#define INT_34XX_ST_MCBSP2_IRQ 4
308#define INT_34XX_ST_MCBSP3_IRQ 5
309#define INT_34XX_SSM_ABORT_IRQ 6
310#define INT_34XX_SYS_NIRQ 7
311#define INT_34XX_D2D_FW_IRQ 8
312#define INT_34XX_PRCM_MPU_IRQ 11
313#define INT_34XX_MCBSP1_IRQ 16
314#define INT_34XX_MCBSP2_IRQ 17
315#define INT_34XX_MCBSP3_IRQ 22
316#define INT_34XX_MCBSP4_IRQ 23
317#define INT_34XX_CAM_IRQ 24
318#define INT_34XX_MCBSP5_IRQ 27
319#define INT_34XX_GPIO_BANK1 29
320#define INT_34XX_GPIO_BANK2 30
321#define INT_34XX_GPIO_BANK3 31
322#define INT_34XX_GPIO_BANK4 32
323#define INT_34XX_GPIO_BANK5 33
324#define INT_34XX_GPIO_BANK6 34
325#define INT_34XX_USIM_IRQ 35
326#define INT_34XX_WDT3_IRQ 36
327#define INT_34XX_SPI4_IRQ 48
328#define INT_34XX_SHA1MD52_IRQ 49
329#define INT_34XX_FPKA_READY_IRQ 50
330#define INT_34XX_SHA1MD51_IRQ 51
331#define INT_34XX_RNG_IRQ 52
332#define INT_34XX_I2C3_IRQ 61
333#define INT_34XX_FPKA_ERROR_IRQ 64
334#define INT_34XX_PBIAS_IRQ 75
335#define INT_34XX_OHCI_IRQ 76
336#define INT_34XX_EHCI_IRQ 77
337#define INT_34XX_TLL_IRQ 78
338#define INT_34XX_PARTHASH_IRQ 79
339#define INT_34XX_MMC3_IRQ 94
340#define INT_34XX_GPT12_IRQ 95
282 341
283#define INT_34XX_BENCH_MPU_EMUL 3 342#define INT_34XX_BENCH_MPU_EMUL 3
284 343
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index 8fdb95e26fcd..6a0d1a0a24a7 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -43,9 +43,15 @@
43 43
44#define OMAP24XX_MCBSP1_BASE 0x48074000 44#define OMAP24XX_MCBSP1_BASE 0x48074000
45#define OMAP24XX_MCBSP2_BASE 0x48076000 45#define OMAP24XX_MCBSP2_BASE 0x48076000
46#define OMAP2430_MCBSP3_BASE 0x4808c000
47#define OMAP2430_MCBSP4_BASE 0x4808e000
48#define OMAP2430_MCBSP5_BASE 0x48096000
46 49
47#define OMAP34XX_MCBSP1_BASE 0x48074000 50#define OMAP34XX_MCBSP1_BASE 0x48074000
48#define OMAP34XX_MCBSP2_BASE 0x49022000 51#define OMAP34XX_MCBSP2_BASE 0x49022000
52#define OMAP34XX_MCBSP3_BASE 0x49024000
53#define OMAP34XX_MCBSP4_BASE 0x49026000
54#define OMAP34XX_MCBSP5_BASE 0x48096000
49 55
50#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) 56#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
51 57
@@ -81,9 +87,6 @@
81#define OMAP_MCBSP_REG_XCERG 0x3A 87#define OMAP_MCBSP_REG_XCERG 0x3A
82#define OMAP_MCBSP_REG_XCERH 0x3C 88#define OMAP_MCBSP_REG_XCERH 0x3C
83 89
84#define OMAP_MAX_MCBSP_COUNT 3
85#define MAX_MCBSP_CLOCKS 3
86
87#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1) 90#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
88#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1) 91#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
89 92
@@ -91,12 +94,14 @@
91#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX 94#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
92#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX 95#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
93 96
94#elif defined(CONFIG_ARCH_OMAP24XX) 97#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
95 98
96#define OMAP_MCBSP_REG_DRR2 0x00 99#define OMAP_MCBSP_REG_DRR2 0x00
97#define OMAP_MCBSP_REG_DRR1 0x04 100#define OMAP_MCBSP_REG_DRR1 0x04
98#define OMAP_MCBSP_REG_DXR2 0x08 101#define OMAP_MCBSP_REG_DXR2 0x08
99#define OMAP_MCBSP_REG_DXR1 0x0C 102#define OMAP_MCBSP_REG_DXR1 0x0C
103#define OMAP_MCBSP_REG_DRR 0x00
104#define OMAP_MCBSP_REG_DXR 0x08
100#define OMAP_MCBSP_REG_SPCR2 0x10 105#define OMAP_MCBSP_REG_SPCR2 0x10
101#define OMAP_MCBSP_REG_SPCR1 0x14 106#define OMAP_MCBSP_REG_SPCR1 0x14
102#define OMAP_MCBSP_REG_RCR2 0x18 107#define OMAP_MCBSP_REG_RCR2 0x18
@@ -124,9 +129,9 @@
124#define OMAP_MCBSP_REG_RCERH 0x70 129#define OMAP_MCBSP_REG_RCERH 0x70
125#define OMAP_MCBSP_REG_XCERG 0x74 130#define OMAP_MCBSP_REG_XCERG 0x74
126#define OMAP_MCBSP_REG_XCERH 0x78 131#define OMAP_MCBSP_REG_XCERH 0x78
127 132#define OMAP_MCBSP_REG_SYSCON 0x8C
128#define OMAP_MAX_MCBSP_COUNT 2 133#define OMAP_MCBSP_REG_XCCR 0xAC
129#define MAX_MCBSP_CLOCKS 2 134#define OMAP_MCBSP_REG_RCCR 0xB0
130 135
131#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) 136#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
132#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) 137#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
@@ -137,10 +142,6 @@
137 142
138#endif 143#endif
139 144
140#define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg)
141#define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg)
142
143
144/************************** McBSP SPCR1 bit definitions ***********************/ 145/************************** McBSP SPCR1 bit definitions ***********************/
145#define RRST 0x0001 146#define RRST 0x0001
146#define RRDY 0x0002 147#define RRDY 0x0002
@@ -151,6 +152,7 @@
151#define DXENA 0x0080 152#define DXENA 0x0080
152#define CLKSTP(value) ((value)<<11) /* bits 11:12 */ 153#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
153#define RJUST(value) ((value)<<13) /* bits 13:14 */ 154#define RJUST(value) ((value)<<13) /* bits 13:14 */
155#define ALB 0x8000
154#define DLB 0x8000 156#define DLB 0x8000
155 157
156/************************** McBSP SPCR2 bit definitions ***********************/ 158/************************** McBSP SPCR2 bit definitions ***********************/
@@ -228,6 +230,17 @@
228#define XPABLK(value) ((value)<<5) /* Bits 5:6 */ 230#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
229#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */ 231#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
230 232
233/*********************** McBSP XCCR bit definitions *************************/
234#define DILB 0x0020
235#define XDMAEN 0x0008
236#define XDISABLE 0x0001
237
238/********************** McBSP RCCR bit definitions *************************/
239#define RDMAEN 0x0008
240#define RDISABLE 0x0001
241
242/********************** McBSP SYSCONFIG bit definitions ********************/
243#define SOFTRST 0x0002
231 244
232/* we don't do multichannel for now */ 245/* we don't do multichannel for now */
233struct omap_mcbsp_reg_cfg { 246struct omap_mcbsp_reg_cfg {
@@ -260,6 +273,8 @@ typedef enum {
260 OMAP_MCBSP1 = 0, 273 OMAP_MCBSP1 = 0,
261 OMAP_MCBSP2, 274 OMAP_MCBSP2,
262 OMAP_MCBSP3, 275 OMAP_MCBSP3,
276 OMAP_MCBSP4,
277 OMAP_MCBSP5
263} omap_mcbsp_id; 278} omap_mcbsp_id;
264 279
265typedef int __bitwise omap_mcbsp_io_type_t; 280typedef int __bitwise omap_mcbsp_io_type_t;
@@ -311,12 +326,10 @@ struct omap_mcbsp_spi_cfg {
311struct omap_mcbsp_ops { 326struct omap_mcbsp_ops {
312 void (*request)(unsigned int); 327 void (*request)(unsigned int);
313 void (*free)(unsigned int); 328 void (*free)(unsigned int);
314 int (*check)(unsigned int);
315}; 329};
316 330
317struct omap_mcbsp_platform_data { 331struct omap_mcbsp_platform_data {
318 unsigned long phys_base; 332 unsigned long phys_base;
319 u32 virt_base;
320 u8 dma_rx_sync, dma_tx_sync; 333 u8 dma_rx_sync, dma_tx_sync;
321 u16 rx_irq, tx_irq; 334 u16 rx_irq, tx_irq;
322 struct omap_mcbsp_ops *ops; 335 struct omap_mcbsp_ops *ops;
@@ -326,7 +339,7 @@ struct omap_mcbsp_platform_data {
326struct omap_mcbsp { 339struct omap_mcbsp {
327 struct device *dev; 340 struct device *dev;
328 unsigned long phys_base; 341 unsigned long phys_base;
329 u32 io_base; 342 void __iomem *io_base;
330 u8 id; 343 u8 id;
331 u8 free; 344 u8 free;
332 omap_mcbsp_word_length rx_word_length; 345 omap_mcbsp_word_length rx_word_length;
@@ -354,6 +367,8 @@ struct omap_mcbsp {
354 struct omap_mcbsp_platform_data *pdata; 367 struct omap_mcbsp_platform_data *pdata;
355 struct clk *clk; 368 struct clk *clk;
356}; 369};
370extern struct omap_mcbsp **mcbsp_ptr;
371extern int omap_mcbsp_count;
357 372
358int omap_mcbsp_init(void); 373int omap_mcbsp_init(void);
359void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, 374void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
@@ -378,5 +393,6 @@ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg *
378/* Polled read/write functions */ 393/* Polled read/write functions */
379int omap_mcbsp_pollread(unsigned int id, u16 * buf); 394int omap_mcbsp_pollread(unsigned int id, u16 * buf);
380int omap_mcbsp_pollwrite(unsigned int id, u16 buf); 395int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
396int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
381 397
382#endif 398#endif
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h
index a325caf80d04..d40cac60b959 100644
--- a/arch/arm/plat-omap/include/mach/memory.h
+++ b/arch/arm/plat-omap/include/mach/memory.h
@@ -38,7 +38,7 @@
38 */ 38 */
39#if defined(CONFIG_ARCH_OMAP1) 39#if defined(CONFIG_ARCH_OMAP1)
40#define PHYS_OFFSET UL(0x10000000) 40#define PHYS_OFFSET UL(0x10000000)
41#elif defined(CONFIG_ARCH_OMAP2) 41#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
42#define PHYS_OFFSET UL(0x80000000) 42#define PHYS_OFFSET UL(0x80000000)
43#endif 43#endif
44 44
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index 614b2c1327c7..6bbf1789bed5 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -125,20 +125,64 @@
125 .pu_pd_val = pull_mode, \ 125 .pu_pd_val = pull_mode, \
126}, 126},
127 127
128 128/* 24xx/34xx mux bit defines */
129#define PULL_DISABLED 0 129#define OMAP2_PULL_ENA (1 << 3)
130#define PULL_ENABLED 1 130#define OMAP2_PULL_UP (1 << 4)
131 131#define OMAP2_ALTELECTRICALSEL (1 << 5)
132#define PULL_DOWN 0 132
133#define PULL_UP 1 133/* 34xx specific mux bit defines */
134#define OMAP3_INPUT_EN (1 << 8)
135#define OMAP3_OFF_EN (1 << 9)
136#define OMAP3_OFFOUT_EN (1 << 10)
137#define OMAP3_OFFOUT_VAL (1 << 11)
138#define OMAP3_OFF_PULL_EN (1 << 12)
139#define OMAP3_OFF_PULL_UP (1 << 13)
140#define OMAP3_WAKEUP_EN (1 << 14)
141
142/* 34xx mux mode options for each pin. See TRM for options */
143#define OMAP34XX_MUX_MODE0 0
144#define OMAP34XX_MUX_MODE1 1
145#define OMAP34XX_MUX_MODE2 2
146#define OMAP34XX_MUX_MODE3 3
147#define OMAP34XX_MUX_MODE4 4
148#define OMAP34XX_MUX_MODE5 5
149#define OMAP34XX_MUX_MODE6 6
150#define OMAP34XX_MUX_MODE7 7
151
152/* 34xx active pin states */
153#define OMAP34XX_PIN_OUTPUT 0
154#define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN
155#define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
156 | OMAP2_PULL_UP)
157#define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
158
159/* 34xx off mode states */
160#define OMAP34XX_PIN_OFF_NONE 0
161#define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
162 | OMAP3_OFFOUT_VAL)
163#define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
164#define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
165 | OMAP3_OFF_PULL_UP)
166#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
167#define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN
168
169#define MUX_CFG_34XX(desc, reg_offset, mux_value) { \
170 .name = desc, \
171 .debug = 0, \
172 .mux_reg = reg_offset, \
173 .mux_val = mux_value \
174},
134 175
135struct pin_config { 176struct pin_config {
136 char *name; 177 char *name;
137 unsigned char busy; 178 const unsigned int mux_reg;
138 unsigned char debug; 179 unsigned char debug;
139 180
140 const char *mux_reg_name; 181#if defined(CONFIG_ARCH_OMAP34XX)
141 const unsigned int mux_reg; 182 u16 mux_val; /* Wake-up, off mode, pull, mux mode */
183#endif
184
185#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
142 const unsigned char mask_offset; 186 const unsigned char mask_offset;
143 const unsigned char mask; 187 const unsigned char mask;
144 188
@@ -150,6 +194,12 @@ struct pin_config {
150 const char *pu_pd_name; 194 const char *pu_pd_name;
151 const unsigned int pu_pd_reg; 195 const unsigned int pu_pd_reg;
152 const unsigned char pu_pd_val; 196 const unsigned char pu_pd_val;
197#endif
198
199#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
200 const char *mux_reg_name;
201#endif
202
153}; 203};
154 204
155enum omap730_index { 205enum omap730_index {
@@ -593,6 +643,114 @@ enum omap24xx_index {
593 643
594}; 644};
595 645
646enum omap34xx_index {
647 /* 34xx I2C */
648 K21_34XX_I2C1_SCL,
649 J21_34XX_I2C1_SDA,
650 AF15_34XX_I2C2_SCL,
651 AE15_34XX_I2C2_SDA,
652 AF14_34XX_I2C3_SCL,
653 AG14_34XX_I2C3_SDA,
654 AD26_34XX_I2C4_SCL,
655 AE26_34XX_I2C4_SDA,
656
657 /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
658 Y8_3430_USB1HS_PHY_CLK,
659 Y9_3430_USB1HS_PHY_STP,
660 AA14_3430_USB1HS_PHY_DIR,
661 AA11_3430_USB1HS_PHY_NXT,
662 W13_3430_USB1HS_PHY_DATA0,
663 W12_3430_USB1HS_PHY_DATA1,
664 W11_3430_USB1HS_PHY_DATA2,
665 Y11_3430_USB1HS_PHY_DATA3,
666 W9_3430_USB1HS_PHY_DATA4,
667 Y12_3430_USB1HS_PHY_DATA5,
668 W8_3430_USB1HS_PHY_DATA6,
669 Y13_3430_USB1HS_PHY_DATA7,
670
671 /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
672 AA8_3430_USB2HS_PHY_CLK,
673 AA10_3430_USB2HS_PHY_STP,
674 AA9_3430_USB2HS_PHY_DIR,
675 AB11_3430_USB2HS_PHY_NXT,
676 AB10_3430_USB2HS_PHY_DATA0,
677 AB9_3430_USB2HS_PHY_DATA1,
678 W3_3430_USB2HS_PHY_DATA2,
679 T4_3430_USB2HS_PHY_DATA3,
680 T3_3430_USB2HS_PHY_DATA4,
681 R3_3430_USB2HS_PHY_DATA5,
682 R4_3430_USB2HS_PHY_DATA6,
683 T2_3430_USB2HS_PHY_DATA7,
684
685
686 /* TLL - HSUSB: 12-pin TLL Port 1*/
687 Y8_3430_USB1HS_TLL_CLK,
688 Y9_3430_USB1HS_TLL_STP,
689 AA14_3430_USB1HS_TLL_DIR,
690 AA11_3430_USB1HS_TLL_NXT,
691 W13_3430_USB1HS_TLL_DATA0,
692 W12_3430_USB1HS_TLL_DATA1,
693 W11_3430_USB1HS_TLL_DATA2,
694 Y11_3430_USB1HS_TLL_DATA3,
695 W9_3430_USB1HS_TLL_DATA4,
696 Y12_3430_USB1HS_TLL_DATA5,
697 W8_3430_USB1HS_TLL_DATA6,
698 Y13_3430_USB1HS_TLL_DATA7,
699
700 /* TLL - HSUSB: 12-pin TLL Port 2*/
701 AA8_3430_USB2HS_TLL_CLK,
702 AA10_3430_USB2HS_TLL_STP,
703 AA9_3430_USB2HS_TLL_DIR,
704 AB11_3430_USB2HS_TLL_NXT,
705 AB10_3430_USB2HS_TLL_DATA0,
706 AB9_3430_USB2HS_TLL_DATA1,
707 W3_3430_USB2HS_TLL_DATA2,
708 T4_3430_USB2HS_TLL_DATA3,
709 T3_3430_USB2HS_TLL_DATA4,
710 R3_3430_USB2HS_TLL_DATA5,
711 R4_3430_USB2HS_TLL_DATA6,
712 T2_3430_USB2HS_TLL_DATA7,
713
714 /* TLL - HSUSB: 12-pin TLL Port 3*/
715 AA6_3430_USB3HS_TLL_CLK,
716 AB3_3430_USB3HS_TLL_STP,
717 AA3_3430_USB3HS_TLL_DIR,
718 Y3_3430_USB3HS_TLL_NXT,
719 AA5_3430_USB3HS_TLL_DATA0,
720 Y4_3430_USB3HS_TLL_DATA1,
721 Y5_3430_USB3HS_TLL_DATA2,
722 W5_3430_USB3HS_TLL_DATA3,
723 AB12_3430_USB3HS_TLL_DATA4,
724 AB13_3430_USB3HS_TLL_DATA5,
725 AA13_3430_USB3HS_TLL_DATA6,
726 AA12_3430_USB3HS_TLL_DATA7,
727
728 /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
729 AF10_3430_USB1FS_PHY_MM1_RXDP,
730 AG9_3430_USB1FS_PHY_MM1_RXDM,
731 W13_3430_USB1FS_PHY_MM1_RXRCV,
732 W12_3430_USB1FS_PHY_MM1_TXSE0,
733 W11_3430_USB1FS_PHY_MM1_TXDAT,
734 Y11_3430_USB1FS_PHY_MM1_TXEN_N,
735
736 /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
737 AF7_3430_USB2FS_PHY_MM2_RXDP,
738 AH7_3430_USB2FS_PHY_MM2_RXDM,
739 AB10_3430_USB2FS_PHY_MM2_RXRCV,
740 AB9_3430_USB2FS_PHY_MM2_TXSE0,
741 W3_3430_USB2FS_PHY_MM2_TXDAT,
742 T4_3430_USB2FS_PHY_MM2_TXEN_N,
743
744 /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
745 AH3_3430_USB3FS_PHY_MM3_RXDP,
746 AE3_3430_USB3FS_PHY_MM3_RXDM,
747 AD1_3430_USB3FS_PHY_MM3_RXRCV,
748 AE1_3430_USB3FS_PHY_MM3_TXSE0,
749 AD2_3430_USB3FS_PHY_MM3_TXDAT,
750 AC1_3430_USB3FS_PHY_MM3_TXEN_N,
751
752};
753
596struct omap_mux_cfg { 754struct omap_mux_cfg {
597 struct pin_config *pins; 755 struct pin_config *pins;
598 unsigned long size; 756 unsigned long size;
diff --git a/arch/arm/plat-omap/include/mach/omap1510.h b/arch/arm/plat-omap/include/mach/omap1510.h
index 505a38af8b22..d24004668138 100644
--- a/arch/arm/plat-omap/include/mach/omap1510.h
+++ b/arch/arm/plat-omap/include/mach/omap1510.h
@@ -44,5 +44,7 @@
44#define OMAP1510_DSPREG_SIZE SZ_128K 44#define OMAP1510_DSPREG_SIZE SZ_128K
45#define OMAP1510_DSPREG_START 0xE1000000 45#define OMAP1510_DSPREG_START 0xE1000000
46 46
47#define OMAP1510_DSP_MMU_BASE (0xfffed200)
48
47#endif /* __ASM_ARCH_OMAP15XX_H */ 49#endif /* __ASM_ARCH_OMAP15XX_H */
48 50
diff --git a/arch/arm/plat-omap/include/mach/omap16xx.h b/arch/arm/plat-omap/include/mach/omap16xx.h
index c6c93afb2788..0e69b504c25f 100644
--- a/arch/arm/plat-omap/include/mach/omap16xx.h
+++ b/arch/arm/plat-omap/include/mach/omap16xx.h
@@ -44,6 +44,11 @@
44#define OMAP16XX_DSPREG_SIZE SZ_128K 44#define OMAP16XX_DSPREG_SIZE SZ_128K
45#define OMAP16XX_DSPREG_START 0xE1000000 45#define OMAP16XX_DSPREG_START 0xE1000000
46 46
47#define OMAP16XX_SEC_BASE 0xFFFE4000
48#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
49#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
50#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
51
47/* 52/*
48 * --------------------------------------------------------------------------- 53 * ---------------------------------------------------------------------------
49 * Interrupts 54 * Interrupts
@@ -190,7 +195,7 @@
190#define WSPR_DISABLE_0 (0x0000aaaa) 195#define WSPR_DISABLE_0 (0x0000aaaa)
191#define WSPR_DISABLE_1 (0x00005555) 196#define WSPR_DISABLE_1 (0x00005555)
192 197
193/* Mailbox */ 198#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
194#define OMAP16XX_MAILBOX_BASE (0xfffcf000) 199#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
195 200
196#endif /* __ASM_ARCH_OMAP16XX_H */ 201#endif /* __ASM_ARCH_OMAP16XX_H */
diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/mach/omap24xx.h
index bb8319d66e9f..24335d4932f5 100644
--- a/arch/arm/plat-omap/include/mach/omap24xx.h
+++ b/arch/arm/plat-omap/include/mach/omap24xx.h
@@ -39,7 +39,6 @@
39/* interrupt controller */ 39/* interrupt controller */
40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) 40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
41#define OMAP24XX_IVA_INTC_BASE 0x40000000 41#define OMAP24XX_IVA_INTC_BASE 0x40000000
42#define IRQ_SIR_IRQ 0x0040
43 42
44#define OMAP2420_CTRL_BASE L4_24XX_BASE 43#define OMAP2420_CTRL_BASE L4_24XX_BASE
45#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) 44#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
@@ -48,6 +47,7 @@
48#define OMAP2420_PRM_BASE OMAP2420_CM_BASE 47#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
49#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000) 48#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
50#define OMAP2420_SMS_BASE 0x68008000 49#define OMAP2420_SMS_BASE 0x68008000
50#define OMAP2420_GPMC_BASE 0x6800a000
51 51
52#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000) 52#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
53#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000) 53#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h
index cae037d13079..ec67fb428607 100644
--- a/arch/arm/plat-omap/include/mach/omapfb.h
+++ b/arch/arm/plat-omap/include/mach/omapfb.h
@@ -62,6 +62,7 @@
62#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000 62#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
63#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000 63#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000
64#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000 64#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000
65#define OMAPFB_CAPS_WINDOW_ROTATE 0x00080000
65#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000 66#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000
66 67
67/* Values from DSP must map to lower 16-bits */ 68/* Values from DSP must map to lower 16-bits */
@@ -305,6 +306,7 @@ struct lcd_ctrl {
305 int screen_width, 306 int screen_width,
306 int pos_x, int pos_y, int width, 307 int pos_x, int pos_y, int width,
307 int height, int color_mode); 308 int height, int color_mode);
309 int (*set_rotate) (int angle);
308 int (*setup_mem) (int plane, size_t size, 310 int (*setup_mem) (int plane, size_t size,
309 int mem_type, unsigned long *paddr); 311 int mem_type, unsigned long *paddr);
310 int (*mmap) (struct fb_info *info, 312 int (*mmap) (struct fb_info *info,
@@ -374,6 +376,7 @@ extern struct lcd_ctrl omap1_lcd_ctrl;
374extern struct lcd_ctrl omap2_disp_ctrl; 376extern struct lcd_ctrl omap2_disp_ctrl;
375#endif 377#endif
376 378
379extern void omapfb_reserve_sdram(void);
377extern void omapfb_register_panel(struct lcd_panel *panel); 380extern void omapfb_register_panel(struct lcd_panel *panel);
378extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval); 381extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
379extern void omapfb_notify_clients(struct omapfb_device *fbdev, 382extern void omapfb_notify_clients(struct omapfb_device *fbdev,
diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h
index bfa09325a5ff..768eb6e7abcf 100644
--- a/arch/arm/plat-omap/include/mach/pm.h
+++ b/arch/arm/plat-omap/include/mach/pm.h
@@ -39,11 +39,11 @@
39 * Register and offset definitions to be used in PM assembler code 39 * Register and offset definitions to be used in PM assembler code
40 * ---------------------------------------------------------------------------- 40 * ----------------------------------------------------------------------------
41 */ 41 */
42#define CLKGEN_REG_ASM_BASE io_p2v(0xfffece00) 42#define CLKGEN_REG_ASM_BASE IO_ADDRESS(0xfffece00)
43#define ARM_IDLECT1_ASM_OFFSET 0x04 43#define ARM_IDLECT1_ASM_OFFSET 0x04
44#define ARM_IDLECT2_ASM_OFFSET 0x08 44#define ARM_IDLECT2_ASM_OFFSET 0x08
45 45
46#define TCMIF_ASM_BASE io_p2v(0xfffecc00) 46#define TCMIF_ASM_BASE IO_ADDRESS(0xfffecc00)
47#define EMIFS_CONFIG_ASM_OFFSET 0x0c 47#define EMIFS_CONFIG_ASM_OFFSET 0x0c
48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20 48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
49 49
@@ -135,7 +135,8 @@ extern void omap_pm_suspend(void);
135extern void omap730_cpu_suspend(unsigned short, unsigned short); 135extern void omap730_cpu_suspend(unsigned short, unsigned short);
136extern void omap1510_cpu_suspend(unsigned short, unsigned short); 136extern void omap1510_cpu_suspend(unsigned short, unsigned short);
137extern void omap1610_cpu_suspend(unsigned short, unsigned short); 137extern void omap1610_cpu_suspend(unsigned short, unsigned short);
138extern void omap24xx_cpu_suspend(u32 dll_ctrl, u32 cpu_revision); 138extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
139 void __iomem *sdrc_power);
139extern void omap730_idle_loop_suspend(void); 140extern void omap730_idle_loop_suspend(void);
140extern void omap1510_idle_loop_suspend(void); 141extern void omap1510_idle_loop_suspend(void);
141extern void omap1610_idle_loop_suspend(void); 142extern void omap1610_idle_loop_suspend(void);
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/mach/powerdomain.h
new file mode 100644
index 000000000000..2806a9c8e4d7
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/powerdomain.h
@@ -0,0 +1,166 @@
1/*
2 * OMAP2/3 powerdomain control
3 *
4 * Copyright (C) 2007-8 Texas Instruments, Inc.
5 * Copyright (C) 2007-8 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
15#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
16
17#include <linux/types.h>
18#include <linux/list.h>
19
20#include <asm/atomic.h>
21
22#include <mach/cpu.h>
23
24
25/* Powerdomain basic power states */
26#define PWRDM_POWER_OFF 0x0
27#define PWRDM_POWER_RET 0x1
28#define PWRDM_POWER_INACTIVE 0x2
29#define PWRDM_POWER_ON 0x3
30
31/* Powerdomain allowable state bitfields */
32#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
33 (1 << PWRDM_POWER_ON))
34
35#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
36 (1 << PWRDM_POWER_RET))
37
38#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
39
40
41/* Powerdomain flags */
42#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
43
44
45/*
46 * Number of memory banks that are power-controllable. On OMAP3430, the
47 * maximum is 4.
48 */
49#define PWRDM_MAX_MEM_BANKS 4
50
51/*
52 * Maximum number of clockdomains that can be associated with a powerdomain.
53 * CORE powerdomain is probably the worst case.
54 */
55#define PWRDM_MAX_CLKDMS 3
56
57/* XXX A completely arbitrary number. What is reasonable here? */
58#define PWRDM_TRANSITION_BAILOUT 100000
59
60struct clockdomain;
61struct powerdomain;
62
63/* Encodes dependencies between powerdomains - statically defined */
64struct pwrdm_dep {
65
66 /* Powerdomain name */
67 const char *pwrdm_name;
68
69 /* Powerdomain pointer - resolved by the powerdomain code */
70 struct powerdomain *pwrdm;
71
72 /* Flags to mark OMAP chip restrictions, etc. */
73 const struct omap_chip_id omap_chip;
74
75};
76
77struct powerdomain {
78
79 /* Powerdomain name */
80 const char *name;
81
82 /* the address offset from CM_BASE/PRM_BASE */
83 const s16 prcm_offs;
84
85 /* Used to represent the OMAP chip types containing this pwrdm */
86 const struct omap_chip_id omap_chip;
87
88 /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
89 const u8 dep_bit;
90
91 /* Powerdomains that can be told to wake this powerdomain up */
92 struct pwrdm_dep *wkdep_srcs;
93
94 /* Powerdomains that can be told to keep this pwrdm from inactivity */
95 struct pwrdm_dep *sleepdep_srcs;
96
97 /* Possible powerdomain power states */
98 const u8 pwrsts;
99
100 /* Possible logic power states when pwrdm in RETENTION */
101 const u8 pwrsts_logic_ret;
102
103 /* Powerdomain flags */
104 const u8 flags;
105
106 /* Number of software-controllable memory banks in this powerdomain */
107 const u8 banks;
108
109 /* Possible memory bank pwrstates when pwrdm in RETENTION */
110 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
111
112 /* Possible memory bank pwrstates when pwrdm is ON */
113 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
114
115 /* Clockdomains in this powerdomain */
116 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
117
118 struct list_head node;
119
120};
121
122
123void pwrdm_init(struct powerdomain **pwrdm_list);
124
125int pwrdm_register(struct powerdomain *pwrdm);
126int pwrdm_unregister(struct powerdomain *pwrdm);
127struct powerdomain *pwrdm_lookup(const char *name);
128
129int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm));
130
131int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
132int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
133int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
134 int (*fn)(struct powerdomain *pwrdm,
135 struct clockdomain *clkdm));
136
137int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
138int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
139int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
140int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
141int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
142int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
143
144int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
145
146int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
147int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
148int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
149int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
150
151int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
152int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
153int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
154
155int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
156int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
157int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
158int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
159
160int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
161int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
162bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
163
164int pwrdm_wait_transition(struct powerdomain *pwrdm);
165
166#endif
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
index 787b7acec546..a98c6c3beb2c 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -25,6 +25,8 @@
25#define SDRC_DLLB_STATUS 0x06C 25#define SDRC_DLLB_STATUS 0x06C
26#define SDRC_POWER 0x070 26#define SDRC_POWER 0x070
27#define SDRC_MR_0 0x084 27#define SDRC_MR_0 0x084
28#define SDRC_ACTIM_CTRL_A_0 0x09c
29#define SDRC_ACTIM_CTRL_B_0 0x0a0
28#define SDRC_RFR_CTRL_0 0x0a4 30#define SDRC_RFR_CTRL_0 0x0a4
29 31
30/* 32/*
@@ -63,9 +65,9 @@
63 */ 65 */
64 66
65 67
66#define OMAP242X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg) 68#define OMAP242X_SMS_REGADDR(reg) IO_ADDRESS(OMAP2420_SMS_BASE + reg)
67#define OMAP243X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg) 69#define OMAP243X_SMS_REGADDR(reg) IO_ADDRESS(OMAP243X_SMS_BASE + reg)
68#define OMAP343X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg) 70#define OMAP343X_SMS_REGADDR(reg) IO_ADDRESS(OMAP343X_SMS_BASE + reg)
69 71
70/* SMS register offsets - read/write with sms_{read,write}_reg() */ 72/* SMS register offsets - read/write with sms_{read,write}_reg() */
71 73
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
index cc6bfa51ccb5..8a676a04be48 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/mach/serial.h
@@ -20,18 +20,24 @@
20#define OMAP_UART1_BASE 0x4806a000 20#define OMAP_UART1_BASE 0x4806a000
21#define OMAP_UART2_BASE 0x4806c000 21#define OMAP_UART2_BASE 0x4806c000
22#define OMAP_UART3_BASE 0x4806e000 22#define OMAP_UART3_BASE 0x4806e000
23#elif defined(CONFIG_ARCH_OMAP3)
24/* OMAP3 serial ports */
25#define OMAP_UART1_BASE 0x4806a000
26#define OMAP_UART2_BASE 0x4806c000
27#define OMAP_UART3_BASE 0x49020000
23#endif 28#endif
24 29
25#define OMAP_MAX_NR_PORTS 3 30#define OMAP_MAX_NR_PORTS 3
26#define OMAP1510_BASE_BAUD (12000000/16) 31#define OMAP1510_BASE_BAUD (12000000/16)
27#define OMAP16XX_BASE_BAUD (48000000/16) 32#define OMAP16XX_BASE_BAUD (48000000/16)
33#define OMAP24XX_BASE_BAUD (48000000/16)
28 34
29#define is_omap_port(p) ({int __ret = 0; \ 35#define is_omap_port(pt) ({int __ret = 0; \
30 if (p == IO_ADDRESS(OMAP_UART1_BASE) || \ 36 if ((pt)->port.mapbase == OMAP_UART1_BASE || \
31 p == IO_ADDRESS(OMAP_UART2_BASE) || \ 37 (pt)->port.mapbase == OMAP_UART2_BASE || \
32 p == IO_ADDRESS(OMAP_UART3_BASE)) \ 38 (pt)->port.mapbase == OMAP_UART3_BASE) \
33 __ret = 1; \ 39 __ret = 1; \
34 __ret; \ 40 __ret; \
35 }) 41 })
36 42
37#endif 43#endif
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index e09323449981..ab35d622dcf5 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -21,6 +21,10 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
21 u32 mem_type); 21 u32 mem_type);
22extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 22extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
23 23
24extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
25 u32 sdrc_actim_ctrla,
26 u32 sdrc_actim_ctrlb, u32 m2);
27
24/* Do not use these */ 28/* Do not use these */
25extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); 29extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
26extern unsigned long omap1_sram_reprogram_clock_sz; 30extern unsigned long omap1_sram_reprogram_clock_sz;
@@ -53,4 +57,10 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
53 u32 mem_type); 57 u32 mem_type);
54extern unsigned long omap243x_sram_reprogram_sdrc_sz; 58extern unsigned long omap243x_sram_reprogram_sdrc_sz;
55 59
60
61extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
62 u32 sdrc_actim_ctrla,
63 u32 sdrc_actim_ctrlb, u32 m2);
64extern unsigned long omap3_sram_configure_core_dpll_sz;
65
56#endif 66#endif
diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/mach/system.h
index 06a28c7b98de..06923f261545 100644
--- a/arch/arm/plat-omap/include/mach/system.h
+++ b/arch/arm/plat-omap/include/mach/system.h
@@ -40,7 +40,7 @@ static inline void omap1_arch_reset(char mode)
40 40
41static inline void arch_reset(char mode) 41static inline void arch_reset(char mode)
42{ 42{
43 if (!cpu_is_omap24xx()) 43 if (!cpu_class_is_omap2())
44 omap1_arch_reset(mode); 44 omap1_arch_reset(mode);
45 else 45 else
46 omap_prcm_arch_reset(mode); 46 omap_prcm_arch_reset(mode);
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
new file mode 100644
index 000000000000..af326efc1ad3
--- /dev/null
+++ b/arch/arm/plat-omap/io.c
@@ -0,0 +1,107 @@
1#include <linux/module.h>
2#include <linux/io.h>
3#include <linux/mm.h>
4
5#include <mach/omap730.h>
6#include <mach/omap1510.h>
7#include <mach/omap16xx.h>
8#include <mach/omap24xx.h>
9#include <mach/omap34xx.h>
10
11#define BETWEEN(p,st,sz) ((p) >= (st) && (p) < ((st) + (sz)))
12#define XLATE(p,pst,vst) ((void __iomem *)((p) - (pst) + (vst)))
13
14/*
15 * Intercept ioremap() requests for addresses in our fixed mapping regions.
16 */
17void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
18{
19#ifdef CONFIG_ARCH_OMAP1
20 if (cpu_class_is_omap1()) {
21 if (BETWEEN(p, IO_PHYS, IO_SIZE))
22 return XLATE(p, IO_PHYS, IO_VIRT);
23 }
24 if (cpu_is_omap730()) {
25 if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE))
26 return XLATE(p, OMAP730_DSP_BASE, OMAP730_DSP_START);
27
28 if (BETWEEN(p, OMAP730_DSPREG_BASE, OMAP730_DSPREG_SIZE))
29 return XLATE(p, OMAP730_DSPREG_BASE,
30 OMAP730_DSPREG_START);
31 }
32 if (cpu_is_omap15xx()) {
33 if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
34 return XLATE(p, OMAP1510_DSP_BASE, OMAP1510_DSP_START);
35
36 if (BETWEEN(p, OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_SIZE))
37 return XLATE(p, OMAP1510_DSPREG_BASE,
38 OMAP1510_DSPREG_START);
39 }
40 if (cpu_is_omap16xx()) {
41 if (BETWEEN(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_SIZE))
42 return XLATE(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_START);
43
44 if (BETWEEN(p, OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_SIZE))
45 return XLATE(p, OMAP16XX_DSPREG_BASE,
46 OMAP16XX_DSPREG_START);
47 }
48#endif
49#ifdef CONFIG_ARCH_OMAP2
50 if (cpu_is_omap24xx()) {
51 if (BETWEEN(p, L3_24XX_PHYS, L3_24XX_SIZE))
52 return XLATE(p, L3_24XX_PHYS, L3_24XX_VIRT);
53 if (BETWEEN(p, L4_24XX_PHYS, L4_24XX_SIZE))
54 return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT);
55 }
56 if (cpu_is_omap2420()) {
57 if (BETWEEN(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_SIZE))
58 return XLATE(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_VIRT);
59 if (BETWEEN(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE))
60 return XLATE(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE);
61 if (BETWEEN(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_SIZE))
62 return XLATE(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_VIRT);
63 }
64 if (cpu_is_omap2430()) {
65 if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE))
66 return XLATE(p, L4_WK_243X_PHYS, L4_WK_243X_VIRT);
67 if (BETWEEN(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_SIZE))
68 return XLATE(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT);
69 if (BETWEEN(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_SIZE))
70 return XLATE(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_VIRT);
71 if (BETWEEN(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_SIZE))
72 return XLATE(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_VIRT);
73 }
74#endif
75#ifdef CONFIG_ARCH_OMAP3
76 if (cpu_is_omap34xx()) {
77 if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
78 return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
79 if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
80 return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
81 if (BETWEEN(p, L4_WK_34XX_PHYS, L4_WK_34XX_SIZE))
82 return XLATE(p, L4_WK_34XX_PHYS, L4_WK_34XX_VIRT);
83 if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE))
84 return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT);
85 if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE))
86 return XLATE(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_VIRT);
87 if (BETWEEN(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_SIZE))
88 return XLATE(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_VIRT);
89 if (BETWEEN(p, L4_PER_34XX_PHYS, L4_PER_34XX_SIZE))
90 return XLATE(p, L4_PER_34XX_PHYS, L4_PER_34XX_VIRT);
91 if (BETWEEN(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_SIZE))
92 return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT);
93 }
94#endif
95
96 return __arm_ioremap(p, size, type);
97}
98EXPORT_SYMBOL(omap_ioremap);
99
100void omap_iounmap(volatile void __iomem *addr)
101{
102 unsigned long virt = (unsigned long)addr;
103
104 if (virt >= VMALLOC_START && virt < VMALLOC_END)
105 __iounmap(addr);
106}
107EXPORT_SYMBOL(omap_iounmap);
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 014d26574bb6..af33fc713e1a 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -27,43 +27,65 @@
27#include <mach/dma.h> 27#include <mach/dma.h>
28#include <mach/mcbsp.h> 28#include <mach/mcbsp.h>
29 29
30static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT]; 30struct omap_mcbsp **mcbsp_ptr;
31int omap_mcbsp_count;
31 32
32#define omap_mcbsp_check_valid_id(id) (mcbsp[id].pdata && \ 33void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
33 mcbsp[id].pdata->ops && \ 34{
34 mcbsp[id].pdata->ops->check && \ 35 if (cpu_class_is_omap1() || cpu_is_omap2420())
35 (mcbsp[id].pdata->ops->check(id) == 0)) 36 __raw_writew((u16)val, io_base + reg);
37 else
38 __raw_writel(val, io_base + reg);
39}
40
41int omap_mcbsp_read(void __iomem *io_base, u16 reg)
42{
43 if (cpu_class_is_omap1() || cpu_is_omap2420())
44 return __raw_readw(io_base + reg);
45 else
46 return __raw_readl(io_base + reg);
47}
48
49#define OMAP_MCBSP_READ(base, reg) \
50 omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
51#define OMAP_MCBSP_WRITE(base, reg, val) \
52 omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
53
54#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
55#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
36 56
37static void omap_mcbsp_dump_reg(u8 id) 57static void omap_mcbsp_dump_reg(u8 id)
38{ 58{
39 dev_dbg(mcbsp[id].dev, "**** McBSP%d regs ****\n", mcbsp[id].id); 59 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
40 dev_dbg(mcbsp[id].dev, "DRR2: 0x%04x\n", 60
41 OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2)); 61 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
42 dev_dbg(mcbsp[id].dev, "DRR1: 0x%04x\n", 62 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
43 OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1)); 63 OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
44 dev_dbg(mcbsp[id].dev, "DXR2: 0x%04x\n", 64 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
45 OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2)); 65 OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
46 dev_dbg(mcbsp[id].dev, "DXR1: 0x%04x\n", 66 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
47 OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1)); 67 OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
48 dev_dbg(mcbsp[id].dev, "SPCR2: 0x%04x\n", 68 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
49 OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2)); 69 OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
50 dev_dbg(mcbsp[id].dev, "SPCR1: 0x%04x\n", 70 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
51 OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1)); 71 OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
52 dev_dbg(mcbsp[id].dev, "RCR2: 0x%04x\n", 72 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
53 OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2)); 73 OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
54 dev_dbg(mcbsp[id].dev, "RCR1: 0x%04x\n", 74 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
55 OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1)); 75 OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
56 dev_dbg(mcbsp[id].dev, "XCR2: 0x%04x\n", 76 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
57 OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2)); 77 OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
58 dev_dbg(mcbsp[id].dev, "XCR1: 0x%04x\n", 78 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
59 OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1)); 79 OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
60 dev_dbg(mcbsp[id].dev, "SRGR2: 0x%04x\n", 80 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
61 OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2)); 81 OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
62 dev_dbg(mcbsp[id].dev, "SRGR1: 0x%04x\n", 82 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
63 OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1)); 83 OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
64 dev_dbg(mcbsp[id].dev, "PCR0: 0x%04x\n", 84 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
65 OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0)); 85 OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
66 dev_dbg(mcbsp[id].dev, "***********************\n"); 86 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
87 OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
88 dev_dbg(mcbsp->dev, "***********************\n");
67} 89}
68 90
69static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id) 91static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
@@ -126,16 +148,18 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
126 */ 148 */
127void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config) 149void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
128{ 150{
129 u32 io_base; 151 struct omap_mcbsp *mcbsp;
152 void __iomem *io_base;
130 153
131 if (!omap_mcbsp_check_valid_id(id)) { 154 if (!omap_mcbsp_check_valid_id(id)) {
132 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 155 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
133 return; 156 return;
134 } 157 }
158 mcbsp = id_to_mcbsp_ptr(id);
135 159
136 io_base = mcbsp[id].io_base; 160 io_base = mcbsp->io_base;
137 dev_dbg(mcbsp[id].dev, "Configuring McBSP%d io_base: 0x%8x\n", 161 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
138 mcbsp[id].id, io_base); 162 mcbsp->id, mcbsp->phys_base);
139 163
140 /* We write the given config */ 164 /* We write the given config */
141 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2); 165 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
@@ -158,23 +182,26 @@ EXPORT_SYMBOL(omap_mcbsp_config);
158 */ 182 */
159int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type) 183int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
160{ 184{
185 struct omap_mcbsp *mcbsp;
186
161 if (!omap_mcbsp_check_valid_id(id)) { 187 if (!omap_mcbsp_check_valid_id(id)) {
162 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 188 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
163 return -ENODEV; 189 return -ENODEV;
164 } 190 }
191 mcbsp = id_to_mcbsp_ptr(id);
165 192
166 spin_lock(&mcbsp[id].lock); 193 spin_lock(&mcbsp->lock);
167 194
168 if (!mcbsp[id].free) { 195 if (!mcbsp->free) {
169 dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n", 196 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
170 mcbsp[id].id); 197 mcbsp->id);
171 spin_unlock(&mcbsp[id].lock); 198 spin_unlock(&mcbsp->lock);
172 return -EINVAL; 199 return -EINVAL;
173 } 200 }
174 201
175 mcbsp[id].io_type = io_type; 202 mcbsp->io_type = io_type;
176 203
177 spin_unlock(&mcbsp[id].lock); 204 spin_unlock(&mcbsp->lock);
178 205
179 return 0; 206 return 0;
180} 207}
@@ -182,53 +209,60 @@ EXPORT_SYMBOL(omap_mcbsp_set_io_type);
182 209
183int omap_mcbsp_request(unsigned int id) 210int omap_mcbsp_request(unsigned int id)
184{ 211{
212 struct omap_mcbsp *mcbsp;
185 int err; 213 int err;
186 214
187 if (!omap_mcbsp_check_valid_id(id)) { 215 if (!omap_mcbsp_check_valid_id(id)) {
188 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 216 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
189 return -ENODEV; 217 return -ENODEV;
190 } 218 }
219 mcbsp = id_to_mcbsp_ptr(id);
191 220
192 if (mcbsp[id].pdata->ops->request) 221 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
193 mcbsp[id].pdata->ops->request(id); 222 mcbsp->pdata->ops->request(id);
194 223
195 clk_enable(mcbsp[id].clk); 224 clk_enable(mcbsp->clk);
196 225
197 spin_lock(&mcbsp[id].lock); 226 spin_lock(&mcbsp->lock);
198 if (!mcbsp[id].free) { 227 if (!mcbsp->free) {
199 dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n", 228 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
200 mcbsp[id].id); 229 mcbsp->id);
201 spin_unlock(&mcbsp[id].lock); 230 spin_unlock(&mcbsp->lock);
202 return -1; 231 return -1;
203 } 232 }
204 233
205 mcbsp[id].free = 0; 234 mcbsp->free = 0;
206 spin_unlock(&mcbsp[id].lock); 235 spin_unlock(&mcbsp->lock);
236
237 /*
238 * Make sure that transmitter, receiver and sample-rate generator are
239 * not running before activating IRQs.
240 */
241 OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
242 OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
207 243
208 if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) { 244 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
209 /* We need to get IRQs here */ 245 /* We need to get IRQs here */
210 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 246 init_completion(&mcbsp->tx_irq_completion);
211 0, "McBSP", (void *) (&mcbsp[id])); 247 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
248 0, "McBSP", (void *)mcbsp);
212 if (err != 0) { 249 if (err != 0) {
213 dev_err(mcbsp[id].dev, "Unable to request TX IRQ %d " 250 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
214 "for McBSP%d\n", mcbsp[id].tx_irq, 251 "for McBSP%d\n", mcbsp->tx_irq,
215 mcbsp[id].id); 252 mcbsp->id);
216 return err; 253 return err;
217 } 254 }
218 255
219 init_completion(&(mcbsp[id].tx_irq_completion)); 256 init_completion(&mcbsp->rx_irq_completion);
220 257 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
221 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 258 0, "McBSP", (void *)mcbsp);
222 0, "McBSP", (void *) (&mcbsp[id]));
223 if (err != 0) { 259 if (err != 0) {
224 dev_err(mcbsp[id].dev, "Unable to request RX IRQ %d " 260 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
225 "for McBSP%d\n", mcbsp[id].rx_irq, 261 "for McBSP%d\n", mcbsp->rx_irq,
226 mcbsp[id].id); 262 mcbsp->id);
227 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id])); 263 free_irq(mcbsp->tx_irq, (void *)mcbsp);
228 return err; 264 return err;
229 } 265 }
230
231 init_completion(&(mcbsp[id].rx_irq_completion));
232 } 266 }
233 267
234 return 0; 268 return 0;
@@ -237,31 +271,34 @@ EXPORT_SYMBOL(omap_mcbsp_request);
237 271
238void omap_mcbsp_free(unsigned int id) 272void omap_mcbsp_free(unsigned int id)
239{ 273{
274 struct omap_mcbsp *mcbsp;
275
240 if (!omap_mcbsp_check_valid_id(id)) { 276 if (!omap_mcbsp_check_valid_id(id)) {
241 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 277 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
242 return; 278 return;
243 } 279 }
280 mcbsp = id_to_mcbsp_ptr(id);
244 281
245 if (mcbsp[id].pdata->ops->free) 282 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
246 mcbsp[id].pdata->ops->free(id); 283 mcbsp->pdata->ops->free(id);
247 284
248 clk_disable(mcbsp[id].clk); 285 clk_disable(mcbsp->clk);
249 286
250 spin_lock(&mcbsp[id].lock); 287 spin_lock(&mcbsp->lock);
251 if (mcbsp[id].free) { 288 if (mcbsp->free) {
252 dev_err(mcbsp[id].dev, "McBSP%d was not reserved\n", 289 dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
253 mcbsp[id].id); 290 mcbsp->id);
254 spin_unlock(&mcbsp[id].lock); 291 spin_unlock(&mcbsp->lock);
255 return; 292 return;
256 } 293 }
257 294
258 mcbsp[id].free = 1; 295 mcbsp->free = 1;
259 spin_unlock(&mcbsp[id].lock); 296 spin_unlock(&mcbsp->lock);
260 297
261 if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) { 298 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
262 /* Free IRQs */ 299 /* Free IRQs */
263 free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id])); 300 free_irq(mcbsp->rx_irq, (void *)mcbsp);
264 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id])); 301 free_irq(mcbsp->tx_irq, (void *)mcbsp);
265 } 302 }
266} 303}
267EXPORT_SYMBOL(omap_mcbsp_free); 304EXPORT_SYMBOL(omap_mcbsp_free);
@@ -273,18 +310,19 @@ EXPORT_SYMBOL(omap_mcbsp_free);
273 */ 310 */
274void omap_mcbsp_start(unsigned int id) 311void omap_mcbsp_start(unsigned int id)
275{ 312{
276 u32 io_base; 313 struct omap_mcbsp *mcbsp;
314 void __iomem *io_base;
277 u16 w; 315 u16 w;
278 316
279 if (!omap_mcbsp_check_valid_id(id)) { 317 if (!omap_mcbsp_check_valid_id(id)) {
280 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 318 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
281 return; 319 return;
282 } 320 }
321 mcbsp = id_to_mcbsp_ptr(id);
322 io_base = mcbsp->io_base;
283 323
284 io_base = mcbsp[id].io_base; 324 mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
285 325 mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
286 mcbsp[id].rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
287 mcbsp[id].tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
288 326
289 /* Start the sample generator */ 327 /* Start the sample generator */
290 w = OMAP_MCBSP_READ(io_base, SPCR2); 328 w = OMAP_MCBSP_READ(io_base, SPCR2);
@@ -310,7 +348,8 @@ EXPORT_SYMBOL(omap_mcbsp_start);
310 348
311void omap_mcbsp_stop(unsigned int id) 349void omap_mcbsp_stop(unsigned int id)
312{ 350{
313 u32 io_base; 351 struct omap_mcbsp *mcbsp;
352 void __iomem *io_base;
314 u16 w; 353 u16 w;
315 354
316 if (!omap_mcbsp_check_valid_id(id)) { 355 if (!omap_mcbsp_check_valid_id(id)) {
@@ -318,7 +357,8 @@ void omap_mcbsp_stop(unsigned int id)
318 return; 357 return;
319 } 358 }
320 359
321 io_base = mcbsp[id].io_base; 360 mcbsp = id_to_mcbsp_ptr(id);
361 io_base = mcbsp->io_base;
322 362
323 /* Reset transmitter */ 363 /* Reset transmitter */
324 w = OMAP_MCBSP_READ(io_base, SPCR2); 364 w = OMAP_MCBSP_READ(io_base, SPCR2);
@@ -337,14 +377,17 @@ EXPORT_SYMBOL(omap_mcbsp_stop);
337/* polled mcbsp i/o operations */ 377/* polled mcbsp i/o operations */
338int omap_mcbsp_pollwrite(unsigned int id, u16 buf) 378int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
339{ 379{
340 u32 base; 380 struct omap_mcbsp *mcbsp;
381 void __iomem *base;
341 382
342 if (!omap_mcbsp_check_valid_id(id)) { 383 if (!omap_mcbsp_check_valid_id(id)) {
343 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 384 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
344 return -ENODEV; 385 return -ENODEV;
345 } 386 }
346 387
347 base = mcbsp[id].io_base; 388 mcbsp = id_to_mcbsp_ptr(id);
389 base = mcbsp->io_base;
390
348 writew(buf, base + OMAP_MCBSP_REG_DXR1); 391 writew(buf, base + OMAP_MCBSP_REG_DXR1);
349 /* if frame sync error - clear the error */ 392 /* if frame sync error - clear the error */
350 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) { 393 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
@@ -366,8 +409,8 @@ int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
366 (XRST), 409 (XRST),
367 base + OMAP_MCBSP_REG_SPCR2); 410 base + OMAP_MCBSP_REG_SPCR2);
368 udelay(10); 411 udelay(10);
369 dev_err(mcbsp[id].dev, "Could not write to" 412 dev_err(mcbsp->dev, "Could not write to"
370 " McBSP%d Register\n", mcbsp[id].id); 413 " McBSP%d Register\n", mcbsp->id);
371 return -2; 414 return -2;
372 } 415 }
373 } 416 }
@@ -379,14 +422,16 @@ EXPORT_SYMBOL(omap_mcbsp_pollwrite);
379 422
380int omap_mcbsp_pollread(unsigned int id, u16 *buf) 423int omap_mcbsp_pollread(unsigned int id, u16 *buf)
381{ 424{
382 u32 base; 425 struct omap_mcbsp *mcbsp;
426 void __iomem *base;
383 427
384 if (!omap_mcbsp_check_valid_id(id)) { 428 if (!omap_mcbsp_check_valid_id(id)) {
385 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 429 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
386 return -ENODEV; 430 return -ENODEV;
387 } 431 }
432 mcbsp = id_to_mcbsp_ptr(id);
388 433
389 base = mcbsp[id].io_base; 434 base = mcbsp->io_base;
390 /* if frame sync error - clear the error */ 435 /* if frame sync error - clear the error */
391 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) { 436 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
392 /* clear error */ 437 /* clear error */
@@ -407,8 +452,8 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf)
407 (RRST), 452 (RRST),
408 base + OMAP_MCBSP_REG_SPCR1); 453 base + OMAP_MCBSP_REG_SPCR1);
409 udelay(10); 454 udelay(10);
410 dev_err(mcbsp[id].dev, "Could not read from" 455 dev_err(mcbsp->dev, "Could not read from"
411 " McBSP%d Register\n", mcbsp[id].id); 456 " McBSP%d Register\n", mcbsp->id);
412 return -2; 457 return -2;
413 } 458 }
414 } 459 }
@@ -424,7 +469,8 @@ EXPORT_SYMBOL(omap_mcbsp_pollread);
424 */ 469 */
425void omap_mcbsp_xmit_word(unsigned int id, u32 word) 470void omap_mcbsp_xmit_word(unsigned int id, u32 word)
426{ 471{
427 u32 io_base; 472 struct omap_mcbsp *mcbsp;
473 void __iomem *io_base;
428 omap_mcbsp_word_length word_length; 474 omap_mcbsp_word_length word_length;
429 475
430 if (!omap_mcbsp_check_valid_id(id)) { 476 if (!omap_mcbsp_check_valid_id(id)) {
@@ -432,10 +478,11 @@ void omap_mcbsp_xmit_word(unsigned int id, u32 word)
432 return; 478 return;
433 } 479 }
434 480
435 io_base = mcbsp[id].io_base; 481 mcbsp = id_to_mcbsp_ptr(id);
436 word_length = mcbsp[id].tx_word_length; 482 io_base = mcbsp->io_base;
483 word_length = mcbsp->tx_word_length;
437 484
438 wait_for_completion(&(mcbsp[id].tx_irq_completion)); 485 wait_for_completion(&mcbsp->tx_irq_completion);
439 486
440 if (word_length > OMAP_MCBSP_WORD_16) 487 if (word_length > OMAP_MCBSP_WORD_16)
441 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16); 488 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
@@ -445,7 +492,8 @@ EXPORT_SYMBOL(omap_mcbsp_xmit_word);
445 492
446u32 omap_mcbsp_recv_word(unsigned int id) 493u32 omap_mcbsp_recv_word(unsigned int id)
447{ 494{
448 u32 io_base; 495 struct omap_mcbsp *mcbsp;
496 void __iomem *io_base;
449 u16 word_lsb, word_msb = 0; 497 u16 word_lsb, word_msb = 0;
450 omap_mcbsp_word_length word_length; 498 omap_mcbsp_word_length word_length;
451 499
@@ -453,11 +501,12 @@ u32 omap_mcbsp_recv_word(unsigned int id)
453 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 501 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
454 return -ENODEV; 502 return -ENODEV;
455 } 503 }
504 mcbsp = id_to_mcbsp_ptr(id);
456 505
457 word_length = mcbsp[id].rx_word_length; 506 word_length = mcbsp->rx_word_length;
458 io_base = mcbsp[id].io_base; 507 io_base = mcbsp->io_base;
459 508
460 wait_for_completion(&(mcbsp[id].rx_irq_completion)); 509 wait_for_completion(&mcbsp->rx_irq_completion);
461 510
462 if (word_length > OMAP_MCBSP_WORD_16) 511 if (word_length > OMAP_MCBSP_WORD_16)
463 word_msb = OMAP_MCBSP_READ(io_base, DRR2); 512 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
@@ -469,7 +518,8 @@ EXPORT_SYMBOL(omap_mcbsp_recv_word);
469 518
470int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) 519int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
471{ 520{
472 u32 io_base; 521 struct omap_mcbsp *mcbsp;
522 void __iomem *io_base;
473 omap_mcbsp_word_length tx_word_length; 523 omap_mcbsp_word_length tx_word_length;
474 omap_mcbsp_word_length rx_word_length; 524 omap_mcbsp_word_length rx_word_length;
475 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; 525 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
@@ -478,10 +528,10 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
478 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 528 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
479 return -ENODEV; 529 return -ENODEV;
480 } 530 }
481 531 mcbsp = id_to_mcbsp_ptr(id);
482 io_base = mcbsp[id].io_base; 532 io_base = mcbsp->io_base;
483 tx_word_length = mcbsp[id].tx_word_length; 533 tx_word_length = mcbsp->tx_word_length;
484 rx_word_length = mcbsp[id].rx_word_length; 534 rx_word_length = mcbsp->rx_word_length;
485 535
486 if (tx_word_length != rx_word_length) 536 if (tx_word_length != rx_word_length)
487 return -EINVAL; 537 return -EINVAL;
@@ -496,8 +546,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
496 udelay(10); 546 udelay(10);
497 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST); 547 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
498 udelay(10); 548 udelay(10);
499 dev_err(mcbsp[id].dev, "McBSP%d transmitter not " 549 dev_err(mcbsp->dev, "McBSP%d transmitter not "
500 "ready\n", mcbsp[id].id); 550 "ready\n", mcbsp->id);
501 return -EAGAIN; 551 return -EAGAIN;
502 } 552 }
503 } 553 }
@@ -517,8 +567,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
517 udelay(10); 567 udelay(10);
518 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST); 568 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
519 udelay(10); 569 udelay(10);
520 dev_err(mcbsp[id].dev, "McBSP%d receiver not " 570 dev_err(mcbsp->dev, "McBSP%d receiver not "
521 "ready\n", mcbsp[id].id); 571 "ready\n", mcbsp->id);
522 return -EAGAIN; 572 return -EAGAIN;
523 } 573 }
524 } 574 }
@@ -534,7 +584,9 @@ EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
534 584
535int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word) 585int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
536{ 586{
537 u32 io_base, clock_word = 0; 587 struct omap_mcbsp *mcbsp;
588 u32 clock_word = 0;
589 void __iomem *io_base;
538 omap_mcbsp_word_length tx_word_length; 590 omap_mcbsp_word_length tx_word_length;
539 omap_mcbsp_word_length rx_word_length; 591 omap_mcbsp_word_length rx_word_length;
540 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; 592 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
@@ -544,9 +596,11 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
544 return -ENODEV; 596 return -ENODEV;
545 } 597 }
546 598
547 io_base = mcbsp[id].io_base; 599 mcbsp = id_to_mcbsp_ptr(id);
548 tx_word_length = mcbsp[id].tx_word_length; 600 io_base = mcbsp->io_base;
549 rx_word_length = mcbsp[id].rx_word_length; 601
602 tx_word_length = mcbsp->tx_word_length;
603 rx_word_length = mcbsp->rx_word_length;
550 604
551 if (tx_word_length != rx_word_length) 605 if (tx_word_length != rx_word_length)
552 return -EINVAL; 606 return -EINVAL;
@@ -561,8 +615,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
561 udelay(10); 615 udelay(10);
562 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST); 616 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
563 udelay(10); 617 udelay(10);
564 dev_err(mcbsp[id].dev, "McBSP%d transmitter not " 618 dev_err(mcbsp->dev, "McBSP%d transmitter not "
565 "ready\n", mcbsp[id].id); 619 "ready\n", mcbsp->id);
566 return -EAGAIN; 620 return -EAGAIN;
567 } 621 }
568 } 622 }
@@ -582,8 +636,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
582 udelay(10); 636 udelay(10);
583 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST); 637 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
584 udelay(10); 638 udelay(10);
585 dev_err(mcbsp[id].dev, "McBSP%d receiver not " 639 dev_err(mcbsp->dev, "McBSP%d receiver not "
586 "ready\n", mcbsp[id].id); 640 "ready\n", mcbsp->id);
587 return -EAGAIN; 641 return -EAGAIN;
588 } 642 }
589 } 643 }
@@ -609,6 +663,7 @@ EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
609int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, 663int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
610 unsigned int length) 664 unsigned int length)
611{ 665{
666 struct omap_mcbsp *mcbsp;
612 int dma_tx_ch; 667 int dma_tx_ch;
613 int src_port = 0; 668 int src_port = 0;
614 int dest_port = 0; 669 int dest_port = 0;
@@ -618,50 +673,51 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
618 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 673 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
619 return -ENODEV; 674 return -ENODEV;
620 } 675 }
676 mcbsp = id_to_mcbsp_ptr(id);
621 677
622 if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", 678 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
623 omap_mcbsp_tx_dma_callback, 679 omap_mcbsp_tx_dma_callback,
624 &mcbsp[id], 680 mcbsp,
625 &dma_tx_ch)) { 681 &dma_tx_ch)) {
626 dev_err(mcbsp[id].dev, " Unable to request DMA channel for " 682 dev_err(mcbsp->dev, " Unable to request DMA channel for "
627 "McBSP%d TX. Trying IRQ based TX\n", 683 "McBSP%d TX. Trying IRQ based TX\n",
628 mcbsp[id].id); 684 mcbsp->id);
629 return -EAGAIN; 685 return -EAGAIN;
630 } 686 }
631 mcbsp[id].dma_tx_lch = dma_tx_ch; 687 mcbsp->dma_tx_lch = dma_tx_ch;
632 688
633 dev_err(mcbsp[id].dev, "McBSP%d TX DMA on channel %d\n", mcbsp[id].id, 689 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
634 dma_tx_ch); 690 dma_tx_ch);
635 691
636 init_completion(&(mcbsp[id].tx_dma_completion)); 692 init_completion(&mcbsp->tx_dma_completion);
637 693
638 if (cpu_class_is_omap1()) { 694 if (cpu_class_is_omap1()) {
639 src_port = OMAP_DMA_PORT_TIPB; 695 src_port = OMAP_DMA_PORT_TIPB;
640 dest_port = OMAP_DMA_PORT_EMIFF; 696 dest_port = OMAP_DMA_PORT_EMIFF;
641 } 697 }
642 if (cpu_class_is_omap2()) 698 if (cpu_class_is_omap2())
643 sync_dev = mcbsp[id].dma_tx_sync; 699 sync_dev = mcbsp->dma_tx_sync;
644 700
645 omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch, 701 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
646 OMAP_DMA_DATA_TYPE_S16, 702 OMAP_DMA_DATA_TYPE_S16,
647 length >> 1, 1, 703 length >> 1, 1,
648 OMAP_DMA_SYNC_ELEMENT, 704 OMAP_DMA_SYNC_ELEMENT,
649 sync_dev, 0); 705 sync_dev, 0);
650 706
651 omap_set_dma_dest_params(mcbsp[id].dma_tx_lch, 707 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
652 src_port, 708 src_port,
653 OMAP_DMA_AMODE_CONSTANT, 709 OMAP_DMA_AMODE_CONSTANT,
654 mcbsp[id].phys_base + OMAP_MCBSP_REG_DXR1, 710 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
655 0, 0); 711 0, 0);
656 712
657 omap_set_dma_src_params(mcbsp[id].dma_tx_lch, 713 omap_set_dma_src_params(mcbsp->dma_tx_lch,
658 dest_port, 714 dest_port,
659 OMAP_DMA_AMODE_POST_INC, 715 OMAP_DMA_AMODE_POST_INC,
660 buffer, 716 buffer,
661 0, 0); 717 0, 0);
662 718
663 omap_start_dma(mcbsp[id].dma_tx_lch); 719 omap_start_dma(mcbsp->dma_tx_lch);
664 wait_for_completion(&(mcbsp[id].tx_dma_completion)); 720 wait_for_completion(&mcbsp->tx_dma_completion);
665 721
666 return 0; 722 return 0;
667} 723}
@@ -670,6 +726,7 @@ EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
670int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, 726int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
671 unsigned int length) 727 unsigned int length)
672{ 728{
729 struct omap_mcbsp *mcbsp;
673 int dma_rx_ch; 730 int dma_rx_ch;
674 int src_port = 0; 731 int src_port = 0;
675 int dest_port = 0; 732 int dest_port = 0;
@@ -679,50 +736,51 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
679 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 736 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
680 return -ENODEV; 737 return -ENODEV;
681 } 738 }
739 mcbsp = id_to_mcbsp_ptr(id);
682 740
683 if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", 741 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
684 omap_mcbsp_rx_dma_callback, 742 omap_mcbsp_rx_dma_callback,
685 &mcbsp[id], 743 mcbsp,
686 &dma_rx_ch)) { 744 &dma_rx_ch)) {
687 dev_err(mcbsp[id].dev, "Unable to request DMA channel for " 745 dev_err(mcbsp->dev, "Unable to request DMA channel for "
688 "McBSP%d RX. Trying IRQ based RX\n", 746 "McBSP%d RX. Trying IRQ based RX\n",
689 mcbsp[id].id); 747 mcbsp->id);
690 return -EAGAIN; 748 return -EAGAIN;
691 } 749 }
692 mcbsp[id].dma_rx_lch = dma_rx_ch; 750 mcbsp->dma_rx_lch = dma_rx_ch;
693 751
694 dev_err(mcbsp[id].dev, "McBSP%d RX DMA on channel %d\n", mcbsp[id].id, 752 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
695 dma_rx_ch); 753 dma_rx_ch);
696 754
697 init_completion(&(mcbsp[id].rx_dma_completion)); 755 init_completion(&mcbsp->rx_dma_completion);
698 756
699 if (cpu_class_is_omap1()) { 757 if (cpu_class_is_omap1()) {
700 src_port = OMAP_DMA_PORT_TIPB; 758 src_port = OMAP_DMA_PORT_TIPB;
701 dest_port = OMAP_DMA_PORT_EMIFF; 759 dest_port = OMAP_DMA_PORT_EMIFF;
702 } 760 }
703 if (cpu_class_is_omap2()) 761 if (cpu_class_is_omap2())
704 sync_dev = mcbsp[id].dma_rx_sync; 762 sync_dev = mcbsp->dma_rx_sync;
705 763
706 omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch, 764 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
707 OMAP_DMA_DATA_TYPE_S16, 765 OMAP_DMA_DATA_TYPE_S16,
708 length >> 1, 1, 766 length >> 1, 1,
709 OMAP_DMA_SYNC_ELEMENT, 767 OMAP_DMA_SYNC_ELEMENT,
710 sync_dev, 0); 768 sync_dev, 0);
711 769
712 omap_set_dma_src_params(mcbsp[id].dma_rx_lch, 770 omap_set_dma_src_params(mcbsp->dma_rx_lch,
713 src_port, 771 src_port,
714 OMAP_DMA_AMODE_CONSTANT, 772 OMAP_DMA_AMODE_CONSTANT,
715 mcbsp[id].phys_base + OMAP_MCBSP_REG_DRR1, 773 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
716 0, 0); 774 0, 0);
717 775
718 omap_set_dma_dest_params(mcbsp[id].dma_rx_lch, 776 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
719 dest_port, 777 dest_port,
720 OMAP_DMA_AMODE_POST_INC, 778 OMAP_DMA_AMODE_POST_INC,
721 buffer, 779 buffer,
722 0, 0); 780 0, 0);
723 781
724 omap_start_dma(mcbsp[id].dma_rx_lch); 782 omap_start_dma(mcbsp->dma_rx_lch);
725 wait_for_completion(&(mcbsp[id].rx_dma_completion)); 783 wait_for_completion(&mcbsp->rx_dma_completion);
726 784
727 return 0; 785 return 0;
728} 786}
@@ -737,12 +795,14 @@ EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
737void omap_mcbsp_set_spi_mode(unsigned int id, 795void omap_mcbsp_set_spi_mode(unsigned int id,
738 const struct omap_mcbsp_spi_cfg *spi_cfg) 796 const struct omap_mcbsp_spi_cfg *spi_cfg)
739{ 797{
798 struct omap_mcbsp *mcbsp;
740 struct omap_mcbsp_reg_cfg mcbsp_cfg; 799 struct omap_mcbsp_reg_cfg mcbsp_cfg;
741 800
742 if (!omap_mcbsp_check_valid_id(id)) { 801 if (!omap_mcbsp_check_valid_id(id)) {
743 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); 802 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
744 return; 803 return;
745 } 804 }
805 mcbsp = id_to_mcbsp_ptr(id);
746 806
747 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg)); 807 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
748 808
@@ -803,9 +863,10 @@ EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
803 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. 863 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
804 * 730 has only 2 McBSP, and both of them are MPU peripherals. 864 * 730 has only 2 McBSP, and both of them are MPU peripherals.
805 */ 865 */
806static int __init omap_mcbsp_probe(struct platform_device *pdev) 866static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
807{ 867{
808 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data; 868 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
869 struct omap_mcbsp *mcbsp;
809 int id = pdev->id - 1; 870 int id = pdev->id - 1;
810 int ret = 0; 871 int ret = 0;
811 872
@@ -818,47 +879,63 @@ static int __init omap_mcbsp_probe(struct platform_device *pdev)
818 879
819 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id); 880 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
820 881
821 if (id >= OMAP_MAX_MCBSP_COUNT) { 882 if (id >= omap_mcbsp_count) {
822 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id); 883 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
823 ret = -EINVAL; 884 ret = -EINVAL;
824 goto exit; 885 goto exit;
825 } 886 }
826 887
827 spin_lock_init(&mcbsp[id].lock); 888 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
828 mcbsp[id].id = id + 1; 889 if (!mcbsp) {
829 mcbsp[id].free = 1; 890 ret = -ENOMEM;
830 mcbsp[id].dma_tx_lch = -1; 891 goto exit;
831 mcbsp[id].dma_rx_lch = -1; 892 }
893 mcbsp_ptr[id] = mcbsp;
894
895 spin_lock_init(&mcbsp->lock);
896 mcbsp->id = id + 1;
897 mcbsp->free = 1;
898 mcbsp->dma_tx_lch = -1;
899 mcbsp->dma_rx_lch = -1;
900
901 mcbsp->phys_base = pdata->phys_base;
902 mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
903 if (!mcbsp->io_base) {
904 ret = -ENOMEM;
905 goto err_ioremap;
906 }
832 907
833 mcbsp[id].phys_base = pdata->phys_base;
834 mcbsp[id].io_base = pdata->virt_base;
835 /* Default I/O is IRQ based */ 908 /* Default I/O is IRQ based */
836 mcbsp[id].io_type = OMAP_MCBSP_IRQ_IO; 909 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
837 mcbsp[id].tx_irq = pdata->tx_irq; 910 mcbsp->tx_irq = pdata->tx_irq;
838 mcbsp[id].rx_irq = pdata->rx_irq; 911 mcbsp->rx_irq = pdata->rx_irq;
839 mcbsp[id].dma_rx_sync = pdata->dma_rx_sync; 912 mcbsp->dma_rx_sync = pdata->dma_rx_sync;
840 mcbsp[id].dma_tx_sync = pdata->dma_tx_sync; 913 mcbsp->dma_tx_sync = pdata->dma_tx_sync;
841 914
842 if (pdata->clk_name) 915 if (pdata->clk_name)
843 mcbsp[id].clk = clk_get(&pdev->dev, pdata->clk_name); 916 mcbsp->clk = clk_get(&pdev->dev, pdata->clk_name);
844 if (IS_ERR(mcbsp[id].clk)) { 917 if (IS_ERR(mcbsp->clk)) {
845 mcbsp[id].free = 0;
846 dev_err(&pdev->dev, 918 dev_err(&pdev->dev,
847 "Invalid clock configuration for McBSP%d.\n", 919 "Invalid clock configuration for McBSP%d.\n",
848 mcbsp[id].id); 920 mcbsp->id);
849 ret = -EINVAL; 921 ret = PTR_ERR(mcbsp->clk);
850 goto exit; 922 goto err_clk;
851 } 923 }
852 924
853 mcbsp[id].pdata = pdata; 925 mcbsp->pdata = pdata;
854 mcbsp[id].dev = &pdev->dev; 926 mcbsp->dev = &pdev->dev;
855 platform_set_drvdata(pdev, &mcbsp[id]); 927 platform_set_drvdata(pdev, mcbsp);
928 return 0;
856 929
930err_clk:
931 iounmap(mcbsp->io_base);
932err_ioremap:
933 mcbsp->free = 0;
857exit: 934exit:
858 return ret; 935 return ret;
859} 936}
860 937
861static int omap_mcbsp_remove(struct platform_device *pdev) 938static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
862{ 939{
863 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); 940 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
864 941
@@ -872,6 +949,8 @@ static int omap_mcbsp_remove(struct platform_device *pdev)
872 clk_disable(mcbsp->clk); 949 clk_disable(mcbsp->clk);
873 clk_put(mcbsp->clk); 950 clk_put(mcbsp->clk);
874 951
952 iounmap(mcbsp->io_base);
953
875 mcbsp->clk = NULL; 954 mcbsp->clk = NULL;
876 mcbsp->free = 0; 955 mcbsp->free = 0;
877 mcbsp->dev = NULL; 956 mcbsp->dev = NULL;
@@ -882,7 +961,7 @@ static int omap_mcbsp_remove(struct platform_device *pdev)
882 961
883static struct platform_driver omap_mcbsp_driver = { 962static struct platform_driver omap_mcbsp_driver = {
884 .probe = omap_mcbsp_probe, 963 .probe = omap_mcbsp_probe,
885 .remove = omap_mcbsp_remove, 964 .remove = __devexit_p(omap_mcbsp_remove),
886 .driver = { 965 .driver = {
887 .name = "omap-mcbsp", 966 .name = "omap-mcbsp",
888 }, 967 },
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index e0003e0746e7..9f9a921829c0 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -271,7 +271,7 @@ int __init omap1_sram_init(void)
271#define omap1_sram_init() do {} while (0) 271#define omap1_sram_init() do {} while (0)
272#endif 272#endif
273 273
274#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 274#if defined(CONFIG_ARCH_OMAP2)
275 275
276static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 276static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
277 u32 base_cs, u32 force_unlock); 277 u32 base_cs, u32 force_unlock);
@@ -352,23 +352,19 @@ static inline int omap243x_sram_init(void)
352 352
353#ifdef CONFIG_ARCH_OMAP3 353#ifdef CONFIG_ARCH_OMAP3
354 354
355static u32 (*_omap2_sram_reprogram_gpmc)(u32 perf_level); 355static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
356u32 omap2_sram_reprogram_gpmc(u32 perf_level) 356 u32 sdrc_actim_ctrla,
357{ 357 u32 sdrc_actim_ctrlb,
358 if (!_omap2_sram_reprogram_gpmc) 358 u32 m2);
359 omap_sram_error(); 359u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
360 360 u32 sdrc_actim_ctrlb, u32 m2)
361 return _omap2_sram_reprogram_gpmc(perf_level);
362}
363
364static u32 (*_omap2_sram_configure_core_dpll)(u32 m, u32 n,
365 u32 freqsel, u32 m2);
366u32 omap2_sram_configure_core_dpll(u32 m, u32 n, u32 freqsel, u32 m2)
367{ 361{
368 if (!_omap2_sram_configure_core_dpll) 362 if (!_omap3_sram_configure_core_dpll)
369 omap_sram_error(); 363 omap_sram_error();
370 364
371 return _omap2_sram_configure_core_dpll(m, n, freqsel, m2); 365 return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
366 sdrc_actim_ctrla,
367 sdrc_actim_ctrlb, m2);
372} 368}
373 369
374/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ 370/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
@@ -376,31 +372,16 @@ void restore_sram_functions(void)
376{ 372{
377 omap_sram_ceil = omap_sram_base + omap_sram_size; 373 omap_sram_ceil = omap_sram_base + omap_sram_size;
378 374
379 _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc, 375 _omap3_sram_configure_core_dpll =
380 omap34xx_sram_reprogram_gpmc_sz); 376 omap_sram_push(omap3_sram_configure_core_dpll,
381 377 omap3_sram_configure_core_dpll_sz);
382 _omap2_sram_configure_core_dpll =
383 omap_sram_push(omap34xx_sram_configure_core_dpll,
384 omap34xx_sram_configure_core_dpll_sz);
385} 378}
386 379
387int __init omap34xx_sram_init(void) 380int __init omap34xx_sram_init(void)
388{ 381{
389 _omap2_sram_ddr_init = omap_sram_push(omap34xx_sram_ddr_init, 382 _omap3_sram_configure_core_dpll =
390 omap34xx_sram_ddr_init_sz); 383 omap_sram_push(omap3_sram_configure_core_dpll,
391 384 omap3_sram_configure_core_dpll_sz);
392 _omap2_sram_reprogram_sdrc = omap_sram_push(omap34xx_sram_reprogram_sdrc,
393 omap34xx_sram_reprogram_sdrc_sz);
394
395 _omap2_set_prcm = omap_sram_push(omap34xx_sram_set_prcm,
396 omap34xx_sram_set_prcm_sz);
397
398 _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
399 omap34xx_sram_reprogram_gpmc_sz);
400
401 _omap2_sram_configure_core_dpll =
402 omap_sram_push(omap34xx_sram_configure_core_dpll,
403 omap34xx_sram_configure_core_dpll_sz);
404 385
405 return 0; 386 return 0;
406} 387}
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
new file mode 100644
index 000000000000..f03d7b35ba37
--- /dev/null
+++ b/arch/arm/plat-s3c/Makefile
@@ -0,0 +1,3 @@
1# dummy makefile, currently just including asm/arm/plat-s3c/include/plat
2
3obj-n := dummy.o
diff --git a/include/asm-arm/plat-s3c/debug-macro.S b/arch/arm/plat-s3c/include/plat/debug-macro.S
index 84c40b847da8..4aa7e2e6c001 100644
--- a/include/asm-arm/plat-s3c/debug-macro.S
+++ b/arch/arm/plat-s3c/include/plat/debug-macro.S
@@ -9,7 +9,7 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10*/ 10*/
11 11
12#include <asm/plat-s3c/regs-serial.h> 12#include <plat/regs-serial.h>
13 13
14/* The S3C2440 implementations are used by default as they are the 14/* The S3C2440 implementations are used by default as they are the
15 * most widely re-used */ 15 * most widely re-used */
diff --git a/include/asm-arm/plat-s3c/map.h b/arch/arm/plat-s3c/include/plat/map.h
index b84289d32a54..b84289d32a54 100644
--- a/include/asm-arm/plat-s3c/map.h
+++ b/arch/arm/plat-s3c/include/plat/map.h
diff --git a/include/asm-arm/plat-s3c/regs-adc.h b/arch/arm/plat-s3c/include/plat/regs-adc.h
index 4323cccc86cd..4323cccc86cd 100644
--- a/include/asm-arm/plat-s3c/regs-adc.h
+++ b/arch/arm/plat-s3c/include/plat/regs-adc.h
diff --git a/include/asm-arm/plat-s3c/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h
index a0daa647b92c..a0daa647b92c 100644
--- a/include/asm-arm/plat-s3c/regs-serial.h
+++ b/arch/arm/plat-s3c/include/plat/regs-serial.h
diff --git a/include/asm-arm/plat-s3c/regs-timer.h b/arch/arm/plat-s3c/include/plat/regs-timer.h
index cc0eedd53e38..cc0eedd53e38 100644
--- a/include/asm-arm/plat-s3c/regs-timer.h
+++ b/arch/arm/plat-s3c/include/plat/regs-timer.h
diff --git a/include/asm-arm/plat-s3c/uncompress.h b/arch/arm/plat-s3c/include/plat/uncompress.h
index 19b9eda39485..4df006b9cc10 100644
--- a/include/asm-arm/plat-s3c/uncompress.h
+++ b/arch/arm/plat-s3c/include/plat/uncompress.h
@@ -27,7 +27,7 @@ static void arch_detect_cpu(void);
27 27
28/* defines for UART registers */ 28/* defines for UART registers */
29 29
30#include <asm/plat-s3c/regs-serial.h> 30#include <plat/regs-serial.h>
31#include <asm/plat-s3c/regs-watchdog.h> 31#include <asm/plat-s3c/regs-watchdog.h>
32 32
33/* working in physical space... */ 33/* working in physical space... */
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c
index 400541359bfb..a005ddbd9ef3 100644
--- a/arch/arm/plat-s3c24xx/clock.c
+++ b/arch/arm/plat-s3c24xx/clock.c
@@ -47,8 +47,8 @@
47#include <mach/regs-clock.h> 47#include <mach/regs-clock.h>
48#include <mach/regs-gpio.h> 48#include <mach/regs-gpio.h>
49 49
50#include <asm/plat-s3c24xx/clock.h> 50#include <plat/clock.h>
51#include <asm/plat-s3c24xx/cpu.h> 51#include <plat/cpu.h>
52 52
53/* clock information */ 53/* clock information */
54 54
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index d528f460f6bc..3098736c65d9 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -40,9 +40,9 @@
40 40
41#include <asm/plat-s3c/nand.h> 41#include <asm/plat-s3c/nand.h>
42 42
43#include <asm/plat-s3c24xx/common-smdk.h> 43#include <plat/common-smdk.h>
44#include <asm/plat-s3c24xx/devs.h> 44#include <plat/devs.h>
45#include <asm/plat-s3c24xx/pm.h> 45#include <plat/pm.h>
46 46
47/* LED devices */ 47/* LED devices */
48 48
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 9c607bbc9343..22a329513c0f 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -42,18 +42,18 @@
42#include <mach/system-reset.h> 42#include <mach/system-reset.h>
43 43
44#include <mach/regs-gpio.h> 44#include <mach/regs-gpio.h>
45#include <asm/plat-s3c/regs-serial.h> 45#include <plat/regs-serial.h>
46 46
47#include <asm/plat-s3c24xx/cpu.h> 47#include <plat/cpu.h>
48#include <asm/plat-s3c24xx/devs.h> 48#include <plat/devs.h>
49#include <asm/plat-s3c24xx/clock.h> 49#include <plat/clock.h>
50#include <asm/plat-s3c24xx/s3c2400.h> 50#include <plat/s3c2400.h>
51#include <asm/plat-s3c24xx/s3c2410.h> 51#include <plat/s3c2410.h>
52#include <asm/plat-s3c24xx/s3c2412.h> 52#include <plat/s3c2412.h>
53#include "s3c244x.h" 53#include "s3c244x.h"
54#include <asm/plat-s3c24xx/s3c2440.h> 54#include <plat/s3c2440.h>
55#include <asm/plat-s3c24xx/s3c2442.h> 55#include <plat/s3c2442.h>
56#include <asm/plat-s3c24xx/s3c2443.h> 56#include <plat/s3c2443.h>
57 57
58struct cpu_table { 58struct cpu_table {
59 unsigned long idcode; 59 unsigned long idcode;
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 6b13b5455dfc..e93f8bf6d338 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -28,11 +28,11 @@
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <asm/irq.h> 29#include <asm/irq.h>
30 30
31#include <asm/plat-s3c/regs-serial.h> 31#include <plat/regs-serial.h>
32#include <asm/plat-s3c24xx/udc.h> 32#include <asm/plat-s3c24xx/udc.h>
33 33
34#include <asm/plat-s3c24xx/devs.h> 34#include <plat/devs.h>
35#include <asm/plat-s3c24xx/cpu.h> 35#include <plat/cpu.h>
36#include <asm/plat-s3c24xx/regs-spi.h> 36#include <asm/plat-s3c24xx/regs-spi.h>
37 37
38/* Serial port registrations */ 38/* Serial port registrations */
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index d6344461a83b..1baf941d1930 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -36,7 +36,7 @@
36#include <asm/mach/dma.h> 36#include <asm/mach/dma.h>
37#include <mach/map.h> 37#include <mach/map.h>
38 38
39#include <asm/plat-s3c24xx/dma.h> 39#include <plat/dma.h>
40 40
41/* io map for dma */ 41/* io map for dma */
42static void __iomem *dma_base; 42static void __iomem *dma_base;
diff --git a/include/asm-arm/plat-s3c24xx/clock.h b/arch/arm/plat-s3c24xx/include/plat/clock.h
index 235b753cd877..235b753cd877 100644
--- a/include/asm-arm/plat-s3c24xx/clock.h
+++ b/arch/arm/plat-s3c24xx/include/plat/clock.h
diff --git a/include/asm-arm/plat-s3c24xx/common-smdk.h b/arch/arm/plat-s3c24xx/include/plat/common-smdk.h
index 58d9094c935c..58d9094c935c 100644
--- a/include/asm-arm/plat-s3c24xx/common-smdk.h
+++ b/arch/arm/plat-s3c24xx/include/plat/common-smdk.h
diff --git a/include/asm-arm/plat-s3c24xx/cpu.h b/arch/arm/plat-s3c24xx/include/plat/cpu.h
index 23e420e8bd5b..23e420e8bd5b 100644
--- a/include/asm-arm/plat-s3c24xx/cpu.h
+++ b/arch/arm/plat-s3c24xx/include/plat/cpu.h
diff --git a/include/asm-arm/plat-s3c24xx/devs.h b/arch/arm/plat-s3c24xx/include/plat/devs.h
index badaac9d64a8..badaac9d64a8 100644
--- a/include/asm-arm/plat-s3c24xx/devs.h
+++ b/arch/arm/plat-s3c24xx/include/plat/devs.h
diff --git a/include/asm-arm/plat-s3c24xx/dma.h b/arch/arm/plat-s3c24xx/include/plat/dma.h
index c78efe316fc8..c78efe316fc8 100644
--- a/include/asm-arm/plat-s3c24xx/dma.h
+++ b/arch/arm/plat-s3c24xx/include/plat/dma.h
diff --git a/include/asm-arm/plat-s3c24xx/irq.h b/arch/arm/plat-s3c24xx/include/plat/irq.h
index 45746a995343..45746a995343 100644
--- a/include/asm-arm/plat-s3c24xx/irq.h
+++ b/arch/arm/plat-s3c24xx/include/plat/irq.h
diff --git a/include/asm-arm/plat-s3c24xx/pm.h b/arch/arm/plat-s3c24xx/include/plat/pm.h
index cc623667e48a..cc623667e48a 100644
--- a/include/asm-arm/plat-s3c24xx/pm.h
+++ b/arch/arm/plat-s3c24xx/include/plat/pm.h
diff --git a/include/asm-arm/plat-s3c24xx/s3c2400.h b/arch/arm/plat-s3c24xx/include/plat/s3c2400.h
index 3a5a16821af8..3a5a16821af8 100644
--- a/include/asm-arm/plat-s3c24xx/s3c2400.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2400.h
diff --git a/include/asm-arm/plat-s3c24xx/s3c2410.h b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
index 3cd1ec677b3f..3cd1ec677b3f 100644
--- a/include/asm-arm/plat-s3c24xx/s3c2410.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
diff --git a/include/asm-arm/plat-s3c24xx/s3c2412.h b/arch/arm/plat-s3c24xx/include/plat/s3c2412.h
index 3ec97685e781..3ec97685e781 100644
--- a/include/asm-arm/plat-s3c24xx/s3c2412.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2412.h
diff --git a/include/asm-arm/plat-s3c24xx/s3c2440.h b/arch/arm/plat-s3c24xx/include/plat/s3c2440.h
index 107853bf9481..107853bf9481 100644
--- a/include/asm-arm/plat-s3c24xx/s3c2440.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2440.h
diff --git a/include/asm-arm/plat-s3c24xx/s3c2442.h b/arch/arm/plat-s3c24xx/include/plat/s3c2442.h
index 451a23a2092a..451a23a2092a 100644
--- a/include/asm-arm/plat-s3c24xx/s3c2442.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2442.h
diff --git a/include/asm-arm/plat-s3c24xx/s3c2443.h b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
index 11d83b5c84e6..11d83b5c84e6 100644
--- a/include/asm-arm/plat-s3c24xx/s3c2443.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index 590fc5a3ab06..963f7a4f26f2 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -65,9 +65,9 @@
65#include <mach/regs-irq.h> 65#include <mach/regs-irq.h>
66#include <mach/regs-gpio.h> 66#include <mach/regs-gpio.h>
67 67
68#include <asm/plat-s3c24xx/cpu.h> 68#include <plat/cpu.h>
69#include <asm/plat-s3c24xx/pm.h> 69#include <plat/pm.h>
70#include <asm/plat-s3c24xx/irq.h> 70#include <plat/irq.h>
71 71
72/* wakeup irq control */ 72/* wakeup irq control */
73 73
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c
index 0a074d35890a..21dfa74773d1 100644
--- a/arch/arm/plat-s3c24xx/pm-simtec.c
+++ b/arch/arm/plat-s3c24xx/pm-simtec.c
@@ -33,7 +33,7 @@
33 33
34#include <asm/mach-types.h> 34#include <asm/mach-types.h>
35 35
36#include <asm/plat-s3c24xx/pm.h> 36#include <plat/pm.h>
37 37
38#define COPYRIGHT ", (c) 2005 Simtec Electronics" 38#define COPYRIGHT ", (c) 2005 Simtec Electronics"
39 39
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index d3934b1119a9..8efb57ad5019 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -40,7 +40,7 @@
40#include <asm/cacheflush.h> 40#include <asm/cacheflush.h>
41#include <mach/hardware.h> 41#include <mach/hardware.h>
42 42
43#include <asm/plat-s3c/regs-serial.h> 43#include <plat/regs-serial.h>
44#include <mach/regs-clock.h> 44#include <mach/regs-clock.h>
45#include <mach/regs-gpio.h> 45#include <mach/regs-gpio.h>
46#include <mach/regs-mem.h> 46#include <mach/regs-mem.h>
@@ -48,7 +48,7 @@
48 48
49#include <asm/mach/time.h> 49#include <asm/mach/time.h>
50 50
51#include <asm/plat-s3c24xx/pm.h> 51#include <plat/pm.h>
52 52
53/* for external use */ 53/* for external use */
54 54
diff --git a/arch/arm/plat-s3c24xx/pwm-clock.c b/arch/arm/plat-s3c24xx/pwm-clock.c
index 306cc9c6f9ef..b8e854f1b1d5 100644
--- a/arch/arm/plat-s3c24xx/pwm-clock.c
+++ b/arch/arm/plat-s3c24xx/pwm-clock.c
@@ -24,10 +24,10 @@
24#include <mach/regs-clock.h> 24#include <mach/regs-clock.h>
25#include <mach/regs-gpio.h> 25#include <mach/regs-gpio.h>
26 26
27#include <asm/plat-s3c24xx/clock.h> 27#include <plat/clock.h>
28#include <asm/plat-s3c24xx/cpu.h> 28#include <plat/cpu.h>
29 29
30#include <asm/plat-s3c/regs-timer.h> 30#include <plat/regs-timer.h>
31 31
32/* Each of the timers 0 through 5 go through the following 32/* Each of the timers 0 through 5 go through the following
33 * clock tree, with the inputs depending on the timers. 33 * clock tree, with the inputs depending on the timers.
diff --git a/arch/arm/plat-s3c24xx/pwm.c b/arch/arm/plat-s3c24xx/pwm.c
index 7a92c938542a..feb770f2e84e 100644
--- a/arch/arm/plat-s3c24xx/pwm.c
+++ b/arch/arm/plat-s3c24xx/pwm.c
@@ -19,8 +19,8 @@
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/pwm.h> 20#include <linux/pwm.h>
21 21
22#include <asm/plat-s3c24xx/devs.h> 22#include <plat/devs.h>
23#include <asm/plat-s3c/regs-timer.h> 23#include <plat/regs-timer.h>
24 24
25struct pwm_device { 25struct pwm_device {
26 struct list_head list; 26 struct list_head list;
diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/plat-s3c24xx/s3c244x-clock.c
index 119647a5eaa6..7c09773ff9fc 100644
--- a/arch/arm/plat-s3c24xx/s3c244x-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c244x-clock.c
@@ -41,8 +41,8 @@
41 41
42#include <mach/regs-clock.h> 42#include <mach/regs-clock.h>
43 43
44#include <asm/plat-s3c24xx/clock.h> 44#include <plat/clock.h>
45#include <asm/plat-s3c24xx/cpu.h> 45#include <plat/cpu.h>
46 46
47static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent) 47static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent)
48{ 48{
diff --git a/arch/arm/plat-s3c24xx/s3c244x-irq.c b/arch/arm/plat-s3c24xx/s3c244x-irq.c
index 0601c5f3230b..0902afd227ca 100644
--- a/arch/arm/plat-s3c24xx/s3c244x-irq.c
+++ b/arch/arm/plat-s3c24xx/s3c244x-irq.c
@@ -34,9 +34,9 @@
34#include <mach/regs-irq.h> 34#include <mach/regs-irq.h>
35#include <mach/regs-gpio.h> 35#include <mach/regs-gpio.h>
36 36
37#include <asm/plat-s3c24xx/cpu.h> 37#include <plat/cpu.h>
38#include <asm/plat-s3c24xx/pm.h> 38#include <plat/pm.h>
39#include <asm/plat-s3c24xx/irq.h> 39#include <plat/irq.h>
40 40
41/* camera irq */ 41/* camera irq */
42 42
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c
index 146863a69aeb..c0344fac4a94 100644
--- a/arch/arm/plat-s3c24xx/s3c244x.c
+++ b/arch/arm/plat-s3c24xx/s3c244x.c
@@ -30,18 +30,18 @@
30#include <asm/irq.h> 30#include <asm/irq.h>
31 31
32#include <mach/regs-clock.h> 32#include <mach/regs-clock.h>
33#include <asm/plat-s3c/regs-serial.h> 33#include <plat/regs-serial.h>
34#include <mach/regs-gpio.h> 34#include <mach/regs-gpio.h>
35#include <mach/regs-gpioj.h> 35#include <mach/regs-gpioj.h>
36#include <mach/regs-dsc.h> 36#include <mach/regs-dsc.h>
37 37
38#include <asm/plat-s3c24xx/s3c2410.h> 38#include <plat/s3c2410.h>
39#include <asm/plat-s3c24xx/s3c2440.h> 39#include <plat/s3c2440.h>
40#include "s3c244x.h" 40#include "s3c244x.h"
41#include <asm/plat-s3c24xx/clock.h> 41#include <plat/clock.h>
42#include <asm/plat-s3c24xx/devs.h> 42#include <plat/devs.h>
43#include <asm/plat-s3c24xx/cpu.h> 43#include <plat/cpu.h>
44#include <asm/plat-s3c24xx/pm.h> 44#include <plat/pm.h>
45 45
46static struct map_desc s3c244x_iodesc[] __initdata = { 46static struct map_desc s3c244x_iodesc[] __initdata = {
47 IODESC_ENT(CLKPWR), 47 IODESC_ENT(CLKPWR),
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
index 4981a08b6ebb..76594b212802 100644
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -32,7 +32,7 @@
32#include <mach/regs-gpio.h> 32#include <mach/regs-gpio.h>
33#include <mach/regs-clock.h> 33#include <mach/regs-clock.h>
34#include <mach/regs-mem.h> 34#include <mach/regs-mem.h>
35#include <asm/plat-s3c/regs-serial.h> 35#include <plat/regs-serial.h>
36 36
37/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not 37/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
38 * reset the UART configuration, only enable if you really need this! 38 * reset the UART configuration, only enable if you really need this!
diff --git a/arch/arm/plat-s3c24xx/time.c b/arch/arm/plat-s3c24xx/time.c
index 64bfa19ae951..c51916236ac0 100644
--- a/arch/arm/plat-s3c24xx/time.c
+++ b/arch/arm/plat-s3c24xx/time.c
@@ -33,12 +33,12 @@
33 33
34#include <asm/irq.h> 34#include <asm/irq.h>
35#include <mach/map.h> 35#include <mach/map.h>
36#include <asm/plat-s3c/regs-timer.h> 36#include <plat/regs-timer.h>
37#include <mach/regs-irq.h> 37#include <mach/regs-irq.h>
38#include <asm/mach/time.h> 38#include <asm/mach/time.h>
39 39
40#include <asm/plat-s3c24xx/clock.h> 40#include <plat/clock.h>
41#include <asm/plat-s3c24xx/cpu.h> 41#include <plat/cpu.h>
42 42
43static unsigned long timer_startval; 43static unsigned long timer_startval;
44static unsigned long timer_usec_ticks; 44static unsigned long timer_usec_ticks;
diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c
index 51738bdd834e..d4e7dca06e4f 100644
--- a/drivers/char/hw_random/omap-rng.c
+++ b/drivers/char/hw_random/omap-rng.c
@@ -118,18 +118,21 @@ static int __init omap_rng_probe(struct platform_device *pdev)
118 118
119 mem = request_mem_region(res->start, res->end - res->start + 1, 119 mem = request_mem_region(res->start, res->end - res->start + 1,
120 pdev->name); 120 pdev->name);
121 if (mem == NULL) 121 if (mem == NULL) {
122 return -EBUSY; 122 ret = -EBUSY;
123 goto err_region;
124 }
123 125
124 dev_set_drvdata(&pdev->dev, mem); 126 dev_set_drvdata(&pdev->dev, mem);
125 rng_base = (u32 __force __iomem *)io_p2v(res->start); 127 rng_base = ioremap(res->start, res->end - res->start + 1);
128 if (!rng_base) {
129 ret = -ENOMEM;
130 goto err_ioremap;
131 }
126 132
127 ret = hwrng_register(&omap_rng_ops); 133 ret = hwrng_register(&omap_rng_ops);
128 if (ret) { 134 if (ret)
129 release_resource(mem); 135 goto err_register;
130 rng_base = NULL;
131 return ret;
132 }
133 136
134 dev_info(&pdev->dev, "OMAP Random Number Generator ver. %02x\n", 137 dev_info(&pdev->dev, "OMAP Random Number Generator ver. %02x\n",
135 omap_rng_read_reg(RNG_REV_REG)); 138 omap_rng_read_reg(RNG_REV_REG));
@@ -138,6 +141,18 @@ static int __init omap_rng_probe(struct platform_device *pdev)
138 rng_dev = pdev; 141 rng_dev = pdev;
139 142
140 return 0; 143 return 0;
144
145err_register:
146 iounmap(rng_base);
147 rng_base = NULL;
148err_ioremap:
149 release_resource(mem);
150err_region:
151 if (cpu_is_omap24xx()) {
152 clk_disable(rng_ick);
153 clk_put(rng_ick);
154 }
155 return ret;
141} 156}
142 157
143static int __exit omap_rng_remove(struct platform_device *pdev) 158static int __exit omap_rng_remove(struct platform_device *pdev)
@@ -148,6 +163,8 @@ static int __exit omap_rng_remove(struct platform_device *pdev)
148 163
149 omap_rng_write_reg(RNG_MASK_REG, 0x0); 164 omap_rng_write_reg(RNG_MASK_REG, 0x0);
150 165
166 iounmap(rng_base);
167
151 if (cpu_is_omap24xx()) { 168 if (cpu_is_omap24xx()) {
152 clk_disable(rng_ick); 169 clk_disable(rng_ick);
153 clk_put(rng_ick); 170 clk_put(rng_ick);
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index e7eb7bf9ddec..608038d64f81 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -589,11 +589,16 @@ omap_i2c_probe(struct platform_device *pdev)
589 589
590 dev->dev = &pdev->dev; 590 dev->dev = &pdev->dev;
591 dev->irq = irq->start; 591 dev->irq = irq->start;
592 dev->base = (void __iomem *) IO_ADDRESS(mem->start); 592 dev->base = ioremap(mem->start, mem->end - mem->start + 1);
593 if (!dev->base) {
594 r = -ENOMEM;
595 goto err_free_mem;
596 }
597
593 platform_set_drvdata(pdev, dev); 598 platform_set_drvdata(pdev, dev);
594 599
595 if ((r = omap_i2c_get_clocks(dev)) != 0) 600 if ((r = omap_i2c_get_clocks(dev)) != 0)
596 goto err_free_mem; 601 goto err_iounmap;
597 602
598 omap_i2c_unidle(dev); 603 omap_i2c_unidle(dev);
599 604
@@ -640,6 +645,8 @@ err_unuse_clocks:
640 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 645 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
641 omap_i2c_idle(dev); 646 omap_i2c_idle(dev);
642 omap_i2c_put_clocks(dev); 647 omap_i2c_put_clocks(dev);
648err_iounmap:
649 iounmap(dev->base);
643err_free_mem: 650err_free_mem:
644 platform_set_drvdata(pdev, NULL); 651 platform_set_drvdata(pdev, NULL);
645 kfree(dev); 652 kfree(dev);
@@ -661,6 +668,7 @@ omap_i2c_remove(struct platform_device *pdev)
661 i2c_del_adapter(&dev->adapter); 668 i2c_del_adapter(&dev->adapter);
662 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 669 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
663 omap_i2c_put_clocks(dev); 670 omap_i2c_put_clocks(dev);
671 iounmap(dev->base);
664 kfree(dev); 672 kfree(dev);
665 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 673 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
666 release_mem_region(mem->start, (mem->end - mem->start) + 1); 674 release_mem_region(mem->start, (mem->end - mem->start) + 1);
diff --git a/drivers/input/keyboard/omap-keypad.c b/drivers/input/keyboard/omap-keypad.c
index 9a816db7cc25..69e674ecf19a 100644
--- a/drivers/input/keyboard/omap-keypad.c
+++ b/drivers/input/keyboard/omap-keypad.c
@@ -62,7 +62,7 @@ struct omap_kp {
62 unsigned int debounce; 62 unsigned int debounce;
63}; 63};
64 64
65DECLARE_TASKLET_DISABLED(kp_tasklet, omap_kp_tasklet, 0); 65static DECLARE_TASKLET_DISABLED(kp_tasklet, omap_kp_tasklet, 0);
66 66
67static int *keymap; 67static int *keymap;
68static unsigned int *row_gpios; 68static unsigned int *row_gpios;
diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c
index c16028872bbb..1b9fc3c6b875 100644
--- a/drivers/mmc/host/omap.c
+++ b/drivers/mmc/host/omap.c
@@ -172,7 +172,7 @@ struct mmc_omap_host {
172 struct omap_mmc_platform_data *pdata; 172 struct omap_mmc_platform_data *pdata;
173}; 173};
174 174
175void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot) 175static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
176{ 176{
177 unsigned long tick_ns; 177 unsigned long tick_ns;
178 178
@@ -182,7 +182,7 @@ void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
182 } 182 }
183} 183}
184 184
185void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable) 185static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
186{ 186{
187 unsigned long flags; 187 unsigned long flags;
188 188
@@ -1455,7 +1455,9 @@ static int __init mmc_omap_probe(struct platform_device *pdev)
1455 1455
1456 host->irq = irq; 1456 host->irq = irq;
1457 host->phys_base = host->mem_res->start; 1457 host->phys_base = host->mem_res->start;
1458 host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base); 1458 host->virt_base = ioremap(res->start, res->end - res->start + 1);
1459 if (!host->virt_base)
1460 goto err_ioremap;
1459 1461
1460 if (cpu_is_omap24xx()) { 1462 if (cpu_is_omap24xx()) {
1461 host->iclk = clk_get(&pdev->dev, "mmc_ick"); 1463 host->iclk = clk_get(&pdev->dev, "mmc_ick");
@@ -1510,6 +1512,8 @@ err_free_iclk:
1510 clk_put(host->iclk); 1512 clk_put(host->iclk);
1511 } 1513 }
1512err_free_mmc_host: 1514err_free_mmc_host:
1515 iounmap(host->virt_base);
1516err_ioremap:
1513 kfree(host); 1517 kfree(host);
1514err_free_mem_region: 1518err_free_mem_region:
1515 release_mem_region(res->start, res->end - res->start + 1); 1519 release_mem_region(res->start, res->end - res->start + 1);
@@ -1536,6 +1540,7 @@ static int mmc_omap_remove(struct platform_device *pdev)
1536 if (host->fclk && !IS_ERR(host->fclk)) 1540 if (host->fclk && !IS_ERR(host->fclk))
1537 clk_put(host->fclk); 1541 clk_put(host->fclk);
1538 1542
1543 iounmap(host->virt_base);
1539 release_mem_region(pdev->resource[0].start, 1544 release_mem_region(pdev->resource[0].start,
1540 pdev->resource[0].end - pdev->resource[0].start + 1); 1545 pdev->resource[0].end - pdev->resource[0].start + 1);
1541 1546
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index 74d1c906c5d6..b46c60b72708 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -64,10 +64,11 @@ sa1100_cs-$(CONFIG_SA1100_SHANNON) += sa1100_shannon.o
64sa1100_cs-$(CONFIG_SA1100_SIMPAD) += sa1100_simpad.o 64sa1100_cs-$(CONFIG_SA1100_SIMPAD) += sa1100_simpad.o
65 65
66pxa2xx_lubbock_cs-y += pxa2xx_lubbock.o sa1111_generic.o 66pxa2xx_lubbock_cs-y += pxa2xx_lubbock.o sa1111_generic.o
67pxa2xx_cm_x2xx_cs-y += pxa2xx_cm_x2xx.o pxa2xx_cm_x255.o pxa2xx_cm_x270.o
67pxa2xx-obj-$(CONFIG_ARCH_LUBBOCK) += pxa2xx_lubbock_cs.o 68pxa2xx-obj-$(CONFIG_ARCH_LUBBOCK) += pxa2xx_lubbock_cs.o
68pxa2xx-obj-$(CONFIG_MACH_MAINSTONE) += pxa2xx_mainstone.o 69pxa2xx-obj-$(CONFIG_MACH_MAINSTONE) += pxa2xx_mainstone.o
69pxa2xx-obj-$(CONFIG_PXA_SHARPSL) += pxa2xx_sharpsl.o 70pxa2xx-obj-$(CONFIG_PXA_SHARPSL) += pxa2xx_sharpsl.o
70pxa2xx-obj-$(CONFIG_MACH_ARMCORE) += pxa2xx_cm_x2xx.o pxa2xx_cm_x255.o pxa2xx_cm_x270.o 71pxa2xx-obj-$(CONFIG_MACH_ARMCORE) += pxa2xx_cm_x2xx_cs.o
71pxa2xx-obj-$(CONFIG_ARCH_VIPER) += pxa2xx_viper.o 72pxa2xx-obj-$(CONFIG_ARCH_VIPER) += pxa2xx_viper.o
72pxa2xx-obj-$(CONFIG_TRIZEPS_PCMCIA) += pxa2xx_trizeps.o 73pxa2xx-obj-$(CONFIG_TRIZEPS_PCMCIA) += pxa2xx_trizeps.o
73pxa2xx-obj-$(CONFIG_MACH_PALMTX) += pxa2xx_palmtx.o 74pxa2xx-obj-$(CONFIG_MACH_PALMTX) += pxa2xx_palmtx.o
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index d3ca7d32abe0..1528de23a650 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -2223,9 +2223,9 @@ serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2223 serial_outp(up, UART_EFR, efr); 2223 serial_outp(up, UART_EFR, efr);
2224 } 2224 }
2225 2225
2226#ifdef CONFIG_ARCH_OMAP15XX 2226#ifdef CONFIG_ARCH_OMAP
2227 /* Workaround to enable 115200 baud on OMAP1510 internal ports */ 2227 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2228 if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) { 2228 if (cpu_is_omap1510() && is_omap_port(up)) {
2229 if (baud == 115200) { 2229 if (baud == 115200) {
2230 quot = 1; 2230 quot = 1;
2231 serial_out(up, UART_OMAP_OSC_12M_SEL, 1); 2231 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
@@ -2278,18 +2278,27 @@ serial8250_pm(struct uart_port *port, unsigned int state,
2278 p->pm(port, state, oldstate); 2278 p->pm(port, state, oldstate);
2279} 2279}
2280 2280
2281static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2282{
2283 if (pt->port.iotype == UPIO_AU)
2284 return 0x100000;
2285#ifdef CONFIG_ARCH_OMAP
2286 if (is_omap_port(pt))
2287 return 0x16 << pt->port.regshift;
2288#endif
2289 return 8 << pt->port.regshift;
2290}
2291
2281/* 2292/*
2282 * Resource handling. 2293 * Resource handling.
2283 */ 2294 */
2284static int serial8250_request_std_resource(struct uart_8250_port *up) 2295static int serial8250_request_std_resource(struct uart_8250_port *up)
2285{ 2296{
2286 unsigned int size = 8 << up->port.regshift; 2297 unsigned int size = serial8250_port_size(up);
2287 int ret = 0; 2298 int ret = 0;
2288 2299
2289 switch (up->port.iotype) { 2300 switch (up->port.iotype) {
2290 case UPIO_AU: 2301 case UPIO_AU:
2291 size = 0x100000;
2292 /* fall thru */
2293 case UPIO_TSI: 2302 case UPIO_TSI:
2294 case UPIO_MEM32: 2303 case UPIO_MEM32:
2295 case UPIO_MEM: 2304 case UPIO_MEM:
@@ -2323,12 +2332,10 @@ static int serial8250_request_std_resource(struct uart_8250_port *up)
2323 2332
2324static void serial8250_release_std_resource(struct uart_8250_port *up) 2333static void serial8250_release_std_resource(struct uart_8250_port *up)
2325{ 2334{
2326 unsigned int size = 8 << up->port.regshift; 2335 unsigned int size = serial8250_port_size(up);
2327 2336
2328 switch (up->port.iotype) { 2337 switch (up->port.iotype) {
2329 case UPIO_AU: 2338 case UPIO_AU:
2330 size = 0x100000;
2331 /* fall thru */
2332 case UPIO_TSI: 2339 case UPIO_TSI:
2333 case UPIO_MEM32: 2340 case UPIO_MEM32:
2334 case UPIO_MEM: 2341 case UPIO_MEM:
diff --git a/drivers/serial/s3c2400.c b/drivers/serial/s3c2400.c
index c8b4266ac35f..4873f2978bd2 100644
--- a/drivers/serial/s3c2400.c
+++ b/drivers/serial/s3c2400.c
@@ -19,7 +19,7 @@
19 19
20#include <mach/hardware.h> 20#include <mach/hardware.h>
21 21
22#include <asm/plat-s3c/regs-serial.h> 22#include <plat/regs-serial.h>
23#include <mach/regs-gpio.h> 23#include <mach/regs-gpio.h>
24 24
25#include "samsung.h" 25#include "samsung.h"
diff --git a/drivers/serial/s3c2410.c b/drivers/serial/s3c2410.c
index 40a2531b5541..87c182ef71b8 100644
--- a/drivers/serial/s3c2410.c
+++ b/drivers/serial/s3c2410.c
@@ -21,7 +21,7 @@
21#include <asm/irq.h> 21#include <asm/irq.h>
22#include <mach/hardware.h> 22#include <mach/hardware.h>
23 23
24#include <asm/plat-s3c/regs-serial.h> 24#include <plat/regs-serial.h>
25#include <mach/regs-gpio.h> 25#include <mach/regs-gpio.h>
26 26
27#include "samsung.h" 27#include "samsung.h"
diff --git a/drivers/serial/s3c2412.c b/drivers/serial/s3c2412.c
index d0170319c729..fd017b375568 100644
--- a/drivers/serial/s3c2412.c
+++ b/drivers/serial/s3c2412.c
@@ -21,7 +21,7 @@
21#include <asm/irq.h> 21#include <asm/irq.h>
22#include <mach/hardware.h> 22#include <mach/hardware.h>
23 23
24#include <asm/plat-s3c/regs-serial.h> 24#include <plat/regs-serial.h>
25#include <mach/regs-gpio.h> 25#include <mach/regs-gpio.h>
26 26
27#include "samsung.h" 27#include "samsung.h"
diff --git a/drivers/serial/s3c2440.c b/drivers/serial/s3c2440.c
index d4a2b17b2498..317d239ab740 100644
--- a/drivers/serial/s3c2440.c
+++ b/drivers/serial/s3c2440.c
@@ -21,7 +21,7 @@
21#include <asm/irq.h> 21#include <asm/irq.h>
22#include <mach/hardware.h> 22#include <mach/hardware.h>
23 23
24#include <asm/plat-s3c/regs-serial.h> 24#include <plat/regs-serial.h>
25#include <mach/regs-gpio.h> 25#include <mach/regs-gpio.h>
26 26
27#include "samsung.h" 27#include "samsung.h"
diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c
index 5a88b3f9fe9b..1e219d3d0352 100644
--- a/drivers/serial/samsung.c
+++ b/drivers/serial/samsung.c
@@ -47,7 +47,7 @@
47 47
48#include <mach/hardware.h> 48#include <mach/hardware.h>
49 49
50#include <asm/plat-s3c/regs-serial.h> 50#include <plat/regs-serial.h>
51#include <mach/regs-gpio.h> 51#include <mach/regs-gpio.h>
52 52
53#include "samsung.h" 53#include "samsung.h"
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index 9d2186fd74aa..454a2712e629 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -119,12 +119,14 @@ struct omap2_mcspi {
119 struct clk *fck; 119 struct clk *fck;
120 /* Virtual base address of the controller */ 120 /* Virtual base address of the controller */
121 void __iomem *base; 121 void __iomem *base;
122 unsigned long phys;
122 /* SPI1 has 4 channels, while SPI2 has 2 */ 123 /* SPI1 has 4 channels, while SPI2 has 2 */
123 struct omap2_mcspi_dma *dma_channels; 124 struct omap2_mcspi_dma *dma_channels;
124}; 125};
125 126
126struct omap2_mcspi_cs { 127struct omap2_mcspi_cs {
127 void __iomem *base; 128 void __iomem *base;
129 unsigned long phys;
128 int word_len; 130 int word_len;
129}; 131};
130 132
@@ -233,7 +235,7 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
233 c = count; 235 c = count;
234 word_len = cs->word_len; 236 word_len = cs->word_len;
235 237
236 base = (unsigned long) io_v2p(cs->base); 238 base = cs->phys;
237 tx_reg = base + OMAP2_MCSPI_TX0; 239 tx_reg = base + OMAP2_MCSPI_TX0;
238 rx_reg = base + OMAP2_MCSPI_RX0; 240 rx_reg = base + OMAP2_MCSPI_RX0;
239 rx = xfer->rx_buf; 241 rx = xfer->rx_buf;
@@ -633,6 +635,7 @@ static int omap2_mcspi_setup(struct spi_device *spi)
633 if (!cs) 635 if (!cs)
634 return -ENOMEM; 636 return -ENOMEM;
635 cs->base = mcspi->base + spi->chip_select * 0x14; 637 cs->base = mcspi->base + spi->chip_select * 0x14;
638 cs->phys = mcspi->phys + spi->chip_select * 0x14;
636 spi->controller_state = cs; 639 spi->controller_state = cs;
637 } 640 }
638 641
@@ -1005,7 +1008,13 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
1005 goto err1; 1008 goto err1;
1006 } 1009 }
1007 1010
1008 mcspi->base = (void __iomem *) io_p2v(r->start); 1011 mcspi->phys = r->start;
1012 mcspi->base = ioremap(r->start, r->end - r->start + 1);
1013 if (!mcspi->base) {
1014 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1015 status = -ENOMEM;
1016 goto err1aa;
1017 }
1009 1018
1010 INIT_WORK(&mcspi->work, omap2_mcspi_work); 1019 INIT_WORK(&mcspi->work, omap2_mcspi_work);
1011 1020
@@ -1055,6 +1064,8 @@ err3:
1055err2: 1064err2:
1056 clk_put(mcspi->ick); 1065 clk_put(mcspi->ick);
1057err1a: 1066err1a:
1067 iounmap(mcspi->base);
1068err1aa:
1058 release_mem_region(r->start, (r->end - r->start) + 1); 1069 release_mem_region(r->start, (r->end - r->start) + 1);
1059err1: 1070err1:
1060 spi_master_put(master); 1071 spi_master_put(master);
@@ -1067,6 +1078,7 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1067 struct omap2_mcspi *mcspi; 1078 struct omap2_mcspi *mcspi;
1068 struct omap2_mcspi_dma *dma_channels; 1079 struct omap2_mcspi_dma *dma_channels;
1069 struct resource *r; 1080 struct resource *r;
1081 void __iomem *base;
1070 1082
1071 master = dev_get_drvdata(&pdev->dev); 1083 master = dev_get_drvdata(&pdev->dev);
1072 mcspi = spi_master_get_devdata(master); 1084 mcspi = spi_master_get_devdata(master);
@@ -1078,7 +1090,9 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1078 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1090 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1079 release_mem_region(r->start, (r->end - r->start) + 1); 1091 release_mem_region(r->start, (r->end - r->start) + 1);
1080 1092
1093 base = mcspi->base;
1081 spi_unregister_master(master); 1094 spi_unregister_master(master);
1095 iounmap(base);
1082 kfree(dma_channels); 1096 kfree(dma_channels);
1083 1097
1084 return 0; 1098 return 0;
diff --git a/drivers/spi/omap_uwire.c b/drivers/spi/omap_uwire.c
index 5515eb97d7c5..bab6ff061e91 100644
--- a/drivers/spi/omap_uwire.c
+++ b/drivers/spi/omap_uwire.c
@@ -59,7 +59,6 @@
59 * and irqs should show there too... 59 * and irqs should show there too...
60 */ 60 */
61#define UWIRE_BASE_PHYS 0xFFFB3000 61#define UWIRE_BASE_PHYS 0xFFFB3000
62#define UWIRE_BASE ((void *__iomem)IO_ADDRESS(UWIRE_BASE_PHYS))
63 62
64/* uWire Registers: */ 63/* uWire Registers: */
65#define UWIRE_IO_SIZE 0x20 64#define UWIRE_IO_SIZE 0x20
@@ -103,16 +102,21 @@ struct uwire_state {
103}; 102};
104 103
105/* REVISIT compile time constant for idx_shift? */ 104/* REVISIT compile time constant for idx_shift? */
105/*
106 * Or, put it in a structure which is used throughout the driver;
107 * that avoids having to issue two loads for each bit of static data.
108 */
106static unsigned int uwire_idx_shift; 109static unsigned int uwire_idx_shift;
110static void __iomem *uwire_base;
107 111
108static inline void uwire_write_reg(int idx, u16 val) 112static inline void uwire_write_reg(int idx, u16 val)
109{ 113{
110 __raw_writew(val, UWIRE_BASE + (idx << uwire_idx_shift)); 114 __raw_writew(val, uwire_base + (idx << uwire_idx_shift));
111} 115}
112 116
113static inline u16 uwire_read_reg(int idx) 117static inline u16 uwire_read_reg(int idx)
114{ 118{
115 return __raw_readw(UWIRE_BASE + (idx << uwire_idx_shift)); 119 return __raw_readw(uwire_base + (idx << uwire_idx_shift));
116} 120}
117 121
118static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags) 122static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
@@ -492,6 +496,14 @@ static int __init uwire_probe(struct platform_device *pdev)
492 return -ENODEV; 496 return -ENODEV;
493 497
494 uwire = spi_master_get_devdata(master); 498 uwire = spi_master_get_devdata(master);
499
500 uwire_base = ioremap(UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
501 if (!uwire_base) {
502 dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
503 spi_master_put(master);
504 return -ENOMEM;
505 }
506
495 dev_set_drvdata(&pdev->dev, uwire); 507 dev_set_drvdata(&pdev->dev, uwire);
496 508
497 uwire->ck = clk_get(&pdev->dev, "armxor_ck"); 509 uwire->ck = clk_get(&pdev->dev, "armxor_ck");
@@ -520,8 +532,10 @@ static int __init uwire_probe(struct platform_device *pdev)
520 uwire->bitbang.txrx_bufs = uwire_txrx; 532 uwire->bitbang.txrx_bufs = uwire_txrx;
521 533
522 status = spi_bitbang_start(&uwire->bitbang); 534 status = spi_bitbang_start(&uwire->bitbang);
523 if (status < 0) 535 if (status < 0) {
524 uwire_off(uwire); 536 uwire_off(uwire);
537 iounmap(uwire_base);
538 }
525 return status; 539 return status;
526} 540}
527 541
@@ -534,6 +548,7 @@ static int __exit uwire_remove(struct platform_device *pdev)
534 548
535 status = spi_bitbang_stop(&uwire->bitbang); 549 status = spi_bitbang_stop(&uwire->bitbang);
536 uwire_off(uwire); 550 uwire_off(uwire);
551 iounmap(uwire_base);
537 return status; 552 return status;
538} 553}
539 554
diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c
index 95b3ec89c126..522185629624 100644
--- a/drivers/usb/host/ohci-omap.c
+++ b/drivers/usb/host/ohci-omap.c
@@ -344,7 +344,12 @@ static int usb_hcd_omap_probe (const struct hc_driver *driver,
344 goto err1; 344 goto err1;
345 } 345 }
346 346
347 hcd->regs = (void __iomem *) (int) IO_ADDRESS(hcd->rsrc_start); 347 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
348 if (!hcd->regs) {
349 dev_err(&pdev->dev, "can't ioremap OHCI HCD\n");
350 retval = -ENOMEM;
351 goto err2;
352 }
348 353
349 ohci = hcd_to_ohci(hcd); 354 ohci = hcd_to_ohci(hcd);
350 ohci_hcd_init(ohci); 355 ohci_hcd_init(ohci);
@@ -355,11 +360,11 @@ static int usb_hcd_omap_probe (const struct hc_driver *driver,
355 irq = platform_get_irq(pdev, 0); 360 irq = platform_get_irq(pdev, 0);
356 if (irq < 0) { 361 if (irq < 0) {
357 retval = -ENXIO; 362 retval = -ENXIO;
358 goto err2; 363 goto err3;
359 } 364 }
360 retval = usb_add_hcd(hcd, irq, IRQF_DISABLED); 365 retval = usb_add_hcd(hcd, irq, IRQF_DISABLED);
361 if (retval) 366 if (retval)
362 goto err2; 367 goto err3;
363 368
364 host_initialized = 1; 369 host_initialized = 1;
365 370
@@ -367,6 +372,8 @@ static int usb_hcd_omap_probe (const struct hc_driver *driver,
367 omap_ohci_clock_power(0); 372 omap_ohci_clock_power(0);
368 373
369 return 0; 374 return 0;
375err3:
376 iounmap(hcd->regs);
370err2: 377err2:
371 release_mem_region(hcd->rsrc_start, hcd->rsrc_len); 378 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
372err1: 379err1:
@@ -401,6 +408,7 @@ usb_hcd_omap_remove (struct usb_hcd *hcd, struct platform_device *pdev)
401 } 408 }
402 if (machine_is_omap_osk()) 409 if (machine_is_omap_osk())
403 omap_free_gpio(9); 410 omap_free_gpio(9);
411 iounmap(hcd->regs);
404 release_mem_region(hcd->rsrc_start, hcd->rsrc_len); 412 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
405 usb_put_hcd(hcd); 413 usb_put_hcd(hcd);
406 clk_put(usb_dc_ck); 414 clk_put(usb_dc_ck);
diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
index 6efcf89e7fbe..dfb72f5e4c96 100644
--- a/drivers/video/omap/dispc.c
+++ b/drivers/video/omap/dispc.c
@@ -156,7 +156,7 @@ struct resmap {
156}; 156};
157 157
158static struct { 158static struct {
159 u32 base; 159 void __iomem *base;
160 160
161 struct omapfb_mem_desc mem_desc; 161 struct omapfb_mem_desc mem_desc;
162 struct resmap *res_map[DISPC_MEMTYPE_NUM]; 162 struct resmap *res_map[DISPC_MEMTYPE_NUM];
@@ -212,9 +212,9 @@ static void enable_rfbi_mode(int enable)
212 dispc_write_reg(DISPC_CONTROL, l); 212 dispc_write_reg(DISPC_CONTROL, l);
213 213
214 /* Set bypass mode in RFBI module */ 214 /* Set bypass mode in RFBI module */
215 l = __raw_readl(io_p2v(RFBI_CONTROL)); 215 l = __raw_readl(IO_ADDRESS(RFBI_CONTROL));
216 l |= enable ? 0 : (1 << 1); 216 l |= enable ? 0 : (1 << 1);
217 __raw_writel(l, io_p2v(RFBI_CONTROL)); 217 __raw_writel(l, IO_ADDRESS(RFBI_CONTROL));
218} 218}
219 219
220static void set_lcd_data_lines(int data_lines) 220static void set_lcd_data_lines(int data_lines)
@@ -1349,14 +1349,19 @@ static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
1349 1349
1350 memset(&dispc, 0, sizeof(dispc)); 1350 memset(&dispc, 0, sizeof(dispc));
1351 1351
1352 dispc.base = io_p2v(DISPC_BASE); 1352 dispc.base = ioremap(DISPC_BASE, SZ_1K);
1353 if (!dispc.base) {
1354 dev_err(fbdev->dev, "can't ioremap DISPC\n");
1355 return -ENOMEM;
1356 }
1357
1353 dispc.fbdev = fbdev; 1358 dispc.fbdev = fbdev;
1354 dispc.ext_mode = ext_mode; 1359 dispc.ext_mode = ext_mode;
1355 1360
1356 init_completion(&dispc.frame_done); 1361 init_completion(&dispc.frame_done);
1357 1362
1358 if ((r = get_dss_clocks()) < 0) 1363 if ((r = get_dss_clocks()) < 0)
1359 return r; 1364 goto fail0;
1360 1365
1361 enable_interface_clocks(1); 1366 enable_interface_clocks(1);
1362 enable_lcd_clocks(1); 1367 enable_lcd_clocks(1);
@@ -1414,7 +1419,7 @@ static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
1414 } 1419 }
1415 1420
1416 /* L3 firewall setting: enable access to OCM RAM */ 1421 /* L3 firewall setting: enable access to OCM RAM */
1417 __raw_writel(0x402000b0, io_p2v(0x680050a0)); 1422 __raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
1418 1423
1419 if ((r = alloc_palette_ram()) < 0) 1424 if ((r = alloc_palette_ram()) < 0)
1420 goto fail2; 1425 goto fail2;
@@ -1464,7 +1469,8 @@ fail1:
1464 enable_lcd_clocks(0); 1469 enable_lcd_clocks(0);
1465 enable_interface_clocks(0); 1470 enable_interface_clocks(0);
1466 put_dss_clocks(); 1471 put_dss_clocks();
1467 1472fail0:
1473 iounmap(dispc.base);
1468 return r; 1474 return r;
1469} 1475}
1470 1476
@@ -1481,6 +1487,7 @@ static void omap_dispc_cleanup(void)
1481 free_irq(INT_24XX_DSS_IRQ, dispc.fbdev); 1487 free_irq(INT_24XX_DSS_IRQ, dispc.fbdev);
1482 enable_interface_clocks(0); 1488 enable_interface_clocks(0);
1483 put_dss_clocks(); 1489 put_dss_clocks();
1490 iounmap(dispc.base);
1484} 1491}
1485 1492
1486const struct lcd_ctrl omap2_int_ctrl = { 1493const struct lcd_ctrl omap2_int_ctrl = {
diff --git a/drivers/video/omap/dispc.h b/drivers/video/omap/dispc.h
index eb1512b56ce8..ef720a78f6d5 100644
--- a/drivers/video/omap/dispc.h
+++ b/drivers/video/omap/dispc.h
@@ -40,4 +40,6 @@ extern void omap_dispc_enable_digit_out(int enable);
40extern int omap_dispc_request_irq(void (*callback)(void *data), void *data); 40extern int omap_dispc_request_irq(void (*callback)(void *data), void *data);
41extern void omap_dispc_free_irq(void); 41extern void omap_dispc_free_irq(void);
42 42
43extern const struct lcd_ctrl omap2_int_ctrl;
44
43#endif 45#endif
diff --git a/drivers/video/omap/lcd_h4.c b/drivers/video/omap/lcd_h4.c
index 88c19d424ef7..6ff56430341b 100644
--- a/drivers/video/omap/lcd_h4.c
+++ b/drivers/video/omap/lcd_h4.c
@@ -47,7 +47,7 @@ static unsigned long h4_panel_get_caps(struct lcd_panel *panel)
47 return 0; 47 return 0;
48} 48}
49 49
50struct lcd_panel h4_panel = { 50static struct lcd_panel h4_panel = {
51 .name = "h4", 51 .name = "h4",
52 .config = OMAP_LCDC_PANEL_TFT, 52 .config = OMAP_LCDC_PANEL_TFT,
53 53
@@ -91,7 +91,7 @@ static int h4_panel_resume(struct platform_device *pdev)
91 return 0; 91 return 0;
92} 92}
93 93
94struct platform_driver h4_panel_driver = { 94static struct platform_driver h4_panel_driver = {
95 .probe = h4_panel_probe, 95 .probe = h4_panel_probe,
96 .remove = h4_panel_remove, 96 .remove = h4_panel_remove,
97 .suspend = h4_panel_suspend, 97 .suspend = h4_panel_suspend,
diff --git a/drivers/video/omap/lcdc.c b/drivers/video/omap/lcdc.c
index 83514f066712..6e2ea7518761 100644
--- a/drivers/video/omap/lcdc.c
+++ b/drivers/video/omap/lcdc.c
@@ -34,6 +34,8 @@
34 34
35#include <asm/mach-types.h> 35#include <asm/mach-types.h>
36 36
37#include "lcdc.h"
38
37#define MODULE_NAME "lcdc" 39#define MODULE_NAME "lcdc"
38 40
39#define OMAP_LCDC_BASE 0xfffec000 41#define OMAP_LCDC_BASE 0xfffec000
diff --git a/drivers/video/omap/lcdc.h b/drivers/video/omap/lcdc.h
index adb731e5314a..845222270db3 100644
--- a/drivers/video/omap/lcdc.h
+++ b/drivers/video/omap/lcdc.h
@@ -4,4 +4,6 @@
4int omap_lcdc_set_dma_callback(void (*callback)(void *data), void *data); 4int omap_lcdc_set_dma_callback(void (*callback)(void *data), void *data);
5void omap_lcdc_free_dma_callback(void); 5void omap_lcdc_free_dma_callback(void);
6 6
7extern const struct lcd_ctrl omap1_int_ctrl;
8
7#endif 9#endif
diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
index 51a138bd113c..5a5e407dc45f 100644
--- a/drivers/video/omap/omapfb_main.c
+++ b/drivers/video/omap/omapfb_main.c
@@ -31,11 +31,14 @@
31#include <mach/dma.h> 31#include <mach/dma.h>
32#include <mach/omapfb.h> 32#include <mach/omapfb.h>
33 33
34#include "lcdc.h"
35#include "dispc.h"
36
34#define MODULE_NAME "omapfb" 37#define MODULE_NAME "omapfb"
35 38
36static unsigned int def_accel; 39static unsigned int def_accel;
37static unsigned long def_vram[OMAPFB_PLANE_NUM]; 40static unsigned long def_vram[OMAPFB_PLANE_NUM];
38static int def_vram_cnt; 41static unsigned int def_vram_cnt;
39static unsigned long def_vxres; 42static unsigned long def_vxres;
40static unsigned long def_vyres; 43static unsigned long def_vyres;
41static unsigned int def_rotate; 44static unsigned int def_rotate;
@@ -84,12 +87,10 @@ static struct caps_table_struct color_caps[] = {
84 * LCD panel 87 * LCD panel
85 * --------------------------------------------------------------------------- 88 * ---------------------------------------------------------------------------
86 */ 89 */
87extern struct lcd_ctrl omap1_int_ctrl;
88extern struct lcd_ctrl omap2_int_ctrl;
89extern struct lcd_ctrl hwa742_ctrl; 90extern struct lcd_ctrl hwa742_ctrl;
90extern struct lcd_ctrl blizzard_ctrl; 91extern struct lcd_ctrl blizzard_ctrl;
91 92
92static struct lcd_ctrl *ctrls[] = { 93static const struct lcd_ctrl *ctrls[] = {
93#ifdef CONFIG_ARCH_OMAP1 94#ifdef CONFIG_ARCH_OMAP1
94 &omap1_int_ctrl, 95 &omap1_int_ctrl,
95#else 96#else
@@ -740,7 +741,7 @@ static int omapfb_update_win(struct fb_info *fbi,
740 int ret; 741 int ret;
741 742
742 omapfb_rqueue_lock(plane->fbdev); 743 omapfb_rqueue_lock(plane->fbdev);
743 ret = omapfb_update_window_async(fbi, win, NULL, 0); 744 ret = omapfb_update_window_async(fbi, win, NULL, NULL);
744 omapfb_rqueue_unlock(plane->fbdev); 745 omapfb_rqueue_unlock(plane->fbdev);
745 746
746 return ret; 747 return ret;
@@ -768,7 +769,7 @@ static int omapfb_update_full_screen(struct fb_info *fbi)
768 win.format = 0; 769 win.format = 0;
769 770
770 omapfb_rqueue_lock(fbdev); 771 omapfb_rqueue_lock(fbdev);
771 r = fbdev->ctrl->update_window(fbi, &win, NULL, 0); 772 r = fbdev->ctrl->update_window(fbi, &win, NULL, NULL);
772 omapfb_rqueue_unlock(fbdev); 773 omapfb_rqueue_unlock(fbdev);
773 774
774 return r; 775 return r;
@@ -1047,7 +1048,7 @@ void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval)
1047 win.height = 2; 1048 win.height = 2;
1048 win.out_width = 2; 1049 win.out_width = 2;
1049 win.out_height = 2; 1050 win.out_height = 2;
1050 fbdev->ctrl->update_window(fbdev->fb_info[0], &win, NULL, 0); 1051 fbdev->ctrl->update_window(fbdev->fb_info[0], &win, NULL, NULL);
1051 } 1052 }
1052 omapfb_rqueue_unlock(fbdev); 1053 omapfb_rqueue_unlock(fbdev);
1053} 1054}
diff --git a/drivers/video/omap/rfbi.c b/drivers/video/omap/rfbi.c
index 4a6f13d3facf..a13c8dcad2a8 100644
--- a/drivers/video/omap/rfbi.c
+++ b/drivers/video/omap/rfbi.c
@@ -59,7 +59,7 @@
59#define DISPC_CONTROL 0x0040 59#define DISPC_CONTROL 0x0040
60 60
61static struct { 61static struct {
62 u32 base; 62 void __iomem *base;
63 void (*lcdc_callback)(void *data); 63 void (*lcdc_callback)(void *data);
64 void *lcdc_callback_data; 64 void *lcdc_callback_data;
65 unsigned long l4_khz; 65 unsigned long l4_khz;
@@ -518,7 +518,11 @@ static int rfbi_init(struct omapfb_device *fbdev)
518 int r; 518 int r;
519 519
520 rfbi.fbdev = fbdev; 520 rfbi.fbdev = fbdev;
521 rfbi.base = io_p2v(RFBI_BASE); 521 rfbi.base = ioremap(RFBI_BASE, SZ_1K);
522 if (!rfbi.base) {
523 dev_err(fbdev->dev, "can't ioremap RFBI\n");
524 return -ENOMEM;
525 }
522 526
523 if ((r = rfbi_get_clocks()) < 0) 527 if ((r = rfbi_get_clocks()) < 0)
524 return r; 528 return r;
@@ -566,6 +570,7 @@ static void rfbi_cleanup(void)
566{ 570{
567 omap_dispc_free_irq(); 571 omap_dispc_free_irq();
568 rfbi_put_clocks(); 572 rfbi_put_clocks();
573 iounmap(rfbi.base);
569} 574}
570 575
571const struct lcd_ctrl_extif omap2_ext_if = { 576const struct lcd_ctrl_extif omap2_ext_if = {
diff --git a/drivers/video/omap/sossi.c b/drivers/video/omap/sossi.c
index 6359353c2c67..a76946220249 100644
--- a/drivers/video/omap/sossi.c
+++ b/drivers/video/omap/sossi.c
@@ -574,7 +574,12 @@ static int sossi_init(struct omapfb_device *fbdev)
574 struct clk *dpll1out_ck; 574 struct clk *dpll1out_ck;
575 int r; 575 int r;
576 576
577 sossi.base = (void __iomem *)IO_ADDRESS(OMAP_SOSSI_BASE); 577 sossi.base = ioremap(OMAP_SOSSI_BASE, SZ_1K);
578 if (!sossi.base) {
579 dev_err(fbdev->dev, "can't ioremap SoSSI\n");
580 return -ENOMEM;
581 }
582
578 sossi.fbdev = fbdev; 583 sossi.fbdev = fbdev;
579 spin_lock_init(&sossi.lock); 584 spin_lock_init(&sossi.lock);
580 585
@@ -665,6 +670,7 @@ static void sossi_cleanup(void)
665{ 670{
666 omap_lcdc_free_dma_callback(); 671 omap_lcdc_free_dma_callback();
667 clk_put(sossi.fck); 672 clk_put(sossi.fck);
673 iounmap(sossi.base);
668} 674}
669 675
670struct lcd_ctrl_extif omap1_ext_if = { 676struct lcd_ctrl_extif omap1_ext_if = {