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-rw-r--r--drivers/gpu/drm/i915/Makefile2
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c4
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c4
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h17
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c25
-rw-r--r--drivers/gpu/drm/i915/i915_opregion.c371
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
7 files changed, 415 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a9e60464df74..b032808d9c14 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -3,7 +3,7 @@
3# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. 3# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
4 4
5ccflags-y := -Iinclude/drm 5ccflags-y := -Iinclude/drm
6i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o 6i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o i915_opregion.o
7 7
8i915-$(CONFIG_COMPAT) += i915_ioc32.o 8i915-$(CONFIG_COMPAT) += i915_ioc32.o
9 9
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index f1b5aa92fa83..29115450ee46 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -810,6 +810,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
810 if (!IS_I945G(dev) && !IS_I945GM(dev)) 810 if (!IS_I945G(dev) && !IS_I945GM(dev))
811 pci_enable_msi(dev->pdev); 811 pci_enable_msi(dev->pdev);
812 812
813 intel_opregion_init(dev);
814
813 spin_lock_init(&dev_priv->user_irq_lock); 815 spin_lock_init(&dev_priv->user_irq_lock);
814 816
815 return ret; 817 return ret;
@@ -827,6 +829,8 @@ int i915_driver_unload(struct drm_device *dev)
827 if (dev_priv->mmio_map) 829 if (dev_priv->mmio_map)
828 drm_rmmap(dev, dev_priv->mmio_map); 830 drm_rmmap(dev, dev_priv->mmio_map);
829 831
832 intel_opregion_free(dev);
833
830 drm_free(dev->dev_private, sizeof(drm_i915_private_t), 834 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
831 DRM_MEM_DRIVER); 835 DRM_MEM_DRIVER);
832 836
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6c99aab12da3..d95eca2bc454 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -371,6 +371,8 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
371 371
372 i915_save_vga(dev); 372 i915_save_vga(dev);
373 373
374 intel_opregion_free(dev);
375
374 if (state.event == PM_EVENT_SUSPEND) { 376 if (state.event == PM_EVENT_SUSPEND) {
375 /* Shut down the device */ 377 /* Shut down the device */
376 pci_disable_device(dev->pdev); 378 pci_disable_device(dev->pdev);
@@ -532,6 +534,8 @@ static int i915_resume(struct drm_device *dev)
532 534
533 i915_restore_vga(dev); 535 i915_restore_vga(dev);
534 536
537 intel_opregion_init(dev);
538
535 return 0; 539 return 0;
536} 540}
537 541
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8daf0d84cd5a..e4bd01c511a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -82,6 +82,14 @@ typedef struct _drm_i915_vbl_swap {
82 unsigned int sequence; 82 unsigned int sequence;
83} drm_i915_vbl_swap_t; 83} drm_i915_vbl_swap_t;
84 84
85struct intel_opregion {
86 struct opregion_header *header;
87 struct opregion_acpi *acpi;
88 struct opregion_swsci *swsci;
89 struct opregion_asle *asle;
90 int enabled;
91};
92
85typedef struct drm_i915_private { 93typedef struct drm_i915_private {
86 drm_local_map_t *sarea; 94 drm_local_map_t *sarea;
87 drm_local_map_t *mmio_map; 95 drm_local_map_t *mmio_map;
@@ -122,6 +130,8 @@ typedef struct drm_i915_private {
122 drm_i915_vbl_swap_t vbl_swaps; 130 drm_i915_vbl_swap_t vbl_swaps;
123 unsigned int swaps_pending; 131 unsigned int swaps_pending;
124 132
133 struct intel_opregion opregion;
134
125 /* Register state */ 135 /* Register state */
126 u8 saveLBB; 136 u8 saveLBB;
127 u32 saveDSPACNTR; 137 u32 saveDSPACNTR;
@@ -244,6 +254,7 @@ extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
244 struct drm_file *file_priv); 254 struct drm_file *file_priv);
245extern int i915_vblank_swap(struct drm_device *dev, void *data, 255extern int i915_vblank_swap(struct drm_device *dev, void *data,
246 struct drm_file *file_priv); 256 struct drm_file *file_priv);
257extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
247 258
248/* i915_mem.c */ 259/* i915_mem.c */
249extern int i915_mem_alloc(struct drm_device *dev, void *data, 260extern int i915_mem_alloc(struct drm_device *dev, void *data,
@@ -258,6 +269,12 @@ extern void i915_mem_takedown(struct mem_block **heap);
258extern void i915_mem_release(struct drm_device * dev, 269extern void i915_mem_release(struct drm_device * dev,
259 struct drm_file *file_priv, struct mem_block *heap); 270 struct drm_file *file_priv, struct mem_block *heap);
260 271
272/* i915_opregion.c */
273extern int intel_opregion_init(struct drm_device *dev);
274extern void intel_opregion_free(struct drm_device *dev);
275extern void opregion_asle_intr(struct drm_device *dev);
276extern void opregion_enable_asle(struct drm_device *dev);
277
261#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 278#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
262#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 279#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
263#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 280#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 24d11ed5bbc7..ae7d3a82a6d1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -36,9 +36,11 @@
36/** These are the interrupts used by the driver */ 36/** These are the interrupts used by the driver */
37#define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT | \ 37#define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT | \
38 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | \ 38 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | \
39 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) 39 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT | \
40 I915_ASLE_INTERRUPT | \
41 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
40 42
41static inline void 43void
42i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) 44i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
43{ 45{
44 if ((dev_priv->irq_mask_reg & mask) != 0) { 46 if ((dev_priv->irq_mask_reg & mask) != 0) {
@@ -274,6 +276,9 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
274 return IRQ_NONE; 276 return IRQ_NONE;
275 } 277 }
276 278
279 I915_WRITE(PIPEASTAT, pipea_stats);
280 I915_WRITE(PIPEBSTAT, pipeb_stats);
281
277 I915_WRITE(IIR, iir); 282 I915_WRITE(IIR, iir);
278 if (dev->pdev->msi_enabled) 283 if (dev->pdev->msi_enabled)
279 I915_WRITE(IMR, dev_priv->irq_mask_reg); 284 I915_WRITE(IMR, dev_priv->irq_mask_reg);
@@ -306,14 +311,14 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
306 311
307 if (dev_priv->swaps_pending > 0) 312 if (dev_priv->swaps_pending > 0)
308 drm_locked_tasklet(dev, i915_vblank_tasklet); 313 drm_locked_tasklet(dev, i915_vblank_tasklet);
309 I915_WRITE(PIPEASTAT,
310 pipea_stats|I915_VBLANK_INTERRUPT_ENABLE|
311 PIPE_VBLANK_INTERRUPT_STATUS);
312 I915_WRITE(PIPEBSTAT,
313 pipeb_stats|I915_VBLANK_INTERRUPT_ENABLE|
314 PIPE_VBLANK_INTERRUPT_STATUS);
315 } 314 }
316 315
316 if (iir & I915_ASLE_INTERRUPT)
317 opregion_asle_intr(dev);
318
319 if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
320 opregion_asle_intr(dev);
321
317 return IRQ_HANDLED; 322 return IRQ_HANDLED;
318} 323}
319 324
@@ -661,10 +666,14 @@ void i915_driver_irq_postinstall(struct drm_device * dev)
661 if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B) 666 if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
662 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 667 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
663 668
669 dev_priv->irq_mask_reg &= I915_INTERRUPT_ENABLE_MASK;
670
664 I915_WRITE(IMR, dev_priv->irq_mask_reg); 671 I915_WRITE(IMR, dev_priv->irq_mask_reg);
665 I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK); 672 I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
666 (void) I915_READ(IER); 673 (void) I915_READ(IER);
667 674
675 opregion_enable_asle(dev);
676
668 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); 677 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
669} 678}
670 679
diff --git a/drivers/gpu/drm/i915/i915_opregion.c b/drivers/gpu/drm/i915/i915_opregion.c
new file mode 100644
index 000000000000..1787a0c7e3ab
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_opregion.c
@@ -0,0 +1,371 @@
1/*
2 * Copyright 2008 Intel Corporation <hong.liu@intel.com>
3 * Copyright 2008 Red Hat <mjg@redhat.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20 * NON-INFRINGEMENT. IN NO EVENT SHALL INTEL AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
22 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * SOFTWARE.
25 *
26 */
27
28#include <linux/acpi.h>
29
30#include "drmP.h"
31#include "i915_drm.h"
32#include "i915_drv.h"
33
34#define PCI_ASLE 0xe4
35#define PCI_LBPC 0xf4
36#define PCI_ASLS 0xfc
37
38#define OPREGION_SZ (8*1024)
39#define OPREGION_HEADER_OFFSET 0
40#define OPREGION_ACPI_OFFSET 0x100
41#define OPREGION_SWSCI_OFFSET 0x200
42#define OPREGION_ASLE_OFFSET 0x300
43#define OPREGION_VBT_OFFSET 0x1000
44
45#define OPREGION_SIGNATURE "IntelGraphicsMem"
46#define MBOX_ACPI (1<<0)
47#define MBOX_SWSCI (1<<1)
48#define MBOX_ASLE (1<<2)
49
50struct opregion_header {
51 u8 signature[16];
52 u32 size;
53 u32 opregion_ver;
54 u8 bios_ver[32];
55 u8 vbios_ver[16];
56 u8 driver_ver[16];
57 u32 mboxes;
58 u8 reserved[164];
59} __attribute__((packed));
60
61/* OpRegion mailbox #1: public ACPI methods */
62struct opregion_acpi {
63 u32 drdy; /* driver readiness */
64 u32 csts; /* notification status */
65 u32 cevt; /* current event */
66 u8 rsvd1[20];
67 u32 didl[8]; /* supported display devices ID list */
68 u32 cpdl[8]; /* currently presented display list */
69 u32 cadl[8]; /* currently active display list */
70 u32 nadl[8]; /* next active devices list */
71 u32 aslp; /* ASL sleep time-out */
72 u32 tidx; /* toggle table index */
73 u32 chpd; /* current hotplug enable indicator */
74 u32 clid; /* current lid state*/
75 u32 cdck; /* current docking state */
76 u32 sxsw; /* Sx state resume */
77 u32 evts; /* ASL supported events */
78 u32 cnot; /* current OS notification */
79 u32 nrdy; /* driver status */
80 u8 rsvd2[60];
81} __attribute__((packed));
82
83/* OpRegion mailbox #2: SWSCI */
84struct opregion_swsci {
85 u32 scic; /* SWSCI command|status|data */
86 u32 parm; /* command parameters */
87 u32 dslp; /* driver sleep time-out */
88 u8 rsvd[244];
89} __attribute__((packed));
90
91/* OpRegion mailbox #3: ASLE */
92struct opregion_asle {
93 u32 ardy; /* driver readiness */
94 u32 aslc; /* ASLE interrupt command */
95 u32 tche; /* technology enabled indicator */
96 u32 alsi; /* current ALS illuminance reading */
97 u32 bclp; /* backlight brightness to set */
98 u32 pfit; /* panel fitting state */
99 u32 cblv; /* current brightness level */
100 u16 bclm[20]; /* backlight level duty cycle mapping table */
101 u32 cpfm; /* current panel fitting mode */
102 u32 epfm; /* enabled panel fitting modes */
103 u8 plut[74]; /* panel LUT and identifier */
104 u32 pfmb; /* PWM freq and min brightness */
105 u8 rsvd[102];
106} __attribute__((packed));
107
108/* ASLE irq request bits */
109#define ASLE_SET_ALS_ILLUM (1 << 0)
110#define ASLE_SET_BACKLIGHT (1 << 1)
111#define ASLE_SET_PFIT (1 << 2)
112#define ASLE_SET_PWM_FREQ (1 << 3)
113#define ASLE_REQ_MSK 0xf
114
115/* response bits of ASLE irq request */
116#define ASLE_ALS_ILLUM_FAIL (2<<10)
117#define ASLE_BACKLIGHT_FAIL (2<<12)
118#define ASLE_PFIT_FAIL (2<<14)
119#define ASLE_PWM_FREQ_FAIL (2<<16)
120
121/* ASLE backlight brightness to set */
122#define ASLE_BCLP_VALID (1<<31)
123#define ASLE_BCLP_MSK (~(1<<31))
124
125/* ASLE panel fitting request */
126#define ASLE_PFIT_VALID (1<<31)
127#define ASLE_PFIT_CENTER (1<<0)
128#define ASLE_PFIT_STRETCH_TEXT (1<<1)
129#define ASLE_PFIT_STRETCH_GFX (1<<2)
130
131/* PWM frequency and minimum brightness */
132#define ASLE_PFMB_BRIGHTNESS_MASK (0xff)
133#define ASLE_PFMB_BRIGHTNESS_VALID (1<<8)
134#define ASLE_PFMB_PWM_MASK (0x7ffffe00)
135#define ASLE_PFMB_PWM_VALID (1<<31)
136
137#define ASLE_CBLV_VALID (1<<31)
138
139static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
140{
141 struct drm_i915_private *dev_priv = dev->dev_private;
142 struct opregion_asle *asle = dev_priv->opregion.asle;
143 u32 blc_pwm_ctl, blc_pwm_ctl2;
144
145 if (!(bclp & ASLE_BCLP_VALID))
146 return ASLE_BACKLIGHT_FAIL;
147
148 bclp &= ASLE_BCLP_MSK;
149 if (bclp < 0 || bclp > 255)
150 return ASLE_BACKLIGHT_FAIL;
151
152 blc_pwm_ctl = I915_READ(BLC_PWM_CTL);
153 blc_pwm_ctl &= ~BACKLIGHT_DUTY_CYCLE_MASK;
154 blc_pwm_ctl2 = I915_READ(BLC_PWM_CTL2);
155
156 if (blc_pwm_ctl2 & BLM_COMBINATION_MODE)
157 pci_write_config_dword(dev->pdev, PCI_LBPC, bclp);
158 else
159 I915_WRITE(BLC_PWM_CTL, blc_pwm_ctl | ((bclp * 0x101)-1));
160
161 asle->cblv = (bclp*0x64)/0xff | ASLE_CBLV_VALID;
162
163 return 0;
164}
165
166static u32 asle_set_als_illum(struct drm_device *dev, u32 alsi)
167{
168 /* alsi is the current ALS reading in lux. 0 indicates below sensor
169 range, 0xffff indicates above sensor range. 1-0xfffe are valid */
170 return 0;
171}
172
173static u32 asle_set_pwm_freq(struct drm_device *dev, u32 pfmb)
174{
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 if (pfmb & ASLE_PFMB_PWM_VALID) {
177 u32 blc_pwm_ctl = I915_READ(BLC_PWM_CTL);
178 u32 pwm = pfmb & ASLE_PFMB_PWM_MASK;
179 blc_pwm_ctl &= BACKLIGHT_DUTY_CYCLE_MASK;
180 pwm = pwm >> 9;
181 /* FIXME - what do we do with the PWM? */
182 }
183 return 0;
184}
185
186static u32 asle_set_pfit(struct drm_device *dev, u32 pfit)
187{
188 /* Panel fitting is currently controlled by the X code, so this is a
189 noop until modesetting support works fully */
190 if (!(pfit & ASLE_PFIT_VALID))
191 return ASLE_PFIT_FAIL;
192 return 0;
193}
194
195void opregion_asle_intr(struct drm_device *dev)
196{
197 struct drm_i915_private *dev_priv = dev->dev_private;
198 struct opregion_asle *asle = dev_priv->opregion.asle;
199 u32 asle_stat = 0;
200 u32 asle_req;
201
202 if (!asle)
203 return;
204
205 asle_req = asle->aslc & ASLE_REQ_MSK;
206
207 if (!asle_req) {
208 DRM_DEBUG("non asle set request??\n");
209 return;
210 }
211
212 if (asle_req & ASLE_SET_ALS_ILLUM)
213 asle_stat |= asle_set_als_illum(dev, asle->alsi);
214
215 if (asle_req & ASLE_SET_BACKLIGHT)
216 asle_stat |= asle_set_backlight(dev, asle->bclp);
217
218 if (asle_req & ASLE_SET_PFIT)
219 asle_stat |= asle_set_pfit(dev, asle->pfit);
220
221 if (asle_req & ASLE_SET_PWM_FREQ)
222 asle_stat |= asle_set_pwm_freq(dev, asle->pfmb);
223
224 asle->aslc = asle_stat;
225}
226
227#define ASLE_ALS_EN (1<<0)
228#define ASLE_BLC_EN (1<<1)
229#define ASLE_PFIT_EN (1<<2)
230#define ASLE_PFMB_EN (1<<3)
231
232void opregion_enable_asle(struct drm_device *dev)
233{
234 struct drm_i915_private *dev_priv = dev->dev_private;
235 struct opregion_asle *asle = dev_priv->opregion.asle;
236
237 if (asle) {
238 u32 pipeb_stats = I915_READ(PIPEBSTAT);
239 if (IS_MOBILE(dev)) {
240 /* Many devices trigger events with a write to the
241 legacy backlight controller, so we need to ensure
242 that it's able to generate interrupts */
243 I915_WRITE(PIPEBSTAT, pipeb_stats |=
244 I915_LEGACY_BLC_EVENT_ENABLE);
245 i915_enable_irq(dev_priv, I915_ASLE_INTERRUPT |
246 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
247 } else
248 i915_enable_irq(dev_priv, I915_ASLE_INTERRUPT);
249
250 asle->tche = ASLE_ALS_EN | ASLE_BLC_EN | ASLE_PFIT_EN |
251 ASLE_PFMB_EN;
252 asle->ardy = 1;
253 }
254}
255
256#define ACPI_EV_DISPLAY_SWITCH (1<<0)
257#define ACPI_EV_LID (1<<1)
258#define ACPI_EV_DOCK (1<<2)
259
260static struct intel_opregion *system_opregion;
261
262int intel_opregion_video_event(struct notifier_block *nb, unsigned long val,
263 void *data)
264{
265 /* The only video events relevant to opregion are 0x80. These indicate
266 either a docking event, lid switch or display switch request. In
267 Linux, these are handled by the dock, button and video drivers.
268 We might want to fix the video driver to be opregion-aware in
269 future, but right now we just indicate to the firmware that the
270 request has been handled */
271
272 struct opregion_acpi *acpi;
273
274 if (!system_opregion)
275 return NOTIFY_DONE;
276
277 acpi = system_opregion->acpi;
278 acpi->csts = 0;
279
280 return NOTIFY_OK;
281}
282
283static struct notifier_block intel_opregion_notifier = {
284 .notifier_call = intel_opregion_video_event,
285};
286
287int intel_opregion_init(struct drm_device *dev)
288{
289 struct drm_i915_private *dev_priv = dev->dev_private;
290 struct intel_opregion *opregion = &dev_priv->opregion;
291 void *base;
292 u32 asls, mboxes;
293 int err = 0;
294
295 pci_read_config_dword(dev->pdev, PCI_ASLS, &asls);
296 DRM_DEBUG("graphic opregion physical addr: 0x%x\n", asls);
297 if (asls == 0) {
298 DRM_DEBUG("ACPI OpRegion not supported!\n");
299 return -ENOTSUPP;
300 }
301
302 base = ioremap(asls, OPREGION_SZ);
303 if (!base)
304 return -ENOMEM;
305
306 opregion->header = base;
307 if (memcmp(opregion->header->signature, OPREGION_SIGNATURE, 16)) {
308 DRM_DEBUG("opregion signature mismatch\n");
309 err = -EINVAL;
310 goto err_out;
311 }
312
313 mboxes = opregion->header->mboxes;
314 if (mboxes & MBOX_ACPI) {
315 DRM_DEBUG("Public ACPI methods supported\n");
316 opregion->acpi = base + OPREGION_ACPI_OFFSET;
317 } else {
318 DRM_DEBUG("Public ACPI methods not supported\n");
319 err = -ENOTSUPP;
320 goto err_out;
321 }
322 opregion->enabled = 1;
323
324 if (mboxes & MBOX_SWSCI) {
325 DRM_DEBUG("SWSCI supported\n");
326 opregion->swsci = base + OPREGION_SWSCI_OFFSET;
327 }
328 if (mboxes & MBOX_ASLE) {
329 DRM_DEBUG("ASLE supported\n");
330 opregion->asle = base + OPREGION_ASLE_OFFSET;
331 }
332
333 /* Notify BIOS we are ready to handle ACPI video ext notifs.
334 * Right now, all the events are handled by the ACPI video module.
335 * We don't actually need to do anything with them. */
336 opregion->acpi->csts = 0;
337 opregion->acpi->drdy = 1;
338
339 system_opregion = opregion;
340 register_acpi_notifier(&intel_opregion_notifier);
341
342 return 0;
343
344err_out:
345 iounmap(opregion->header);
346 opregion->header = NULL;
347 return err;
348}
349
350void intel_opregion_free(struct drm_device *dev)
351{
352 struct drm_i915_private *dev_priv = dev->dev_private;
353 struct intel_opregion *opregion = &dev_priv->opregion;
354
355 if (!opregion->enabled)
356 return;
357
358 opregion->acpi->drdy = 0;
359
360 system_opregion = NULL;
361 unregister_acpi_notifier(&intel_opregion_notifier);
362
363 /* just clear all opregion memory pointers now */
364 iounmap(opregion->header);
365 opregion->header = NULL;
366 opregion->acpi = NULL;
367 opregion->swsci = NULL;
368 opregion->asle = NULL;
369
370 opregion->enabled = 0;
371}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 477c64e6ba2d..43ad2cb8b9f5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -740,6 +740,7 @@
740#define BLC_PWM_CTL 0x61254 740#define BLC_PWM_CTL 0x61254
741#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 741#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
742#define BLC_PWM_CTL2 0x61250 /* 965+ only */ 742#define BLC_PWM_CTL2 0x61250 /* 965+ only */
743#define BLM_COMBINATION_MODE (1 << 30)
743/* 744/*
744 * This is the most significant 15 bits of the number of backlight cycles in a 745 * This is the most significant 15 bits of the number of backlight cycles in a
745 * complete cycle of the modulated backlight control. 746 * complete cycle of the modulated backlight control.