2 files changed, 21 insertions, 0 deletions

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 475cf8a6d165..736bd2cbc1f0 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -40,6 +40,7 @@ config MACH_ARMADA_375
         select ARM_GIC
         select ARMADA_375_CLK
         select CPU_V7
+        select HAVE_ARM_SCU
         select MACH_MVEBU_V7
         select PINCTRL_ARMADA_375
         help
@@ -53,6 +54,7 @@ config MACH_ARMADA_38X
         select ARM_GIC
         select ARMADA_38X_CLK
         select CPU_V7
+        select HAVE_ARM_SCU
         select MACH_MVEBU_V7
         select PINCTRL_ARMADA_38X
         help
diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index 1730e0cdb6f6..85f964e55bf3 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -27,12 +27,30 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <asm/smp_scu.h>
 #include "armada-370-xp.h"
 #include "common.h"
 #include "coherency.h"
 #include "mvebu-soc-id.h"
 
 /*
+ * Enables the SCU when available. Obviously, this is only useful on
+ * Cortex-A based SOCs, not on PJ4B based ones.
+ */
+static void __init mvebu_scu_enable(void)
+{
+        void __iomem *scu_base;
+
+        struct device_node *np =
+                of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+        if (np) {
+                scu_base = of_iomap(np, 0);
+                scu_enable(scu_base);
+                of_node_put(np);
+        }
+}
+
+/*
  * Early versions of Armada 375 SoC have a bug where the BootROM
  * leaves an external data abort pending. The kernel is hit by this
  * data abort as soon as it enters userspace, because it unmasks the
@@ -57,6 +75,7 @@ static void __init mvebu_timer_and_clk_init(void)
 {
         of_clk_init(NULL);
         clocksource_of_init();
+        mvebu_scu_enable();
         coherency_init();
         BUG_ON(mvebu_mbus_dt_init(coherency_available()));
 #ifdef CONFIG_CACHE_L2X0