3 files changed, 19 insertions, 2 deletions

diff --git a/sound/soc/blackfin/bf5xx-i2s-pcm.c b/sound/soc/blackfin/bf5xx-i2s-pcm.c
index b5101efd1c87..f1fd95bb6416 100644
--- a/sound/soc/blackfin/bf5xx-i2s-pcm.c
+++ b/sound/soc/blackfin/bf5xx-i2s-pcm.c
@@ -138,11 +138,20 @@ static snd_pcm_uframes_t bf5xx_pcm_pointer(struct snd_pcm_substream *substream)
         pr_debug("%s enter\n", __func__);
         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
                 diff = sport_curr_offset_tx(sport);
-                frames = bytes_to_frames(substream->runtime, diff);
         } else {
                 diff = sport_curr_offset_rx(sport);
-                frames = bytes_to_frames(substream->runtime, diff);
         }
+
+        /*
+         * TX at least can report one frame beyond the end of the
+         * buffer if we hit the wraparound case - clamp to within the
+         * buffer as the ALSA APIs require.
+         */
+        if (diff == snd_pcm_lib_buffer_bytes(substream))
+                diff = 0;
+
+        frames = bytes_to_frames(substream->runtime, diff);
+
         return frames;
 }
 
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index 970a95c5360b..c2fc0356c2a4 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -1713,6 +1713,8 @@ static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
                                     reg);
+
+                msleep(5);
         }
 
         wm8994->fll[id].in = freq_in;
diff --git a/sound/soc/tegra/tegra_i2s.c b/sound/soc/tegra/tegra_i2s.c
index 6b817e20548c..95f03c10b4f7 100644
--- a/sound/soc/tegra/tegra_i2s.c
+++ b/sound/soc/tegra/tegra_i2s.c
@@ -222,12 +222,18 @@ static int tegra_i2s_hw_params(struct snd_pcm_substream *substream,
         if (i2sclock % (2 * srate))
                 reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE;
 
+        if (!i2s->clk_refs)
+                clk_enable(i2s->clk_i2s);
+
         tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg);
 
         tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR,
                 TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
                 TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
 
+        if (!i2s->clk_refs)
+                clk_disable(i2s->clk_i2s);
+
         return 0;
 }