diff options
-rw-r--r-- | arch/arm/mach-exynos/clock-exynos4.c | 41 | ||||
-rw-r--r-- | arch/arm/mach-exynos/clock-exynos4.h | 3 | ||||
-rw-r--r-- | arch/arm/mach-exynos/clock-exynos4210.c | 37 |
3 files changed, 42 insertions, 39 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index bcb7db453145..18d59d3868b3 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c | |||
@@ -620,10 +620,6 @@ static struct clk exynos4_init_clocks_off[] = { | |||
620 | .enable = exynos4_clk_ip_peril_ctrl, | 620 | .enable = exynos4_clk_ip_peril_ctrl, |
621 | .ctrlbit = (1 << 27), | 621 | .ctrlbit = (1 << 27), |
622 | }, { | 622 | }, { |
623 | .name = "fimg2d", | ||
624 | .enable = exynos4_clk_ip_image_ctrl, | ||
625 | .ctrlbit = (1 << 0), | ||
626 | }, { | ||
627 | .name = "mfc", | 623 | .name = "mfc", |
628 | .devname = "s5p-mfc", | 624 | .devname = "s5p-mfc", |
629 | .enable = exynos4_clk_ip_mfc_ctrl, | 625 | .enable = exynos4_clk_ip_mfc_ctrl, |
@@ -819,47 +815,21 @@ static struct clk *exynos4_clkset_mout_g2d0_list[] = { | |||
819 | [1] = &exynos4_clk_sclk_apll.clk, | 815 | [1] = &exynos4_clk_sclk_apll.clk, |
820 | }; | 816 | }; |
821 | 817 | ||
822 | static struct clksrc_sources exynos4_clkset_mout_g2d0 = { | 818 | struct clksrc_sources exynos4_clkset_mout_g2d0 = { |
823 | .sources = exynos4_clkset_mout_g2d0_list, | 819 | .sources = exynos4_clkset_mout_g2d0_list, |
824 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list), | 820 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list), |
825 | }; | 821 | }; |
826 | 822 | ||
827 | static struct clksrc_clk exynos4_clk_mout_g2d0 = { | ||
828 | .clk = { | ||
829 | .name = "mout_g2d0", | ||
830 | }, | ||
831 | .sources = &exynos4_clkset_mout_g2d0, | ||
832 | .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 }, | ||
833 | }; | ||
834 | |||
835 | static struct clk *exynos4_clkset_mout_g2d1_list[] = { | 823 | static struct clk *exynos4_clkset_mout_g2d1_list[] = { |
836 | [0] = &exynos4_clk_mout_epll.clk, | 824 | [0] = &exynos4_clk_mout_epll.clk, |
837 | [1] = &exynos4_clk_sclk_vpll.clk, | 825 | [1] = &exynos4_clk_sclk_vpll.clk, |
838 | }; | 826 | }; |
839 | 827 | ||
840 | static struct clksrc_sources exynos4_clkset_mout_g2d1 = { | 828 | struct clksrc_sources exynos4_clkset_mout_g2d1 = { |
841 | .sources = exynos4_clkset_mout_g2d1_list, | 829 | .sources = exynos4_clkset_mout_g2d1_list, |
842 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list), | 830 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list), |
843 | }; | 831 | }; |
844 | 832 | ||
845 | static struct clksrc_clk exynos4_clk_mout_g2d1 = { | ||
846 | .clk = { | ||
847 | .name = "mout_g2d1", | ||
848 | }, | ||
849 | .sources = &exynos4_clkset_mout_g2d1, | ||
850 | .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 }, | ||
851 | }; | ||
852 | |||
853 | static struct clk *exynos4_clkset_mout_g2d_list[] = { | ||
854 | [0] = &exynos4_clk_mout_g2d0.clk, | ||
855 | [1] = &exynos4_clk_mout_g2d1.clk, | ||
856 | }; | ||
857 | |||
858 | static struct clksrc_sources exynos4_clkset_mout_g2d = { | ||
859 | .sources = exynos4_clkset_mout_g2d_list, | ||
860 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d_list), | ||
861 | }; | ||
862 | |||
863 | static struct clk *exynos4_clkset_mout_mfc0_list[] = { | 833 | static struct clk *exynos4_clkset_mout_mfc0_list[] = { |
864 | [0] = &exynos4_clk_mout_mpll.clk, | 834 | [0] = &exynos4_clk_mout_mpll.clk, |
865 | [1] = &exynos4_clk_sclk_apll.clk, | 835 | [1] = &exynos4_clk_sclk_apll.clk, |
@@ -1126,13 +1096,6 @@ static struct clksrc_clk exynos4_clksrcs[] = { | |||
1126 | .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 }, | 1096 | .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 }, |
1127 | }, { | 1097 | }, { |
1128 | .clk = { | 1098 | .clk = { |
1129 | .name = "sclk_fimg2d", | ||
1130 | }, | ||
1131 | .sources = &exynos4_clkset_mout_g2d, | ||
1132 | .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 }, | ||
1133 | .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 }, | ||
1134 | }, { | ||
1135 | .clk = { | ||
1136 | .name = "sclk_mfc", | 1099 | .name = "sclk_mfc", |
1137 | .devname = "s5p-mfc", | 1100 | .devname = "s5p-mfc", |
1138 | }, | 1101 | }, |
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h index 28a119701182..bd12d5f8b63d 100644 --- a/arch/arm/mach-exynos/clock-exynos4.h +++ b/arch/arm/mach-exynos/clock-exynos4.h | |||
@@ -23,6 +23,9 @@ extern struct clksrc_sources exynos4_clkset_group; | |||
23 | extern struct clk *exynos4_clkset_aclk_top_list[]; | 23 | extern struct clk *exynos4_clkset_aclk_top_list[]; |
24 | extern struct clk *exynos4_clkset_group_list[]; | 24 | extern struct clk *exynos4_clkset_group_list[]; |
25 | 25 | ||
26 | extern struct clksrc_sources exynos4_clkset_mout_g2d0; | ||
27 | extern struct clksrc_sources exynos4_clkset_mout_g2d1; | ||
28 | |||
26 | extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable); | 29 | extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable); |
27 | extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable); | 30 | extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable); |
28 | extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable); | 31 | extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable); |
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c index b8689ff60baf..fed4c26e9dad 100644 --- a/arch/arm/mach-exynos/clock-exynos4210.c +++ b/arch/arm/mach-exynos/clock-exynos4210.c | |||
@@ -48,6 +48,32 @@ static struct clksrc_clk *sysclks[] = { | |||
48 | /* nothing here yet */ | 48 | /* nothing here yet */ |
49 | }; | 49 | }; |
50 | 50 | ||
51 | static struct clksrc_clk exynos4210_clk_mout_g2d0 = { | ||
52 | .clk = { | ||
53 | .name = "mout_g2d0", | ||
54 | }, | ||
55 | .sources = &exynos4_clkset_mout_g2d0, | ||
56 | .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 }, | ||
57 | }; | ||
58 | |||
59 | static struct clksrc_clk exynos4210_clk_mout_g2d1 = { | ||
60 | .clk = { | ||
61 | .name = "mout_g2d1", | ||
62 | }, | ||
63 | .sources = &exynos4_clkset_mout_g2d1, | ||
64 | .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 }, | ||
65 | }; | ||
66 | |||
67 | static struct clk *exynos4210_clkset_mout_g2d_list[] = { | ||
68 | [0] = &exynos4210_clk_mout_g2d0.clk, | ||
69 | [1] = &exynos4210_clk_mout_g2d1.clk, | ||
70 | }; | ||
71 | |||
72 | static struct clksrc_sources exynos4210_clkset_mout_g2d = { | ||
73 | .sources = exynos4210_clkset_mout_g2d_list, | ||
74 | .nr_sources = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list), | ||
75 | }; | ||
76 | |||
51 | static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) | 77 | static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) |
52 | { | 78 | { |
53 | return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable); | 79 | return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable); |
@@ -74,6 +100,13 @@ static struct clksrc_clk clksrcs[] = { | |||
74 | .sources = &exynos4_clkset_group, | 100 | .sources = &exynos4_clkset_group, |
75 | .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 }, | 101 | .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 }, |
76 | .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 }, | 102 | .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 }, |
103 | }, { | ||
104 | .clk = { | ||
105 | .name = "sclk_fimg2d", | ||
106 | }, | ||
107 | .sources = &exynos4210_clkset_mout_g2d, | ||
108 | .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 }, | ||
109 | .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 }, | ||
77 | }, | 110 | }, |
78 | }; | 111 | }; |
79 | 112 | ||
@@ -105,6 +138,10 @@ static struct clk init_clocks_off[] = { | |||
105 | .devname = SYSMMU_CLOCK_DEVNAME(fimd1, 11), | 138 | .devname = SYSMMU_CLOCK_DEVNAME(fimd1, 11), |
106 | .enable = exynos4_clk_ip_lcd1_ctrl, | 139 | .enable = exynos4_clk_ip_lcd1_ctrl, |
107 | .ctrlbit = (1 << 4), | 140 | .ctrlbit = (1 << 4), |
141 | }, { | ||
142 | .name = "fimg2d", | ||
143 | .enable = exynos4_clk_ip_image_ctrl, | ||
144 | .ctrlbit = (1 << 0), | ||
108 | }, | 145 | }, |
109 | }; | 146 | }; |
110 | 147 | ||