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-rw-r--r--arch/powerpc/kernel/power4-pmu.c2
-rw-r--r--arch/powerpc/kernel/power5+-pmu.c2
-rw-r--r--arch/powerpc/kernel/power5-pmu.c2
-rw-r--r--arch/powerpc/kernel/power6-pmu.c2
-rw-r--r--arch/powerpc/kernel/power7-pmu.c2
-rw-r--r--arch/powerpc/kernel/ppc970-pmu.c2
-rw-r--r--arch/x86/kernel/cpu/perf_counter.c12
-rw-r--r--include/linux/perf_counter.h4
8 files changed, 14 insertions, 14 deletions
diff --git a/arch/powerpc/kernel/power4-pmu.c b/arch/powerpc/kernel/power4-pmu.c
index 73956f084b29..07bd308a5fa7 100644
--- a/arch/powerpc/kernel/power4-pmu.c
+++ b/arch/powerpc/kernel/power4-pmu.c
@@ -561,7 +561,7 @@ static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
561 [C(OP_WRITE)] = { -1, -1 }, 561 [C(OP_WRITE)] = { -1, -1 },
562 [C(OP_PREFETCH)] = { 0, 0 }, 562 [C(OP_PREFETCH)] = { 0, 0 },
563 }, 563 },
564 [C(L2)] = { /* RESULT_ACCESS RESULT_MISS */ 564 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
565 [C(OP_READ)] = { 0, 0 }, 565 [C(OP_READ)] = { 0, 0 },
566 [C(OP_WRITE)] = { 0, 0 }, 566 [C(OP_WRITE)] = { 0, 0 },
567 [C(OP_PREFETCH)] = { 0xc34, 0 }, 567 [C(OP_PREFETCH)] = { 0xc34, 0 },
diff --git a/arch/powerpc/kernel/power5+-pmu.c b/arch/powerpc/kernel/power5+-pmu.c
index 5f8b7741e970..41e5d2d958d4 100644
--- a/arch/powerpc/kernel/power5+-pmu.c
+++ b/arch/powerpc/kernel/power5+-pmu.c
@@ -632,7 +632,7 @@ static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
632 [C(OP_WRITE)] = { -1, -1 }, 632 [C(OP_WRITE)] = { -1, -1 },
633 [C(OP_PREFETCH)] = { 0, 0 }, 633 [C(OP_PREFETCH)] = { 0, 0 },
634 }, 634 },
635 [C(L2)] = { /* RESULT_ACCESS RESULT_MISS */ 635 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
636 [C(OP_READ)] = { 0, 0 }, 636 [C(OP_READ)] = { 0, 0 },
637 [C(OP_WRITE)] = { 0, 0 }, 637 [C(OP_WRITE)] = { 0, 0 },
638 [C(OP_PREFETCH)] = { 0xc50c3, 0 }, 638 [C(OP_PREFETCH)] = { 0xc50c3, 0 },
diff --git a/arch/powerpc/kernel/power5-pmu.c b/arch/powerpc/kernel/power5-pmu.c
index d54723ab627d..05600b66221a 100644
--- a/arch/powerpc/kernel/power5-pmu.c
+++ b/arch/powerpc/kernel/power5-pmu.c
@@ -574,7 +574,7 @@ static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
574 [C(OP_WRITE)] = { -1, -1 }, 574 [C(OP_WRITE)] = { -1, -1 },
575 [C(OP_PREFETCH)] = { 0, 0 }, 575 [C(OP_PREFETCH)] = { 0, 0 },
576 }, 576 },
577 [C(L2)] = { /* RESULT_ACCESS RESULT_MISS */ 577 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
578 [C(OP_READ)] = { 0, 0x3c309b }, 578 [C(OP_READ)] = { 0, 0x3c309b },
579 [C(OP_WRITE)] = { 0, 0 }, 579 [C(OP_WRITE)] = { 0, 0 },
580 [C(OP_PREFETCH)] = { 0xc50c3, 0 }, 580 [C(OP_PREFETCH)] = { 0xc50c3, 0 },
diff --git a/arch/powerpc/kernel/power6-pmu.c b/arch/powerpc/kernel/power6-pmu.c
index 0cd406ee765b..46f74bebcfd9 100644
--- a/arch/powerpc/kernel/power6-pmu.c
+++ b/arch/powerpc/kernel/power6-pmu.c
@@ -493,7 +493,7 @@ static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
493 [C(OP_WRITE)] = { -1, -1 }, 493 [C(OP_WRITE)] = { -1, -1 },
494 [C(OP_PREFETCH)] = { 0x4008c, 0 }, 494 [C(OP_PREFETCH)] = { 0x4008c, 0 },
495 }, 495 },
496 [C(L2)] = { /* RESULT_ACCESS RESULT_MISS */ 496 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
497 [C(OP_READ)] = { 0x150730, 0x250532 }, 497 [C(OP_READ)] = { 0x150730, 0x250532 },
498 [C(OP_WRITE)] = { 0x250432, 0x150432 }, 498 [C(OP_WRITE)] = { 0x250432, 0x150432 },
499 [C(OP_PREFETCH)] = { 0x810a6, 0 }, 499 [C(OP_PREFETCH)] = { 0x810a6, 0 },
diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/kernel/power7-pmu.c
index 060e0deb399e..b3f7d1216bae 100644
--- a/arch/powerpc/kernel/power7-pmu.c
+++ b/arch/powerpc/kernel/power7-pmu.c
@@ -320,7 +320,7 @@ static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
320 [C(OP_WRITE)] = { -1, -1 }, 320 [C(OP_WRITE)] = { -1, -1 },
321 [C(OP_PREFETCH)] = { 0x408a, 0 }, 321 [C(OP_PREFETCH)] = { 0x408a, 0 },
322 }, 322 },
323 [C(L2)] = { /* RESULT_ACCESS RESULT_MISS */ 323 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
324 [C(OP_READ)] = { 0x6080, 0x6084 }, 324 [C(OP_READ)] = { 0x6080, 0x6084 },
325 [C(OP_WRITE)] = { 0x6082, 0x6086 }, 325 [C(OP_WRITE)] = { 0x6082, 0x6086 },
326 [C(OP_PREFETCH)] = { 0, 0 }, 326 [C(OP_PREFETCH)] = { 0, 0 },
diff --git a/arch/powerpc/kernel/ppc970-pmu.c b/arch/powerpc/kernel/ppc970-pmu.c
index 46a206409420..ba0a357a89f4 100644
--- a/arch/powerpc/kernel/ppc970-pmu.c
+++ b/arch/powerpc/kernel/ppc970-pmu.c
@@ -445,7 +445,7 @@ static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
445 [C(OP_WRITE)] = { -1, -1 }, 445 [C(OP_WRITE)] = { -1, -1 },
446 [C(OP_PREFETCH)] = { 0, 0 }, 446 [C(OP_PREFETCH)] = { 0, 0 },
447 }, 447 },
448 [C(L2)] = { /* RESULT_ACCESS RESULT_MISS */ 448 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
449 [C(OP_READ)] = { 0, 0 }, 449 [C(OP_READ)] = { 0, 0 },
450 [C(OP_WRITE)] = { 0, 0 }, 450 [C(OP_WRITE)] = { 0, 0 },
451 [C(OP_PREFETCH)] = { 0x733, 0 }, 451 [C(OP_PREFETCH)] = { 0x733, 0 },
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 572fb434a666..895c82e78455 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -131,7 +131,7 @@ static const u64 nehalem_hw_cache_event_ids
131 [ C(RESULT_MISS) ] = 0x0, 131 [ C(RESULT_MISS) ] = 0x0,
132 }, 132 },
133 }, 133 },
134 [ C(L2 ) ] = { 134 [ C(LL ) ] = {
135 [ C(OP_READ) ] = { 135 [ C(OP_READ) ] = {
136 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */ 136 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
137 [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */ 137 [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
@@ -141,8 +141,8 @@ static const u64 nehalem_hw_cache_event_ids
141 [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */ 141 [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
142 }, 142 },
143 [ C(OP_PREFETCH) ] = { 143 [ C(OP_PREFETCH) ] = {
144 [ C(RESULT_ACCESS) ] = 0xc024, /* L2_RQSTS.PREFETCHES */ 144 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
145 [ C(RESULT_MISS) ] = 0x8024, /* L2_RQSTS.PREFETCH_MISS */ 145 [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
146 }, 146 },
147 }, 147 },
148 [ C(DTLB) ] = { 148 [ C(DTLB) ] = {
@@ -222,7 +222,7 @@ static const u64 core2_hw_cache_event_ids
222 [ C(RESULT_MISS) ] = 0, 222 [ C(RESULT_MISS) ] = 0,
223 }, 223 },
224 }, 224 },
225 [ C(L2 ) ] = { 225 [ C(LL ) ] = {
226 [ C(OP_READ) ] = { 226 [ C(OP_READ) ] = {
227 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 227 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
228 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 228 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
@@ -313,7 +313,7 @@ static const u64 atom_hw_cache_event_ids
313 [ C(RESULT_MISS) ] = 0, 313 [ C(RESULT_MISS) ] = 0,
314 }, 314 },
315 }, 315 },
316 [ C(L2 ) ] = { 316 [ C(LL ) ] = {
317 [ C(OP_READ) ] = { 317 [ C(OP_READ) ] = {
318 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 318 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
319 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 319 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
@@ -422,7 +422,7 @@ static const u64 amd_0f_hw_cache_event_ids
422 [ C(RESULT_MISS) ] = 0, 422 [ C(RESULT_MISS) ] = 0,
423 }, 423 },
424 }, 424 },
425 [ C(L2 ) ] = { 425 [ C(LL ) ] = {
426 [ C(OP_READ) ] = { 426 [ C(OP_READ) ] = {
427 [ C(RESULT_ACCESS) ] = 0, 427 [ C(RESULT_ACCESS) ] = 0,
428 [ C(RESULT_MISS) ] = 0, 428 [ C(RESULT_MISS) ] = 0,
diff --git a/include/linux/perf_counter.h b/include/linux/perf_counter.h
index 887df88a9c2a..20cf5af27ade 100644
--- a/include/linux/perf_counter.h
+++ b/include/linux/perf_counter.h
@@ -56,14 +56,14 @@ enum perf_hw_id {
56/* 56/*
57 * Generalized hardware cache counters: 57 * Generalized hardware cache counters:
58 * 58 *
59 * { L1-D, L1-I, L2, LLC, ITLB, DTLB, BPU } x 59 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU } x
60 * { read, write, prefetch } x 60 * { read, write, prefetch } x
61 * { accesses, misses } 61 * { accesses, misses }
62 */ 62 */
63enum perf_hw_cache_id { 63enum perf_hw_cache_id {
64 PERF_COUNT_HW_CACHE_L1D = 0, 64 PERF_COUNT_HW_CACHE_L1D = 0,
65 PERF_COUNT_HW_CACHE_L1I = 1, 65 PERF_COUNT_HW_CACHE_L1I = 1,
66 PERF_COUNT_HW_CACHE_L2 = 2, 66 PERF_COUNT_HW_CACHE_LL = 2,
67 PERF_COUNT_HW_CACHE_DTLB = 3, 67 PERF_COUNT_HW_CACHE_DTLB = 3,
68 PERF_COUNT_HW_CACHE_ITLB = 4, 68 PERF_COUNT_HW_CACHE_ITLB = 4,
69 PERF_COUNT_HW_CACHE_BPU = 5, 69 PERF_COUNT_HW_CACHE_BPU = 5,