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-rw-r--r--arch/arm/mach-tegra/dma.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
index 998c55ddca42..abea4f6e2dd5 100644
--- a/arch/arm/mach-tegra/dma.c
+++ b/arch/arm/mach-tegra/dma.c
@@ -52,8 +52,6 @@
52#define CSR_ONCE (1<<27) 52#define CSR_ONCE (1<<27)
53#define CSR_FLOW (1<<21) 53#define CSR_FLOW (1<<21)
54#define CSR_REQ_SEL_SHIFT 16 54#define CSR_REQ_SEL_SHIFT 16
55#define CSR_REQ_SEL_MASK (0x1F<<CSR_REQ_SEL_SHIFT)
56#define CSR_REQ_SEL_INVALID (31<<CSR_REQ_SEL_SHIFT)
57#define CSR_WCOUNT_SHIFT 2 55#define CSR_WCOUNT_SHIFT 2
58#define CSR_WCOUNT_MASK 0xFFFC 56#define CSR_WCOUNT_MASK 0xFFFC
59 57
@@ -183,18 +181,12 @@ static void tegra_dma_stop(struct tegra_dma_channel *ch)
183 181
184static int tegra_dma_cancel(struct tegra_dma_channel *ch) 182static int tegra_dma_cancel(struct tegra_dma_channel *ch)
185{ 183{
186 u32 csr;
187 unsigned long irq_flags; 184 unsigned long irq_flags;
188 185
189 spin_lock_irqsave(&ch->lock, irq_flags); 186 spin_lock_irqsave(&ch->lock, irq_flags);
190 while (!list_empty(&ch->list)) 187 while (!list_empty(&ch->list))
191 list_del(ch->list.next); 188 list_del(ch->list.next);
192 189
193 csr = readl(ch->addr + APB_DMA_CHAN_CSR);
194 csr &= ~CSR_REQ_SEL_MASK;
195 csr |= CSR_REQ_SEL_INVALID;
196 writel(csr, ch->addr + APB_DMA_CHAN_CSR);
197
198 tegra_dma_stop(ch); 190 tegra_dma_stop(ch);
199 191
200 spin_unlock_irqrestore(&ch->lock, irq_flags); 192 spin_unlock_irqrestore(&ch->lock, irq_flags);