4 files changed, 23 insertions, 8 deletions

diff --git a/arch/powerpc/include/asm/exception-64e.h b/arch/powerpc/include/asm/exception-64e.h
index e73452f09019..51fa43e536b9 100644
--- a/arch/powerpc/include/asm/exception-64e.h
+++ b/arch/powerpc/include/asm/exception-64e.h
@@ -46,8 +46,9 @@
 #define EX_CR           (1 * 8)
 #define EX_R10          (2 * 8)
 #define EX_R11          (3 * 8)
-#define EX_R14          (4 * 8)
-#define EX_R15          (5 * 8)
+#define EX_R13          (4 * 8)
+#define EX_R14          (5 * 8)
+#define EX_R15          (6 * 8)
 
 /*
  * The TLB miss exception uses different slots.
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index c195bf0e6241..a391244c18e1 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -761,7 +761,8 @@
  * 64-bit embedded
  *      - SPRG0 generic exception scratch
  *      - SPRG2 TLB exception stack
- *      - SPRG3 CPU and NUMA node for VDSO getcpu (user visible)
+ *      - SPRG3 critical exception scratch and
+ *        CPU and NUMA node for VDSO getcpu (user visible)
  *      - SPRG4 unused (user visible)
  *      - SPRG6 TLB miss scratch (user visible, sorry !)
  *      - SPRG7 critical exception scratch
@@ -858,7 +859,7 @@
 
 #ifdef CONFIG_PPC_BOOK3E_64
 #define SPRN_SPRG_MC_SCRATCH    SPRN_SPRG8
-#define SPRN_SPRG_CRIT_SCRATCH  SPRN_SPRG7
+#define SPRN_SPRG_CRIT_SCRATCH  SPRN_SPRG3
 #define SPRN_SPRG_DBG_SCRATCH   SPRN_SPRG9
 #define SPRN_SPRG_TLB_EXFRAME   SPRN_SPRG2
 #define SPRN_SPRG_TLB_SCRATCH   SPRN_SPRG6
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 83c20e84a4fb..7476b0ae09fb 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -42,6 +42,7 @@
         mfspr   r13,SPRN_SPRG_PACA;     /* get PACA */                      \
         std     r10,PACA_EX##type+EX_R10(r13);                              \
         std     r11,PACA_EX##type+EX_R11(r13);                              \
+        PROLOG_STORE_RESTORE_SCRATCH_##type;                                \
         mfcr    r10;                    /* save CR */                       \
         mfspr   r11,SPRN_##type##_SRR1;/* what are we coming from */        \
         DO_KVM  intnum,SPRN_##type##_SRR1;    /* KVM hook */                \
@@ -99,6 +100,18 @@
 #define GDBELL_EXCEPTION_PROLOG(n, intnum, addition)                        \
         EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n))
 
+/*
+ * Store user-visible scratch in PACA exception slots and restore proper value
+ */
+#define PROLOG_STORE_RESTORE_SCRATCH_GEN
+#define PROLOG_STORE_RESTORE_SCRATCH_GDBELL
+#define PROLOG_STORE_RESTORE_SCRATCH_DBG
+#define PROLOG_STORE_RESTORE_SCRATCH_MC
+
+#define PROLOG_STORE_RESTORE_SCRATCH_CRIT                                   \
+        mfspr   r10,SPRN_SPRG_CRIT_SCRATCH;     /* get r13 */               \
+        std     r10,PACA_EXCRIT+EX_R13(r13)
+
 /* Variants of the "addition" argument for the prolog
  */
 #define PROLOG_ADDITION_NONE_GEN(n)
@@ -454,7 +467,7 @@ interrupt_end_book3e:
         mtcr    r10
         ld      r10,PACA_EXCRIT+EX_R10(r13)     /* restore registers */
         ld      r11,PACA_EXCRIT+EX_R11(r13)
-        mfspr   r13,SPRN_SPRG_CRIT_SCRATCH
+        ld      r13,PACA_EXCRIT+EX_R13(r13)
         rfci
 
         /* Normal debug exception */
@@ -467,7 +480,7 @@ interrupt_end_book3e:
         /* Now we mash up things to make it look like we are coming on a
          * normal exception
          */
-        mfspr   r15,SPRN_SPRG_CRIT_SCRATCH
+        ld      r15,PACA_EXCRIT+EX_R13(r13)
         mtspr   SPRN_SPRG_GEN_SCRATCH,r15
         mfspr   r14,SPRN_DBSR
         EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE)
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index d884fa44d34f..b4113bf86353 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -40,7 +40,7 @@
  **********************************************************************/
 
 .macro tlb_prolog_bolted intnum addr
-        mtspr   SPRN_SPRG_TLB_SCRATCH,r13
+        mtspr   SPRN_SPRG_GEN_SCRATCH,r13
         mfspr   r13,SPRN_SPRG_PACA
         std     r10,PACA_EXTLB+EX_TLB_R10(r13)
         mfcr    r10
@@ -69,7 +69,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
         ld      r15,PACA_EXTLB+EX_TLB_R15(r13)
         TLB_MISS_RESTORE_STATS_BOLTED
         ld      r16,PACA_EXTLB+EX_TLB_R16(r13)
-        mfspr   r13,SPRN_SPRG_TLB_SCRATCH
+        mfspr   r13,SPRN_SPRG_GEN_SCRATCH
 .endm
 
 /* Data TLB miss */