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-rw-r--r--arch/arm/mach-msm/board-qsd8x50.c81
-rw-r--r--arch/arm/mach-msm/devices-qsd8x50.c196
-rw-r--r--arch/arm/mach-msm/gpiomux-8x50.c23
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x50.h8
4 files changed, 303 insertions, 5 deletions
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 2e8391307f55..12863f791434 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -1,4 +1,4 @@
1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. 1/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 * 2 *
3 * This program is free software; you can redistribute it and/or modify 3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and 4 * it under the terms of the GNU General Public License version 2 and
@@ -21,6 +21,7 @@
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/delay.h> 22#include <linux/delay.h>
23#include <linux/usb/msm_hsusb.h> 23#include <linux/usb/msm_hsusb.h>
24#include <linux/err.h>
24 25
25#include <asm/mach-types.h> 26#include <asm/mach-types.h>
26#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
@@ -31,6 +32,8 @@
31#include <mach/irqs.h> 32#include <mach/irqs.h>
32#include <mach/sirc.h> 33#include <mach/sirc.h>
33#include <mach/gpio.h> 34#include <mach/gpio.h>
35#include <mach/vreg.h>
36#include <mach/mmc.h>
34 37
35#include "devices.h" 38#include "devices.h"
36 39
@@ -95,6 +98,81 @@ static struct platform_device *devices[] __initdata = {
95 &msm_device_hsusb_host, 98 &msm_device_hsusb_host,
96}; 99};
97 100
101static struct msm_mmc_gpio sdc1_gpio_cfg[] = {
102 {51, "sdc1_dat_3"},
103 {52, "sdc1_dat_2"},
104 {53, "sdc1_dat_1"},
105 {54, "sdc1_dat_0"},
106 {55, "sdc1_cmd"},
107 {56, "sdc1_clk"}
108};
109
110static struct vreg *vreg_mmc;
111static unsigned long vreg_sts;
112
113static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
114{
115 int rc = 0;
116 struct platform_device *pdev;
117
118 pdev = container_of(dv, struct platform_device, dev);
119
120 if (vdd == 0) {
121 if (!vreg_sts)
122 return 0;
123
124 clear_bit(pdev->id, &vreg_sts);
125
126 if (!vreg_sts) {
127 rc = vreg_disable(vreg_mmc);
128 if (rc)
129 pr_err("vreg_mmc disable failed for slot "
130 "%d: %d\n", pdev->id, rc);
131 }
132 return 0;
133 }
134
135 if (!vreg_sts) {
136 rc = vreg_set_level(vreg_mmc, 2900);
137 if (rc)
138 pr_err("vreg_mmc set level failed for slot %d: %d\n",
139 pdev->id, rc);
140 rc = vreg_enable(vreg_mmc);
141 if (rc)
142 pr_err("vreg_mmc enable failed for slot %d: %d\n",
143 pdev->id, rc);
144 }
145 set_bit(pdev->id, &vreg_sts);
146 return 0;
147}
148
149static struct msm_mmc_gpio_data sdc1_gpio = {
150 .gpio = sdc1_gpio_cfg,
151 .size = ARRAY_SIZE(sdc1_gpio_cfg),
152};
153
154static struct msm_mmc_platform_data qsd8x50_sdc1_data = {
155 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
156 .translate_vdd = msm_sdcc_setup_power,
157 .gpio_data = &sdc1_gpio,
158};
159
160static void __init qsd8x50_init_mmc(void)
161{
162 if (machine_is_qsd8x50_ffa() || machine_is_qsd8x50a_ffa())
163 vreg_mmc = vreg_get(NULL, "gp6");
164 else
165 vreg_mmc = vreg_get(NULL, "gp5");
166
167 if (IS_ERR(vreg_mmc)) {
168 pr_err("vreg get for vreg_mmc failed (%ld)\n",
169 PTR_ERR(vreg_mmc));
170 return;
171 }
172
173 msm_add_sdcc(1, &qsd8x50_sdc1_data, 0, 0);
174}
175
98static void __init qsd8x50_map_io(void) 176static void __init qsd8x50_map_io(void)
99{ 177{
100 msm_map_qsd8x50_io(); 178 msm_map_qsd8x50_io();
@@ -113,6 +191,7 @@ static void __init qsd8x50_init(void)
113 msm_device_hsusb.dev.parent = &msm_device_otg.dev; 191 msm_device_hsusb.dev.parent = &msm_device_otg.dev;
114 msm_device_hsusb_host.dev.parent = &msm_device_otg.dev; 192 msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
115 platform_add_devices(devices, ARRAY_SIZE(devices)); 193 platform_add_devices(devices, ARRAY_SIZE(devices));
194 qsd8x50_init_mmc();
116} 195}
117 196
118MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") 197MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index a4b798f20ccb..b1a8f0f680a7 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -124,6 +124,194 @@ struct platform_device msm_device_hsusb_host = {
124 }, 124 },
125}; 125};
126 126
127static struct resource resources_sdc1[] = {
128 {
129 .start = MSM_SDC1_PHYS,
130 .end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
131 .flags = IORESOURCE_MEM,
132 },
133 {
134 .start = INT_SDC1_0,
135 .end = INT_SDC1_0,
136 .flags = IORESOURCE_IRQ,
137 .name = "cmd_irq",
138 },
139 {
140 .start = INT_SDC1_1,
141 .end = INT_SDC1_1,
142 .flags = IORESOURCE_IRQ,
143 .name = "pio_irq",
144 },
145 {
146 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
147 .name = "status_irq"
148 },
149 {
150 .start = 8,
151 .end = 8,
152 .flags = IORESOURCE_DMA,
153 },
154};
155
156static struct resource resources_sdc2[] = {
157 {
158 .start = MSM_SDC2_PHYS,
159 .end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
160 .flags = IORESOURCE_MEM,
161 },
162 {
163 .start = INT_SDC2_0,
164 .end = INT_SDC2_0,
165 .flags = IORESOURCE_IRQ,
166 .name = "cmd_irq",
167 },
168 {
169 .start = INT_SDC2_1,
170 .end = INT_SDC2_1,
171 .flags = IORESOURCE_IRQ,
172 .name = "pio_irq",
173 },
174 {
175 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
176 .name = "status_irq"
177 },
178 {
179 .start = 8,
180 .end = 8,
181 .flags = IORESOURCE_DMA,
182 },
183};
184
185static struct resource resources_sdc3[] = {
186 {
187 .start = MSM_SDC3_PHYS,
188 .end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
189 .flags = IORESOURCE_MEM,
190 },
191 {
192 .start = INT_SDC3_0,
193 .end = INT_SDC3_0,
194 .flags = IORESOURCE_IRQ,
195 .name = "cmd_irq",
196 },
197 {
198 .start = INT_SDC3_1,
199 .end = INT_SDC3_1,
200 .flags = IORESOURCE_IRQ,
201 .name = "pio_irq",
202 },
203 {
204 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
205 .name = "status_irq"
206 },
207 {
208 .start = 8,
209 .end = 8,
210 .flags = IORESOURCE_DMA,
211 },
212};
213
214static struct resource resources_sdc4[] = {
215 {
216 .start = MSM_SDC4_PHYS,
217 .end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
218 .flags = IORESOURCE_MEM,
219 },
220 {
221 .start = INT_SDC4_0,
222 .end = INT_SDC4_0,
223 .flags = IORESOURCE_IRQ,
224 .name = "cmd_irq",
225 },
226 {
227 .start = INT_SDC4_1,
228 .end = INT_SDC4_1,
229 .flags = IORESOURCE_IRQ,
230 .name = "pio_irq",
231 },
232 {
233 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
234 .name = "status_irq"
235 },
236 {
237 .start = 8,
238 .end = 8,
239 .flags = IORESOURCE_DMA,
240 },
241};
242
243struct platform_device msm_device_sdc1 = {
244 .name = "msm_sdcc",
245 .id = 1,
246 .num_resources = ARRAY_SIZE(resources_sdc1),
247 .resource = resources_sdc1,
248 .dev = {
249 .coherent_dma_mask = 0xffffffff,
250 },
251};
252
253struct platform_device msm_device_sdc2 = {
254 .name = "msm_sdcc",
255 .id = 2,
256 .num_resources = ARRAY_SIZE(resources_sdc2),
257 .resource = resources_sdc2,
258 .dev = {
259 .coherent_dma_mask = 0xffffffff,
260 },
261};
262
263struct platform_device msm_device_sdc3 = {
264 .name = "msm_sdcc",
265 .id = 3,
266 .num_resources = ARRAY_SIZE(resources_sdc3),
267 .resource = resources_sdc3,
268 .dev = {
269 .coherent_dma_mask = 0xffffffff,
270 },
271};
272
273struct platform_device msm_device_sdc4 = {
274 .name = "msm_sdcc",
275 .id = 4,
276 .num_resources = ARRAY_SIZE(resources_sdc4),
277 .resource = resources_sdc4,
278 .dev = {
279 .coherent_dma_mask = 0xffffffff,
280 },
281};
282
283static struct platform_device *msm_sdcc_devices[] __initdata = {
284 &msm_device_sdc1,
285 &msm_device_sdc2,
286 &msm_device_sdc3,
287 &msm_device_sdc4,
288};
289
290int __init msm_add_sdcc(unsigned int controller,
291 struct msm_mmc_platform_data *plat,
292 unsigned int stat_irq, unsigned long stat_irq_flags)
293{
294 struct platform_device *pdev;
295 struct resource *res;
296
297 if (controller < 1 || controller > 4)
298 return -EINVAL;
299
300 pdev = msm_sdcc_devices[controller-1];
301 pdev->dev.platform_data = plat;
302
303 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
304 if (!res)
305 return -EINVAL;
306 else if (stat_irq) {
307 res->start = res->end = stat_irq;
308 res->flags &= ~IORESOURCE_DISABLED;
309 res->flags |= stat_irq_flags;
310 }
311
312 return platform_device_register(pdev);
313}
314
127struct clk msm_clocks_8x50[] = { 315struct clk msm_clocks_8x50[] = {
128 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), 316 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
129 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), 317 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
@@ -144,6 +332,14 @@ struct clk msm_clocks_8x50[] = {
144 CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN), 332 CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN),
145 CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), 333 CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
146 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), 334 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
335 CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF),
336 CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF),
337 CLK_PCOM("sdc_clk", SDC2_CLK, &msm_device_sdc2.dev, OFF),
338 CLK_PCOM("sdc_pclk", SDC2_P_CLK, &msm_device_sdc2.dev, OFF),
339 CLK_PCOM("sdc_clk", SDC3_CLK, &msm_device_sdc3.dev, OFF),
340 CLK_PCOM("sdc_pclk", SDC3_P_CLK, &msm_device_sdc3.dev, OFF),
341 CLK_PCOM("sdc_clk", SDC4_CLK, &msm_device_sdc4.dev, OFF),
342 CLK_PCOM("sdc_pclk", SDC4_P_CLK, &msm_device_sdc4.dev, OFF),
147 CLK_PCOM("spi_clk", SPI_CLK, NULL, 0), 343 CLK_PCOM("spi_clk", SPI_CLK, NULL, 0),
148 CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), 344 CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0),
149 CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), 345 CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0),
diff --git a/arch/arm/mach-msm/gpiomux-8x50.c b/arch/arm/mach-msm/gpiomux-8x50.c
index 4406e0f4ae95..f7a4ea593c95 100644
--- a/arch/arm/mach-msm/gpiomux-8x50.c
+++ b/arch/arm/mach-msm/gpiomux-8x50.c
@@ -16,6 +16,19 @@
16 */ 16 */
17#include "gpiomux.h" 17#include "gpiomux.h"
18 18
19#if defined(CONFIG_MMC_MSM) || defined(CONFIG_MMC_MSM_MODULE)
20 #define SDCC_DAT_0_3_CMD_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_UP\
21 | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA)
22 #define SDCC_CLK_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_NONE\
23 | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA)
24#else
25 #define SDCC_DAT_0_3_CMD_ACTV_CFG 0
26 #define SDCC_CLK_ACTV_CFG 0
27#endif
28
29#define SDC1_SUSPEND_CONFIG (GPIOMUX_VALID | GPIOMUX_PULL_DOWN\
30 | GPIOMUX_FUNC_GPIO | GPIOMUX_DRV_2MA)
31
19struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { 32struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
20 [86] = { /* UART3 RX */ 33 [86] = { /* UART3 RX */
21 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | 34 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
@@ -25,4 +38,14 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
25 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | 38 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
26 GPIOMUX_FUNC_1 | GPIOMUX_VALID, 39 GPIOMUX_FUNC_1 | GPIOMUX_VALID,
27 }, 40 },
41 /* SDC1 data[3:0] & CMD */
42 [51 ... 55] = {
43 .active = SDCC_DAT_0_3_CMD_ACTV_CFG,
44 .suspended = SDC1_SUSPEND_CONFIG
45 },
46 /* SDC1 CLK */
47 [56] = {
48 .active = SDCC_CLK_ACTV_CFG,
49 .suspended = SDC1_SUSPEND_CONFIG
50 },
28}; 51};
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index acc819eb76e5..732a9657677c 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -132,16 +132,16 @@
132#define MSM_UART2DM_PHYS 0xA0900000 132#define MSM_UART2DM_PHYS 0xA0900000
133 133
134 134
135#define MSM_SDC1_PHYS 0xA0400000 135#define MSM_SDC1_PHYS 0xA0300000
136#define MSM_SDC1_SIZE SZ_4K 136#define MSM_SDC1_SIZE SZ_4K
137 137
138#define MSM_SDC2_PHYS 0xA0500000 138#define MSM_SDC2_PHYS 0xA0400000
139#define MSM_SDC2_SIZE SZ_4K 139#define MSM_SDC2_SIZE SZ_4K
140 140
141#define MSM_SDC3_PHYS 0xA0600000 141#define MSM_SDC3_PHYS 0xA0500000
142#define MSM_SDC3_SIZE SZ_4K 142#define MSM_SDC3_SIZE SZ_4K
143 143
144#define MSM_SDC4_PHYS 0xA0700000 144#define MSM_SDC4_PHYS 0xA0600000
145#define MSM_SDC4_SIZE SZ_4K 145#define MSM_SDC4_SIZE SZ_4K
146 146
147#endif 147#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 04:20:58 -0400