diff options
-rw-r--r-- | drivers/gpu/drm/radeon/si.c | 20 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/sid.h | 1 |
2 files changed, 20 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 113ed9f1f0d1..1d8c61518ff6 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c | |||
@@ -2003,7 +2003,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) | |||
2003 | WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); | 2003 | WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); |
2004 | } | 2004 | } |
2005 | } else if ((rdev->family == CHIP_VERDE) || | 2005 | } else if ((rdev->family == CHIP_VERDE) || |
2006 | (rdev->family == CHIP_OLAND)) { | 2006 | (rdev->family == CHIP_OLAND) || |
2007 | (rdev->family == CHIP_HAINAN)) { | ||
2007 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { | 2008 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { |
2008 | switch (reg_offset) { | 2009 | switch (reg_offset) { |
2009 | case 0: /* non-AA compressed depth or any compressed stencil */ | 2010 | case 0: /* non-AA compressed depth or any compressed stencil */ |
@@ -2466,6 +2467,23 @@ static void si_gpu_init(struct radeon_device *rdev) | |||
2466 | rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; | 2467 | rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; |
2467 | gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; | 2468 | gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; |
2468 | break; | 2469 | break; |
2470 | case CHIP_HAINAN: | ||
2471 | rdev->config.si.max_shader_engines = 1; | ||
2472 | rdev->config.si.max_tile_pipes = 4; | ||
2473 | rdev->config.si.max_cu_per_sh = 5; | ||
2474 | rdev->config.si.max_sh_per_se = 1; | ||
2475 | rdev->config.si.max_backends_per_se = 1; | ||
2476 | rdev->config.si.max_texture_channel_caches = 2; | ||
2477 | rdev->config.si.max_gprs = 256; | ||
2478 | rdev->config.si.max_gs_threads = 16; | ||
2479 | rdev->config.si.max_hw_contexts = 8; | ||
2480 | |||
2481 | rdev->config.si.sc_prim_fifo_size_frontend = 0x20; | ||
2482 | rdev->config.si.sc_prim_fifo_size_backend = 0x40; | ||
2483 | rdev->config.si.sc_hiz_tile_fifo_size = 0x30; | ||
2484 | rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; | ||
2485 | gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; | ||
2486 | break; | ||
2469 | } | 2487 | } |
2470 | 2488 | ||
2471 | /* Initialize HDP */ | 2489 | /* Initialize HDP */ |
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index 222877ba6cf5..8f2d7d4f9b28 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h | |||
@@ -28,6 +28,7 @@ | |||
28 | 28 | ||
29 | #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 | 29 | #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 |
30 | #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 | 30 | #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 |
31 | #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 | ||
31 | 32 | ||
32 | /* discrete uvd clocks */ | 33 | /* discrete uvd clocks */ |
33 | #define CG_UPLL_FUNC_CNTL 0x634 | 34 | #define CG_UPLL_FUNC_CNTL 0x634 |