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-rw-r--r--drivers/spi/spi_bfin5xx.c152
1 files changed, 80 insertions, 72 deletions
diff --git a/drivers/spi/spi_bfin5xx.c b/drivers/spi/spi_bfin5xx.c
index ce3c0ce2316e..7d2d9ec6cac3 100644
--- a/drivers/spi/spi_bfin5xx.c
+++ b/drivers/spi/spi_bfin5xx.c
@@ -126,7 +126,7 @@ struct chip_data {
126 126
127 u8 chip_select_num; 127 u8 chip_select_num;
128 u8 n_bytes; 128 u8 n_bytes;
129 u32 width; /* 0 or 1 */ 129 u8 width; /* 0 or 1 */
130 u8 enable_dma; 130 u8 enable_dma;
131 u8 bits_per_word; /* 8 or 16 */ 131 u8 bits_per_word; /* 8 or 16 */
132 u8 cs_change_per_word; 132 u8 cs_change_per_word;
@@ -136,7 +136,7 @@ struct chip_data {
136 void (*duplex) (struct driver_data *); 136 void (*duplex) (struct driver_data *);
137}; 137};
138 138
139void bfin_spi_enable(struct driver_data *drv_data) 139static void bfin_spi_enable(struct driver_data *drv_data)
140{ 140{
141 u16 cr; 141 u16 cr;
142 142
@@ -145,7 +145,7 @@ void bfin_spi_enable(struct driver_data *drv_data)
145 SSYNC(); 145 SSYNC();
146} 146}
147 147
148void bfin_spi_disable(struct driver_data *drv_data) 148static void bfin_spi_disable(struct driver_data *drv_data)
149{ 149{
150 u16 cr; 150 u16 cr;
151 151
@@ -163,9 +163,6 @@ static u16 hz_to_spi_baud(u32 speed_hz)
163 if ((sclk % (2 * speed_hz)) > 0) 163 if ((sclk % (2 * speed_hz)) > 0)
164 spi_baud++; 164 spi_baud++;
165 165
166 pr_debug("sclk = %ld, speed_hz = %d, spi_baud = %d\n", sclk, speed_hz,
167 spi_baud);
168
169 return spi_baud; 166 return spi_baud;
170} 167}
171 168
@@ -190,11 +187,12 @@ static void restore_state(struct driver_data *drv_data)
190 /* Clear status and disable clock */ 187 /* Clear status and disable clock */
191 write_STAT(BIT_STAT_CLR); 188 write_STAT(BIT_STAT_CLR);
192 bfin_spi_disable(drv_data); 189 bfin_spi_disable(drv_data);
193 pr_debug("restoring spi ctl state\n"); 190 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
194 191
195#if defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) 192#if defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
196 pr_debug("chip select number is %d\n", chip->chip_select_num); 193 dev_dbg(&drv_data->pdev->dev,
197 194 "chip select number is %d\n", chip->chip_select_num);
195
198 switch (chip->chip_select_num) { 196 switch (chip->chip_select_num) {
199 case 1: 197 case 1:
200 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3c00); 198 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3c00);
@@ -280,7 +278,8 @@ static void null_reader(struct driver_data *drv_data)
280 278
281static void u8_writer(struct driver_data *drv_data) 279static void u8_writer(struct driver_data *drv_data)
282{ 280{
283 pr_debug("cr8-s is 0x%x\n", read_STAT()); 281 dev_dbg(&drv_data->pdev->dev,
282 "cr8-s is 0x%x\n", read_STAT());
284 while (drv_data->tx < drv_data->tx_end) { 283 while (drv_data->tx < drv_data->tx_end) {
285 write_TDBR(*(u8 *) (drv_data->tx)); 284 write_TDBR(*(u8 *) (drv_data->tx));
286 while (read_STAT() & BIT_STAT_TXS) 285 while (read_STAT() & BIT_STAT_TXS)
@@ -318,7 +317,8 @@ static void u8_cs_chg_writer(struct driver_data *drv_data)
318 317
319static void u8_reader(struct driver_data *drv_data) 318static void u8_reader(struct driver_data *drv_data)
320{ 319{
321 pr_debug("cr-8 is 0x%x\n", read_STAT()); 320 dev_dbg(&drv_data->pdev->dev,
321 "cr-8 is 0x%x\n", read_STAT());
322 322
323 /* clear TDBR buffer before read(else it will be shifted out) */ 323 /* clear TDBR buffer before read(else it will be shifted out) */
324 write_TDBR(0xFFFF); 324 write_TDBR(0xFFFF);
@@ -404,7 +404,9 @@ static void u8_cs_chg_duplex(struct driver_data *drv_data)
404 404
405static void u16_writer(struct driver_data *drv_data) 405static void u16_writer(struct driver_data *drv_data)
406{ 406{
407 pr_debug("cr16 is 0x%x\n", read_STAT()); 407 dev_dbg(&drv_data->pdev->dev,
408 "cr16 is 0x%x\n", read_STAT());
409
408 while (drv_data->tx < drv_data->tx_end) { 410 while (drv_data->tx < drv_data->tx_end) {
409 write_TDBR(*(u16 *) (drv_data->tx)); 411 write_TDBR(*(u16 *) (drv_data->tx));
410 while ((read_STAT() & BIT_STAT_TXS)) 412 while ((read_STAT() & BIT_STAT_TXS))
@@ -442,7 +444,8 @@ static void u16_cs_chg_writer(struct driver_data *drv_data)
442 444
443static void u16_reader(struct driver_data *drv_data) 445static void u16_reader(struct driver_data *drv_data)
444{ 446{
445 pr_debug("cr-16 is 0x%x\n", read_STAT()); 447 dev_dbg(&drv_data->pdev->dev,
448 "cr-16 is 0x%x\n", read_STAT());
446 dummy_read(); 449 dummy_read();
447 450
448 while (drv_data->rx < (drv_data->rx_end - 2)) { 451 while (drv_data->rx < (drv_data->rx_end - 2)) {
@@ -571,12 +574,12 @@ static void giveback(struct driver_data *drv_data)
571 msg->complete(msg->context); 574 msg->complete(msg->context);
572} 575}
573 576
574static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs) 577static irqreturn_t dma_irq_handler(int irq, void *dev_id)
575{ 578{
576 struct driver_data *drv_data = (struct driver_data *)dev_id; 579 struct driver_data *drv_data = (struct driver_data *)dev_id;
577 struct spi_message *msg = drv_data->cur_msg; 580 struct spi_message *msg = drv_data->cur_msg;
578 581
579 pr_debug("in dma_irq_handler\n"); 582 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
580 clear_dma_irqstat(CH_SPI); 583 clear_dma_irqstat(CH_SPI);
581 584
582 /* 585 /*
@@ -604,7 +607,9 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
604 tasklet_schedule(&drv_data->pump_transfers); 607 tasklet_schedule(&drv_data->pump_transfers);
605 608
606 /* free the irq handler before next transfer */ 609 /* free the irq handler before next transfer */
607 pr_debug("disable dma channel irq%d\n", CH_SPI); 610 dev_dbg(&drv_data->pdev->dev,
611 "disable dma channel irq%d\n",
612 CH_SPI);
608 dma_disable_irq(CH_SPI); 613 dma_disable_irq(CH_SPI);
609 614
610 return IRQ_HANDLED; 615 return IRQ_HANDLED;
@@ -617,7 +622,8 @@ static void pump_transfers(unsigned long data)
617 struct spi_transfer *transfer = NULL; 622 struct spi_transfer *transfer = NULL;
618 struct spi_transfer *previous = NULL; 623 struct spi_transfer *previous = NULL;
619 struct chip_data *chip = NULL; 624 struct chip_data *chip = NULL;
620 u16 cr, width, dma_width, dma_config; 625 u8 width;
626 u16 cr, dma_width, dma_config;
621 u32 tranf_success = 1; 627 u32 tranf_success = 1;
622 628
623 /* Get current state information */ 629 /* Get current state information */
@@ -662,8 +668,8 @@ static void pump_transfers(unsigned long data)
662 if (transfer->tx_buf != NULL) { 668 if (transfer->tx_buf != NULL) {
663 drv_data->tx = (void *)transfer->tx_buf; 669 drv_data->tx = (void *)transfer->tx_buf;
664 drv_data->tx_end = drv_data->tx + transfer->len; 670 drv_data->tx_end = drv_data->tx + transfer->len;
665 pr_debug("tx_buf is %p, tx_end is %p\n", transfer->tx_buf, 671 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
666 drv_data->tx_end); 672 transfer->tx_buf, drv_data->tx_end);
667 } else { 673 } else {
668 drv_data->tx = NULL; 674 drv_data->tx = NULL;
669 } 675 }
@@ -671,8 +677,8 @@ static void pump_transfers(unsigned long data)
671 if (transfer->rx_buf != NULL) { 677 if (transfer->rx_buf != NULL) {
672 drv_data->rx = transfer->rx_buf; 678 drv_data->rx = transfer->rx_buf;
673 drv_data->rx_end = drv_data->rx + transfer->len; 679 drv_data->rx_end = drv_data->rx + transfer->len;
674 pr_debug("rx_buf is %p, rx_end is %p\n", transfer->rx_buf, 680 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
675 drv_data->rx_end); 681 transfer->rx_buf, drv_data->rx_end);
676 } else { 682 } else {
677 drv_data->rx = NULL; 683 drv_data->rx = NULL;
678 } 684 }
@@ -690,9 +696,9 @@ static void pump_transfers(unsigned long data)
690 drv_data->write = drv_data->tx ? chip->write : null_writer; 696 drv_data->write = drv_data->tx ? chip->write : null_writer;
691 drv_data->read = drv_data->rx ? chip->read : null_reader; 697 drv_data->read = drv_data->rx ? chip->read : null_reader;
692 drv_data->duplex = chip->duplex ? chip->duplex : null_writer; 698 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
693 pr_debug 699 dev_dbg(&drv_data->pdev->dev,
694 ("transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n", 700 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
695 drv_data->write, chip->write, null_writer); 701 drv_data->write, chip->write, null_writer);
696 702
697 /* speed and width has been set on per message */ 703 /* speed and width has been set on per message */
698 message->state = RUNNING_STATE; 704 message->state = RUNNING_STATE;
@@ -706,8 +712,9 @@ static void pump_transfers(unsigned long data)
706 } 712 }
707 write_FLAG(chip->flag); 713 write_FLAG(chip->flag);
708 714
709 pr_debug("now pumping a transfer: width is %d, len is %d\n", width, 715 dev_dbg(&drv_data->pdev->dev,
710 transfer->len); 716 "now pumping a transfer: width is %d, len is %d\n",
717 width, transfer->len);
711 718
712 /* 719 /*
713 * Try to map dma buffer and do a dma transfer if 720 * Try to map dma buffer and do a dma transfer if
@@ -722,7 +729,7 @@ static void pump_transfers(unsigned long data)
722 bfin_spi_disable(drv_data); 729 bfin_spi_disable(drv_data);
723 730
724 /* config dma channel */ 731 /* config dma channel */
725 pr_debug("doing dma transfer\n"); 732 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
726 if (width == CFG_SPI_WORDSIZE16) { 733 if (width == CFG_SPI_WORDSIZE16) {
727 set_dma_x_count(CH_SPI, drv_data->len); 734 set_dma_x_count(CH_SPI, drv_data->len);
728 set_dma_x_modify(CH_SPI, 2); 735 set_dma_x_modify(CH_SPI, 2);
@@ -738,7 +745,8 @@ static void pump_transfers(unsigned long data)
738 745
739 /* dirty hack for autobuffer DMA mode */ 746 /* dirty hack for autobuffer DMA mode */
740 if (drv_data->tx_dma == 0xFFFF) { 747 if (drv_data->tx_dma == 0xFFFF) {
741 pr_debug("doing autobuffer DMA out.\n"); 748 dev_dbg(&drv_data->pdev->dev,
749 "doing autobuffer DMA out.\n");
742 750
743 /* no irq in autobuffer mode */ 751 /* no irq in autobuffer mode */
744 dma_config = 752 dma_config =
@@ -758,7 +766,7 @@ static void pump_transfers(unsigned long data)
758 /* In dma mode, rx or tx must be NULL in one transfer */ 766 /* In dma mode, rx or tx must be NULL in one transfer */
759 if (drv_data->rx != NULL) { 767 if (drv_data->rx != NULL) {
760 /* set transfer mode, and enable SPI */ 768 /* set transfer mode, and enable SPI */
761 pr_debug("doing DMA in.\n"); 769 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
762 770
763 /* disable SPI before write to TDBR */ 771 /* disable SPI before write to TDBR */
764 write_CTRL(cr & ~BIT_CTL_ENABLE); 772 write_CTRL(cr & ~BIT_CTL_ENABLE);
@@ -781,7 +789,7 @@ static void pump_transfers(unsigned long data)
781 /* set transfer mode, and enable SPI */ 789 /* set transfer mode, and enable SPI */
782 write_CTRL(cr); 790 write_CTRL(cr);
783 } else if (drv_data->tx != NULL) { 791 } else if (drv_data->tx != NULL) {
784 pr_debug("doing DMA out.\n"); 792 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
785 793
786 /* start dma */ 794 /* start dma */
787 dma_enable_irq(CH_SPI); 795 dma_enable_irq(CH_SPI);
@@ -796,7 +804,7 @@ static void pump_transfers(unsigned long data)
796 } 804 }
797 } else { 805 } else {
798 /* IO mode write then read */ 806 /* IO mode write then read */
799 pr_debug("doing IO transfer\n"); 807 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
800 808
801 write_STAT(BIT_STAT_CLR); 809 write_STAT(BIT_STAT_CLR);
802 810
@@ -804,11 +812,11 @@ static void pump_transfers(unsigned long data)
804 /* full duplex mode */ 812 /* full duplex mode */
805 BUG_ON((drv_data->tx_end - drv_data->tx) != 813 BUG_ON((drv_data->tx_end - drv_data->tx) !=
806 (drv_data->rx_end - drv_data->rx)); 814 (drv_data->rx_end - drv_data->rx));
807 cr = (read_CTRL() & (~BIT_CTL_TIMOD)); /* clear the TIMOD bits */ 815 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
808 cr |= 816 cr |= CFG_SPI_WRITE | (width << 8) |
809 CFG_SPI_WRITE | (width << 8) | (CFG_SPI_ENABLE << 817 (CFG_SPI_ENABLE << 14);
810 14); 818 dev_dbg(&drv_data->pdev->dev,
811 pr_debug("IO duplex: cr is 0x%x\n", cr); 819 "IO duplex: cr is 0x%x\n", cr);
812 820
813 write_CTRL(cr); 821 write_CTRL(cr);
814 SSYNC(); 822 SSYNC();
@@ -819,11 +827,11 @@ static void pump_transfers(unsigned long data)
819 tranf_success = 0; 827 tranf_success = 0;
820 } else if (drv_data->tx != NULL) { 828 } else if (drv_data->tx != NULL) {
821 /* write only half duplex */ 829 /* write only half duplex */
822 cr = (read_CTRL() & (~BIT_CTL_TIMOD)); /* clear the TIMOD bits */ 830 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
823 cr |= 831 cr |= CFG_SPI_WRITE | (width << 8) |
824 CFG_SPI_WRITE | (width << 8) | (CFG_SPI_ENABLE << 832 (CFG_SPI_ENABLE << 14);
825 14); 833 dev_dbg(&drv_data->pdev->dev,
826 pr_debug("IO write: cr is 0x%x\n", cr); 834 "IO write: cr is 0x%x\n", cr);
827 835
828 write_CTRL(cr); 836 write_CTRL(cr);
829 SSYNC(); 837 SSYNC();
@@ -834,11 +842,11 @@ static void pump_transfers(unsigned long data)
834 tranf_success = 0; 842 tranf_success = 0;
835 } else if (drv_data->rx != NULL) { 843 } else if (drv_data->rx != NULL) {
836 /* read only half duplex */ 844 /* read only half duplex */
837 cr = (read_CTRL() & (~BIT_CTL_TIMOD)); /* cleare the TIMOD bits */ 845 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
838 cr |= 846 cr |= CFG_SPI_READ | (width << 8) |
839 CFG_SPI_READ | (width << 8) | (CFG_SPI_ENABLE << 847 (CFG_SPI_ENABLE << 14);
840 14); 848 dev_dbg(&drv_data->pdev->dev,
841 pr_debug("IO read: cr is 0x%x\n", cr); 849 "IO read: cr is 0x%x\n", cr);
842 850
843 write_CTRL(cr); 851 write_CTRL(cr);
844 SSYNC(); 852 SSYNC();
@@ -849,7 +857,8 @@ static void pump_transfers(unsigned long data)
849 } 857 }
850 858
851 if (!tranf_success) { 859 if (!tranf_success) {
852 pr_debug("IO write error!\n"); 860 dev_dbg(&drv_data->pdev->dev,
861 "IO write error!\n");
853 message->state = ERROR_STATE; 862 message->state = ERROR_STATE;
854 } else { 863 } else {
855 /* Update total byte transfered */ 864 /* Update total byte transfered */
@@ -899,11 +908,14 @@ static void pump_messages(struct work_struct *work)
899 /* Setup the SSP using the per chip configuration */ 908 /* Setup the SSP using the per chip configuration */
900 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); 909 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
901 restore_state(drv_data); 910 restore_state(drv_data);
902 pr_debug 911 dev_dbg(&drv_data->pdev->dev,
903 ("got a message to pump, state is set to: baud %d, flag 0x%x, ctl 0x%x\n", 912 "got a message to pump, state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
904 drv_data->cur_chip->baud, drv_data->cur_chip->flag, 913 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
905 drv_data->cur_chip->ctl_reg); 914 drv_data->cur_chip->ctl_reg);
906 pr_debug("the first transfer len is %d\n", drv_data->cur_transfer->len); 915
916 dev_dbg(&drv_data->pdev->dev,
917 "the first transfer len is %d\n",
918 drv_data->cur_transfer->len);
907 919
908 /* Mark as busy and launch transfers */ 920 /* Mark as busy and launch transfers */
909 tasklet_schedule(&drv_data->pump_transfers); 921 tasklet_schedule(&drv_data->pump_transfers);
@@ -932,7 +944,7 @@ static int transfer(struct spi_device *spi, struct spi_message *msg)
932 msg->status = -EINPROGRESS; 944 msg->status = -EINPROGRESS;
933 msg->state = START_STATE; 945 msg->state = START_STATE;
934 946
935 pr_debug("adding an msg in transfer() \n"); 947 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
936 list_add_tail(&msg->queue, &drv_data->queue); 948 list_add_tail(&msg->queue, &drv_data->queue);
937 949
938 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) 950 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
@@ -1002,13 +1014,13 @@ static int setup(struct spi_device *spi)
1002 if (chip->enable_dma && !dma_requested) { 1014 if (chip->enable_dma && !dma_requested) {
1003 /* register dma irq handler */ 1015 /* register dma irq handler */
1004 if (request_dma(CH_SPI, "BF53x_SPI_DMA") < 0) { 1016 if (request_dma(CH_SPI, "BF53x_SPI_DMA") < 0) {
1005 pr_debug 1017 dev_dbg(&spi->dev,
1006 ("Unable to request BlackFin SPI DMA channel\n"); 1018 "Unable to request BlackFin SPI DMA channel\n");
1007 return -ENODEV; 1019 return -ENODEV;
1008 } 1020 }
1009 if (set_dma_callback(CH_SPI, (void *)dma_irq_handler, drv_data) 1021 if (set_dma_callback(CH_SPI, (void *)dma_irq_handler, drv_data)
1010 < 0) { 1022 < 0) {
1011 pr_debug("Unable to set dma callback\n"); 1023 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1012 return -EPERM; 1024 return -EPERM;
1013 } 1025 }
1014 dma_disable_irq(CH_SPI); 1026 dma_disable_irq(CH_SPI);
@@ -1054,9 +1066,9 @@ static int setup(struct spi_device *spi)
1054 return -ENODEV; 1066 return -ENODEV;
1055 } 1067 }
1056 1068
1057 pr_debug("setup spi chip %s, width is %d, dma is %d,", 1069 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d,",
1058 spi->modalias, chip->width, chip->enable_dma); 1070 spi->modalias, chip->width, chip->enable_dma);
1059 pr_debug("ctl_reg is 0x%x, flag_reg is 0x%x\n", 1071 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1060 chip->ctl_reg, chip->flag); 1072 chip->ctl_reg, chip->flag);
1061 1073
1062 spi_set_ctldata(spi, chip); 1074 spi_set_ctldata(spi, chip);
@@ -1068,7 +1080,7 @@ static int setup(struct spi_device *spi)
1068 * callback for spi framework. 1080 * callback for spi framework.
1069 * clean driver specific data 1081 * clean driver specific data
1070 */ 1082 */
1071static void cleanup(const struct spi_device *spi) 1083static void cleanup(struct spi_device *spi)
1072{ 1084{
1073 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi); 1085 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
1074 1086
@@ -1207,7 +1219,7 @@ static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1207 dev_err(&pdev->dev, "problem registering spi master\n"); 1219 dev_err(&pdev->dev, "problem registering spi master\n");
1208 goto out_error_queue_alloc; 1220 goto out_error_queue_alloc;
1209 } 1221 }
1210 pr_debug("controller probe successfully\n"); 1222 dev_dbg(&pdev->dev, "controller probe successfully\n");
1211 return status; 1223 return status;
1212 1224
1213 out_error_queue_alloc: 1225 out_error_queue_alloc:
@@ -1287,27 +1299,23 @@ static int bfin5xx_spi_resume(struct platform_device *pdev)
1287#endif /* CONFIG_PM */ 1299#endif /* CONFIG_PM */
1288 1300
1289static struct platform_driver bfin5xx_spi_driver = { 1301static struct platform_driver bfin5xx_spi_driver = {
1290 .driver = { 1302 .driver = {
1291 .name = "bfin-spi-master", 1303 .name = "bfin-spi-master",
1292 .bus = &platform_bus_type, 1304 .owner = THIS_MODULE,
1293 .owner = THIS_MODULE, 1305 },
1294 }, 1306 .suspend = bfin5xx_spi_suspend,
1295 .probe = bfin5xx_spi_probe, 1307 .resume = bfin5xx_spi_resume,
1296 .remove = __devexit_p(bfin5xx_spi_remove), 1308 .remove = __devexit_p(bfin5xx_spi_remove),
1297 .suspend = bfin5xx_spi_suspend,
1298 .resume = bfin5xx_spi_resume,
1299}; 1309};
1300 1310
1301static int __init bfin5xx_spi_init(void) 1311static int __init bfin5xx_spi_init(void)
1302{ 1312{
1303 return platform_driver_register(&bfin5xx_spi_driver); 1313 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1304} 1314}
1305
1306module_init(bfin5xx_spi_init); 1315module_init(bfin5xx_spi_init);
1307 1316
1308static void __exit bfin5xx_spi_exit(void) 1317static void __exit bfin5xx_spi_exit(void)
1309{ 1318{
1310 platform_driver_unregister(&bfin5xx_spi_driver); 1319 platform_driver_unregister(&bfin5xx_spi_driver);
1311} 1320}
1312
1313module_exit(bfin5xx_spi_exit); 1321module_exit(bfin5xx_spi_exit);