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-rw-r--r--Documentation/devicetree/bindings/arm/samsung/pmu.txt2
-rw-r--r--arch/arm/Kconfig.debug20
-rw-r--r--arch/arm/boot/dts/exynos3250.dtsi15
-rw-r--r--arch/arm/boot/dts/exynos5250-cros-common.dtsi159
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts2
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts165
-rw-r--r--arch/arm/boot/dts/exynos5260.dtsi5
-rw-r--r--arch/arm/boot/dts/exynos5410.dtsi5
-rw-r--r--arch/arm/mach-exynos/common.h27
-rw-r--r--arch/arm/mach-exynos/exynos.c76
-rw-r--r--arch/arm/mach-exynos/headsmp.S1
-rw-r--r--arch/arm/mach-exynos/hotplug.c3
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h6
-rw-r--r--arch/arm/mach-exynos/include/mach/memory.h3
-rw-r--r--arch/arm/mach-exynos/mcpm-exynos.c106
-rw-r--r--arch/arm/mach-exynos/platsmp.c7
-rw-r--r--arch/arm/mach-exynos/pm.c77
-rw-r--r--arch/arm/mach-exynos/pm_domains.c9
-rw-r--r--arch/arm/mach-exynos/pmu.c41
-rw-r--r--arch/arm/mach-exynos/regs-pmu.h525
-rw-r--r--arch/arm/mach-exynos/regs-sys.h22
-rw-r--r--arch/arm/plat-samsung/include/plat/map-s5p.h1
-rw-r--r--drivers/cpuidle/Kconfig.arm2
-rw-r--r--drivers/cpuidle/cpuidle-big_little.c12
24 files changed, 697 insertions, 594 deletions
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 2a4ab046a8a1..e0e955e7af8c 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -7,6 +7,8 @@ Properties:
7 - "samsung,exynos4212-pmu" - for Exynos4212 SoC, 7 - "samsung,exynos4212-pmu" - for Exynos4212 SoC,
8 - "samsung,exynos4412-pmu" - for Exynos4412 SoC, 8 - "samsung,exynos4412-pmu" - for Exynos4412 SoC,
9 - "samsung,exynos5250-pmu" - for Exynos5250 SoC, 9 - "samsung,exynos5250-pmu" - for Exynos5250 SoC,
10 - "samsung,exynos5260-pmu" - for Exynos5260 SoC.
11 - "samsung,exynos5410-pmu" - for Exynos5410 SoC,
10 - "samsung,exynos5420-pmu" - for Exynos5420 SoC. 12 - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
11 second value must be always "syscon". 13 second value must be always "syscon".
12 14
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 8dcc00d44dab..e43b838bae4b 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -625,53 +625,41 @@ choice
625 depends on PLAT_SAMSUNG 625 depends on PLAT_SAMSUNG
626 select DEBUG_EXYNOS_UART if ARCH_EXYNOS 626 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
627 select DEBUG_S3C24XX_UART if ARCH_S3C24XX 627 select DEBUG_S3C24XX_UART if ARCH_S3C24XX
628 bool "Use S3C UART 0 for low-level debug" 628 bool "Use Samsung S3C UART 0 for low-level debug"
629 help 629 help
630 Say Y here if you want the debug print routines to direct 630 Say Y here if you want the debug print routines to direct
631 their output to UART 0. The port must have been initialised 631 their output to UART 0. The port must have been initialised
632 by the boot-loader before use. 632 by the boot-loader before use.
633 633
634 The uncompressor code port configuration is now handled
635 by CONFIG_S3C_LOWLEVEL_UART_PORT.
636
637 config DEBUG_S3C_UART1 634 config DEBUG_S3C_UART1
638 depends on PLAT_SAMSUNG 635 depends on PLAT_SAMSUNG
639 select DEBUG_EXYNOS_UART if ARCH_EXYNOS 636 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
640 select DEBUG_S3C24XX_UART if ARCH_S3C24XX 637 select DEBUG_S3C24XX_UART if ARCH_S3C24XX
641 bool "Use S3C UART 1 for low-level debug" 638 bool "Use Samsung S3C UART 1 for low-level debug"
642 help 639 help
643 Say Y here if you want the debug print routines to direct 640 Say Y here if you want the debug print routines to direct
644 their output to UART 1. The port must have been initialised 641 their output to UART 1. The port must have been initialised
645 by the boot-loader before use. 642 by the boot-loader before use.
646 643
647 The uncompressor code port configuration is now handled
648 by CONFIG_S3C_LOWLEVEL_UART_PORT.
649
650 config DEBUG_S3C_UART2 644 config DEBUG_S3C_UART2
651 depends on PLAT_SAMSUNG 645 depends on PLAT_SAMSUNG
652 select DEBUG_EXYNOS_UART if ARCH_EXYNOS 646 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
653 select DEBUG_S3C24XX_UART if ARCH_S3C24XX 647 select DEBUG_S3C24XX_UART if ARCH_S3C24XX
654 bool "Use S3C UART 2 for low-level debug" 648 bool "Use Samsung S3C UART 2 for low-level debug"
655 help 649 help
656 Say Y here if you want the debug print routines to direct 650 Say Y here if you want the debug print routines to direct
657 their output to UART 2. The port must have been initialised 651 their output to UART 2. The port must have been initialised
658 by the boot-loader before use. 652 by the boot-loader before use.
659 653
660 The uncompressor code port configuration is now handled
661 by CONFIG_S3C_LOWLEVEL_UART_PORT.
662
663 config DEBUG_S3C_UART3 654 config DEBUG_S3C_UART3
664 depends on PLAT_SAMSUNG && ARCH_EXYNOS 655 depends on PLAT_SAMSUNG && ARCH_EXYNOS
665 select DEBUG_EXYNOS_UART 656 select DEBUG_EXYNOS_UART
666 bool "Use S3C UART 3 for low-level debug" 657 bool "Use Samsung S3C UART 3 for low-level debug"
667 help 658 help
668 Say Y here if you want the debug print routines to direct 659 Say Y here if you want the debug print routines to direct
669 their output to UART 3. The port must have been initialised 660 their output to UART 3. The port must have been initialised
670 by the boot-loader before use. 661 by the boot-loader before use.
671 662
672 The uncompressor code port configuration is now handled
673 by CONFIG_S3C_LOWLEVEL_UART_PORT.
674
675 config DEBUG_S3C2410_UART0 663 config DEBUG_S3C2410_UART0
676 depends on ARCH_S3C24XX 664 depends on ARCH_S3C24XX
677 select DEBUG_S3C2410_UART 665 select DEBUG_S3C2410_UART
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 77a06df6dc72..abd6eb31b2c2 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -168,6 +168,15 @@
168 status = "disabled"; 168 status = "disabled";
169 }; 169 };
170 170
171 tmu: tmu@100C0000 {
172 compatible = "samsung,exynos3250-tmu";
173 reg = <0x100C0000 0x100>;
174 interrupts = <0 216 0>;
175 clocks = <&cmu CLK_TMU_APBIF>;
176 clock-names = "tmu_apbif";
177 status = "disabled";
178 };
179
171 gic: interrupt-controller@10481000 { 180 gic: interrupt-controller@10481000 {
172 compatible = "arm,cortex-a15-gic"; 181 compatible = "arm,cortex-a15-gic";
173 #interrupt-cells = <3>; 182 #interrupt-cells = <3>;
@@ -195,7 +204,6 @@
195 204
196 wakeup-interrupt-controller { 205 wakeup-interrupt-controller {
197 compatible = "samsung,exynos4210-wakeup-eint"; 206 compatible = "samsung,exynos4210-wakeup-eint";
198 interrupt-parent = <&gic>;
199 interrupts = <0 48 0>; 207 interrupts = <0 48 0>;
200 }; 208 };
201 }; 209 };
@@ -234,7 +242,6 @@
234 compatible = "arm,amba-bus"; 242 compatible = "arm,amba-bus";
235 #address-cells = <1>; 243 #address-cells = <1>;
236 #size-cells = <1>; 244 #size-cells = <1>;
237 interrupt-parent = <&gic>;
238 ranges; 245 ranges;
239 246
240 pdma0: pdma@12680000 { 247 pdma0: pdma@12680000 {
@@ -277,6 +284,8 @@
277 interrupts = <0 109 0>; 284 interrupts = <0 109 0>;
278 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; 285 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
279 clock-names = "uart", "clk_uart_baud0"; 286 clock-names = "uart", "clk_uart_baud0";
287 pinctrl-names = "default";
288 pinctrl-0 = <&uart0_data &uart0_fctl>;
280 status = "disabled"; 289 status = "disabled";
281 }; 290 };
282 291
@@ -286,6 +295,8 @@
286 interrupts = <0 110 0>; 295 interrupts = <0 110 0>;
287 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; 296 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
288 clock-names = "uart", "clk_uart_baud0"; 297 clock-names = "uart", "clk_uart_baud0";
298 pinctrl-names = "default";
299 pinctrl-0 = <&uart1_data>;
289 status = "disabled"; 300 status = "disabled";
290 }; 301 };
291 302
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 89ac90f59e2e..e603e9c70142 100644
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -27,177 +27,18 @@
27 i2c2_bus: i2c2-bus { 27 i2c2_bus: i2c2-bus {
28 samsung,pin-pud = <0>; 28 samsung,pin-pud = <0>;
29 }; 29 };
30
31 max77686_irq: max77686-irq {
32 samsung,pins = "gpx3-2";
33 samsung,pin-function = <0>;
34 samsung,pin-pud = <0>;
35 samsung,pin-drv = <0>;
36 };
37 }; 30 };
38 31
39 i2c@12C60000 { 32 i2c@12C60000 {
40 status = "okay"; 33 status = "okay";
41 samsung,i2c-sda-delay = <100>; 34 samsung,i2c-sda-delay = <100>;
42 samsung,i2c-max-bus-freq = <378000>; 35 samsung,i2c-max-bus-freq = <378000>;
43
44 max77686@09 {
45 compatible = "maxim,max77686";
46 interrupt-parent = <&gpx3>;
47 interrupts = <2 0>;
48 pinctrl-names = "default";
49 pinctrl-0 = <&max77686_irq>;
50 wakeup-source;
51 reg = <0x09>;
52 #clock-cells = <1>;
53
54 voltage-regulators {
55 ldo1_reg: LDO1 {
56 regulator-name = "P1.0V_LDO_OUT1";
57 regulator-min-microvolt = <1000000>;
58 regulator-max-microvolt = <1000000>;
59 regulator-always-on;
60 };
61
62 ldo2_reg: LDO2 {
63 regulator-name = "P1.8V_LDO_OUT2";
64 regulator-min-microvolt = <1800000>;
65 regulator-max-microvolt = <1800000>;
66 regulator-always-on;
67 };
68
69 ldo3_reg: LDO3 {
70 regulator-name = "P1.8V_LDO_OUT3";
71 regulator-min-microvolt = <1800000>;
72 regulator-max-microvolt = <1800000>;
73 regulator-always-on;
74 };
75
76 ldo7_reg: LDO7 {
77 regulator-name = "P1.1V_LDO_OUT7";
78 regulator-min-microvolt = <1100000>;
79 regulator-max-microvolt = <1100000>;
80 regulator-always-on;
81 };
82
83 ldo8_reg: LDO8 {
84 regulator-name = "P1.0V_LDO_OUT8";
85 regulator-min-microvolt = <1000000>;
86 regulator-max-microvolt = <1000000>;
87 regulator-always-on;
88 };
89
90 ldo10_reg: LDO10 {
91 regulator-name = "P1.8V_LDO_OUT10";
92 regulator-min-microvolt = <1800000>;
93 regulator-max-microvolt = <1800000>;
94 regulator-always-on;
95 };
96
97 ldo12_reg: LDO12 {
98 regulator-name = "P3.0V_LDO_OUT12";
99 regulator-min-microvolt = <3000000>;
100 regulator-max-microvolt = <3000000>;
101 regulator-always-on;
102 };
103
104 ldo14_reg: LDO14 {
105 regulator-name = "P1.8V_LDO_OUT14";
106 regulator-min-microvolt = <1800000>;
107 regulator-max-microvolt = <1800000>;
108 regulator-always-on;
109 };
110
111 ldo15_reg: LDO15 {
112 regulator-name = "P1.0V_LDO_OUT15";
113 regulator-min-microvolt = <1000000>;
114 regulator-max-microvolt = <1000000>;
115 regulator-always-on;
116 };
117
118 ldo16_reg: LDO16 {
119 regulator-name = "P1.8V_LDO_OUT16";
120 regulator-min-microvolt = <1800000>;
121 regulator-max-microvolt = <1800000>;
122 regulator-always-on;
123 };
124
125 buck1_reg: BUCK1 {
126 regulator-name = "vdd_mif";
127 regulator-min-microvolt = <950000>;
128 regulator-max-microvolt = <1300000>;
129 regulator-always-on;
130 regulator-boot-on;
131 };
132
133 buck2_reg: BUCK2 {
134 regulator-name = "vdd_arm";
135 regulator-min-microvolt = <850000>;
136 regulator-max-microvolt = <1350000>;
137 regulator-always-on;
138 regulator-boot-on;
139 };
140
141 buck3_reg: BUCK3 {
142 regulator-name = "vdd_int";
143 regulator-min-microvolt = <900000>;
144 regulator-max-microvolt = <1200000>;
145 regulator-always-on;
146 regulator-boot-on;
147 };
148
149 buck4_reg: BUCK4 {
150 regulator-name = "vdd_g3d";
151 regulator-min-microvolt = <850000>;
152 regulator-max-microvolt = <1300000>;
153 regulator-always-on;
154 regulator-boot-on;
155 };
156
157 buck5_reg: BUCK5 {
158 regulator-name = "P1.8V_BUCK_OUT5";
159 regulator-min-microvolt = <1800000>;
160 regulator-max-microvolt = <1800000>;
161 regulator-always-on;
162 regulator-boot-on;
163 };
164
165 buck6_reg: BUCK6 {
166 regulator-name = "P1.35V_BUCK_OUT6";
167 regulator-min-microvolt = <1350000>;
168 regulator-max-microvolt = <1350000>;
169 regulator-always-on;
170 };
171
172 buck7_reg: BUCK7 {
173 regulator-name = "P2.0V_BUCK_OUT7";
174 regulator-min-microvolt = <2000000>;
175 regulator-max-microvolt = <2000000>;
176 regulator-always-on;
177 };
178
179 buck8_reg: BUCK8 {
180 regulator-name = "P2.85V_BUCK_OUT8";
181 regulator-min-microvolt = <2850000>;
182 regulator-max-microvolt = <2850000>;
183 regulator-always-on;
184 };
185 };
186 };
187 }; 36 };
188 37
189 i2c@12C70000 { 38 i2c@12C70000 {
190 status = "okay"; 39 status = "okay";
191 samsung,i2c-sda-delay = <100>; 40 samsung,i2c-sda-delay = <100>;
192 samsung,i2c-max-bus-freq = <378000>; 41 samsung,i2c-max-bus-freq = <378000>;
193
194 trackpad {
195 reg = <0x67>;
196 compatible = "cypress,cyapa";
197 interrupts = <2 0>;
198 interrupt-parent = <&gpx1>;
199 wakeup-source;
200 };
201 }; 42 };
202 43
203 i2c@12C80000 { 44 i2c@12C80000 {
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index a794a705d404..aaa055ac0fe3 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -44,6 +44,8 @@
44 max77686@09 { 44 max77686@09 {
45 compatible = "maxim,max77686"; 45 compatible = "maxim,max77686";
46 reg = <0x09>; 46 reg = <0x09>;
47 interrupt-parent = <&gpx3>;
48 interrupts = <2 0>;
47 49
48 voltage-regulators { 50 voltage-regulators {
49 ldo1_reg: LDO1 { 51 ldo1_reg: LDO1 {
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index c682c8831172..f2b8c4116541 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -344,4 +344,169 @@
344 }; 344 };
345}; 345};
346 346
347&i2c_0 {
348 max77686@09 {
349 compatible = "maxim,max77686";
350 interrupt-parent = <&gpx3>;
351 interrupts = <2 0>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&max77686_irq>;
354 wakeup-source;
355 reg = <0x09>;
356 #clock-cells = <1>;
357
358 voltage-regulators {
359 ldo1_reg: LDO1 {
360 regulator-name = "P1.0V_LDO_OUT1";
361 regulator-min-microvolt = <1000000>;
362 regulator-max-microvolt = <1000000>;
363 regulator-always-on;
364 };
365
366 ldo2_reg: LDO2 {
367 regulator-name = "P1.8V_LDO_OUT2";
368 regulator-min-microvolt = <1800000>;
369 regulator-max-microvolt = <1800000>;
370 regulator-always-on;
371 };
372
373 ldo3_reg: LDO3 {
374 regulator-name = "P1.8V_LDO_OUT3";
375 regulator-min-microvolt = <1800000>;
376 regulator-max-microvolt = <1800000>;
377 regulator-always-on;
378 };
379
380 ldo7_reg: LDO7 {
381 regulator-name = "P1.1V_LDO_OUT7";
382 regulator-min-microvolt = <1100000>;
383 regulator-max-microvolt = <1100000>;
384 regulator-always-on;
385 };
386
387 ldo8_reg: LDO8 {
388 regulator-name = "P1.0V_LDO_OUT8";
389 regulator-min-microvolt = <1000000>;
390 regulator-max-microvolt = <1000000>;
391 regulator-always-on;
392 };
393
394 ldo10_reg: LDO10 {
395 regulator-name = "P1.8V_LDO_OUT10";
396 regulator-min-microvolt = <1800000>;
397 regulator-max-microvolt = <1800000>;
398 regulator-always-on;
399 };
400
401 ldo12_reg: LDO12 {
402 regulator-name = "P3.0V_LDO_OUT12";
403 regulator-min-microvolt = <3000000>;
404 regulator-max-microvolt = <3000000>;
405 regulator-always-on;
406 };
407
408 ldo14_reg: LDO14 {
409 regulator-name = "P1.8V_LDO_OUT14";
410 regulator-min-microvolt = <1800000>;
411 regulator-max-microvolt = <1800000>;
412 regulator-always-on;
413 };
414
415 ldo15_reg: LDO15 {
416 regulator-name = "P1.0V_LDO_OUT15";
417 regulator-min-microvolt = <1000000>;
418 regulator-max-microvolt = <1000000>;
419 regulator-always-on;
420 };
421
422 ldo16_reg: LDO16 {
423 regulator-name = "P1.8V_LDO_OUT16";
424 regulator-min-microvolt = <1800000>;
425 regulator-max-microvolt = <1800000>;
426 regulator-always-on;
427 };
428
429 buck1_reg: BUCK1 {
430 regulator-name = "vdd_mif";
431 regulator-min-microvolt = <950000>;
432 regulator-max-microvolt = <1300000>;
433 regulator-always-on;
434 regulator-boot-on;
435 };
436
437 buck2_reg: BUCK2 {
438 regulator-name = "vdd_arm";
439 regulator-min-microvolt = <850000>;
440 regulator-max-microvolt = <1350000>;
441 regulator-always-on;
442 regulator-boot-on;
443 };
444
445 buck3_reg: BUCK3 {
446 regulator-name = "vdd_int";
447 regulator-min-microvolt = <900000>;
448 regulator-max-microvolt = <1200000>;
449 regulator-always-on;
450 regulator-boot-on;
451 };
452
453 buck4_reg: BUCK4 {
454 regulator-name = "vdd_g3d";
455 regulator-min-microvolt = <850000>;
456 regulator-max-microvolt = <1300000>;
457 regulator-always-on;
458 regulator-boot-on;
459 };
460
461 buck5_reg: BUCK5 {
462 regulator-name = "P1.8V_BUCK_OUT5";
463 regulator-min-microvolt = <1800000>;
464 regulator-max-microvolt = <1800000>;
465 regulator-always-on;
466 regulator-boot-on;
467 };
468
469 buck6_reg: BUCK6 {
470 regulator-name = "P1.35V_BUCK_OUT6";
471 regulator-min-microvolt = <1350000>;
472 regulator-max-microvolt = <1350000>;
473 regulator-always-on;
474 };
475
476 buck7_reg: BUCK7 {
477 regulator-name = "P2.0V_BUCK_OUT7";
478 regulator-min-microvolt = <2000000>;
479 regulator-max-microvolt = <2000000>;
480 regulator-always-on;
481 };
482
483 buck8_reg: BUCK8 {
484 regulator-name = "P2.85V_BUCK_OUT8";
485 regulator-min-microvolt = <2850000>;
486 regulator-max-microvolt = <2850000>;
487 regulator-always-on;
488 };
489 };
490 };
491};
492
493&i2c_1 {
494 trackpad {
495 reg = <0x67>;
496 compatible = "cypress,cyapa";
497 interrupts = <2 0>;
498 interrupt-parent = <&gpx1>;
499 wakeup-source;
500 };
501};
502
503&pinctrl_0 {
504 max77686_irq: max77686-irq {
505 samsung,pins = "gpx3-2";
506 samsung,pin-function = <0>;
507 samsung,pin-pud = <0>;
508 samsung,pin-drv = <0>;
509 };
510};
511
347#include "cros-ec-keyboard.dtsi" 512#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index 5398a60207ca..4f2fabeecb0e 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -227,6 +227,11 @@
227 interrupts = <0 243 0>; 227 interrupts = <0 243 0>;
228 }; 228 };
229 229
230 pmu_system_controller: system-controller@10D50000 {
231 compatible = "samsung,exynos5260-pmu", "syscon";
232 reg = <0x10D50000 0x10000>;
233 };
234
230 uart0: serial@12C00000 { 235 uart0: serial@12C00000 {
231 compatible = "samsung,exynos4210-uart"; 236 compatible = "samsung,exynos4210-uart";
232 reg = <0x12C00000 0x100>; 237 reg = <0x12C00000 0x100>;
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 9d0b8cc1409c..790d4886d7b5 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -91,6 +91,11 @@
91 reg = <0x10000000 0x100>; 91 reg = <0x10000000 0x100>;
92 }; 92 };
93 93
94 pmu_system_controller: system-controller@10040000 {
95 compatible = "samsung,exynos5410-pmu", "syscon";
96 reg = <0x10040000 0x5000>;
97 };
98
94 mct: mct@101C0000 { 99 mct: mct@101C0000 {
95 compatible = "samsung,exynos4210-mct"; 100 compatible = "samsung,exynos4210-mct";
96 reg = <0x101C0000 0xB00>; 101 reg = <0x101C0000 0xB00>;
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 1ee91763fa7c..47b904b3b973 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -111,25 +111,14 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
111#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \ 111#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \
112 soc_is_exynos5420() || soc_is_exynos5800()) 112 soc_is_exynos5420() || soc_is_exynos5800())
113 113
114void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
115
116struct map_desc;
117extern void __iomem *sysram_ns_base_addr; 114extern void __iomem *sysram_ns_base_addr;
118extern void __iomem *sysram_base_addr; 115extern void __iomem *sysram_base_addr;
119void exynos_init_io(void); 116extern void __iomem *pmu_base_addr;
120void exynos_restart(enum reboot_mode mode, const char *cmd);
121void exynos_sysram_init(void); 117void exynos_sysram_init(void);
122void exynos_cpuidle_init(void);
123void exynos_cpufreq_init(void);
124void exynos_init_late(void);
125 118
126void exynos_firmware_init(void); 119void exynos_firmware_init(void);
127 120
128#ifdef CONFIG_PINCTRL_EXYNOS
129extern u32 exynos_get_eint_wake_mask(void); 121extern u32 exynos_get_eint_wake_mask(void);
130#else
131static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; }
132#endif
133 122
134#ifdef CONFIG_PM_SLEEP 123#ifdef CONFIG_PM_SLEEP
135extern void __init exynos_pm_init(void); 124extern void __init exynos_pm_init(void);
@@ -145,7 +134,7 @@ extern void exynos_cpu_die(unsigned int cpu);
145 134
146/* PMU(Power Management Unit) support */ 135/* PMU(Power Management Unit) support */
147 136
148#define PMU_TABLE_END NULL 137#define PMU_TABLE_END (-1U)
149 138
150enum sys_powerdown { 139enum sys_powerdown {
151 SYS_AFTR, 140 SYS_AFTR,
@@ -155,7 +144,7 @@ enum sys_powerdown {
155}; 144};
156 145
157struct exynos_pmu_conf { 146struct exynos_pmu_conf {
158 void __iomem *reg; 147 unsigned int offset;
159 unsigned int val[NUM_SYS_POWERDOWN]; 148 unsigned int val[NUM_SYS_POWERDOWN];
160}; 149};
161 150
@@ -171,4 +160,14 @@ extern void exynos_enter_aftr(void);
171extern void s5p_init_cpu(void __iomem *cpuid_addr); 160extern void s5p_init_cpu(void __iomem *cpuid_addr);
172extern unsigned int samsung_rev(void); 161extern unsigned int samsung_rev(void);
173 162
163static inline void pmu_raw_writel(u32 val, u32 offset)
164{
165 __raw_writel(val, pmu_base_addr + offset);
166}
167
168static inline u32 pmu_raw_readl(u32 offset)
169{
170 return __raw_readl(pmu_base_addr + offset);
171}
172
174#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */ 173#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 46d893fcbe85..493dbc23936f 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -19,6 +19,7 @@
19#include <linux/of_platform.h> 19#include <linux/of_platform.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/pm_domain.h> 21#include <linux/pm_domain.h>
22#include <linux/irqchip.h>
22 23
23#include <asm/cacheflush.h> 24#include <asm/cacheflush.h>
24#include <asm/hardware/cache-l2x0.h> 25#include <asm/hardware/cache-l2x0.h>
@@ -29,6 +30,9 @@
29#include "common.h" 30#include "common.h"
30#include "mfc.h" 31#include "mfc.h"
31#include "regs-pmu.h" 32#include "regs-pmu.h"
33#include "regs-sys.h"
34
35void __iomem *pmu_base_addr;
32 36
33static struct map_desc exynos4_iodesc[] __initdata = { 37static struct map_desc exynos4_iodesc[] __initdata = {
34 { 38 {
@@ -57,11 +61,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
57 .length = SZ_4K, 61 .length = SZ_4K,
58 .type = MT_DEVICE, 62 .type = MT_DEVICE,
59 }, { 63 }, {
60 .virtual = (unsigned long)S5P_VA_PMU,
61 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
62 .length = SZ_64K,
63 .type = MT_DEVICE,
64 }, {
65 .virtual = (unsigned long)S5P_VA_COMBINER_BASE, 64 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
66 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER), 65 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
67 .length = SZ_4K, 66 .length = SZ_4K,
@@ -135,19 +134,14 @@ static struct map_desc exynos5_iodesc[] __initdata = {
135 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU), 134 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
136 .length = 144 * SZ_1K, 135 .length = 144 * SZ_1K,
137 .type = MT_DEVICE, 136 .type = MT_DEVICE,
138 }, {
139 .virtual = (unsigned long)S5P_VA_PMU,
140 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
141 .length = SZ_64K,
142 .type = MT_DEVICE,
143 }, 137 },
144}; 138};
145 139
146void exynos_restart(enum reboot_mode mode, const char *cmd) 140static void exynos_restart(enum reboot_mode mode, const char *cmd)
147{ 141{
148 struct device_node *np; 142 struct device_node *np;
149 u32 val = 0x1; 143 u32 val = 0x1;
150 void __iomem *addr = EXYNOS_SWRESET; 144 void __iomem *addr = pmu_base_addr + EXYNOS_SWRESET;
151 145
152 if (of_machine_is_compatible("samsung,exynos5440")) { 146 if (of_machine_is_compatible("samsung,exynos5440")) {
153 u32 status; 147 u32 status;
@@ -171,17 +165,6 @@ static struct platform_device exynos_cpuidle = {
171 .id = -1, 165 .id = -1,
172}; 166};
173 167
174void __init exynos_cpuidle_init(void)
175{
176 if (soc_is_exynos4210() || soc_is_exynos5250())
177 platform_device_register(&exynos_cpuidle);
178}
179
180void __init exynos_cpufreq_init(void)
181{
182 platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
183}
184
185void __iomem *sysram_base_addr; 168void __iomem *sysram_base_addr;
186void __iomem *sysram_ns_base_addr; 169void __iomem *sysram_ns_base_addr;
187 170
@@ -204,7 +187,7 @@ void __init exynos_sysram_init(void)
204 } 187 }
205} 188}
206 189
207void __init exynos_init_late(void) 190static void __init exynos_init_late(void)
208{ 191{
209 if (of_machine_is_compatible("samsung,exynos5440")) 192 if (of_machine_is_compatible("samsung,exynos5440"))
210 /* to be supported later */ 193 /* to be supported later */
@@ -251,7 +234,7 @@ static void __init exynos_map_io(void)
251 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); 234 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
252} 235}
253 236
254void __init exynos_init_io(void) 237static void __init exynos_init_io(void)
255{ 238{
256 debug_ll_io_init(); 239 debug_ll_io_init();
257 240
@@ -263,6 +246,41 @@ void __init exynos_init_io(void)
263 exynos_map_io(); 246 exynos_map_io();
264} 247}
265 248
249static const struct of_device_id exynos_dt_pmu_match[] = {
250 { .compatible = "samsung,exynos3250-pmu" },
251 { .compatible = "samsung,exynos4210-pmu" },
252 { .compatible = "samsung,exynos4212-pmu" },
253 { .compatible = "samsung,exynos4412-pmu" },
254 { .compatible = "samsung,exynos5250-pmu" },
255 { .compatible = "samsung,exynos5260-pmu" },
256 { .compatible = "samsung,exynos5410-pmu" },
257 { .compatible = "samsung,exynos5420-pmu" },
258 { /*sentinel*/ },
259};
260
261static void exynos_map_pmu(void)
262{
263 struct device_node *np;
264
265 np = of_find_matching_node(NULL, exynos_dt_pmu_match);
266 if (np)
267 pmu_base_addr = of_iomap(np, 0);
268
269 if (!pmu_base_addr)
270 panic("failed to find exynos pmu register\n");
271}
272
273static void __init exynos_init_irq(void)
274{
275 irqchip_init();
276 /*
277 * Since platsmp.c needs pmu base address by the time
278 * DT is not unflatten so we can't use DT APIs before
279 * init_irq
280 */
281 exynos_map_pmu();
282}
283
266static void __init exynos_dt_machine_init(void) 284static void __init exynos_dt_machine_init(void)
267{ 285{
268 struct device_node *i2c_np; 286 struct device_node *i2c_np;
@@ -298,8 +316,11 @@ static void __init exynos_dt_machine_init(void)
298 if (!IS_ENABLED(CONFIG_SMP)) 316 if (!IS_ENABLED(CONFIG_SMP))
299 exynos_sysram_init(); 317 exynos_sysram_init();
300 318
301 exynos_cpuidle_init(); 319 if (of_machine_is_compatible("samsung,exynos4210") ||
302 exynos_cpufreq_init(); 320 of_machine_is_compatible("samsung,exynos5250"))
321 platform_device_register(&exynos_cpuidle);
322
323 platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
303 324
304 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 325 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
305} 326}
@@ -343,6 +364,7 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
343 .smp = smp_ops(exynos_smp_ops), 364 .smp = smp_ops(exynos_smp_ops),
344 .map_io = exynos_init_io, 365 .map_io = exynos_init_io,
345 .init_early = exynos_firmware_init, 366 .init_early = exynos_firmware_init,
367 .init_irq = exynos_init_irq,
346 .init_machine = exynos_dt_machine_init, 368 .init_machine = exynos_dt_machine_init,
347 .init_late = exynos_init_late, 369 .init_late = exynos_init_late,
348 .dt_compat = exynos_dt_compat, 370 .dt_compat = exynos_dt_compat,
diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S
index cdd9d91e9933..b54f9701e421 100644
--- a/arch/arm/mach-exynos/headsmp.S
+++ b/arch/arm/mach-exynos/headsmp.S
@@ -1,5 +1,4 @@
1/* 1/*
2 * linux/arch/arm/mach-exynos4/headsmp.S
3 * 2 *
4 * Cloned from linux/arch/arm/mach-realview/headsmp.S 3 * Cloned from linux/arch/arm/mach-realview/headsmp.S
5 * 4 *
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 920a4baa53cd..4d86961a7957 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -1,5 +1,4 @@
1/* linux arch/arm/mach-exynos4/hotplug.c 1/*
2 *
3 * Cloned from linux/arch/arm/mach-realview/hotplug.c 2 * Cloned from linux/arch/arm/mach-realview/hotplug.c
4 * 3 *
5 * Copyright (C) 2002 ARM Ltd. 4 * Copyright (C) 2002 ARM Ltd.
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 548269a60634..f0b7e92bad6c 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -1,5 +1,4 @@
1/* linux/arch/arm/mach-exynos/include/mach/map.h 1/*
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 3 * http://www.samsung.com/
5 * 4 *
@@ -28,9 +27,6 @@
28#define EXYNOS4_PA_SYSCON 0x10010000 27#define EXYNOS4_PA_SYSCON 0x10010000
29#define EXYNOS5_PA_SYSCON 0x10050100 28#define EXYNOS5_PA_SYSCON 0x10050100
30 29
31#define EXYNOS4_PA_PMU 0x10020000
32#define EXYNOS5_PA_PMU 0x10040000
33
34#define EXYNOS4_PA_CMU 0x10030000 30#define EXYNOS4_PA_CMU 0x10030000
35#define EXYNOS5_PA_CMU 0x10010000 31#define EXYNOS5_PA_CMU 0x10010000
36 32
diff --git a/arch/arm/mach-exynos/include/mach/memory.h b/arch/arm/mach-exynos/include/mach/memory.h
index 2a4cdb7cb326..e19df1f18c0d 100644
--- a/arch/arm/mach-exynos/include/mach/memory.h
+++ b/arch/arm/mach-exynos/include/mach/memory.h
@@ -1,5 +1,4 @@
1/* linux/arch/arm/mach-exynos4/include/mach/memory.h 1/*
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index ace0ed617476..70e8ccd94668 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -26,6 +26,10 @@
26#define EXYNOS5420_CPUS_PER_CLUSTER 4 26#define EXYNOS5420_CPUS_PER_CLUSTER 4
27#define EXYNOS5420_NR_CLUSTERS 2 27#define EXYNOS5420_NR_CLUSTERS 2
28 28
29#define EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN BIT(9)
30#define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29)
31#define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30)
32
29/* 33/*
30 * The common v7_exit_coherency_flush API could not be used because of the 34 * The common v7_exit_coherency_flush API could not be used because of the
31 * Erratum 799270 workaround. This macro is the same as the common one (in 35 * Erratum 799270 workaround. This macro is the same as the common one (in
@@ -51,7 +55,7 @@
51 "dsb\n\t" \ 55 "dsb\n\t" \
52 "ldmfd sp!, {fp, ip}" \ 56 "ldmfd sp!, {fp, ip}" \
53 : \ 57 : \
54 : "Ir" (S5P_INFORM0) \ 58 : "Ir" (pmu_base_addr + S5P_INFORM0) \
55 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 59 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
56 "r9", "r10", "lr", "memory") 60 "r9", "r10", "lr", "memory")
57 61
@@ -73,36 +77,9 @@ cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
73 77
74#define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster) 78#define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster)
75 79
76static int exynos_cluster_power_control(unsigned int cluster, int enable)
77{
78 unsigned int tries = 100;
79 unsigned int val;
80
81 if (enable) {
82 exynos_cluster_power_up(cluster);
83 val = S5P_CORE_LOCAL_PWR_EN;
84 } else {
85 exynos_cluster_power_down(cluster);
86 val = 0;
87 }
88
89 /* Wait until cluster power control is applied */
90 while (tries--) {
91 if (exynos_cluster_power_state(cluster) == val)
92 return 0;
93
94 cpu_relax();
95 }
96 pr_debug("timed out waiting for cluster %u to power %s\n", cluster,
97 enable ? "on" : "off");
98
99 return -ETIMEDOUT;
100}
101
102static int exynos_power_up(unsigned int cpu, unsigned int cluster) 80static int exynos_power_up(unsigned int cpu, unsigned int cluster)
103{ 81{
104 unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER); 82 unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
105 int err = 0;
106 83
107 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); 84 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
108 if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER || 85 if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
@@ -126,12 +103,9 @@ static int exynos_power_up(unsigned int cpu, unsigned int cluster)
126 * cores. 103 * cores.
127 */ 104 */
128 if (was_cluster_down) 105 if (was_cluster_down)
129 err = exynos_cluster_power_control(cluster, 1); 106 exynos_cluster_power_up(cluster);
130 107
131 if (!err) 108 exynos_cpu_power_up(cpunr);
132 exynos_cpu_power_up(cpunr);
133 else
134 exynos_cluster_power_control(cluster, 0);
135 } else if (cpu_use_count[cpu][cluster] != 2) { 109 } else if (cpu_use_count[cpu][cluster] != 2) {
136 /* 110 /*
137 * The only possible values are: 111 * The only possible values are:
@@ -147,7 +121,7 @@ static int exynos_power_up(unsigned int cpu, unsigned int cluster)
147 arch_spin_unlock(&exynos_mcpm_lock); 121 arch_spin_unlock(&exynos_mcpm_lock);
148 local_irq_enable(); 122 local_irq_enable();
149 123
150 return err; 124 return 0;
151} 125}
152 126
153/* 127/*
@@ -178,9 +152,10 @@ static void exynos_power_down(void)
178 if (cpu_use_count[cpu][cluster] == 0) { 152 if (cpu_use_count[cpu][cluster] == 0) {
179 exynos_cpu_power_down(cpunr); 153 exynos_cpu_power_down(cpunr);
180 154
181 if (exynos_cluster_unused(cluster)) 155 if (exynos_cluster_unused(cluster)) {
182 /* TODO: Turn off the cluster here to save power. */ 156 exynos_cluster_power_down(cluster);
183 last_man = true; 157 last_man = true;
158 }
184 } else if (cpu_use_count[cpu][cluster] == 1) { 159 } else if (cpu_use_count[cpu][cluster] == 1) {
185 /* 160 /*
186 * A power_up request went ahead of us. 161 * A power_up request went ahead of us.
@@ -257,10 +232,46 @@ static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
257 return -ETIMEDOUT; /* timeout */ 232 return -ETIMEDOUT; /* timeout */
258} 233}
259 234
235static void exynos_powered_up(void)
236{
237 unsigned int mpidr, cpu, cluster;
238
239 mpidr = read_cpuid_mpidr();
240 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
241 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
242
243 arch_spin_lock(&exynos_mcpm_lock);
244 if (cpu_use_count[cpu][cluster] == 0)
245 cpu_use_count[cpu][cluster] = 1;
246 arch_spin_unlock(&exynos_mcpm_lock);
247}
248
249static void exynos_suspend(u64 residency)
250{
251 unsigned int mpidr, cpunr;
252
253 exynos_power_down();
254
255 /*
256 * Execution reaches here only if cpu did not power down.
257 * Hence roll back the changes done in exynos_power_down function.
258 *
259 * CAUTION: "This function requires the stack data to be visible through
260 * power down and can only be executed on processors like A15 and A7
261 * that hit the cache with the C bit clear in the SCTLR register."
262 */
263 mpidr = read_cpuid_mpidr();
264 cpunr = exynos_pmu_cpunr(mpidr);
265
266 exynos_cpu_power_up(cpunr);
267}
268
260static const struct mcpm_platform_ops exynos_power_ops = { 269static const struct mcpm_platform_ops exynos_power_ops = {
261 .power_up = exynos_power_up, 270 .power_up = exynos_power_up,
262 .power_down = exynos_power_down, 271 .power_down = exynos_power_down,
263 .wait_for_powerdown = exynos_wait_for_powerdown, 272 .wait_for_powerdown = exynos_wait_for_powerdown,
273 .suspend = exynos_suspend,
274 .powered_up = exynos_powered_up,
264}; 275};
265 276
266static void __init exynos_mcpm_usage_count_init(void) 277static void __init exynos_mcpm_usage_count_init(void)
@@ -299,6 +310,7 @@ static int __init exynos_mcpm_init(void)
299{ 310{
300 struct device_node *node; 311 struct device_node *node;
301 void __iomem *ns_sram_base_addr; 312 void __iomem *ns_sram_base_addr;
313 unsigned int value, i;
302 int ret; 314 int ret;
303 315
304 node = of_find_matching_node(NULL, exynos_dt_mcpm_match); 316 node = of_find_matching_node(NULL, exynos_dt_mcpm_match);
@@ -325,7 +337,7 @@ static int __init exynos_mcpm_init(void)
325 * To increase the stability of KFC reset we need to program 337 * To increase the stability of KFC reset we need to program
326 * the PMU SPARE3 register 338 * the PMU SPARE3 register
327 */ 339 */
328 __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3); 340 pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
329 341
330 exynos_mcpm_usage_count_init(); 342 exynos_mcpm_usage_count_init();
331 343
@@ -342,6 +354,26 @@ static int __init exynos_mcpm_init(void)
342 pr_info("Exynos MCPM support installed\n"); 354 pr_info("Exynos MCPM support installed\n");
343 355
344 /* 356 /*
357 * On Exynos5420/5800 for the A15 and A7 clusters:
358 *
359 * EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN ensures that all the cores
360 * in a cluster are turned off before turning off the cluster L2.
361 *
362 * EXYNOS5420_USE_ARM_CORE_DOWN_STATE ensures that a cores is powered
363 * off before waking it up.
364 *
365 * EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 will be
366 * turned on before the first man is powered up.
367 */
368 for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
369 value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
370 value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
371 EXYNOS5420_USE_ARM_CORE_DOWN_STATE |
372 EXYNOS5420_USE_L2_COMMON_UP_STATE;
373 pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
374 }
375
376 /*
345 * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr 377 * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
346 * as part of secondary_cpu_start(). Let's redirect it to the 378 * as part of secondary_cpu_start(). Let's redirect it to the
347 * mcpm_entry_point(). 379 * mcpm_entry_point().
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 50b9aad5e27b..7c829989859c 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/mach-exynos4/platsmp.c 1 /*
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
@@ -27,6 +26,8 @@
27#include <asm/smp_scu.h> 26#include <asm/smp_scu.h>
28#include <asm/firmware.h> 27#include <asm/firmware.h>
29 28
29#include <mach/map.h>
30
30#include "common.h" 31#include "common.h"
31#include "regs-pmu.h" 32#include "regs-pmu.h"
32 33
@@ -35,7 +36,7 @@ extern void exynos4_secondary_startup(void);
35static inline void __iomem *cpu_boot_reg_base(void) 36static inline void __iomem *cpu_boot_reg_base(void)
36{ 37{
37 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1) 38 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
38 return S5P_INFORM5; 39 return pmu_base_addr + S5P_INFORM5;
39 return sysram_base_addr; 40 return sysram_base_addr;
40} 41}
41 42
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 202ca73e49c4..bcb96be1efee 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -35,6 +35,7 @@
35 35
36#include "common.h" 36#include "common.h"
37#include "regs-pmu.h" 37#include "regs-pmu.h"
38#include "regs-sys.h"
38 39
39/** 40/**
40 * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping 41 * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
@@ -110,7 +111,7 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
110 */ 111 */
111void exynos_cpu_power_down(int cpu) 112void exynos_cpu_power_down(int cpu)
112{ 113{
113 __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); 114 pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
114} 115}
115 116
116/** 117/**
@@ -121,8 +122,8 @@ void exynos_cpu_power_down(int cpu)
121 */ 122 */
122void exynos_cpu_power_up(int cpu) 123void exynos_cpu_power_up(int cpu)
123{ 124{
124 __raw_writel(S5P_CORE_LOCAL_PWR_EN, 125 pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
125 EXYNOS_ARM_CORE_CONFIGURATION(cpu)); 126 EXYNOS_ARM_CORE_CONFIGURATION(cpu));
126} 127}
127 128
128/** 129/**
@@ -132,7 +133,7 @@ void exynos_cpu_power_up(int cpu)
132 */ 133 */
133int exynos_cpu_power_state(int cpu) 134int exynos_cpu_power_state(int cpu)
134{ 135{
135 return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) & 136 return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
136 S5P_CORE_LOCAL_PWR_EN); 137 S5P_CORE_LOCAL_PWR_EN);
137} 138}
138 139
@@ -142,7 +143,7 @@ int exynos_cpu_power_state(int cpu)
142 */ 143 */
143void exynos_cluster_power_down(int cluster) 144void exynos_cluster_power_down(int cluster)
144{ 145{
145 __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster)); 146 pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
146} 147}
147 148
148/** 149/**
@@ -151,8 +152,8 @@ void exynos_cluster_power_down(int cluster)
151 */ 152 */
152void exynos_cluster_power_up(int cluster) 153void exynos_cluster_power_up(int cluster)
153{ 154{
154 __raw_writel(S5P_CORE_LOCAL_PWR_EN, 155 pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
155 EXYNOS_COMMON_CONFIGURATION(cluster)); 156 EXYNOS_COMMON_CONFIGURATION(cluster));
156} 157}
157 158
158/** 159/**
@@ -162,16 +163,20 @@ void exynos_cluster_power_up(int cluster)
162 */ 163 */
163int exynos_cluster_power_state(int cluster) 164int exynos_cluster_power_state(int cluster)
164{ 165{
165 return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) & 166 return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
166 S5P_CORE_LOCAL_PWR_EN); 167 S5P_CORE_LOCAL_PWR_EN);
167} 168}
168 169
169#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 170#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
170 S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ 171 pmu_base_addr + S5P_INFORM7 : \
171 (sysram_base_addr + 0x24) : S5P_INFORM0)) 172 (samsung_rev() == EXYNOS4210_REV_1_0 ? \
173 (sysram_base_addr + 0x24) : \
174 pmu_base_addr + S5P_INFORM0))
172#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 175#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
173 S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ 176 pmu_base_addr + S5P_INFORM6 : \
174 (sysram_base_addr + 0x20) : S5P_INFORM1)) 177 (samsung_rev() == EXYNOS4210_REV_1_0 ? \
178 (sysram_base_addr + 0x20) : \
179 pmu_base_addr + S5P_INFORM1))
175 180
176#define S5P_CHECK_AFTR 0xFCBA0D10 181#define S5P_CHECK_AFTR 0xFCBA0D10
177#define S5P_CHECK_SLEEP 0x00000BAD 182#define S5P_CHECK_SLEEP 0x00000BAD
@@ -179,7 +184,7 @@ int exynos_cluster_power_state(int cluster)
179/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ 184/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
180static void exynos_set_wakeupmask(long mask) 185static void exynos_set_wakeupmask(long mask)
181{ 186{
182 __raw_writel(mask, S5P_WAKEUP_MASK); 187 pmu_raw_writel(mask, S5P_WAKEUP_MASK);
183} 188}
184 189
185static void exynos_cpu_set_boot_vector(long flags) 190static void exynos_cpu_set_boot_vector(long flags)
@@ -256,27 +261,27 @@ static void exynos_pm_prepare(void)
256 unsigned int tmp; 261 unsigned int tmp;
257 262
258 /* Set wake-up mask registers */ 263 /* Set wake-up mask registers */
259 __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); 264 pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
260 __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); 265 pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
261 266
262 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 267 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
263 268
264 if (soc_is_exynos5250()) { 269 if (soc_is_exynos5250()) {
265 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save)); 270 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
266 /* Disable USE_RETENTION of JPEG_MEM_OPTION */ 271 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
267 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION); 272 tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
268 tmp &= ~EXYNOS5_OPTION_USE_RETENTION; 273 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
269 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); 274 pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
270 } 275 }
271 276
272 /* Set value of power down register for sleep mode */ 277 /* Set value of power down register for sleep mode */
273 278
274 exynos_sys_powerdown_conf(SYS_SLEEP); 279 exynos_sys_powerdown_conf(SYS_SLEEP);
275 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 280 pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
276 281
277 /* ensure at least INFORM0 has the resume address */ 282 /* ensure at least INFORM0 has the resume address */
278 283
279 __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 284 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
280} 285}
281 286
282static void exynos_pm_central_suspend(void) 287static void exynos_pm_central_suspend(void)
@@ -284,9 +289,9 @@ static void exynos_pm_central_suspend(void)
284 unsigned long tmp; 289 unsigned long tmp;
285 290
286 /* Setting Central Sequence Register for power down mode */ 291 /* Setting Central Sequence Register for power down mode */
287 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 292 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
288 tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 293 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
289 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 294 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
290} 295}
291 296
292static int exynos_pm_suspend(void) 297static int exynos_pm_suspend(void)
@@ -298,7 +303,7 @@ static int exynos_pm_suspend(void)
298 /* Setting SEQ_OPTION register */ 303 /* Setting SEQ_OPTION register */
299 304
300 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0); 305 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
301 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); 306 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
302 307
303 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) 308 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
304 exynos_cpu_save_register(); 309 exynos_cpu_save_register();
@@ -316,12 +321,12 @@ static int exynos_pm_central_resume(void)
316 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically 321 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
317 * in this situation. 322 * in this situation.
318 */ 323 */
319 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 324 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
320 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { 325 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
321 tmp |= S5P_CENTRAL_LOWPWR_CFG; 326 tmp |= S5P_CENTRAL_LOWPWR_CFG;
322 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 327 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
323 /* clear the wakeup state register */ 328 /* clear the wakeup state register */
324 __raw_writel(0x0, S5P_WAKEUP_STAT); 329 pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
325 /* No need to perform below restore code */ 330 /* No need to perform below restore code */
326 return -1; 331 return -1;
327 } 332 }
@@ -339,13 +344,13 @@ static void exynos_pm_resume(void)
339 344
340 /* For release retention */ 345 /* For release retention */
341 346
342 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); 347 pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
343 __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); 348 pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
344 __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); 349 pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
345 __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); 350 pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
346 __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); 351 pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
347 __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); 352 pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
348 __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); 353 pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
349 354
350 if (soc_is_exynos5250()) 355 if (soc_is_exynos5250())
351 s3c_pm_do_restore(exynos5_sys_save, 356 s3c_pm_do_restore(exynos5_sys_save,
@@ -359,7 +364,7 @@ static void exynos_pm_resume(void)
359early_wakeup: 364early_wakeup:
360 365
361 /* Clear SLEEP mode set in INFORM1 */ 366 /* Clear SLEEP mode set in INFORM1 */
362 __raw_writel(0x0, S5P_INFORM1); 367 pmu_raw_writel(0x0, S5P_INFORM1);
363 368
364 return; 369 return;
365} 370}
@@ -403,7 +408,7 @@ static int exynos_suspend_enter(suspend_state_t state)
403 s3c_pm_restore_uarts(); 408 s3c_pm_restore_uarts();
404 409
405 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, 410 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
406 __raw_readl(S5P_WAKEUP_STAT)); 411 pmu_raw_readl(S5P_WAKEUP_STAT));
407 412
408 s3c_pm_check_restore(); 413 s3c_pm_check_restore();
409 414
@@ -474,9 +479,9 @@ void __init exynos_pm_init(void)
474 gic_arch_extn.irq_set_wake = exynos_irq_set_wake; 479 gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
475 480
476 /* All wakeup disable */ 481 /* All wakeup disable */
477 tmp = __raw_readl(S5P_WAKEUP_MASK); 482 tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
478 tmp |= ((0xFF << 8) | (0x1F << 1)); 483 tmp |= ((0xFF << 8) | (0x1F << 1));
479 __raw_writel(tmp, S5P_WAKEUP_MASK); 484 pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
480 485
481 register_syscore_ops(&exynos_pm_syscore_ops); 486 register_syscore_ops(&exynos_pm_syscore_ops);
482 suspend_set_ops(&exynos_suspend_ops); 487 suspend_set_ops(&exynos_suspend_ops);
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 797cb134bfff..fd76e1b5a471 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -23,8 +23,7 @@
23#include <linux/of_platform.h> 23#include <linux/of_platform.h>
24#include <linux/sched.h> 24#include <linux/sched.h>
25 25
26#include "regs-pmu.h" 26#define INT_LOCAL_PWR_EN 0x7
27
28#define MAX_CLK_PER_DOMAIN 4 27#define MAX_CLK_PER_DOMAIN 4
29 28
30/* 29/*
@@ -63,13 +62,13 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
63 } 62 }
64 } 63 }
65 64
66 pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0; 65 pwr = power_on ? INT_LOCAL_PWR_EN : 0;
67 __raw_writel(pwr, base); 66 __raw_writel(pwr, base);
68 67
69 /* Wait max 1ms */ 68 /* Wait max 1ms */
70 timeout = 10; 69 timeout = 10;
71 70
72 while ((__raw_readl(base + 0x4) & S5P_INT_LOCAL_PWR_EN) != pwr) { 71 while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
73 if (!timeout) { 72 if (!timeout) {
74 op = (power_on) ? "enable" : "disable"; 73 op = (power_on) ? "enable" : "disable";
75 pr_err("Power domain %s %s failed\n", domain->name, op); 74 pr_err("Power domain %s %s failed\n", domain->name, op);
@@ -231,7 +230,7 @@ static __init int exynos4_pm_init_power_domain(void)
231no_clk: 230no_clk:
232 platform_set_drvdata(pdev, pd); 231 platform_set_drvdata(pdev, pd);
233 232
234 on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN; 233 on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;
235 234
236 pm_genpd_init(&pd->pd, NULL, !on); 235 pm_genpd_init(&pd->pd, NULL, !on);
237 } 236 }
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index fb0deda3b3a4..ff9d23f0a7d9 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -11,7 +11,6 @@
11 11
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/bug.h>
15 14
16#include "common.h" 15#include "common.h"
17#include "regs-pmu.h" 16#include "regs-pmu.h"
@@ -19,7 +18,7 @@
19static const struct exynos_pmu_conf *exynos_pmu_config; 18static const struct exynos_pmu_conf *exynos_pmu_config;
20 19
21static const struct exynos_pmu_conf exynos4210_pmu_config[] = { 20static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
22 /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ 21 /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
23 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, 22 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
24 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, 23 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
25 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, 24 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
@@ -213,7 +212,7 @@ static const struct exynos_pmu_conf exynos4412_pmu_config[] = {
213}; 212};
214 213
215static const struct exynos_pmu_conf exynos5250_pmu_config[] = { 214static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
216 /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ 215 /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
217 { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, 216 { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
218 { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 217 { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
219 { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, 218 { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
@@ -316,7 +315,7 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
316 { PMU_TABLE_END,}, 315 { PMU_TABLE_END,},
317}; 316};
318 317
319static void __iomem * const exynos5_list_both_cnt_feed[] = { 318static unsigned int const exynos5_list_both_cnt_feed[] = {
320 EXYNOS5_ARM_CORE0_OPTION, 319 EXYNOS5_ARM_CORE0_OPTION,
321 EXYNOS5_ARM_CORE1_OPTION, 320 EXYNOS5_ARM_CORE1_OPTION,
322 EXYNOS5_ARM_COMMON_OPTION, 321 EXYNOS5_ARM_COMMON_OPTION,
@@ -330,7 +329,7 @@ static void __iomem * const exynos5_list_both_cnt_feed[] = {
330 EXYNOS5_TOP_PWR_SYSMEM_OPTION, 329 EXYNOS5_TOP_PWR_SYSMEM_OPTION,
331}; 330};
332 331
333static void __iomem * const exynos5_list_diable_wfi_wfe[] = { 332static unsigned int const exynos5_list_diable_wfi_wfe[] = {
334 EXYNOS5_ARM_CORE1_OPTION, 333 EXYNOS5_ARM_CORE1_OPTION,
335 EXYNOS5_FSYS_ARM_OPTION, 334 EXYNOS5_FSYS_ARM_OPTION,
336 EXYNOS5_ISP_ARM_OPTION, 335 EXYNOS5_ISP_ARM_OPTION,
@@ -345,27 +344,27 @@ static void exynos5_init_pmu(void)
345 * Enable both SC_FEEDBACK and SC_COUNTER 344 * Enable both SC_FEEDBACK and SC_COUNTER
346 */ 345 */
347 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) { 346 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
348 tmp = __raw_readl(exynos5_list_both_cnt_feed[i]); 347 tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]);
349 tmp |= (EXYNOS5_USE_SC_FEEDBACK | 348 tmp |= (EXYNOS5_USE_SC_FEEDBACK |
350 EXYNOS5_USE_SC_COUNTER); 349 EXYNOS5_USE_SC_COUNTER);
351 __raw_writel(tmp, exynos5_list_both_cnt_feed[i]); 350 pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
352 } 351 }
353 352
354 /* 353 /*
355 * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable 354 * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
356 */ 355 */
357 tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION); 356 tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION);
358 tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; 357 tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
359 __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION); 358 pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
360 359
361 /* 360 /*
362 * Disable WFI/WFE on XXX_OPTION 361 * Disable WFI/WFE on XXX_OPTION
363 */ 362 */
364 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) { 363 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
365 tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]); 364 tmp = pmu_raw_readl(exynos5_list_diable_wfi_wfe[i]);
366 tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE | 365 tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
367 EXYNOS5_OPTION_USE_STANDBYWFI); 366 EXYNOS5_OPTION_USE_STANDBYWFI);
368 __raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]); 367 pmu_raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
369 } 368 }
370} 369}
371 370
@@ -376,14 +375,14 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
376 if (soc_is_exynos5250()) 375 if (soc_is_exynos5250())
377 exynos5_init_pmu(); 376 exynos5_init_pmu();
378 377
379 for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++) 378 for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++)
380 __raw_writel(exynos_pmu_config[i].val[mode], 379 pmu_raw_writel(exynos_pmu_config[i].val[mode],
381 exynos_pmu_config[i].reg); 380 exynos_pmu_config[i].offset);
382 381
383 if (soc_is_exynos4412()) { 382 if (soc_is_exynos4412()) {
384 for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++) 383 for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END ; i++)
385 __raw_writel(exynos4412_pmu_config[i].val[mode], 384 pmu_raw_writel(exynos4412_pmu_config[i].val[mode],
386 exynos4412_pmu_config[i].reg); 385 exynos4412_pmu_config[i].offset);
387 } 386 }
388} 387}
389 388
@@ -404,13 +403,13 @@ static int __init exynos_pmu_init(void)
404 * When SYS_WDTRESET is set, watchdog timer reset request 403 * When SYS_WDTRESET is set, watchdog timer reset request
405 * is ignored by power management unit. 404 * is ignored by power management unit.
406 */ 405 */
407 value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE); 406 value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
408 value &= ~EXYNOS5_SYS_WDTRESET; 407 value &= ~EXYNOS5_SYS_WDTRESET;
409 __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE); 408 pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
410 409
411 value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST); 410 value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
412 value &= ~EXYNOS5_SYS_WDTRESET; 411 value &= ~EXYNOS5_SYS_WDTRESET;
413 __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); 412 pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
414 413
415 exynos_pmu_config = exynos5250_pmu_config; 414 exynos_pmu_config = exynos5250_pmu_config;
416 pr_info("EXYNOS5250 PMU Initialize\n"); 415 pr_info("EXYNOS5250 PMU Initialize\n");
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 1d13b08708f0..96a1569262b5 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -12,304 +12,298 @@
12#ifndef __ASM_ARCH_REGS_PMU_H 12#ifndef __ASM_ARCH_REGS_PMU_H
13#define __ASM_ARCH_REGS_PMU_H __FILE__ 13#define __ASM_ARCH_REGS_PMU_H __FILE__
14 14
15#include <mach/map.h> 15#define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
16
17#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
18#define S5P_SYSREG(x) (S3C_VA_SYS + (x))
19
20#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
21 16
22#define S5P_CENTRAL_LOWPWR_CFG (1 << 16) 17#define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
23 18
24#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208) 19#define S5P_CENTRAL_SEQ_OPTION 0x0208
25 20
26#define S5P_USE_STANDBY_WFI0 (1 << 16) 21#define S5P_USE_STANDBY_WFI0 (1 << 16)
27#define S5P_USE_STANDBY_WFE0 (1 << 24) 22#define S5P_USE_STANDBY_WFE0 (1 << 24)
28 23
29#define EXYNOS_SWRESET S5P_PMUREG(0x0400) 24#define EXYNOS_SWRESET 0x0400
30#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4) 25#define EXYNOS5440_SWRESET 0x00C4
31 26
32#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) 27#define S5P_WAKEUP_STAT 0x0600
33#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) 28#define S5P_EINT_WAKEUP_MASK 0x0604
34#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) 29#define S5P_WAKEUP_MASK 0x0608
35 30
36#define S5P_INFORM0 S5P_PMUREG(0x0800) 31#define S5P_INFORM0 0x0800
37#define S5P_INFORM1 S5P_PMUREG(0x0804) 32#define S5P_INFORM1 0x0804
38#define S5P_INFORM5 S5P_PMUREG(0x0814) 33#define S5P_INFORM5 0x0814
39#define S5P_INFORM6 S5P_PMUREG(0x0818) 34#define S5P_INFORM6 0x0818
40#define S5P_INFORM7 S5P_PMUREG(0x081C) 35#define S5P_INFORM7 0x081C
41#define S5P_PMU_SPARE3 S5P_PMUREG(0x090C) 36#define S5P_PMU_SPARE3 0x090C
42 37
43#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000) 38#define S5P_ARM_CORE0_LOWPWR 0x1000
44#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004) 39#define S5P_DIS_IRQ_CORE0 0x1004
45#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008) 40#define S5P_DIS_IRQ_CENTRAL0 0x1008
46#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010) 41#define S5P_ARM_CORE1_LOWPWR 0x1010
47#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014) 42#define S5P_DIS_IRQ_CORE1 0x1014
48#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018) 43#define S5P_DIS_IRQ_CENTRAL1 0x1018
49#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080) 44#define S5P_ARM_COMMON_LOWPWR 0x1080
50#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0) 45#define S5P_L2_0_LOWPWR 0x10C0
51#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4) 46#define S5P_L2_1_LOWPWR 0x10C4
52#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100) 47#define S5P_CMU_ACLKSTOP_LOWPWR 0x1100
53#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104) 48#define S5P_CMU_SCLKSTOP_LOWPWR 0x1104
54#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C) 49#define S5P_CMU_RESET_LOWPWR 0x110C
55#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120) 50#define S5P_APLL_SYSCLK_LOWPWR 0x1120
56#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124) 51#define S5P_MPLL_SYSCLK_LOWPWR 0x1124
57#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128) 52#define S5P_VPLL_SYSCLK_LOWPWR 0x1128
58#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C) 53#define S5P_EPLL_SYSCLK_LOWPWR 0x112C
59#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138) 54#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 0x1138
60#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C) 55#define S5P_CMU_RESET_GPSALIVE_LOWPWR 0x113C
61#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140) 56#define S5P_CMU_CLKSTOP_CAM_LOWPWR 0x1140
62#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144) 57#define S5P_CMU_CLKSTOP_TV_LOWPWR 0x1144
63#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148) 58#define S5P_CMU_CLKSTOP_MFC_LOWPWR 0x1148
64#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C) 59#define S5P_CMU_CLKSTOP_G3D_LOWPWR 0x114C
65#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150) 60#define S5P_CMU_CLKSTOP_LCD0_LOWPWR 0x1150
66#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158) 61#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 0x1158
67#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C) 62#define S5P_CMU_CLKSTOP_GPS_LOWPWR 0x115C
68#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160) 63#define S5P_CMU_RESET_CAM_LOWPWR 0x1160
69#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164) 64#define S5P_CMU_RESET_TV_LOWPWR 0x1164
70#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168) 65#define S5P_CMU_RESET_MFC_LOWPWR 0x1168
71#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C) 66#define S5P_CMU_RESET_G3D_LOWPWR 0x116C
72#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170) 67#define S5P_CMU_RESET_LCD0_LOWPWR 0x1170
73#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178) 68#define S5P_CMU_RESET_MAUDIO_LOWPWR 0x1178
74#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C) 69#define S5P_CMU_RESET_GPS_LOWPWR 0x117C
75#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180) 70#define S5P_TOP_BUS_LOWPWR 0x1180
76#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184) 71#define S5P_TOP_RETENTION_LOWPWR 0x1184
77#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188) 72#define S5P_TOP_PWR_LOWPWR 0x1188
78#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0) 73#define S5P_LOGIC_RESET_LOWPWR 0x11A0
79#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0) 74#define S5P_ONENAND_MEM_LOWPWR 0x11C0
80#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8) 75#define S5P_G2D_ACP_MEM_LOWPWR 0x11C8
81#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC) 76#define S5P_USBOTG_MEM_LOWPWR 0x11CC
82#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0) 77#define S5P_HSMMC_MEM_LOWPWR 0x11D0
83#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4) 78#define S5P_CSSYS_MEM_LOWPWR 0x11D4
84#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8) 79#define S5P_SECSS_MEM_LOWPWR 0x11D8
85#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200) 80#define S5P_PAD_RETENTION_DRAM_LOWPWR 0x1200
86#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204) 81#define S5P_PAD_RETENTION_MAUDIO_LOWPWR 0x1204
87#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220) 82#define S5P_PAD_RETENTION_GPIO_LOWPWR 0x1220
88#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224) 83#define S5P_PAD_RETENTION_UART_LOWPWR 0x1224
89#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228) 84#define S5P_PAD_RETENTION_MMCA_LOWPWR 0x1228
90#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C) 85#define S5P_PAD_RETENTION_MMCB_LOWPWR 0x122C
91#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230) 86#define S5P_PAD_RETENTION_EBIA_LOWPWR 0x1230
92#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234) 87#define S5P_PAD_RETENTION_EBIB_LOWPWR 0x1234
93#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240) 88#define S5P_PAD_RETENTION_ISOLATION_LOWPWR 0x1240
94#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260) 89#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 0x1260
95#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280) 90#define S5P_XUSBXTI_LOWPWR 0x1280
96#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284) 91#define S5P_XXTI_LOWPWR 0x1284
97#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0) 92#define S5P_EXT_REGULATOR_LOWPWR 0x12C0
98#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300) 93#define S5P_GPIO_MODE_LOWPWR 0x1300
99#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340) 94#define S5P_GPIO_MODE_MAUDIO_LOWPWR 0x1340
100#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380) 95#define S5P_CAM_LOWPWR 0x1380
101#define S5P_TV_LOWPWR S5P_PMUREG(0x1384) 96#define S5P_TV_LOWPWR 0x1384
102#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388) 97#define S5P_MFC_LOWPWR 0x1388
103#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C) 98#define S5P_G3D_LOWPWR 0x138C
104#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390) 99#define S5P_LCD0_LOWPWR 0x1390
105#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398) 100#define S5P_MAUDIO_LOWPWR 0x1398
106#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) 101#define S5P_GPS_LOWPWR 0x139C
107#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) 102#define S5P_GPS_ALIVE_LOWPWR 0x13A0
108 103
109#define EXYNOS_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) 104#define EXYNOS_ARM_CORE0_CONFIGURATION 0x2000
110#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \ 105#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \
111 (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr))) 106 (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
112#define EXYNOS_ARM_CORE_STATUS(_nr) \ 107#define EXYNOS_ARM_CORE_STATUS(_nr) \
113 (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4) 108 (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
114 109
115#define EXYNOS_ARM_COMMON_CONFIGURATION S5P_PMUREG(0x2500) 110#define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500
116#define EXYNOS_COMMON_CONFIGURATION(_nr) \ 111#define EXYNOS_COMMON_CONFIGURATION(_nr) \
117 (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr))) 112 (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr)))
118#define EXYNOS_COMMON_STATUS(_nr) \ 113#define EXYNOS_COMMON_STATUS(_nr) \
119 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4) 114 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4)
115#define EXYNOS_COMMON_OPTION(_nr) \
116 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
120 117
121#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028) 118#define S5P_PAD_RET_MAUDIO_OPTION 0x3028
122#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108) 119#define S5P_PAD_RET_GPIO_OPTION 0x3108
123#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128) 120#define S5P_PAD_RET_UART_OPTION 0x3128
124#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148) 121#define S5P_PAD_RET_MMCA_OPTION 0x3148
125#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168) 122#define S5P_PAD_RET_MMCB_OPTION 0x3168
126#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188) 123#define S5P_PAD_RET_EBIA_OPTION 0x3188
127#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8) 124#define S5P_PAD_RET_EBIB_OPTION 0x31A8
128 125
129#define S5P_CORE_LOCAL_PWR_EN 0x3 126#define S5P_CORE_LOCAL_PWR_EN 0x3
130#define S5P_INT_LOCAL_PWR_EN 0x7
131 127
132/* Only for EXYNOS4210 */ 128/* Only for EXYNOS4210 */
133#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) 129#define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154
134#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174) 130#define S5P_CMU_RESET_LCD1_LOWPWR 0x1174
135#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4) 131#define S5P_MODIMIF_MEM_LOWPWR 0x11C4
136#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0) 132#define S5P_PCIE_MEM_LOWPWR 0x11E0
137#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4) 133#define S5P_SATA_MEM_LOWPWR 0x11E4
138#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394) 134#define S5P_LCD1_LOWPWR 0x1394
139 135
140/* Only for EXYNOS4x12 */ 136/* Only for EXYNOS4x12 */
141#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050) 137#define S5P_ISP_ARM_LOWPWR 0x1050
142#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054) 138#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 0x1054
143#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058) 139#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 0x1058
144#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110) 140#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 0x1110
145#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114) 141#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 0x1114
146#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C) 142#define S5P_CMU_RESET_COREBLK_LOWPWR 0x111C
147#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130) 143#define S5P_MPLLUSER_SYSCLK_LOWPWR 0x1130
148#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154) 144#define S5P_CMU_CLKSTOP_ISP_LOWPWR 0x1154
149#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174) 145#define S5P_CMU_RESET_ISP_LOWPWR 0x1174
150#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190) 146#define S5P_TOP_BUS_COREBLK_LOWPWR 0x1190
151#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194) 147#define S5P_TOP_RETENTION_COREBLK_LOWPWR 0x1194
152#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198) 148#define S5P_TOP_PWR_COREBLK_LOWPWR 0x1198
153#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4) 149#define S5P_OSCCLK_GATE_LOWPWR 0x11A4
154#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0) 150#define S5P_LOGIC_RESET_COREBLK_LOWPWR 0x11B0
155#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4) 151#define S5P_OSCCLK_GATE_COREBLK_LOWPWR 0x11B4
156#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4) 152#define S5P_HSI_MEM_LOWPWR 0x11C4
157#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC) 153#define S5P_ROTATOR_MEM_LOWPWR 0x11DC
158#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C) 154#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 0x123C
159#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250) 155#define S5P_PAD_ISOLATION_COREBLK_LOWPWR 0x1250
160#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320) 156#define S5P_GPIO_MODE_COREBLK_LOWPWR 0x1320
161#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344) 157#define S5P_TOP_ASB_RESET_LOWPWR 0x1344
162#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348) 158#define S5P_TOP_ASB_ISOLATION_LOWPWR 0x1348
163#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394) 159#define S5P_ISP_LOWPWR 0x1394
164#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0) 160#define S5P_DRAM_FREQ_DOWN_LOWPWR 0x13B0
165#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4) 161#define S5P_DDRPHY_DLLOFF_LOWPWR 0x13B4
166#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8) 162#define S5P_CMU_SYSCLK_ISP_LOWPWR 0x13B8
167#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC) 163#define S5P_CMU_SYSCLK_GPS_LOWPWR 0x13BC
168#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0) 164#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 0x13C0
169 165
170#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608) 166#define S5P_ARM_L2_0_OPTION 0x2608
171#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628) 167#define S5P_ARM_L2_1_OPTION 0x2628
172#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08) 168#define S5P_ONENAND_MEM_OPTION 0x2E08
173#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28) 169#define S5P_HSI_MEM_OPTION 0x2E28
174#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48) 170#define S5P_G2D_ACP_MEM_OPTION 0x2E48
175#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68) 171#define S5P_USBOTG_MEM_OPTION 0x2E68
176#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88) 172#define S5P_HSMMC_MEM_OPTION 0x2E88
177#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8) 173#define S5P_CSSYS_MEM_OPTION 0x2EA8
178#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8) 174#define S5P_SECSS_MEM_OPTION 0x2EC8
179#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48) 175#define S5P_ROTATOR_MEM_OPTION 0x2F48
180 176
181/* Only for EXYNOS4412 */ 177/* Only for EXYNOS4412 */
182#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020) 178#define S5P_ARM_CORE2_LOWPWR 0x1020
183#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024) 179#define S5P_DIS_IRQ_CORE2 0x1024
184#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028) 180#define S5P_DIS_IRQ_CENTRAL2 0x1028
185#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030) 181#define S5P_ARM_CORE3_LOWPWR 0x1030
186#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034) 182#define S5P_DIS_IRQ_CORE3 0x1034
187#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038) 183#define S5P_DIS_IRQ_CENTRAL3 0x1038
188 184
189/* For EXYNOS5 */ 185/* For EXYNOS5 */
190 186
191#define EXYNOS5_SYS_I2C_CFG S5P_SYSREG(0x0234) 187#define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408
192 188#define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C
193#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408)
194#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C)
195 189
196#define EXYNOS5_SYS_WDTRESET (1 << 20) 190#define EXYNOS5_SYS_WDTRESET (1 << 20)
197 191
198#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000) 192#define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000
199#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004) 193#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004
200#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008) 194#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008
201#define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010) 195#define EXYNOS5_ARM_CORE1_SYS_PWR_REG 0x1010
202#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014) 196#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014
203#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018) 197#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018
204#define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040) 198#define EXYNOS5_FSYS_ARM_SYS_PWR_REG 0x1040
205#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048) 199#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG 0x1048
206#define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050) 200#define EXYNOS5_ISP_ARM_SYS_PWR_REG 0x1050
207#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054) 201#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054
208#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058) 202#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058
209#define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080) 203#define EXYNOS5_ARM_COMMON_SYS_PWR_REG 0x1080
210#define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0) 204#define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0
211#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100) 205#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 0x1100
212#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104) 206#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 0x1104
213#define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C) 207#define EXYNOS5_CMU_RESET_SYS_PWR_REG 0x110C
214#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120) 208#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG 0x1120
215#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124) 209#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG 0x1124
216#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C) 210#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 0x112C
217#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130) 211#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 0x1130
218#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134) 212#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 0x1134
219#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138) 213#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 0x1138
220#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140) 214#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 0x1140
221#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144) 215#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 0x1144
222#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148) 216#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 0x1148
223#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C) 217#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 0x114C
224#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150) 218#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 0x1150
225#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154) 219#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 0x1154
226#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164) 220#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1164
227#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170) 221#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1170
228#define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180) 222#define EXYNOS5_TOP_BUS_SYS_PWR_REG 0x1180
229#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184) 223#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 0x1184
230#define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188) 224#define EXYNOS5_TOP_PWR_SYS_PWR_REG 0x1188
231#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190) 225#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 0x1190
232#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194) 226#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG 0x1194
233#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198) 227#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 0x1198
234#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0) 228#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 0x11A0
235#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4) 229#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4
236#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0) 230#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 0x11B0
237#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4) 231#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4
238#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0) 232#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 0x11C0
239#define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8) 233#define EXYNOS5_G2D_MEM_SYS_PWR_REG 0x11C8
240#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC) 234#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 0x11CC
241#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0) 235#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 0x11D0
242#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4) 236#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 0x11D4
243#define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8) 237#define EXYNOS5_SECSS_MEM_SYS_PWR_REG 0x11D8
244#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC) 238#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 0x11DC
245#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0) 239#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 0x11E0
246#define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4) 240#define EXYNOS5_INTROM_MEM_SYS_PWR_REG 0x11E4
247#define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8) 241#define EXYNOS5_JPEG_MEM_SYS_PWR_REG 0x11E8
248#define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC) 242#define EXYNOS5_HSI_MEM_SYS_PWR_REG 0x11EC
249#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4) 243#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 0x11F4
250#define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC) 244#define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC
251#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200) 245#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200
252#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204) 246#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204
253#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208) 247#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG 0x1208
254#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220) 248#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220
255#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224) 249#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224
256#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228) 250#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228
257#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C) 251#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C
258#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230) 252#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230
259#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234) 253#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234
260#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238) 254#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238
261#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C) 255#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG 0x123C
262#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240) 256#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 0x1240
263#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250) 257#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG 0x1250
264#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260) 258#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260
265#define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280) 259#define EXYNOS5_XUSBXTI_SYS_PWR_REG 0x1280
266#define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284) 260#define EXYNOS5_XXTI_SYS_PWR_REG 0x1284
267#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0) 261#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 0x12C0
268#define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300) 262#define EXYNOS5_GPIO_MODE_SYS_PWR_REG 0x1300
269#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320) 263#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 0x1320
270#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340) 264#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 0x1340
271#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344) 265#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 0x1344
272#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348) 266#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348
273#define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400) 267#define EXYNOS5_GSCL_SYS_PWR_REG 0x1400
274#define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404) 268#define EXYNOS5_ISP_SYS_PWR_REG 0x1404
275#define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408) 269#define EXYNOS5_MFC_SYS_PWR_REG 0x1408
276#define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C) 270#define EXYNOS5_G3D_SYS_PWR_REG 0x140C
277#define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414) 271#define EXYNOS5_DISP1_SYS_PWR_REG 0x1414
278#define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418) 272#define EXYNOS5_MAU_SYS_PWR_REG 0x1418
279#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480) 273#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 0x1480
280#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484) 274#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1484
281#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488) 275#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1488
282#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C) 276#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x148C
283#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494) 277#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1494
284#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498) 278#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1498
285#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0) 279#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0
286#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4) 280#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 0x14C4
287#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8) 281#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 0x14C8
288#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC) 282#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 0x14CC
289#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4) 283#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D4
290#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8) 284#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D8
291#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580) 285#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 0x1580
292#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584) 286#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 0x1584
293#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588) 287#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 0x1588
294#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C) 288#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 0x158C
295#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594) 289#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 0x1594
296#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598) 290#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 0x1598
297 291
298#define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008) 292#define EXYNOS5_ARM_CORE0_OPTION 0x2008
299#define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088) 293#define EXYNOS5_ARM_CORE1_OPTION 0x2088
300#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208) 294#define EXYNOS5_FSYS_ARM_OPTION 0x2208
301#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288) 295#define EXYNOS5_ISP_ARM_OPTION 0x2288
302#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408) 296#define EXYNOS5_ARM_COMMON_OPTION 0x2408
303#define EXYNOS5_ARM_L2_OPTION S5P_PMUREG(0x2608) 297#define EXYNOS5_ARM_L2_OPTION 0x2608
304#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48) 298#define EXYNOS5_TOP_PWR_OPTION 0x2C48
305#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8) 299#define EXYNOS5_TOP_PWR_SYSMEM_OPTION 0x2CC8
306#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48) 300#define EXYNOS5_JPEG_MEM_OPTION 0x2F48
307#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008) 301#define EXYNOS5_GSCL_OPTION 0x4008
308#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028) 302#define EXYNOS5_ISP_OPTION 0x4028
309#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048) 303#define EXYNOS5_MFC_OPTION 0x4048
310#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068) 304#define EXYNOS5_G3D_OPTION 0x4068
311#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8) 305#define EXYNOS5_DISP1_OPTION 0x40A8
312#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8) 306#define EXYNOS5_MAU_OPTION 0x40C8
313 307
314#define EXYNOS5_USE_SC_FEEDBACK (1 << 1) 308#define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
315#define EXYNOS5_USE_SC_COUNTER (1 << 0) 309#define EXYNOS5_USE_SC_COUNTER (1 << 0)
@@ -323,4 +317,13 @@
323 317
324#define EXYNOS5420_SWRESET_KFC_SEL 0x3 318#define EXYNOS5420_SWRESET_KFC_SEL 0x3
325 319
320#include <asm/cputype.h>
321#define MAX_CPUS_IN_CLUSTER 4
322
323static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
324{
325 return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
326 + MPIDR_AFFINITY_LEVEL(mpidr, 0));
327}
328
326#endif /* __ASM_ARCH_REGS_PMU_H */ 329#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/regs-sys.h b/arch/arm/mach-exynos/regs-sys.h
new file mode 100644
index 000000000000..84332b0dd7a6
--- /dev/null
+++ b/arch/arm/mach-exynos/regs-sys.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS - system register definition
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_REGS_SYS_H
13#define __ASM_ARCH_REGS_SYS_H __FILE__
14
15#include <mach/map.h>
16
17#define S5P_SYSREG(x) (S3C_VA_SYS + (x))
18
19/* For EXYNOS5 */
20#define EXYNOS5_SYS_I2C_CFG S5P_SYSREG(0x0234)
21
22#endif /* __ASM_ARCH_REGS_SYS_H */
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index c18678610bc0..f5b9d3ff9cd4 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -15,7 +15,6 @@
15 15
16#define S5P_VA_CHIPID S3C_ADDR(0x02000000) 16#define S5P_VA_CHIPID S3C_ADDR(0x02000000)
17#define S5P_VA_CMU S3C_ADDR(0x02100000) 17#define S5P_VA_CMU S3C_ADDR(0x02100000)
18#define S5P_VA_PMU S3C_ADDR(0x02180000)
19#define S5P_VA_GPIO S3C_ADDR(0x02200000) 18#define S5P_VA_GPIO S3C_ADDR(0x02200000)
20#define S5P_VA_GPIO1 S5P_VA_GPIO 19#define S5P_VA_GPIO1 S5P_VA_GPIO
21#define S5P_VA_GPIO2 S3C_ADDR(0x02240000) 20#define S5P_VA_GPIO2 S3C_ADDR(0x02240000)
diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index b6d69e899f5d..2f6b33ea6e08 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -9,7 +9,7 @@ config ARM_ARMADA_370_XP_CPUIDLE
9 9
10config ARM_BIG_LITTLE_CPUIDLE 10config ARM_BIG_LITTLE_CPUIDLE
11 bool "Support for ARM big.LITTLE processors" 11 bool "Support for ARM big.LITTLE processors"
12 depends on ARCH_VEXPRESS_TC2_PM 12 depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS
13 select ARM_CPU_SUSPEND 13 select ARM_CPU_SUSPEND
14 select CPU_IDLE_MULTIPLE_DRIVERS 14 select CPU_IDLE_MULTIPLE_DRIVERS
15 help 15 help
diff --git a/drivers/cpuidle/cpuidle-big_little.c b/drivers/cpuidle/cpuidle-big_little.c
index b45fc6249041..344d79fa3407 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -163,14 +163,24 @@ static int __init bl_idle_driver_init(struct cpuidle_driver *drv, int cpu_id)
163 return 0; 163 return 0;
164} 164}
165 165
166static const struct of_device_id compatible_machine_match[] = {
167 { .compatible = "arm,vexpress,v2p-ca15_a7" },
168 { .compatible = "samsung,exynos5420" },
169 {},
170};
171
166static int __init bl_idle_init(void) 172static int __init bl_idle_init(void)
167{ 173{
168 int ret; 174 int ret;
175 struct device_node *root = of_find_node_by_path("/");
176
177 if (!root)
178 return -ENODEV;
169 179
170 /* 180 /*
171 * Initialize the driver just for a compliant set of machines 181 * Initialize the driver just for a compliant set of machines
172 */ 182 */
173 if (!of_machine_is_compatible("arm,vexpress,v2p-ca15_a7")) 183 if (!of_match_node(compatible_machine_match, root))
174 return -ENODEV; 184 return -ENODEV;
175 /* 185 /*
176 * For now the differentiation between little and big cores 186 * For now the differentiation between little and big cores
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-18 11:22:32 -0500