15 files changed, 722 insertions, 746 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 84449dd8f031..63f40b43b062 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -446,6 +446,7 @@ config ARCH_MXC
         select CLKSRC_MMIO
         select GENERIC_IRQ_CHIP
         select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
         help
           Support for Freescale MXC/iMX-based family of processors
 
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index fd9efb044656..d73f5e8ea9cb 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -11,50 +11,6 @@
 #ifndef __ASM_ARCH_MXC_IRQS_H__
 #define __ASM_ARCH_MXC_IRQS_H__
 
-#include <asm-generic/gpio.h>
-
-/*
- * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC
- * have 128 IRQs, and those with AVIC have 64.
- *
- * To support single image, the biggest number should be defined on
- * top of the list.
- */
-#if defined CONFIG_ARM_GIC
-#define MXC_INTERNAL_IRQS       160
-#elif defined CONFIG_MXC_TZIC
-#define MXC_INTERNAL_IRQS       128
-#else
-#define MXC_INTERNAL_IRQS       64
-#endif
-
-#define MXC_GPIO_IRQ_START      MXC_INTERNAL_IRQS
-
-/*
- * The next 16 interrupts are for board specific purposes.  Since
- * the kernel can only run on one machine at a time, we can re-use
- * these.  If you need more, increase MXC_BOARD_IRQS, but keep it
- * within sensible limits.
- */
-#define MXC_BOARD_IRQ_START     (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS)
-
-#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
-#define MXC_BOARD_IRQS  80
-#else
-#define MXC_BOARD_IRQS  16
-#endif
-
-#define MXC_IPU_IRQ_START       (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
-
-#ifdef CONFIG_MX3_IPU_IRQS
-#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
-#else
-#define MX3_IPU_IRQS 0
-#endif
-/* REVISIT: Add IPU irqs on IMX51 */
-
-#define NR_IRQS                 (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
-
 extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
 
 /* all normal IRQs can be FIQs */
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 2b7c08d13e89..45bd31cc34d6 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -78,61 +78,62 @@
 #define MX1_IO_ADDRESS(x)               IOMEM(MX1_IO_P2V(x))
 
 /* fixed interrput numbers */
-#define MX1_INT_SOFTINT         0
-#define MX1_INT_CSI             6
-#define MX1_DSPA_MAC_INT        7
-#define MX1_DSPA_INT            8
-#define MX1_COMP_INT            9
-#define MX1_MSHC_XINT           10
-#define MX1_GPIO_INT_PORTA      11
-#define MX1_GPIO_INT_PORTB      12
-#define MX1_GPIO_INT_PORTC      13
-#define MX1_INT_LCDC            14
-#define MX1_SIM_INT             15
-#define MX1_SIM_DATA_INT        16
-#define MX1_RTC_INT             17
-#define MX1_RTC_SAMINT          18
-#define MX1_INT_UART2PFERR      19
-#define MX1_INT_UART2RTS        20
-#define MX1_INT_UART2DTR        21
-#define MX1_INT_UART2UARTC      22
-#define MX1_INT_UART2TX         23
-#define MX1_INT_UART2RX         24
-#define MX1_INT_UART1PFERR      25
-#define MX1_INT_UART1RTS        26
-#define MX1_INT_UART1DTR        27
-#define MX1_INT_UART1UARTC      28
-#define MX1_INT_UART1TX         29
-#define MX1_INT_UART1RX         30
-#define MX1_VOICE_DAC_INT       31
-#define MX1_VOICE_ADC_INT       32
-#define MX1_PEN_DATA_INT        33
-#define MX1_PWM_INT             34
-#define MX1_SDHC_INT            35
-#define MX1_INT_I2C             39
-#define MX1_INT_CSPI2           40
-#define MX1_INT_CSPI1           41
-#define MX1_SSI_TX_INT          42
-#define MX1_SSI_TX_ERR_INT      43
-#define MX1_SSI_RX_INT          44
-#define MX1_SSI_RX_ERR_INT      45
-#define MX1_TOUCH_INT           46
-#define MX1_INT_USBD0           47
-#define MX1_INT_USBD1           48
-#define MX1_INT_USBD2           49
-#define MX1_INT_USBD3           50
-#define MX1_INT_USBD4           51
-#define MX1_INT_USBD5           52
-#define MX1_INT_USBD6           53
-#define MX1_BTSYS_INT           55
-#define MX1_BTTIM_INT           56
-#define MX1_BTWUI_INT           57
-#define MX1_TIM2_INT            58
-#define MX1_TIM1_INT            59
-#define MX1_DMA_ERR             60
-#define MX1_DMA_INT             61
-#define MX1_GPIO_INT_PORTD      62
-#define MX1_WDT_INT             63
+#include <asm/irq.h>
+#define MX1_INT_SOFTINT         (NR_IRQS_LEGACY + 0)
+#define MX1_INT_CSI             (NR_IRQS_LEGACY + 6)
+#define MX1_DSPA_MAC_INT        (NR_IRQS_LEGACY + 7)
+#define MX1_DSPA_INT            (NR_IRQS_LEGACY + 8)
+#define MX1_COMP_INT            (NR_IRQS_LEGACY + 9)
+#define MX1_MSHC_XINT           (NR_IRQS_LEGACY + 10)
+#define MX1_GPIO_INT_PORTA      (NR_IRQS_LEGACY + 11)
+#define MX1_GPIO_INT_PORTB      (NR_IRQS_LEGACY + 12)
+#define MX1_GPIO_INT_PORTC      (NR_IRQS_LEGACY + 13)
+#define MX1_INT_LCDC            (NR_IRQS_LEGACY + 14)
+#define MX1_SIM_INT             (NR_IRQS_LEGACY + 15)
+#define MX1_SIM_DATA_INT        (NR_IRQS_LEGACY + 16)
+#define MX1_RTC_INT             (NR_IRQS_LEGACY + 17)
+#define MX1_RTC_SAMINT          (NR_IRQS_LEGACY + 18)
+#define MX1_INT_UART2PFERR      (NR_IRQS_LEGACY + 19)
+#define MX1_INT_UART2RTS        (NR_IRQS_LEGACY + 20)
+#define MX1_INT_UART2DTR        (NR_IRQS_LEGACY + 21)
+#define MX1_INT_UART2UARTC      (NR_IRQS_LEGACY + 22)
+#define MX1_INT_UART2TX         (NR_IRQS_LEGACY + 23)
+#define MX1_INT_UART2RX         (NR_IRQS_LEGACY + 24)
+#define MX1_INT_UART1PFERR      (NR_IRQS_LEGACY + 25)
+#define MX1_INT_UART1RTS        (NR_IRQS_LEGACY + 26)
+#define MX1_INT_UART1DTR        (NR_IRQS_LEGACY + 27)
+#define MX1_INT_UART1UARTC      (NR_IRQS_LEGACY + 28)
+#define MX1_INT_UART1TX         (NR_IRQS_LEGACY + 29)
+#define MX1_INT_UART1RX         (NR_IRQS_LEGACY + 30)
+#define MX1_VOICE_DAC_INT       (NR_IRQS_LEGACY + 31)
+#define MX1_VOICE_ADC_INT       (NR_IRQS_LEGACY + 32)
+#define MX1_PEN_DATA_INT        (NR_IRQS_LEGACY + 33)
+#define MX1_PWM_INT             (NR_IRQS_LEGACY + 34)
+#define MX1_SDHC_INT            (NR_IRQS_LEGACY + 35)
+#define MX1_INT_I2C             (NR_IRQS_LEGACY + 39)
+#define MX1_INT_CSPI2           (NR_IRQS_LEGACY + 40)
+#define MX1_INT_CSPI1           (NR_IRQS_LEGACY + 41)
+#define MX1_SSI_TX_INT          (NR_IRQS_LEGACY + 42)
+#define MX1_SSI_TX_ERR_INT      (NR_IRQS_LEGACY + 43)
+#define MX1_SSI_RX_INT          (NR_IRQS_LEGACY + 44)
+#define MX1_SSI_RX_ERR_INT      (NR_IRQS_LEGACY + 45)
+#define MX1_TOUCH_INT           (NR_IRQS_LEGACY + 46)
+#define MX1_INT_USBD0           (NR_IRQS_LEGACY + 47)
+#define MX1_INT_USBD1           (NR_IRQS_LEGACY + 48)
+#define MX1_INT_USBD2           (NR_IRQS_LEGACY + 49)
+#define MX1_INT_USBD3           (NR_IRQS_LEGACY + 50)
+#define MX1_INT_USBD4           (NR_IRQS_LEGACY + 51)
+#define MX1_INT_USBD5           (NR_IRQS_LEGACY + 52)
+#define MX1_INT_USBD6           (NR_IRQS_LEGACY + 53)
+#define MX1_BTSYS_INT           (NR_IRQS_LEGACY + 55)
+#define MX1_BTTIM_INT           (NR_IRQS_LEGACY + 56)
+#define MX1_BTWUI_INT           (NR_IRQS_LEGACY + 57)
+#define MX1_TIM2_INT            (NR_IRQS_LEGACY + 58)
+#define MX1_TIM1_INT            (NR_IRQS_LEGACY + 59)
+#define MX1_DMA_ERR             (NR_IRQS_LEGACY + 60)
+#define MX1_DMA_INT             (NR_IRQS_LEGACY + 61)
+#define MX1_GPIO_INT_PORTD      (NR_IRQS_LEGACY + 62)
+#define MX1_WDT_INT             (NR_IRQS_LEGACY + 63)
 
 /* DMA */
 #define MX1_DMA_REQ_UART3_T             2
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 6cd049ebbd8d..468738aa997f 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -99,59 +99,60 @@