2 files changed, 6 insertions, 0 deletions

diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index 83c4e384b16d..1aeae38725dd 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -100,6 +100,7 @@ ENTRY(vfp_support_entry)
         beq     no_old_VFP_process
         VFPFSTMIA r4, r5                @ save the working registers
         VFPFMRX r5, FPSCR               @ current status
+#ifndef CONFIG_CPU_FEROCEON
         tst     r1, #FPEXC_EX           @ is there additional state to save?
         beq     1f
         VFPFMRX r6, FPINST              @ FPINST (only if FPEXC.EX is set)
@@ -107,6 +108,7 @@ ENTRY(vfp_support_entry)
         beq     1f
         VFPFMRX r8, FPINST2             @ FPINST2 if needed (and present)
 1:
+#endif
         stmia   r4, {r1, r5, r6, r8}    @ save FPEXC, FPSCR, FPINST, FPINST2
                                         @ and point r4 at the word at the
                                         @ start of the register dump
@@ -119,6 +121,7 @@ no_old_VFP_process:
         VFPFLDMIA r10, r5               @ reload the working registers while
                                         @ FPEXC is in a safe state
         ldmia   r10, {r1, r5, r6, r8}   @ load FPEXC, FPSCR, FPINST, FPINST2
+#ifndef CONFIG_CPU_FEROCEON
         tst     r1, #FPEXC_EX           @ is there additional state to restore?
         beq     1f
         VFPFMXR FPINST, r6              @ restore FPINST (only if FPEXC.EX is set)
@@ -126,6 +129,7 @@ no_old_VFP_process:
         beq     1f
         VFPFMXR FPINST2, r8             @ FPINST2 if needed (and present)
 1:
+#endif
         VFPFMXR FPSCR, r5               @ restore status
 
 check_for_exception:
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 01599c4ef726..2d7423af1197 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -253,12 +253,14 @@ void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
         }
 
         if (fpexc & FPEXC_EX) {
+#ifndef CONFIG_CPU_FEROCEON
                 /*
                  * Asynchronous exception. The instruction is read from FPINST
                  * and the interrupted instruction has to be restarted.
                  */
                 trigger = fmrx(FPINST);
                 regs->ARM_pc -= 4;
+#endif
         } else if (!(fpexc & FPEXC_DEX)) {
                 /*
                  * Illegal combination of bits. It can be caused by an