495 files changed, 44831 insertions, 9936 deletions

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 795c487af8e4..b3a5aad7e629 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -1242,6 +1242,11 @@ and is between 256 and 4096 characters. It is defined in the file
         mtdparts=       [MTD]
                         See drivers/mtd/cmdlinepart.c.
 
+        mtdset=         [ARM]
+                        ARM/S3C2412 JIVE boot control
+
+                        See arch/arm/mach-s3c2412/mach-jive.c
+
         mtouchusb.raw_coordinates=
                         [HW] Make the MicroTouch USB driver use raw coordinates
                         ('y', default) or cooked coordinates ('n')
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3845e5c8a34f..258f1369fb0c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -24,6 +24,9 @@ config ARM
           Europe.  There is an ARM Linux project with a web page at
           <http://www.arm.linux.org.uk/>.
 
+config HAVE_PWM
+        bool
+
 config SYS_SUPPORTS_APM_EMULATION
         bool
 
@@ -86,6 +89,11 @@ config STACKTRACE_SUPPORT
         bool
         default y
 
+config HAVE_LATENCYTOP_SUPPORT
+        bool
+        depends on !SMP
+        default y
+
 config LOCKDEP_SUPPORT
         bool
         default y
@@ -149,6 +157,10 @@ config FIQ
 config ARCH_MTD_XIP
         bool
 
+config GENERIC_HARDIRQS_NO__DO_IRQ
+        bool
+        def_bool y
+
 if OPROFILE
 
 config OPROFILE_ARMV6
@@ -234,13 +246,6 @@ config ARCH_CLPS711X
         help
           Support for Cirrus Logic 711x/721x based boards.
 
-config ARCH_CO285
-        bool "Co-EBSA285"
-        select FOOTBRIDGE
-        select FOOTBRIDGE_ADDIN
-        help
-          Support for Intel's EBSA285 companion chip.
-
 config ARCH_EBSA110
         bool "EBSA-110"
         select ISA
@@ -301,6 +306,8 @@ config ARCH_IOP32X
         depends on MMU
         select PLAT_IOP
         select PCI
+        select GENERIC_GPIO
+        select HAVE_GPIO_LIB
         help
           Support for Intel's 80219 and IOP32X (XScale) family of
           processors.
@@ -310,6 +317,8 @@ config ARCH_IOP33X
         depends on MMU
         select PLAT_IOP
         select PCI
+        select GENERIC_GPIO
+        select HAVE_GPIO_LIB
         help
           Support for Intel's IOP33X (XScale) family of processors.
 
@@ -349,6 +358,16 @@ config ARCH_L7200
           If you have any questions or comments about the Linux kernel port
           to this board, send e-mail to <sjhill@cotw.com>.
 
+config ARCH_KIRKWOOD
+        bool "Marvell Kirkwood"
+        select PCI
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select PLAT_ORION
+        help
+          Support for the following Marvell Kirkwood series SoCs:
+          88F6180, 88F6192 and 88F6281.
+
 config ARCH_KS8695
         bool "Micrel/Kendin KS8695"
         select GENERIC_GPIO
@@ -367,9 +386,31 @@ config ARCH_NS9XXX
 
           <http://www.digi.com/products/microprocessors/index.jsp>
 
+config ARCH_LOKI
+        bool "Marvell Loki (88RC8480)"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select PLAT_ORION
+        help
+          Support for the Marvell Loki (88RC8480) SoC.
+
+config ARCH_MV78XX0
+        bool "Marvell MV78xx0"
+        select PCI
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select PLAT_ORION
+        help
+          Support for the following Marvell MV78xx0 series SoCs:
+          MV781x0, MV782x0.
+
 config ARCH_MXC
         bool "Freescale MXC/iMX-based"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
         select ARCH_MTD_XIP
+        select GENERIC_GPIO
+        select HAVE_GPIO_LIB
         help
           Support for Freescale MXC/iMX-based family of processors
 
@@ -383,7 +424,8 @@ config ARCH_ORION5X
         select PLAT_ORION
         help
           Support for the following Marvell Orion 5x series SoCs:
-          Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.)
+          Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
+          Orion-2 (5281).
 
 config ARCH_PNX4008
         bool "Philips Nexperia PNX4008 Mobile"
@@ -408,6 +450,7 @@ config ARCH_RPC
         select FIQ
         select TIMER_ACORN
         select ARCH_MAY_HAVE_PC_FDC
+        select HAVE_PATA_PLATFORM
         select ISA_DMA_API
         select NO_IOPORT
         help
@@ -504,6 +547,10 @@ source "arch/arm/mach-ixp2000/Kconfig"
 
 source "arch/arm/mach-ixp23xx/Kconfig"
 
+source "arch/arm/mach-loki/Kconfig"
+
+source "arch/arm/mach-mv78xx0/Kconfig"
+
 source "arch/arm/mach-pxa/Kconfig"
 
 source "arch/arm/mach-sa1100/Kconfig"
@@ -516,6 +563,8 @@ source "arch/arm/mach-omap2/Kconfig"
 
 source "arch/arm/mach-orion5x/Kconfig"
 
+source "arch/arm/mach-kirkwood/Kconfig"
+
 source "arch/arm/plat-s3c24xx/Kconfig"
 source "arch/arm/plat-s3c/Kconfig"
 
@@ -705,27 +754,6 @@ config PREEMPT
           Say Y here if you are building a kernel for a desktop, embedded
           or real-time system.  Say N if you are unsure.
 
-config NO_IDLE_HZ
-        bool "Dynamic tick timer"
-        depends on !GENERIC_CLOCKEVENTS
-        help
-          Select this option if you want to disable continuous timer ticks
-          and have them programmed to occur as required. This option saves
-          power as the system can remain in idle state for longer.
-
-          By default dynamic tick is disabled during the boot, and can be
-          manually enabled with:
-
-            echo 1 > /sys/devices/system/timer/timer0/dyn_tick
-
-          Alternatively, if you want dynamic tick automatically enabled
-          during boot, pass "dyntick=enable" via the kernel command string.
-
-          Please note that dynamic tick may affect the accuracy of
-          timekeeping on some platforms depending on the implementation.
-          Currently at least OMAP, PXA2xx and SA11x0 platforms are known
-          to have accurate timekeeping with dynamic tick.
-
 config HZ
         int
         default 128 if ARCH_L7200
@@ -791,7 +819,7 @@ source "mm/Kconfig"
 
 config LEDS
         bool "Timer and CPU usage LEDs"
-        depends on ARCH_CDB89712 || ARCH_CO285 || ARCH_EBSA110 || \
+        depends on ARCH_CDB89712 || ARCH_EBSA110 || \
                    ARCH_EBSA285 || ARCH_IMX || ARCH_INTEGRATOR || \
                    ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
                    ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index e72db27e0ba0..b20995a82e04 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -100,8 +100,6 @@ textofs-y	:= 0x00008000
   incdir-$(CONFIG_ARCH_CLPS7500)   := cl7500
  machine-$(CONFIG_FOOTBRIDGE)      := footbridge
   incdir-$(CONFIG_FOOTBRIDGE)      := ebsa285
- machine-$(CONFIG_ARCH_CO285)      := footbridge
-  incdir-$(CONFIG_ARCH_CO285)      := ebsa285
  machine-$(CONFIG_ARCH_SHARK)      := shark
  machine-$(CONFIG_ARCH_SA1100)     := sa1100
 ifeq ($(CONFIG_ARCH_SA1100),y)
@@ -135,11 +133,15 @@ endif
  machine-$(CONFIG_ARCH_NETX)       := netx
  machine-$(CONFIG_ARCH_NS9XXX)     := ns9xxx
  machine-$(CONFIG_ARCH_DAVINCI)    := davinci
+ machine-$(CONFIG_ARCH_KIRKWOOD)   := kirkwood
  machine-$(CONFIG_ARCH_KS8695)     := ks8695
   incdir-$(CONFIG_ARCH_MXC)        := mxc
+ machine-$(CONFIG_ARCH_MX2)        := mx2
  machine-$(CONFIG_ARCH_MX3)        := mx3
  machine-$(CONFIG_ARCH_ORION5X)    := orion5x
  machine-$(CONFIG_ARCH_MSM7X00A)   := msm
+ machine-$(CONFIG_ARCH_LOKI)       := loki
+ machine-$(CONFIG_ARCH_MV78XX0)    := mv78xx0
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 # This is what happens if you forget the IOCS16 line.
@@ -190,8 +192,6 @@ core-$(CONFIG_PLAT_S3C24XX)		+= arch/arm/plat-s3c24xx/
 core-$(CONFIG_ARCH_MXC)         += arch/arm/plat-mxc/
 
 drivers-$(CONFIG_OPROFILE)      += arch/arm/oprofile/
-drivers-$(CONFIG_ARCH_CLPS7500) += drivers/acorn/char/
-drivers-$(CONFIG_ARCH_L7200)    += drivers/acorn/char/
 
 libs-y                          := arch/arm/lib/ $(libs-y)
 
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 3c2c8f2a1dc4..de41daeab5e9 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -623,8 +623,8 @@ proc_types:
                 b       __armv4_mmu_cache_off
                 b       __armv4_mmu_cache_flush
 
-                .word   0x56055310              @ Feroceon
-                .word   0xfffffff0
+                .word   0x56050000              @ Feroceon
+                .word   0xff0f0000
                 b       __armv4_mmu_cache_on
                 b       __armv4_mmu_cache_off
                 b       __armv5tej_mmu_cache_flush
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 3d0b9fa42f84..325e4b6a6afb 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -2,7 +2,6 @@
 # Makefile for the linux kernel.
 #
 
-obj-y                           += rtctime.o
 obj-$(CONFIG_ARM_GIC)           += gic.o
 obj-$(CONFIG_ARM_VIC)           += vic.o
 obj-$(CONFIG_ICST525)           += icst525.o
diff --git a/arch/arm/common/rtctime.c b/arch/arm/common/rtctime.c
deleted file mode 100644
index aa8f7739c822..000000000000
--- a/arch/arm/common/rtctime.c
+++ /dev/null
@@ -1,434 +0,0 @@
-/*
- *  linux/arch/arm/common/rtctime.c
- *
- *  Copyright (C) 2003 Deep Blue Solutions Ltd.
- *  Based on sa1100-rtc.c, Nils Faerber, CIH, Nicolas Pitre.
- *  Based on rtc.c by Paul Gortmaker
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/time.h>
-#include <linux/rtc.h>
-#include <linux/poll.h>
-#include <linux/proc_fs.h>
-#include <linux/miscdevice.h>
-#include <linux/spinlock.h>
-#include <linux/capability.h>
-#include <linux/device.h>
-#include <linux/mutex.h>
-
-#include <asm/rtc.h>
-
-static DECLARE_WAIT_QUEUE_HEAD(rtc_wait);
-static struct fasync_struct *rtc_async_queue;
-
-/*
- * rtc_lock protects rtc_irq_data
- */
-static DEFINE_SPINLOCK(rtc_lock);
-static unsigned long rtc_irq_data;
-
-/*
- * rtc_sem protects rtc_inuse and rtc_ops
- */
-static DEFINE_MUTEX(rtc_mutex);
-static unsigned long rtc_inuse;
-static struct rtc_ops *rtc_ops;
-
-#define rtc_epoch 1900UL
-
-/*
- * Calculate the next alarm time given the requested alarm time mask
- * and the current time.
- */
-void rtc_next_alarm_time(struct rtc_time *next, struct rtc_time *now, struct rtc_time *alrm)
-{
-        unsigned long next_time;
-        unsigned long now_time;
-
-        next->tm_year = now->tm_year;
-        next->tm_mon = now->tm_mon;
-        next->tm_mday = now->tm_mday;
-        next->tm_hour = alrm->tm_hour;
-        next->tm_min = alrm->tm_min;
-        next->tm_sec = alrm->tm_sec;
-
-        rtc_tm_to_time(now, &now_time);
-        rtc_tm_to_time(next, &next_time);
-
-        if (next_time < now_time) {
-                /* Advance one day */
-                next_time += 60 * 60 * 24;
-                rtc_time_to_tm(next_time, next);
-        }
-}
-EXPORT_SYMBOL(rtc_next_alarm_time);
-
-static inline int rtc_arm_read_time(struct rtc_ops *ops, struct rtc_time *tm)
-{
-        memset(tm, 0, sizeof(struct rtc_time));
-        return ops->read_time(tm);
-}
-
-static inline int rtc_arm_set_time(struct rtc_ops *ops, struct rtc_time *tm)
-{
-        int ret;
-
-        ret = rtc_valid_tm(tm);
-        if (ret == 0)
-                ret = ops->set_time(tm);
-
-        return ret;
-}
-
-static inline int rtc_arm_read_alarm(struct rtc_ops *ops, struct rtc_wkalrm *alrm)
-{
-        int ret = -EINVAL;
-        if (ops->read_alarm) {
-                memset(alrm, 0, sizeof(struct rtc_wkalrm));
-                ret = ops->read_alarm(alrm);
-        }
-        return ret;
-}
-
-static inline int rtc_arm_set_alarm(struct rtc_ops *ops, struct rtc_wkalrm *alrm)
-{
-        int ret = -EINVAL;
-        if (ops->set_alarm)
-                ret = ops->set_alarm(alrm);
-        return ret;
-}
-
-void rtc_update(unsigned long num, unsigned long events)
-{
-        spin_lock(&rtc_lock);
-        rtc_irq_data = (rtc_irq_data + (num << 8)) | events;
-        spin_unlock(&rtc_lock);
-
-        wake_up_interruptible(&rtc_wait);
-        kill_fasync(&rtc_async_queue, SIGIO, POLL_IN);
-}
-EXPORT_SYMBOL(rtc_update);
-
-
-static ssize_t
-rtc_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
-{
-        DECLARE_WAITQUEUE(wait, current);
-        unsigned long data;
-        ssize_t ret;
-
-        if (count < sizeof(unsigned long))
-                return -EINVAL;
-
-        add_wait_queue(&rtc_wait, &wait);
-        do {
-                __set_current_state(TASK_INTERRUPTIBLE);
-
-                spin_lock_irq(&rtc_lock);
-                data = rtc_irq_data;
-                rtc_irq_data = 0;
-                spin_unlock_irq(&rtc_lock);
-
-                if (data != 0) {
-                        ret = 0;
-                        break;
-                }
-                if (file->f_flags & O_NONBLOCK) {
-                        ret = -EAGAIN;
-                        break;
-                }
-                if (signal_pending(current)) {
-                        ret = -ERESTARTSYS;
-                        break;
-                }
-                schedule();
-        } while (1);
-        set_current_state(TASK_RUNNING);
-        remove_wait_queue(&rtc_wait, &wait);
-
-        if (ret == 0) {
-                ret = put_user(data, (unsigned long __user *)buf);
-                if (ret == 0)
-                        ret = sizeof(unsigned long);
-        }
-        return ret;
-}
-
-static unsigned int rtc_poll(struct file *file, poll_table *wait)
-{
-        unsigned long data;
-
-        poll_wait(file, &rtc_wait, wait);
-
-        spin_lock_irq(&rtc_lock);
-        data = rtc_irq_data;
-        spin_unlock_irq(&rtc_lock);
-
-        return data != 0 ? POLLIN | POLLRDNORM : 0;
-}
-
-static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
-                     unsigned long arg)
-{
-        struct rtc_ops *ops = file->private_data;
-        struct rtc_time tm;
-        struct rtc_wkalrm alrm;
-        void __user *uarg = (void __user *)arg;
-        int ret = -EINVAL;
-
-        switch (cmd) {
-        case RTC_ALM_READ:
-                ret = rtc_arm_read_alarm(ops, &alrm);
-                if (ret)
-                        break;
-                ret = copy_to_user(uarg, &alrm.time, sizeof(tm));
-                if (ret)
-                        ret = -EFAULT;
-                break;
-
-        case RTC_ALM_SET:
-                ret = copy_from_user(&alrm.time, uarg, sizeof(tm));
-                if (ret) {
-                        ret = -EFAULT;
-                        break;
-                }
-                alrm.enabled = 0;
-                alrm.pending = 0;
-                alrm.time.tm_mday = -1;
-                alrm.time.tm_mon = -1;
-                alrm.time.tm_year = -1;
-                alrm.time.tm_wday = -1;
-                alrm.time.tm_yday = -1;
-                alrm.time.tm_isdst = -1;
-                ret = rtc_arm_set_alarm(ops, &alrm);
-                break;
-
-        case RTC_RD_TIME:
-                ret = rtc_arm_read_time(ops, &tm);
-                if (ret)
-                        break;
-                ret = copy_to_user(uarg, &tm, sizeof(tm));
-                if (ret)
-                        ret = -EFAULT;
-                break;
-
-        case RTC_SET_TIME:
-                if (!capable(CAP_SYS_TIME)) {
-                        ret = -EACCES;
-                        break;
-                }
-                ret = copy_from_user(&tm, uarg, sizeof(tm));
-                if (ret) {
-                        ret = -EFAULT;
-                        break;
-                }
-                ret = rtc_arm_set_time(ops, &tm);
-                break;
-
-        case RTC_EPOCH_SET:
-#ifndef rtc_epoch
-                /*
-                 * There were no RTC clocks before 1900.
-                 */
-                if (arg < 1900) {
-                        ret = -EINVAL;
-                        break;
-                }
-                if (!capable(CAP_SYS_TIME)) {
-                        ret = -EACCES;
-                        break;
-                }
-                rtc_epoch = arg;
-                ret = 0;
-#endif
-                break;
-
-        case RTC_EPOCH_READ:
-                ret = put_user(rtc_epoch, (unsigned long __user *)uarg);
-                break;
-
-        case RTC_WKALM_SET:
-                ret = copy_from_user(&alrm, uarg, sizeof(alrm));
-                if (ret) {
-                        ret = -EFAULT;
-                        break;
-                }
-                ret = rtc_arm_set_alarm(ops, &alrm);
-                break;
-
-        case RTC_WKALM_RD:
-                ret = rtc_arm_read_alarm(ops, &alrm);
-                if (ret)
-                        break;
-                ret = copy_to_user(uarg, &alrm, sizeof(alrm));
-                if (ret)
-                        ret = -EFAULT;
-                break;
-
-        default:
-                if (ops->ioctl)
-                        ret = ops->ioctl(cmd, arg);
-                break;
-        }
-        return ret;
-}
-
-static int rtc_open(struct inode *inode, struct file *file)
-{
-        int ret;
-
-        mutex_lock(&rtc_mutex);
-
-        if (rtc_inuse) {
-                ret = -EBUSY;
-        } else if (!rtc_ops || !try_module_get(rtc_ops->owner)) {
-                ret = -ENODEV;
-        } else {
-                file->private_data = rtc_ops;
-
-                ret = rtc_ops->open ? rtc_ops->open() : 0;
-                if (ret == 0) {
-                        spin_lock_irq(&rtc_lock);
-                        rtc_irq_data = 0;
-                        spin_unlock_irq(&rtc_lock);
-
-                        rtc_inuse = 1;
-                }
-        }
-        mutex_unlock(&rtc_mutex);
-
-        return ret;
-}
-
-static int rtc_release(struct inode *inode, struct file *file)
-{
-        struct rtc_ops *ops = file->private_data;
-
-        if (ops->release)
-                ops->release();
-
-        spin_lock_irq(&rtc_lock);
-        rtc_irq_data = 0;
-        spin_unlock_irq(&rtc_lock);
-
-        module_put(rtc_ops->owner);
-        rtc_inuse = 0;
-
-        return 0;
-}
-
-static int rtc_fasync(int fd, struct file *file, int on)
-{
-        return fasync_helper(fd, file, on, &rtc_async_queue);
-}
-
-static const struct file_operations rtc_fops = {
-        .owner          = THIS_MODULE,
-        .llseek         = no_llseek,
-        .read           = rtc_read,
-        .poll           = rtc_poll,
-        .ioctl          = rtc_ioctl,
-        .open           = rtc_open,
-        .release        = rtc_release,
-        .fasync         = rtc_fasync,
-};
-
-static struct miscdevice rtc_miscdev = {
-        .minor          = RTC_MINOR,
-        .name           = "rtc",
-        .fops           = &rtc_fops,
-};
-
-
-static int rtc_read_proc(char *page, char **start, off_t off, int count, int *eof, void *data)
-{
-        struct rtc_ops *ops = data;
-        struct rtc_wkalrm alrm;
-        struct rtc_time tm;
-        char *p = page;
-
-        if (rtc_arm_read_time(ops, &tm) == 0) {
-                p += sprintf(p,
-                        "rtc_time\t: %02d:%02d:%02d\n"
-                        "rtc_date\t: %04d-%02d-%02d\n"
-                        "rtc_epoch\t: %04lu\n",
-                        tm.tm_hour, tm.tm_min, tm.tm_sec,
-                        tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
-                        rtc_epoch);
-        }
-
-        if (rtc_arm_read_alarm(ops, &alrm) == 0) {
-                p += sprintf(p, "alrm_time\t: ");
-                if ((unsigned int)alrm.time.tm_hour <= 24)
-                        p += sprintf(p, "%02d:", alrm.time.tm_hour);
-                else
-                        p += sprintf(p, "**:");
-                if ((unsigned int)alrm.time.tm_min <= 59)
-                        p += sprintf(p, "%02d:", alrm.time.tm_min);
-                else
-                        p += sprintf(p, "**:");
-                if ((unsigned int)alrm.time.tm_sec <= 59)
-                        p += sprintf(p, "%02d\n", alrm.time.tm_sec);
-                else
-                        p += sprintf(p, "**\n");
-
-                p += sprintf(p, "alrm_date\t: ");
-                if ((unsigned int)alrm.time.tm_year <= 200)
-                        p += sprintf(p, "%04d-", alrm.time.tm_year + 1900);
-                else
-                        p += sprintf(p, "****-");
-                if ((unsigned int)alrm.time.tm_mon <= 11)
-                        p += sprintf(p, "%02d-", alrm.time.tm_mon + 1);
-                else
-                        p += sprintf(p, "**-");
-                if ((unsigned int)alrm.time.tm_mday <= 31)
-                        p += sprintf(p, "%02d\n", alrm.time.tm_mday);
-                else
-                        p += sprintf(p, "**\n");
-                p += sprintf(p, "alrm_wakeup\t: %s\n",
-                             alrm.enabled ? "yes" : "no");
-                p += sprintf(p, "alrm_pending\t: %s\n",
-                             alrm.pending ? "yes" : "no");
-        }
-
-        if (ops->proc)
-                p += ops->proc(p);
-
-        return p - page;
-}
-
-int register_rtc(struct rtc_ops *ops)
-{
-        int ret = -EBUSY;
-
-        mutex_lock(&rtc_mutex);
-        if (rtc_ops == NULL) {
-                rtc_ops = ops;
-
-                ret = misc_register(&rtc_miscdev);
-                if (ret == 0)
-                        create_proc_read_entry("driver/rtc", 0, NULL,
-                                               rtc_read_proc, ops);
-        }
-        mutex_unlock(&rtc_mutex);
-
-        return ret;
-}
-EXPORT_SYMBOL(register_rtc);
-
-void unregister_rtc(struct rtc_ops *rtc)
-{
-        mutex_lock(&rtc_mutex);
-        if (rtc == rtc_ops) {
-                remove_proc_entry("driver/rtc", NULL);
-                misc_deregister(&rtc_miscdev);
-                rtc_ops = NULL;
-        }
-        mutex_unlock(&rtc_mutex);
-}
-EXPORT_SYMBOL(unregister_rtc);
diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c
index 5bba5255b119..8822b684d474 100644
--- a/arch/arm/common/sharpsl_pm.c
+++ b/arch/arm/common/sharpsl_pm.c
@@ -31,6 +31,7 @@
 #include <asm/irq.h>
 #include <asm/arch/pm.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/sharpsl.h>
 #include <asm/hardware/sharpsl_pm.h>
 
@@ -157,6 +158,7 @@ static void sharpsl_battery_thread(struct work_struct *private_)
         dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage,
                         sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies);
 
+#ifdef CONFIG_BACKLIGHT_CORGI
         /* If battery is low. limit backlight intensity to save power. */
         if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
                         && ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW) ||
@@ -169,6 +171,7 @@ static void sharpsl_battery_thread(struct work_struct *private_)
                 sharpsl_pm.machinfo->backlight_limit(0);
                 sharpsl_pm.flags &= ~SHARPSL_BL_LIMIT;
         }
+#endif
 
         /* Suspend if critical battery level */
         if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
diff --git a/arch/arm/configs/at91cap9adk_defconfig b/arch/arm/configs/at91cap9adk_defconfig
index e32e73648129..be2b2f38fd94 100644
--- a/arch/arm/configs/at91cap9adk_defconfig
+++ b/arch/arm/configs/at91cap9adk_defconfig
@@ -213,7 +213,6 @@ CONFIG_CPU_CP15_MMU=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
@@ -907,7 +906,32 @@ CONFIG_USB_MON=y
 #
 # USB Gadget Support
 #
-# CONFIG_USB_GADGET is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_USB_ATMEL_USBA=y
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
@@ -926,7 +950,59 @@ CONFIG_MMC_AT91=y
 # CONFIG_MMC_SPI is not set
 # CONFIG_NEW_LEDS is not set
 CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91SAM9=y
+CONFIG_RTC_DRV_AT91SAM9_RTT=0
+CONFIG_RTC_DRV_AT91SAM9_GPBR=0
 
 #
 # File systems
diff --git a/arch/arm/configs/at91rm9200dk_defconfig b/arch/arm/configs/at91rm9200dk_defconfig
index 2dbbbc3d4ac3..868fb7b9530b 100644
--- a/arch/arm/configs/at91rm9200dk_defconfig
+++ b/arch/arm/configs/at91rm9200dk_defconfig
@@ -169,7 +169,6 @@ CONFIG_AT91_CF=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
diff --git a/arch/arm/configs/at91rm9200ek_defconfig b/arch/arm/configs/at91rm9200ek_defconfig
index 6e994f7820c6..de43fc675616 100644
--- a/arch/arm/configs/at91rm9200ek_defconfig
+++ b/arch/arm/configs/at91rm9200ek_defconfig
@@ -160,7 +160,6 @@ CONFIG_ISA_DMA_API=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
diff --git a/arch/arm/configs/at91sam9260ek_defconfig b/arch/arm/configs/at91sam9260ek_defconfig
index f659c938473f..2011adfa6758 100644
--- a/arch/arm/configs/at91sam9260ek_defconfig
+++ b/arch/arm/configs/at91sam9260ek_defconfig
@@ -220,7 +220,6 @@ CONFIG_CPU_CP15_MMU=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/at91sam9261ek_defconfig b/arch/arm/configs/at91sam9261ek_defconfig
index 3802e85f7483..4049768962d2 100644
--- a/arch/arm/configs/at91sam9261ek_defconfig
+++ b/arch/arm/configs/at91sam9261ek_defconfig
@@ -213,7 +213,6 @@ CONFIG_CPU_CP15_MMU=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/at91sam9263ek_defconfig b/arch/arm/configs/at91sam9263ek_defconfig
index 32a0d74e0c89..fa1c5aecb5a8 100644
--- a/arch/arm/configs/at91sam9263ek_defconfig
+++ b/arch/arm/configs/at91sam9263ek_defconfig
@@ -213,7 +213,6 @@ CONFIG_CPU_CP15_MMU=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/at91sam9g20ek_defconfig
index 6bea0901bdf0..c06863847364 100644
--- a/arch/arm/configs/em_x270_defconfig
+++ b/arch/arm/configs/at91sam9g20ek_defconfig
@@ -1,13 +1,13 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22
-# Mon Jul  9 15:18:20 2007
+# Linux kernel version: 2.6.24
+# Tue Jun 10 15:51:52 2008
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
-# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
 # CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
@@ -22,45 +22,40 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_ZONE_DMA=y
-CONFIG_ARCH_MTD_XIP=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION="-em-x270"
+CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SWAP=y
+# CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_FAIR_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
 # CONFIG_RELAY is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
+# CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
@@ -71,42 +66,35 @@ CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
 CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
 CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
@@ -120,7 +108,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
+CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
@@ -139,8 +127,9 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
@@ -150,25 +139,60 @@ CONFIG_ARCH_PXA=y
 # CONFIG_ARCH_OMAP is not set
 
 #
-# Intel PXA2xx Implementations
+# Boot options
+#
+
+#
+# Power management
 #
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_MACH_TRIZEPS4 is not set
-CONFIG_MACH_EM_X270=y
-CONFIG_PXA27x=y
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+CONFIG_ARCH_AT91SAM9G20=y
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9G20 Board Type
+#
+CONFIG_MACH_AT91SAM9G20EK=y
+
+#
+# AT91 Board Options
+#
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
+# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
+
+#
+# AT91 Feature Selections
+#
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_AT91_SLOW_CLOCK is not set
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
 
 #
 # Processor Type
 #
 CONFIG_CPU_32=y
-CONFIG_CPU_XSCALE=y
+CONFIG_CPU_ARM926T=y
 CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_ABRT_EV5TJ=y
 CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
 CONFIG_CPU_TLB_V4WBI=y
 CONFIG_CPU_CP15=y
 CONFIG_CPU_CP15_MMU=y
@@ -176,28 +200,28 @@ CONFIG_CPU_CP15_MMU=y
 #
 # Processor Features
 #
-CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
 # CONFIG_OUTER_CACHE is not set
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
 
 #
 # Bus support
 #
+# CONFIG_PCI_SYSCALL is not set
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
 # CONFIG_PCCARD is not set
 
 #
 # Kernel Features
 #
 # CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
@@ -209,9 +233,14 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_LEDS=y
+CONFIG_LEDS_CPU=y
 CONFIG_ALIGNMENT_TRAP=y
 
 #
@@ -219,7 +248,7 @@ CONFIG_ALIGNMENT_TRAP=y
 #
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE=""
+CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
 # CONFIG_XIP_KERNEL is not set
 # CONFIG_KEXEC is not set
 
@@ -233,6 +262,7 @@ CONFIG_CMDLINE=""
 CONFIG_FPE_NWFPE=y
 # CONFIG_FPE_NWFPE_XP is not set
 # CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
 
 #
 # Userspace binary formats
@@ -245,10 +275,12 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 CONFIG_PM=y
-CONFIG_PM_LEGACY=y
+# CONFIG_PM_LEGACY is not set
 # CONFIG_PM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
-CONFIG_APM_EMULATION=m
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_SUSPEND=y
+# CONFIG_APM_EMULATION is not set
 
 #
 # Networking
@@ -261,17 +293,13 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_DHCP is not set
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
@@ -283,9 +311,10 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
@@ -311,10 +340,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -323,28 +348,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
 # CONFIG_IRDA is not set
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=m
-# CONFIG_BT_RFCOMM_TTY is not set
-CONFIG_BT_BNEP=m
-# CONFIG_BT_BNEP_MC_FILTER is not set
-# CONFIG_BT_BNEP_PROTO_FILTER is not set
-CONFIG_BT_HIDP=m
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_HCIUSB=m
-# CONFIG_BT_HCIUSB_SCO is not set
-CONFIG_BT_HCIUART=m
-# CONFIG_BT_HCIUART_H4 is not set
-# CONFIG_BT_HCIUART_BCSP is not set
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
 
 #
@@ -353,13 +357,9 @@ CONFIG_BT_HCIBFUSB=m
 # CONFIG_CFG80211 is not set
 # CONFIG_WIRELESS_EXT is not set
 # CONFIG_MAC80211 is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-# CONFIG_IEEE80211_CRYPT_TKIP is not set
-# CONFIG_IEEE80211_SOFTMAC is not set
+# CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -368,23 +368,18 @@ CONFIG_IEEE80211_CRYPT_CCMP=m
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_FW_LOADER is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 CONFIG_MTD_CONCAT=y
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AFS_PARTS is not set
 
 #
@@ -398,15 +393,13 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
 #
 # CONFIG_MTD_CFI is not set
 # CONFIG_MTD_JEDECPROBE is not set
-# CONFIG_MTD_CFI_NOSWAP is not set
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
 CONFIG_MTD_MAP_BANK_WIDTH_1=y
 CONFIG_MTD_MAP_BANK_WIDTH_2=y
 CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -425,12 +418,13 @@ CONFIG_MTD_CFI_I2=y
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_SHARP_SL is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
 # Self-contained MTD device drivers
 #
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_M25P80 is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -446,32 +440,23 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_H1900 is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_SHARPSL is not set
+CONFIG_MTD_NAND_AT91=y
+CONFIG_MTD_NAND_AT91_ECC_SOFT=y
+# CONFIG_MTD_NAND_AT91_ECC_HW is not set
+# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
-CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
-
-#
-# Parallel port support
-#
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -479,20 +464,24 @@ CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_UB is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=12000
+CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-# CONFIG_IDE is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ATMEL_PWM=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
 
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
-# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
 # SCSI support type (disk, tape, CD-ROM)
@@ -507,7 +496,7 @@ CONFIG_BLK_DEV_SD=y
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 #
-# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
 # CONFIG_SCSI_SCAN_ASYNC is not set
@@ -519,39 +508,46 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
-CONFIG_DM9000=y
-# CONFIG_SMC911X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 
@@ -568,7 +564,6 @@ CONFIG_DM9000=y
 # CONFIG_USB_KAWETH is not set
 # CONFIG_USB_PEGASUS is not set
 # CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
 # CONFIG_USB_USBNET is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
@@ -577,10 +572,6 @@ CONFIG_DM9000=y
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 
 #
@@ -595,10 +586,9 @@ CONFIG_INPUT=y
 #
 CONFIG_INPUT_MOUSEDEV=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -612,29 +602,18 @@ CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_KEYBOARD_PXA27x=m
-# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_UCB1400 is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
 #
 # Hardware I/O ports
 #
 CONFIG_SERIO=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_SERPORT=y
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
 
@@ -655,45 +634,50 @@ CONFIG_HW_CONSOLE=y
 #
 # Non-8250 serial port support
 #
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
+CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_HW_RANDOM=m
+CONFIG_HW_RANDOM=y
 # CONFIG_NVRAM is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
 
 #
 # SPI support
 #
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
 
 #
-# Dallas's 1-wire bus
+# SPI Master Controller Drivers
 #
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SPI_TLE62X0 is not set
 # CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# Misc devices
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
@@ -701,19 +685,6 @@ CONFIG_HW_RANDOM=m
 # CONFIG_MFD_SM501 is not set
 
 #
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
@@ -723,81 +694,51 @@ CONFIG_HW_RANDOM=m
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
-# CONFIG_VGASTATE is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_PARAMETERS is not set
-# CONFIG_FB_MBX is not set
-# CONFIG_FB_VIRTUAL is not set
 
 #
 # Console display driver support
 #
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
 
 #
 # Sound
 #
-CONFIG_SOUND=m
+CONFIG_SOUND=y
 
 #
 # Advanced Linux Sound Architecture
 #
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SEQUENCER=y
+# CONFIG_SND_SEQ_DUMMY is not set
 CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
 CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
 # CONFIG_SND_DYNAMIC_MINORS is not set
 CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
 
 #
 # Generic devices
 #
-CONFIG_SND_AC97_CODEC=m
 # CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
 # CONFIG_SND_MTPAV is not set
 # CONFIG_SND_SERIAL_U16550 is not set
 # CONFIG_SND_MPU401 is not set
@@ -805,8 +746,13 @@ CONFIG_SND_AC97_CODEC=m
 #
 # ALSA ARM devices
 #
-CONFIG_SND_PXA2XX_PCM=m
-CONFIG_SND_PXA2XX_AC97=m
+# CONFIG_SND_AT91_AC97 is not set
+
+#
+# SPI devices
+#
+CONFIG_SND_AT73C213=y
+CONFIG_SND_AT73C213_TARGET_BITRATE=48000
 
 #
 # USB devices
@@ -820,16 +766,17 @@ CONFIG_SND_PXA2XX_AC97=m
 # CONFIG_SND_SOC is not set
 
 #
-# Open Sound System
+# SoC Audio support for SuperH
 #
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=m
 
 #
-# HID Devices
+# Open Sound System
 #
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
 
 #
 # USB Input Devices
@@ -838,10 +785,7 @@ CONFIG_USB_HID=y
 # CONFIG_USB_HIDINPUT_POWERBOOK is not set
 # CONFIG_HID_FF is not set
 # CONFIG_USB_HIDDEV is not set
-
-#
-# USB support
-#
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
@@ -855,6 +799,7 @@ CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_PERSIST is not set
 # CONFIG_USB_OTG is not set
 
 #
@@ -866,6 +811,7 @@ CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # USB Device Class drivers
@@ -884,6 +830,7 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
@@ -898,7 +845,7 @@ CONFIG_USB_STORAGE=y
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-# CONFIG_USB_MON is not set
+CONFIG_USB_MON=y
 
 #
 # USB port drivers
@@ -939,26 +886,66 @@ CONFIG_USB_STORAGE=y
 #
 # USB Gadget Support
 #
-# CONFIG_USB_GADGET is not set
-CONFIG_MMC=m
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+CONFIG_USB_ZERO=m
+# CONFIG_USB_ETH is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
 # MMC/SD Card Drivers
 #
-CONFIG_MMC_BLOCK=m
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
 
 #
 # MMC/SD Host Controller Drivers
 #
-CONFIG_MMC_PXA=m
+CONFIG_MMC_AT91=y
+# CONFIG_MMC_SPI is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
 
 #
-# Real Time Clock
+# LED drivers
 #
+CONFIG_LEDS_ATMEL_PWM=y
+CONFIG_LEDS_GPIO=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=m
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
 
 #
 # RTC interfaces
@@ -970,26 +957,28 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_TEST is not set
 
 #
-# I2C RTC drivers
-#
-
-#
 # SPI RTC drivers
 #
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
 
 #
 # Platform RTC drivers
 #
 # CONFIG_RTC_DRV_CMOS is not set
 # CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
-CONFIG_RTC_DRV_V3020=m
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 
 #
 # on-CPU RTC drivers
 #
-CONFIG_RTC_DRV_SA1100=m
+CONFIG_RTC_DRV_AT91SAM9=y
+CONFIG_RTC_DRV_AT91SAM9_RTT=0
+CONFIG_RTC_DRV_AT91SAM9_GPBR=0
 
 #
 # File systems
@@ -997,14 +986,8 @@ CONFIG_RTC_DRV_SA1100=m
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT3_FS is not set
 # CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
@@ -1046,7 +1029,6 @@ CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -1062,22 +1044,21 @@ CONFIG_RAMFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
 CONFIG_JFFS2_SUMMARY=y
 # CONFIG_JFFS2_FS_XATTR is not set
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
-# CONFIG_CRAMFS is not set
+CONFIG_CRAMFS=y
 # CONFIG_VXFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
@@ -1092,29 +1073,23 @@ CONFIG_SUNRPC=y
 # CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=y
-# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_CODEPAGE_737 is not set
 # CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
+CONFIG_NLS_CODEPAGE_850=y
 # CONFIG_NLS_CODEPAGE_852 is not set
 # CONFIG_NLS_CODEPAGE_855 is not set
 # CONFIG_NLS_CODEPAGE_857 is not set
@@ -1145,108 +1120,36 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_ISO8859_9 is not set
 # CONFIG_NLS_ISO8859_13 is not set
 # CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
+CONFIG_NLS_ISO8859_15=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 CONFIG_NLS_UTF8=y
-
-#
-# Distributed Lock Manager
-#
 # CONFIG_DLM is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+# CONFIG_INSTRUMENTATION is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
 CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_MAGIC_SYSRQ=y
+# CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_FRAME_POINTER=y
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=m
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_MANAGER=m
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-CONFIG_CRYPTO_AES=m
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
 
 #
 # Library routines
@@ -1256,10 +1159,10 @@ CONFIG_BITREVERSE=y
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/at91sam9rlek_defconfig b/arch/arm/configs/at91sam9rlek_defconfig
index 98e6746d02be..d8ec5f9ca6ec 100644
--- a/arch/arm/configs/at91sam9rlek_defconfig
+++ b/arch/arm/configs/at91sam9rlek_defconfig
@@ -211,7 +211,6 @@ CONFIG_CPU_CP15_MMU=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/ateb9200_defconfig b/arch/arm/configs/ateb9200_defconfig
index d846a492e5ce..85c80f723d8e 100644
--- a/arch/arm/configs/ateb9200_defconfig
+++ b/arch/arm/configs/ateb9200_defconfig
@@ -171,7 +171,6 @@ CONFIG_AT91_CF=m
 # Kernel Features
 #
 CONFIG_PREEMPT=y
-CONFIG_NO_IDLE_HZ=y
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig
index 4264e273202d..f7622e658163 100644
--- a/arch/arm/configs/collie_defconfig
+++ b/arch/arm/configs/collie_defconfig
@@ -166,7 +166,6 @@ CONFIG_PCMCIA_SA1100=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig
index e8980a9bb893..9b8748a8d9dd 100644
--- a/arch/arm/configs/corgi_defconfig
+++ b/arch/arm/configs/corgi_defconfig
@@ -165,7 +165,6 @@ CONFIG_PCMCIA_PXA2XX=y
 # Kernel Features
 #
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
diff --git a/arch/arm/configs/ecbat91_defconfig b/arch/arm/configs/ecbat91_defconfig
index 90ed214e3673..cfeb817ad21a 100644
--- a/arch/arm/configs/ecbat91_defconfig
+++ b/arch/arm/configs/ecbat91_defconfig
@@ -230,7 +230,6 @@ CONFIG_AT91_CF=y
 #
 # CONFIG_TICK_ONESHOT is not set
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index 24a701ab33e5..21aa013793c6 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -184,7 +184,6 @@ CONFIG_ARM_AMBA=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/eseries_pxa_defconfig b/arch/arm/configs/eseries_pxa_defconfig
index ed487b90dbed..493ecee24f94 100644
--- a/arch/arm/configs/eseries_pxa_defconfig
+++ b/arch/arm/configs/eseries_pxa_defconfig
@@ -251,7 +251,6 @@ CONFIG_PCMCIA_PXA2XX=m
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
diff --git a/arch/arm/configs/imx27ads_defconfig b/arch/arm/configs/imx27ads_defconfig
new file mode 100644
index 000000000000..bcd95b8dd2df
--- /dev/null
+++ b/arch/arm/configs/imx27ads_defconfig
@@ -0,0 +1,826 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc6
+# Fri Jun 20 16:29:34 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Freescale MXC Implementations
+#
+CONFIG_ARCH_MX2=y
+# CONFIG_ARCH_MX3 is not set
+
+#
+# MX2 family CPU support
+#
+CONFIG_MACH_MX27=y
+
+#
+# MX2 Platforms
+#
+CONFIG_MACH_MX27ADS=y
+# CONFIG_MACH_PCM038 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x00000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_FEC_OLD is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_IMX is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+CONFIG_HAVE_GPIO_LIB=y
+
+#
+# GPIO Support
+#
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+CONFIG_NLS_ISO8859_15=m
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/iop13xx_defconfig b/arch/arm/configs/iop13xx_defconfig
index 988b4d13e76f..482e57061053 100644
--- a/arch/arm/configs/iop13xx_defconfig
+++ b/arch/arm/configs/iop13xx_defconfig
@@ -197,7 +197,6 @@ CONFIG_PCI_LEGACY=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig
index 83f40d4041a6..8612f58e1056 100644
--- a/arch/arm/configs/iop32x_defconfig
+++ b/arch/arm/configs/iop32x_defconfig
@@ -201,7 +201,6 @@ CONFIG_PCI_LEGACY=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/iop33x_defconfig b/arch/arm/configs/iop33x_defconfig
index 917afb5ccfac..8b0098d19d08 100644
--- a/arch/arm/configs/iop33x_defconfig
+++ b/arch/arm/configs/iop33x_defconfig
@@ -197,7 +197,6 @@ CONFIG_PCI_LEGACY=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/ixp2000_defconfig b/arch/arm/configs/ixp2000_defconfig
index f8f9793b526f..84680db6c615 100644
--- a/arch/arm/configs/ixp2000_defconfig
+++ b/arch/arm/configs/ixp2000_defconfig
@@ -184,7 +184,6 @@ CONFIG_PCI=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/ixp23xx_defconfig b/arch/arm/configs/ixp23xx_defconfig
index 27cf022dd807..4a2f7b2372db 100644
--- a/arch/arm/configs/ixp23xx_defconfig
+++ b/arch/arm/configs/ixp23xx_defconfig
@@ -180,7 +180,6 @@ CONFIG_PCI=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig
index efa0485d2f7e..fc14932e3abd 100644
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -165,6 +165,7 @@ CONFIG_ARCH_PRPMC1100=y
 CONFIG_MACH_NAS100D=y
 CONFIG_MACH_DSMG600=y
 CONFIG_ARCH_IXDP4XX=y
+CONFIG_MACH_FSG=y
 CONFIG_CPU_IXP46X=y
 CONFIG_CPU_IXP43X=y
 CONFIG_MACH_GTWX5715=y
@@ -770,7 +771,7 @@ CONFIG_ATA=y
 # CONFIG_SATA_SIL24 is not set
 # CONFIG_SATA_SIS is not set
 # CONFIG_SATA_ULI is not set
-# CONFIG_SATA_VIA is not set
+CONFIG_SATA_VIA=y
 # CONFIG_SATA_VITESSE is not set
 # CONFIG_SATA_INIC162X is not set
 # CONFIG_PATA_ALI is not set
@@ -1143,7 +1144,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_VIA686A is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_VT8231 is not set
-# CONFIG_SENSORS_W83781D is not set
+CONFIG_SENSORS_W83781D=y
 # CONFIG_SENSORS_W83791D is not set
 # CONFIG_SENSORS_W83792D is not set
 # CONFIG_SENSORS_W83793 is not set
@@ -1334,8 +1335,8 @@ CONFIG_LEDS_CLASS=y
 #
 # LED drivers
 #
-# CONFIG_LEDS_IXP4XX is not set
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_FSG=y
 
 #
 # LED Triggers
@@ -1367,7 +1368,7 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_DS1672 is not set
 # CONFIG_RTC_DRV_MAX6900 is not set
 # CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
+CONFIG_RTC_DRV_ISL1208=y
 CONFIG_RTC_DRV_X1205=y
 CONFIG_RTC_DRV_PCF8563=y
 # CONFIG_RTC_DRV_PCF8583 is not set
diff --git a/arch/arm/configs/kafa_defconfig b/arch/arm/configs/kafa_defconfig
index ae51a40db6f9..6dd95a2c8d5d 100644
--- a/arch/arm/configs/kafa_defconfig
+++ b/arch/arm/configs/kafa_defconfig
@@ -162,7 +162,6 @@ CONFIG_CPU_TLB_V4WBI=y
 # Kernel Features
 #
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/kb9202_defconfig b/arch/arm/configs/kb9202_defconfig
index c16537d9d67a..8e74c66f239d 100644
--- a/arch/arm/configs/kb9202_defconfig
+++ b/arch/arm/configs/kb9202_defconfig
@@ -126,7 +126,6 @@ CONFIG_ISA_DMA_API=y
 #
 # Kernel Features
 #
-# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
new file mode 100644
index 000000000000..e3357ba10f1f
--- /dev/null
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -0,0 +1,1426 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc5
+# Sun Jun 22 15:51:25 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+CONFIG_ARCH_KIRKWOOD=y
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Marvell Kirkwood Implementations
+#
+CONFIG_MACH_DB88F6281_BP=y
+CONFIG_MACH_RD88F6192_NAS=y
+CONFIG_MACH_RD88F6281=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+CONFIG_PLAT_ORION=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_FEROCEON=y
+# CONFIG_CPU_FEROCEON_OLD_ID is not set
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_FEROCEON=y
+CONFIG_CPU_TLB_FEROCEON=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_FEROCEON_L2=y
+
+#
+# Bus support
+#
+CONFIG_PCI=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=0
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_ORION=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+CONFIG_SATA_MV=y
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+CONFIG_E1000=y
+CONFIG_E1000_NAPI=y
+# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
+# CONFIG_E1000E is not set
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+CONFIG_MV643XX_ETH=y
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_MV64XXX=y
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+CONFIG_SPI_ORION=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+CONFIG_USB_PRINTER=y
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+# CONFIG_USB_STORAGE_ISD200 is not set
+CONFIG_USB_STORAGE_DPCM=y
+# CONFIG_USB_STORAGE_USBAT is not set
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_NEW_LEDS=y
+# CONFIG_LEDS_CLASS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGERS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+CONFIG_RTC_DRV_MV=y
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_MV_XOR=y
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_XFS_FS=y
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_ASYNC_CORE=y
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/ks8695_defconfig b/arch/arm/configs/ks8695_defconfig
index 8ab21a0719e9..6077f2cb88e4 100644
--- a/arch/arm/configs/ks8695_defconfig
+++ b/arch/arm/configs/ks8695_defconfig
@@ -174,7 +174,6 @@ CONFIG_PCCARD_NONSTATIC=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/loki_defconfig b/arch/arm/configs/loki_defconfig
new file mode 100644
index 000000000000..17da7c3b3d53
--- /dev/null
+++ b/arch/arm/configs/loki_defconfig
@@ -0,0 +1,1147 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc5
+# Fri Jun 13 03:07:49 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+# CONFIG_GENERIC_GPIO is not set
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+CONFIG_ARCH_LOKI=y
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Marvell Loki (88RC8480) Implementations
+#
+CONFIG_MACH_LB88RC8480=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+CONFIG_PLAT_ORION=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_FEROCEON=y
+# CONFIG_CPU_FEROCEON_OLD_ID is not set
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_FEROCEON=y
+CONFIG_CPU_TLB_FEROCEON=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_FTL=y
+CONFIG_NFTL=y
+# CONFIG_NFTL_RW is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_I4=y
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=0
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_ORION=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_ATA_SFF=y
+CONFIG_SATA_MV=y
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_MV643XX_ETH=y
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_MV64XXX=y
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+CONFIG_USB_PRINTER=y
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+# CONFIG_USB_STORAGE_ISD200 is not set
+CONFIG_USB_STORAGE_DPCM=y
+# CONFIG_USB_STORAGE_USBAT is not set
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_NEW_LEDS=y
+# CONFIG_LEDS_CLASS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGERS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_XFS_FS=y
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_LDM_PARTITION=y
+CONFIG_LDM_DEBUG=y
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/lpd270_defconfig b/arch/arm/configs/lpd270_defconfig
index a3bf5833b87a..1a38d8e3fe66 100644
--- a/arch/arm/configs/lpd270_defconfig
+++ b/arch/arm/configs/lpd270_defconfig
@@ -173,7 +173,6 @@ CONFIG_XSCALE_PMU=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/lpd7a404_defconfig b/arch/arm/configs/lpd7a404_defconfig
index 46a0f7fe1fa5..7a2e932da1c6 100644
--- a/arch/arm/configs/lpd7a404_defconfig
+++ b/arch/arm/configs/lpd7a404_defconfig
@@ -148,7 +148,6 @@ CONFIG_ARM_AMBA=y
 # Kernel Features
 #
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_AEABI is not set
 CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
 CONFIG_SELECT_MEMORY_MODEL=y
diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig
new file mode 100644
index 000000000000..d38ebf8721a4
--- /dev/null
+++ b/arch/arm/configs/mv78xx0_defconfig
@@ -0,0 +1,1445 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc5
+# Fri Jun 13 02:57:32 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+# CONFIG_GENERIC_GPIO is not set
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+CONFIG_ARCH_MV78XX0=y
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Marvell MV78xx0 Implementations
+#
+CONFIG_MACH_DB78X00_BP=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+CONFIG_PLAT_ORION=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_FEROCEON=y
+CONFIG_CPU_FEROCEON_OLD_ID=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_FEROCEON=y
+CONFIG_CPU_TLB_FEROCEON=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_FEROCEON_L2=y
+
+#
+# Bus support
+#
+CONFIG_PCI=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=0
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_ORION=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+CONFIG_SATA_MV=y
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+CONFIG_MV643XX_ETH=y
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_MV64XXX=y
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+CONFIG_USB_PRINTER=y
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+# CONFIG_USB_STORAGE_ISD200 is not set
+CONFIG_USB_STORAGE_DPCM=y
+# CONFIG_USB_STORAGE_USBAT is not set
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=y
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+CONFIG_RTC_DRV_RS5C372=y
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+CONFIG_RTC_DRV_M41T80=y
+# CONFIG_RTC_DRV_M41T80_WDT is not set
+# CONFIG_RTC_DRV_S35390A is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/mx31ads_defconfig b/arch/arm/configs/mx31ads_defconfig
new file mode 100644
index 000000000000..e05271753e15
--- /dev/null
+++ b/arch/arm/configs/mx31ads_defconfig
@@ -0,0 +1,839 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc6
+# Fri Jun 20 16:21:11 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Freescale MXC Implementations
+#
+# CONFIG_ARCH_MX2 is not set
+CONFIG_ARCH_MX3=y
+
+#
+# MX3 Options
+#
+CONFIG_MACH_MX31ADS=y
+# CONFIG_MACH_PCM037 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+# CONFIG_CPU_32v6K is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
+# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
+# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+# CONFIG_BLK_DEV is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+CONFIG_HAVE_GPIO_LIB=y
+
+#
+# GPIO Support
+#
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/mx31litekit_defconfig b/arch/arm/configs/mx31litekit_defconfig
new file mode 100644
index 000000000000..4f41c4135685
--- /dev/null
+++ b/arch/arm/configs/mx31litekit_defconfig
@@ -0,0 +1,1100 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc5
+# Fri Jun 13 14:23:39 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+# CONFIG_GENERIC_GPIO is not set
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Freescale MXC Implementations
+#
+CONFIG_ARCH_MX3=y
+
+#
+# MX3 Options
+#
+# CONFIG_MACH_MX31ADS is not set
+CONFIG_MACH_MX31LITE=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+# CONFIG_CPU_32v6K is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# PC-card bridges
+#
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+CONFIG_PREEMPT=y
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_AOUT=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+# CONFIG_SUSPEND is not set
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
+# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
+# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+# CONFIG_BLK_DEV is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+CONFIG_V4L_USB_DRIVERS=y
+# CONFIG_USB_VICAM is not set
+# CONFIG_USB_IBMCAM is not set
+# CONFIG_USB_KONICAWC is not set
+# CONFIG_USB_QUICKCAM_MESSENGER is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_OV511 is not set
+# CONFIG_USB_SE401 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STV680 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_SI470X is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/netx_defconfig b/arch/arm/configs/netx_defconfig
index 57f32f39d0ff..0884f2370c3a 100644
--- a/arch/arm/configs/netx_defconfig
+++ b/arch/arm/configs/netx_defconfig
@@ -154,7 +154,6 @@ CONFIG_ARM_AMBA=y
 # Kernel Features
 #
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/onearm_defconfig b/arch/arm/configs/onearm_defconfig
index 650a248613e5..418ca2febbe3 100644
--- a/arch/arm/configs/onearm_defconfig
+++ b/arch/arm/configs/onearm_defconfig
@@ -202,7 +202,6 @@ CONFIG_AT91_CF=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
index 52cd99bd52fb..9578b5d9f9c7 100644
--- a/arch/arm/configs/orion5x_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24
-# Thu Feb  7 14:10:30 2008
+# Linux kernel version: 2.6.26-rc4
+# Mon Jun  2 23:54:48 2008
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -21,6 +21,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_ZONE_DMA=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -40,24 +41,24 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 # CONFIG_BLK_DEV_INITRD is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
@@ -73,20 +74,25 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
 # CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
+CONFIG_PROFILING=y
 # CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
 CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
 CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
 CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
@@ -111,7 +117,6 @@ CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
 CONFIG_CLASSIC_RCU=y
-# CONFIG_PREEMPT_RCU is not set
 
 #
 # System Type
@@ -160,6 +165,15 @@ CONFIG_MACH_RD88F5182=y
 CONFIG_MACH_KUROBOX_PRO=y
 CONFIG_MACH_DNS323=y
 CONFIG_MACH_TS209=y
+CONFIG_MACH_LINKSTATION_PRO=y
+CONFIG_MACH_TS409=y
+CONFIG_MACH_WRT350N_V2=y
+CONFIG_MACH_TS78XX=y
+CONFIG_MACH_MV2120=y
+CONFIG_MACH_MSS2=y
+CONFIG_MACH_WNR854T=y
+CONFIG_MACH_RD88F5181L_GE=y
+CONFIG_MACH_RD88F5181L_FXO=y
 
 #
 # Boot options
@@ -168,6 +182,7 @@ CONFIG_MACH_TS209=y
 #
 # Power management
 #
+CONFIG_PLAT_ORION=y
 
 #
 # Processor Type
@@ -177,8 +192,9 @@ CONFIG_CPU_FEROCEON=y
 CONFIG_CPU_FEROCEON_OLD_ID=y
 CONFIG_CPU_32v5=y
 CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
 CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_COPY_FEROCEON=y
 CONFIG_CPU_TLB_V4WBI=y
 CONFIG_CPU_CP15=y
 CONFIG_CPU_CP15_MMU=y
@@ -189,7 +205,6 @@ CONFIG_CPU_CP15_MMU=y
 CONFIG_ARM_THUMB=y
 # CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
 # CONFIG_OUTER_CACHE is not set
 
 #
@@ -199,6 +214,7 @@ CONFIG_PCI=y
 CONFIG_PCI_SYSCALL=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
 # CONFIG_PCCARD is not set
 
 #
@@ -221,6 +237,7 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
 # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
@@ -238,7 +255,6 @@ CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE=""
 # CONFIG_XIP_KERNEL is not set
 # CONFIG_KEXEC is not set
-# CONFIG_ATAGS_PROC is not set
 
 #
 # Floating point emulation
@@ -311,8 +327,6 @@ CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
@@ -335,6 +349,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # Network testing
 #
 CONFIG_NET_PKTGEN=m
+# CONFIG_NET_TCPPROBE is not set
 # CONFIG_HAMRADIO is not set
 # CONFIG_CAN is not set
 # CONFIG_IRDA is not set
@@ -362,6 +377,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
@@ -371,6 +388,7 @@ CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -378,9 +396,8 @@ CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
-CONFIG_FTL=y
-CONFIG_NFTL=y
-# CONFIG_NFTL_RW is not set
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
@@ -405,12 +422,12 @@ CONFIG_MTD_MAP_BANK_WIDTH_4=y
 # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
 CONFIG_MTD_CFI_I1=y
 CONFIG_MTD_CFI_I2=y
-CONFIG_MTD_CFI_I4=y
+# CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
 # CONFIG_MTD_OTP is not set
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
+# CONFIG_MTD_CFI_STAA is not set
 CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
@@ -481,6 +498,9 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_SGI_IOC4 is not set
 # CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
 
 #
 # SCSI device support
@@ -542,6 +562,7 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_IPS is not set
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_STEX is not set
 # CONFIG_SCSI_SYM53C8XX_2 is not set
 # CONFIG_SCSI_IPR is not set
@@ -556,7 +577,10 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_SRP is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
 # CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
 # CONFIG_SATA_SVW is not set
 # CONFIG_ATA_PIIX is not set
 CONFIG_SATA_MV=y
@@ -566,7 +590,6 @@ CONFIG_SATA_MV=y
 # CONFIG_SATA_PROMISE is not set
 # CONFIG_SATA_SX4 is not set
 # CONFIG_SATA_SIL is not set
-# CONFIG_SATA_SIL24 is not set
 # CONFIG_SATA_SIS is not set
 # CONFIG_SATA_ULI is not set
 # CONFIG_SATA_VIA is not set
@@ -611,6 +634,7 @@ CONFIG_SATA_MV=y
 # CONFIG_PATA_VIA is not set
 # CONFIG_PATA_WINBOND is not set
 # CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
 # CONFIG_MD is not set
 # CONFIG_FUSION is not set
 
@@ -652,7 +676,7 @@ CONFIG_NET_PCI=y
 # CONFIG_B44 is not set
 # CONFIG_FORCEDETH is not set
 # CONFIG_EEPRO100 is not set
-CONFIG_E100=y
+# CONFIG_E100 is not set
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
 # CONFIG_NE2K_PCI is not set
@@ -668,9 +692,7 @@ CONFIG_E100=y
 CONFIG_NETDEV_1000=y
 # CONFIG_ACENIC is not set
 # CONFIG_DL2K is not set
-CONFIG_E1000=y
-CONFIG_E1000_NAPI=y
-# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
+# CONFIG_E1000 is not set
 # CONFIG_E1000E is not set
 # CONFIG_E1000E_ENABLED is not set
 # CONFIG_IP1000 is not set
@@ -680,27 +702,15 @@ CONFIG_E1000_NAPI=y
 # CONFIG_YELLOWFIN is not set
 # CONFIG_R8169 is not set
 # CONFIG_SIS190 is not set
-CONFIG_SKGE=y
-CONFIG_SKY2=y
-# CONFIG_SK98LIN is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
 # CONFIG_VIA_VELOCITY is not set
-CONFIG_TIGON3=y
+# CONFIG_TIGON3 is not set
 # CONFIG_BNX2 is not set
 CONFIG_MV643XX_ETH=y
 # CONFIG_QLA3XXX is not set
 # CONFIG_ATL1 is not set
-CONFIG_NETDEV_10000=y
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_CHELSIO_T3 is not set
-# CONFIG_IXGBE is not set
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-# CONFIG_NETXEN_NIC is not set
-# CONFIG_NIU is not set
-# CONFIG_MLX4_CORE is not set
-# CONFIG_TEHUTI is not set
-# CONFIG_BNX2X is not set
+# CONFIG_NETDEV_10000 is not set
 # CONFIG_TR is not set
 
 #
@@ -708,6 +718,7 @@ CONFIG_NETDEV_10000=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 
 #
 # USB Network Adapters
@@ -738,12 +749,9 @@ CONFIG_INPUT=y
 #
 # Userland interfaces
 #
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
+CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
 #
@@ -765,10 +773,8 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 #
 # Character devices
 #
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 # CONFIG_NOZOMI is not set
 
@@ -777,7 +783,7 @@ CONFIG_HW_CONSOLE=y
 #
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
+# CONFIG_SERIAL_8250_PCI is not set
 CONFIG_SERIAL_8250_NR_UARTS=4
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
 # CONFIG_SERIAL_8250_EXTENDED is not set
@@ -792,7 +798,7 @@ CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_IPMI_HANDLER is not set
-CONFIG_HW_RANDOM=m
+# CONFIG_HW_RANDOM is not set
 # CONFIG_NVRAM is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
@@ -804,13 +810,6 @@ CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
 
 #
-# I2C Algorithms
-#
-# CONFIG_I2C_ALGOBIT is not set
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
-
-#
 # I2C Hardware Bus support
 #
 # CONFIG_I2C_ALI1535 is not set
@@ -837,6 +836,7 @@ CONFIG_I2C_CHARDEV=y
 # CONFIG_I2C_VIA is not set
 # CONFIG_I2C_VIAPRO is not set
 # CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
 CONFIG_I2C_MV64XXX=y
 
 #
@@ -847,19 +847,13 @@ CONFIG_I2C_MV64XXX=y
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_TPS65010 is not set
 # CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
@@ -872,6 +866,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
 # CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_I5K_AMB is not set
@@ -901,6 +896,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
 # CONFIG_SENSORS_THMC50 is not set
 # CONFIG_SENSORS_VIA686A is not set
 # CONFIG_SENSORS_VT1211 is not set
@@ -910,6 +906,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_W83792D is not set
 # CONFIG_SENSORS_W83793 is not set
 # CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
@@ -925,14 +922,24 @@ CONFIG_SSB_POSSIBLE=y
 # Multifunction device drivers
 #
 # CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
-CONFIG_DAB=y
-# CONFIG_USB_DABUSB is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
 
 #
 # Graphics support
@@ -949,12 +956,6 @@ CONFIG_DAB=y
 # CONFIG_DISPLAY_SUPPORT is not set
 
 #
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-
-#
 # Sound
 #
 # CONFIG_SOUND is not set
@@ -985,14 +986,18 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_USB_EHCI_TT_NEWSCHED=y
 # CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
 # CONFIG_USB_OHCI_HCD is not set
 # CONFIG_USB_UHCI_HCD is not set
 # CONFIG_USB_SL811_HCD is not set
@@ -1003,6 +1008,7 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y
 #
 # CONFIG_USB_ACM is not set
 CONFIG_USB_PRINTER=y
+# CONFIG_USB_WDM is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1022,7 +1028,9 @@ CONFIG_USB_STORAGE_SDDR09=y
 CONFIG_USB_STORAGE_SDDR55=y
 CONFIG_USB_STORAGE_JUMPSHOT=y
 # CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
 # CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 # CONFIG_USB_LIBUSUAL is not set
 
 #
@@ -1060,6 +1068,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
 CONFIG_NEW_LEDS=y
@@ -1068,7 +1077,7 @@ CONFIG_LEDS_CLASS=y
 #
 # LED drivers
 #
-# CONFIG_LEDS_GPIO is not set
+CONFIG_LEDS_GPIO=y
 
 #
 # LED Triggers
@@ -1076,6 +1085,7 @@ CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -1105,6 +1115,7 @@ CONFIG_RTC_DRV_RS5C372=y
 # CONFIG_RTC_DRV_PCF8583 is not set
 CONFIG_RTC_DRV_M41T80=y
 # CONFIG_RTC_DRV_M41T80_WDT is not set
+# CONFIG_RTC_DRV_S35390A is not set
 
 #
 # SPI RTC drivers
@@ -1125,6 +1136,7 @@ CONFIG_RTC_DRV_M41T80=y
 #
 # on-CPU RTC drivers
 #
+# CONFIG_UIO is not set
 
 #
 # File systems
@@ -1140,14 +1152,11 @@ CONFIG_JBD=y
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -1155,8 +1164,8 @@ CONFIG_DNOTIFY=y
 #
 # CD-ROM/DVD Filesystems
 #
-CONFIG_ISO9660_FS=y
-# CONFIG_JOLIET is not set
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
 # CONFIG_ZISOFS is not set
 CONFIG_UDF_FS=m
 CONFIG_UDF_NLS=y
@@ -1205,8 +1214,10 @@ CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 CONFIG_CRAMFS=y
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -1214,7 +1225,6 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 # CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
@@ -1241,14 +1251,13 @@ CONFIG_PARTITION_ADVANCED=y
 # CONFIG_MAC_PARTITION is not set
 CONFIG_MSDOS_PARTITION=y
 CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_LDM_DEBUG=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
 # CONFIG_SGI_PARTITION is not set
 # CONFIG_ULTRIX_PARTITION is not set
-CONFIG_SUN_PARTITION=y
+# CONFIG_SUN_PARTITION is not set
 # CONFIG_KARMA_PARTITION is not set
 # CONFIG_EFI_PARTITION is not set
 # CONFIG_SYSV68_PARTITION is not set
@@ -1300,15 +1309,48 @@ CONFIG_NLS_ISO8859_2=y
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
 # CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
 
 #
 # Security options
@@ -1317,50 +1359,79 @@ CONFIG_DEBUG_USER=y
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
 CONFIG_CRYPTO_ALGAPI=m
 CONFIG_CRYPTO_BLKCIPHER=m
-# CONFIG_CRYPTO_SEQIV is not set
 CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_XTS is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
 # CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_SEED is not set
 # CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
 # CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-# CONFIG_CRYPTO_AUTHENC is not set
 # CONFIG_CRYPTO_LZO is not set
 CONFIG_CRYPTO_HW=y
 # CONFIG_CRYPTO_DEV_HIFN_795X is not set
@@ -1369,12 +1440,14 @@ CONFIG_CRYPTO_HW=y
 # Library routines
 #
 CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-# CONFIG_CRC_ITU_T is not set
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
-CONFIG_LIBCRC32C=y
+# CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_PLIST=y
diff --git a/arch/arm/configs/pcm037_defconfig b/arch/arm/configs/pcm037_defconfig
new file mode 100644
index 000000000000..627474586470
--- /dev/null
+++ b/arch/arm/configs/pcm037_defconfig
@@ -0,0 +1,748 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc6
+# Wed Jun 25 11:52:42 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Freescale MXC Implementations
+#
+CONFIG_ARCH_MX3=y
+
+#
+# MX3 Options
+#
+# CONFIG_MACH_MX31ADS is not set
+CONFIG_MACH_PCM037=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+# CONFIG_CPU_32v6K is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+# CONFIG_MTD_CFI_NOSWAP is not set
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+# CONFIG_BLK_DEV is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+CONFIG_HAVE_GPIO_LIB=y
+
+#
+# GPIO Support
+#
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/pcm038_defconfig b/arch/arm/configs/pcm038_defconfig
new file mode 100644
index 000000000000..6b798c215ca8
--- /dev/null
+++ b/arch/arm/configs/pcm038_defconfig
@@ -0,0 +1,1008 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc6
+# Fri Jun 20 16:38:36 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_MARKERS=y
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Freescale MXC Implementations
+#
+CONFIG_ARCH_MX2=y
+# CONFIG_ARCH_MX3 is not set
+
+#
+# MX2 family CPU support
+#
+CONFIG_MACH_MX27=y
+
+#
+# MX2 Platforms
+#
+# CONFIG_MACH_MX27ADS is not set
+CONFIG_MACH_PCM038=y
+CONFIG_MACH_PCM970_BASEBOARD=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x00000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_FEC_OLD=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_HAVE_GPIO_LIB=y
+
+#
+# GPIO Support
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_TUNER_3036 is not set
+# CONFIG_SOC_CAMERA is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_LOGO is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+CONFIG_RTC_DRV_PCF8563=y
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+CONFIG_NLS_ISO8859_15=m
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/picotux200_defconfig b/arch/arm/configs/picotux200_defconfig
index 95a22f512805..14826f0dabde 100644
--- a/arch/arm/configs/picotux200_defconfig
+++ b/arch/arm/configs/picotux200_defconfig
@@ -201,7 +201,6 @@ CONFIG_ARM_THUMB=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-CONFIG_NO_IDLE_HZ=y
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
diff --git a/arch/arm/configs/pnx4008_defconfig b/arch/arm/configs/pnx4008_defconfig
index b5e11aa2e290..811b8f60d19d 100644
--- a/arch/arm/configs/pnx4008_defconfig
+++ b/arch/arm/configs/pnx4008_defconfig
@@ -151,7 +151,6 @@ CONFIG_ARM_THUMB=y
 # Kernel Features
 #
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/qil-a9260_defconfig b/arch/arm/configs/qil-a9260_defconfig
new file mode 100644
index 000000000000..ef903bed061e
--- /dev/null
+++ b/arch/arm/configs/qil-a9260_defconfig
@@ -0,0 +1,1256 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24
+# Tue Apr 15 12:28:38 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+CONFIG_ARCH_AT91SAM9260=y
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9260 Variants
+#
+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
+
+#
+# AT91SAM9260 / AT91SAM9XE Board Type
+#
+# CONFIG_MACH_AT91SAM9260EK is not set
+# CONFIG_MACH_CAM60 is not set
+# CONFIG_MACH_SAM9_L9260 is not set
+# CONFIG_MACH_USB_A9260 is not set
+CONFIG_MACH_QIL_A9260=y
+
+#
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_SLOW_CLOCK=y
+CONFIG_AT91_TIMER_HZ=100
+# CONFIG_AT91_EARLY_DBGU is not set
+CONFIG_AT91_EARLY_USART0=y
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=64M console=ttyS1,115200"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_SUSPEND=y
+# CONFIG_APM_EMULATION is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_AT91=y
+CONFIG_MTD_NAND_AT91_ECC_SOFT=y
+# CONFIG_MTD_NAND_AT91_ECC_HW is not set
+# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=y
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_AT91SAM9_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_PERSIST is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_AT91=y
+# CONFIG_MMC_SPI is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+CONFIG_RTC_DRV_M41T94=y
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_AT91SAM9 is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+# CONFIG_INSTRUMENTATION is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig
index fc39ba1a89f3..0c09b23167ec 100644
--- a/arch/arm/configs/realview-smp_defconfig
+++ b/arch/arm/configs/realview-smp_defconfig
@@ -177,7 +177,6 @@ CONFIG_NR_CPUS=4
 CONFIG_HOTPLUG_CPU=y
 CONFIG_LOCAL_TIMERS=y
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index accbf529ce5b..907e54344dad 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -126,7 +126,6 @@ CONFIG_ISA_DMA_API=y
 #
 # Kernel Features
 #
-# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig
index 5ddecb9ddf01..f62d1817d2c6 100644
--- a/arch/arm/configs/rpc_defconfig
+++ b/arch/arm/configs/rpc_defconfig
@@ -190,7 +190,6 @@ CONFIG_ISA_DMA_API=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
index f8a1645b3d4a..35faaea8623e 100644
--- a/arch/arm/configs/s3c2410_defconfig
+++ b/arch/arm/configs/s3c2410_defconfig
@@ -1,15 +1,18 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21-rc6
-# Mon Apr  9 10:12:58 2007
+# Linux kernel version: 2.6.26-rc8
+# Mon Jul  7 16:59:23 2008
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 # CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
 CONFIG_MMU=y
 CONFIG_NO_IOPORT=y
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
@@ -18,34 +21,39 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_ZONE_DMA=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
+CONFIG_IKCONFIG=m
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
@@ -53,6 +61,7 @@ CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -60,34 +69,43 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_SLAB=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
@@ -101,6 +119,7 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System Type
@@ -119,14 +138,17 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
 # CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
@@ -134,18 +156,32 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 CONFIG_ARCH_S3C2410=y
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
 CONFIG_PLAT_S3C24XX=y
 CONFIG_CPU_S3C244X=y
+# CONFIG_S3C24XX_PWM is not set
 CONFIG_PM_SIMTEC=y
+CONFIG_S3C2410_DMA=y
+# CONFIG_S3C2410_DMA_DEBUG is not set
+CONFIG_MACH_SMDK=y
+CONFIG_PLAT_S3C=y
+CONFIG_CPU_LLSERIAL_S3C2410=y
+CONFIG_CPU_LLSERIAL_S3C2440=y
+
+#
+# Boot options
+#
 # CONFIG_S3C_BOOT_WATCHDOG is not set
 # CONFIG_S3C_BOOT_ERROR_RESET is not set
+
+#
+# Power management
+#
 # CONFIG_S3C2410_PM_DEBUG is not set
 # CONFIG_S3C2410_PM_CHECK is not set
 CONFIG_S3C_LOWLEVEL_UART_PORT=0
-CONFIG_S3C2410_DMA=y
-# CONFIG_S3C2410_DMA_DEBUG is not set
-CONFIG_MACH_SMDK=y
 
 #
 # S3C2400 Machines
@@ -155,6 +191,8 @@ CONFIG_CPU_S3C2410_DMA=y
 CONFIG_S3C2410_PM=y
 CONFIG_S3C2410_GPIO=y
 CONFIG_S3C2410_CLOCK=y
+CONFIG_SIMTEC_NOR=y
+CONFIG_MACH_BAST_IDE=y
 
 #
 # S3C2410 Machines
@@ -167,6 +205,7 @@ CONFIG_ARCH_BAST=y
 CONFIG_MACH_OTOM=y
 CONFIG_MACH_AML_M5900=y
 CONFIG_BAST_PC104_IRQ=y
+# CONFIG_MACH_TCT_HAMMER is not set
 CONFIG_MACH_VR1000=y
 CONFIG_MACH_QT2410=y
 CONFIG_CPU_S3C2412=y
@@ -176,8 +215,10 @@ CONFIG_S3C2412_PM=y
 #
 # S3C2412 Machines
 #
+# CONFIG_MACH_JIVE is not set
 CONFIG_MACH_SMDK2413=y
 CONFIG_MACH_S3C2413=y
+# CONFIG_MACH_SMDK2412 is not set
 CONFIG_MACH_VSTMS=y
 CONFIG_CPU_S3C2440=y
 CONFIG_S3C2440_DMA=y
@@ -191,6 +232,7 @@ CONFIG_MACH_RX3715=y
 CONFIG_ARCH_S3C2440=y
 CONFIG_MACH_NEXCODER_2440=y
 CONFIG_SMDK2440_CPU2440=y
+# CONFIG_MACH_AT2440EVB is not set
 CONFIG_CPU_S3C2442=y
 
 #
@@ -215,6 +257,7 @@ CONFIG_CPU_32v4T=y
 CONFIG_CPU_32v5=y
 CONFIG_CPU_ABRT_EV4T=y
 CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
 CONFIG_CPU_CACHE_V4WT=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_COPY_V4WB=y
@@ -236,17 +279,15 @@ CONFIG_CPU_CP15_MMU=y
 # Bus support
 #
 CONFIG_ISA=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
 #
 # Kernel Features
 #
+# CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=200
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
@@ -257,9 +298,13 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 CONFIG_ALIGNMENT_TRAP=y
 
 #
@@ -279,7 +324,7 @@ CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0"
 # At least one emulation must be selected
 #
 CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
+CONFIG_FPE_NWFPE_XP=y
 # CONFIG_FPE_FASTFPE is not set
 # CONFIG_VFP is not set
 
@@ -295,10 +340,12 @@ CONFIG_BINFMT_AOUT=y
 # Power management options
 #
 CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
 # CONFIG_PM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
-# CONFIG_APM_EMULATION is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=m
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
 # Networking
@@ -308,59 +355,67 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
-# CONFIG_PACKET is not set
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
+CONFIG_IP_MULTICAST=y
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
 # CONFIG_ARPD is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_INET_AH is not set
 # CONFIG_INET_ESP is not set
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
+CONFIG_IPV6=m
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+# CONFIG_IPV6_ROUTE_INFO is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -373,20 +428,71 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
+CONFIG_NET_SCH_FIFO=y
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
-# CONFIG_BT is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIUSB=m
+CONFIG_BT_HCIUSB_SCO=y
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIVHCI=m
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+CONFIG_NL80211=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_MAC80211=m
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_NONE is not set
+
+#
+# Selecting 'y' for an algorithm will
+#
+
+#
+# build the algorithm into mac80211.
+#
+CONFIG_MAC80211_RC_DEFAULT="pid"
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_MESH=y
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set
+# CONFIG_MAC80211_DEBUG is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -395,21 +501,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
+CONFIG_FW_LOADER=m
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
@@ -420,6 +519,7 @@ CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
 # CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -432,6 +532,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -457,7 +558,6 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 CONFIG_MTD_ROM=y
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
@@ -486,13 +586,10 @@ CONFIG_MTD_BAST_MAXSIZE=4
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
 CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 CONFIG_MTD_NAND_S3C2410=y
 # CONFIG_MTD_NAND_S3C2410_DEBUG is not set
@@ -500,30 +597,25 @@ CONFIG_MTD_NAND_S3C2410=y
 # CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
-
-#
-# OneNAND Flash Device Drivers
-#
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
 CONFIG_PARPORT=y
-# CONFIG_PARPORT_PC is not set
+CONFIG_PARPORT_PC=m
+# CONFIG_PARPORT_PC_FIFO is not set
+# CONFIG_PARPORT_PC_SUPERIO is not set
 # CONFIG_PARPORT_GSC is not set
-# CONFIG_PARPORT_AX88796 is not set
+CONFIG_PARPORT_AX88796=m
 CONFIG_PARPORT_1284=y
-
-#
-# Plug and Play support
-#
+CONFIG_PARPORT_NOT_PC=y
 # CONFIG_PNP is not set
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
+# CONFIG_PARIDE is not set
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -532,34 +624,34 @@ CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 CONFIG_ATA_OVER_ETH=m
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
 CONFIG_BLK_DEV_IDE=y
 
 #
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
 # CONFIG_BLK_DEV_IDE_SATA is not set
 CONFIG_BLK_DEV_IDEDISK=y
 # CONFIG_IDEDISK_MULTI_MODE is not set
 CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
 CONFIG_BLK_DEV_IDETAPE=m
 CONFIG_BLK_DEV_IDEFLOPPY=m
+# CONFIG_BLK_DEV_IDESCSI is not set
 # CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
 
 #
 # IDE chipset support/bugfixes
 #
-CONFIG_IDE_GENERIC=y
-# CONFIG_IDE_ARM is not set
-CONFIG_BLK_DEV_IDE_BAST=y
-# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
 # CONFIG_BLK_DEV_IDEDMA is not set
 # CONFIG_BLK_DEV_HD is not set
 
@@ -567,101 +659,119 @@ CONFIG_BLK_DEV_IDE_BAST=y
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
 # CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=m
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_PPA is not set
+# CONFIG_SCSI_IMM is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_DEBUG is not set
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+CONFIG_HAVE_PATA_PLATFORM=y
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# ARCnet devices
-#
+# CONFIG_VETH is not set
 # CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
 # CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+# CONFIG_AX88796 is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_NET_VENDOR_SMC is not set
 # CONFIG_SMC91X is not set
 CONFIG_DM9000=y
+# CONFIG_ENC28J60 is not set
+CONFIG_DM9000_DEBUGLEVEL=4
 # CONFIG_NET_VENDOR_RACAL is not set
 # CONFIG_AT1700 is not set
 # CONFIG_DEPCA is not set
 # CONFIG_HP100 is not set
 # CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 # CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
 # CONFIG_NET_POCKET is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
+CONFIG_NETDEV_1000=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_NETDEV_10000=y
 # CONFIG_TR is not set
 
 #
-# Wireless LAN (non-hamradio)
+# Wireless LAN
 #
-# CONFIG_NET_RADIO is not set
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 
 #
-# Wan interfaces
+# USB Network Adapters
 #
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_WAN is not set
 # CONFIG_PLIP is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 
 #
@@ -669,6 +779,7 @@ CONFIG_DM9000=y
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -678,7 +789,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -695,12 +805,21 @@ CONFIG_KEYBOARD_ATKBD=y
 # CONFIG_KEYBOARD_GPIO is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
 # CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
 # CONFIG_MOUSE_INPORT is not set
 # CONFIG_MOUSE_LOGIBM is not set
 # CONFIG_MOUSE_PC110PAD is not set
 # CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -721,6 +840,7 @@ CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 CONFIG_SERIAL_NONSTANDARD=y
 # CONFIG_COMPUTONE is not set
 # CONFIG_ROCKETPORT is not set
@@ -728,8 +848,6 @@ CONFIG_SERIAL_NONSTANDARD=y
 # CONFIG_DIGIEPCA is not set
 # CONFIG_MOXA_INTELLIO is not set
 # CONFIG_MOXA_SMARTIO is not set
-# CONFIG_MOXA_SMARTIO_NEW is not set
-# CONFIG_SYNCLINKMP is not set
 # CONFIG_N_HDLC is not set
 # CONFIG_RISCOM8 is not set
 # CONFIG_SPECIALIX is not set
@@ -758,8 +876,12 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
 #
 # Non-8250 serial port support
 #
+CONFIG_SERIAL_SAMSUNG=y
+# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
 CONFIG_SERIAL_S3C2410=y
-CONFIG_SERIAL_S3C2410_CONSOLE=y
+CONFIG_SERIAL_S3C2412=y
+CONFIG_SERIAL_S3C2440=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
@@ -768,89 +890,50 @@ CONFIG_LEGACY_PTY_COUNT=256
 CONFIG_PRINTER=y
 # CONFIG_LP_CONSOLE is not set
 CONFIG_PPDEV=y
-# CONFIG_TIPAR is not set
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-CONFIG_S3C2410_WATCHDOG=y
-
-#
-# ISA-based Watchdog Cards
-#
-# CONFIG_PCWATCHDOG is not set
-# CONFIG_MIXCOMWD is not set
-# CONFIG_WDT is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
 CONFIG_HW_RANDOM=y
 # CONFIG_NVRAM is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
+CONFIG_DEVPORT=y
 CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=m
-
-#
-# I2C Algorithms
-#
-CONFIG_I2C_ALGOBIT=m
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
+CONFIG_I2C_ALGOBIT=y
 
 #
 # I2C Hardware Bus support
 #
 # CONFIG_I2C_ELEKTOR is not set
+# CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
 CONFIG_I2C_S3C2410=y
+CONFIG_I2C_SIMTEC=y
+# CONFIG_I2C_TAOS_EVM is not set
 # CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
 # CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
 
 #
 # Miscellaneous I2C Chip support
 #
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
 CONFIG_SENSORS_EEPROM=m
 # CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
 # CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
 CONFIG_SPI=y
 # CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
@@ -860,6 +943,7 @@ CONFIG_SPI_MASTER=y
 #
 CONFIG_SPI_BITBANG=m
 # CONFIG_SPI_BUTTERFLY is not set
+# CONFIG_SPI_LM70_LLP is not set
 CONFIG_SPI_S3C24XX=m
 CONFIG_SPI_S3C24XX_GPIO=m
 
@@ -867,30 +951,43 @@ CONFIG_SPI_S3C24XX_GPIO=m
 # SPI Protocol Masters
 #
 # CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_HAVE_GPIO_LIB=y
 
 #
-# Dallas's 1-wire bus
+# GPIO Support
 #
-# CONFIG_W1 is not set
+# CONFIG_DEBUG_GPIO is not set
 
 #
-# Hardware Monitoring support
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
 #
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 CONFIG_HWMON_VID=m
-# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_AD7418 is not set
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
 # CONFIG_SENSORS_ADM1026 is not set
 # CONFIG_SENSORS_ADM1029 is not set
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
 # CONFIG_SENSORS_GL518SM is not set
 # CONFIG_SENSORS_GL520SM is not set
 # CONFIG_SENSORS_IT87 is not set
@@ -905,72 +1002,95 @@ CONFIG_SENSORS_LM85=m
 # CONFIG_SENSORS_LM87 is not set
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
 # CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_W83781D is not set
 # CONFIG_SENSORS_W83791D is not set
 # CONFIG_SENSORS_W83792D is not set
 # CONFIG_SENSORS_W83793 is not set
 # CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
 
 #
-# Misc devices
+# Watchdog Device Drivers
 #
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_S3C2410_WATCHDOG=y
 
 #
-# Multifunction device drivers
+# ISA-based Watchdog Cards
 #
-# CONFIG_MFD_SM501 is not set
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_WDT is not set
 
 #
-# LED devices
+# USB-based Watchdog Cards
 #
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=m
+# CONFIG_USBPCWATCHDOG is not set
 
 #
-# LED drivers
+# Sonics Silicon Backplane
 #
-CONFIG_LEDS_S3C24XX=m
-CONFIG_LEDS_H1940=m
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# LED Triggers
+# Multifunction device drivers
 #
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_MFD_SM501=y
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multimedia drivers
 #
-# CONFIG_DVB is not set
-# CONFIG_USB_DABUSB is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 # CONFIG_FB_DDC is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -978,12 +1098,19 @@ CONFIG_FB_MODE_HELPERS=y
 # CONFIG_FB_TILEBLITTING is not set
 
 #
-# Frambuffer hardware drivers
+# Frame buffer hardware drivers
 #
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_S3C2410=y
 # CONFIG_FB_S3C2410_DEBUG is not set
+CONFIG_FB_SM501=y
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -992,40 +1119,45 @@ CONFIG_FB_S3C2410=y
 # CONFIG_MDA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
 # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
 # CONFIG_FONTS is not set
 CONFIG_FONT_8x8=y
 CONFIG_FONT_8x16=y
-
-#
-# Logo configuration
-#
 # CONFIG_LOGO is not set
 
 #
 # Sound
 #
 # CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
 
 #
-# HID Devices
+# USB Input Devices
 #
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
+# CONFIG_USB_HID is not set
 
 #
-# USB support
+# USB HID Boot Protocol drivers
 #
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
 CONFIG_USB=y
 # CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
 # Miscellaneous USB options
 #
 CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_SUSPEND is not set
 # CONFIG_USB_OTG is not set
@@ -1033,18 +1165,22 @@ CONFIG_USB_DEVICEFS=y
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # USB Device Class drivers
 #
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1053,57 +1189,78 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 #
 # may also be needed; see USB_STORAGE Help for more information
 #
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-# CONFIG_USB_GTCO is not set
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
 
 #
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
+# CONFIG_USB_MICROTEK is not set
 CONFIG_USB_MON=y
 
 #
 # USB port drivers
 #
 # CONFIG_USB_USS720 is not set
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_CONSOLE is not set
+# CONFIG_USB_EZUSB is not set
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_AIRPRIME is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP2101 is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+CONFIG_USB_SERIAL_FTDI_SIO=y
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=y
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+CONFIG_USB_SERIAL_OPTION=m
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
 
 #
 # USB Miscellaneous drivers
@@ -1116,35 +1273,38 @@ CONFIG_USB_MON=y
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
 # CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
+CONFIG_USB_LED=m
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
 # CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_FTDI_ELAN is not set
 # CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
+CONFIG_USB_LD=m
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
+# CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
 
 #
-# MMC/SD Card support
+# LED drivers
 #
-# CONFIG_MMC is not set
+CONFIG_LEDS_S3C24XX=m
+CONFIG_LEDS_H1940=m
+# CONFIG_LEDS_GPIO is not set
 
 #
-# Real Time Clock
+# LED Triggers
 #
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -1158,61 +1318,86 @@ CONFIG_RTC_INTF_SYSFS=y
 CONFIG_RTC_INTF_PROC=y
 CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# RTC drivers
+# I2C RTC drivers
 #
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_X1205 is not set
 # CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
 # CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
 # CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
 # CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-CONFIG_RTC_DRV_S3C=y
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_TEST is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_S3C=y
+# CONFIG_UIO is not set
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
 # CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
+CONFIG_EXT3_FS_POSIX_ACL=y
 # CONFIG_EXT3_FS_SECURITY is not set
 # CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FS_POSIX_ACL=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-CONFIG_ROMFS_FS=y
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
 
 #
 # CD-ROM/DVD Filesystems
 #
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
 
 #
 # DOS/FAT/NT Filesystems
@@ -1222,7 +1407,9 @@ CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_FAT_DEFAULT_CODEPAGE=437
 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
 
 #
 # Pseudo filesystems
@@ -1230,10 +1417,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-# CONFIG_CONFIGFS_FS is not set
+CONFIG_CONFIGFS_FS=m
 
 #
 # Miscellaneous filesystems
@@ -1248,31 +1435,32 @@ CONFIG_RAMFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
 # CONFIG_JFFS2_FS_XATTR is not set
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 CONFIG_CRAMFS=y
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 # CONFIG_NFS_V3 is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 # CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1280,7 +1468,6 @@ CONFIG_SUNRPC=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
@@ -1302,94 +1489,93 @@ CONFIG_SOLARIS_X86_PARTITION=y
 # CONFIG_SUN_PARTITION is not set
 # CONFIG_KARMA_PARTITION is not set
 # CONFIG_EFI_PARTITION is not set
-
-#
-# Native Language Support
-#
+# CONFIG_SYSV68_PARTITION is not set
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-# CONFIG_NLS_ISO8859_1 is not set
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
 # CONFIG_DLM is not set
 
 #
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
-CONFIG_LOG_BUF_SHIFT=16
 CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
 # CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
-CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
 CONFIG_DEBUG_S3C_PORT=y
@@ -1400,21 +1586,100 @@ CONFIG_DEBUG_S3C_UART=0
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
 
 #
-# Cryptographic options
+# Compression
 #
-# CONFIG_CRYPTO is not set
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig
index 484dc9739dfc..8688362bcf7b 100644
--- a/arch/arm/configs/sam9_l9260_defconfig
+++ b/arch/arm/configs/sam9_l9260_defconfig
@@ -211,7 +211,6 @@ CONFIG_ARM_THUMB=y
 #
 # CONFIG_TICK_ONESHOT is not set
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
index aa7a01179500..7d59fb1f1cea 100644
--- a/arch/arm/configs/spitz_defconfig
+++ b/arch/arm/configs/spitz_defconfig
@@ -164,7 +164,6 @@ CONFIG_PCMCIA_PXA2XX=y
 # Kernel Features
 #
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig
index 576b8339f0d6..07dfb98df4f0 100644
--- a/arch/arm/configs/tct_hammer_defconfig
+++ b/arch/arm/configs/tct_hammer_defconfig
@@ -247,7 +247,6 @@ CONFIG_ARM_THUMB=y
 #
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=200
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig
index 6db6392806f9..8b7a431a8bfc 100644
--- a/arch/arm/configs/trizeps4_defconfig
+++ b/arch/arm/configs/trizeps4_defconfig
@@ -195,7 +195,6 @@ CONFIG_PCMCIA_PXA2XX=y
 # Kernel Features
 #
 CONFIG_PREEMPT=y
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
diff --git a/arch/arm/configs/usb-a9260_defconfig b/arch/arm/configs/usb-a9260_defconfig
new file mode 100644
index 000000000000..3680bd2df26d
--- /dev/null
+++ b/arch/arm/configs/usb-a9260_defconfig
@@ -0,0 +1,1142 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24
+# Tue Apr 15 11:39:35 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+CONFIG_ARCH_AT91SAM9260=y
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9260 Variants
+#
+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
+
+#
+# AT91SAM9260 / AT91SAM9XE Board Type
+#
+# CONFIG_MACH_AT91SAM9260EK is not set
+# CONFIG_MACH_CAM60 is not set
+# CONFIG_MACH_SAM9_L9260 is not set
+CONFIG_MACH_USB_A9260=y
+# CONFIG_MACH_QIL_A9260 is not set
+
+#
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_SLOW_CLOCK=y
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=64M console=ttyS0,115200"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_SUSPEND=y
+# CONFIG_APM_EMULATION is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_AT91=y
+CONFIG_MTD_NAND_AT91_ECC_SOFT=y
+# CONFIG_MTD_NAND_AT91_ECC_HW is not set
+# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=y
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_PERSIST is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+# CONFIG_INSTRUMENTATION is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/usb-a9263_defconfig b/arch/arm/configs/usb-a9263_defconfig
new file mode 100644
index 000000000000..48d455bc7363
--- /dev/null
+++ b/arch/arm/configs/usb-a9263_defconfig
@@ -0,0 +1,1134 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24
+# Tue Apr 15 11:15:19 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+CONFIG_ARCH_AT91SAM9263=y
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9263 Board Type
+#
+# CONFIG_MACH_AT91SAM9263EK is not set
+CONFIG_MACH_USB_A9263=y
+
+#
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_SLOW_CLOCK=y
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=64M console=ttyS0,115200"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_SUSPEND=y
+# CONFIG_APM_EMULATION is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_AT91=y
+CONFIG_MTD_NAND_AT91_ECC_SOFT=y
+# CONFIG_MTD_NAND_AT91_ECC_HW is not set
+# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=y
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_PERSIST is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+# CONFIG_INSTRUMENTATION is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index 48dca69addae..8355f88f7292 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -151,7 +151,6 @@ CONFIG_ARM_AMBA=y
 # Kernel Features
 #
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/cm_x270_defconfig b/arch/arm/configs/xm_x270_defconfig
index 5cab08397ae7..aa40d91ce599 100644
--- a/arch/arm/configs/cm_x270_defconfig
+++ b/arch/arm/configs/xm_x270_defconfig
@@ -1,13 +1,13 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22
-# Wed Jul 18 14:11:48 2007
+# Linux kernel version: 2.6.25
+# Sun May 11 15:12:52 2008
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
-# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
 # CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
@@ -21,21 +21,18 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_ZONE_DMA=y
 CONFIG_ARCH_MTD_XIP=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SWAP=y
@@ -44,13 +41,20 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
 # CONFIG_AUDIT is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=17
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
@@ -58,6 +62,7 @@ CONFIG_SYSCTL=y
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -65,24 +70,34 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_PROC_PAGE_MONITOR is not set
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
@@ -99,11 +114,12 @@ CONFIG_IOSCHED_NOOP=y
 CONFIG_IOSCHED_AS=y
 CONFIG_IOSCHED_DEADLINE=y
 CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_AS is not set
 # CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System Type
@@ -131,6 +147,8 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
 # CONFIG_ARCH_PNX4008 is not set
 CONFIG_ARCH_PXA=y
 # CONFIG_ARCH_RPC is not set
@@ -140,19 +158,41 @@ CONFIG_ARCH_PXA=y
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
 CONFIG_DMABOUNCE=y
 
 #
-# Intel PXA2xx Implementations
+# Intel PXA2xx/PXA3xx Implementations
 #
+
+#
+# Select target boards
+#
+# CONFIG_ARCH_GUMSTIX is not set
 # CONFIG_ARCH_LUBBOCK is not set
 # CONFIG_MACH_LOGICPD_PXA270 is not set
 # CONFIG_MACH_MAINSTONE is not set
 # CONFIG_ARCH_PXA_IDP is not set
 # CONFIG_PXA_SHARPSL is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
 # CONFIG_MACH_TRIZEPS4 is not set
+CONFIG_MACH_EM_X270=y
+# CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_LITTLETON is not set
 CONFIG_MACH_ARMCORE=y
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_PCM027 is not set
 CONFIG_PXA27x=y
+# CONFIG_PXA_PWM is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
 
 #
 # Processor Type
@@ -161,6 +201,7 @@ CONFIG_CPU_32=y
 CONFIG_CPU_XSCALE=y
 CONFIG_CPU_32v5=y
 CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_TLB_V4WBI=y
 CONFIG_CPU_CP15=y
@@ -182,21 +223,40 @@ CONFIG_PCI=y
 CONFIG_PCI_SYSCALL=y
 CONFIG_PCI_HOST_ITE8152=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
 # CONFIG_PCI_DEBUG is not set
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
 
 #
-# PCCARD (PCMCIA/CardBus) support
+# PC-card bridges
 #
-# CONFIG_PCCARD is not set
+CONFIG_YENTA=m
+# CONFIG_YENTA_O2 is not set
+# CONFIG_YENTA_RICOH is not set
+CONFIG_YENTA_TI=y
+# CONFIG_YENTA_ENE_TUNE is not set
+# CONFIG_YENTA_TOSHIBA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+CONFIG_PCMCIA_PXA2XX=m
+CONFIG_PCCARD_NONSTATIC=m
 
 #
 # Kernel Features
 #
-# CONFIG_TICK_ONESHOT is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
-# CONFIG_AEABI is not set
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
@@ -205,6 +265,8 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
@@ -217,11 +279,16 @@ CONFIG_ALIGNMENT_TRAP=y
 #
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE=""
+CONFIG_CMDLINE="root=1f03 mem=32M"
 # CONFIG_XIP_KERNEL is not set
 # CONFIG_KEXEC is not set
 
 #
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
 # Floating point emulation
 #
 
@@ -238,16 +305,17 @@ CONFIG_FPE_NWFPE=y
 CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
-# CONFIG_ARTHUR is not set
 
 #
 # Power management options
 #
 CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
 # CONFIG_PM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
-# CONFIG_APM_EMULATION is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=m
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
 # Networking
@@ -258,15 +326,16 @@ CONFIG_NET=y
 # Networking options
 #
 CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
+CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
+CONFIG_IP_MULTICAST=y
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
@@ -275,6 +344,7 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
 # CONFIG_ARPD is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_INET_AH is not set
@@ -285,15 +355,13 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INET_XFRM_MODE_BEET=y
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
@@ -310,10 +378,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -321,8 +385,33 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
-# CONFIG_BT is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+# CONFIG_BT_RFCOMM_TTY is not set
+CONFIG_BT_BNEP=m
+# CONFIG_BT_BNEP_MC_FILTER is not set
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIUSB=m
+CONFIG_BT_HCIUSB_SCO=y
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIDTL1 is not set
+# CONFIG_BT_HCIBT3C is not set
+# CONFIG_BT_HCIBLUECARD is not set
+# CONFIG_BT_HCIBTUART is not set
+# CONFIG_BT_HCIVHCI is not set
 # CONFIG_AF_RXRPC is not set
 
 #
@@ -331,12 +420,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
 # CONFIG_MAC80211 is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-# CONFIG_IEEE80211_CRYPT_TKIP is not set
-# CONFIG_IEEE80211_SOFTMAC is not set
+# CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -347,38 +431,47 @@ CONFIG_IEEE80211_CRYPT_CCMP=m
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
+CONFIG_FW_LOADER=m
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
-CONFIG_MTD=m
+CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
 #
-CONFIG_MTD_CHAR=m
-CONFIG_MTD_BLKDEVS=m
-CONFIG_MTD_BLOCK=m
-# CONFIG_MTD_BLOCK_RO is not set
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
 #
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_GEOMETRY is not set
 CONFIG_MTD_MAP_BANK_WIDTH_1=y
 CONFIG_MTD_MAP_BANK_WIDTH_2=y
 CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -389,15 +482,29 @@ CONFIG_MTD_CFI_I1=y
 CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0x400000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+CONFIG_MTD_PXA2XX=y
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
 # CONFIG_MTD_SHARP_SL is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
@@ -415,18 +522,19 @@ CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND=m
+CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 # CONFIG_MTD_NAND_H1900 is not set
-CONFIG_MTD_NAND_IDS=m
+CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_SHARPSL is not set
 # CONFIG_MTD_NAND_CAFE is not set
-CONFIG_MTD_NAND_CM_X270=m
+CONFIG_MTD_NAND_CM_X270=y
 # CONFIG_MTD_NAND_NANDSIM is not set
-# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
@@ -447,36 +555,13 @@ CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_UB is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=12000
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-CONFIG_IDE=m
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=m
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=m
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECD=m
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_BLK_DEV_IDESCSI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-CONFIG_IDE_PROC_FS=y
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_BLK_DEV_IDEPCI is not set
-# CONFIG_IDEPCI_PCIBUS_ORDER is not set
-# CONFIG_IDE_ARM is not set
-# CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
 
 #
 # SCSI device support
@@ -486,7 +571,7 @@ CONFIG_SCSI=y
 CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
-# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
 # SCSI support type (disk, tape, CD-ROM)
@@ -513,12 +598,9 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_BLK_DEV_3W_XXXX_RAID is not set
 # CONFIG_SCSI_3W_9XXX is not set
@@ -529,6 +611,7 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_AIC79XX is not set
 # CONFIG_SCSI_AIC94XX is not set
 # CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
 # CONFIG_SCSI_ARCMSR is not set
 # CONFIG_MEGARAID_NEWGEN is not set
 # CONFIG_MEGARAID_LEGACY is not set
@@ -539,8 +622,10 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_IPS is not set
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_STEX is not set
 # CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
 # CONFIG_SCSI_QLOGIC_1280 is not set
 # CONFIG_SCSI_QLA_FC is not set
 # CONFIG_SCSI_QLA_ISCSI is not set
@@ -550,16 +635,69 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_NSP32 is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_SRP is not set
-# CONFIG_ATA is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+CONFIG_ATA=m
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_SATA_PMP is not set
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+CONFIG_PATA_PCMCIA=m
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_PLATFORM is not set
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
 # CONFIG_FUSION is not set
-# CONFIG_FUSION_SPI is not set
-# CONFIG_FUSION_FC is not set
-# CONFIG_FUSION_SAS is not set
 
 #
 # IEEE 1394 (FireWire) support
@@ -574,6 +712,7 @@ CONFIG_NETDEVICES=y
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_VETH is not set
 # CONFIG_ARCNET is not set
 # CONFIG_PHYLIB is not set
 CONFIG_NET_ETHERNET=y
@@ -585,64 +724,65 @@ CONFIG_MII=y
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_SMC91X is not set
 CONFIG_DM9000=y
+CONFIG_DM9000_DEBUGLEVEL=1
 # CONFIG_SMC911X is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 CONFIG_NET_PCI=y
 # CONFIG_PCNET32 is not set
 # CONFIG_AMD8111_ETH is not set
 # CONFIG_ADAPTEC_STARFIRE is not set
 # CONFIG_B44 is not set
 # CONFIG_FORCEDETH is not set
-# CONFIG_DGRS is not set
 # CONFIG_EEPRO100 is not set
 # CONFIG_E100 is not set
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
 # CONFIG_NE2K_PCI is not set
 # CONFIG_8139CP is not set
-CONFIG_8139TOO=m
+CONFIG_8139TOO=y
 # CONFIG_8139TOO_PIO is not set
 # CONFIG_8139TOO_TUNE_TWISTER is not set
 # CONFIG_8139TOO_8129 is not set
 # CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
 # CONFIG_SC92031 is not set
-CONFIG_NETDEV_1000=y
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-# CONFIG_E1000 is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_VIA_VELOCITY is not set
-# CONFIG_TIGON3 is not set
-# CONFIG_BNX2 is not set
-# CONFIG_QLA3XXX is not set
-# CONFIG_ATL1 is not set
-CONFIG_NETDEV_10000=y
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_CHELSIO_T3 is not set
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-# CONFIG_NETXEN_NIC is not set
-# CONFIG_MLX4_CORE is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
 # CONFIG_TR is not set
 
 #
 # Wireless LAN
 #
 # CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+CONFIG_LIBERTAS=m
+# CONFIG_LIBERTAS_USB is not set
+# CONFIG_LIBERTAS_CS is not set
+CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
 
 #
 # USB Network Adapters
@@ -651,15 +791,24 @@ CONFIG_NETDEV_10000=y
 # CONFIG_USB_KAWETH is not set
 # CONFIG_USB_PEGASUS is not set
 # CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
 # CONFIG_USB_USBNET is not set
+# CONFIG_NET_PCMCIA is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
 # CONFIG_SLIP is not set
+CONFIG_SLHC=m
 # CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -675,20 +824,32 @@ CONFIG_INPUT=y
 #
 # Userland interfaces
 #
-# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_APMPOWER is not set
 
 #
 # Input Device Drivers
 #
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_PXA27x=m
+# CONFIG_KEYBOARD_GPIO is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
@@ -697,13 +858,22 @@ CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
 CONFIG_TOUCHSCREEN_UCB1400=m
+CONFIG_TOUCHSCREEN_WM97XX=m
+# CONFIG_TOUCHSCREEN_WM9705 is not set
+CONFIG_TOUCHSCREEN_WM9712=y
+# CONFIG_TOUCHSCREEN_WM9713 is not set
+# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_INPUT_MISC is not set
 
 #
 # Hardware I/O ports
 #
-# CONFIG_SERIO is not set
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
 
 #
@@ -713,7 +883,9 @@ CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
@@ -730,83 +902,141 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_HW_RANDOM=m
+# CONFIG_HW_RANDOM is not set
 # CONFIG_NVRAM is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_DEVPORT=y
-# CONFIG_I2C is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+CONFIG_I2C_PXA=y
+# CONFIG_I2C_PXA_SLAVE is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_HAVE_GPIO_LIB=y
 
 #
-# SPI support
+# GPIO Support
 #
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-# CONFIG_W1 is not set
-# CONFIG_HWMON is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_PHANTOM is not set
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_SGI_IOC4 is not set
-# CONFIG_TIFM_CORE is not set
+# CONFIG_DEBUG_GPIO is not set
 
 #
-# Multifunction device drivers
+# I2C GPIO expanders:
 #
-# CONFIG_MFD_SM501 is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
 
 #
-# LED devices
+# SPI GPIO expanders:
 #
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# LED drivers
+# Sonics Silicon Backplane
 #
-CONFIG_LEDS_CM_X270=y
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# LED Triggers
+# Multifunction device drivers
 #
-CONFIG_LEDS_TRIGGERS=y
-# CONFIG_LEDS_TRIGGER_TIMER is not set
-# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
-CONFIG_DAB=y
-# CONFIG_USB_DABUSB is not set
 
 #
-# Graphics support
+# Multimedia drivers
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_DAB is not set
 
 #
-# Display device support
+# Graphics support
 #
-# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_DRM is not set
 # CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
 CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
@@ -842,9 +1072,17 @@ CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_ARK is not set
 # CONFIG_FB_PM3 is not set
 CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_PARAMETERS is not set
+# CONFIG_FB_PXA_SMARTPANEL is not set
+CONFIG_FB_PXA_PARAMETERS=y
 CONFIG_FB_MBX=m
+# CONFIG_FB_AM200EPD is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -904,10 +1142,12 @@ CONFIG_SND_AC97_CODEC=m
 # CONFIG_SND_AU8810 is not set
 # CONFIG_SND_AU8820 is not set
 # CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
 # CONFIG_SND_AZT3328 is not set
 # CONFIG_SND_BT87X is not set
 # CONFIG_SND_CA0106 is not set
 # CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
 # CONFIG_SND_CS4281 is not set
 # CONFIG_SND_CS46XX is not set
 # CONFIG_SND_DARLA20 is not set
@@ -932,6 +1172,7 @@ CONFIG_SND_AC97_CODEC=m
 # CONFIG_SND_HDA_INTEL is not set
 # CONFIG_SND_HDSP is not set
 # CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
 # CONFIG_SND_ICE1712 is not set
 # CONFIG_SND_ICE1724 is not set
 # CONFIG_SND_INTEL8X0 is not set
@@ -949,6 +1190,7 @@ CONFIG_SND_AC97_CODEC=m
 # CONFIG_SND_TRIDENT is not set
 # CONFIG_SND_VIA82XX is not set
 # CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
 # CONFIG_SND_VX222 is not set
 # CONFIG_SND_YMFPCI is not set
 # CONFIG_SND_AC97_POWER_SAVE is not set
@@ -966,18 +1208,33 @@ CONFIG_SND_PXA2XX_AC97=m
 # CONFIG_SND_USB_CAIAQ is not set
 
 #
+# PCMCIA devices
+#
+# CONFIG_SND_VXPOCKET is not set
+# CONFIG_SND_PDAUDIOCF is not set
+
+#
 # System on Chip audio support
 #
 # CONFIG_SND_SOC is not set
 
 #
+# ALSA SoC audio for Freescale SOCs
+#
+
+#
+# SoC Audio for the Texas Instruments OMAP
+#
+
+#
 # Open Sound System
 #
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=m
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
 
 #
 # USB Input Devices
@@ -992,6 +1249,7 @@ CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
 CONFIG_USB=y
 # CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
 # Miscellaneous USB options
@@ -1000,8 +1258,9 @@ CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_PERSIST is not set
 # CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # USB Host Controller Drivers
@@ -1033,13 +1292,16 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
 # CONFIG_USB_STORAGE_SDDR55 is not set
 # CONFIG_USB_STORAGE_JUMPSHOT is not set
 # CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
 # CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 # CONFIG_USB_LIBUSUAL is not set
 
 #
@@ -1052,10 +1314,6 @@ CONFIG_USB_MON=y
 #
 # USB port drivers
 #
-
-#
-# USB Serial Converter support
-#
 # CONFIG_USB_SERIAL is not set
 
 #
@@ -1080,14 +1338,6 @@ CONFIG_USB_MON=y
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
 # CONFIG_USB_GADGET is not set
 CONFIG_MMC=m
 # CONFIG_MMC_DEBUG is not set
@@ -1098,6 +1348,7 @@ CONFIG_MMC=m
 #
 CONFIG_MMC_BLOCK=m
 CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
 
 #
 # MMC/SD Host Controller Drivers
@@ -1105,10 +1356,22 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 CONFIG_MMC_PXA=m
 # CONFIG_MMC_SDHCI is not set
 # CONFIG_MMC_TIFM_SD is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
 
 #
-# Real Time Clock
+# LED drivers
 #
+# CONFIG_LEDS_GPIO is not set
+CONFIG_LEDS_CM_X270=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -1125,11 +1388,32 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_TEST is not set
 
 #
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+
+#
+# SPI RTC drivers
+#
+
+#
 # Platform RTC drivers
 #
 # CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
 CONFIG_RTC_DRV_V3020=y
@@ -1138,19 +1422,7 @@ CONFIG_RTC_DRV_V3020=y
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_SA1100=y
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
+# CONFIG_UIO is not set
 
 #
 # File systems
@@ -1164,20 +1436,16 @@ CONFIG_EXT3_FS_XATTR=y
 # CONFIG_EXT3_FS_SECURITY is not set
 # CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -1191,9 +1459,9 @@ CONFIG_DNOTIFY=y
 #
 # DOS/FAT/NT Filesystems
 #
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
+CONFIG_FAT_FS=m
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_CODEPAGE=437
 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
@@ -1207,7 +1475,6 @@ CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -1220,22 +1487,30 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 # CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
@@ -1245,9 +1520,13 @@ CONFIG_SUNRPC=y
 # CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=y
-# CONFIG_SMB_NLS_DEFAULT is not set
-# CONFIG_CIFS is not set
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
@@ -1255,15 +1534,27 @@ CONFIG_SMB_FS=y
 #
 # Partition Types
 #
-# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=m
 CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_437=m
 # CONFIG_NLS_CODEPAGE_737 is not set
 # CONFIG_NLS_CODEPAGE_775 is not set
 # CONFIG_NLS_CODEPAGE_850 is not set
@@ -1287,7 +1578,7 @@ CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_CODEPAGE_1250 is not set
 # CONFIG_NLS_CODEPAGE_1251 is not set
 # CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_1=m
 # CONFIG_NLS_ISO8859_2 is not set
 # CONFIG_NLS_ISO8859_3 is not set
 # CONFIG_NLS_ISO8859_4 is not set
@@ -1300,53 +1591,52 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_ISO8859_15 is not set
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
+CONFIG_NLS_UTF8=m
 # CONFIG_DLM is not set
 
 #
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_MAGIC_SYSRQ=y
+CONFIG_FRAME_WARN=0
+# CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
 # CONFIG_DETECT_SOFTLOCKUP is not set
-CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHED_DEBUG is not set
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
 # CONFIG_DEBUG_LOCK_ALLOC is not set
 # CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
 # CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
-CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
 
@@ -1355,55 +1645,96 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=m
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_MANAGER=m
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
 # CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
 # CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_LZO is not set
+# CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
diff --git a/arch/arm/kernel/atags.c b/arch/arm/kernel/atags.c
index 64c420805e6f..42a1a1415fa6 100644
--- a/arch/arm/kernel/atags.c
+++ b/arch/arm/kernel/atags.c
@@ -1,5 +1,4 @@
 #include <linux/slab.h>
-#include <linux/kexec.h>
 #include <linux/proc_fs.h>
 #include <asm/setup.h>
 #include <asm/types.h>
@@ -7,9 +6,8 @@
 
 struct buffer {
         size_t size;
-        char *data;
+        char data[];
 };
-static struct buffer tags_buffer;
 
 static int
 read_buffer(char* page, char** start, off_t off, int count,
@@ -29,58 +27,57 @@ read_buffer(char* page, char** start, off_t off, int count,
         return count;
 }
 
-
-static int
-create_proc_entries(void)
-{
-        struct proc_dir_entry* tags_entry;
-
-        tags_entry = create_proc_read_entry("atags", 0400, NULL, read_buffer, &tags_buffer);
-        if (!tags_entry)
-                return -ENOMEM;
-
-        return 0;
-}
-
-
-static char __initdata atags_copy_buf[KEXEC_BOOT_PARAMS_SIZE];
-static char __initdata *atags_copy;
+#define BOOT_PARAMS_SIZE 1536
+static char __initdata atags_copy[BOOT_PARAMS_SIZE];
 
 void __init save_atags(const struct tag *tags)
 {
-        atags_copy = atags_copy_buf;
-        memcpy(atags_copy, tags, KEXEC_BOOT_PARAMS_SIZE);
+        memcpy(atags_copy, tags, sizeof(atags_copy));
 }
 
-
 static int __init init_atags_procfs(void)
 {
-        struct tag *tag;
-        int error;
+        /*
+         * This cannot go into save_atags() because kmalloc and proc don't work
+         * yet when it is called.
+         */
+        struct proc_dir_entry *tags_entry;
+        struct tag *tag = (struct tag *)atags_copy;
+        struct buffer *b;
+        size_t size;
 
-        if (!atags_copy) {
-                printk(KERN_WARNING "Exporting ATAGs: No saved tags found\n");
-                return -EIO;
+        if (tag->hdr.tag != ATAG_CORE) {
+                printk(KERN_INFO "No ATAGs?");
+                return -EINVAL;
         }
 
-        for (tag = (struct tag *) atags_copy; tag->hdr.size; tag = tag_next(tag))
+        for (; tag->hdr.size; tag = tag_next(tag))
                 ;
 
-        tags_buffer.size = ((char *) tag - atags_copy) + sizeof(tag->hdr);
-        tags_buffer.data = kmalloc(tags_buffer.size, GFP_KERNEL);
-        if (tags_buffer.data == NULL)
-                return -ENOMEM;
-        memcpy(tags_buffer.data, atags_copy, tags_buffer.size);
-
-        error = create_proc_entries();
-        if (error) {
-                printk(KERN_ERR "Exporting ATAGs: not enough memory\n");
-                kfree(tags_buffer.data);
-                tags_buffer.size = 0;
-                tags_buffer.data = NULL;
-        }
+        /* include the terminating ATAG_NONE */
+        size = (char *)tag - atags_copy + sizeof(struct tag_header);
 
-        return error;
-}
+        WARN_ON(tag->hdr.tag != ATAG_NONE);
+
+        b = kmalloc(sizeof(*b) + size, GFP_KERNEL);
+        if (!b)
+                goto nomem;
 
+        b->size = size;
+        memcpy(b->data, atags_copy, size);
+
+        tags_entry = create_proc_read_entry("atags", 0400,
+                        NULL, read_buffer, b);
+
+        if (!tags_entry)
+                goto nomem;
+
+        return 0;
+
+nomem:
+        kfree(b);
+        printk(KERN_ERR "Exporting ATAGs: not enough memory\n");
+
+        return -ENOMEM;
+}
 arch_initcall(init_atags_procfs);
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index a53c0aba5c14..8bfd299bfe77 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -680,7 +680,7 @@ static int __init ecard_probeirqhw(void)
 #define IO_EC_MEMC8_BASE 0
 #endif
 
-unsigned int __ecard_address(ecard_t *ec, card_type_t type, card_speed_t speed)
+static unsigned int __ecard_address(ecard_t *ec, card_type_t type, card_speed_t speed)
 {
         unsigned long address = 0;
         int slot = ec->slot_no;
@@ -1002,7 +1002,7 @@ ecard_probe(int slot, card_type_t type)
         }
 
         rc = -ENODEV;
-        if ((ec->podaddr = ecard_address(ec, type, ECARD_SYNC)) == 0)
+        if ((ec->podaddr = __ecard_address(ec, type, ECARD_SYNC)) == 0)
                 goto nodev;
 
         cid.r_zero = 1;
@@ -1141,10 +1141,10 @@ static int ecard_drv_probe(struct device *dev)
 
         id = ecard_match_device(drv->id_table, ec);
 
-        ecard_claim(ec);
+        ec->claimed = 1;
         ret = drv->probe(ec, id);
         if (ret)
-                ecard_release(ec);
+                ec->claimed = 0;
         return ret;
 }
 
@@ -1154,7 +1154,7 @@ static int ecard_drv_remove(struct device *dev)
         struct ecard_driver *drv = ECARD_DRV(dev->driver);
 
         drv->remove(ec);
-        ecard_release(ec);
+        ec->claimed = 0;
 
         /*
          * Restore the default operations.  We ensure that the
@@ -1182,7 +1182,7 @@ static void ecard_drv_shutdown(struct device *dev)
         if (dev->driver) {
                 if (drv->shutdown)
                         drv->shutdown(ec);
-                ecard_release(ec);
+                ec->claimed = 0;
         }
 
         /*
@@ -1239,7 +1239,6 @@ static int ecard_bus_init(void)
 postcore_initcall(ecard_bus_init);
 
 EXPORT_SYMBOL(ecard_readchunk);
-EXPORT_SYMBOL(__ecard_address);
 EXPORT_SYMBOL(ecard_register_driver);
 EXPORT_SYMBOL(ecard_remove_driver);
 EXPORT_SYMBOL(ecard_bus_type);
diff --git a/arch/arm/kernel/ecard.h b/arch/arm/kernel/ecard.h
index d7c2dacf935d..4642d436be2a 100644
--- a/arch/arm/kernel/ecard.h
+++ b/arch/arm/kernel/ecard.h
@@ -54,3 +54,16 @@ struct ex_chunk_dir {
 #define c_len(x)        ((x)->r_len[0]|((x)->r_len[1]<<8)|((x)->r_len[2]<<16))
 #define c_start(x)      ((x)->r_start)
 };
+
+typedef enum ecard_type {               /* Cards address space          */
+        ECARD_IOC,
+        ECARD_MEMC,
+        ECARD_EASI
+} card_type_t;
+
+typedef enum {                          /* Speed for ECARD_IOC space    */
+        ECARD_SLOW       = 0,
+        ECARD_MEDIUM     = 1,
+        ECARD_FAST       = 2,
+        ECARD_SYNC       = 3
+} card_speed_t;
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 46bf2ede6128..199b3680118b 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -133,10 +133,8 @@ static void default_idle(void)
                 cpu_relax();
         else {
                 local_irq_disable();
-                if (!need_resched()) {
-                        timer_dyn_reprogram();
+                if (!need_resched())
                         arch_idle();
-                }
                 local_irq_enable();
         }
 }
diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c
index ae31deb2d065..90e0c35ae60d 100644
--- a/arch/arm/kernel/stacktrace.c
+++ b/arch/arm/kernel/stacktrace.c
@@ -36,6 +36,7 @@ EXPORT_SYMBOL(walk_stackframe);
 #ifdef CONFIG_STACKTRACE
 struct stack_trace_data {
         struct stack_trace *trace;
+        unsigned int no_sched_functions;
         unsigned int skip;
 };
 
@@ -43,27 +44,52 @@ static int save_trace(struct stackframe *frame, void *d)
 {
         struct stack_trace_data *data = d;
         struct stack_trace *trace = data->trace;
+        unsigned long addr = frame->lr;
 
+        if (data->no_sched_functions && in_sched_functions(addr))
+                return 0;
         if (data->skip) {
                 data->skip--;
                 return 0;
         }
 
-        trace->entries[trace->nr_entries++] = frame->lr;
+        trace->entries[trace->nr_entries++] = addr;
 
         return trace->nr_entries >= trace->max_entries;
 }
 
-void save_stack_trace(struct stack_trace *trace)
+void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
 {
         struct stack_trace_data data;
         unsigned long fp, base;
 
         data.trace = trace;
         data.skip = trace->skip;
-        base = (unsigned long)task_stack_page(current);
-        asm("mov %0, fp" : "=r" (fp));
+        base = (unsigned long)task_stack_page(tsk);
+
+        if (tsk != current) {
+#ifdef CONFIG_SMP
+                /*
+                 * What guarantees do we have here that 'tsk'
+                 * is not running on another CPU?
+                 */
+                BUG();
+#else
+                data.no_sched_functions = 1;
+                fp = thread_saved_fp(tsk);
+#endif
+        } else {
+                data.no_sched_functions = 0;
+                asm("mov %0, fp" : "=r" (fp));
+        }
 
         walk_stackframe(fp, base, base + THREAD_SIZE, save_trace, &data);
+        if (trace->nr_entries < trace->max_entries)
+                trace->entries[trace->nr_entries++] = ULONG_MAX;
+}
+
+void save_stack_trace(struct stack_trace *trace)
+{
+        save_stack_trace_tsk(current, trace);
 }
 #endif
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index b5867eca1d0b..cc5145b28e7f 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -365,108 +365,6 @@ static struct sysdev_class timer_sysclass = {
         .resume         = timer_resume,
 };
 
-#ifdef CONFIG_NO_IDLE_HZ
-static int timer_dyn_tick_enable(void)
-{
-        struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick;
-        unsigned long flags;
-        int ret = -ENODEV;
-
-        if (dyn_tick) {
-                spin_lock_irqsave(&dyn_tick->lock, flags);
-                ret = 0;
-                if (!(dyn_tick->state & DYN_TICK_ENABLED)) {
-                        ret = dyn_tick->enable();
-
-                        if (ret == 0)
-                                dyn_tick->state |= DYN_TICK_ENABLED;
-                }
-                spin_unlock_irqrestore(&dyn_tick->lock, flags);
-        }
-
-        return ret;
-}
-
-static int timer_dyn_tick_disable(void)
-{
-        struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick;
-        unsigned long flags;
-        int ret = -ENODEV;
-
-        if (dyn_tick) {
-                spin_lock_irqsave(&dyn_tick->lock, flags);
-                ret = 0;
-                if (dyn_tick->state & DYN_TICK_ENABLED) {
-                        ret = dyn_tick->disable();
-
-                        if (ret == 0)
-                                dyn_tick->state &= ~DYN_TICK_ENABLED;
-                }
-                spin_unlock_irqrestore(&dyn_tick->lock, flags);
-        }
-
-        return ret;
-}
-
-/*
- * Reprogram the system timer for at least the calculated time interval.
- * This function should be called from the idle thread with IRQs disabled,
- * immediately before sleeping.
- */
-void timer_dyn_reprogram(void)
-{
-        struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick;
-        unsigned long next, seq, flags;
-
-        if (!dyn_tick)
-                return;
-
-        spin_lock_irqsave(&dyn_tick->lock, flags);
-        if (dyn_tick->state & DYN_TICK_ENABLED) {
-                next = next_timer_interrupt();
-                do {
-                        seq = read_seqbegin(&xtime_lock);
-                        dyn_tick->reprogram(next - jiffies);
-                } while (read_seqretry(&xtime_lock, seq));
-        }
-        spin_unlock_irqrestore(&dyn_tick->lock, flags);
-}
-
-static ssize_t timer_show_dyn_tick(struct sys_device *dev, char *buf)
-{
-        return sprintf(buf, "%i\n",
-                       (system_timer->dyn_tick->state & DYN_TICK_ENABLED) >> 1);
-}
-
-static ssize_t timer_set_dyn_tick(struct sys_device *dev, const char *buf,
-                                  size_t count)
-{
-        unsigned int enable = simple_strtoul(buf, NULL, 2);
-
-        if (enable)
-                timer_dyn_tick_enable();
-        else
-                timer_dyn_tick_disable();
-
-        return count;
-}
-static SYSDEV_ATTR(dyn_tick, 0644, timer_show_dyn_tick, timer_set_dyn_tick);
-
-/*
- * dyntick=enable|disable
- */
-static char dyntick_str[4] __initdata = "";
-
-static int __init dyntick_setup(char *str)
-{
-        if (str)
-                strlcpy(dyntick_str, str, sizeof(dyntick_str));
-        return 1;
-}
-
-__setup("dyntick=", dyntick_setup);
-#endif
-
 static int __init timer_init_sysfs(void)
 {
         int ret = sysdev_class_register(&timer_sysclass);
@@ -475,19 +373,6 @@ static int __init timer_init_sysfs(void)
                 ret = sysdev_register(&system_timer->dev);
         }
 
-#ifdef CONFIG_NO_IDLE_HZ
-        if (ret == 0 && system_timer->dyn_tick) {
-                ret = sysdev_create_file(&system_timer->dev, &attr_dyn_tick);
-
-                /*
-                 * Turn on dynamic tick after calibrate delay
-                 * for correct bogomips
-                 */
-                if (ret == 0 && dyntick_str[0] == 'e')
-                        ret = timer_dyn_tick_enable();
-        }
-#endif
-
         return ret;
 }
 
@@ -500,10 +385,5 @@ void __init time_init(void)
                 system_timer->offset = dummy_gettimeoffset;
 #endif
         system_timer->init();
-
-#ifdef CONFIG_NO_IDLE_HZ
-        if (system_timer->dyn_tick)
-                spin_lock_init(&system_timer->dyn_tick->lock);
-#endif
 }
 
diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index cab355c0c1f7..139cce646055 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -13,14 +13,6 @@
  */
 
 /*
- * This can be used to enable code to cacheline align the source pointer.
- * Experiments on tested architectures (StrongARM and XScale) didn't show
- * this a worthwhile thing to do.  That might be different in the future.
- */
-//#define CALGN(code...)        code
-#define CALGN(code...)
-
-/*
  * Theory of operation
  * -------------------
  *
@@ -82,7 +74,7 @@
                 stmfd   sp!, {r5 - r8}
                 blt     5f
 
-        CALGN(  ands    ip, r1, #31             )
+        CALGN(  ands    ip, r0, #31             )
         CALGN(  rsb     r3, ip, #32             )
         CALGN(  sbcnes  r4, r3, r2              )  @ C is always set here
         CALGN(  bcs     2f                      )
@@ -168,7 +160,7 @@
                 subs    r2, r2, #28
                 blt     14f
 
-        CALGN(  ands    ip, r1, #31             )
+        CALGN(  ands    ip, r0, #31             )
         CALGN(  rsb     ip, ip, #32             )
         CALGN(  sbcnes  r4, ip, r2              )  @ C is always set here
         CALGN(  subcc   r2, r2, ip              )
diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S
index ef7fddc14ac9..2e301b7bd8f1 100644
--- a/arch/arm/lib/memmove.S
+++ b/arch/arm/lib/memmove.S
@@ -13,14 +13,6 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-/*
- * This can be used to enable code to cacheline align the source pointer.
- * Experiments on tested architectures (StrongARM and XScale) didn't show
- * this a worthwhile thing to do.  That might be different in the future.
- */
-//#define CALGN(code...)        code
-#define CALGN(code...)
-
                 .text
 
 /*
@@ -55,11 +47,12 @@ ENTRY(memmove)
                 stmfd   sp!, {r5 - r8}
                 blt     5f
 
-        CALGN(  ands    ip, r1, #31             )
+        CALGN(  ands    ip, r0, #31             )
         CALGN(  sbcnes  r4, ip, r2              )  @ C is always set here
         CALGN(  bcs     2f                      )
         CALGN(  adr     r4, 6f                  )
         CALGN(  subs    r2, r2, ip              )  @ C is set here
+        CALGN(  rsb     ip, ip, #32             )
         CALGN(  add     pc, r4, ip              )
 
         PLD(    pld     [r1, #-4]               )
@@ -138,8 +131,7 @@ ENTRY(memmove)
                 subs    r2, r2, #28
                 blt     14f
 
-        CALGN(  ands    ip, r1, #31             )
-        CALGN(  rsb     ip, ip, #32             )
+        CALGN(  ands    ip, r0, #31             )
         CALGN(  sbcnes  r4, ip, r2              )  @ C is always set here
         CALGN(  subcc   r2, r2, ip              )
         CALGN(  bcc     15f                     )
diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S
index 95b110b07a89..b477d4ac88ef 100644
--- a/arch/arm/lib/memset.S
+++ b/arch/arm/lib/memset.S
@@ -39,6 +39,9 @@ ENTRY(memset)
         mov     r3, r1
         cmp     r2, #16
         blt     4f
+
+#if ! CALGN(1)+0
+
 /*
  * We need an extra register for this loop - save the return address and
  * use the LR
@@ -64,6 +67,49 @@ ENTRY(memset)
         stmneia r0!, {r1, r3, ip, lr}
         ldr     lr, [sp], #4
 
+#else
+
+/*
+ * This version aligns the destination pointer in order to write
+ * whole cache lines at once.
+ */
+
+        stmfd   sp!, {r4-r7, lr}
+        mov     r4, r1
+        mov     r5, r1
+        mov     r6, r1
+        mov     r7, r1
+        mov     ip, r1
+        mov     lr, r1
+
+        cmp     r2, #96
+        tstgt   r0, #31
+        ble     3f
+
+        and     ip, r0, #31
+        rsb     ip, ip, #32
+        sub     r2, r2, ip
+        movs    ip, ip, lsl #(32 - 4)
+        stmcsia r0!, {r4, r5, r6, r7}
+        stmmiia r0!, {r4, r5}
+        tst     ip, #(1 << 30)
+        mov     ip, r1
+        strne   r1, [r0], #4
+
+3:      subs    r2, r2, #64
+        stmgeia r0!, {r1, r3-r7, ip, lr}
+        stmgeia r0!, {r1, r3-r7, ip, lr}
+        bgt     3b
+        ldmeqfd sp!, {r4-r7, pc}
+
+        tst     r2, #32
+        stmneia r0!, {r1, r3-r7, ip, lr}
+        tst     r2, #16
+        stmneia r0!, {r4-r7}
+        ldmfd   sp!, {r4-r7, lr}
+
+#endif
+
 4:      tst     r2, #8
         stmneia r0!, {r1, r3}
         tst     r2, #4
diff --git a/arch/arm/lib/memzero.S b/arch/arm/lib/memzero.S
index abf2508e8221..b8f79d80ee9b 100644
--- a/arch/arm/lib/memzero.S
+++ b/arch/arm/lib/memzero.S
@@ -39,6 +39,9 @@ ENTRY(__memzero)
  */
         cmp     r1, #16                 @ 1 we can skip this chunk if we
         blt     4f                      @ 1 have < 16 bytes
+
+#if ! CALGN(1)+0
+
 /*
  * We need an extra register for this loop - save the return address and
  * use the LR
@@ -64,6 +67,47 @@ ENTRY(__memzero)
         stmneia r0!, {r2, r3, ip, lr}   @ 4
         ldr     lr, [sp], #4            @ 1
 
+#else
+
+/*
+ * This version aligns the destination pointer in order to write
+ * whole cache lines at once.
+ */
+
+        stmfd   sp!, {r4-r7, lr}
+        mov     r4, r2
+        mov     r5, r2
+        mov     r6, r2
+        mov     r7, r2
+        mov     ip, r2
+        mov     lr, r2
+
+        cmp     r1, #96
+        andgts  ip, r0, #31
+        ble     3f
+
+        rsb     ip, ip, #32
+        sub     r1, r1, ip
+        movs    ip, ip, lsl #(32 - 4)
+        stmcsia r0!, {r4, r5, r6, r7}
+        stmmiia r0!, {r4, r5}
+        movs    ip, ip, lsl #2
+        strcs   r2, [r0], #4
+
+3:      subs    r1, r1, #64
+        stmgeia r0!, {r2-r7, ip, lr}
+        stmgeia r0!, {r2-r7, ip, lr}
+        bgt     3b
+        ldmeqfd sp!, {r4-r7, pc}
+
+        tst     r1, #32
+        stmneia r0!, {r2-r7, ip, lr}
+        tst     r1, #16
+        stmneia r0!, {r4-r7}
+        ldmfd   sp!, {r4-r7, lr}
+
+#endif
+
 4:      tst     r1, #8                  @ 1 8 bytes or more?
         stmneia r0!, {r2, r3}           @ 2
         tst     r1, #4                  @ 1 4 bytes or more?
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 0fc07b6db749..5bad6b9b00d7 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -30,6 +30,11 @@ config ARCH_AT91SAM9RL
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
 
+config ARCH_AT91SAM9G20
+        bool "AT91SAM9G20"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+
 config ARCH_AT91CAP9
         bool "AT91CAP9"
         select GENERIC_TIME
@@ -126,6 +131,12 @@ config MACH_ECBAT91
           Select this if you are using emQbit's ECB_AT91 board.
           <http://wiki.emqbit.com/free-ecb-at91>
 
+config MACH_YL9200
+        bool "ucDragon YL-9200"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using the ucDragon YL-9200 board.
+
 endif
 
 # ----------------------------------------------------------
@@ -164,6 +175,20 @@ config MACH_SAM9_L9260
           Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
           <http://www.olimex.com/dev/sam9-L9260.html>
 
+config MACH_USB_A9260
+        bool "CALAO USB-A9260"
+        depends on ARCH_AT91SAM9260
+        help
+          Select this if you are using a Calao Systems USB-A9260.
+          <http://www.calao-systems.com>
+
+config MACH_QIL_A9260
+        bool "CALAO QIL-A9260 board"
+        depends on ARCH_AT91SAM9260
+        help
+          Select this if you are using a Calao Systems QIL-A9260 Board.
+          <http://www.calao-systems.com>
+
 endif
 
 # ----------------------------------------------------------
@@ -194,6 +219,13 @@ config MACH_AT91SAM9263EK
           Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
           <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
 
+config MACH_USB_A9263
+        bool "CALAO USB-A9263"
+        depends on ARCH_AT91SAM9263
+        help
+          Select this if you are using a Calao Systems USB-A9263.
+          <http://www.calao-systems.com>
+
 endif
 
 # ----------------------------------------------------------
@@ -212,6 +244,20 @@ endif
 
 # ----------------------------------------------------------
 
+if ARCH_AT91SAM9G20
+
+comment "AT91SAM9G20 Board Type"
+
+config MACH_AT91SAM9G20EK
+        bool "Atmel AT91SAM9G20-EK Evaluation Kit"
+        depends on ARCH_AT91SAM9G20
+        help
+          Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit.
+
+endif
+
+# ----------------------------------------------------------
+
 if ARCH_AT91CAP9
 
 comment "AT91CAP9 Board Type"
@@ -247,13 +293,13 @@ comment "AT91 Board Options"
 
 config MTD_AT91_DATAFLASH_CARD
         bool "Enable DataFlash Card support"
-        depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK || MACH_SAM9_L9260 || MACH_ECBAT91)
+        depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK)
         help
           Enable support for the DataFlash card.
 
 config MTD_NAND_AT91_BUSWIDTH_16
         bool "Enable 16-bit data bus interface to NAND flash"
-        depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK)
+        depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91CAP9ADK)
         help
           On AT91SAM926x boards both types of NAND flash can be present
           (8 and 16 bit data bus width).
@@ -302,15 +348,15 @@ config AT91_EARLY_USART2
 
 config AT91_EARLY_USART3
         bool "USART3"
-        depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260)
+        depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
 
 config AT91_EARLY_USART4
         bool "USART4"
-        depends on ARCH_AT91SAM9260
+        depends on ARCH_AT91SAM9260 || ARCH_AT91SAM9G20
 
 config AT91_EARLY_USART5
         bool "USART5"
-        depends on ARCH_AT91SAM9260
+        depends on ARCH_AT91SAM9260 || ARCH_AT91SAM9G20
 
 endchoice
 
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 8d9bc0153b18..7d641f97516b 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_AT91SAM9260)	+= at91sam9260.o at91sam926x_time.o at91sam9260_d
 obj-$(CONFIG_ARCH_AT91SAM9261)  += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9263)  += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9RL)   += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o
 obj-$(CONFIG_ARCH_AT91CAP9)     += at91cap9.o at91sam926x_time.o at91cap9_devices.o
 obj-$(CONFIG_ARCH_AT91X40)      += at91x40.o at91x40_time.o
 
@@ -30,21 +31,28 @@ obj-$(CONFIG_MACH_ATEB9200)	+= board-eb9200.o
 obj-$(CONFIG_MACH_KAFA)         += board-kafa.o
 obj-$(CONFIG_MACH_PICOTUX2XX)   += board-picotux200.o
 obj-$(CONFIG_MACH_ECBAT91)      += board-ecbat91.o
+obj-$(CONFIG_MACH_YL9200)       += board-yl-9200.o
 
 # AT91SAM9260 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
 obj-$(CONFIG_MACH_CAM60)        += board-cam60.o
 obj-$(CONFIG_MACH_SAM9_L9260)   += board-sam9-l9260.o
+obj-$(CONFIG_MACH_USB_A9260)    += board-usb-a9260.o
+obj-$(CONFIG_MACH_QIL_A9260)    += board-qil-a9260.o
 
 # AT91SAM9261 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
 
 # AT91SAM9263 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
+obj-$(CONFIG_MACH_USB_A9263)    += board-usb-a9263.o
 
 # AT91SAM9RL board-specific support
 obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
 
+# AT91SAM9G20 board-specific support
+obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
+
 # AT91CAP9 board-specific support
 obj-$(CONFIG_MACH_AT91CAP9ADK)  += board-cap9adk.o
 
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
index be526746e01e..747b9dedab88 100644
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -84,6 +84,105 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
 
 
 /* --------------------------------------------------------------------
+ *  USB HS Device (Gadget)
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
+
+static struct resource usba_udc_resources[] = {
+        [0] = {
+                .start  = AT91CAP9_UDPHS_FIFO,
+                .end    = AT91CAP9_UDPHS_FIFO + SZ_512K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91CAP9_BASE_UDPHS,
+                .end    = AT91CAP9_BASE_UDPHS + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = AT91CAP9_ID_UDPHS,
+                .end    = AT91CAP9_ID_UDPHS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+#define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
+        [idx] = {                                               \
+                .name           = nam,                          \
+                .index          = idx,                          \
+                .fifo_size      = maxpkt,                       \
+                .nr_banks       = maxbk,                        \
+                .can_dma        = dma,                          \
+                .can_isoc       = isoc,                         \
+        }
+
+static struct usba_ep_data usba_udc_ep[] = {
+        EP("ep0", 0,   64, 1, 0, 0),
+        EP("ep1", 1, 1024, 3, 1, 1),
+        EP("ep2", 2, 1024, 3, 1, 1),
+        EP("ep3", 3, 1024, 2, 1, 1),
+        EP("ep4", 4, 1024, 2, 1, 1),
+        EP("ep5", 5, 1024, 2, 1, 0),
+        EP("ep6", 6, 1024, 2, 1, 0),
+        EP("ep7", 7, 1024, 2, 0, 0),
+};
+
+#undef EP
+
+/*
+ * pdata doesn't have room for any endpoints, so we need to
+ * append room for the ones we need right after it.
+ */
+static struct {
+        struct usba_platform_data pdata;
+        struct usba_ep_data ep[8];
+} usba_udc_data;
+
+static struct platform_device at91_usba_udc_device = {
+        .name           = "atmel_usba_udc",
+        .id             = -1,
+        .dev            = {
+                                .platform_data  = &usba_udc_data.pdata,
+        },
+        .resource       = usba_udc_resources,
+        .num_resources  = ARRAY_SIZE(usba_udc_resources),
+};
+
+void __init at91_add_device_usba(struct usba_platform_data *data)
+{
+        at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
+                                          AT91_MATRIX_UDPHS_BYPASS_LOCK);
+
+        /*
+         * Invalid pins are 0 on AT91, but the usba driver is shared
+         * with AVR32, which use negative values instead. Once/if
+         * gpio_is_valid() is ported to AT91, revisit this code.
+         */
+        usba_udc_data.pdata.vbus_pin = -EINVAL;
+        usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
+        memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
+
+        if (data && data->vbus_pin > 0) {
+                at91_set_gpio_input(data->vbus_pin, 0);
+                at91_set_deglitch(data->vbus_pin, 1);
+                usba_udc_data.pdata.vbus_pin = data->vbus_pin;
+        }
+
+        /* Pullup pin is handled internally by USB device peripheral */
+
+        /* Clocks */
+        at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
+        at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
+
+        platform_device_register(&at91_usba_udc_device);
+}
+#else
+void __init at91_add_device_usba(struct usba_platform_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
  *  Ethernet
  * -------------------------------------------------------------------- */
 
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index ee26550cdc21..380f12a12200 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -47,6 +47,20 @@ static struct map_desc at91sam9260_sram_desc[] __initdata = {
         }
 };
 
+static struct map_desc at91sam9g20_sram_desc[] __initdata = {
+        {
+                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE,
+                .pfn            = __phys_to_pfn(AT91SAM9G20_SRAM0_BASE),
+                .length         = AT91SAM9G20_SRAM0_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE - AT91SAM9G20_SRAM1_SIZE,
+                .pfn            = __phys_to_pfn(AT91SAM9G20_SRAM1_BASE),
+                .length         = AT91SAM9G20_SRAM1_SIZE,
+                .type           = MT_DEVICE,
+        }
+};
+
 static struct map_desc at91sam9xe_sram_desc[] __initdata = {
         {
                 .pfn            = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
@@ -307,6 +321,8 @@ void __init at91sam9260_initialize(unsigned long main_clock)
 
         if (cpu_is_at91sam9xe())
                 at91sam9xe_initialize();
+        else if (cpu_is_at91sam9g20())
+                iotable_init(at91sam9g20_sram_desc, ARRAY_SIZE(at91sam9g20_sram_desc));
         else
                 iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
 
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 393a32aefce5..86cba4ac29b1 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -18,6 +18,7 @@
 
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/at91sam9260.h>
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
@@ -320,20 +321,41 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
         csa = at91_sys_read(AT91_MATRIX_EBICSA);
         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
-        /* set the bus interface characteristics */
-        at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
-                        | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+        if (cpu_is_at91sam9260()) {
+                /* Timing for sam9260 */
+                /* set the bus interface characteristics */
+                at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
+                                | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
 
-        at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
-                        | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+                at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
+                                | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
 
-        at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+                at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
 
-        if (data->bus_width_16)
-                mode = AT91_SMC_DBW_16;
-        else
-                mode = AT91_SMC_DBW_8;
-        at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
+                if (data->bus_width_16)
+                        mode = AT91_SMC_DBW_16;
+                else
+                        mode = AT91_SMC_DBW_8;
+                at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
+        }
+
+        if (cpu_is_at91sam9g20()) {
+                /* Timing for sam9g20 */
+                /* set the bus interface characteristics */
+                at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0)
+                                | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
+
+                at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(4)
+                                | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(4));
+
+                at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+
+                if (data->bus_width_16)
+                        mode = AT91_SMC_DBW_16;
+                else
+                        mode = AT91_SMC_DBW_8;
+                at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(3));
+        }
 
         /* enable pin */
         if (data->enable_pin)
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 0babb645b83c..ec1891375dfb 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -232,19 +232,19 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
         /* set the bus interface characteristics */
-        at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
-                        | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+        at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
+                        | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
 
-        at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
-                        | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
+        at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
+                        | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
 
-        at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+        at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
 
         if (data->bus_width_16)
                 mode = AT91_SMC_DBW_16;
         else
                 mode = AT91_SMC_DBW_8;
-        at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
+        at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
 
         /* enable pin */
         if (data->enable_pin)
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 719667e25c98..8a81f76f0200 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -391,8 +391,8 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
         at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
 
         /* set the bus interface characteristics */
-        at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
-                        | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+        at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
+                        | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
 
         at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
                         | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 450db304936f..ae28101e7542 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -26,6 +26,101 @@
 
 
 /* --------------------------------------------------------------------
+ *  USB HS Device (Gadget)
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
+
+static struct resource usba_udc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9RL_UDPHS_FIFO,
+                .end    = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9RL_BASE_UDPHS,
+                .end    = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = AT91SAM9RL_ID_UDPHS,
+                .end    = AT91SAM9RL_ID_UDPHS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+#define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
+        [idx] = {                                               \
+                .name           = nam,                          \
+                .index          = idx,                          \
+                .fifo_size      = maxpkt,                       \
+                .nr_banks       = maxbk,                        \
+                .can_dma        = dma,                          \
+                .can_isoc       = isoc,                         \
+        }
+
+static struct usba_ep_data usba_udc_ep[] __initdata = {
+        EP("ep0", 0, 64, 1, 0, 0),
+        EP("ep1", 1, 1024, 2, 1, 1),
+        EP("ep2", 2, 1024, 2, 1, 1),
+        EP("ep3", 3, 1024, 3, 1, 0),
+        EP("ep4", 4, 1024, 3, 1, 0),
+        EP("ep5", 5, 1024, 3, 1, 1),
+        EP("ep6", 6, 1024, 3, 1, 1),
+};
+
+#undef EP
+
+/*
+ * pdata doesn't have room for any endpoints, so we need to
+ * append room for the ones we need right after it.
+ */
+static struct {
+        struct usba_platform_data pdata;
+        struct usba_ep_data ep[7];
+} usba_udc_data;
+
+static struct platform_device at91_usba_udc_device = {
+        .name           = "atmel_usba_udc",
+        .id             = -1,
+        .dev            = {
+                                .platform_data  = &usba_udc_data.pdata,
+        },
+        .resource       = usba_udc_resources,
+        .num_resources  = ARRAY_SIZE(usba_udc_resources),
+};
+
+void __init at91_add_device_usba(struct usba_platform_data *data)
+{
+        /*
+         * Invalid pins are 0 on AT91, but the usba driver is shared
+         * with AVR32, which use negative values instead. Once/if
+         * gpio_is_valid() is ported to AT91, revisit this code.
+         */
+        usba_udc_data.pdata.vbus_pin = -EINVAL;
+        usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
+        memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
+
+        if (data && data->vbus_pin > 0) {
+                at91_set_gpio_input(data->vbus_pin, 0);
+                at91_set_deglitch(data->vbus_pin, 1);
+                usba_udc_data.pdata.vbus_pin = data->vbus_pin;
+        }
+
+        /* Pullup pin is handled internally by USB device peripheral */
+
+        /* Clocks */
+        at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
+        at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
+
+        platform_device_register(&at91_usba_udc_device);
+}
+#else
+void __init at91_add_device_usba(struct usba_platform_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
  *  MMC / SD
  * -------------------------------------------------------------------- */
 
@@ -138,15 +233,15 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
         /* set the bus interface characteristics */
-        at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
-                        | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+        at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
+                        | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
 
-        at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
-                        | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
+        at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
+                        | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
 
-        at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+        at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
 
-        at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
+        at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
 
         /* enable pin */
         if (data->enable_pin)
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
index e5512d1ff217..8a2a958639db 100644
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ b/arch/arm/mach-at91/board-cap9adk.c
@@ -78,6 +78,12 @@ static struct at91_usbh_data __initdata cap9adk_usbh_data = {
         .ports          = 2,
 };
 
+/*
+ * USB HS Device port
+ */
+static struct usba_platform_data __initdata cap9adk_usba_udc_data = {
+        .vbus_pin       = AT91_PIN_PB31,
+};
 
 /*
  * ADS7846 Touchscreen
@@ -326,6 +332,9 @@ static void __init cap9adk_board_init(void)
         /* USB Host */
         set_irq_type(AT91CAP9_ID_UHP, IRQT_HIGH);
         at91_add_device_usbh(&cap9adk_usbh_data);
+        /* USB HS */
+        set_irq_type(AT91CAP9_ID_UDPHS, IRQT_HIGH);
+        at91_add_device_usba(&cap9adk_usba_udc_data);
         /* SPI */
         at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices));
         /* Touchscreen */
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 0f0878294a67..9854fc3dd1f2 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -40,24 +40,21 @@
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata carmeva_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 4, 1, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
-};
-
 static void __init carmeva_map_io(void)
 {
         /* Initialize processor: 20.000 MHz crystal */
         at91rm9200_initialize(20000000, AT91RM9200_BGA);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&carmeva_uart_config);
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init carmeva_init_irq(void)
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index 419fd19b620b..bb1a5474ddab 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -45,10 +45,10 @@ static void __init csb637_map_io(void)
         /* Initialize processor: 3.6864 MHz crystal */
         at91rm9200_initialize(3686400, AT91RM9200_BGA);
 
-        /* DBGU on ttyS0 */
+        /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
 
-        /* make console=ttyS0 the default */
+        /* make console=ttyS0 (ie, DBGU) the default */
         at91_set_serial_console(0);
 }
 
diff --git a/arch/arm/mach-at91/board-dk.c b/arch/arm/mach-at91/board-dk.c
index c1a813c7169b..dab958d25926 100644
--- a/arch/arm/mach-at91/board-dk.c
+++ b/arch/arm/mach-at91/board-dk.c
@@ -45,17 +45,6 @@
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata dk_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 4, 1, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
-};
-
 static void __init dk_map_io(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
@@ -64,8 +53,16 @@ static void __init dk_map_io(void)
         /* Setup the LEDs */
         at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&dk_uart_config);
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init dk_init_irq(void)
@@ -163,7 +160,7 @@ static struct at91_nand_data __initdata dk_nand_data = {
 #define DK_FLASH_SIZE   0x200000
 
 static struct physmap_flash_data dk_flash_data = {
-        .width  = 2,
+        .width          = 2,
 };
 
 static struct resource dk_flash_resource = {
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index af1a1d8ecc30..3fe054e0056b 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -40,24 +40,24 @@
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata eb9200_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 4, 1, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
-};
-
 static void __init eb9200_map_io(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
         at91rm9200_initialize(18432000, AT91RM9200_BGA);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&eb9200_uart_config);
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                        | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                        | ATMEL_UART_RI);
+
+        /* USART2 on ttyS2. (Rx, Tx) - IRDA */
+        at91_register_uart(AT91RM9200_ID_US2, 2, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init eb9200_init_irq(void)
diff --git a/arch/arm/mach-at91/board-ek.c b/arch/arm/mach-at91/board-ek.c
index 0574e50a30dd..74aa4325eab3 100644
--- a/arch/arm/mach-at91/board-ek.c
+++ b/arch/arm/mach-at91/board-ek.c
@@ -45,17 +45,6 @@
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata ek_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 4, 1, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
-};
-
 static void __init ek_map_io(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
@@ -64,8 +53,16 @@ static void __init ek_map_io(void)
         /* Setup the LEDs */
         at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&ek_uart_config);
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init ek_init_irq(void)
@@ -122,7 +119,7 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = {
 #define EK_FLASH_SIZE   0x200000
 
 static struct physmap_flash_data ek_flash_data = {
-        .width  = 2,
+        .width          = 2,
 };
 
 static struct resource ek_flash_resource = {
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 4b39b9cda75b..cb065febd95e 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -37,19 +37,10 @@
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
 
-#include "generic.h"
+#include <asm/arch/at91rm9200_mc.h>
 
+#include "generic.h"
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata kb9202_uart_config = {
-        .console_tty    = 0,                                    /* ttyS0 */
-        .nr_tty         = 3,
-        .tty_map        = { 4, 0, 1, -1, -1 }                   /* ttyS0, ..., ttyS4 */
-};
 
 static void __init kb9202_map_io(void)
 {
@@ -59,8 +50,20 @@ static void __init kb9202_map_io(void)
         /* Set up the LEDs */
         at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&kb9202_uart_config);
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1 (Rx & Tx only) */
+        at91_register_uart(AT91RM9200_ID_US0, 1, 0);
+
+        /* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */
+        at91_register_uart(AT91RM9200_ID_US1, 2, 0);
+
+        /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */
+        at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init kb9202_init_irq(void)
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
new file mode 100644
index 000000000000..99b4ec3818d6
--- /dev/null
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -0,0 +1,255 @@
+/*
+ * linux/arch/arm/mach-at91/board-qil-a9260.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2006 Atmel
+ *  Copyright (C) 2007 Calao-systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/clk.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_shdwc.h>
+
+#include "generic.h"
+
+
+static void __init ek_map_io(void)
+{
+        /* Initialize processor: 12.000 MHz crystal */
+        at91sam9260_initialize(12000000);
+
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+
+        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* set serial console to ttyS1 (ie, USART0) */
+        at91_set_serial_console(1);
+
+}
+
+static void __init ek_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host port
+ */
+static struct at91_usbh_data __initdata ek_usbh_data = {
+        .ports          = 2,
+};
+
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata ek_udc_data = {
+        .vbus_pin       = AT91_PIN_PC5,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+/*
+ * SPI devices.
+ */
+static struct spi_board_info ek_spi_devices[] = {
+#if defined(CONFIG_RTC_DRV_M41T94)
+        {       /* M41T94 RTC */
+                .modalias       = "m41t94",
+                .chip_select    = 0,
+                .max_speed_hz   = 1 * 1000 * 1000,
+                .bus_num        = 0,
+        }
+#endif
+};
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata ek_macb_data = {
+        .phy_irq_pin    = AT91_PIN_PA31,
+        .is_rmii        = 1,
+};
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata ek_nand_partition[] = {
+        {
+                .name   = "Uboot & Kernel",
+                .offset = 0x00000000,
+                .size   = 16 * 1024 * 1024,
+        },
+        {
+                .name   = "Root FS",
+                .offset = 0x01000000,
+                .size   = 120 * 1024 * 1024,
+        },
+        {
+                .name   = "FS",
+                .offset = 0x08800000,
+                .size   = 120 * 1024 * 1024,
+        },
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(ek_nand_partition);
+        return ek_nand_partition;
+}
+
+static struct at91_nand_data __initdata ek_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+//      .det_pin        = ... not connected
+        .rdy_pin        = AT91_PIN_PC13,
+        .enable_pin     = AT91_PIN_PC14,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+
+/*
+ * MCI (SD/MMC)
+ */
+static struct at91_mmc_data __initdata ek_mmc_data = {
+        .slot_b         = 0,
+        .wire4          = 1,
+//      .det_pin        = ... not connected
+//      .wp_pin         = ... not connected
+//      .vcc_pin        = ... not connected
+};
+
+/*
+ * GPIO Buttons
+ */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button ek_buttons[] = {
+        {       /* USER PUSH BUTTON */
+                .code           = KEY_ENTER,
+                .gpio           = AT91_PIN_PB10,
+                .active_low     = 1,
+                .desc           = "user_pb",
+                .wakeup         = 1,
+        }
+};
+
+static struct gpio_keys_platform_data ek_button_data = {
+        .buttons        = ek_buttons,
+        .nbuttons       = ARRAY_SIZE(ek_buttons),
+};
+
+static struct platform_device ek_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ek_button_data,
+        }
+};
+
+static void __init ek_add_device_buttons(void)
+{
+        at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
+        at91_set_deglitch(AT91_PIN_PB10, 1);
+
+        platform_device_register(&ek_button_device);
+}
+#else
+static void __init ek_add_device_buttons(void) {}
+#endif
+
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* user_led (green) */
+                .name                   = "user_led",
+                .gpio                   = AT91_PIN_PB21,
+                .active_low             = 0,
+                .default_trigger        = "heartbeat",
+        }
+};
+
+static void __init ek_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&ek_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&ek_udc_data);
+        /* SPI */
+        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+        /* NAND */
+        at91_add_device_nand(&ek_nand_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+        /* Ethernet */
+        at91_add_device_eth(&ek_macb_data);
+        /* MMC */
+        at91_add_device_mmc(0, &ek_mmc_data);
+        /* Push Buttons */
+        ek_add_device_buttons();
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        /* shutdown controller, wakeup button (5 msec low) */
+        at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
+                                | AT91_SHDW_RTTWKEN);
+}
+
+MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
+        /* Maintainer: calao-systems */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
new file mode 100644
index 000000000000..45617c201240
--- /dev/null
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -0,0 +1,218 @@
+/*
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2008 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/at73c213.h>
+#include <linux/clk.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+
+#include "generic.h"
+
+
+static void __init ek_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91sam9260_initialize(18432000);
+
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+
+        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init ek_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host port
+ */
+static struct at91_usbh_data __initdata ek_usbh_data = {
+        .ports          = 2,
+};
+
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata ek_udc_data = {
+        .vbus_pin       = AT91_PIN_PC5,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+
+/*
+ * SPI devices.
+ */
+static struct spi_board_info ek_spi_devices[] = {
+#if !defined(CONFIG_MMC_AT91)
+        {       /* DataFlash chip */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 1,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
+        {       /* DataFlash card */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#endif
+#endif
+};
+
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata ek_macb_data = {
+        .phy_irq_pin    = AT91_PIN_PA7,
+        .is_rmii        = 1,
+};
+
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata ek_nand_partition[] = {
+        {
+                .name   = "Bootstrap",
+                .offset = 0,
+                .size   = 4 * 1024 * 1024,
+        },
+        {
+                .name   = "Partition 1",
+                .offset = 4 * 1024 * 1024,
+                .size   = 60 * 1024 * 1024,
+        },
+        {
+                .name   = "Partition 2",
+                .offset = 64 * 1024 * 1024,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(ek_nand_partition);
+        return ek_nand_partition;
+}
+
+/* det_pin is not connected */
+static struct at91_nand_data __initdata ek_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+        .rdy_pin        = AT91_PIN_PC13,
+        .enable_pin     = AT91_PIN_PC14,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+
+
+/*
+ * MCI (SD/MMC)
+ * det_pin, wp_pin and vcc_pin are not connected
+ */
+static struct at91_mmc_data __initdata ek_mmc_data = {
+        .slot_b         = 1,
+        .wire4          = 1,
+};
+
+
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* "bottom" led, green, userled1 to be defined */
+                .name                   = "ds5",
+                .gpio                   = AT91_PIN_PA6,
+                .active_low             = 1,
+                .default_trigger        = "none",
+        },
+        {       /* "power" led, yellow */
+                .name                   = "ds1",
+                .gpio                   = AT91_PIN_PA9,
+                .default_trigger        = "heartbeat",
+        }
+};
+
+static void __init ek_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&ek_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&ek_udc_data);
+        /* SPI */
+        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+        /* NAND */
+        at91_add_device_nand(&ek_nand_data);
+        /* Ethernet */
+        at91_add_device_eth(&ek_macb_data);
+        /* MMC */
+        at91_add_device_mmc(0, &ek_mmc_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+}
+
+MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
+        /* Maintainer: Atmel */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index ffc0597aee8d..b6a70fc735c3 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -56,6 +56,14 @@ static void __init ek_init_irq(void)
 
 
 /*
+ * USB HS Device port
+ */
+static struct usba_platform_data __initdata ek_usba_udc_data = {
+        .vbus_pin       = AT91_PIN_PA8,
+};
+
+
+/*
  * MCI (SD/MMC)
  */
 static struct at91_mmc_data __initdata ek_mmc_data = {
@@ -175,6 +183,8 @@ static void __init ek_board_init(void)
 {
         /* Serial */
         at91_add_device_serial();
+        /* USB HS */
+        at91_add_device_usba(&ek_usba_udc_data);
         /* I2C */
         at91_add_device_i2c(NULL, 0);
         /* NAND */
diff --git a/arch/arm/mach-at91/board-usb-a9260.c b/arch/arm/mach-at91/board-usb-a9260.c
new file mode 100644
index 000000000000..837aedf8ffeb
--- /dev/null
+++ b/arch/arm/mach-at91/board-usb-a9260.c
@@ -0,0 +1,215 @@
+/*
+ * linux/arch/arm/mach-at91/board-usb-a9260.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2006 Atmel
+ *  Copyright (C) 2007 Calao-systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/clk.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_shdwc.h>
+
+#include "generic.h"
+
+
+static void __init ek_map_io(void)
+{
+        /* Initialize processor: 12.000 MHz crystal */
+        at91sam9260_initialize(12000000);
+
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init ek_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host port
+ */
+static struct at91_usbh_data __initdata ek_usbh_data = {
+        .ports          = 2,
+};
+
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata ek_udc_data = {
+        .vbus_pin       = AT91_PIN_PC5,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata ek_macb_data = {
+        .phy_irq_pin    = AT91_PIN_PA31,
+        .is_rmii        = 1,
+};
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata ek_nand_partition[] = {
+        {
+                .name   = "Uboot & Kernel",
+                .offset = 0x00000000,
+                .size   = 16 * 1024 * 1024,
+        },
+        {
+                .name   = "Root FS",
+                .offset = 0x01000000,
+                .size   = 120 * 1024 * 1024,
+        },
+        {
+                .name   = "FS",
+                .offset = 0x08800000,
+                .size   = 120 * 1024 * 1024,
+        }
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(ek_nand_partition);
+        return ek_nand_partition;
+}
+
+static struct at91_nand_data __initdata ek_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+//      .det_pin        = ... not connected
+        .rdy_pin        = AT91_PIN_PC13,
+        .enable_pin     = AT91_PIN_PC14,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+
+/*
+ * GPIO Buttons
+ */
+
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button ek_buttons[] = {
+        {       /* USER PUSH BUTTON */
+                .code           = KEY_ENTER,
+                .gpio           = AT91_PIN_PB10,
+                .active_low     = 1,
+                .desc           = "user_pb",
+                .wakeup         = 1,
+        }
+};
+
+static struct gpio_keys_platform_data ek_button_data = {
+        .buttons        = ek_buttons,
+        .nbuttons       = ARRAY_SIZE(ek_buttons),
+};
+
+static struct platform_device ek_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ek_button_data,
+        }
+};
+
+static void __init ek_add_device_buttons(void)
+{
+        at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
+        at91_set_deglitch(AT91_PIN_PB10, 1);
+
+        platform_device_register(&ek_button_device);
+}
+#else
+static void __init ek_add_device_buttons(void) {}
+#endif
+
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* user_led (green) */
+                .name                   = "user_led",
+                .gpio                   = AT91_PIN_PB21,
+                .active_low             = 0,
+                .default_trigger        = "heartbeat",
+        }
+};
+
+static void __init ek_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&ek_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&ek_udc_data);
+        /* NAND */
+        at91_add_device_nand(&ek_nand_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+        /* Ethernet */
+        at91_add_device_eth(&ek_macb_data);
+        /* Push Buttons */
+        ek_add_device_buttons();
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        /* shutdown controller, wakeup button (5 msec low) */
+        at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
+                                | AT91_SHDW_RTTWKEN);
+}
+
+MACHINE_START(USB_A9260, "CALAO USB_A9260")
+        /* Maintainer: calao-systems */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-usb-a9263.c b/arch/arm/mach-at91/board-usb-a9263.c
new file mode 100644
index 000000000000..95800d32bd49
--- /dev/null
+++ b/arch/arm/mach-at91/board-usb-a9263.c
@@ -0,0 +1,230 @@
+/*
+ * linux/arch/arm/mach-at91/board-usb-a9263.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2007 Atmel Corporation.
+ *  Copyright (C) 2007 Calao-systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_shdwc.h>
+
+#include "generic.h"
+
+
+static void __init ek_map_io(void)
+{
+        /* Initialize processor: 12.00 MHz crystal */
+        at91sam9263_initialize(12000000);
+
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init ek_init_irq(void)
+{
+        at91sam9263_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host port
+ */
+static struct at91_usbh_data __initdata ek_usbh_data = {
+        .ports          = 2,
+};
+
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata ek_udc_data = {
+        .vbus_pin       = AT91_PIN_PB11,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+/*
+ * SPI devices.
+ */
+static struct spi_board_info ek_spi_devices[] = {
+#if !defined(CONFIG_MMC_AT91)
+        {       /* DataFlash chip */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        }
+#endif
+};
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata ek_macb_data = {
+        .phy_irq_pin    = AT91_PIN_PE31,
+        .is_rmii        = 1,
+};
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata ek_nand_partition[] = {
+        {
+                .name   = "Linux Kernel",
+                .offset = 0x00000000,
+                .size   = 16 * 1024 * 1024,
+        },
+        {
+                .name   = "Root FS",
+                .offset = 0x01000000,
+                .size   = 120 * 1024 * 1024,
+        },
+        {
+                .name   = "FS",
+                .offset = 0x08800000,
+                .size   = 120 * 1024 * 1024,
+        }
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(ek_nand_partition);
+        return ek_nand_partition;
+}
+
+static struct at91_nand_data __initdata ek_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+//      .det_pin        = ... not connected
+        .rdy_pin        = AT91_PIN_PA22,
+        .enable_pin     = AT91_PIN_PD15,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+
+/*
+ * GPIO Buttons
+ */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button ek_buttons[] = {
+        {       /* USER PUSH BUTTON */
+                .code           = KEY_ENTER,
+                .gpio           = AT91_PIN_PB10,
+                .active_low     = 1,
+                .desc           = "user_pb",
+                .wakeup         = 1,
+        }
+};
+
+static struct gpio_keys_platform_data ek_button_data = {
+        .buttons        = ek_buttons,
+        .nbuttons       = ARRAY_SIZE(ek_buttons),
+};
+
+static struct platform_device ek_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ek_button_data,
+        }
+};
+
+static void __init ek_add_device_buttons(void)
+{
+        at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
+        at91_set_deglitch(AT91_PIN_PB10, 1);
+
+        platform_device_register(&ek_button_device);
+}
+#else
+static void __init ek_add_device_buttons(void) {}
+#endif
+
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* user_led (green) */
+                .name                   = "user_led",
+                .gpio                   = AT91_PIN_PB21,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        }
+};
+
+
+static void __init ek_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&ek_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&ek_udc_data);
+        /* SPI */
+        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+        /* Ethernet */
+        at91_add_device_eth(&ek_macb_data);
+        /* NAND */
+        at91_add_device_nand(&ek_nand_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+        /* Push Buttons */
+        ek_add_device_buttons();
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        /* shutdown controller, wakeup button (5 msec low) */
+        at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
+                                | AT91_SHDW_RTTWKEN);
+}
+
+MACHINE_START(USB_A9263, "CALAO USB_A9263")
+        /* Maintainer: calao-systems */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index b5717108991d..7079050ab88d 100755
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -1,11 +1,10 @@
 /*
  * linux/arch/arm/mach-at91/board-yl-9200.c
  *
- * Adapted from:
- *various board files in
- * /arch/arm/mach-at91
- * modifications  to convert to  YL-9200 platform
- *  Copyright (C) 2007 S.Birtles
+ * Adapted from various board files in arch/arm/mach-at91
+ *
+ * Modifications for YL-9200 platform:
+ *  Copyright (C) 2007 S. Birtles
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -26,13 +25,14 @@
 #include <linux/init.h>
 #include <linux/mm.h>
 #include <linux/module.h>
+#include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
-/*#include <linux/can_bus/candata.h>*/
 #include <linux/spi/ads7846.h>
 #include <linux/mtd/physmap.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
 
-/*#include <sound/gpio_sounder.h>*/
 #include <asm/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -45,179 +45,108 @@
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91rm9200_mc.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
 
 #include "generic.h"
-#include <asm/arch/at91_pio.h>
 
-#define YL_9200_FLASH_BASE      AT91_CHIPSELECT_0
-#define YL_9200_FLASH_SIZE      0x800000
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- *atmel_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a ATMEL_SERIAL
- *atmel_usart.1: ttyS1 at MMIO 0xfffc0000 (irq = 6) is a ATMEL_SERIAL
- *atmel_usart.2: ttyS2 at MMIO 0xfffc4000 (irq = 7) is a ATMEL_SERIAL
- *atmel_usart.3: ttyS3 at MMIO 0xfffc8000 (irq = 8) is a ATMEL_SERIAL
- *atmel_usart.4: ttyS4 at MMIO 0xfffcc000 (irq = 9) is a ATMEL_SERIAL
- * on the YL-9200 we are sitting at the following
- *ttyS0 at MMIO 0xfefff200 (irq = 1) is a AT91_SERIAL
- *ttyS1 at MMIO 0xfefc4000 (irq = 7) is a AT91_SERIAL
- */
+static void __init yl9200_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91rm9200_initialize(18432000, AT91RM9200_PQFP);
 
-/* extern void __init yl_9200_add_device_sounder(struct gpio_sounder *sounders, int nr);*/
+        /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
+        at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
 
-static struct at91_uart_config __initdata yl_9200_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 3,
-        .tty_map        = { 4, 1, 0, -1, -1 }           /* ttyS0, ..., ttyS4 */
-};
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
 
-static void __init yl_9200_map_io(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        /*Also initialises register clocks & gpio*/
-        at91rm9200_initialize(18432000, AT91RM9200_PQFP); /*we have a 3 bank system*/
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                        | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                        | ATMEL_UART_RI);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&yl_9200_uart_config);
+        /* USART0 on ttyS2. (Rx & Tx only to JP3) */
+        at91_register_uart(AT91RM9200_ID_US0, 2, 0);
 
-        /* Setup the LEDs D2=PB17,D3=PB16 */
-        at91_init_leds(AT91_PIN_PB16,AT91_PIN_PB17); /*cpu-led,timer-led*/
+        /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
+        at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
-static void __init yl_9200_init_irq(void)
+static void __init yl9200_init_irq(void)
 {
         at91rm9200_init_interrupts(NULL);
 }
 
-static struct at91_eth_data __initdata yl_9200_eth_data = {
-        .phy_irq_pin    = AT91_PIN_PB28,
-        .is_rmii        = 1,
-};
 
-static struct at91_usbh_data __initdata yl_9200_usbh_data = {
-        .ports          = 1,  /* this should be 1 not 2 for the Yl9200*/
+/*
+ * LEDs
+ */
+static struct gpio_led yl9200_leds[] = {
+        {       /* D2 */
+                .name                   = "led2",
+                .gpio                   = AT91_PIN_PB17,
+                .active_low             = 1,
+                .default_trigger        = "timer",
+        },
+        {       /* D3 */
+                .name                   = "led3",
+                .gpio                   = AT91_PIN_PB16,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+        {       /* D4 */
+                .name                   = "led4",
+                .gpio                   = AT91_PIN_PB15,
+                .active_low             = 1,
+        },
+        {       /* D5 */
+                .name                   = "led5",
+                .gpio                   = AT91_PIN_PB8,
+                .active_low             = 1,
+        }
 };
 
-static struct at91_udc_data __initdata yl_9200_udc_data = {
-/*on sheet 7 Schemitic rev 1.0*/
-        .pullup_pin     = AT91_PIN_PC4,
-        .vbus_pin=  AT91_PIN_PC5,
-        .pullup_active_low = 1, /*ACTIVE LOW!! due to PNP transistor on page 7*/
-
-};
 /*
-static struct at91_cf_data __initdata yl_9200_cf_data = {
-TODO S.BIRTLES
-        .det_pin        = AT91_PIN_xxx,
-        .rst_pin        = AT91_PIN_xxx,
-        .irq_pin        = ... not connected
-        .vcc_pin        = ... always powered
-
+ * Ethernet
+ */
+static struct at91_eth_data __initdata yl9200_eth_data = {
+        .phy_irq_pin            = AT91_PIN_PB28,
+        .is_rmii                = 1,
 };
-*/
-static struct at91_mmc_data __initdata yl_9200_mmc_data = {
-        .det_pin        = AT91_PIN_PB9, /*THIS LOOKS CORRECT SHEET7*/
-/*      .wp_pin         = ... not connected  SHEET7*/
-        .slot_b         = 0,
-        .wire4          = 1,
 
+/*
+ * USB Host
+ */
+static struct at91_usbh_data __initdata yl9200_usbh_data = {
+        .ports                  = 1,    /* PQFP version of AT91RM9200 */
 };
 
-/* --------------------------------------------------------------------
- *  Touch screen
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-static int ads7843_pendown_state(void)
-{
-        return !at91_get_gpio_value(AT91_PIN_PB11);     /* Touchscreen PENIRQ */
-}
-
-static void __init at91_init_device_ts(void)
-{
-/*IMPORTANT NOTE THE SPI INTERFACE IS ALREADY CONFIGURED BY XXX_DEVICES.C
-THAT IS TO SAY THAT  MISO,MOSI,SPCK AND CS  are already configured
-we only need to enable the other datapins which are:
-PB10/RK1 BUSY
-*/
-/* Touchscreen BUSY signal ,  pin,use pullup ( TODO not currently used in the ADS7843/6.c driver)*/
-at91_set_gpio_input(AT91_PIN_PB10, 1);
-}
-
-#else
-static void __init at91_init_device_ts(void) {}
-#endif
-
-static struct ads7846_platform_data ads_info = {
-        .model                  = 7843,
-        .x_min                  = 150,
-        .x_max                  = 3830,
-        .y_min                  = 190,
-        .y_max                  = 3830,
-        .vref_delay_usecs       = 100,
-/* for a 8" touch screen*/
-        //.x_plate_ohms         = 603, //= 450, S.Birtles TODO
-        //.y_plate_ohms         = 332, //= 250, S.Birtles TODO
-/*for a 10.4" touch screen*/
-        //.x_plate_ohms         =611,
-        //.y_plate_ohms         =325,
-
-        .x_plate_ohms   = 576,
-        .y_plate_ohms   = 366,
-                //
-        .pressure_max           = 15000, /*generally nonsense on the 7843*/
-         /*number of times to send query to chip in a given run 0 equals one time (do not set to 0!! ,there is a bug in ADS 7846 code)*/
-        .debounce_max           = 1,
-        .debounce_rep           = 0,
-        .debounce_tol           = (~0),
-        .get_pendown_state      = ads7843_pendown_state,
-};
+/*
+ * USB Device
+ */
+static struct at91_udc_data __initdata yl9200_udc_data = {
+        .pullup_pin             = AT91_PIN_PC4,
+        .vbus_pin               = AT91_PIN_PC5,
+        .pullup_active_low      = 1,    /* Active Low due to PNP transistor (pg 7) */
 
-/*static struct canbus_platform_data can_info = {
-        .model                  = 2510,
 };
-*/
-
-static struct spi_board_info yl_9200_spi_devices[] = {
-/*this sticks it at:
- /sys/devices/platform/atmel_spi.0/spi0.0
- /sys/bus/platform/devices/
-Documentation/spi IIRC*/
 
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
- /*(this IS correct 04-NOV-2007)*/
-        {
-                .modalias               = "ads7846", /* because the driver is called ads7846*/
-                .chip_select    = 0, /*THIS MUST BE AN INDEX INTO AN ARRAY OF  pins */
-/*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select*/
-                /*.controller_data =AT91_PIN_PA3 ,*/
-                .max_speed_hz   = 5000*26, /*(4700 * 26)-125000 * 26, (max sample rate @ 3V) * (cmd + data + overhead) */
-                .bus_num                = 0,
-                .platform_data  = &ads_info,
-                .irq                    = AT91_PIN_PB11,
-        },
-#endif
-/*we need to put our CAN driver data here!!*/
-/*THIS IS ALL DUMMY DATA*/
-/*      {
-                .modalias               = "mcp2510", //DUMMY for MCP2510 chip
-                .chip_select    = 1,*/ /*THIS MUST BE AN INDEX INTO AN ARRAY OF  pins */
-        /*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select */
-        /*  .controller_data =AT91_PIN_PA4 ,
-                .max_speed_hz   = 25000 * 26,
-                .bus_num                = 0,
-                .platform_data  = &can_info,
-                .irq                    = AT91_PIN_PC0,
-        },
-        */
-        //max SPI chip needs to go here
+/*
+ * MMC
+ */
+static struct at91_mmc_data __initdata yl9200_mmc_data = {
+        .det_pin        = AT91_PIN_PB9,
+        // .wp_pin      = ... not connected
+        .wire4          = 1,
 };
 
-static struct mtd_partition __initdata yl_9200_nand_partition[] = {
+/*
+ * NAND Flash
+ */
+static struct mtd_partition __initdata yl9200_nand_partition[] = {
         {
                 .name   = "AT91 NAND partition 1, boot",
                 .offset = 0,
@@ -242,442 +171,434 @@ static struct mtd_partition __initdata yl_9200_nand_partition[] = {
                 .name   = "AT91 NAND partition 5, ext-fs",
                 .offset = 32 * SZ_1M,
                 .size   = 32 * SZ_1M
-        },
+        }
 };
 
 static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
 {
-        *num_partitions = ARRAY_SIZE(yl_9200_nand_partition);
-        return yl_9200_nand_partition;
+        *num_partitions = ARRAY_SIZE(yl9200_nand_partition);
+        return yl9200_nand_partition;
 }
 
-static struct at91_nand_data __initdata yl_9200_nand_data = {
-        .ale= 6,
-        .cle= 7,
-        /*.det_pin      = AT91_PIN_PCxx,*/   /*we don't have a det pin because NandFlash is fixed to board*/
-        .rdy_pin        = AT91_PIN_PC14,  /*R/!B Sheet10*/
-        .enable_pin     = AT91_PIN_PC15,  /*!CE  Sheet10 */
+static struct at91_nand_data __initdata yl9200_nand_data = {
+        .ale            = 6,
+        .cle            = 7,
+        // .det_pin     = ... not connected
+        .rdy_pin        = AT91_PIN_PC14,        /* R/!B (Sheet10) */
+        .enable_pin     = AT91_PIN_PC15,        /* !CE  (Sheet10) */
         .partition_info = nand_partitions,
 };
 
-
-
 /*
-TODO S.Birtles
-potentially a problem with the size above
-physmap platform flash device: 00800000 at 10000000
-physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank
-NOR chip too large to fit in mapping. Attempting to cope...
- Intel/Sharp Extended Query Table at 0x0031
-Using buffer write method
-cfi_cmdset_0001: Erase suspend on write enabled
-Reducing visibility of 16384KiB chip to 8192KiB
-*/
+ * NOR Flash
+ */
+#define YL9200_FLASH_BASE       AT91_CHIPSELECT_0
+#define YL9200_FLASH_SIZE       0x1000000
 
-static struct mtd_partition yl_9200_flash_partitions[] = {
+static struct mtd_partition yl9200_flash_partitions[] = {
+        {
+                .name           = "Bootloader",
+                .size           = 0x00040000,
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+        },
         {
-                .name =         "Bootloader",
-                .size =         0x00040000,
-                .offset =       0,
-                .mask_flags =   MTD_WRITEABLE  /* force read-only */
-        },{
-                .name =         "Kernel",
-                .size =         0x001C0000,
-                .offset =       0x00040000,
-        },{
-                .name =         "Filesystem",
-                .size =         MTDPART_SIZ_FULL,
-                .offset =       0x00200000
+                .name           = "Kernel",
+                .size           = 0x001C0000,
+                .offset         = 0x00040000,
+        },
+        {
+                .name           = "Filesystem",
+                .size           = MTDPART_SIZ_FULL,
+                .offset         = 0x00200000
         }
-
 };
 
-static struct physmap_flash_data yl_9200_flash_data = {
-        .width  = 2,
-        .parts          = yl_9200_flash_partitions,
-        .nr_parts       = ARRAY_SIZE(yl_9200_flash_partitions),
+static struct physmap_flash_data yl9200_flash_data = {
+        .width          = 2,
+        .parts          = yl9200_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(yl9200_flash_partitions),
 };
 
-static struct resource yl_9200_flash_resources[] = {
-{
-        .start          = YL_9200_FLASH_BASE,
-        .end            = YL_9200_FLASH_BASE + YL_9200_FLASH_SIZE - 1,
-        .flags          = IORESOURCE_MEM,
+static struct resource yl9200_flash_resources[] = {
+        {
+                .start  = YL9200_FLASH_BASE,
+                .end    = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
         }
 };
 
-static struct platform_device yl_9200_flash = {
+static struct platform_device yl9200_flash = {
         .name           = "physmap-flash",
         .id             = 0,
         .dev            = {
-                                .platform_data  = &yl_9200_flash_data,
+                                .platform_data  = &yl9200_flash_data,
                         },
-        .resource       = yl_9200_flash_resources,
-        .num_resources  = ARRAY_SIZE(yl_9200_flash_resources),
+        .resource       = yl9200_flash_resources,
+        .num_resources  = ARRAY_SIZE(yl9200_flash_resources),
 };
 
-
-static struct gpio_led yl_9200_leds[] = {
-/*D2 &D3 are passed directly in via at91_init_leds*/
-        {
-                .name                   = "led4",  /*D4*/
-                .gpio                   = AT91_PIN_PB15,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-                /*.default_trigger      = "timer",*/
-        },
-        {
-                .name                   = "led5",  /*D5*/
-                .gpio                   = AT91_PIN_PB8,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        }
-};
-
-//static struct gpio_sounder yl_9200_sounder[] = {*/
-/*This is a simple speaker attached to a gpo line*/
-
-//      {
-//              .name                   = "Speaker",  /*LS1*/
-//              .gpio                   = AT91_PIN_PA22,
-//              .active_low             = 0,
-//              .default_trigger        = "heartbeat",
-                /*.default_trigger      = "timer",*/
-//      },
-//};
-
-
-
-static struct i2c_board_info __initdata yl_9200_i2c_devices[] = {
-        {
-        /*TODO*/
-                I2C_BOARD_INFO("CS4334", 0x00),
+/*
+ * I2C (TWI)
+ */
+static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
+        {       /* EEPROM */
+                I2C_BOARD_INFO("24c128", 0x50),
         }
 };
 
-
- /*
+/*
  * GPIO Buttons
- */
+*/
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button yl_9200_buttons[] = {
+static struct gpio_keys_button yl9200_buttons[] = {
         {
                 .gpio           = AT91_PIN_PA24,
-                .code   = BTN_2,
+                .code           = BTN_2,
                 .desc           = "SW2",
                 .active_low     = 1,
                 .wakeup         = 1,
         },
         {
                 .gpio           = AT91_PIN_PB1,
-                .code   = BTN_3,
+                .code           = BTN_3,
                 .desc           = "SW3",
                 .active_low     = 1,
                 .wakeup         = 1,
         },
         {
                 .gpio           = AT91_PIN_PB2,
-                .code   = BTN_4,
+                .code           = BTN_4,
                 .desc           = "SW4",
                 .active_low     = 1,
                 .wakeup         = 1,
         },
         {
                 .gpio           = AT91_PIN_PB6,
-                .code   = BTN_5,
+                .code           = BTN_5,
                 .desc           = "SW5",
                 .active_low     = 1,
                 .wakeup         = 1,
-        },
-
+        }
 };
 
-static struct gpio_keys_platform_data yl_9200_button_data = {
-        .buttons        = yl_9200_buttons,
-        .nbuttons       = ARRAY_SIZE(yl_9200_buttons),
+static struct gpio_keys_platform_data yl9200_button_data = {
+        .buttons        = yl9200_buttons,
+        .nbuttons       = ARRAY_SIZE(yl9200_buttons),
 };
 
-static struct platform_device yl_9200_button_device = {
+static struct platform_device yl9200_button_device = {
         .name           = "gpio-keys",
         .id             = -1,
         .num_resources  = 0,
         .dev            = {
-        .platform_data  = &yl_9200_button_data,
+                .platform_data  = &yl9200_button_data,
         }
 };
 
-static void __init yl_9200_add_device_buttons(void)
+static void __init yl9200_add_device_buttons(void)
 {
-        //SW2
-        at91_set_gpio_input(AT91_PIN_PA24, 0);
+        at91_set_gpio_input(AT91_PIN_PA24, 1);  /* SW2 */
         at91_set_deglitch(AT91_PIN_PA24, 1);
-
-        //SW3
-        at91_set_gpio_input(AT91_PIN_PB1, 0);
+        at91_set_gpio_input(AT91_PIN_PB1, 1);   /* SW3 */
         at91_set_deglitch(AT91_PIN_PB1, 1);
-        //SW4
-        at91_set_gpio_input(AT91_PIN_PB2, 0);
+        at91_set_gpio_input(AT91_PIN_PB2, 1);   /* SW4 */
         at91_set_deglitch(AT91_PIN_PB2, 1);
-
-        //SW5
-        at91_set_gpio_input(AT91_PIN_PB6, 0);
+        at91_set_gpio_input(AT91_PIN_PB6, 1);   /* SW5 */
         at91_set_deglitch(AT91_PIN_PB6, 1);
 
+        /* Enable buttons (Sheet 5) */
+        at91_set_gpio_output(AT91_PIN_PB7, 1);
+
+        platform_device_register(&yl9200_button_device);
+}
+#else
+static void __init yl9200_add_device_buttons(void) {}
+#endif
+
+/*
+ * Touchscreen
+ */
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+static int ads7843_pendown_state(void)
+{
+        return !at91_get_gpio_value(AT91_PIN_PB11);     /* Touchscreen PENIRQ */
+}
+
+static struct ads7846_platform_data ads_info = {
+        .model                  = 7843,
+        .x_min                  = 150,
+        .x_max                  = 3830,
+        .y_min                  = 190,
+        .y_max                  = 3830,
+        .vref_delay_usecs       = 100,
+
+        /* For a 8" touch-screen */
+        // .x_plate_ohms                = 603,
+        // .y_plate_ohms                = 332,
+
+        /* For a 10.4" touch-screen */
+        // .x_plate_ohms                = 611,
+        // .y_plate_ohms                = 325,
+
+        .x_plate_ohms           = 576,
+        .y_plate_ohms           = 366,
+
+        .pressure_max           = 15000, /* generally nonsense on the 7843 */
+        .debounce_max           = 1,
+        .debounce_rep           = 0,
+        .debounce_tol           = (~0),
+        .get_pendown_state      = ads7843_pendown_state,
+};
 
-        at91_set_gpio_output(AT91_PIN_PB7, 1);  /* #TURN BUTTONS ON, SHEET 5  of schematics */
-        platform_device_register(&yl_9200_button_device);
+static void __init yl9200_add_device_ts(void)
+{
+        at91_set_gpio_input(AT91_PIN_PB11, 1);  /* Touchscreen interrupt pin */
+        at91_set_gpio_input(AT91_PIN_PB10, 1);  /* Touchscreen BUSY signal - not used! */
 }
 #else
-static void __init yl_9200_add_device_buttons(void) {}
+static void __init yl9200_add_device_ts(void) {}
+#endif
+
+/*
+ * SPI devices
+ */
+static struct spi_board_info yl9200_spi_devices[] = {
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+        {       /* Touchscreen */
+                .modalias       = "ads7846",
+                .chip_select    = 0,
+                .max_speed_hz   = 5000 * 26,
+                .platform_data  = &ads_info,
+                .irq            = AT91_PIN_PB11,
+        },
 #endif
+        {       /* CAN */
+                .modalias       = "mcp2510",
+                .chip_select    = 1,
+                .max_speed_hz   = 25000 * 26,
+                .irq            = AT91_PIN_PC0,
+        }
+};
 
+/*
+ * LCD / VGA
+ *
+ * EPSON S1D13806 FB (discontinued chip)
+ * EPSON S1D13506 FB
+ */
 #if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE)
 #include <video/s1d13xxxfb.h>
 
-/* EPSON S1D13806 FB (discontinued chip)*/
-/* EPSON S1D13506 FB */
-
 #define AT91_FB_REG_BASE        0x80000000L
 #define AT91_FB_REG_SIZE        0x200
 #define AT91_FB_VMEM_BASE       0x80200000L
 #define AT91_FB_VMEM_SIZE       0x200000L
 
-/*#define S1D_DISPLAY_WIDTH           640*/
-/*#define S1D_DISPLAY_HEIGHT          480*/
-
-
-static void __init yl_9200_init_video(void)
+static void __init yl9200_init_video(void)
 {
-        at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
-        at91_sys_write(AT91_PIOC + PIO_BSR,0);
-        at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
-
-        at91_sys_write( AT91_SMC_CSR(2),
-        AT91_SMC_NWS_(0x4) |
-        AT91_SMC_WSEN |
-        AT91_SMC_TDF_(0x100) |
-        AT91_SMC_DBW
-        );
-
-
+        /* NWAIT Signal */
+        at91_set_A_periph(AT91_PIN_PC6, 0);
 
+        /* Initialization of the Static Memory Controller for Chip Select 2 */
+        at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16         /* 16 bit */
+                        | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4)    /* wait states */
+                        | AT91_SMC_TDF_(0x100)                  /* float time */
+        );
 }
 
-
-static struct s1d13xxxfb_regval yl_9200_s1dfb_initregs[] =
+static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
 {
-        {S1DREG_MISC,                           0x00},   /* Miscellaneous Register*/
-        {S1DREG_COM_DISP_MODE,          0x01},   /* Display Mode Register, LCD only*/
-        {S1DREG_GPIO_CNF0,                      0x00},   /* General IO Pins Configuration Register*/
-        {S1DREG_GPIO_CTL0,                      0x00},   /* General IO Pins Control Register*/
-        {S1DREG_CLK_CNF,                        0x11},   /* Memory Clock Configuration Register*/
-        {S1DREG_LCD_CLK_CNF,            0x10},   /* LCD Pixel Clock Configuration Register*/
-        {S1DREG_CRT_CLK_CNF,            0x12},   /* CRT/TV Pixel Clock Configuration Register*/
-        {S1DREG_MPLUG_CLK_CNF,          0x01},   /* MediaPlug Clock Configuration Register*/
-        {S1DREG_CPU2MEM_WST_SEL,        0x02},   /* CPU To Memory Wait State Select Register*/
-        {S1DREG_MEM_CNF,                        0x00},   /* Memory Configuration Register*/
-        {S1DREG_SDRAM_REF_RATE,         0x04},   /* DRAM Refresh Rate Register, MCLK source*/
-        {S1DREG_SDRAM_TC0,                      0x12},   /* DRAM Timings Control Register 0*/
-        {S1DREG_SDRAM_TC1,                      0x02},   /* DRAM Timings Control Register 1*/
-        {S1DREG_PANEL_TYPE,                     0x25},   /* Panel Type Register*/
-        {S1DREG_MOD_RATE,                       0x00},   /* MOD Rate Register*/
-        {S1DREG_LCD_DISP_HWIDTH,        0x4F},   /* LCD Horizontal Display Width Register*/
-        {S1DREG_LCD_NDISP_HPER,         0x13},   /* LCD Horizontal Non-Display Period Register*/
-        {S1DREG_TFT_FPLINE_START,       0x01},   /* TFT FPLINE Start Position Register*/
-        {S1DREG_TFT_FPLINE_PWIDTH,      0x0c},   /* TFT FPLINE Pulse Width Register*/
-        {S1DREG_LCD_DISP_VHEIGHT0,      0xDF},   /* LCD Vertical Display Height Register 0*/
-        {S1DREG_LCD_DISP_VHEIGHT1,      0x01},   /* LCD Vertical Display Height Register 1*/
-        {S1DREG_LCD_NDISP_VPER,         0x2c},   /* LCD Vertical Non-Display Period Register*/
-        {S1DREG_TFT_FPFRAME_START,      0x0a},   /* TFT FPFRAME Start Position Register*/
-        {S1DREG_TFT_FPFRAME_PWIDTH,     0x02},   /* TFT FPFRAME Pulse Width Register*/
-        {S1DREG_LCD_DISP_MODE,          0x05},   /* LCD Display Mode Register*/
-        {S1DREG_LCD_MISC,                       0x01},   /* LCD Miscellaneous Register*/
-        {S1DREG_LCD_DISP_START0,        0x00},   /* LCD Display Start Address Register 0*/
-        {S1DREG_LCD_DISP_START1,        0x00},   /* LCD Display Start Address Register 1*/
-        {S1DREG_LCD_DISP_START2,        0x00},   /* LCD Display Start Address Register 2*/
-        {S1DREG_LCD_MEM_OFF0,           0x80},   /* LCD Memory Address Offset Register 0*/
-        {S1DREG_LCD_MEM_OFF1,           0x02},   /* LCD Memory Address Offset Register 1*/
-        {S1DREG_LCD_PIX_PAN,            0x03},   /* LCD Pixel Panning Register*/
-        {S1DREG_LCD_DISP_FIFO_HTC,      0x00},   /* LCD Display FIFO High Threshold Control Register*/
-        {S1DREG_LCD_DISP_FIFO_LTC,      0x00},   /* LCD Display FIFO Low Threshold Control Register*/
-        {S1DREG_CRT_DISP_HWIDTH,        0x4F},   /* CRT/TV Horizontal Display Width Register*/
-        {S1DREG_CRT_NDISP_HPER,         0x13},   /* CRT/TV Horizontal Non-Display Period Register*/
-        {S1DREG_CRT_HRTC_START,         0x01},   /* CRT/TV HRTC Start Position Register*/
-        {S1DREG_CRT_HRTC_PWIDTH,        0x0B},   /* CRT/TV HRTC Pulse Width Register*/
-        {S1DREG_CRT_DISP_VHEIGHT0,      0xDF},   /* CRT/TV Vertical Display Height Register 0*/
-        {S1DREG_CRT_DISP_VHEIGHT1,      0x01},   /* CRT/TV Vertical Display Height Register 1*/
-        {S1DREG_CRT_NDISP_VPER,         0x2B},   /* CRT/TV Vertical Non-Display Period Register*/
-        {S1DREG_CRT_VRTC_START,         0x09},   /* CRT/TV VRTC Start Position Register*/
-        {S1DREG_CRT_VRTC_PWIDTH,        0x01},   /* CRT/TV VRTC Pulse Width Register*/
-        {S1DREG_TV_OUT_CTL,                     0x18},   /* TV Output Control Register */
-        {S1DREG_CRT_DISP_MODE,          0x05},   /* CRT/TV Display Mode Register, 16BPP*/
-        {S1DREG_CRT_DISP_START0,        0x00},   /* CRT/TV Display Start Address Register 0*/
-        {S1DREG_CRT_DISP_START1,        0x00},   /* CRT/TV Display Start Address Register 1*/
-        {S1DREG_CRT_DISP_START2,        0x00},   /* CRT/TV Display Start Address Register 2*/
-        {S1DREG_CRT_MEM_OFF0,           0x80},   /* CRT/TV Memory Address Offset Register 0*/
-        {S1DREG_CRT_MEM_OFF1,           0x02},   /* CRT/TV Memory Address Offset Register 1*/
-        {S1DREG_CRT_PIX_PAN,            0x00},   /* CRT/TV Pixel Panning Register*/
-        {S1DREG_CRT_DISP_FIFO_HTC,      0x00},   /* CRT/TV Display FIFO High Threshold Control Register*/
-        {S1DREG_CRT_DISP_FIFO_LTC,      0x00},   /* CRT/TV Display FIFO Low Threshold Control Register*/
-        {S1DREG_LCD_CUR_CTL,            0x00},   /* LCD Ink/Cursor Control Register*/
-        {S1DREG_LCD_CUR_START,          0x01},   /* LCD Ink/Cursor Start Address Register*/
-        {S1DREG_LCD_CUR_XPOS0,          0x00},   /* LCD Cursor X Position Register 0*/
-        {S1DREG_LCD_CUR_XPOS1,          0x00},   /* LCD Cursor X Position Register 1*/
-        {S1DREG_LCD_CUR_YPOS0,          0x00},   /* LCD Cursor Y Position Register 0*/
-        {S1DREG_LCD_CUR_YPOS1,          0x00},   /* LCD Cursor Y Position Register 1*/
-        {S1DREG_LCD_CUR_BCTL0,          0x00},   /* LCD Ink/Cursor Blue Color 0 Register*/
-        {S1DREG_LCD_CUR_GCTL0,          0x00},   /* LCD Ink/Cursor Green Color 0 Register*/
-        {S1DREG_LCD_CUR_RCTL0,          0x00},   /* LCD Ink/Cursor Red Color 0 Register*/
-        {S1DREG_LCD_CUR_BCTL1,          0x1F},   /* LCD Ink/Cursor Blue Color 1 Register*/
-        {S1DREG_LCD_CUR_GCTL1,          0x3F},   /* LCD Ink/Cursor Green Color 1 Register*/
-        {S1DREG_LCD_CUR_RCTL1,          0x1F},   /* LCD Ink/Cursor Red Color 1 Register*/
-        {S1DREG_LCD_CUR_FIFO_HTC,       0x00},   /* LCD Ink/Cursor FIFO Threshold Register*/
-        {S1DREG_CRT_CUR_CTL,            0x00},   /* CRT/TV Ink/Cursor Control Register*/
-        {S1DREG_CRT_CUR_START,          0x01},   /* CRT/TV Ink/Cursor Start Address Register*/
-        {S1DREG_CRT_CUR_XPOS0,          0x00},   /* CRT/TV Cursor X Position Register 0*/
-        {S1DREG_CRT_CUR_XPOS1,          0x00},   /* CRT/TV Cursor X Position Register 1*/
-        {S1DREG_CRT_CUR_YPOS0,          0x00},   /* CRT/TV Cursor Y Position Register 0*/
-        {S1DREG_CRT_CUR_YPOS1,          0x00},   /* CRT/TV Cursor Y Position Register 1*/
-        {S1DREG_CRT_CUR_BCTL0,          0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register*/
-        {S1DREG_CRT_CUR_GCTL0,          0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register*/
-        {S1DREG_CRT_CUR_RCTL0,          0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register*/
-        {S1DREG_CRT_CUR_BCTL1,          0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register*/
-        {S1DREG_CRT_CUR_GCTL1,          0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register*/
-        {S1DREG_CRT_CUR_RCTL1,          0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register*/
-        {S1DREG_CRT_CUR_FIFO_HTC,       0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register*/
-        {S1DREG_BBLT_CTL0,                      0x00},   /* BitBlt Control Register 0*/
-        {S1DREG_BBLT_CTL1,                      0x01},   /* BitBlt Control Register 1*/
-        {S1DREG_BBLT_CC_EXP,            0x00},   /* BitBlt ROP Code/Color Expansion Register*/
-        {S1DREG_BBLT_OP,                        0x00},   /* BitBlt Operation Register*/
-        {S1DREG_BBLT_SRC_START0,        0x00},   /* BitBlt Source Start Address Register 0*/
-        {S1DREG_BBLT_SRC_START1,        0x00},   /* BitBlt Source Start Address Register 1*/
-        {S1DREG_BBLT_SRC_START2,        0x00},   /* BitBlt Source Start Address Register 2*/
-        {S1DREG_BBLT_DST_START0,        0x00},   /* BitBlt Destination Start Address Register 0*/
-        {S1DREG_BBLT_DST_START1,        0x00},   /* BitBlt Destination Start Address Register 1*/
-        {S1DREG_BBLT_DST_START2,        0x00},   /* BitBlt Destination Start Address Register 2*/
-        {S1DREG_BBLT_MEM_OFF0,          0x00},   /* BitBlt Memory Address Offset Register 0*/
-        {S1DREG_BBLT_MEM_OFF1,          0x00},   /* BitBlt Memory Address Offset Register 1*/
-        {S1DREG_BBLT_WIDTH0,            0x00},   /* BitBlt Width Register 0*/
-        {S1DREG_BBLT_WIDTH1,            0x00},   /* BitBlt Width Register 1*/
-        {S1DREG_BBLT_HEIGHT0,           0x00},   /* BitBlt Height Register 0*/
-        {S1DREG_BBLT_HEIGHT1,           0x00},   /* BitBlt Height Register 1*/
-        {S1DREG_BBLT_BGC0,                      0x00},   /* BitBlt Background Color Register 0*/
-        {S1DREG_BBLT_BGC1,                      0x00},   /* BitBlt Background Color Register 1*/
-        {S1DREG_BBLT_FGC0,                      0x00},   /* BitBlt Foreground Color Register 0*/
-        {S1DREG_BBLT_FGC1,                      0x00},   /* BitBlt Foreground Color Register 1*/
-        {S1DREG_LKUP_MODE,                      0x00},   /* Look-Up Table Mode Register*/
-        {S1DREG_LKUP_ADDR,                      0x00},   /* Look-Up Table Address Register*/
-        {S1DREG_PS_CNF,                         0x00},   /* Power Save Configuration Register*/
-        {S1DREG_PS_STATUS,                      0x00},   /* Power Save Status Register*/
-        {S1DREG_CPU2MEM_WDOGT,          0x00},   /* CPU-to-Memory Access Watchdog Timer Register*/
-        {S1DREG_COM_DISP_MODE,          0x01},   /* Display Mode Register, LCD only*/
+        {S1DREG_MISC,                   0x00},  /* Miscellaneous Register*/
+        {S1DREG_COM_DISP_MODE,          0x01},  /* Display Mode Register, LCD only*/
+        {S1DREG_GPIO_CNF0,              0x00},  /* General IO Pins Configuration Register*/
+        {S1DREG_GPIO_CTL0,              0x00},  /* General IO Pins Control Register*/
+        {S1DREG_CLK_CNF,                0x11},  /* Memory Clock Configuration Register*/
+        {S1DREG_LCD_CLK_CNF,            0x10},  /* LCD Pixel Clock Configuration Register*/
+        {S1DREG_CRT_CLK_CNF,            0x12},  /* CRT/TV Pixel Clock Configuration Register*/
+        {S1DREG_MPLUG_CLK_CNF,          0x01},  /* MediaPlug Clock Configuration Register*/
+        {S1DREG_CPU2MEM_WST_SEL,        0x02},  /* CPU To Memory Wait State Select Register*/
+        {S1DREG_MEM_CNF,                0x00},  /* Memory Configuration Register*/
+        {S1DREG_SDRAM_REF_RATE,         0x04},  /* DRAM Refresh Rate Register, MCLK source*/
+        {S1DREG_SDRAM_TC0,              0x12},  /* DRAM Timings Control Register 0*/
+        {S1DREG_SDRAM_TC1,              0x02},  /* DRAM Timings Control Register 1*/
+        {S1DREG_PANEL_TYPE,             0x25},  /* Panel Type Register*/
+        {S1DREG_MOD_RATE,               0x00},  /* MOD Rate Register*/
+        {S1DREG_LCD_DISP_HWIDTH,        0x4F},  /* LCD Horizontal Display Width Register*/
+        {S1DREG_LCD_NDISP_HPER,         0x13},  /* LCD Horizontal Non-Display Period Register*/
+        {S1DREG_TFT_FPLINE_START,       0x01},  /* TFT FPLINE Start Position Register*/
+        {S1DREG_TFT_FPLINE_PWIDTH,      0x0c},  /* TFT FPLINE Pulse Width Register*/
+        {S1DREG_LCD_DISP_VHEIGHT0,      0xDF},  /* LCD Vertical Display Height Register 0*/
+        {S1DREG_LCD_DISP_VHEIGHT1,      0x01},  /* LCD Vertical Display Height Register 1*/
+        {S1DREG_LCD_NDISP_VPER,         0x2c},  /* LCD Vertical Non-Display Period Register*/
+        {S1DREG_TFT_FPFRAME_START,      0x0a},  /* TFT FPFRAME Start Position Register*/
+        {S1DREG_TFT_FPFRAME_PWIDTH,     0x02},  /* TFT FPFRAME Pulse Width Register*/
+        {S1DREG_LCD_DISP_MODE,          0x05},  /* LCD Display Mode Register*/
+        {S1DREG_LCD_MISC,               0x01},  /* LCD Miscellaneous Register*/
+        {S1DREG_LCD_DISP_START0,        0x00},  /* LCD Display Start Address Register 0*/
+        {S1DREG_LCD_DISP_START1,        0x00},  /* LCD Display Start Address Register 1*/
+        {S1DREG_LCD_DISP_START2,        0x00},  /* LCD Display Start Address Register 2*/
+        {S1DREG_LCD_MEM_OFF0,           0x80},  /* LCD Memory Address Offset Register 0*/
+        {S1DREG_LCD_MEM_OFF1,           0x02},  /* LCD Memory Address Offset Register 1*/
+        {S1DREG_LCD_PIX_PAN,            0x03},  /* LCD Pixel Panning Register*/
+        {S1DREG_LCD_DISP_FIFO_HTC,      0x00},  /* LCD Display FIFO High Threshold Control Register*/
+        {S1DREG_LCD_DISP_FIFO_LTC,      0x00},  /* LCD Display FIFO Low Threshold Control Register*/
+        {S1DREG_CRT_DISP_HWIDTH,        0x4F},  /* CRT/TV Horizontal Display Width Register*/
+        {S1DREG_CRT_NDISP_HPER,         0x13},  /* CRT/TV Horizontal Non-Display Period Register*/
+        {S1DREG_CRT_HRTC_START,         0x01},  /* CRT/TV HRTC Start Position Register*/
+        {S1DREG_CRT_HRTC_PWIDTH,        0x0B},  /* CRT/TV HRTC Pulse Width Register*/
+        {S1DREG_CRT_DISP_VHEIGHT0,      0xDF},  /* CRT/TV Vertical Display Height Register 0*/
+        {S1DREG_CRT_DISP_VHEIGHT1,      0x01},  /* CRT/TV Vertical Display Height Register 1*/
+        {S1DREG_CRT_NDISP_VPER,         0x2B},  /* CRT/TV Vertical Non-Display Period Register*/
+        {S1DREG_CRT_VRTC_START,         0x09},  /* CRT/TV VRTC Start Position Register*/
+        {S1DREG_CRT_VRTC_PWIDTH,        0x01},  /* CRT/TV VRTC Pulse Width Register*/
+        {S1DREG_TV_OUT_CTL,             0x18},  /* TV Output Control Register */
+        {S1DREG_CRT_DISP_MODE,          0x05},  /* CRT/TV Display Mode Register, 16BPP*/
+        {S1DREG_CRT_DISP_START0,        0x00},  /* CRT/TV Display Start Address Register 0*/
+        {S1DREG_CRT_DISP_START1,        0x00},  /* CRT/TV Display Start Address Register 1*/
+        {S1DREG_CRT_DISP_START2,        0x00},  /* CRT/TV Display Start Address Register 2*/
+        {S1DREG_CRT_MEM_OFF0,           0x80},  /* CRT/TV Memory Address Offset Register 0*/
+        {S1DREG_CRT_MEM_OFF1,           0x02},  /* CRT/TV Memory Address Offset Register 1*/
+        {S1DREG_CRT_PIX_PAN,            0x00},  /* CRT/TV Pixel Panning Register*/
+        {S1DREG_CRT_DISP_FIFO_HTC,      0x00},  /* CRT/TV Display FIFO High Threshold Control Register*/
+        {S1DREG_CRT_DISP_FIFO_LTC,      0x00},  /* CRT/TV Display FIFO Low Threshold Control Register*/
+        {S1DREG_LCD_CUR_CTL,            0x00},  /* LCD Ink/Cursor Control Register*/
+        {S1DREG_LCD_CUR_START,          0x01},  /* LCD Ink/Cursor Start Address Register*/
+        {S1DREG_LCD_CUR_XPOS0,          0x00},  /* LCD Cursor X Position Register 0*/
+        {S1DREG_LCD_CUR_XPOS1,          0x00},  /* LCD Cursor X Position Register 1*/
+        {S1DREG_LCD_CUR_YPOS0,          0x00},  /* LCD Cursor Y Position Register 0*/
+        {S1DREG_LCD_CUR_YPOS1,          0x00},  /* LCD Cursor Y Position Register 1*/
+        {S1DREG_LCD_CUR_BCTL0,          0x00},  /* LCD Ink/Cursor Blue Color 0 Register*/
+        {S1DREG_LCD_CUR_GCTL0,          0x00},  /* LCD Ink/Cursor Green Color 0 Register*/
+        {S1DREG_LCD_CUR_RCTL0,          0x00},  /* LCD Ink/Cursor Red Color 0 Register*/
+        {S1DREG_LCD_CUR_BCTL1,          0x1F},  /* LCD Ink/Cursor Blue Color 1 Register*/
+        {S1DREG_LCD_CUR_GCTL1,          0x3F},  /* LCD Ink/Cursor Green Color 1 Register*/
+        {S1DREG_LCD_CUR_RCTL1,          0x1F},  /* LCD Ink/Cursor Red Color 1 Register*/
+        {S1DREG_LCD_CUR_FIFO_HTC,       0x00},  /* LCD Ink/Cursor FIFO Threshold Register*/
+        {S1DREG_CRT_CUR_CTL,            0x00},  /* CRT/TV Ink/Cursor Control Register*/
+        {S1DREG_CRT_CUR_START,          0x01},  /* CRT/TV Ink/Cursor Start Address Register*/
+        {S1DREG_CRT_CUR_XPOS0,          0x00},  /* CRT/TV Cursor X Position Register 0*/
+        {S1DREG_CRT_CUR_XPOS1,          0x00},  /* CRT/TV Cursor X Position Register 1*/
+        {S1DREG_CRT_CUR_YPOS0,          0x00},  /* CRT/TV Cursor Y Position Register 0*/
+        {S1DREG_CRT_CUR_YPOS1,          0x00},  /* CRT/TV Cursor Y Position Register 1*/
+        {S1DREG_CRT_CUR_BCTL0,          0x00},  /* CRT/TV Ink/Cursor Blue Color 0 Register*/
+        {S1DREG_CRT_CUR_GCTL0,          0x00},  /* CRT/TV Ink/Cursor Green Color 0 Register*/
+        {S1DREG_CRT_CUR_RCTL0,          0x00},  /* CRT/TV Ink/Cursor Red Color 0 Register*/
+        {S1DREG_CRT_CUR_BCTL1,          0x1F},  /* CRT/TV Ink/Cursor Blue Color 1 Register*/
+        {S1DREG_CRT_CUR_GCTL1,          0x3F},  /* CRT/TV Ink/Cursor Green Color 1 Register*/
+        {S1DREG_CRT_CUR_RCTL1,          0x1F},  /* CRT/TV Ink/Cursor Red Color 1 Register*/
+        {S1DREG_CRT_CUR_FIFO_HTC,       0x00},  /* CRT/TV Ink/Cursor FIFO Threshold Register*/
+        {S1DREG_BBLT_CTL0,              0x00},  /* BitBlt Control Register 0*/
+        {S1DREG_BBLT_CTL1,              0x01},  /* BitBlt Control Register 1*/
+        {S1DREG_BBLT_CC_EXP,            0x00},  /* BitBlt ROP Code/Color Expansion Register*/
+        {S1DREG_BBLT_OP,                0x00},  /* BitBlt Operation Register*/
+        {S1DREG_BBLT_SRC_START0,        0x00},  /* BitBlt Source Start Address Register 0*/
+        {S1DREG_BBLT_SRC_START1,        0x00},  /* BitBlt Source Start Address Register 1*/
+        {S1DREG_BBLT_SRC_START2,        0x00},  /* BitBlt Source Start Address Register 2*/
+        {S1DREG_BBLT_DST_START0,        0x00},  /* BitBlt Destination Start Address Register 0*/
+        {S1DREG_BBLT_DST_START1,        0x00},  /* BitBlt Destination Start Address Register 1*/
+        {S1DREG_BBLT_DST_START2,        0x00},  /* BitBlt Destination Start Address Register 2*/
+        {S1DREG_BBLT_MEM_OFF0,          0x00},  /* BitBlt Memory Address Offset Register 0*/
+        {S1DREG_BBLT_MEM_OFF1,          0x00},  /* BitBlt Memory Address Offset Register 1*/
+        {S1DREG_BBLT_WIDTH0,            0x00},  /* BitBlt Width Register 0*/
+        {S1DREG_BBLT_WIDTH1,            0x00},  /* BitBlt Width Register 1*/
+        {S1DREG_BBLT_HEIGHT0,           0x00},  /* BitBlt Height Register 0*/
+        {S1DREG_BBLT_HEIGHT1,           0x00},  /* BitBlt Height Register 1*/
+        {S1DREG_BBLT_BGC0,              0x00},  /* BitBlt Background Color Register 0*/
+        {S1DREG_BBLT_BGC1,              0x00},  /* BitBlt Background Color Register 1*/
+        {S1DREG_BBLT_FGC0,              0x00},  /* BitBlt Foreground Color Register 0*/
+        {S1DREG_BBLT_FGC1,              0x00},  /* BitBlt Foreground Color Register 1*/
+        {S1DREG_LKUP_MODE,              0x00},  /* Look-Up Table Mode Register*/
+        {S1DREG_LKUP_ADDR,              0x00},  /* Look-Up Table Address Register*/
+        {S1DREG_PS_CNF,                 0x00},  /* Power Save Configuration Register*/
+        {S1DREG_PS_STATUS,              0x00},  /* Power Save Status Register*/
+        {S1DREG_CPU2MEM_WDOGT,          0x00},  /* CPU-to-Memory Access Watchdog Timer Register*/
+        {S1DREG_COM_DISP_MODE,          0x01},  /* Display Mode Register, LCD only*/
 };
 
-static u64 s1dfb_dmamask = 0xffffffffUL;
+static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
 
-static struct s1d13xxxfb_pdata yl_9200_s1dfb_pdata = {
-                .initregs                               = yl_9200_s1dfb_initregs,
-                .initregssize                   = ARRAY_SIZE(yl_9200_s1dfb_initregs),
-                .platform_init_video    = yl_9200_init_video,
+static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
+        .initregs               = yl9200_s1dfb_initregs,
+        .initregssize           = ARRAY_SIZE(yl9200_s1dfb_initregs),
+        .platform_init_video    = yl9200_init_video,
 };
 
-static struct resource yl_9200_s1dfb_resource[] = {
+static struct resource yl9200_s1dfb_resource[] = {
         [0] = { /* video mem */
-                .name   = "s1d13xxxfb memory",
-        /*      .name   = "s1d13806 memory",*/
-                .start  = AT91_FB_VMEM_BASE,
-                .end    = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
-                .flags  = IORESOURCE_MEM,
+                .name   = "s1d13xxxfb memory",
+                .start  = AT91_FB_VMEM_BASE,
+                .end    = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
+                .flags  = IORESOURCE_MEM,
         },
         [1] = { /* video registers */
-                .name   = "s1d13xxxfb registers",
-        /*      .name   = "s1d13806 registers",*/
-                .start  = AT91_FB_REG_BASE,
-                .end    = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
-                .flags  = IORESOURCE_MEM,
+                .name   = "s1d13xxxfb registers",
+                .start  = AT91_FB_REG_BASE,
+                .end    = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
+                .flags  = IORESOURCE_MEM,
         },
 };
 
-static struct platform_device yl_9200_s1dfb_device = {
-        /*TODO S.Birtles , really we need the chip revision in here as well*/
-                .name           = "s1d13806fb",
-        /*  .name               = "s1d13506fb",*/
-                .id                     = -1,
-                .dev            = {
-        /*TODO theres a waring here!!*/
-        /*WARNING: vmlinux.o(.data+0x2dbc): Section mismatch: reference to .init.text: (between 'yl_9200_s1dfb_pdata' and 's1dfb_dmamask')*/
+static struct platform_device yl9200_s1dfb_device = {
+        .name           = "s1d13806fb",
+        .id             = -1,
+        .dev    = {
                 .dma_mask               = &s1dfb_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &yl_9200_s1dfb_pdata,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &yl9200_s1dfb_pdata,
         },
-        .resource       = yl_9200_s1dfb_resource,
-        .num_resources  = ARRAY_SIZE(yl_9200_s1dfb_resource),
+        .resource       = yl9200_s1dfb_resource,
+        .num_resources  = ARRAY_SIZE(yl9200_s1dfb_resource),
 };
 
-void __init yl_9200_add_device_video(void)
+void __init yl9200_add_device_video(void)
 {
-        platform_device_register(&yl_9200_s1dfb_device);
+        platform_device_register(&yl9200_s1dfb_device);
 }
 #else
-        void __init yl_9200_add_device_video(void) {}
+void __init yl9200_add_device_video(void) {}
 #endif
 
-/*this is not called first , yl_9200_map_io is called first*/
-static void __init yl_9200_board_init(void)
+
+static void __init yl9200_board_init(void)
 {
         /* Serial */
         at91_add_device_serial();
         /* Ethernet */
-        at91_add_device_eth(&yl_9200_eth_data);
+        at91_add_device_eth(&yl9200_eth_data);
         /* USB Host */
-        at91_add_device_usbh(&yl_9200_usbh_data);
+        at91_add_device_usbh(&yl9200_usbh_data);
         /* USB Device */
-        at91_add_device_udc(&yl_9200_udc_data);
-        /* pullup_pin it is  actually active low, but this is not needed, driver sets it up */
-        /*at91_set_multi_drive(yl_9200_udc_data.pullup_pin, 0);*/
-
-        /* Compact Flash */
-        /*at91_add_device_cf(&yl_9200_cf_data);*/
-
+        at91_add_device_udc(&yl9200_udc_data);
         /* I2C */
-        at91_add_device_i2c(yl_9200_i2c_devices, ARRAY_SIZE(yl_9200_i2c_devices));
-        /* SPI */
-        /*TODO YL9200 we have 2 spi interfaces touch screen & CAN*/
-        /* AT91_PIN_PA5, AT91_PIN_PA6 , are used on the  max 485 NOT SPI*/
-
-        /*touch screen and CAN*/
-        at91_add_device_spi(yl_9200_spi_devices, ARRAY_SIZE(yl_9200_spi_devices));
-
-        /*Basically the  TS uses  PB11 & PB10 , PB11 is configured by the SPI system BP10 IS NOT USED!!*/
-        /* we need this incase the board is running without a touch screen*/
-        #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-        at91_init_device_ts(); /*init the touch screen device*/
-        #endif
-        /* DataFlash card */
-        at91_add_device_mmc(0, &yl_9200_mmc_data);
+        at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
+        /* MMC */
+        at91_add_device_mmc(0, &yl9200_mmc_data);
         /* NAND */
-        at91_add_device_nand(&yl_9200_nand_data);
+        at91_add_device_nand(&yl9200_nand_data);
         /* NOR Flash */
-        platform_device_register(&yl_9200_flash);
-        /* LEDs. Note!! this does not include the led's we passed for the processor status */
-        at91_gpio_leds(yl_9200_leds, ARRAY_SIZE(yl_9200_leds));
-        /* VGA  */
-        /*this is self registered by including the s1d13xxx chip in the kernel build*/
-        yl_9200_add_device_video();
+        platform_device_register(&yl9200_flash);
+#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
+        /* SPI */
+        at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
+        /* Touchscreen */
+        yl9200_add_device_ts();
+#endif
+        /* LEDs. */
+        at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
         /* Push Buttons */
-        yl_9200_add_device_buttons();
-        /*TODO fixup the Sounder */
-//      yl_9200_add_device_sounder(yl_9200_sounder,ARRAY_SIZE(yl_9200_sounder));
-
+        yl9200_add_device_buttons();
+        /* VGA */
+        yl9200_add_device_video();
 }
 
 MACHINE_START(YL9200, "uCdragon YL-9200")
-        /* Maintainer: S.Birtles*/
-        .phys_io                = AT91_BASE_SYS,
+        /* Maintainer: S.Birtles */
+        .phys_io        = AT91_BASE_SYS,
         .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
-        .timer                  = &at91rm9200_timer,
-        .map_io                 = yl_9200_map_io,
-        .init_irq               = yl_9200_init_irq,
-        .init_machine   = yl_9200_board_init,
+        .timer          = &at91rm9200_timer,
+        .map_io         = yl9200_map_io,
+        .init_irq       = yl9200_init_irq,
+        .init_machine   = yl9200_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index a33dfe450726..464bdbbf74df 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -112,12 +112,34 @@ static void pmc_sys_mode(struct clk *clk, int is_on)
                 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
 }
 
+static void pmc_uckr_mode(struct clk *clk, int is_on)
+{
+        unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
+
+        if (is_on) {
+                is_on = AT91_PMC_LOCKU;
+                at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
+        } else
+                at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
+
+        do {
+                cpu_relax();
+        } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
+}
+
 /* USB function clocks (PLLB must be 48 MHz) */
 static struct clk udpck = {
         .name           = "udpck",
         .parent         = &pllb,
         .mode           = pmc_sys_mode,
 };
+static struct clk utmi_clk = {
+        .name           = "utmi_clk",
+        .parent         = &main_clk,
+        .pmc_mask       = AT91_PMC_UPLLEN,      /* in CKGR_UCKR */
+        .mode           = pmc_uckr_mode,
+        .type           = CLK_TYPE_PLL,
+};
 static struct clk uhpck = {
         .name           = "uhpck",
         .parent         = &pllb,
@@ -361,7 +383,7 @@ static void __init init_programmable_clock(struct clk *clk)
 
 static int at91_clk_show(struct seq_file *s, void *unused)
 {
-        u32             scsr, pcsr, sr;
+        u32             scsr, pcsr, uckr = 0, sr;
         struct clk      *clk;
 
         seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
@@ -369,7 +391,10 @@ static int at91_clk_show(struct seq_file *s, void *unused)
         seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
         seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
         seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
-        seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
+        if (!cpu_is_at91sam9rl())
+                seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
+        if (cpu_is_at91cap9() || cpu_is_at91sam9rl())
+                seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
         seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
         seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
 
@@ -382,6 +407,8 @@ static int at91_clk_show(struct seq_file *s, void *unused)
                         state = (scsr & clk->pmc_mask) ? "on" : "off";
                 else if (clk->mode == pmc_periph_mode)
                         state = (pcsr & clk->pmc_mask) ? "on" : "off";
+                else if (clk->mode == pmc_uckr_mode)
+                        state = (uckr & clk->pmc_mask) ? "on" : "off";
                 else if (clk->pmc_mask)
                         state = (sr & clk->pmc_mask) ? "on" : "off";
                 else if (clk == &clk32k || clk == &main_clk)
@@ -488,14 +515,19 @@ static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
                 /*
                  * PLL input between 1MHz and 32MHz per spec, but lower
                  * frequences seem necessary in some cases so allow 100K.
+                 * Warning: some newer products need 2MHz min.
                  */
                 input = main_freq / i;
+                if (cpu_is_at91sam9g20() && input < 2000000)
+                        continue;
                 if (input < 100000)
                         continue;
                 if (input > 32000000)
                         continue;
 
                 mul1 = out_freq / input;
+                if (cpu_is_at91sam9g20() && mul > 63)
+                        continue;
                 if (mul1 > 2048)
                         continue;
                 if (mul1 < 2)
@@ -555,7 +587,8 @@ int __init at91_clock_init(unsigned long main_clock)
 
         /* report if PLLA is more than mildly overclocked */
         plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
-        if (plla.rate_hz > 209000000)
+        if ((!cpu_is_at91sam9g20() && plla.rate_hz > 209000000)
+           || (cpu_is_at91sam9g20() && plla.rate_hz > 800000000))
                 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 
         /*
@@ -570,7 +603,7 @@ int __init at91_clock_init(unsigned long main_clock)
                 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
                 udpck.pmc_mask = AT91RM9200_PMC_UDP;
                 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
-        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) {
+        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
         } else if (cpu_is_at91cap9()) {
@@ -582,6 +615,17 @@ int __init at91_clock_init(unsigned long main_clock)
         uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 
         /*
+         * USB HS clock init
+         */
+        if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) {
+                /*
+                 * multiplier is hard-wired to 40
+                 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
+                 */
+                utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
+        }
+
+        /*
          * MCK and CPU derive from one of those primary clocks.
          * For now, assume this parentage won't change.
          */
@@ -591,13 +635,21 @@ int __init at91_clock_init(unsigned long main_clock)
         freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));                           /* prescale */
         if (cpu_is_at91rm9200())
                 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
-        else
-                mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
+        else if (cpu_is_at91sam9g20()) {
+                mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
+                        freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;    /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
+                if (mckr & AT91_PMC_PDIV)
+                        freq /= 2;              /* processor clock division */
+        } else
+                mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
 
         /* Register the PMC's standard clocks */
         for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
                 list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
 
+        if (cpu_is_at91cap9() || cpu_is_at91sam9rl())
+                list_add_tail(&utmi_clk.node, &clocks);
+
         /* MCK and CPU clock are "always on" */
         clk_enable(&mck);
 
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index aa863c157708..8ab4feb1ec5b 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -202,7 +202,7 @@ static int at91_pm_verify_clocks(void)
                         pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
                         return 0;
                 }
-        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) {
+        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
                 if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) {
                         pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
                         return 0;
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 9d7515c36bff..f62c35500bb7 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -74,6 +74,7 @@ struct clk *clk_get(struct device *dev, const char *id)
 
         return ERR_PTR(-ENOENT);
 }
+EXPORT_SYMBOL(clk_get);
 
 int clk_enable(struct clk *clk)
 {
@@ -86,6 +87,7 @@ int clk_enable(struct clk *clk)
 
         return 0;
 }
+EXPORT_SYMBOL(clk_enable);
 
 void clk_disable(struct clk *clk)
 {
@@ -96,15 +98,18 @@ void clk_disable(struct clk *clk)
                 __raw_writel(value & ~clk->enable_mask, clk->enable_reg);
         }
 }
+EXPORT_SYMBOL(clk_disable);
 
 unsigned long clk_get_rate(struct clk *clk)
 {
         return clk->rate;
 }
+EXPORT_SYMBOL(clk_get_rate);
 
 void clk_put(struct clk *clk)
 {
 }
+EXPORT_SYMBOL(clk_put);
 
 
 
diff --git a/arch/arm/mach-footbridge/Makefile b/arch/arm/mach-footbridge/Makefile
index 0694ad6b6476..32f8609e4f85 100644
--- a/arch/arm/mach-footbridge/Makefile
+++ b/arch/arm/mach-footbridge/Makefile
@@ -14,12 +14,10 @@ pci-$(CONFIG_ARCH_EBSA285_HOST) += ebsa285-pci.o
 pci-$(CONFIG_ARCH_NETWINDER) += netwinder-pci.o
 pci-$(CONFIG_ARCH_PERSONAL_SERVER) += personal-pci.o
 
-leds-$(CONFIG_ARCH_CO285) += ebsa285-leds.o
 leds-$(CONFIG_ARCH_EBSA285) += ebsa285-leds.o
 leds-$(CONFIG_ARCH_NETWINDER) += netwinder-leds.o
 
 obj-$(CONFIG_ARCH_CATS) += cats-hw.o isa-timer.o
-obj-$(CONFIG_ARCH_CO285) += co285.o dc21285-timer.o
 obj-$(CONFIG_ARCH_EBSA285) += ebsa285.o dc21285-timer.o
 obj-$(CONFIG_ARCH_NETWINDER) += netwinder-hw.o isa-timer.o
 obj-$(CONFIG_ARCH_PERSONAL_SERVER) += personal.o dc21285-timer.o
diff --git a/arch/arm/mach-footbridge/co285.c b/arch/arm/mach-footbridge/co285.c
deleted file mode 100644
index 4545576ad8d9..000000000000
--- a/arch/arm/mach-footbridge/co285.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * linux/arch/arm/mach-footbridge/co285.c
- *
- * CO285 machine fixup
- */
-#include <linux/init.h>
-
-#include <asm/hardware/dec21285.h>
-#include <asm/mach-types.h>
-
-#include <asm/mach/arch.h>
-
-#include "common.h"
-
-static void __init
-fixup_coebsa285(struct machine_desc *desc, struct tag *tags,
-                char **cmdline, struct meminfo *mi)
-{
-        extern unsigned long boot_memory_end;
-        extern char boot_command_line[];
-
-        mi->nr_banks      = 1;
-        mi->bank[0].start = PHYS_OFFSET;
-        mi->bank[0].size  = boot_memory_end;
-        mi->bank[0].node  = 0;
-
-        *cmdline = boot_command_line;
-}
-
-MACHINE_START(CO285, "co-EBSA285")
-        /* Maintainer: Mark van Doesburg */
-        .phys_io        = DC21285_ARMCSR_BASE,
-        .io_pg_offst    = ((0x7cf00000) >> 18) & 0xfffc,
-        .fixup          = fixup_coebsa285,
-        .map_io         = footbridge_map_io,
-        .init_irq       = footbridge_init_irq,
-        .timer          = &footbridge_timer,
-MACHINE_END
-
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index ef29fc34ce65..b08ab507c052 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -177,25 +177,6 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = {
 #endif
 };
 
-/*
- * The CO-ebsa285 mapping.
- */
-static struct map_desc co285_io_desc[] __initdata = {
-#ifdef CONFIG_ARCH_CO285
-        {
-                .virtual        = PCIO_BASE,
-                .pfn            = __phys_to_pfn(DC21285_PCI_IO),
-                .length         = PCIO_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = PCIMEM_BASE,
-                .pfn            = __phys_to_pfn(DC21285_PCI_MEM),
-                .length         = PCIMEM_SIZE,
-                .type           = MT_DEVICE,
-        },
-#endif
-};
-
 void __init footbridge_map_io(void)
 {
         /*
@@ -208,8 +189,6 @@ void __init footbridge_map_io(void)
          * Now, work out what we've got to map in addition on this
          * platform.
          */
-        if (machine_is_co285())
-                iotable_init(co285_io_desc, ARRAY_SIZE(co285_io_desc));
         if (footbridge_cfn_mode())
                 iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
 }
diff --git a/arch/arm/mach-footbridge/ebsa285-leds.c b/arch/arm/mach-footbridge/ebsa285-leds.c
index a64e22226515..09c1fbc51876 100644
--- a/arch/arm/mach-footbridge/ebsa285-leds.c
+++ b/arch/arm/mach-footbridge/ebsa285-leds.c
@@ -128,7 +128,7 @@ static void ebsa285_leds_event(led_event_t evt)
 
 static int __init leds_init(void)
 {
-        if (machine_is_ebsa285() || machine_is_co285())
+        if (machine_is_ebsa285())
                 leds_event = ebsa285_leds_event;
 
         leds_event(led_start);
diff --git a/arch/arm/mach-footbridge/time.c b/arch/arm/mach-footbridge/time.c
index 5d02e95dede3..d5cfcda385d6 100644
--- a/arch/arm/mach-footbridge/time.c
+++ b/arch/arm/mach-footbridge/time.c
@@ -115,8 +115,7 @@ static int set_isa_cmos_time(void)
 
 void __init isa_rtc_init(void)
 {
-        if (machine_is_co285() ||
-            machine_is_personal_server())
+        if (machine_is_personal_server())
                 /*
                  * Add-in 21285s shouldn't access the RTC
                  */
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 88d5e61a2e13..b047c7e795a9 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -4,7 +4,7 @@
 
 # Object file lists.
 
-obj-y                   += irq.o time.o dma.o generic.o
+obj-y                   += irq.o time.o dma.o generic.o clock.o
 
 obj-$(CONFIG_CPU_FREQ_IMX)      += cpufreq.o
 
diff --git a/arch/arm/mach-imx/clock.c b/arch/arm/mach-imx/clock.c
new file mode 100644
index 000000000000..6a90fe5578df
--- /dev/null
+++ b/arch/arm/mach-imx/clock.c
@@ -0,0 +1,205 @@
+/*
+ *  Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/math64.h>
+#include <linux/err.h>
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * Very simple approach: We can't disable clocks, so we do
+ * not need refcounting
+ */
+
+struct clk {
+        struct list_head node;
+        const char *name;
+        unsigned long (*get_rate)(void);
+};
+
+/*
+ *  get the system pll clock in Hz
+ *
+ *                  mfi + mfn / (mfd +1)
+ *  f = 2 * f_ref * --------------------
+ *                        pd + 1
+ */
+static unsigned long imx_decode_pll(unsigned int pll, u32 f_ref)
+{
+        unsigned long long ll;
+        unsigned long quot;
+
+        u32 mfi = (pll >> 10) & 0xf;
+        u32 mfn = pll & 0x3ff;
+        u32 mfd = (pll >> 16) & 0x3ff;
+        u32 pd =  (pll >> 26) & 0xf;
+
+        mfi = mfi <= 5 ? 5 : mfi;
+
+        ll = 2 * (unsigned long long)f_ref *
+                ((mfi << 16) + (mfn << 16) / (mfd + 1));
+        quot = (pd + 1) * (1 << 16);
+        ll += quot / 2;
+        do_div(ll, quot);
+        return (unsigned long)ll;
+}
+
+static unsigned long imx_get_system_clk(void)
+{
+        u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
+
+        return imx_decode_pll(SPCTL0, f_ref);
+}
+
+static unsigned long imx_get_mcu_clk(void)
+{
+        return imx_decode_pll(MPCTL0, CLK32 * 512);
+}
+
+/*
+ *  get peripheral clock 1 ( UART[12], Timer[12], PWM )
+ */
+static unsigned long imx_get_perclk1(void)
+{
+        return imx_get_system_clk() / (((PCDR) & 0xf)+1);
+}
+
+/*
+ *  get peripheral clock 2 ( LCD, SD, SPI[12] )
+ */
+static unsigned long imx_get_perclk2(void)
+{
+        return imx_get_system_clk() / (((PCDR>>4) & 0xf)+1);
+}
+
+/*
+ *  get peripheral clock 3 ( SSI )
+ */
+static unsigned long imx_get_perclk3(void)
+{
+        return imx_get_system_clk() / (((PCDR>>16) & 0x7f)+1);
+}
+
+/*
+ *  get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
+ */
+static unsigned long imx_get_hclk(void)
+{
+        return imx_get_system_clk() / (((CSCR>>10) & 0xf)+1);
+}
+
+static struct clk clk_system_clk = {
+        .name = "system_clk",
+        .get_rate = imx_get_system_clk,
+};
+
+static struct clk clk_hclk = {
+        .name = "hclk",
+        .get_rate = imx_get_hclk,
+};
+
+static struct clk clk_mcu_clk = {
+        .name = "mcu_clk",
+        .get_rate = imx_get_mcu_clk,
+};
+
+static struct clk clk_perclk1 = {
+        .name = "perclk1",
+        .get_rate = imx_get_perclk1,
+};
+
+static struct clk clk_uart_clk = {
+        .name = "uart_clk",
+        .get_rate = imx_get_perclk1,
+};
+
+static struct clk clk_perclk2 = {
+        .name = "perclk2",
+        .get_rate = imx_get_perclk2,
+};
+
+static struct clk clk_perclk3 = {
+        .name = "perclk3",
+        .get_rate = imx_get_perclk3,
+};
+
+static struct clk *clks[] = {
+        &clk_perclk1,
+        &clk_perclk2,
+        &clk_perclk3,
+        &clk_system_clk,
+        &clk_hclk,
+        &clk_mcu_clk,
+        &clk_uart_clk,
+};
+
+static LIST_HEAD(clocks);
+static DEFINE_MUTEX(clocks_mutex);
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+        struct clk *p, *clk = ERR_PTR(-ENOENT);
+
+        mutex_lock(&clocks_mutex);
+        list_for_each_entry(p, &clocks, node) {
+                if (!strcmp(p->name, id)) {
+                        clk = p;
+                        goto found;
+                }
+        }
+
+found:
+        mutex_unlock(&clocks_mutex);
+
+        return clk;
+}
+
+void clk_put(struct clk *clk)
+{
+}
+
+int clk_enable(struct clk *clk)
+{
+        return 0;
+}
+
+void clk_disable(struct clk *clk)
+{
+}
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return clk->get_rate();
+}
+
+int imx_clocks_init(void)
+{
+        int i;
+
+        mutex_lock(&clocks_mutex);
+        for (i = 0; i < ARRAY_SIZE(clks); i++)
+                list_add(&clks[i]->node, &clocks);
+        mutex_unlock(&clocks_mutex);
+
+        return 0;
+}
+
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
index e548ba74a4d2..be0809b33e08 100644
--- a/arch/arm/mach-imx/cpufreq.c
+++ b/arch/arm/mach-imx/cpufreq.c
@@ -32,6 +32,8 @@
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/cpufreq.h>
+#include <linux/clk.h>
+#include <linux/err.h>
 #include <asm/system.h>
 
 #include <asm/hardware.h>
@@ -52,6 +54,8 @@
 static u32 mpctl0_at_boot;
 static u32 bclk_div_at_boot;
 
+static struct clk *system_clk, *mcu_clk;
+
 static void imx_set_async_mode(void)
 {
         adjust_cr(CR_920T_CLOCK_MODE, CR_920T_ASYNC_MODE);
@@ -160,10 +164,10 @@ static unsigned int imx_get_speed(unsigned int cpu)
         cr = get_cr();
 
         if((cr & CR_920T_CLOCK_MODE) == CR_920T_FASTBUS_MODE) {
-                freq = imx_get_system_clk();
+                freq = clk_get_rate(system_clk);
                 freq = (freq + bclk_div/2) / bclk_div;
         } else {
-                freq = imx_get_mcu_clk();
+                freq = clk_get_rate(mcu_clk);
                 if (cscr & CSCR_MPU_PRESC)
                         freq /= 2;
         }
@@ -201,7 +205,7 @@ static int imx_set_target(struct cpufreq_policy *policy,
         pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n",
                         freq, mpctl0_at_boot);
 
-        sysclk = imx_get_system_clk();
+        sysclk = clk_get_rate(system_clk);
 
         if (freq > sysclk / bclk_div_at_boot + 1000000) {
                 freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, CLK32 * 512, freq, relation);
@@ -290,6 +294,16 @@ static int __init imx_cpufreq_init(void)
         bclk_div_at_boot = __mfld2val(CSCR_BCLK_DIV, CSCR) + 1;
         mpctl0_at_boot = 0;
 
+        system_clk = clk_get(NULL, "system_clk");
+        if (IS_ERR(system_clk))
+                return PTR_ERR(system_clk);
+
+        mcu_clk = clk_get(NULL, "mcu_clk");
+        if (IS_ERR(mcu_clk)) {
+                clk_put(system_clk);
+                return PTR_ERR(mcu_clk);
+        }
+
         if((CSCR & CSCR_MPEN) &&
            ((get_cr() & CR_920T_CLOCK_MODE) != CR_920T_FASTBUS_MODE))
                 mpctl0_at_boot = MPCTL0;
diff --git a/arch/arm/mach-imx/dma.c b/arch/arm/mach-imx/dma.c
index a59ff2987cb7..ee1c6f06ff64 100644
--- a/arch/arm/mach-imx/dma.c
+++ b/arch/arm/mach-imx/dma.c
@@ -410,7 +410,6 @@ void imx_dma_free(imx_dmach_t dma_ch)
 
 /**
  * imx_dma_request_by_prio - find and request some of free channels best suiting requested priority
- * @dma_ch: i.MX DMA channel number
  * @name: the driver/caller own non-%NULL identification
  * @prio: one of the hardware distinguished priority level:
  *        %DMA_PRIO_HIGH, %DMA_PRIO_MEDIUM, %DMA_PRIO_LOW
@@ -420,11 +419,9 @@ void imx_dma_free(imx_dmach_t dma_ch)
  * in the higher and then even lower priority groups.
  *
  * Return value: If there is no free channel to allocate, -%ENODEV is returned.
- *               Zero value indicates successful channel allocation.
+ *               On successful allocation channel is returned.
  */
-int
-imx_dma_request_by_prio(imx_dmach_t * pdma_ch, const char *name,
-                        imx_dma_prio prio)
+imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio)
 {
         int i;
         int best;
@@ -444,15 +441,13 @@ imx_dma_request_by_prio(imx_dmach_t * pdma_ch, const char *name,
 
         for (i = best; i < IMX_DMA_CHANNELS; i++) {
                 if (!imx_dma_request(i, name)) {
-                        *pdma_ch = i;
-                        return 0;
+                        return i;
                 }
         }
 
         for (i = best - 1; i >= 0; i--) {
                 if (!imx_dma_request(i, name)) {
-                        *pdma_ch = i;
-                        return 0;
+                        return i;
                 }
         }
 
diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c
index 4cfc9d3af28a..98ddd8a6d05f 100644
--- a/arch/arm/mach-imx/generic.c
+++ b/arch/arm/mach-imx/generic.c
@@ -214,82 +214,6 @@ int imx_irq_to_gpio(unsigned irq)
 
 EXPORT_SYMBOL(imx_irq_to_gpio);
 
-/*
- *  get the system pll clock in Hz
- *
- *                  mfi + mfn / (mfd +1)
- *  f = 2 * f_ref * --------------------
- *                        pd + 1
- */
-static unsigned int imx_decode_pll(unsigned int pll, u32 f_ref)
-{
-        unsigned long long ll;
-        unsigned long quot;
-
-        u32 mfi = (pll >> 10) & 0xf;
-        u32 mfn = pll & 0x3ff;
-        u32 mfd = (pll >> 16) & 0x3ff;
-        u32 pd =  (pll >> 26) & 0xf;
-
-        mfi = mfi <= 5 ? 5 : mfi;
-
-        ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) );
-        quot = (pd+1) * (1<<16);
-        ll += quot / 2;
-        do_div(ll, quot);
-        return (unsigned int) ll;
-}
-
-unsigned int imx_get_system_clk(void)
-{
-        u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
-
-        return imx_decode_pll(SPCTL0, f_ref);
-}
-EXPORT_SYMBOL(imx_get_system_clk);
-
-unsigned int imx_get_mcu_clk(void)
-{
-        return imx_decode_pll(MPCTL0, CLK32 * 512);
-}
-EXPORT_SYMBOL(imx_get_mcu_clk);
-
-/*
- *  get peripheral clock 1 ( UART[12], Timer[12], PWM )
- */
-unsigned int imx_get_perclk1(void)
-{
-        return imx_get_system_clk() / (((PCDR) & 0xf)+1);
-}
-EXPORT_SYMBOL(imx_get_perclk1);
-
-/*
- *  get peripheral clock 2 ( LCD, SD, SPI[12] )
- */
-unsigned int imx_get_perclk2(void)
-{
-        return imx_get_system_clk() / (((PCDR>>4) & 0xf)+1);
-}
-EXPORT_SYMBOL(imx_get_perclk2);
-
-/*
- *  get peripheral clock 3 ( SSI )
- */
-unsigned int imx_get_perclk3(void)
-{
-        return imx_get_system_clk() / (((PCDR>>16) & 0x7f)+1);
-}
-EXPORT_SYMBOL(imx_get_perclk3);
-
-/*
- *  get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
- */
-unsigned int imx_get_hclk(void)
-{
-        return imx_get_system_clk() / (((CSCR>>10) & 0xf)+1);
-}
-EXPORT_SYMBOL(imx_get_hclk);
-
 static struct resource imx_mmc_resources[] = {
         [0] = {
                 .start  = 0x00214000,
diff --git a/arch/arm/mach-imx/mx1ads.c b/arch/arm/mach-imx/mx1ads.c
index a9778c1587ab..9635d5812bcd 100644
--- a/arch/arm/mach-imx/mx1ads.c
+++ b/arch/arm/mach-imx/mx1ads.c
@@ -69,6 +69,11 @@ static struct resource imx_uart1_resources[] = {
                 .end    = (UART1_MINT_TX),
                 .flags  = IORESOURCE_IRQ,
         },
+        [3] = {
+                .start  = UART1_MINT_RTS,
+                .end    = UART1_MINT_RTS,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 
 static struct platform_device imx_uart1_device = {
@@ -97,6 +102,11 @@ static struct resource imx_uart2_resources[] = {
                 .end    = (UART2_MINT_TX),
                 .flags  = IORESOURCE_IRQ,
         },
+        [3] = {
+                .start  = UART2_MINT_RTS,
+                .end    = UART2_MINT_RTS,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 
 static struct platform_device imx_uart2_device = {
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index d86d124aea22..5a41e96e8586 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -17,6 +17,7 @@
 #include <linux/time.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
+#include <linux/clk.h>
 
 #include <asm/hardware.h>
 #include <asm/io.h>
@@ -86,10 +87,10 @@ static struct clocksource clocksource_imx = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-static int __init imx_clocksource_init(void)
+static int __init imx_clocksource_init(unsigned long rate)
 {
         clocksource_imx.mult =
-                clocksource_hz2mult(imx_get_perclk1(), clocksource_imx.shift);
+                clocksource_hz2mult(rate, clocksource_imx.shift);
         clocksource_register(&clocksource_imx);
 
         return 0;
@@ -174,9 +175,9 @@ static struct clock_event_device clockevent_imx = {
         .rating         = 200,
 };
 
-static int __init imx_clockevent_init(void)
+static int __init imx_clockevent_init(unsigned long rate)
 {
-        clockevent_imx.mult = div_sc(imx_get_perclk1(), NSEC_PER_SEC,
+        clockevent_imx.mult = div_sc(rate, NSEC_PER_SEC,
                                         clockevent_imx.shift);
         clockevent_imx.max_delta_ns =
                 clockevent_delta2ns(0xfffffffe, &clockevent_imx);
@@ -190,13 +191,23 @@ static int __init imx_clockevent_init(void)
         return 0;
 }
 
+extern int imx_clocks_init(void);
 
 static void __init imx_timer_init(void)
 {
+        struct clk *clk;
+        unsigned long rate;
+
+        imx_clocks_init();
+
+        clk = clk_get(NULL, "perclk1");
+        clk_enable(clk);
+        rate = clk_get_rate(clk);
+
         imx_timer_hardware_init();
-        imx_clocksource_init();
+        imx_clocksource_init(rate);
 
-        imx_clockevent_init();
+        imx_clockevent_init(rate);
 
         /*
          * Make irqs happen for the system timer
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index 158daaf9e3b0..6a5ef8d30b10 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -4,7 +4,7 @@
 
 # Object file lists.
 
-obj-y                                   := clock.o core.o lm.o time.o
+obj-y                                   := clock.o core.o lm.o
 obj-$(CONFIG_ARCH_INTEGRATOR_AP)        += integrator_ap.o
 obj-$(CONFIG_ARCH_INTEGRATOR_CP)        += integrator_cp.o
 
diff --git a/arch/arm/mach-integrator/time.c b/arch/arm/mach-integrator/time.c
deleted file mode 100644
index 8508a0db3eaf..000000000000
--- a/arch/arm/mach-integrator/time.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- *  linux/arch/arm/mach-integrator/time.c
- *
- *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/time.h>
-#include <linux/mc146818rtc.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-
-#include <asm/hardware.h>
-#include <asm/io.h>
-#include <asm/uaccess.h>
-#include <asm/rtc.h>
-
-#include <asm/mach/time.h>
-
-#define RTC_DR          (0)
-#define RTC_MR          (4)
-#define RTC_STAT        (8)
-#define RTC_EOI         (8)
-#define RTC_LR          (12)
-#define RTC_CR          (16)
-#define RTC_CR_MIE      (1 << 0)
-
-extern int (*set_rtc)(void);
-static void __iomem *rtc_base;
-
-static int integrator_set_rtc(void)
-{
-        __raw_writel(xtime.tv_sec, rtc_base + RTC_LR);
-        return 1;
-}
-
-static int integrator_rtc_read_alarm(struct rtc_wkalrm *alrm)
-{
-        rtc_time_to_tm(readl(rtc_base + RTC_MR), &alrm->time);
-        return 0;
-}
-
-static inline int integrator_rtc_set_alarm(struct rtc_wkalrm *alrm)
-{
-        unsigned long time;
-        int ret;
-
-        /*
-         * At the moment, we can only deal with non-wildcarded alarm times.
-         */
-        ret = rtc_valid_tm(&alrm->time);
-        if (ret == 0)
-                ret = rtc_tm_to_time(&alrm->time, &time);
-        if (ret == 0)
-                writel(time, rtc_base + RTC_MR);
-        return ret;
-}
-
-static int integrator_rtc_read_time(struct rtc_time *tm)
-{
-        rtc_time_to_tm(readl(rtc_base + RTC_DR), tm);
-        return 0;
-}
-
-/*
- * Set the RTC time.  Unfortunately, we can't accurately set
- * the point at which the counter updates.
- *
- * Also, since RTC_LR is transferred to RTC_CR on next rising
- * edge of the 1Hz clock, we must write the time one second
- * in advance.
- */
-static inline int integrator_rtc_set_time(struct rtc_time *tm)
-{
-        unsigned long time;
-        int ret;
-
-        ret = rtc_tm_to_time(tm, &time);
-        if (ret == 0)
-                writel(time + 1, rtc_base + RTC_LR);
-
-        return ret;
-}
-
-static struct rtc_ops rtc_ops = {
-        .owner          = THIS_MODULE,
-        .read_time      = integrator_rtc_read_time,
-        .set_time       = integrator_rtc_set_time,
-        .read_alarm     = integrator_rtc_read_alarm,
-        .set_alarm      = integrator_rtc_set_alarm,
-};
-
-static irqreturn_t arm_rtc_interrupt(int irq, void *dev_id)
-{
-        writel(0, rtc_base + RTC_EOI);
-        return IRQ_HANDLED;
-}
-
-static int rtc_probe(struct amba_device *dev, void *id)
-{
-        int ret;
-
-        if (rtc_base)
-                return -EBUSY;
-
-        ret = amba_request_regions(dev, NULL);
-        if (ret)
-                goto out;
-
-        rtc_base = ioremap(dev->res.start, SZ_4K);
-        if (!rtc_base) {
-                ret = -ENOMEM;
-                goto res_out;
-        }
-
-        __raw_writel(0, rtc_base + RTC_CR);
-        __raw_writel(0, rtc_base + RTC_EOI);
-
-        xtime.tv_sec = __raw_readl(rtc_base + RTC_DR);
-
-        /* note that 'dev' is merely used for irq disambiguation;
-         * it is not actually referenced in the irq handler
-         */
-        ret = request_irq(dev->irq[0], arm_rtc_interrupt, IRQF_DISABLED,
-                          "rtc-pl030", dev);
-        if (ret)
-                goto map_out;
-
-        ret = register_rtc(&rtc_ops);
-        if (ret)
-                goto irq_out;
-
-        set_rtc = integrator_set_rtc;
-        return 0;
-
- irq_out:
-        free_irq(dev->irq[0], dev);
- map_out:
-        iounmap(rtc_base);
-        rtc_base = NULL;
- res_out:
-        amba_release_regions(dev);
- out:
-        return ret;
-}
-
-static int rtc_remove(struct amba_device *dev)
-{
-        set_rtc = NULL;
-
-        writel(0, rtc_base + RTC_CR);
-
-        free_irq(dev->irq[0], dev);
-        unregister_rtc(&rtc_ops);
-
-        iounmap(rtc_base);
-        rtc_base = NULL;
-        amba_release_regions(dev);
-
-        return 0;
-}
-
-static struct timespec rtc_delta;
-
-static int rtc_suspend(struct amba_device *dev, pm_message_t state)
-{
-        struct timespec rtc;
-
-        rtc.tv_sec = readl(rtc_base + RTC_DR);
-        rtc.tv_nsec = 0;
-        save_time_delta(&rtc_delta, &rtc);
-
-        return 0;
-}
-
-static int rtc_resume(struct amba_device *dev)
-{
-        struct timespec rtc;
-
-        rtc.tv_sec = readl(rtc_base + RTC_DR);
-        rtc.tv_nsec = 0;
-        restore_time_delta(&rtc_delta, &rtc);
-
-        return 0;
-}
-
-static struct amba_id rtc_ids[] = {
-        {
-                .id     = 0x00041030,
-                .mask   = 0x000fffff,
-        },
-        { 0, 0 },
-};
-
-static struct amba_driver rtc_driver = {
-        .drv            = {
-                .name   = "rtc-pl030",
-        },
-        .probe          = rtc_probe,
-        .remove         = rtc_remove,
-        .suspend        = rtc_suspend,
-        .resume         = rtc_resume,
-        .id_table       = rtc_ids,
-};
-
-static int __init integrator_rtc_init(void)
-{
-        return amba_driver_register(&rtc_driver);
-}
-
-static void __exit integrator_rtc_exit(void)
-{
-        amba_driver_unregister(&rtc_driver);
-}
-
-module_init(integrator_rtc_init);
-module_exit(integrator_rtc_exit);
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index e774447c0592..db8b5fe06c0d 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -125,6 +125,15 @@ config	ARCH_IXDP4XX
         depends on ARCH_IXDP425 || MACH_IXDP465 || MACH_KIXRP435
         default y
 
+config MACH_FSG
+        bool
+        prompt "Freecom FSG-3"
+        select PCI
+        help
+          Say 'Y' here if you want your kernel to support Freecom's
+          FSG-3 device. For more information on this platform,
+          see http://www.nslu2-linux.org/wiki/FSG3/HomePage
+
 #
 # Certain registers and IRQs are only enabled if supporting IXP465 CPUs
 #
diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
index c1956882c48b..2e6bbf927a74 100644
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -15,6 +15,7 @@ obj-pci-$(CONFIG_MACH_NAS100D)		+= nas100d-pci.o
 obj-pci-$(CONFIG_MACH_DSMG600)          += dsmg600-pci.o
 obj-pci-$(CONFIG_MACH_GATEWAY7001)      += gateway7001-pci.o
 obj-pci-$(CONFIG_MACH_WG302V2)          += wg302v2-pci.o
+obj-pci-$(CONFIG_MACH_FSG)              += fsg-pci.o
 
 obj-y   += common.o
 
@@ -28,6 +29,7 @@ obj-$(CONFIG_MACH_NAS100D)	+= nas100d-setup.o
 obj-$(CONFIG_MACH_DSMG600)      += dsmg600-setup.o
 obj-$(CONFIG_MACH_GATEWAY7001)  += gateway7001-setup.o
 obj-$(CONFIG_MACH_WG302V2)      += wg302v2-setup.o
+obj-$(CONFIG_MACH_FSG)          += fsg-setup.o
 
 obj-$(CONFIG_PCI)               += $(obj-pci-$(CONFIG_PCI)) common-pci.o
 obj-$(CONFIG_IXP4XX_QMGR)       += ixp4xx_qmgr.o
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index f6d66dce6852..3781b3db9f49 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -326,11 +326,11 @@ static struct resource ixp4xx_udc_resources[] = {
 };
 
 /*
- * USB device controller. The IXP4xx uses the same controller as PXA2XX,
+ * USB device controller. The IXP4xx uses the same controller as PXA25X,
  * so we just use the same device.
  */
 static struct platform_device ixp4xx_udc_device = {
-        .name           = "pxa2xx-udc",
+        .name           = "pxa25x-udc",
         .id             = -1,
         .num_resources  = 2,
         .resource       = ixp4xx_udc_resources,
diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c
new file mode 100644
index 000000000000..f19f3f6feda1
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/fsg-pci.c
@@ -0,0 +1,71 @@
+/*
+ * arch/arch/mach-ixp4xx/fsg-pci.c
+ *
+ * FSG board-level PCI initialization
+ *
+ * Author: Rod Whitby <rod@whitby.id.au>
+ * Maintainer: http://www.nslu2-linux.org/
+ *
+ * based on ixdp425-pci.c:
+ *      Copyright (C) 2002 Intel Corporation.
+ *      Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+#include <asm/mach/pci.h>
+#include <asm/mach-types.h>
+
+void __init fsg_pci_preinit(void)
+{
+        set_irq_type(IRQ_FSG_PCI_INTA, IRQT_LOW);
+        set_irq_type(IRQ_FSG_PCI_INTB, IRQT_LOW);
+        set_irq_type(IRQ_FSG_PCI_INTC, IRQT_LOW);
+
+        ixp4xx_pci_preinit();
+}
+
+static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        static int pci_irq_table[FSG_PCI_IRQ_LINES] = {
+                IRQ_FSG_PCI_INTC,
+                IRQ_FSG_PCI_INTB,
+                IRQ_FSG_PCI_INTA,
+        };
+
+        int irq = -1;
+        slot = slot - 11;
+
+        if (slot >= 1 && slot <= FSG_PCI_MAX_DEV &&
+            pin >= 1 && pin <= FSG_PCI_IRQ_LINES)
+                irq = pci_irq_table[(slot - 1)];
+        printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
+               __func__, slot, pin, irq);
+
+        return irq;
+}
+
+struct hw_pci fsg_pci __initdata = {
+        .nr_controllers = 1,
+        .preinit =        fsg_pci_preinit,
+        .swizzle =        pci_std_swizzle,
+        .setup =          ixp4xx_setup,
+        .scan =           ixp4xx_scan_bus,
+        .map_irq =        fsg_map_irq,
+};
+
+int __init fsg_pci_init(void)
+{
+        if (machine_is_fsg())
+                pci_common_init(&fsg_pci);
+        return 0;
+}
+
+subsys_initcall(fsg_pci_init);
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
new file mode 100644
index 000000000000..0db3a909ae61
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -0,0 +1,276 @@
+/*
+ * arch/arm/mach-ixp4xx/fsg-setup.c
+ *
+ * FSG board-setup
+ *
+ * Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
+ *
+ * based on ixdp425-setup.c:
+ *      Copyright (C) 2003-2004 MontaVista Software, Inc.
+ * based on nslu2-power.c
+ *      Copyright (C) 2005 Tower Technologies
+ *
+ * Author: Rod Whitby <rod@whitby.id.au>
+ * Maintainers: http://www.nslu2-linux.org/
+ *
+ */
+
+#include <linux/if_ether.h>
+#include <linux/irq.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/leds.h>
+#include <linux/reboot.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+static struct flash_platform_data fsg_flash_data = {
+        .map_name               = "cfi_probe",
+        .width                  = 2,
+};
+
+static struct resource fsg_flash_resource = {
+        .flags                  = IORESOURCE_MEM,
+};
+
+static struct platform_device fsg_flash = {
+        .name                   = "IXP4XX-Flash",
+        .id                     = 0,
+        .dev = {
+                .platform_data  = &fsg_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &fsg_flash_resource,
+};
+
+static struct i2c_gpio_platform_data fsg_i2c_gpio_data = {
+        .sda_pin                = FSG_SDA_PIN,
+        .scl_pin                = FSG_SCL_PIN,
+};
+
+static struct platform_device fsg_i2c_gpio = {
+        .name                   = "i2c-gpio",
+        .id                     = 0,
+        .dev = {
+                .platform_data  = &fsg_i2c_gpio_data,
+        },
+};
+
+static struct i2c_board_info __initdata fsg_i2c_board_info [] = {
+        {
+                I2C_BOARD_INFO("rtc-isl1208", 0x6f),
+        },
+};
+
+static struct resource fsg_uart_resources[] = {
+        {
+                .start          = IXP4XX_UART1_BASE_PHYS,
+                .end            = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = IXP4XX_UART2_BASE_PHYS,
+                .end            = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+                .flags          = IORESOURCE_MEM,
+        }
+};
+
+static struct plat_serial8250_port fsg_uart_data[] = {
+        {
+                .mapbase        = IXP4XX_UART1_BASE_PHYS,
+                .membase        = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+                .irq            = IRQ_IXP4XX_UART1,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = IXP4XX_UART_XTAL,
+        },
+        {
+                .mapbase        = IXP4XX_UART2_BASE_PHYS,
+                .membase        = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+                .irq            = IRQ_IXP4XX_UART2,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = IXP4XX_UART_XTAL,
+        },
+        { }
+};
+
+static struct platform_device fsg_uart = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev = {
+                .platform_data  = fsg_uart_data,
+        },
+        .num_resources          = ARRAY_SIZE(fsg_uart_resources),
+        .resource               = fsg_uart_resources,
+};
+
+static struct platform_device fsg_leds = {
+        .name           = "fsg-led",
+        .id             = -1,
+};
+
+/* Built-in 10/100 Ethernet MAC interfaces */
+static struct eth_plat_info fsg_plat_eth[] = {
+        {
+                .phy            = 5,
+                .rxq            = 3,
+                .txreadyq       = 20,
+        }, {
+                .phy            = 4,
+                .rxq            = 4,
+                .txreadyq       = 21,
+        }
+};
+
+static struct platform_device fsg_eth[] = {
+        {
+                .name                   = "ixp4xx_eth",
+                .id                     = IXP4XX_ETH_NPEB,
+                .dev = {
+                        .platform_data  = fsg_plat_eth,
+                },
+        }, {
+                .name                   = "ixp4xx_eth",
+                .id                     = IXP4XX_ETH_NPEC,
+                .dev = {
+                        .platform_data  = fsg_plat_eth + 1,
+                },
+        }
+};
+
+static struct platform_device *fsg_devices[] __initdata = {
+        &fsg_i2c_gpio,
+        &fsg_flash,
+        &fsg_leds,
+        &fsg_eth[0],
+        &fsg_eth[1],
+};
+
+static irqreturn_t fsg_power_handler(int irq, void *dev_id)
+{
+        /* Signal init to do the ctrlaltdel action, this will bypass init if
+         * it hasn't started and do a kernel_restart.
+         */
+        ctrl_alt_del();
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t fsg_reset_handler(int irq, void *dev_id)
+{
+        /* This is the paper-clip reset which does an emergency reboot. */
+        printk(KERN_INFO "Restarting system.\n");
+        machine_restart(NULL);
+
+        /* This should never be reached. */
+        return IRQ_HANDLED;
+}
+
+static void __init fsg_init(void)
+{
+        DECLARE_MAC_BUF(mac_buf);
+        uint8_t __iomem *f;
+        int i;
+
+        ixp4xx_sys_init();
+
+        fsg_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+        fsg_flash_resource.end =
+                IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+
+        *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
+        *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
+
+        /* Configure CS2 for operation, 8bit and writable */
+        *IXP4XX_EXP_CS2 = 0xbfff0002;
+
+        i2c_register_board_info(0, fsg_i2c_board_info,
+                                ARRAY_SIZE(fsg_i2c_board_info));
+
+        /* This is only useful on a modified machine, but it is valuable
+         * to have it first in order to see debug messages, and so that
+         * it does *not* get removed if platform_add_devices fails!
+         */
+        (void)platform_device_register(&fsg_uart);
+
+        platform_add_devices(fsg_devices, ARRAY_SIZE(fsg_devices));
+
+        if (request_irq(gpio_to_irq(FSG_RB_GPIO), &fsg_reset_handler,
+                        IRQF_DISABLED | IRQF_TRIGGER_LOW,
+                        "FSG reset button", NULL) < 0) {
+
+                printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
+                        gpio_to_irq(FSG_RB_GPIO));
+        }
+
+        if (request_irq(gpio_to_irq(FSG_SB_GPIO), &fsg_power_handler,
+                        IRQF_DISABLED | IRQF_TRIGGER_LOW,
+                        "FSG power button", NULL) < 0) {
+
+                printk(KERN_DEBUG "Power Button IRQ %d not available\n",
+                        gpio_to_irq(FSG_SB_GPIO));
+        }
+
+        /*
+         * Map in a portion of the flash and read the MAC addresses.
+         * Since it is stored in BE in the flash itself, we need to
+         * byteswap it if we're in LE mode.
+         */
+        f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x400000);
+        if (f) {
+#ifdef __ARMEB__
+                for (i = 0; i < 6; i++) {
+                        fsg_plat_eth[0].hwaddr[i] = readb(f + 0x3C0422 + i);
+                        fsg_plat_eth[1].hwaddr[i] = readb(f + 0x3C043B + i);
+                }
+#else
+
+                /*
+                  Endian-swapped reads from unaligned addresses are
+                  required to extract the two MACs from the big-endian
+                  Redboot config area in flash.
+                */
+
+                fsg_plat_eth[0].hwaddr[0] = readb(f + 0x3C0421);
+                fsg_plat_eth[0].hwaddr[1] = readb(f + 0x3C0420);
+                fsg_plat_eth[0].hwaddr[2] = readb(f + 0x3C0427);
+                fsg_plat_eth[0].hwaddr[3] = readb(f + 0x3C0426);
+                fsg_plat_eth[0].hwaddr[4] = readb(f + 0x3C0425);
+                fsg_plat_eth[0].hwaddr[5] = readb(f + 0x3C0424);
+
+                fsg_plat_eth[1].hwaddr[0] = readb(f + 0x3C0439);
+                fsg_plat_eth[1].hwaddr[1] = readb(f + 0x3C043F);
+                fsg_plat_eth[1].hwaddr[2] = readb(f + 0x3C043E);
+                fsg_plat_eth[1].hwaddr[3] = readb(f + 0x3C043D);
+                fsg_plat_eth[1].hwaddr[4] = readb(f + 0x3C043C);
+                fsg_plat_eth[1].hwaddr[5] = readb(f + 0x3C0443);
+#endif
+                iounmap(f);
+        }
+        printk(KERN_INFO "FSG: Using MAC address %s for port 0\n",
+               print_mac(mac_buf, fsg_plat_eth[0].hwaddr));
+        printk(KERN_INFO "FSG: Using MAC address %s for port 1\n",
+               print_mac(mac_buf, fsg_plat_eth[1].hwaddr));
+
+}
+
+MACHINE_START(FSG, "Freecom FSG-3")
+        /* Maintainer: www.nslu2-linux.org */
+        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
+        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
+        .map_io         = ixp4xx_map_io,
+        .init_irq       = ixp4xx_init_irq,
+        .timer          = &ixp4xx_timer,
+        .boot_params    = 0x0100,
+        .init_machine   = fsg_init,
+MACHINE_END
+
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
new file mode 100644
index 000000000000..3600cd9f0519
--- /dev/null
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -0,0 +1,25 @@
+if ARCH_KIRKWOOD
+
+menu "Marvell Kirkwood Implementations"
+
+config MACH_DB88F6281_BP
+        bool "Marvell DB-88F6281-BP Development Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell DB-88F6281-BP Development Board.
+
+config MACH_RD88F6192_NAS
+        bool "Marvell RD-88F6192-NAS Reference Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell RD-88F6192-NAS Reference Board.
+
+config MACH_RD88F6281
+        bool "Marvell RD-88F6281 Reference Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell RD-88F6281 Reference Board.
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
new file mode 100644
index 000000000000..e14bf40bfb07
--- /dev/null
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -0,0 +1,5 @@
+obj-y                           += common.o addr-map.o irq.o pcie.o
+
+obj-$(CONFIG_MACH_DB88F6281_BP)         += db88f6281-bp-setup.o
+obj-$(CONFIG_MACH_RD88F6192_NAS)        += rd88f6192-nas-setup.o
+obj-$(CONFIG_MACH_RD88F6192_NAS)        += rd88f6281-setup.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
new file mode 100644
index 000000000000..a39f0f3c4730
--- /dev/null
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -0,0 +1,139 @@
+/*
+ * arch/arm/mach-kirkwood/addr-map.c
+ *
+ * Address map functions for Marvell Kirkwood SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <asm/hardware.h>
+#include "common.h"
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define TARGET_DDR              0
+#define TARGET_DEV_BUS          1
+#define TARGET_PCIE             4
+#define ATTR_DEV_SPI_ROM        0x1e
+#define ATTR_DEV_BOOT           0x1d
+#define ATTR_DEV_NAND           0x2f
+#define ATTR_DEV_CS3            0x37
+#define ATTR_DEV_CS2            0x3b
+#define ATTR_DEV_CS1            0x3d
+#define ATTR_DEV_CS0            0x3e
+#define ATTR_PCIE_IO            0xe0
+#define ATTR_PCIE_MEM           0xe8
+
+/*
+ * Helpers to get DDR bank info
+ */
+#define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
+#define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
+
+/*
+ * CPU Address Decode Windows registers
+ */
+#define WIN_OFF(n)              (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
+#define WIN_CTRL_OFF            0x0000
+#define WIN_BASE_OFF            0x0004
+#define WIN_REMAP_LO_OFF        0x0008
+#define WIN_REMAP_HI_OFF        0x000c
+
+
+struct mbus_dram_target_info kirkwood_mbus_dram_info;
+
+static int __init cpu_win_can_remap(int win)
+{
+        if (win < 4)
+                return 1;
+
+        return 0;
+}
+
+static void __init setup_cpu_win(int win, u32 base, u32 size,
+                                 u8 target, u8 attr, int remap)
+{
+        void __iomem *addr = (void __iomem *)WIN_OFF(win);
+        u32 ctrl;
+
+        base &= 0xffff0000;
+        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
+
+        writel(base, addr + WIN_BASE_OFF);
+        writel(ctrl, addr + WIN_CTRL_OFF);
+        if (cpu_win_can_remap(win)) {
+                if (remap < 0)
+                        remap = base;
+
+                writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
+                writel(0, addr + WIN_REMAP_HI_OFF);
+        }
+}
+
+void __init kirkwood_setup_cpu_mbus(void)
+{
+        void __iomem *addr;
+        int i;
+        int cs;
+
+        /*
+         * First, disable and clear windows.
+         */
+        for (i = 0; i < 8; i++) {
+                addr = (void __iomem *)WIN_OFF(i);
+
+                writel(0, addr + WIN_BASE_OFF);
+                writel(0, addr + WIN_CTRL_OFF);
+                if (cpu_win_can_remap(i)) {
+                        writel(0, addr + WIN_REMAP_LO_OFF);
+                        writel(0, addr + WIN_REMAP_HI_OFF);
+                }
+        }
+
+        /*
+         * Setup windows for PCIe IO+MEM space.
+         */
+        setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
+                      TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
+        setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
+                      TARGET_PCIE, ATTR_PCIE_MEM, -1);
+
+        /*
+         * Setup window for NAND controller.
+         */
+        setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
+                      TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
+
+        /*
+         * Setup MBUS dram target info.
+         */
+        kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+
+        addr = (void __iomem *)DDR_WINDOW_CPU_BASE;
+
+        for (i = 0, cs = 0; i < 4; i++) {
+                u32 base = readl(addr + DDR_BASE_CS_OFF(i));
+                u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
+
+                /*
+                 * Chip select enabled?
+                 */
+                if (size & 1) {
+                        struct mbus_dram_window *w;
+
+                        w = &kirkwood_mbus_dram_info.cs[cs++];
+                        w->cs_index = i;
+                        w->mbus_attr = 0xf & ~(1 << i);
+                        w->base = base & 0xffff0000;
+                        w->size = (size | 0x0000ffff) + 1;
+                }
+        }
+        kirkwood_mbus_dram_info.num_cs = cs;
+}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
new file mode 100644
index 000000000000..5938a3b33cdc
--- /dev/null
+++ b/arch/arm/mach-kirkwood/common.c
@@ -0,0 +1,331 @@
+/*
+ * arch/arm/mach-kirkwood/common.c
+ *
+ * Core functions for Marvell Kirkwood SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/mbus.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ata_platform.h>
+#include <asm/page.h>
+#include <asm/timex.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/plat-orion/cache-feroceon-l2.h>
+#include <asm/plat-orion/ehci-orion.h>
+#include <asm/plat-orion/orion_nand.h>
+#include <asm/plat-orion/time.h>
+#include "common.h"
+
+/*****************************************************************************
+ * I/O Address Mapping
+ ****************************************************************************/
+static struct map_desc kirkwood_io_desc[] __initdata = {
+        {
+                .virtual        = KIRKWOOD_PCIE_IO_VIRT_BASE,
+                .pfn            = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
+                .length         = KIRKWOOD_PCIE_IO_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = KIRKWOOD_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
+                .length         = KIRKWOOD_REGS_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+void __init kirkwood_map_io(void)
+{
+        iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
+}
+
+
+/*****************************************************************************
+ * EHCI
+ ****************************************************************************/
+static struct orion_ehci_data kirkwood_ehci_data = {
+        .dram           = &kirkwood_mbus_dram_info,
+};
+
+static u64 ehci_dmamask = 0xffffffffUL;
+
+
+/*****************************************************************************
+ * EHCI0
+ ****************************************************************************/
+static struct resource kirkwood_ehci_resources[] = {
+        {
+                .start  = USB_PHYS_BASE,
+                .end    = USB_PHYS_BASE + 0x0fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_KIRKWOOD_USB,
+                .end    = IRQ_KIRKWOOD_USB,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device kirkwood_ehci = {
+        .name           = "orion-ehci",
+        .id             = 0,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &kirkwood_ehci_data,
+        },
+        .resource       = kirkwood_ehci_resources,
+        .num_resources  = ARRAY_SIZE(kirkwood_ehci_resources),
+};
+
+void __init kirkwood_ehci_init(void)
+{
+        platform_device_register(&kirkwood_ehci);
+}
+
+
+/*****************************************************************************
+ * GE00
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
+        .t_clk          = KIRKWOOD_TCLK,
+        .dram           = &kirkwood_mbus_dram_info,
+};
+
+static struct resource kirkwood_ge00_shared_resources[] = {
+        {
+                .name   = "ge00 base",
+                .start  = GE00_PHYS_BASE + 0x2000,
+                .end    = GE00_PHYS_BASE + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device kirkwood_ge00_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &kirkwood_ge00_shared_data,
+        },
+        .num_resources  = 1,
+        .resource       = kirkwood_ge00_shared_resources,
+};
+
+static struct resource kirkwood_ge00_resources[] = {
+        {
+                .name   = "ge00 irq",
+                .start  = IRQ_KIRKWOOD_GE00_SUM,
+                .end    = IRQ_KIRKWOOD_GE00_SUM,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device kirkwood_ge00 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = kirkwood_ge00_resources,
+};
+
+void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
+{
+        eth_data->shared = &kirkwood_ge00_shared;
+        kirkwood_ge00.dev.platform_data = eth_data;
+
+        platform_device_register(&kirkwood_ge00_shared);
+        platform_device_register(&kirkwood_ge00);
+}
+
+
+/*****************************************************************************
+ * SoC RTC
+ ****************************************************************************/
+static struct resource kirkwood_rtc_resource = {
+        .start  = RTC_PHYS_BASE,
+        .end    = RTC_PHYS_BASE + SZ_16 - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+void __init kirkwood_rtc_init(void)
+{
+        platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1);
+}
+
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct resource kirkwood_sata_resources[] = {
+        {
+                .name   = "sata base",
+                .start  = SATA_PHYS_BASE,
+                .end    = SATA_PHYS_BASE + 0x5000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "sata irq",
+                .start  = IRQ_KIRKWOOD_SATA,
+                .end    = IRQ_KIRKWOOD_SATA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device kirkwood_sata = {
+        .name           = "sata_mv",
+        .id             = 0,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(kirkwood_sata_resources),
+        .resource       = kirkwood_sata_resources,
+};
+
+void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
+{
+        sata_data->dram = &kirkwood_mbus_dram_info;
+        kirkwood_sata.dev.platform_data = sata_data;
+        platform_device_register(&kirkwood_sata);
+}
+
+
+/*****************************************************************************
+ * UART0
+ ****************************************************************************/
+static struct plat_serial8250_port kirkwood_uart0_data[] = {
+        {
+                .mapbase        = UART0_PHYS_BASE,
+                .membase        = (char *)UART0_VIRT_BASE,
+                .irq            = IRQ_KIRKWOOD_UART_0,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = KIRKWOOD_TCLK,
+        }, {
+        },
+};
+
+static struct resource kirkwood_uart0_resources[] = {
+        {
+                .start          = UART0_PHYS_BASE,
+                .end            = UART0_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_KIRKWOOD_UART_0,
+                .end            = IRQ_KIRKWOOD_UART_0,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device kirkwood_uart0 = {
+        .name                   = "serial8250",
+        .id                     = 0,
+        .dev                    = {
+                .platform_data  = kirkwood_uart0_data,
+        },
+        .resource               = kirkwood_uart0_resources,
+        .num_resources          = ARRAY_SIZE(kirkwood_uart0_resources),
+};
+
+void __init kirkwood_uart0_init(void)
+{
+        platform_device_register(&kirkwood_uart0);
+}
+
+
+/*****************************************************************************
+ * UART1
+ ****************************************************************************/
+static struct plat_serial8250_port kirkwood_uart1_data[] = {
+        {
+                .mapbase        = UART1_PHYS_BASE,
+                .membase        = (char *)UART1_VIRT_BASE,
+                .irq            = IRQ_KIRKWOOD_UART_1,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = KIRKWOOD_TCLK,
+        }, {
+        },
+};
+
+static struct resource kirkwood_uart1_resources[] = {
+        {
+                .start          = UART1_PHYS_BASE,
+                .end            = UART1_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_KIRKWOOD_UART_1,
+                .end            = IRQ_KIRKWOOD_UART_1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device kirkwood_uart1 = {
+        .name                   = "serial8250",
+        .id                     = 1,
+        .dev                    = {
+                .platform_data  = kirkwood_uart1_data,
+        },
+        .resource               = kirkwood_uart1_resources,
+        .num_resources          = ARRAY_SIZE(kirkwood_uart1_resources),
+};
+
+void __init kirkwood_uart1_init(void)
+{
+        platform_device_register(&kirkwood_uart1);
+}
+
+
+/*****************************************************************************
+ * Time handling
+ ****************************************************************************/
+static void kirkwood_timer_init(void)
+{
+        orion_time_init(IRQ_KIRKWOOD_BRIDGE, KIRKWOOD_TCLK);
+}
+
+struct sys_timer kirkwood_timer = {
+        .init = kirkwood_timer_init,
+};
+
+
+/*****************************************************************************
+ * General
+ ****************************************************************************/
+static char * __init kirkwood_id(void)
+{
+        switch (readl(DEVICE_ID) & 0x3) {
+        case 0:
+                return "88F6180";
+        case 1:
+                return "88F6192";
+        case 2:
+                return "88F6281";
+        }
+
+        return "unknown 88F6000 variant";
+}
+
+static int __init is_l2_writethrough(void)
+{
+        return !!(readl(L2_CONFIG_REG) & L2_WRITETHROUGH);
+}
+
+void __init kirkwood_init(void)
+{
+        printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
+                kirkwood_id(), KIRKWOOD_TCLK);
+
+        kirkwood_setup_cpu_mbus();
+
+#ifdef CONFIG_CACHE_FEROCEON_L2
+        feroceon_l2_init(is_l2_writethrough());
+#endif
+}
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
new file mode 100644
index 000000000000..5dee2f6b40a5
--- /dev/null
+++ b/arch/arm/mach-kirkwood/common.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-kirkwood/common.h
+ *
+ * Core functions for Marvell Kirkwood SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_KIRKWOOD_COMMON_H
+#define __ARCH_KIRKWOOD_COMMON_H
+
+struct mv643xx_eth_platform_data;
+struct mv_sata_platform_data;
+
+/*
+ * Basic Kirkwood init functions used early by machine-setup.
+ */
+void kirkwood_map_io(void);
+void kirkwood_init(void);
+void kirkwood_init_irq(void);
+
+extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
+void kirkwood_setup_cpu_mbus(void);
+void kirkwood_setup_pcie_io_win(int window, u32 base, u32 size,
+                                int maj, int min);
+void kirkwood_setup_pcie_mem_win(int window, u32 base, u32 size,
+                                 int maj, int min);
+
+void kirkwood_ehci_init(void);
+void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
+void kirkwood_pcie_init(void);
+void kirkwood_rtc_init(void);
+void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
+void kirkwood_uart0_init(void);
+void kirkwood_uart1_init(void);
+
+extern struct sys_timer kirkwood_timer;
+
+
+#endif
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
new file mode 100644
index 000000000000..d5c482c628e3
--- /dev/null
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -0,0 +1,68 @@
+/*
+ * arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+ *
+ * Marvell DB-88F6281-BP Development Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/timer.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/kirkwood.h>
+#include "common.h"
+
+static struct mv643xx_eth_platform_data db88f6281_ge00_data = {
+        .phy_addr       = 8,
+};
+
+static struct mv_sata_platform_data db88f6281_sata_data = {
+        .n_ports        = 2,
+};
+
+static void __init db88f6281_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&db88f6281_ge00_data);
+        kirkwood_rtc_init();
+        kirkwood_sata_init(&db88f6281_sata_data);
+        kirkwood_uart0_init();
+        kirkwood_uart1_init();
+}
+
+static int __init db88f6281_pci_init(void)
+{
+        if (machine_is_db88f6281_bp())
+                kirkwood_pcie_init();
+
+        return 0;
+}
+subsys_initcall(db88f6281_pci_init);
+
+MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
+        /* Maintainer: Saeed Bishara <saeed@marvell.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = db88f6281_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
new file mode 100644
index 000000000000..302bb2cf6669
--- /dev/null
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-kirkwood/irq.c
+ *
+ * Kirkwood IRQ handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <asm/plat-orion/irq.h>
+#include "common.h"
+
+void __init kirkwood_init_irq(void)
+{
+        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
+        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+}
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
new file mode 100644
index 000000000000..8282d0ff84bf
--- /dev/null
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -0,0 +1,180 @@
+/*
+ * arch/arm/mach-kirkwood/pcie.c
+ *
+ * PCIe functions for Marvell Kirkwood SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/mbus.h>
+#include <asm/mach/pci.h>
+#include <asm/plat-orion/pcie.h>
+#include "common.h"
+
+
+#define PCIE_BASE       ((void __iomem *)PCIE_VIRT_BASE)
+
+static int pcie_valid_config(int bus, int dev)
+{
+        /*
+         * Don't go out when trying to access --
+         * 1. nonexisting device on local bus
+         * 2. where there's no device connected (no link)
+         */
+        if (bus == 0 && dev == 0)
+                return 1;
+
+        if (!orion_pcie_link_up(PCIE_BASE))
+                return 0;
+
+        if (bus == 0 && dev != 1)
+                return 0;
+
+        return 1;
+}
+
+
+/*
+ * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
+ * and then reading the PCIE_CONF_DATA register. Need to make sure these
+ * transactions are atomic.
+ */
+static DEFINE_SPINLOCK(kirkwood_pcie_lock);
+
+static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+                        int size, u32 *val)
+{
+        unsigned long flags;
+        int ret;
+
+        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        spin_lock_irqsave(&kirkwood_pcie_lock, flags);
+        ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+
+        return ret;
+}
+
+static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+                        int where, int size, u32 val)
+{
+        unsigned long flags;
+        int ret;
+
+        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        spin_lock_irqsave(&kirkwood_pcie_lock, flags);
+        ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+
+        return ret;
+}
+
+static struct pci_ops pcie_ops = {
+        .read = pcie_rd_conf,
+        .write = pcie_wr_conf,
+};
+
+
+static int kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+        struct resource *res;
+
+        /*
+         * Generic PCIe unit setup.
+         */
+        orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
+
+        /*
+         * Request resources.
+         */
+        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+        if (!res)
+                panic("pcie_setup unable to alloc resources");
+
+        /*
+         * IORESOURCE_IO
+         */
+        res[0].name = "PCIe I/O Space";
+        res[0].flags = IORESOURCE_IO;
+        res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
+        res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
+        if (request_resource(&ioport_resource, &res[0]))
+                panic("Request PCIe IO resource failed\n");
+        sys->resource[0] = &res[0];
+
+        /*
+         * IORESOURCE_MEM
+         */
+        res[1].name = "PCIe Memory Space";
+        res[1].flags = IORESOURCE_MEM;
+        res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+        res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+        if (request_resource(&iomem_resource, &res[1]))
+                panic("Request PCIe Memory resource failed\n");
+        sys->resource[1] = &res[1];
+
+        sys->resource[2] = NULL;
+        sys->io_offset = 0;
+
+        return 1;
+}
+
+static void __devinit rc_pci_fixup(struct pci_dev *dev)
+{
+        /*
+         * Prevent enumeration of root complex.
+         */
+        if (dev->bus->parent == NULL && dev->devfn == 0) {
+                int i;
+
+                for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+                        dev->resource[i].start = 0;
+                        dev->resource[i].end   = 0;
+                        dev->resource[i].flags = 0;
+                }
+        }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
+
+static struct pci_bus __init *
+kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        struct pci_bus *bus;
+
+        if (nr == 0) {
+                bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+        } else {
+                bus = NULL;
+                BUG();
+        }
+
+        return bus;
+}
+
+static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        return IRQ_KIRKWOOD_PCIE;
+}
+
+static struct hw_pci kirkwood_pci __initdata = {
+        .nr_controllers = 1,
+        .swizzle        = pci_std_swizzle,
+        .setup          = kirkwood_pcie_setup,
+        .scan           = kirkwood_pcie_scan_bus,
+        .map_irq        = kirkwood_pcie_map_irq,
+};
+
+void __init kirkwood_pcie_init(void)
+{
+        pci_common_init(&kirkwood_pci);
+}
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
new file mode 100644
index 000000000000..6cf642c504d3
--- /dev/null
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -0,0 +1,69 @@
+/*
+ * arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+ *
+ * Marvell RD-88F6192-NAS Reference Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/timer.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/kirkwood.h>
+#include "common.h"
+
+#define RD88F6192_GPIO_USB_VBUS         10
+
+static struct mv643xx_eth_platform_data rd88f6192_ge00_data = {
+        .phy_addr       = 8,
+};
+
+static struct mv_sata_platform_data rd88f6192_sata_data = {
+        .n_ports        = 2,
+};
+
+static void __init rd88f6192_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&rd88f6192_ge00_data);
+        kirkwood_rtc_init();
+        kirkwood_sata_init(&rd88f6192_sata_data);
+        kirkwood_uart0_init();
+}
+
+static int __init rd88f6192_pci_init(void)
+{
+        if (machine_is_rd88f6192_nas())
+                kirkwood_pcie_init();
+
+        return 0;
+}
+subsys_initcall(rd88f6192_pci_init);
+
+MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
+        /* Maintainer: Saeed Bishara <saeed@marvell.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = rd88f6192_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
new file mode 100644
index 000000000000..e1f8de2c74a2
--- /dev/null
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -0,0 +1,113 @@
+/*
+ * arch/arm/mach-kirkwood/rd88f6281-setup.c
+ *
+ * Marvell RD-88F6281 Reference Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/timer.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/plat-orion/orion_nand.h>
+#include "common.h"
+
+static struct mtd_partition rd88f6281_nand_parts[] = {
+        {
+                .name = "u-boot",
+                .offset = 0,
+                .size = SZ_1M
+        }, {
+                .name = "uImage",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = SZ_2M
+        }, {
+                .name = "root",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = MTDPART_SIZ_FULL
+        },
+};
+
+static struct resource rd88f6281_nand_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = KIRKWOOD_NAND_MEM_PHYS_BASE,
+        .end            = KIRKWOOD_NAND_MEM_PHYS_BASE +
+                          KIRKWOOD_NAND_MEM_SIZE - 1,
+};
+
+static struct orion_nand_data rd88f6281_nand_data = {
+        .parts          = rd88f6281_nand_parts,
+        .nr_parts       = ARRAY_SIZE(rd88f6281_nand_parts),
+        .cle            = 0,
+        .ale            = 1,
+        .width          = 8,
+        .chip_delay     = 25,
+};
+
+static struct platform_device rd88f6281_nand_flash = {
+        .name           = "orion_nand",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &rd88f6281_nand_data,
+        },
+        .resource       = &rd88f6281_nand_resource,
+        .num_resources  = 1,
+};
+
+static struct mv643xx_eth_platform_data rd88f6281_ge00_data = {
+        .phy_addr       = -1,
+};
+
+static struct mv_sata_platform_data rd88f6281_sata_data = {
+        .n_ports        = 2,
+};
+
+static void __init rd88f6281_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&rd88f6281_ge00_data);
+        kirkwood_rtc_init();
+        kirkwood_sata_init(&rd88f6281_sata_data);
+        kirkwood_uart0_init();
+        kirkwood_uart1_init();
+
+        platform_device_register(&rd88f6281_nand_flash);
+}
+
+static int __init rd88f6281_pci_init(void)
+{
+        if (machine_is_rd88f6281())
+                kirkwood_pcie_init();
+
+        return 0;
+}
+subsys_initcall(rd88f6281_pci_init);
+
+MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
+        /* Maintainer: Saeed Bishara <saeed@marvell.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = rd88f6281_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-loki/Kconfig b/arch/arm/mach-loki/Kconfig
new file mode 100644
index 000000000000..0045bdd761ca
--- /dev/null
+++ b/arch/arm/mach-loki/Kconfig
@@ -0,0 +1,13 @@
+if ARCH_LOKI
+
+menu "Marvell Loki (88RC8480) Implementations"
+
+config MACH_LB88RC8480
+        bool "Marvell LB88RC8480 Development Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell LB88RC8480 Development Board.
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-loki/Makefile b/arch/arm/mach-loki/Makefile
new file mode 100644
index 000000000000..d43233ee590f
--- /dev/null
+++ b/arch/arm/mach-loki/Makefile
@@ -0,0 +1,3 @@
+obj-y                           += common.o addr-map.o irq.o
+
+obj-$(CONFIG_MACH_LB88RC8480)   += lb88rc8480-setup.o
diff --git a/arch/arm/mach-loki/Makefile.boot b/arch/arm/mach-loki/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-loki/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-loki/addr-map.c b/arch/arm/mach-loki/addr-map.c
new file mode 100644
index 000000000000..ba25e56ade58
--- /dev/null
+++ b/arch/arm/mach-loki/addr-map.c
@@ -0,0 +1,121 @@
+/*
+ * arch/arm/mach-loki/addr-map.c
+ *
+ * Address map functions for Marvell Loki (88RC8480) SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include "common.h"
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define TARGET_DDR              0
+#define TARGET_DEV_BUS          1
+#define TARGET_PCIE0            3
+#define TARGET_PCIE1            4
+#define ATTR_DEV_BOOT           0x0f
+#define ATTR_DEV_CS2            0x1b
+#define ATTR_DEV_CS1            0x1d
+#define ATTR_DEV_CS0            0x1e
+#define ATTR_PCIE_IO            0x51
+#define ATTR_PCIE_MEM           0x59
+
+/*
+ * Helpers to get DDR bank info
+ */
+#define DDR_SIZE_CS(n)          DDR_REG(0x1500 + ((n) << 3))
+#define DDR_BASE_CS(n)          DDR_REG(0x1504 + ((n) << 3))
+
+/*
+ * CPU Address Decode Windows registers
+ */
+#define CPU_WIN_CTRL(n)         BRIDGE_REG(0x000 | ((n) << 4))
+#define CPU_WIN_BASE(n)         BRIDGE_REG(0x004 | ((n) << 4))
+#define CPU_WIN_REMAP_LO(n)     BRIDGE_REG(0x008 | ((n) << 4))
+#define CPU_WIN_REMAP_HI(n)     BRIDGE_REG(0x00c | ((n) << 4))
+
+
+struct mbus_dram_target_info loki_mbus_dram_info;
+
+static void __init setup_cpu_win(int win, u32 base, u32 size,
+                                 u8 target, u8 attr, int remap)
+{
+        u32 ctrl;
+
+        base &= 0xffff0000;
+        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (1 << 5) | target;
+
+        writel(base, CPU_WIN_BASE(win));
+        writel(ctrl, CPU_WIN_CTRL(win));
+        if (win < 2) {
+                if (remap < 0)
+                        remap = base;
+
+                writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
+                writel(0, CPU_WIN_REMAP_HI(win));
+        }
+}
+
+void __init loki_setup_cpu_mbus(void)
+{
+        int i;
+        int cs;
+
+        /*
+         * First, disable and clear windows.
+         */
+        for (i = 0; i < 8; i++) {
+                writel(0, CPU_WIN_BASE(i));
+                writel(0, CPU_WIN_CTRL(i));
+                if (i < 2) {
+                        writel(0, CPU_WIN_REMAP_LO(i));
+                        writel(0, CPU_WIN_REMAP_HI(i));
+                }
+        }
+
+        /*
+         * Setup windows for PCIe IO+MEM space.
+         */
+        setup_cpu_win(2, LOKI_PCIE0_MEM_PHYS_BASE, LOKI_PCIE0_MEM_SIZE,
+                      TARGET_PCIE0, ATTR_PCIE_MEM, -1);
+        setup_cpu_win(3, LOKI_PCIE1_MEM_PHYS_BASE, LOKI_PCIE1_MEM_SIZE,
+                      TARGET_PCIE1, ATTR_PCIE_MEM, -1);
+
+        /*
+         * Setup MBUS dram target info.
+         */
+        loki_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+
+        for (i = 0, cs = 0; i < 4; i++) {
+                u32 base = readl(DDR_BASE_CS(i));
+                u32 size = readl(DDR_SIZE_CS(i));
+
+                /*
+                 * Chip select enabled?
+                 */
+                if (size & 1) {
+                        struct mbus_dram_window *w;
+
+                        w = &loki_mbus_dram_info.cs[cs++];
+                        w->cs_index = i;
+                        w->mbus_attr = 0xf & ~(1 << i);
+                        w->base = base & 0xffff0000;
+                        w->size = (size | 0x0000ffff) + 1;
+                }
+        }
+        loki_mbus_dram_info.num_cs = cs;
+}
+
+void __init loki_setup_dev_boot_win(u32 base, u32 size)
+{
+        setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
+}
diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c
new file mode 100644
index 000000000000..410f50399dd3
--- /dev/null
+++ b/arch/arm/mach-loki/common.c
@@ -0,0 +1,305 @@
+/*
+ * arch/arm/mach-loki/common.c
+ *
+ * Core functions for Marvell Loki (88RC8480) SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/mbus.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/page.h>
+#include <asm/timex.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/arch/loki.h>
+#include <asm/plat-orion/orion_nand.h>
+#include <asm/plat-orion/time.h>
+#include "common.h"
+
+/*****************************************************************************
+ * I/O Address Mapping
+ ****************************************************************************/
+static struct map_desc loki_io_desc[] __initdata = {
+        {
+                .virtual        = LOKI_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(LOKI_REGS_PHYS_BASE),
+                .length         = LOKI_REGS_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+void __init loki_map_io(void)
+{
+        iotable_init(loki_io_desc, ARRAY_SIZE(loki_io_desc));
+}
+
+
+/*****************************************************************************
+ * GE0
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = {
+        .t_clk          = LOKI_TCLK,
+        .dram           = &loki_mbus_dram_info,
+};
+
+static struct resource loki_ge0_shared_resources[] = {
+        {
+                .name   = "ge0 base",
+                .start  = GE0_PHYS_BASE + 0x2000,
+                .end    = GE0_PHYS_BASE + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device loki_ge0_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &loki_ge0_shared_data,
+        },
+        .num_resources  = 1,
+        .resource       = loki_ge0_shared_resources,
+};
+
+static struct resource loki_ge0_resources[] = {
+        {
+                .name   = "ge0 irq",
+                .start  = IRQ_LOKI_GBE_A_INT,
+                .end    = IRQ_LOKI_GBE_A_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device loki_ge0 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = loki_ge0_resources,
+};
+
+void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
+{
+        eth_data->shared = &loki_ge0_shared;
+        loki_ge0.dev.platform_data = eth_data;
+
+        writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
+        platform_device_register(&loki_ge0_shared);
+        platform_device_register(&loki_ge0);
+}
+
+
+/*****************************************************************************
+ * GE1
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = {
+        .t_clk          = LOKI_TCLK,
+        .dram           = &loki_mbus_dram_info,
+};
+
+static struct resource loki_ge1_shared_resources[] = {
+        {
+                .name   = "ge1 base",
+                .start  = GE1_PHYS_BASE + 0x2000,
+                .end    = GE1_PHYS_BASE + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device loki_ge1_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &loki_ge1_shared_data,
+        },
+        .num_resources  = 1,
+        .resource       = loki_ge1_shared_resources,
+};
+
+static struct resource loki_ge1_resources[] = {
+        {
+                .name   = "ge1 irq",
+                .start  = IRQ_LOKI_GBE_B_INT,
+                .end    = IRQ_LOKI_GBE_B_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device loki_ge1 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 1,
+        .num_resources  = 1,
+        .resource       = loki_ge1_resources,
+};
+
+void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
+{
+        eth_data->shared = &loki_ge1_shared;
+        loki_ge1.dev.platform_data = eth_data;
+
+        writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
+        platform_device_register(&loki_ge1_shared);
+        platform_device_register(&loki_ge1);
+}
+
+
+/*****************************************************************************
+ * SAS/SATA
+ ****************************************************************************/
+static struct resource loki_sas_resources[] = {
+        {
+                .name   = "mvsas0 mem",
+                .start  = SAS0_PHYS_BASE,
+                .end    = SAS0_PHYS_BASE + 0x01ff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "mvsas0 irq",
+                .start  = IRQ_LOKI_SAS_A,
+                .end    = IRQ_LOKI_SAS_A,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .name   = "mvsas1 mem",
+                .start  = SAS1_PHYS_BASE,
+                .end    = SAS1_PHYS_BASE + 0x01ff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "mvsas1 irq",
+                .start  = IRQ_LOKI_SAS_B,
+                .end    = IRQ_LOKI_SAS_B,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device loki_sas = {
+        .name           = "mvsas",
+        .id             = 0,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(loki_sas_resources),
+        .resource       = loki_sas_resources,
+};
+
+void __init loki_sas_init(void)
+{
+        writel(0x8300f707, DDR_REG(0x1424));
+        platform_device_register(&loki_sas);
+}
+
+
+/*****************************************************************************
+ * UART0
+ ****************************************************************************/
+static struct plat_serial8250_port loki_uart0_data[] = {
+        {
+                .mapbase        = UART0_PHYS_BASE,
+                .membase        = (char *)UART0_VIRT_BASE,
+                .irq            = IRQ_LOKI_UART0,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = LOKI_TCLK,
+        }, {
+        },
+};
+
+static struct resource loki_uart0_resources[] = {
+        {
+                .start          = UART0_PHYS_BASE,
+                .end            = UART0_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_LOKI_UART0,
+                .end            = IRQ_LOKI_UART0,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device loki_uart0 = {
+        .name                   = "serial8250",
+        .id                     = 0,
+        .dev                    = {
+                .platform_data  = loki_uart0_data,
+        },
+        .resource               = loki_uart0_resources,
+        .num_resources          = ARRAY_SIZE(loki_uart0_resources),
+};
+
+void __init loki_uart0_init(void)
+{
+        platform_device_register(&loki_uart0);
+}
+
+
+/*****************************************************************************
+ * UART1
+ ****************************************************************************/
+static struct plat_serial8250_port loki_uart1_data[] = {
+        {
+                .mapbase        = UART1_PHYS_BASE,
+                .membase        = (char *)UART1_VIRT_BASE,
+                .irq            = IRQ_LOKI_UART1,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = LOKI_TCLK,
+        }, {
+        },
+};
+
+static struct resource loki_uart1_resources[] = {
+        {
+                .start          = UART1_PHYS_BASE,
+                .end            = UART1_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_LOKI_UART1,
+                .end            = IRQ_LOKI_UART1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device loki_uart1 = {
+        .name                   = "serial8250",
+        .id                     = 1,
+        .dev                    = {
+                .platform_data  = loki_uart1_data,
+        },
+        .resource               = loki_uart1_resources,
+        .num_resources          = ARRAY_SIZE(loki_uart1_resources),
+};
+
+void __init loki_uart1_init(void)
+{
+        platform_device_register(&loki_uart1);
+}
+
+
+/*****************************************************************************
+ * Time handling
+ ****************************************************************************/
+static void loki_timer_init(void)
+{
+        orion_time_init(IRQ_LOKI_BRIDGE, LOKI_TCLK);
+}
+
+struct sys_timer loki_timer = {
+        .init = loki_timer_init,
+};
+
+
+/*****************************************************************************
+ * General
+ ****************************************************************************/
+void __init loki_init(void)
+{
+        printk(KERN_INFO "Loki ID: 88RC8480. TCLK=%d.\n", LOKI_TCLK);
+
+        loki_setup_cpu_mbus();
+}
diff --git a/arch/arm/mach-loki/common.h b/arch/arm/mach-loki/common.h
new file mode 100644
index 000000000000..26054fd0f05e
--- /dev/null
+++ b/arch/arm/mach-loki/common.h
@@ -0,0 +1,36 @@
+/*
+ * arch/arm/mach-loki/common.h
+ *
+ * Core functions for Marvell Loki (88RC8480) SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_LOKI_COMMON_H
+#define __ARCH_LOKI_COMMON_H
+
+struct mv643xx_eth_platform_data;
+
+/*
+ * Basic Loki init functions used early by machine-setup.
+ */
+void loki_map_io(void);
+void loki_init(void);
+void loki_init_irq(void);
+
+extern struct mbus_dram_target_info loki_mbus_dram_info;
+void loki_setup_cpu_mbus(void);
+void loki_setup_dev_boot_win(u32 base, u32 size);
+
+void loki_ge0_init(struct mv643xx_eth_platform_data *eth_data);
+void loki_ge1_init(struct mv643xx_eth_platform_data *eth_data);
+void loki_sas_init(void);
+void loki_uart0_init(void);
+void loki_uart1_init(void);
+
+extern struct sys_timer loki_timer;
+
+
+#endif
diff --git a/arch/arm/mach-loki/irq.c b/arch/arm/mach-loki/irq.c
new file mode 100644
index 000000000000..d839af91fe03
--- /dev/null
+++ b/arch/arm/mach-loki/irq.c
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-loki/irq.c
+ *
+ * Marvell Loki (88RC8480) IRQ handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <asm/io.h>
+#include <asm/plat-orion/irq.h>
+#include "common.h"
+
+void __init loki_init_irq(void)
+{
+        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_OFF));
+}
diff --git a/arch/arm/mach-loki/lb88rc8480-setup.c b/arch/arm/mach-loki/lb88rc8480-setup.c
new file mode 100644
index 000000000000..d1b9e6e6253a
--- /dev/null
+++ b/arch/arm/mach-loki/lb88rc8480-setup.c
@@ -0,0 +1,100 @@
+/*
+ * arch/arm/mach-loki/lb88rc8480-setup.c
+ *
+ * Marvell LB88RC8480 Development Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/timer.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/arch/loki.h>
+#include "common.h"
+
+#define LB88RC8480_FLASH_BOOT_CS_BASE   0xf8000000
+#define LB88RC8480_FLASH_BOOT_CS_SIZE   SZ_128M
+
+#define LB88RC8480_NOR_BOOT_BASE        0xff000000
+#define LB88RC8480_NOR_BOOT_SIZE        SZ_16M
+
+static struct mtd_partition lb88rc8480_boot_flash_parts[] = {
+        {
+                .name   = "kernel",
+                .offset = 0,
+                .size   = SZ_2M,
+        }, {
+                .name   = "root-fs",
+                .offset = SZ_2M,
+                .size   = (SZ_8M + SZ_4M + SZ_1M),
+        }, {
+                .name   = "u-boot",
+                .offset = (SZ_8M + SZ_4M + SZ_2M + SZ_1M),
+                .size   = SZ_1M,
+        },
+};
+
+static struct physmap_flash_data lb88rc8480_boot_flash_data = {
+        .parts          = lb88rc8480_boot_flash_parts,
+        .nr_parts       = ARRAY_SIZE(lb88rc8480_boot_flash_parts),
+        .width          = 1,    /* 8 bit bus width */
+};
+
+static struct resource lb88rc8480_boot_flash_resource = {
+        .flags  = IORESOURCE_MEM,
+        .start  = LB88RC8480_NOR_BOOT_BASE,
+        .end    = LB88RC8480_NOR_BOOT_BASE + LB88RC8480_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device lb88rc8480_boot_flash = {
+        .name   = "physmap-flash",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &lb88rc8480_boot_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &lb88rc8480_boot_flash_resource,
+};
+
+static struct mv643xx_eth_platform_data lb88rc8480_ge0_data = {
+        .phy_addr       = 1,
+        .mac_addr       = { 0x00, 0x50, 0x43, 0x11, 0x22, 0x33 },
+};
+
+static void __init lb88rc8480_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        loki_init();
+
+        loki_ge0_init(&lb88rc8480_ge0_data);
+        loki_sas_init();
+        loki_uart0_init();
+        loki_uart1_init();
+
+        loki_setup_dev_boot_win(LB88RC8480_FLASH_BOOT_CS_BASE,
+                                LB88RC8480_FLASH_BOOT_CS_SIZE);
+        platform_device_register(&lb88rc8480_boot_flash);
+}
+
+MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board")
+        /* Maintainer: Ke Wei <kewei@marvell.com> */
+        .phys_io        = LOKI_REGS_PHYS_BASE,
+        .io_pg_offst    = ((LOKI_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = lb88rc8480_init,
+        .map_io         = loki_map_io,
+        .init_irq       = loki_init_irq,
+        .timer          = &loki_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig
new file mode 100644
index 000000000000..d83cb86837db
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/Kconfig
@@ -0,0 +1,13 @@
+if ARCH_MV78XX0
+
+menu "Marvell MV78xx0 Implementations"
+
+config MACH_DB78X00_BP
+        bool "Marvell DB-78x00-BP Development Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell DB-78x00-BP Development Board.
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile
new file mode 100644
index 000000000000..ec16c05c3b1b
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/Makefile
@@ -0,0 +1,2 @@
+obj-y                           += common.o addr-map.o irq.o pcie.o
+obj-$(CONFIG_MACH_DB78X00_BP)   += db78x00-bp-setup.o
diff --git a/arch/arm/mach-mv78xx0/Makefile.boot b/arch/arm/mach-mv78xx0/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
new file mode 100644
index 000000000000..4004b672a2eb
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -0,0 +1,156 @@
+/*
+ * arch/arm/mach-mv78xx0/addr-map.c
+ *
+ * Address map functions for Marvell MV78xx0 SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <asm/io.h>
+#include "common.h"
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define TARGET_DDR              0
+#define TARGET_DEV_BUS          1
+#define TARGET_PCIE0            4
+#define TARGET_PCIE1            8
+#define TARGET_PCIE(i)          ((i) ? TARGET_PCIE1 : TARGET_PCIE0)
+#define ATTR_DEV_SPI_ROM        0x1f
+#define ATTR_DEV_BOOT           0x2f
+#define ATTR_DEV_CS3            0x37
+#define ATTR_DEV_CS2            0x3b
+#define ATTR_DEV_CS1            0x3d
+#define ATTR_DEV_CS0            0x3e
+#define ATTR_PCIE_IO(l)         (0xf0 & ~(0x10 << (l)))
+#define ATTR_PCIE_MEM(l)        (0xf8 & ~(0x10 << (l)))
+
+/*
+ * Helpers to get DDR bank info
+ */
+#define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
+#define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
+
+/*
+ * CPU Address Decode Windows registers
+ */
+#define WIN0_OFF(n)             (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
+#define WIN8_OFF(n)             (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
+#define WIN_CTRL_OFF            0x0000
+#define WIN_BASE_OFF            0x0004
+#define WIN_REMAP_LO_OFF        0x0008
+#define WIN_REMAP_HI_OFF        0x000c
+
+
+struct mbus_dram_target_info mv78xx0_mbus_dram_info;
+
+static void __init __iomem *win_cfg_base(int win)
+{
+        /*
+         * Find the control register base address for this window.
+         *
+         * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's)
+         * MBUS bridge depending on which CPU core we're running on,
+         * so we don't need to take that into account here.
+         */
+
+        return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
+}
+
+static int __init cpu_win_can_remap(int win)
+{
+        if (win < 8)
+                return 1;
+
+        return 0;
+}
+
+static void __init setup_cpu_win(int win, u32 base, u32 size,
+                                 u8 target, u8 attr, int remap)
+{
+        void __iomem *addr = win_cfg_base(win);
+        u32 ctrl;
+
+        base &= 0xffff0000;
+        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
+
+        writel(base, addr + WIN_BASE_OFF);
+        writel(ctrl, addr + WIN_CTRL_OFF);
+        if (cpu_win_can_remap(win)) {
+                if (remap < 0)
+                        remap = base;
+
+                writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
+                writel(0, addr + WIN_REMAP_HI_OFF);
+        }
+}
+
+void __init mv78xx0_setup_cpu_mbus(void)
+{
+        void __iomem *addr;
+        int i;
+        int cs;
+
+        /*
+         * First, disable and clear windows.
+         */
+        for (i = 0; i < 14; i++) {
+                addr = win_cfg_base(i);
+
+                writel(0, addr + WIN_BASE_OFF);
+                writel(0, addr + WIN_CTRL_OFF);
+                if (cpu_win_can_remap(i)) {
+                        writel(0, addr + WIN_REMAP_LO_OFF);
+                        writel(0, addr + WIN_REMAP_HI_OFF);
+                }
+        }
+
+        /*
+         * Setup MBUS dram target info.
+         */
+        mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+
+        if (mv78xx0_core_index() == 0)
+                addr = (void __iomem *)DDR_WINDOW_CPU0_BASE;
+        else
+                addr = (void __iomem *)DDR_WINDOW_CPU1_BASE;
+
+        for (i = 0, cs = 0; i < 4; i++) {
+                u32 base = readl(addr + DDR_BASE_CS_OFF(i));
+                u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
+
+                /*
+                 * Chip select enabled?
+                 */
+                if (size & 1) {
+                        struct mbus_dram_window *w;
+
+                        w = &mv78xx0_mbus_dram_info.cs[cs++];
+                        w->cs_index = i;
+                        w->mbus_attr = 0xf & ~(1 << i);
+                        w->base = base & 0xffff0000;
+                        w->size = (size | 0x0000ffff) + 1;
+                }
+        }
+        mv78xx0_mbus_dram_info.num_cs = cs;
+}
+
+void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
+                                      int maj, int min)
+{
+        setup_cpu_win(window, base, size, TARGET_PCIE(maj),
+                      ATTR_PCIE_IO(min), -1);
+}
+
+void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
+                                       int maj, int min)
+{
+        setup_cpu_win(window, base, size, TARGET_PCIE(maj),
+                      ATTR_PCIE_MEM(min), -1);
+}
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
new file mode 100644
index 000000000000..d27b83b7bf62
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -0,0 +1,754 @@
+/*
+ * arch/arm/mach-mv78xx0/common.c
+ *
+ * Core functions for Marvell MV78xx0 SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/mbus.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ata_platform.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/arch/mv78xx0.h>
+#include <asm/plat-orion/cache-feroceon-l2.h>
+#include <asm/plat-orion/ehci-orion.h>
+#include <asm/plat-orion/orion_nand.h>
+#include <asm/plat-orion/time.h>
+#include "common.h"
+
+
+/*****************************************************************************
+ * Common bits
+ ****************************************************************************/
+int mv78xx0_core_index(void)
+{
+        u32 extra;
+
+        /*
+         * Read Extra Features register.
+         */
+        __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
+
+        return !!(extra & 0x00004000);
+}
+
+static int get_hclk(void)
+{
+        int hclk;
+
+        /*
+         * HCLK tick rate is configured by DEV_D[7:5] pins.
+         */
+        switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
+        case 0:
+                hclk = 166666667;
+                break;
+        case 1:
+                hclk = 200000000;
+                break;
+        case 2:
+                hclk = 266666667;
+                break;
+        case 3:
+                hclk = 333333333;
+                break;
+        case 4:
+                hclk = 400000000;
+                break;
+        default:
+                panic("unknown HCLK PLL setting: %.8x\n",
+                        readl(SAMPLE_AT_RESET_LOW));
+        }
+
+        return hclk;
+}
+
+static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
+{
+        u32 cfg;
+
+        /*
+         * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
+         * PCLK/L2CLK by bits [19:14].
+         */
+        if (core_index == 0) {
+                cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
+        } else {
+                cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
+        }
+
+        /*
+         * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
+         * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
+         */
+        *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
+
+        /*
+         * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
+         * ratio (1, 2, 3).
+         */
+        *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
+}
+
+static int get_tclk(void)
+{
+        int tclk;
+
+        /*
+         * TCLK tick rate is configured by DEV_A[2:0] strap pins.
+         */
+        switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
+        case 1:
+                tclk = 166666667;
+                break;
+        case 3:
+                tclk = 200000000;
+                break;
+        default:
+                panic("unknown TCLK PLL setting: %.8x\n",
+                        readl(SAMPLE_AT_RESET_HIGH));
+        }
+
+        return tclk;
+}
+
+
+/*****************************************************************************
+ * I/O Address Mapping
+ ****************************************************************************/
+static struct map_desc mv78xx0_io_desc[] __initdata = {
+        {
+                .virtual        = MV78XX0_CORE_REGS_VIRT_BASE,
+                .pfn            = 0,
+                .length         = MV78XX0_CORE_REGS_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MV78XX0_PCIE_IO_VIRT_BASE(0),
+                .pfn            = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
+                .length         = MV78XX0_PCIE_IO_SIZE * 8,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MV78XX0_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
+                .length         = MV78XX0_REGS_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+void __init mv78xx0_map_io(void)
+{
+        unsigned long phys;
+
+        /*
+         * Map the right set of per-core registers depending on
+         * which core we are running on.
+         */
+        if (mv78xx0_core_index() == 0) {
+                phys = MV78XX0_CORE0_REGS_PHYS_BASE;
+        } else {
+                phys = MV78XX0_CORE1_REGS_PHYS_BASE;
+        }
+        mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
+
+        iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
+}
+
+
+/*****************************************************************************
+ * EHCI
+ ****************************************************************************/
+static struct orion_ehci_data mv78xx0_ehci_data = {
+        .dram           = &mv78xx0_mbus_dram_info,
+};
+
+static u64 ehci_dmamask = 0xffffffffUL;
+
+
+/*****************************************************************************
+ * EHCI0
+ ****************************************************************************/
+static struct resource mv78xx0_ehci0_resources[] = {
+        {
+                .start  = USB0_PHYS_BASE,
+                .end    = USB0_PHYS_BASE + 0x0fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_MV78XX0_USB_0,
+                .end    = IRQ_MV78XX0_USB_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_ehci0 = {
+        .name           = "orion-ehci",
+        .id             = 0,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &mv78xx0_ehci_data,
+        },
+        .resource       = mv78xx0_ehci0_resources,
+        .num_resources  = ARRAY_SIZE(mv78xx0_ehci0_resources),
+};
+
+void __init mv78xx0_ehci0_init(void)
+{
+        platform_device_register(&mv78xx0_ehci0);
+}
+
+
+/*****************************************************************************
+ * EHCI1
+ ****************************************************************************/
+static struct resource mv78xx0_ehci1_resources[] = {
+        {
+                .start  = USB1_PHYS_BASE,
+                .end    = USB1_PHYS_BASE + 0x0fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_MV78XX0_USB_1,
+                .end    = IRQ_MV78XX0_USB_1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_ehci1 = {
+        .name           = "orion-ehci",
+        .id             = 1,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &mv78xx0_ehci_data,
+        },
+        .resource       = mv78xx0_ehci1_resources,
+        .num_resources  = ARRAY_SIZE(mv78xx0_ehci1_resources),
+};
+
+void __init mv78xx0_ehci1_init(void)
+{
+        platform_device_register(&mv78xx0_ehci1);
+}
+
+
+/*****************************************************************************
+ * EHCI2
+ ****************************************************************************/
+static struct resource mv78xx0_ehci2_resources[] = {
+        {
+                .start  = USB2_PHYS_BASE,
+                .end    = USB2_PHYS_BASE + 0x0fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_MV78XX0_USB_2,
+                .end    = IRQ_MV78XX0_USB_2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_ehci2 = {
+        .name           = "orion-ehci",
+        .id             = 2,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &mv78xx0_ehci_data,
+        },
+        .resource       = mv78xx0_ehci2_resources,
+        .num_resources  = ARRAY_SIZE(mv78xx0_ehci2_resources),
+};
+
+void __init mv78xx0_ehci2_init(void)
+{
+        platform_device_register(&mv78xx0_ehci2);
+}
+
+
+/*****************************************************************************
+ * GE00
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
+        .t_clk          = 0,
+        .dram           = &mv78xx0_mbus_dram_info,
+};
+
+static struct resource mv78xx0_ge00_shared_resources[] = {
+        {
+                .name   = "ge00 base",
+                .start  = GE00_PHYS_BASE + 0x2000,
+                .end    = GE00_PHYS_BASE + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device mv78xx0_ge00_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &mv78xx0_ge00_shared_data,
+        },
+        .num_resources  = 1,
+        .resource       = mv78xx0_ge00_shared_resources,
+};
+
+static struct resource mv78xx0_ge00_resources[] = {
+        {
+                .name   = "ge00 irq",
+                .start  = IRQ_MV78XX0_GE00_SUM,
+                .end    = IRQ_MV78XX0_GE00_SUM,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_ge00 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = mv78xx0_ge00_resources,
+};
+
+void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
+{
+        eth_data->shared = &mv78xx0_ge00_shared;
+        mv78xx0_ge00.dev.platform_data = eth_data;
+
+        platform_device_register(&mv78xx0_ge00_shared);
+        platform_device_register(&mv78xx0_ge00);
+}
+
+
+/*****************************************************************************
+ * GE01
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
+        .t_clk          = 0,
+        .dram           = &mv78xx0_mbus_dram_info,
+};
+
+static struct resource mv78xx0_ge01_shared_resources[] = {
+        {
+                .name   = "ge01 base",
+                .start  = GE01_PHYS_BASE + 0x2000,
+                .end    = GE01_PHYS_BASE + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device mv78xx0_ge01_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &mv78xx0_ge01_shared_data,
+        },
+        .num_resources  = 1,
+        .resource       = mv78xx0_ge01_shared_resources,
+};
+
+static struct resource mv78xx0_ge01_resources[] = {
+        {
+                .name   = "ge01 irq",
+                .start  = IRQ_MV78XX0_GE01_SUM,
+                .end    = IRQ_MV78XX0_GE01_SUM,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_ge01 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 1,
+        .num_resources  = 1,
+        .resource       = mv78xx0_ge01_resources,
+};
+
+void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
+{
+        eth_data->shared = &mv78xx0_ge01_shared;
+        eth_data->shared_smi = &mv78xx0_ge00_shared;
+        mv78xx0_ge01.dev.platform_data = eth_data;
+
+        platform_device_register(&mv78xx0_ge01_shared);
+        platform_device_register(&mv78xx0_ge01);
+}
+
+
+/*****************************************************************************
+ * GE10
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
+        .t_clk          = 0,
+        .dram           = &mv78xx0_mbus_dram_info,
+};
+
+static struct resource mv78xx0_ge10_shared_resources[] = {
+        {
+                .name   = "ge10 base",
+                .start  = GE10_PHYS_BASE + 0x2000,
+                .end    = GE10_PHYS_BASE + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device mv78xx0_ge10_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &mv78xx0_ge10_shared_data,
+        },
+        .num_resources  = 1,
+        .resource       = mv78xx0_ge10_shared_resources,
+};
+
+static struct resource mv78xx0_ge10_resources[] = {
+        {
+                .name   = "ge10 irq",
+                .start  = IRQ_MV78XX0_GE10_SUM,
+                .end    = IRQ_MV78XX0_GE10_SUM,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_ge10 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 2,
+        .num_resources  = 1,
+        .resource       = mv78xx0_ge10_resources,
+};
+
+void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
+{
+        eth_data->shared = &mv78xx0_ge10_shared;
+        eth_data->shared_smi = &mv78xx0_ge00_shared;
+        mv78xx0_ge10.dev.platform_data = eth_data;
+
+        platform_device_register(&mv78xx0_ge10_shared);
+        platform_device_register(&mv78xx0_ge10);
+}
+
+
+/*****************************************************************************
+ * GE11
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
+        .t_clk          = 0,
+        .dram           = &mv78xx0_mbus_dram_info,
+};
+
+static struct resource mv78xx0_ge11_shared_resources[] = {
+        {
+                .name   = "ge11 base",
+                .start  = GE11_PHYS_BASE + 0x2000,
+                .end    = GE11_PHYS_BASE + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device mv78xx0_ge11_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &mv78xx0_ge11_shared_data,
+        },
+        .num_resources  = 1,
+        .resource       = mv78xx0_ge11_shared_resources,
+};
+
+static struct resource mv78xx0_ge11_resources[] = {
+        {
+                .name   = "ge11 irq",
+                .start  = IRQ_MV78XX0_GE11_SUM,
+                .end    = IRQ_MV78XX0_GE11_SUM,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_ge11 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 3,
+        .num_resources  = 1,
+        .resource       = mv78xx0_ge11_resources,
+};
+
+void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
+{
+        eth_data->shared = &mv78xx0_ge11_shared;
+        eth_data->shared_smi = &mv78xx0_ge00_shared;
+        mv78xx0_ge11.dev.platform_data = eth_data;
+
+        platform_device_register(&mv78xx0_ge11_shared);
+        platform_device_register(&mv78xx0_ge11);
+}
+
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct resource mv78xx0_sata_resources[] = {
+        {
+                .name   = "sata base",
+                .start  = SATA_PHYS_BASE,
+                .end    = SATA_PHYS_BASE + 0x5000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "sata irq",
+                .start  = IRQ_MV78XX0_SATA,
+                .end    = IRQ_MV78XX0_SATA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_sata = {
+        .name           = "sata_mv",
+        .id             = 0,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(mv78xx0_sata_resources),
+        .resource       = mv78xx0_sata_resources,
+};
+
+void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
+{
+        sata_data->dram = &mv78xx0_mbus_dram_info;
+        mv78xx0_sata.dev.platform_data = sata_data;
+        platform_device_register(&mv78xx0_sata);
+}
+
+
+/*****************************************************************************
+ * UART0
+ ****************************************************************************/
+static struct plat_serial8250_port mv78xx0_uart0_data[] = {
+        {
+                .mapbase        = UART0_PHYS_BASE,
+                .membase        = (char *)UART0_VIRT_BASE,
+                .irq            = IRQ_MV78XX0_UART_0,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 0,
+        }, {
+        },
+};
+
+static struct resource mv78xx0_uart0_resources[] = {
+        {
+                .start          = UART0_PHYS_BASE,
+                .end            = UART0_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_MV78XX0_UART_0,
+                .end            = IRQ_MV78XX0_UART_0,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_uart0 = {
+        .name                   = "serial8250",
+        .id                     = 0,
+        .dev                    = {
+                .platform_data  = mv78xx0_uart0_data,
+        },
+        .resource               = mv78xx0_uart0_resources,
+        .num_resources          = ARRAY_SIZE(mv78xx0_uart0_resources),
+};
+
+void __init mv78xx0_uart0_init(void)
+{
+        platform_device_register(&mv78xx0_uart0);
+}
+
+
+/*****************************************************************************
+ * UART1
+ ****************************************************************************/
+static struct plat_serial8250_port mv78xx0_uart1_data[] = {
+        {
+                .mapbase        = UART1_PHYS_BASE,
+                .membase        = (char *)UART1_VIRT_BASE,
+                .irq            = IRQ_MV78XX0_UART_1,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 0,
+        }, {
+        },
+};
+
+static struct resource mv78xx0_uart1_resources[] = {
+        {
+                .start          = UART1_PHYS_BASE,
+                .end            = UART1_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_MV78XX0_UART_1,
+                .end            = IRQ_MV78XX0_UART_1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_uart1 = {
+        .name                   = "serial8250",
+        .id                     = 1,
+        .dev                    = {
+                .platform_data  = mv78xx0_uart1_data,
+        },
+        .resource               = mv78xx0_uart1_resources,
+        .num_resources          = ARRAY_SIZE(mv78xx0_uart1_resources),
+};
+
+void __init mv78xx0_uart1_init(void)
+{
+        platform_device_register(&mv78xx0_uart1);
+}
+
+
+/*****************************************************************************
+ * UART2
+ ****************************************************************************/
+static struct plat_serial8250_port mv78xx0_uart2_data[] = {
+        {
+                .mapbase        = UART2_PHYS_BASE,
+                .membase        = (char *)UART2_VIRT_BASE,
+                .irq            = IRQ_MV78XX0_UART_2,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 0,
+        }, {
+        },
+};
+
+static struct resource mv78xx0_uart2_resources[] = {
+        {
+                .start          = UART2_PHYS_BASE,
+                .end            = UART2_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_MV78XX0_UART_2,
+                .end            = IRQ_MV78XX0_UART_2,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_uart2 = {
+        .name                   = "serial8250",
+        .id                     = 2,
+        .dev                    = {
+                .platform_data  = mv78xx0_uart2_data,
+        },
+        .resource               = mv78xx0_uart2_resources,
+        .num_resources          = ARRAY_SIZE(mv78xx0_uart2_resources),
+};
+
+void __init mv78xx0_uart2_init(void)
+{
+        platform_device_register(&mv78xx0_uart2);
+}
+
+
+/*****************************************************************************
+ * UART3
+ ****************************************************************************/
+static struct plat_serial8250_port mv78xx0_uart3_data[] = {
+        {
+                .mapbase        = UART3_PHYS_BASE,
+                .membase        = (char *)UART3_VIRT_BASE,
+                .irq            = IRQ_MV78XX0_UART_3,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 0,
+        }, {
+        },
+};
+
+static struct resource mv78xx0_uart3_resources[] = {
+        {
+                .start          = UART3_PHYS_BASE,
+                .end            = UART3_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_MV78XX0_UART_3,
+                .end            = IRQ_MV78XX0_UART_3,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mv78xx0_uart3 = {
+        .name                   = "serial8250",
+        .id                     = 3,
+        .dev                    = {
+                .platform_data  = mv78xx0_uart3_data,
+        },
+        .resource               = mv78xx0_uart3_resources,
+        .num_resources          = ARRAY_SIZE(mv78xx0_uart3_resources),
+};
+
+void __init mv78xx0_uart3_init(void)
+{
+        platform_device_register(&mv78xx0_uart3);
+}
+
+
+/*****************************************************************************
+ * Time handling
+ ****************************************************************************/
+static void mv78xx0_timer_init(void)
+{
+        orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk());
+}
+
+struct sys_timer mv78xx0_timer = {
+        .init = mv78xx0_timer_init,
+};
+
+
+/*****************************************************************************
+ * General
+ ****************************************************************************/
+static int __init is_l2_writethrough(void)
+{
+        return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
+}
+
+void __init mv78xx0_init(void)
+{
+        int core_index;
+        int hclk;
+        int pclk;
+        int l2clk;
+        int tclk;
+
+        core_index = mv78xx0_core_index();
+        hclk = get_hclk();
+        get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
+        tclk = get_tclk();
+
+        printk(KERN_INFO "MV78xx0 core #%d, ", core_index);
+        printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
+        printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
+        printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
+        printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000);
+
+        mv78xx0_setup_cpu_mbus();
+
+#ifdef CONFIG_CACHE_FEROCEON_L2
+        feroceon_l2_init(is_l2_writethrough());
+#endif
+
+        mv78xx0_ge00_shared_data.t_clk = tclk;
+        mv78xx0_ge01_shared_data.t_clk = tclk;
+        mv78xx0_ge10_shared_data.t_clk = tclk;
+        mv78xx0_ge11_shared_data.t_clk = tclk;
+        mv78xx0_uart0_data[0].uartclk = tclk;
+        mv78xx0_uart1_data[0].uartclk = tclk;
+        mv78xx0_uart2_data[0].uartclk = tclk;
+        mv78xx0_uart3_data[0].uartclk = tclk;
+}
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
new file mode 100644
index 000000000000..78af5de319dd
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -0,0 +1,49 @@
+/*
+ * arch/arm/mach-mv78xx0/common.h
+ *
+ * Core functions for Marvell MV78xx0 SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_MV78XX0_COMMON_H
+#define __ARCH_MV78XX0_COMMON_H
+
+struct mv643xx_eth_platform_data;
+struct mv_sata_platform_data;
+
+/*
+ * Basic MV78xx0 init functions used early by machine-setup.
+ */
+int mv78xx0_core_index(void);
+void mv78xx0_map_io(void);
+void mv78xx0_init(void);
+void mv78xx0_init_irq(void);
+
+extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
+void mv78xx0_setup_cpu_mbus(void);
+void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
+                               int maj, int min);
+void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
+                                int maj, int min);
+
+void mv78xx0_ehci0_init(void);
+void mv78xx0_ehci1_init(void);
+void mv78xx0_ehci2_init(void);
+void mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data);
+void mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data);
+void mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data);
+void mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data);
+void mv78xx0_pcie_init(int init_port0, int init_port1);
+void mv78xx0_sata_init(struct mv_sata_platform_data *sata_data);
+void mv78xx0_uart0_init(void);
+void mv78xx0_uart1_init(void);
+void mv78xx0_uart2_init(void);
+void mv78xx0_uart3_init(void);
+
+extern struct sys_timer mv78xx0_timer;
+
+
+#endif
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
new file mode 100644
index 000000000000..0c93d19193df
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -0,0 +1,94 @@
+/*
+ * arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+ *
+ * Marvell DB-78x00-BP Development Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/arch/mv78xx0.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include "common.h"
+
+static struct mv643xx_eth_platform_data db78x00_ge00_data = {
+        .phy_addr       = 8,
+};
+
+static struct mv643xx_eth_platform_data db78x00_ge01_data = {
+        .phy_addr       = 9,
+};
+
+static struct mv643xx_eth_platform_data db78x00_ge10_data = {
+        .phy_addr       = -1,
+};
+
+static struct mv643xx_eth_platform_data db78x00_ge11_data = {
+        .phy_addr       = -1,
+};
+
+static struct mv_sata_platform_data db78x00_sata_data = {
+        .n_ports        = 2,
+};
+
+static void __init db78x00_init(void)
+{
+        /*
+         * Basic MV78xx0 setup. Needs to be called early.
+         */
+        mv78xx0_init();
+
+        /*
+         * Partition on-chip peripherals between the two CPU cores.
+         */
+        if (mv78xx0_core_index() == 0) {
+                mv78xx0_ehci0_init();
+                mv78xx0_ehci1_init();
+                mv78xx0_ehci2_init();
+                mv78xx0_ge00_init(&db78x00_ge00_data);
+                mv78xx0_ge01_init(&db78x00_ge01_data);
+                mv78xx0_ge10_init(&db78x00_ge10_data);
+                mv78xx0_ge11_init(&db78x00_ge11_data);
+                mv78xx0_sata_init(&db78x00_sata_data);
+                mv78xx0_uart0_init();
+                mv78xx0_uart2_init();
+        } else {
+                mv78xx0_uart1_init();
+                mv78xx0_uart3_init();
+        }
+}
+
+static int __init db78x00_pci_init(void)
+{
+        if (machine_is_db78x00_bp()) {
+                /*
+                 * Assign the x16 PCIe slot on the board to CPU core
+                 * #0, and let CPU core #1 have the four x1 slots.
+                 */
+                if (mv78xx0_core_index() == 0)
+                        mv78xx0_pcie_init(0, 1);
+                else
+                        mv78xx0_pcie_init(1, 0);
+        }
+
+        return 0;
+}
+subsys_initcall(db78x00_pci_init);
+
+MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
+        /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
+        .phys_io        = MV78XX0_REGS_PHYS_BASE,
+        .io_pg_offst    = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = db78x00_init,
+        .map_io         = mv78xx0_map_io,
+        .init_irq       = mv78xx0_init_irq,
+        .timer          = &mv78xx0_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
new file mode 100644
index 000000000000..60f4ee4d4532
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-mv78xx0/irq.c
+ *
+ * MV78xx0 IRQ handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <asm/arch/mv78xx0.h>
+#include <asm/plat-orion/irq.h>
+#include "common.h"
+
+void __init mv78xx0_init_irq(void)
+{
+        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
+        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+}
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
new file mode 100644
index 000000000000..b78e1443159f
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -0,0 +1,312 @@
+/*
+ * arch/arm/mach-mv78xx0/pcie.c
+ *
+ * PCIe functions for Marvell MV78xx0 SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/mbus.h>
+#include <asm/mach/pci.h>
+#include <asm/plat-orion/pcie.h>
+#include "common.h"
+
+struct pcie_port {
+        u8                      maj;
+        u8                      min;
+        u8                      root_bus_nr;
+        void __iomem            *base;
+        spinlock_t              conf_lock;
+        char                    io_space_name[16];
+        char                    mem_space_name[16];
+        struct resource         res[2];
+};
+
+static struct pcie_port pcie_port[8];
+static int num_pcie_ports;
+static struct resource pcie_io_space;
+static struct resource pcie_mem_space;
+
+
+static void __init mv78xx0_pcie_preinit(void)
+{
+        int i;
+        u32 size_each;
+        u32 start;
+        int win;
+
+        pcie_io_space.name = "PCIe I/O Space";
+        pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
+        pcie_io_space.end =
+                MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
+        pcie_io_space.flags = IORESOURCE_IO;
+        if (request_resource(&iomem_resource, &pcie_io_space))
+                panic("can't allocate PCIe I/O space");
+
+        pcie_mem_space.name = "PCIe MEM Space";
+        pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE;
+        pcie_mem_space.end =
+                MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1;
+        pcie_mem_space.flags = IORESOURCE_MEM;
+        if (request_resource(&iomem_resource, &pcie_mem_space))
+                panic("can't allocate PCIe MEM space");
+
+        for (i = 0; i < num_pcie_ports; i++) {
+                struct pcie_port *pp = pcie_port + i;
+
+                snprintf(pp->io_space_name, sizeof(pp->io_space_name),
+                        "PCIe %d.%d I/O", pp->maj, pp->min);
+                pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
+                pp->res[0].name = pp->io_space_name;
+                pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i);
+                pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1;
+                pp->res[0].flags = IORESOURCE_IO;
+
+                snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
+                        "PCIe %d.%d MEM", pp->maj, pp->min);
+                pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
+                pp->res[1].name = pp->mem_space_name;
+                pp->res[1].flags = IORESOURCE_MEM;
+        }
+
+        switch (num_pcie_ports) {
+        case 0:
+                size_each = 0;
+                break;
+
+        case 1:
+                size_each = 0x30000000;
+                break;
+
+        case 2 ... 3:
+                size_each = 0x10000000;
+                break;
+
+        case 4 ... 6:
+                size_each = 0x08000000;
+                break;
+
+        case 7:
+                size_each = 0x04000000;
+                break;
+
+        default:
+                panic("invalid number of PCIe ports");
+        }
+
+        start = MV78XX0_PCIE_MEM_PHYS_BASE;
+        for (i = 0; i < num_pcie_ports; i++) {
+                struct pcie_port *pp = pcie_port + i;
+
+                pp->res[1].start = start;
+                pp->res[1].end = start + size_each - 1;
+                start += size_each;
+        }
+
+        for (i = 0; i < num_pcie_ports; i++) {
+                struct pcie_port *pp = pcie_port + i;
+
+                if (request_resource(&pcie_io_space, &pp->res[0]))
+                        panic("can't allocate PCIe I/O sub-space");
+
+                if (request_resource(&pcie_mem_space, &pp->res[1]))
+                        panic("can't allocate PCIe MEM sub-space");
+        }
+
+        win = 0;
+        for (i = 0; i < num_pcie_ports; i++) {
+                struct pcie_port *pp = pcie_port + i;
+
+                mv78xx0_setup_pcie_io_win(win++, pp->res[0].start,
+                        pp->res[0].end - pp->res[0].start + 1,
+                        pp->maj, pp->min);
+
+                mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start,
+                        pp->res[1].end - pp->res[1].start + 1,
+                        pp->maj, pp->min);
+        }
+}
+
+static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+        struct pcie_port *pp;
+
+        if (nr >= num_pcie_ports)
+                return 0;
+
+        pp = &pcie_port[nr];
+        pp->root_bus_nr = sys->busnr;
+
+        /*
+         * Generic PCIe unit setup.
+         */
+        orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
+        orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info);
+
+        sys->resource[0] = &pp->res[0];
+        sys->resource[1] = &pp->res[1];
+        sys->resource[2] = NULL;
+
+        return 1;
+}
+
+static struct pcie_port *bus_to_port(int bus)
+{
+        int i;
+
+        for (i = num_pcie_ports - 1; i >= 0; i--) {
+                int rbus = pcie_port[i].root_bus_nr;
+                if (rbus != -1 && rbus <= bus)
+                        break;
+        }
+
+        return i >= 0 ? pcie_port + i : NULL;
+}
+
+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
+{
+        /*
+         * Don't go out when trying to access nonexisting devices
+         * on the local bus.
+         */
+        if (bus == pp->root_bus_nr && dev > 1)
+                return 0;
+
+        return 1;
+}
+
+static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+                        int size, u32 *val)
+{
+        struct pcie_port *pp = bus_to_port(bus->number);
+        unsigned long flags;
+        int ret;
+
+        if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        spin_lock_irqsave(&pp->conf_lock, flags);
+        ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&pp->conf_lock, flags);
+
+        return ret;
+}
+
+static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+                        int where, int size, u32 val)
+{
+        struct pcie_port *pp = bus_to_port(bus->number);
+        unsigned long flags;
+        int ret;
+
+        if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        spin_lock_irqsave(&pp->conf_lock, flags);
+        ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&pp->conf_lock, flags);
+
+        return ret;
+}
+
+static struct pci_ops pcie_ops = {
+        .read = pcie_rd_conf,
+        .write = pcie_wr_conf,
+};
+
+static void __devinit rc_pci_fixup(struct pci_dev *dev)
+{
+        /*
+         * Prevent enumeration of root complex.
+         */
+        if (dev->bus->parent == NULL && dev->devfn == 0) {
+                int i;
+
+                for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+                        dev->resource[i].start = 0;
+                        dev->resource[i].end   = 0;
+                        dev->resource[i].flags = 0;
+                }
+        }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
+
+static struct pci_bus __init *
+mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        struct pci_bus *bus;
+
+        if (nr < num_pcie_ports) {
+                bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+        } else {
+                bus = NULL;
+                BUG();
+        }
+
+        return bus;
+}
+
+static int __init mv78xx0_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        struct pcie_port *pp = bus_to_port(dev->bus->number);
+
+        return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min;
+}
+
+static struct hw_pci mv78xx0_pci __initdata = {
+        .nr_controllers = 8,
+        .preinit        = mv78xx0_pcie_preinit,
+        .swizzle        = pci_std_swizzle,
+        .setup          = mv78xx0_pcie_setup,
+        .scan           = mv78xx0_pcie_scan_bus,
+        .map_irq        = mv78xx0_pcie_map_irq,
+};
+
+static void __init add_pcie_port(int maj, int min, unsigned long base)
+{
+        printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
+
+        if (orion_pcie_link_up((void __iomem *)base)) {
+                struct pcie_port *pp = &pcie_port[num_pcie_ports++];
+
+                printk("link up\n");
+
+                pp->maj = maj;
+                pp->min = min;
+                pp->root_bus_nr = -1;
+                pp->base = (void __iomem *)base;
+                spin_lock_init(&pp->conf_lock);
+                memset(pp->res, 0, sizeof(pp->res));
+        } else {
+                printk("link down, ignoring\n");
+        }
+}
+
+void __init mv78xx0_pcie_init(int init_port0, int init_port1)
+{
+        if (init_port0) {
+                add_pcie_port(0, 0, PCIE00_VIRT_BASE);
+                if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
+                        add_pcie_port(0, 1, PCIE01_VIRT_BASE);
+                        add_pcie_port(0, 2, PCIE02_VIRT_BASE);
+                        add_pcie_port(0, 3, PCIE03_VIRT_BASE);
+                }
+        }
+
+        if (init_port1) {
+                add_pcie_port(1, 0, PCIE10_VIRT_BASE);
+                if (!orion_pcie_x4_mode((void __iomem *)PCIE10_VIRT_BASE)) {
+                        add_pcie_port(1, 1, PCIE11_VIRT_BASE);
+                        add_pcie_port(1, 2, PCIE12_VIRT_BASE);
+                        add_pcie_port(1, 3, PCIE13_VIRT_BASE);
+                }
+        }
+
+        pci_common_init(&mv78xx0_pci);
+}
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
new file mode 100644
index 000000000000..1eaa97cb716d
--- /dev/null
+++ b/arch/arm/mach-mx2/Kconfig
@@ -0,0 +1,39 @@
+comment "MX2 family CPU support"
+        depends on ARCH_MX2
+
+config MACH_MX27
+        bool "i.MX27 support"
+        depends on ARCH_MX2
+        help
+          This enables support for Freescale's MX2 based i.MX27 processor.
+
+comment "MX2 Platforms"
+        depends on ARCH_MX2
+
+config MACH_MX27ADS
+        bool "MX27ADS platform"
+        depends on MACH_MX27
+        help
+          Include support for MX27ADS platform. This includes specific
+          configurations for the board and its peripherals.
+
+config MACH_PCM038
+        bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
+        depends on MACH_MX27
+        help
+          Include support for phyCORE-i.MX27 (aka pcm038) platform. This
+          includes specific configurations for the module and its peripherals.
+
+choice
+        prompt "Baseboard"
+        depends on MACH_PCM038
+        default MACH_PCM970_BASEBOARD
+
+config MACH_PCM970_BASEBOARD
+        prompt "PHYTEC PCM970 development board"
+        bool
+        help
+          This adds board specific devices that can be found on Phytec's
+          PCM970 evaluation board.
+
+endchoice
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
new file mode 100644
index 000000000000..382d86080e86
--- /dev/null
+++ b/arch/arm/mach-mx2/Makefile
@@ -0,0 +1,14 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-y   :=  system.o generic.o devices.o serial.o
+
+obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
+obj-$(CONFIG_MACH_MX27) += clock_imx27.o
+
+obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o
+obj-$(CONFIG_MACH_PCM038) += pcm038.o
+obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
diff --git a/arch/arm/mach-mx2/Makefile.boot b/arch/arm/mach-mx2/Makefile.boot
new file mode 100644
index 000000000000..696831dcd485
--- /dev/null
+++ b/arch/arm/mach-mx2/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0xA0008000
+params_phys-y   := 0xA0000100
+initrd_phys-y   := 0xA0800000
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
new file mode 100644
index 000000000000..0a29ef29c73a
--- /dev/null
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -0,0 +1,1626 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/common.h>
+#include <asm/div64.h>
+#include <asm/mach-types.h>
+
+#include "crm_regs.h"
+
+static struct clk ckil_clk;
+static struct clk mpll_clk;
+static struct clk mpll_main_clk[];
+static struct clk spll_clk;
+
+static int _clk_enable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 1 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void _clk_disable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static int _clk_spll_enable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_CSCR);
+        reg |= CCM_CSCR_SPEN;
+        __raw_writel(reg, CCM_CSCR);
+
+        while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0)
+                ;
+
+        return 0;
+}
+
+static void _clk_spll_disable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_CSCR);
+        reg &= ~CCM_CSCR_SPEN;
+        __raw_writel(reg, CCM_CSCR);
+}
+
+static void _clk_pccr01_enable(unsigned long mask0, unsigned long mask1)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR0);
+        reg |= mask0;
+        __raw_writel(reg, CCM_PCCR0);
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg |= mask1;
+        __raw_writel(reg, CCM_PCCR1);
+
+}
+
+static void _clk_pccr01_disable(unsigned long mask0, unsigned long mask1)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR0);
+        reg &= ~mask0;
+        __raw_writel(reg, CCM_PCCR0);
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg &= ~mask1;
+        __raw_writel(reg, CCM_PCCR1);
+}
+
+static void _clk_pccr10_enable(unsigned long mask1, unsigned long mask0)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg |= mask1;
+        __raw_writel(reg, CCM_PCCR1);
+
+        reg = __raw_readl(CCM_PCCR0);
+        reg |= mask0;
+        __raw_writel(reg, CCM_PCCR0);
+}
+
+static void _clk_pccr10_disable(unsigned long mask1, unsigned long mask0)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg &= ~mask1;
+        __raw_writel(reg, CCM_PCCR1);
+
+        reg = __raw_readl(CCM_PCCR0);
+        reg &= ~mask0;
+        __raw_writel(reg, CCM_PCCR0);
+}
+
+static int _clk_dma_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK);
+
+        return 0;
+}
+
+static void _clk_dma_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK);
+}
+
+static int _clk_rtic_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK);
+
+        return 0;
+}
+
+static void _clk_rtic_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK);
+}
+
+static int _clk_emma_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK);
+
+        return 0;
+}
+
+static void _clk_emma_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK);
+}
+
+static int _clk_slcdc_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK);
+
+        return 0;
+}
+
+static void _clk_slcdc_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK);
+}
+
+static int _clk_fec_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK);
+
+        return 0;
+}
+
+static void _clk_fec_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK);
+}
+
+static int _clk_vpu_enable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg |= CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK;
+        __raw_writel(reg, CCM_PCCR1);
+
+        return 0;
+}
+
+static void _clk_vpu_disable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg &= ~(CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK);
+        __raw_writel(reg, CCM_PCCR1);
+}
+
+static int _clk_sahara2_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK);
+
+        return 0;
+}
+
+static void _clk_sahara2_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK);
+}
+
+static int _clk_mstick1_enable(struct clk *clk)
+{
+        _clk_pccr10_enable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK);
+
+        return 0;
+}
+
+static void _clk_mstick1_disable(struct clk *clk)
+{
+        _clk_pccr10_disable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK);
+}
+
+#define CSCR() (__raw_readl(CCM_CSCR))
+#define PCDR0() (__raw_readl(CCM_PCDR0))
+#define PCDR1() (__raw_readl(CCM_PCDR1))
+
+static int _clk_cpu_set_parent(struct clk *clk, struct clk *parent)
+{
+        int cscr = CSCR();
+
+        if (clk->parent == parent)
+                return 0;
+
+        if (mx27_revision() >= CHIP_REV_2_0) {
+                if (parent == &mpll_main_clk[0]) {
+                        cscr |= CCM_CSCR_ARM_SRC;
+                } else {
+                        if (parent == &mpll_main_clk[1])
+                                cscr &= ~CCM_CSCR_ARM_SRC;
+                        else
+                                return -EINVAL;
+                }
+                __raw_writel(cscr, CCM_CSCR);
+        } else
+                return -ENODEV;
+
+        clk->parent = parent;
+        return 0;
+}
+
+static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate)
+{
+        int div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+        if (parent_rate % rate)
+                div++;
+
+        if (div > 4)
+                div = 4;
+
+        return parent_rate / div;
+}
+
+static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int div;
+        uint32_t reg;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+
+        if (div > 4 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+
+        div--;
+
+        reg = __raw_readl(CCM_CSCR);
+        if (mx27_revision() >= CHIP_REV_2_0) {
+                reg &= ~CCM_CSCR_ARM_MASK;
+                reg |= div << CCM_CSCR_ARM_OFFSET;
+                reg &= ~0x06;
+                __raw_writel(reg | 0x80000000, CCM_CSCR);
+        } else {
+                printk(KERN_ERR "Cant set CPU frequency!\n");
+        }
+
+        return 0;
+}
+
+static unsigned long _clk_perclkx_round_rate(struct clk *clk,
+                                             unsigned long rate)
+{
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+        if (parent_rate % rate)
+                div++;
+
+        if (div > 64)
+                div = 64;
+
+        return parent_rate / div;
+}
+
+static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (clk->id < 0 || clk->id > 3)
+                return -EINVAL;
+
+        div = parent_rate / rate;
+        if (div > 64 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+        div--;
+
+        reg =
+            __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK <<
+                                       (clk->id << 3));
+        reg |= div << (clk->id << 3);
+        __raw_writel(reg, CCM_PCDR1);
+
+        return 0;
+}
+
+static unsigned long _clk_usb_recalc(struct clk *clk)
+{
+        unsigned long usb_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET;
+
+        return parent_rate / (usb_pdf + 1U);
+}
+
+static unsigned long _clk_ssi1_recalc(struct clk *clk)
+{
+        unsigned long ssi1_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        ssi1_pdf = (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK) >>
+                                        CCM_PCDR0_SSI1BAUDDIV_OFFSET;
+
+        if (mx27_revision() >= CHIP_REV_2_0)
+                ssi1_pdf += 4;
+        else
+                ssi1_pdf = (ssi1_pdf < 2) ? 124UL : ssi1_pdf;
+
+        return 2UL * parent_rate / ssi1_pdf;
+}
+
+static unsigned long _clk_ssi2_recalc(struct clk *clk)
+{
+        unsigned long ssi2_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        ssi2_pdf = (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >>
+            CCM_PCDR0_SSI2BAUDDIV_OFFSET;
+
+        if (mx27_revision() >= CHIP_REV_2_0)
+                ssi2_pdf += 4;
+        else
+                ssi2_pdf = (ssi2_pdf < 2) ? 124UL : ssi2_pdf;
+
+        return 2UL * parent_rate / ssi2_pdf;
+}
+
+static unsigned long _clk_nfc_recalc(struct clk *clk)
+{
+        unsigned long nfc_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (mx27_revision() >= CHIP_REV_2_0) {
+                nfc_pdf =
+                    (PCDR0() & CCM_PCDR0_NFCDIV2_MASK) >>
+                    CCM_PCDR0_NFCDIV2_OFFSET;
+        } else {
+                nfc_pdf =
+                    (PCDR0() & CCM_PCDR0_NFCDIV_MASK) >>
+                    CCM_PCDR0_NFCDIV_OFFSET;
+        }
+
+        return parent_rate / (nfc_pdf + 1);
+}
+
+static unsigned long _clk_vpu_recalc(struct clk *clk)
+{
+        unsigned long vpu_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (mx27_revision() >= CHIP_REV_2_0) {
+                vpu_pdf =
+                    (PCDR0() & CCM_PCDR0_VPUDIV2_MASK) >>
+                    CCM_PCDR0_VPUDIV2_OFFSET;
+                vpu_pdf += 4;
+        } else {
+                vpu_pdf =
+                    (PCDR0() & CCM_PCDR0_VPUDIV_MASK) >>
+                    CCM_PCDR0_VPUDIV_OFFSET;
+                vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf;
+        }
+        return 2UL * parent_rate / vpu_pdf;
+}
+
+static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
+{
+        return clk->parent->round_rate(clk->parent, rate);
+}
+
+static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
+{
+        return clk->parent->set_rate(clk->parent, rate);
+}
+
+/* in Hz */
+static unsigned long external_high_reference = 26000000;
+
+static unsigned long get_high_reference_clock_rate(struct clk *clk)
+{
+        return external_high_reference;
+}
+
+/*
+ * the high frequency external clock reference
+ * Default case is 26MHz. Could be changed at runtime
+ * with a call to change_external_high_reference()
+ */
+static struct clk ckih_clk = {
+        .name = "ckih",
+        .get_rate = get_high_reference_clock_rate,
+};
+
+/* in Hz */
+static unsigned long external_low_reference = 32768;
+
+static unsigned long get_low_reference_clock_rate(struct clk *clk)
+{
+        return external_low_reference;
+}
+
+/*
+ * the low frequency external clock reference
+ * Default case is 32.768kHz Could be changed at runtime
+ * with a call to change_external_low_reference()
+ */
+static struct clk ckil_clk = {
+        .name = "ckil",
+        .get_rate = get_low_reference_clock_rate,
+};
+
+static unsigned long get_mpll_clk(struct clk *clk)
+{
+        uint32_t reg;
+        unsigned long ref_clk;
+        unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
+        unsigned long long temp;
+
+        ref_clk = clk_get_rate(clk->parent);
+
+        reg = __raw_readl(CCM_MPCTL0);
+        pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET;
+        mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET;
+        mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET;
+        mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET;
+
+        mfi = (mfi <= 5) ? 5 : mfi;
+        temp = 2LL * ref_clk * mfn;
+        do_div(temp, mfd + 1);
+        temp = 2LL * ref_clk * mfi + temp;
+        do_div(temp, pdf + 1);
+
+        return (unsigned long)temp;
+}
+
+static struct clk mpll_clk = {
+        .name = "mpll",
+        .parent = &ckih_clk,
+        .get_rate = get_mpll_clk,
+};
+
+static unsigned long _clk_mpll_main_get_rate(struct clk *clk)
+{
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        /* i.MX27 TO2:
+         * clk->id == 0: arm clock source path 1 which is from 2*MPLL/DIV_2
+         * clk->id == 1: arm clock source path 2 which is from 2*MPLL/DIV_3
+         */
+
+        if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1)
+                return 2UL * parent_rate / 3UL;
+
+        return parent_rate;
+}
+
+static struct clk mpll_main_clk[] = {
+        {
+                /* For i.MX27 TO2, it is the MPLL path 1 of ARM core
+                 * It provide the clock source whose rate is same as MPLL
+                 */
+                .name = "mpll_main",
+                .id = 0,
+                .parent = &mpll_clk,
+                .get_rate = _clk_mpll_main_get_rate
+        }, {
+                /* For i.MX27 TO2, it is the MPLL path 2 of ARM core
+                 * It provide the clock source whose rate is same MPLL * 2/3
+                 */
+                .name = "mpll_main",
+                .id = 1,
+                .parent = &mpll_clk,
+                .get_rate = _clk_mpll_main_get_rate
+        }
+};
+
+static unsigned long get_spll_clk(struct clk *clk)
+{
+        uint32_t reg;
+        unsigned long ref_clk;
+        unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
+        unsigned long long temp;
+
+        ref_clk = clk_get_rate(clk->parent);
+
+        reg = __raw_readl(CCM_SPCTL0);
+        /*TODO: This is TO2 Bug */
+        if (mx27_revision() >= CHIP_REV_2_0)
+                __raw_writel(reg, CCM_SPCTL0);
+
+        pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET;
+        mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET;
+        mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET;
+        mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET;
+
+        mfi = (mfi <= 5) ? 5 : mfi;
+        temp = 2LL * ref_clk * mfn;
+        do_div(temp, mfd + 1);
+        temp = 2LL * ref_clk * mfi + temp;
+        do_div(temp, pdf + 1);
+
+        return (unsigned long)temp;
+}
+
+static struct clk spll_clk = {
+        .name = "spll",
+        .parent = &ckih_clk,
+        .get_rate = get_spll_clk,
+        .enable = _clk_spll_enable,
+        .disable = _clk_spll_disable,
+};
+
+static unsigned long get_cpu_clk(struct clk *clk)
+{
+        u32 div;
+        unsigned long rate;
+
+        if (mx27_revision() >= CHIP_REV_2_0)
+                div = (CSCR() & CCM_CSCR_ARM_MASK) >> CCM_CSCR_ARM_OFFSET;
+        else
+                div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET;
+
+        rate = clk_get_rate(clk->parent);
+        return rate / (div + 1);
+}
+
+static struct clk cpu_clk = {
+        .name = "cpu_clk",
+        .parent = &mpll_main_clk[1],
+        .set_parent = _clk_cpu_set_parent,
+        .round_rate = _clk_cpu_round_rate,
+        .get_rate = get_cpu_clk,
+        .set_rate = _clk_cpu_set_rate,
+};
+
+static unsigned long get_ahb_clk(struct clk *clk)
+{
+        unsigned long rate;
+        unsigned long bclk_pdf;
+
+        if (mx27_revision() >= CHIP_REV_2_0)
+                bclk_pdf = (CSCR() & CCM_CSCR_AHB_MASK)
+                                        >> CCM_CSCR_AHB_OFFSET;
+        else
+                bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK)
+                                        >> CCM_CSCR_BCLK_OFFSET;
+
+        rate = clk_get_rate(clk->parent);
+        return rate / (bclk_pdf + 1);
+}
+
+static struct clk ahb_clk = {
+        .name = "ahb_clk",
+        .parent = &mpll_main_clk[1],
+        .get_rate = get_ahb_clk,
+};
+
+static unsigned long get_ipg_clk(struct clk *clk)
+{
+        unsigned long rate;
+        unsigned long ipg_pdf;
+
+        if (mx27_revision() >= CHIP_REV_2_0)
+                return clk_get_rate(clk->parent);
+        else
+                ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET;
+
+        rate = clk_get_rate(clk->parent);
+        return rate / (ipg_pdf + 1);
+}
+
+static struct clk ipg_clk = {
+        .name = "ipg_clk",
+        .parent = &ahb_clk,
+        .get_rate = get_ipg_clk,
+};
+
+static unsigned long _clk_perclkx_recalc(struct clk *clk)
+{
+        unsigned long perclk_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (clk->id < 0 || clk->id > 3)
+                return 0;
+
+        perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK;
+
+        return parent_rate / (perclk_pdf + 1);
+}
+
+static struct clk per_clk[] = {
+        {
+                .name = "per_clk",
+                .id = 0,
+                .parent = &mpll_main_clk[1],
+                .get_rate = _clk_perclkx_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_PERCLK1_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "per_clk",
+                .id = 1,
+                .parent = &mpll_main_clk[1],
+                .get_rate = _clk_perclkx_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_PERCLK2_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "per_clk",
+                .id = 2,
+                .parent = &mpll_main_clk[1],
+                .round_rate = _clk_perclkx_round_rate,
+                .set_rate = _clk_perclkx_set_rate,
+                .get_rate = _clk_perclkx_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_PERCLK3_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "per_clk",
+                .id = 3,
+                .parent = &mpll_main_clk[1],
+                .round_rate = _clk_perclkx_round_rate,
+                .set_rate = _clk_perclkx_set_rate,
+                .get_rate = _clk_perclkx_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_PERCLK4_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart1_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 0,
+                .parent = &per_clk[0],
+                .secondary = &uart1_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART1_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart2_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 1,
+                .parent = &per_clk[0],
+                .secondary = &uart2_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart3_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 2,
+                .parent = &per_clk[0],
+                .secondary = &uart3_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 2,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART3_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart4_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 3,
+                .parent = &per_clk[0],
+                .secondary = &uart4_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 3,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART4_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart5_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 4,
+                .parent = &per_clk[0],
+                .secondary = &uart5_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 4,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART5_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart6_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 5,
+                .parent = &per_clk[0],
+                .secondary = &uart6_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 5,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART6_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt1_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 0,
+                .parent = &per_clk[0],
+                .secondary = &gpt1_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT1_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt2_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 1,
+                .parent = &per_clk[0],
+                .secondary = &gpt2_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt3_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 2,
+                .parent = &per_clk[0],
+                .secondary = &gpt3_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 2,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT3_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt4_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 3,
+                .parent = &per_clk[0],
+                .secondary = &gpt4_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 3,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT4_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt5_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 4,
+                .parent = &per_clk[0],
+                .secondary = &gpt5_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 4,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT5_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt6_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 5,
+                .parent = &per_clk[0],
+                .secondary = &gpt6_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 5,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT6_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk pwm_clk[] = {
+        {
+                .name = "pwm_clk",
+                .parent = &per_clk[0],
+                .secondary = &pwm_clk[1],
+        }, {
+                .name = "pwm_clk",
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_PWM_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk sdhc1_clk[] = {
+        {
+                .name = "sdhc_clk",
+                .id = 0,
+                .parent = &per_clk[1],
+                .secondary = &sdhc1_clk[1],
+        }, {
+                .name = "sdhc_ipg_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_SDHC1_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk sdhc2_clk[] = {
+        {
+                .name = "sdhc_clk",
+                .id = 1,
+                .parent = &per_clk[1],
+                .secondary = &sdhc2_clk[1],
+        }, {
+                .name = "sdhc_ipg_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_SDHC2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk sdhc3_clk[] = {
+        {
+                .name = "sdhc_clk",
+                .id = 2,
+                .parent = &per_clk[1],
+                .secondary = &sdhc3_clk[1],
+        }, {
+                .name = "sdhc_ipg_clk",
+                .id = 2,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_SDHC3_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk cspi1_clk[] = {
+        {
+                .name = "cspi_clk",
+                .id = 0,
+                .parent = &per_clk[1],
+                .secondary = &cspi1_clk[1],
+        }, {
+                .name = "cspi_ipg_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_CSPI1_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk cspi2_clk[] = {
+        {
+                .name = "cspi_clk",
+                .id = 1,
+                .parent = &per_clk[1],
+                .secondary = &cspi2_clk[1],
+        }, {
+                .name = "cspi_ipg_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_CSPI2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk cspi3_clk[] = {
+        {
+                .name = "cspi_clk",
+                .id = 2,
+                .parent = &per_clk[1],
+                .secondary = &cspi3_clk[1],
+        }, {
+                .name = "cspi_ipg_clk",
+                .id = 2,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_CSPI3_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk lcdc_clk[] = {
+        {
+                .name = "lcdc_clk",
+                .parent = &per_clk[2],
+                .secondary = &lcdc_clk[1],
+                .round_rate = _clk_parent_round_rate,
+                .set_rate = _clk_parent_set_rate,
+        }, {
+                .name = "lcdc_ipg_clk",
+                .parent = &ipg_clk,
+                .secondary = &lcdc_clk[2],
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_LCDC_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "lcdc_ahb_clk",
+                .parent = &ahb_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_HCLK_LCDC_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk csi_clk[] = {
+        {
+                .name = "csi_perclk",
+                .parent = &per_clk[3],
+                .secondary = &csi_clk[1],
+                .round_rate = _clk_parent_round_rate,
+                .set_rate = _clk_parent_set_rate,
+        }, {
+                .name = "csi_ahb_clk",
+                .parent = &ahb_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_HCLK_CSI_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk usb_clk[] = {
+        {
+                .name = "usb_clk",
+                .parent = &spll_clk,
+                .get_rate = _clk_usb_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_USBOTG_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "usb_ahb_clk",
+                .parent = &ahb_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_HCLK_USBOTG_OFFSET,
+                .disable = _clk_disable,
+        }
+};
+
+static struct clk ssi1_clk[] = {
+        {
+                .name = "ssi_clk",
+                .id = 0,
+                .parent = &mpll_main_clk[1],
+                .secondary = &ssi1_clk[1],
+                .get_rate = _clk_ssi1_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_SSI1_BAUD_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "ssi_ipg_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_SSI1_IPG_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk ssi2_clk[] = {
+        {
+                .name = "ssi_clk",
+                .id = 1,
+                .parent = &mpll_main_clk[1],
+                .secondary = &ssi2_clk[1],
+                .get_rate = _clk_ssi2_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_SSI2_BAUD_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "ssi_ipg_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_SSI2_IPG_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk nfc_clk = {
+        .name = "nfc_clk",
+        .parent = &cpu_clk,
+        .get_rate = _clk_nfc_recalc,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR1_NFC_BAUD_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk vpu_clk = {
+        .name = "vpu_clk",
+        .parent = &mpll_main_clk[1],
+        .get_rate = _clk_vpu_recalc,
+        .enable = _clk_vpu_enable,
+        .disable = _clk_vpu_disable,
+};
+
+static struct clk dma_clk = {
+        .name = "dma_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_dma_enable,
+        .disable = _clk_dma_disable,
+};
+
+static struct clk rtic_clk = {
+        .name = "rtic_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_rtic_enable,
+        .disable = _clk_rtic_disable,
+};
+
+static struct clk brom_clk = {
+        .name = "brom_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR1_HCLK_BROM_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk emma_clk = {
+        .name = "emma_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_emma_enable,
+        .disable = _clk_emma_disable,
+};
+
+static struct clk slcdc_clk = {
+        .name = "slcdc_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_slcdc_enable,
+        .disable = _clk_slcdc_disable,
+};
+
+static struct clk fec_clk = {
+        .name = "fec_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_fec_enable,
+        .disable = _clk_fec_disable,
+};
+
+static struct clk emi_clk = {
+        .name = "emi_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR1_HCLK_EMI_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk sahara2_clk = {
+        .name = "sahara_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_sahara2_enable,
+        .disable = _clk_sahara2_disable,
+};
+
+static struct clk ata_clk = {
+        .name = "ata_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR1_HCLK_ATA_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk mstick1_clk = {
+        .name = "mstick1_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_mstick1_enable,
+        .disable = _clk_mstick1_disable,
+};
+
+static struct clk wdog_clk = {
+        .name = "wdog_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR1_WDT_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk gpio_clk = {
+        .name = "gpio_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR0_GPIO_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk i2c_clk[] = {
+        {
+                .name = "i2c_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_I2C1_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "i2c_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_I2C2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk iim_clk = {
+        .name = "iim_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR0,
+        .enable_shift = CCM_PCCR0_IIM_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk kpp_clk = {
+        .name = "kpp_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR0,
+        .enable_shift = CCM_PCCR0_KPP_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk owire_clk = {
+        .name = "owire_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR0,
+        .enable_shift = CCM_PCCR0_OWIRE_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk rtc_clk = {
+        .name = "rtc_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR0,
+        .enable_shift = CCM_PCCR0_RTC_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk scc_clk = {
+        .name = "scc_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR0,
+        .enable_shift = CCM_PCCR0_SCC_OFFSET,
+        .disable = _clk_disable,
+};
+
+static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+        div = parent_rate / rate;
+        if (parent_rate % rate)
+                div++;
+
+        if (div > 8)
+                div = 8;
+
+        return parent_rate / div;
+}
+
+static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+
+        if (div > 8 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+        div--;
+
+        reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKODIV_MASK;
+        reg |= div << CCM_PCDR0_CLKODIV_OFFSET;
+        __raw_writel(reg, CCM_PCDR0);
+
+        return 0;
+}
+
+static unsigned long _clk_clko_recalc(struct clk *clk)
+{
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_CLKODIV_MASK >>
+                CCM_PCDR0_CLKODIV_OFFSET;
+        div++;
+
+        return parent_rate / div;
+}
+
+static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+
+        reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK;
+
+        if (parent == &ckil_clk)
+                reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ckih_clk)
+                reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == mpll_clk.parent)
+                reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == spll_clk.parent)
+                reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &mpll_clk)
+                reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &spll_clk)
+                reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &cpu_clk)
+                reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ahb_clk)
+                reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ipg_clk)
+                reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[0])
+                reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[1])
+                reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[2])
+                reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[3])
+                reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ssi1_clk[0])
+                reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ssi2_clk[0])
+                reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &nfc_clk)
+                reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &mstick1_clk)
+                reg |= 0x11 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &vpu_clk)
+                reg |= 0x12 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &usb_clk[0])
+                reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET;
+        else
+                return -EINVAL;
+
+        __raw_writel(reg, CCM_CCSR);
+
+        return 0;
+}
+
+static int _clk_clko_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(CCM_PCDR0) | CCM_PCDR0_CLKO_EN;
+        __raw_writel(reg, CCM_PCDR0);
+
+        return 0;
+}
+
+static void _clk_clko_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKO_EN;
+        __raw_writel(reg, CCM_PCDR0);
+}
+
+static struct clk clko_clk = {
+        .name = "clko_clk",
+        .get_rate = _clk_clko_recalc,
+        .set_rate = _clk_clko_set_rate,
+        .round_rate = _clk_clko_round_rate,
+        .set_parent = _clk_clko_set_parent,
+        .enable = _clk_clko_enable,
+        .disable = _clk_clko_disable,
+};
+
+static struct clk *mxc_clks[] = {
+        &ckih_clk,
+        &ckil_clk,
+        &mpll_clk,
+        &mpll_main_clk[0],
+        &mpll_main_clk[1],
+        &spll_clk,
+        &cpu_clk,
+        &ahb_clk,
+        &ipg_clk,
+        &per_clk[0],
+        &per_clk[1],
+        &per_clk[2],
+        &per_clk[3],
+        &clko_clk,
+        &uart1_clk[0],
+        &uart1_clk[1],
+        &uart2_clk[0],
+        &uart2_clk[1],
+        &uart3_clk[0],
+        &uart3_clk[1],
+        &uart4_clk[0],
+        &uart4_clk[1],
+        &uart5_clk[0],
+        &uart5_clk[1],
+        &uart6_clk[0],
+        &uart6_clk[1],
+        &gpt1_clk[0],
+        &gpt1_clk[1],
+        &gpt2_clk[0],
+        &gpt2_clk[1],
+        &gpt3_clk[0],
+        &gpt3_clk[1],
+        &gpt4_clk[0],
+        &gpt4_clk[1],
+        &gpt5_clk[0],
+        &gpt5_clk[1],
+        &gpt6_clk[0],
+        &gpt6_clk[1],
+        &pwm_clk[0],
+        &pwm_clk[1],
+        &sdhc1_clk[0],
+        &sdhc1_clk[1],
+        &sdhc2_clk[0],
+        &sdhc2_clk[1],
+        &sdhc3_clk[0],
+        &sdhc3_clk[1],
+        &cspi1_clk[0],
+        &cspi1_clk[1],
+        &cspi2_clk[0],
+        &cspi2_clk[1],
+        &cspi3_clk[0],
+        &cspi3_clk[1],
+        &lcdc_clk[0],
+        &lcdc_clk[1],
+        &lcdc_clk[2],
+        &csi_clk[0],
+        &csi_clk[1],
+        &usb_clk[0],
+        &usb_clk[1],
+        &ssi1_clk[0],
+        &ssi1_clk[1],
+        &ssi2_clk[0],
+        &ssi2_clk[1],
+        &nfc_clk,
+        &vpu_clk,
+        &dma_clk,
+        &rtic_clk,
+        &brom_clk,
+        &emma_clk,
+        &slcdc_clk,
+        &fec_clk,
+        &emi_clk,
+        &sahara2_clk,
+        &ata_clk,
+        &mstick1_clk,
+        &wdog_clk,
+        &gpio_clk,
+        &i2c_clk[0],
+        &i2c_clk[1],
+        &iim_clk,
+        &kpp_clk,
+        &owire_clk,
+        &rtc_clk,
+        &scc_clk,
+};
+
+void __init change_external_low_reference(unsigned long new_ref)
+{
+        external_low_reference = new_ref;
+}
+
+unsigned long __init clk_early_get_timer_rate(void)
+{
+        return clk_get_rate(&per_clk[0]);
+}
+
+static void __init probe_mxc_clocks(void)
+{
+        int i;
+
+        if (mx27_revision() >= CHIP_REV_2_0) {
+                if (CSCR() & 0x8000)
+                        cpu_clk.parent = &mpll_main_clk[0];
+
+                if (!(CSCR() & 0x00800000))
+                        ssi2_clk[0].parent = &spll_clk;
+
+                if (!(CSCR() & 0x00400000))
+                        ssi1_clk[0].parent = &spll_clk;
+
+                if (!(CSCR() & 0x00200000))
+                        vpu_clk.parent = &spll_clk;
+        } else {
+                cpu_clk.parent = &mpll_clk;
+                cpu_clk.set_parent = NULL;
+                cpu_clk.round_rate = NULL;
+                cpu_clk.set_rate = NULL;
+                ahb_clk.parent = &mpll_clk;
+
+                for (i = 0; i < sizeof(per_clk) / sizeof(per_clk[0]); i++)
+                        per_clk[i].parent = &mpll_clk;
+
+                ssi1_clk[0].parent = &mpll_clk;
+                ssi2_clk[0].parent = &mpll_clk;
+
+                vpu_clk.parent = &mpll_clk;
+        }
+}
+
+/*
+ * must be called very early to get information about the
+ * available clock rate when the timer framework starts
+ */
+int __init mxc_clocks_init(unsigned long fref)
+{
+        u32 cscr;
+        struct clk **clkp;
+
+        external_high_reference = fref;
+
+        /* detect clock reference for both system PLL */
+        cscr = CSCR();
+        if (cscr & CCM_CSCR_MCU)
+                mpll_clk.parent = &ckih_clk;
+        else
+                mpll_clk.parent = &ckil_clk;
+
+        if (cscr & CCM_CSCR_SP)
+                spll_clk.parent = &ckih_clk;
+        else
+                spll_clk.parent = &ckil_clk;
+
+        probe_mxc_clocks();
+
+        per_clk[0].enable(&per_clk[0]);
+        gpt1_clk[1].enable(&gpt1_clk[1]);
+
+        for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
+                clk_register(*clkp);
+
+        /* Turn off all possible clocks */
+        __raw_writel(CCM_PCCR0_GPT1_MASK, CCM_PCCR0);
+        __raw_writel(CCM_PCCR1_PERCLK1_MASK | CCM_PCCR1_HCLK_EMI_MASK,
+                     CCM_PCCR1);
+        spll_clk.disable(&spll_clk);
+
+        /* This will propagate to all children and init all the clock rates */
+
+        clk_enable(&emi_clk);
+        clk_enable(&gpio_clk);
+        clk_enable(&iim_clk);
+        clk_enable(&gpt1_clk[0]);
+#ifdef CONFIG_DEBUG_LL_CONSOLE
+        clk_enable(&uart1_clk[0]);
+#endif
+        return 0;
+}
diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-mx2/cpu_imx27.c
new file mode 100644
index 000000000000..d6b5c2e3377f
--- /dev/null
+++ b/arch/arm/mach-mx2/cpu_imx27.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+/*
+ * i.MX27 specific CPU detection code
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+
+#include <asm/hardware.h>
+
+#include "crm_regs.h"
+
+static int cpu_silicon_rev = -1;
+static int cpu_partnumber;
+
+static void query_silicon_parameter(void)
+{
+        u32 val;
+        /*
+         * now we have access to the IO registers. As we need
+         * the silicon revision very early we read it here to
+         * avoid any further hooks
+        */
+        val = __raw_readl(IO_ADDRESS(SYSCTRL_BASE_ADDR) + SYS_CHIP_ID);
+
+        cpu_silicon_rev = (int)(val >> 28);
+        cpu_partnumber = (int)((val >> 12) & 0xFFFF);
+}
+
+/*
+ * Returns:
+ *      the silicon revision of the cpu
+ *      -EINVAL - not a mx27
+ */
+int mx27_revision(void)
+{
+        if (cpu_silicon_rev == -1)
+                query_silicon_parameter();
+
+        if (cpu_partnumber != 0x8821)
+                return -EINVAL;
+
+        return cpu_silicon_rev;
+}
+EXPORT_SYMBOL(mx27_revision);
diff --git a/arch/arm/mach-mx2/crm_regs.h b/arch/arm/mach-mx2/crm_regs.h
new file mode 100644
index 000000000000..a40a9b950ce9
--- /dev/null
+++ b/arch/arm/mach-mx2/crm_regs.h
@@ -0,0 +1,273 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_MX2_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX2_CRM_REGS_H__
+
+#include <asm/arch/hardware.h>
+
+/* Register offsets */
+#define CCM_CSCR                (IO_ADDRESS(CCM_BASE_ADDR) + 0x0)
+#define CCM_MPCTL0              (IO_ADDRESS(CCM_BASE_ADDR) + 0x4)
+#define CCM_MPCTL1              (IO_ADDRESS(CCM_BASE_ADDR) + 0x8)
+#define CCM_SPCTL0              (IO_ADDRESS(CCM_BASE_ADDR) + 0xC)
+#define CCM_SPCTL1              (IO_ADDRESS(CCM_BASE_ADDR) + 0x10)
+#define CCM_OSC26MCTL           (IO_ADDRESS(CCM_BASE_ADDR) + 0x14)
+#define CCM_PCDR0               (IO_ADDRESS(CCM_BASE_ADDR) + 0x18)
+#define CCM_PCDR1               (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c)
+#define CCM_PCCR0               (IO_ADDRESS(CCM_BASE_ADDR) + 0x20)
+#define CCM_PCCR1               (IO_ADDRESS(CCM_BASE_ADDR) + 0x24)
+#define CCM_CCSR                (IO_ADDRESS(CCM_BASE_ADDR) + 0x28)
+#define CCM_PMCTL               (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c)
+#define CCM_PMCOUNT             (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
+#define CCM_WKGDCTL             (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
+
+#define CCM_CSCR_USB_OFFSET     28
+#define CCM_CSCR_USB_MASK       (0x7 << 28)
+#define CCM_CSCR_SD_OFFSET      24
+#define CCM_CSCR_SD_MASK        (0x3 << 24)
+#define CCM_CSCR_SSI2           (1 << 23)
+#define CCM_CSCR_SSI2_OFFSET    23
+#define CCM_CSCR_SSI1           (1 << 22)
+#define CCM_CSCR_SSI1_OFFSET    22
+#define CCM_CSCR_VPU           (1 << 21)
+#define CCM_CSCR_VPU_OFFSET    21
+#define CCM_CSCR_MSHC           (1 << 20)
+#define CCM_CSCR_SPLLRES        (1 << 19)
+#define CCM_CSCR_MPLLRES        (1 << 18)
+#define CCM_CSCR_SP             (1 << 17)
+#define CCM_CSCR_MCU            (1 << 16)
+/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_ARM_SRC        (1 << 15)
+#define CCM_CSCR_ARM_OFFSET     12
+#define CCM_CSCR_ARM_MASK       (0x3 << 12)
+/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_PRESC_OFFSET   13
+#define CCM_CSCR_PRESC_MASK     (0x7 << 13)
+#define CCM_CSCR_BCLK_OFFSET    9
+#define CCM_CSCR_BCLK_MASK      (0xf << 9)
+#define CCM_CSCR_IPDIV_OFFSET   8
+#define CCM_CSCR_IPDIV          (1 << 8)
+/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_AHB_OFFSET     8
+#define CCM_CSCR_AHB_MASK       (0x3 << 8)
+/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_OSC26MDIV      (1 << 4)
+#define CCM_CSCR_OSC26M         (1 << 3)
+#define CCM_CSCR_FPM            (1 << 2)
+#define CCM_CSCR_SPEN           (1 << 1)
+#define CCM_CSCR_MPEN           1
+
+#define CCM_MPCTL0_CPLM         (1 << 31)
+#define CCM_MPCTL0_PD_OFFSET    26
+#define CCM_MPCTL0_PD_MASK      (0xf << 26)
+#define CCM_MPCTL0_MFD_OFFSET   16
+#define CCM_MPCTL0_MFD_MASK     (0x3ff << 16)
+#define CCM_MPCTL0_MFI_OFFSET   10
+#define CCM_MPCTL0_MFI_MASK     (0xf << 10)
+#define CCM_MPCTL0_MFN_OFFSET   0
+#define CCM_MPCTL0_MFN_MASK     0x3ff
+
+#define CCM_MPCTL1_LF           (1 << 15)
+#define CCM_MPCTL1_BRMO         (1 << 6)
+
+#define CCM_SPCTL0_CPLM         (1 << 31)
+#define CCM_SPCTL0_PD_OFFSET    26
+#define CCM_SPCTL0_PD_MASK      (0xf << 26)
+#define CCM_SPCTL0_MFD_OFFSET   16
+#define CCM_SPCTL0_MFD_MASK     (0x3ff << 16)
+#define CCM_SPCTL0_MFI_OFFSET   10
+#define CCM_SPCTL0_MFI_MASK     (0xf << 10)
+#define CCM_SPCTL0_MFN_OFFSET   0
+#define CCM_SPCTL0_MFN_MASK     0x3ff
+
+#define CCM_SPCTL1_LF           (1 << 15)
+#define CCM_SPCTL1_BRMO         (1 << 6)
+
+#define CCM_OSC26MCTL_PEAK_OFFSET       16
+#define CCM_OSC26MCTL_PEAK_MASK         (0x3 << 16)
+#define CCM_OSC26MCTL_AGC_OFFSET        8
+#define CCM_OSC26MCTL_AGC_MASK          (0x3f << 8)
+#define CCM_OSC26MCTL_ANATEST_OFFSET    0
+#define CCM_OSC26MCTL_ANATEST_MASK      0x3f
+
+#define CCM_PCDR0_SSI2BAUDDIV_OFFSET    26
+#define CCM_PCDR0_SSI2BAUDDIV_MASK      (0x3f << 26)
+#define CCM_PCDR0_CLKO_EN               25
+#define CCM_PCDR0_CLKODIV_OFFSET        22
+#define CCM_PCDR0_CLKODIV_MASK          (0x7 << 22)
+#define CCM_PCDR0_SSI1BAUDDIV_OFFSET    16
+#define CCM_PCDR0_SSI1BAUDDIV_MASK      (0x3f << 16)
+/*The difinition for i.MX27 TO2*/
+#define CCM_PCDR0_VPUDIV2_OFFSET        10
+#define CCM_PCDR0_VPUDIV2_MASK          (0x3f << 10)
+#define CCM_PCDR0_NFCDIV2_OFFSET         6
+#define CCM_PCDR0_NFCDIV2_MASK           (0xf << 6)
+#define CCM_PCDR0_MSHCDIV2_MASK          0x3f
+/*The difinition for i.MX27 TO2*/
+#define CCM_PCDR0_NFCDIV_OFFSET         12
+#define CCM_PCDR0_NFCDIV_MASK           (0xf << 12)
+#define CCM_PCDR0_VPUDIV_OFFSET        8
+#define CCM_PCDR0_VPUDIV_MASK          (0xf << 8)
+#define CCM_PCDR0_MSHCDIV_OFFSET        0
+#define CCM_PCDR0_MSHCDIV_MASK          0x1f
+
+#define CCM_PCDR1_PERDIV4_OFFSET        24
+#define CCM_PCDR1_PERDIV4_MASK          (0x3f << 24)
+#define CCM_PCDR1_PERDIV3_OFFSET        16
+#define CCM_PCDR1_PERDIV3_MASK          (0x3f << 16)
+#define CCM_PCDR1_PERDIV2_OFFSET        8
+#define CCM_PCDR1_PERDIV2_MASK          (0x3f << 8)
+#define CCM_PCDR1_PERDIV1_OFFSET        0
+#define CCM_PCDR1_PERDIV1_MASK          0x3f
+
+#define CCM_PCCR0_CSPI1_OFFSET          31
+#define CCM_PCCR0_CSPI1_MASK            (1 << 31)
+#define CCM_PCCR0_CSPI2_OFFSET          30
+#define CCM_PCCR0_CSPI2_MASK            (1 << 30)
+#define CCM_PCCR0_CSPI3_OFFSET          29
+#define CCM_PCCR0_CSPI3_MASK            (1 << 29)
+#define CCM_PCCR0_DMA_OFFSET            28
+#define CCM_PCCR0_DMA_MASK              (1 << 28)
+#define CCM_PCCR0_EMMA_OFFSET           27
+#define CCM_PCCR0_EMMA_MASK             (1 << 27)
+#define CCM_PCCR0_FEC_OFFSET            26
+#define CCM_PCCR0_FEC_MASK              (1 << 26)
+#define CCM_PCCR0_GPIO_OFFSET           25
+#define CCM_PCCR0_GPIO_MASK             (1 << 25)
+#define CCM_PCCR0_GPT1_OFFSET           24
+#define CCM_PCCR0_GPT1_MASK             (1 << 24)
+#define CCM_PCCR0_GPT2_OFFSET           23
+#define CCM_PCCR0_GPT2_MASK             (1 << 23)
+#define CCM_PCCR0_GPT3_OFFSET           22
+#define CCM_PCCR0_GPT3_MASK             (1 << 22)
+#define CCM_PCCR0_GPT4_OFFSET           21
+#define CCM_PCCR0_GPT4_MASK             (1 << 21)
+#define CCM_PCCR0_GPT5_OFFSET           20
+#define CCM_PCCR0_GPT5_MASK             (1 << 20)
+#define CCM_PCCR0_GPT6_OFFSET           19
+#define CCM_PCCR0_GPT6_MASK             (1 << 19)
+#define CCM_PCCR0_I2C1_OFFSET           18
+#define CCM_PCCR0_I2C1_MASK             (1 << 18)
+#define CCM_PCCR0_I2C2_OFFSET           17
+#define CCM_PCCR0_I2C2_MASK             (1 << 17)
+#define CCM_PCCR0_IIM_OFFSET            16
+#define CCM_PCCR0_IIM_MASK              (1 << 16)
+#define CCM_PCCR0_KPP_OFFSET            15
+#define CCM_PCCR0_KPP_MASK              (1 << 15)
+#define CCM_PCCR0_LCDC_OFFSET           14
+#define CCM_PCCR0_LCDC_MASK             (1 << 14)
+#define CCM_PCCR0_MSHC_OFFSET           13
+#define CCM_PCCR0_MSHC_MASK             (1 << 13)
+#define CCM_PCCR0_OWIRE_OFFSET          12
+#define CCM_PCCR0_OWIRE_MASK            (1 << 12)
+#define CCM_PCCR0_PWM_OFFSET            11
+#define CCM_PCCR0_PWM_MASK              (1 << 11)
+#define CCM_PCCR0_RTC_OFFSET            9
+#define CCM_PCCR0_RTC_MASK              (1 << 9)
+#define CCM_PCCR0_RTIC_OFFSET           8
+#define CCM_PCCR0_RTIC_MASK             (1 << 8)
+#define CCM_PCCR0_SAHARA_OFFSET         7
+#define CCM_PCCR0_SAHARA_MASK           (1 << 7)
+#define CCM_PCCR0_SCC_OFFSET            6
+#define CCM_PCCR0_SCC_MASK              (1 << 6)
+#define CCM_PCCR0_SDHC1_OFFSET          5
+#define CCM_PCCR0_SDHC1_MASK            (1 << 5)
+#define CCM_PCCR0_SDHC2_OFFSET          4
+#define CCM_PCCR0_SDHC2_MASK            (1 << 4)
+#define CCM_PCCR0_SDHC3_OFFSET          3
+#define CCM_PCCR0_SDHC3_MASK            (1 << 3)
+#define CCM_PCCR0_SLCDC_OFFSET          2
+#define CCM_PCCR0_SLCDC_MASK            (1 << 2)
+#define CCM_PCCR0_SSI1_IPG_OFFSET       1
+#define CCM_PCCR0_SSI1_IPG_MASK         (1 << 1)
+#define CCM_PCCR0_SSI2_IPG_OFFSET       0
+#define CCM_PCCR0_SSI2_IPG_MASK         (1 << 0)
+
+#define CCM_PCCR1_UART1_OFFSET          31
+#define CCM_PCCR1_UART1_MASK            (1 << 31)
+#define CCM_PCCR1_UART2_OFFSET          30
+#define CCM_PCCR1_UART2_MASK            (1 << 30)
+#define CCM_PCCR1_UART3_OFFSET          29
+#define CCM_PCCR1_UART3_MASK            (1 << 29)
+#define CCM_PCCR1_UART4_OFFSET          28
+#define CCM_PCCR1_UART4_MASK            (1 << 28)
+#define CCM_PCCR1_UART5_OFFSET          27
+#define CCM_PCCR1_UART5_MASK            (1 << 27)
+#define CCM_PCCR1_UART6_OFFSET          26
+#define CCM_PCCR1_UART6_MASK            (1 << 26)
+#define CCM_PCCR1_USBOTG_OFFSET         25
+#define CCM_PCCR1_USBOTG_MASK           (1 << 25)
+#define CCM_PCCR1_WDT_OFFSET            24
+#define CCM_PCCR1_WDT_MASK              (1 << 24)
+#define CCM_PCCR1_HCLK_ATA_OFFSET       23
+#define CCM_PCCR1_HCLK_ATA_MASK         (1 << 23)
+#define CCM_PCCR1_HCLK_BROM_OFFSET      22
+#define CCM_PCCR1_HCLK_BROM_MASK        (1 << 22)
+#define CCM_PCCR1_HCLK_CSI_OFFSET       21
+#define CCM_PCCR1_HCLK_CSI_MASK         (1 << 21)
+#define CCM_PCCR1_HCLK_DMA_OFFSET       20
+#define CCM_PCCR1_HCLK_DMA_MASK         (1 << 20)
+#define CCM_PCCR1_HCLK_EMI_OFFSET       19
+#define CCM_PCCR1_HCLK_EMI_MASK         (1 << 19)
+#define CCM_PCCR1_HCLK_EMMA_OFFSET      18
+#define CCM_PCCR1_HCLK_EMMA_MASK        (1 << 18)
+#define CCM_PCCR1_HCLK_FEC_OFFSET       17
+#define CCM_PCCR1_HCLK_FEC_MASK         (1 << 17)
+#define CCM_PCCR1_HCLK_VPU_OFFSET       16
+#define CCM_PCCR1_HCLK_VPU_MASK         (1 << 16)
+#define CCM_PCCR1_HCLK_LCDC_OFFSET      15
+#define CCM_PCCR1_HCLK_LCDC_MASK        (1 << 15)
+#define CCM_PCCR1_HCLK_RTIC_OFFSET      14
+#define CCM_PCCR1_HCLK_RTIC_MASK        (1 << 14)
+#define CCM_PCCR1_HCLK_SAHARA_OFFSET    13
+#define CCM_PCCR1_HCLK_SAHARA_MASK      (1 << 13)
+#define CCM_PCCR1_HCLK_SLCDC_OFFSET     12
+#define CCM_PCCR1_HCLK_SLCDC_MASK       (1 << 12)
+#define CCM_PCCR1_HCLK_USBOTG_OFFSET    11
+#define CCM_PCCR1_HCLK_USBOTG_MASK      (1 << 11)
+#define CCM_PCCR1_PERCLK1_OFFSET        10
+#define CCM_PCCR1_PERCLK1_MASK          (1 << 10)
+#define CCM_PCCR1_PERCLK2_OFFSET        9
+#define CCM_PCCR1_PERCLK2_MASK          (1 << 9)
+#define CCM_PCCR1_PERCLK3_OFFSET        8
+#define CCM_PCCR1_PERCLK3_MASK          (1 << 8)
+#define CCM_PCCR1_PERCLK4_OFFSET        7
+#define CCM_PCCR1_PERCLK4_MASK          (1 << 7)
+#define CCM_PCCR1_VPU_BAUD_OFFSET       6
+#define CCM_PCCR1_VPU_BAUD_MASK         (1 << 6)
+#define CCM_PCCR1_SSI1_BAUD_OFFSET      5
+#define CCM_PCCR1_SSI1_BAUD_MASK        (1 << 5)
+#define CCM_PCCR1_SSI2_BAUD_OFFSET      4
+#define CCM_PCCR1_SSI2_BAUD_MASK        (1 << 4)
+#define CCM_PCCR1_NFC_BAUD_OFFSET       3
+#define CCM_PCCR1_NFC_BAUD_MASK         (1 << 3)
+#define CCM_PCCR1_MSHC_BAUD_OFFSET      2
+#define CCM_PCCR1_MSHC_BAUD_MASK        (1 << 2)
+
+#define CCM_CCSR_32KSR          (1 << 15)
+#define CCM_CCSR_CLKMODE1       (1 << 9)
+#define CCM_CCSR_CLKMODE0       (1 << 8)
+#define CCM_CCSR_CLKOSEL_OFFSET 0
+#define CCM_CCSR_CLKOSEL_MASK   0x1f
+
+#define SYS_FMCR                0x14    /*  Functional Muxing Control Reg */
+#define SYS_CHIP_ID             0x00    /* The offset of CHIP ID register */
+
+#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
new file mode 100644
index 000000000000..a1f44c3c5315
--- /dev/null
+++ b/arch/arm/mach-mx2/devices.c
@@ -0,0 +1,231 @@
+/*
+ * Author: MontaVista Software, Inc.
+ *       <source@mvista.com>
+ *
+ * Based on the OMAP devices.c
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+
+#include <asm/hardware.h>
+
+/*
+ * Resource definition for the MXC IrDA
+ */
+static struct resource mxc_irda_resources[] = {
+        [0] = {
+                .start   = UART3_BASE_ADDR,
+                .end     = UART3_BASE_ADDR + SZ_4K - 1,
+                .flags   = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start   = MXC_INT_UART3,
+                .end     = MXC_INT_UART3,
+                .flags   = IORESOURCE_IRQ,
+        },
+};
+
+/* Platform Data for MXC IrDA */
+struct platform_device mxc_irda_device = {
+        .name = "mxc_irda",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_irda_resources),
+        .resource = mxc_irda_resources,
+};
+
+/*
+ * General Purpose Timer
+ * - i.MX1: 2 timer (slighly different register handling)
+ * - i.MX21: 3 timer
+ * - i.MX27: 6 timer
+ */
+
+/* We use gpt0 as system timer, so do not add a device for this one */
+
+static struct resource timer1_resources[] = {
+        [0] = {
+                .start  = GPT2_BASE_ADDR,
+                .end    = GPT2_BASE_ADDR + 0x17,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start   = MXC_INT_GPT2,
+                .end     = MXC_INT_GPT2,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_gpt1 = {
+        .name = "imx_gpt",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(timer1_resources),
+        .resource = timer1_resources
+};
+
+static struct resource timer2_resources[] = {
+        [0] = {
+                .start  = GPT3_BASE_ADDR,
+                .end    = GPT3_BASE_ADDR + 0x17,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start   = MXC_INT_GPT3,
+                .end     = MXC_INT_GPT3,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_gpt2 = {
+        .name = "imx_gpt",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(timer2_resources),
+        .resource = timer2_resources
+};
+
+#ifdef CONFIG_MACH_MX27
+static struct resource timer3_resources[] = {
+        [0] = {
+                .start  = GPT4_BASE_ADDR,
+                .end    = GPT4_BASE_ADDR + 0x17,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start   = MXC_INT_GPT4,
+                .end     = MXC_INT_GPT4,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_gpt3 = {
+        .name = "imx_gpt",
+        .id = 3,
+        .num_resources = ARRAY_SIZE(timer3_resources),
+        .resource = timer3_resources
+};
+
+static struct resource timer4_resources[] = {
+        [0] = {
+                .start  = GPT5_BASE_ADDR,
+                .end    = GPT5_BASE_ADDR + 0x17,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start   = MXC_INT_GPT5,
+                .end     = MXC_INT_GPT5,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_gpt4 = {
+        .name = "imx_gpt",
+        .id = 4,
+        .num_resources = ARRAY_SIZE(timer4_resources),
+        .resource = timer4_resources
+};
+
+static struct resource timer5_resources[] = {
+        [0] = {
+                .start  = GPT6_BASE_ADDR,
+                .end    = GPT6_BASE_ADDR + 0x17,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start   = MXC_INT_GPT6,
+                .end     = MXC_INT_GPT6,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_gpt5 = {
+        .name = "imx_gpt",
+        .id = 5,
+        .num_resources = ARRAY_SIZE(timer5_resources),
+        .resource = timer5_resources
+};
+#endif
+
+/*
+ * Watchdog:
+ * - i.MX1
+ * - i.MX21
+ * - i.MX27
+ */
+static struct resource mxc_wdt_resources[] = {
+        {
+                .start  = WDOG_BASE_ADDR,
+                .end    = WDOG_BASE_ADDR + 0x30,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device mxc_wdt = {
+        .name = "mxc_wdt",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_wdt_resources),
+        .resource = mxc_wdt_resources,
+};
+
+/* GPIO port description */
+static struct mxc_gpio_port imx_gpio_ports[] = {
+        [0] = {
+                .chip.label = "gpio-0",
+                .irq = MXC_INT_GPIO,
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0),
+                .virtual_irq_start = MXC_MAX_INT_LINES,
+        },
+        [1] = {
+                .chip.label = "gpio-1",
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1),
+                .virtual_irq_start = MXC_MAX_INT_LINES + 32,
+        },
+        [2] = {
+                .chip.label = "gpio-2",
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2),
+                .virtual_irq_start = MXC_MAX_INT_LINES + 64,
+        },
+        [3] = {
+                .chip.label = "gpio-3",
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3),
+                .virtual_irq_start = MXC_MAX_INT_LINES + 96,
+        },
+        [4] = {
+                .chip.label = "gpio-4",
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4),
+                .virtual_irq_start = MXC_MAX_INT_LINES + 128,
+        },
+        [5] = {
+                .chip.label = "gpio-5",
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5),
+                .virtual_irq_start = MXC_MAX_INT_LINES + 160,
+        }
+};
+
+int __init mxc_register_gpios(void)
+{
+        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
+}
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/generic.c
new file mode 100644
index 000000000000..07875cf00de9
--- /dev/null
+++ b/arch/arm/mach-mx2/generic.c
@@ -0,0 +1,74 @@
+/*
+ * generic.c
+ *
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <asm/hardware.h>
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+
+/* MX27 memory map definition */
+static struct map_desc mxc_io_desc[] __initdata = {
+        /*
+         * this fixed mapping covers:
+         * - AIPI1
+         * - AIPI2
+         * - AITC
+         * - ROM Patch
+         * - and some reserved space
+         */
+        {
+                .virtual = AIPI_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(AIPI_BASE_ADDR),
+                .length = AIPI_SIZE,
+                .type = MT_DEVICE
+        },
+        /*
+         * this fixed mapping covers:
+         * - CSI
+         * - ATA
+         */
+        {
+                .virtual = SAHB1_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(SAHB1_BASE_ADDR),
+                .length = SAHB1_SIZE,
+                .type = MT_DEVICE
+        },
+        /*
+         * this fixed mapping covers:
+         * - EMI
+         */
+        {
+                .virtual = X_MEMC_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
+                .length = X_MEMC_SIZE,
+                .type = MT_DEVICE
+        }
+};
+
+/*
+ * Initialize the memory map. It is called during the
+ * system startup to create static physical to virtual
+ * memory map for the IO modules.
+ */
+void __init mxc_map_io(void)
+{
+        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+}
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
new file mode 100644
index 000000000000..a9ff01fff137
--- /dev/null
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -0,0 +1,304 @@
+/*
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <asm/arch/common.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/imx-uart.h>
+#include <asm/arch/iomux-mx1-mx2.h>
+#include <asm/arch/board-mx27ads.h>
+
+/* ADS's NOR flash */
+static struct physmap_flash_data mx27ads_flash_data = {
+        .width = 2,
+};
+
+static struct resource mx27ads_flash_resource = {
+        .start = 0xc0000000,
+        .end = 0xc0000000 + 0x02000000 - 1,
+        .flags = IORESOURCE_MEM,
+
+};
+
+static struct platform_device mx27ads_nor_mtd_device = {
+        .name = "physmap-flash",
+        .id = 0,
+        .dev = {
+                .platform_data = &mx27ads_flash_data,
+        },
+        .num_resources = 1,
+        .resource = &mx27ads_flash_resource,
+};
+
+static int mxc_uart0_pins[] = {
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS
+};
+
+static int uart_mxc_port0_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
+                        ARRAY_SIZE(mxc_uart0_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART0");
+}
+
+static int uart_mxc_port0_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
+                        ARRAY_SIZE(mxc_uart0_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART0");
+}
+
+static int mxc_uart1_pins[] = {
+        PE3_PF_UART2_CTS,
+        PE4_PF_UART2_RTS,
+        PE6_PF_UART2_TXD,
+        PE7_PF_UART2_RXD
+};
+
+static int uart_mxc_port1_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
+                        ARRAY_SIZE(mxc_uart1_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART1");
+}
+
+static int uart_mxc_port1_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
+                        ARRAY_SIZE(mxc_uart1_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART1");
+}
+
+static int mxc_uart2_pins[] = {
+        PE8_PF_UART3_TXD,
+        PE9_PF_UART3_RXD,
+        PE10_PF_UART3_CTS,
+        PE11_PF_UART3_RTS
+};
+
+static int uart_mxc_port2_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
+                        ARRAY_SIZE(mxc_uart2_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART2");
+}
+
+static int uart_mxc_port2_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
+                        ARRAY_SIZE(mxc_uart2_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART2");
+}
+
+static int mxc_uart3_pins[] = {
+        PB26_AF_UART4_RTS,
+        PB28_AF_UART4_TXD,
+        PB29_AF_UART4_CTS,
+        PB31_AF_UART4_RXD
+};
+
+static int uart_mxc_port3_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart3_pins,
+                        ARRAY_SIZE(mxc_uart3_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART3");
+}
+
+static int uart_mxc_port3_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart3_pins,
+                        ARRAY_SIZE(mxc_uart3_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART3");
+}
+
+static int mxc_uart4_pins[] = {
+        PB18_AF_UART5_TXD,
+        PB19_AF_UART5_RXD,
+        PB20_AF_UART5_CTS,
+        PB21_AF_UART5_RTS
+};
+
+static int uart_mxc_port4_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart4_pins,
+                        ARRAY_SIZE(mxc_uart4_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART4");
+}
+
+static int uart_mxc_port4_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart4_pins,
+                        ARRAY_SIZE(mxc_uart4_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART4");
+}
+
+static int mxc_uart5_pins[] = {
+        PB10_AF_UART6_TXD,
+        PB12_AF_UART6_CTS,
+        PB11_AF_UART6_RXD,
+        PB13_AF_UART6_RTS
+};
+
+static int uart_mxc_port5_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
+                        ARRAY_SIZE(mxc_uart5_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART5");
+}
+
+static int uart_mxc_port5_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
+                        ARRAY_SIZE(mxc_uart5_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART5");
+}
+
+static struct platform_device *platform_devices[] __initdata = {
+        &mx27ads_nor_mtd_device,
+};
+
+static int mxc_fec_pins[] = {
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_CLR,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN
+};
+
+static void gpio_fec_active(void)
+{
+        mxc_gpio_setup_multiple_pins(mxc_fec_pins,
+                        ARRAY_SIZE(mxc_fec_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "FEC");
+}
+
+static void gpio_fec_inactive(void)
+{
+        mxc_gpio_setup_multiple_pins(mxc_fec_pins,
+                        ARRAY_SIZE(mxc_fec_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "FEC");
+}
+
+static struct imxuart_platform_data uart_pdata[] = {
+        {
+                .init = uart_mxc_port0_init,
+                .exit = uart_mxc_port0_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port1_init,
+                .exit = uart_mxc_port1_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port2_init,
+                .exit = uart_mxc_port2_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port3_init,
+                .exit = uart_mxc_port3_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port4_init,
+                .exit = uart_mxc_port4_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port5_init,
+                .exit = uart_mxc_port5_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        },
+};
+
+static void __init mx27ads_board_init(void)
+{
+        int i;
+
+        gpio_fec_active();
+
+        for (i = 0; i < 6; i++)
+                imx_init_uart(i, &uart_pdata[i]);
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+
+static void __init mx27ads_timer_init(void)
+{
+        unsigned long fref = 26000000;
+
+        if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
+                fref = 27000000;
+
+        mxc_clocks_init(fref);
+        mxc_timer_init("gpt_clk.0");
+}
+
+struct sys_timer mx27ads_timer = {
+        .init   = mx27ads_timer_init,
+};
+
+static struct map_desc mx27ads_io_desc[] __initdata = {
+        {
+                .virtual = PBC_BASE_ADDRESS,
+                .pfn = __phys_to_pfn(CS4_BASE_ADDR),
+                .length = SZ_1M,
+                .type = MT_DEVICE,
+        },
+};
+
+void __init mx27ads_map_io(void)
+{
+        mxc_map_io();
+        iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
+}
+
+MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
+        /* maintainer: Freescale Semiconductor, Inc. */
+        .phys_io        = AIPI_BASE_ADDR,
+        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx27ads_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = mx27ads_board_init,
+        .timer          = &mx27ads_timer,
+MACHINE_END
+
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
new file mode 100644
index 000000000000..a9a28f58e714
--- /dev/null
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/arch/common.h>
+#include <asm/hardware.h>
+#include <asm/arch/iomux-mx1-mx2.h>
+#include <asm/mach/time.h>
+#include <asm/arch/imx-uart.h>
+#include <asm/arch/board-pcm038.h>
+
+/*
+ * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
+ * 16 bit width
+ */
+static struct physmap_flash_data pcm038_flash_data = {
+        .width = 2,
+};
+
+static struct resource pcm038_flash_resource = {
+        .start = 0xc0000000,
+        .end   = 0xc1ffffff,
+        .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device pcm038_nor_mtd_device = {
+        .name = "physmap-flash",
+        .id = 0,
+        .dev = {
+                .platform_data = &pcm038_flash_data,
+        },
+        .num_resources = 1,
+        .resource = &pcm038_flash_resource,
+};
+
+static int mxc_uart0_pins[] = {
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS
+};
+
+static int uart_mxc_port0_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
+                        ARRAY_SIZE(mxc_uart0_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART0");
+}
+
+static int uart_mxc_port0_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
+                        ARRAY_SIZE(mxc_uart0_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART0");
+}
+
+static int mxc_uart1_pins[] = {
+        PE3_PF_UART2_CTS,
+        PE4_PF_UART2_RTS,
+        PE6_PF_UART2_TXD,
+        PE7_PF_UART2_RXD
+};
+
+static int uart_mxc_port1_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
+                        ARRAY_SIZE(mxc_uart1_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART1");
+}
+
+static int uart_mxc_port1_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
+                        ARRAY_SIZE(mxc_uart1_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART1");
+}
+
+static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS,
+                                PE9_PF_UART3_RXD,
+                                PE10_PF_UART3_CTS,
+                                PE9_PF_UART3_RXD };
+
+static int uart_mxc_port2_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
+                        ARRAY_SIZE(mxc_uart2_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART2");
+}
+
+static int uart_mxc_port2_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
+                        ARRAY_SIZE(mxc_uart2_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART2");
+}
+
+static struct imxuart_platform_data uart_pdata[] = {
+        {
+                .init = uart_mxc_port0_init,
+                .exit = uart_mxc_port0_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port1_init,
+                .exit = uart_mxc_port1_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port2_init,
+                .exit = uart_mxc_port2_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        },
+};
+
+static int mxc_fec_pins[] = {
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_CLR,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN
+};
+
+static void gpio_fec_active(void)
+{
+        mxc_gpio_setup_multiple_pins(mxc_fec_pins,
+                        ARRAY_SIZE(mxc_fec_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "FEC");
+}
+
+static void gpio_fec_inactive(void)
+{
+        mxc_gpio_setup_multiple_pins(mxc_fec_pins,
+                        ARRAY_SIZE(mxc_fec_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "FEC");
+}
+
+static struct platform_device *platform_devices[] __initdata = {
+        &pcm038_nor_mtd_device,
+};
+
+static void __init pcm038_init(void)
+{
+        int i;
+        gpio_fec_active();
+
+        for (i = 0; i < 3; i++)
+                imx_init_uart(i, &uart_pdata[i]);
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+#ifdef CONFIG_MACH_PCM970_BASEBOARD
+        pcm970_baseboard_init();
+#endif
+}
+
+static void __init pcm038_timer_init(void)
+{
+        mxc_clocks_init(26000000);
+        mxc_timer_init("gpt_clk.0");
+}
+
+struct sys_timer pcm038_timer = {
+        .init = pcm038_timer_init,
+};
+
+MACHINE_START(PCM038, "phyCORE-i.MX27")
+        .phys_io        = AIPI_BASE_ADDR,
+        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mxc_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = pcm038_init,
+        .timer          = &pcm038_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c
new file mode 100644
index 000000000000..028ac4d33684
--- /dev/null
+++ b/arch/arm/mach-mx2/pcm970-baseboard.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+/*
+ * system init for baseboard usage. Will be called by pcm038 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init pcm970_baseboard_init(void)
+{
+}
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c
new file mode 100644
index 000000000000..570c02b8e5df
--- /dev/null
+++ b/arch/arm/mach-mx2/serial.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <asm/hardware.h>
+#include <asm/arch/imx-uart.h>
+
+static struct resource uart0[] = {
+        {
+                .start = UART1_BASE_ADDR,
+                .end = UART1_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART1,
+                .end = MXC_INT_UART1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device0 = {
+        .name = "imx-uart",
+        .id = 0,
+        .resource = uart0,
+        .num_resources = ARRAY_SIZE(uart0),
+};
+
+static struct resource uart1[] = {
+        {
+                .start = UART2_BASE_ADDR,
+                .end = UART2_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART2,
+                .end = MXC_INT_UART2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device1 = {
+        .name = "imx-uart",
+        .id = 1,
+        .resource = uart1,
+        .num_resources = ARRAY_SIZE(uart1),
+};
+
+static struct resource uart2[] = {
+        {
+                .start = UART3_BASE_ADDR,
+                .end = UART3_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART3,
+                .end = MXC_INT_UART3,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device2 = {
+        .name = "imx-uart",
+        .id = 2,
+        .resource = uart2,
+        .num_resources = ARRAY_SIZE(uart2),
+};
+
+static struct resource uart3[] = {
+        {
+                .start = UART4_BASE_ADDR,
+                .end = UART4_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART4,
+                .end = MXC_INT_UART4,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device3 = {
+        .name = "imx-uart",
+        .id = 3,
+        .resource = uart3,
+        .num_resources = ARRAY_SIZE(uart3),
+};
+
+static struct resource uart4[] = {
+        {
+                .start = UART5_BASE_ADDR,
+                .end = UART5_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART5,
+                .end = MXC_INT_UART5,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device4 = {
+        .name = "imx-uart",
+        .id = 4,
+        .resource = uart4,
+        .num_resources = ARRAY_SIZE(uart4),
+};
+
+static struct resource uart5[] = {
+        {
+                .start = UART6_BASE_ADDR,
+                .end = UART6_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART6,
+                .end = MXC_INT_UART6,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device5 = {
+        .name = "imx-uart",
+        .id = 5,
+        .resource = uart5,
+        .num_resources = ARRAY_SIZE(uart5),
+};
+
+/*
+ * Register only those UARTs that physically exists
+ */
+int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata)
+{
+        switch (uart_no) {
+        case 0:
+                mxc_uart_device0.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device0);
+                break;
+        case 1:
+                mxc_uart_device1.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device1);
+                break;
+#ifndef CONFIG_MXC_IRDA
+        case 2:
+                mxc_uart_device2.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device2);
+                break;
+#endif
+        case 3:
+                mxc_uart_device3.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device3);
+                break;
+        case 4:
+                mxc_uart_device4.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device4);
+                break;
+        case 5:
+                mxc_uart_device5.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device5);
+                break;
+        default:
+                return -ENODEV;
+        }
+
+        return 0;
+}
diff --git a/arch/arm/mach-mx2/system.c b/arch/arm/mach-mx2/system.c
new file mode 100644
index 000000000000..99304645299d
--- /dev/null
+++ b/arch/arm/mach-mx2/system.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/arch/hardware.h>
+#include <asm/proc-fns.h>
+#include <asm/system.h>
+
+/*
+ * Put the CPU into idle mode. It is called by default_idle()
+ * in process.c file.
+ */
+void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks.
+         */
+        cpu_do_idle();
+}
+
+#define WDOG_WCR_REG                    IO_ADDRESS(WDOG_BASE_ADDR)
+#define WDOG_WCR_SRS                    (1 << 4)
+
+/*
+ * Reset the system. It is called by machine_restart().
+ */
+void arch_reset(char mode)
+{
+        struct clk *clk;
+
+        clk = clk_get(NULL, "wdog_clk");
+        if (!clk) {
+                printk(KERN_ERR"Cannot activate the watchdog. Giving up\n");
+                return;
+        }
+
+        clk_enable(clk);
+
+        /* Assert SRS signal */
+        __raw_writew(__raw_readw(WDOG_WCR_REG) & ~WDOG_WCR_SRS, WDOG_WCR_REG);
+}
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 5fe8606cac08..db9431dee1b4 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -8,5 +8,18 @@ config MACH_MX31ADS
           Include support for MX31ADS platform. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_PCM037
+        bool "Support Phytec pcm037 platforms"
+        help
+          Include support for Phytec pcm037 platform. This includes
+          specific configurations for the board and its peripherals.
+
+config MACH_MX31LITE
+        bool "Support MX31 LITEKIT (LogicPD)"
+        default n
+        help
+          Include support for MX31 LITEKIT platform. This includes specific
+          configurations for the board and its peripherals.
+
 endmenu
 
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index cbec997f332a..8b21abb71fb0 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -4,5 +4,7 @@
 
 # Object file lists.
 
-obj-y                   := mm.o time.o
+obj-y                   := mm.o clock.o devices.o iomux.o
 obj-$(CONFIG_MACH_MX31ADS)      += mx31ads.o
+obj-$(CONFIG_MACH_MX31LITE)     += mx31lite.o
+obj-$(CONFIG_MACH_PCM037)       += pcm037.o
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
new file mode 100644
index 000000000000..2f3635943e70
--- /dev/null
+++ b/arch/arm/mach-mx3/clock.c
@@ -0,0 +1,1147 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <asm/arch/clock.h>
+#include <asm/div64.h>
+
+#include "crm_regs.h"
+
+#define PRE_DIV_MIN_FREQ    10000000 /* Minimum Frequency after Predivider */
+
+static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
+{
+        u32 min_pre, temp_pre, old_err, err;
+
+        if (div >= 512) {
+                *pre = 8;
+                *post = 64;
+        } else if (div >= 64) {
+                min_pre = (div - 1) / 64 + 1;
+                old_err = 8;
+                for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
+                        err = div % temp_pre;
+                        if (err == 0) {
+                                *pre = temp_pre;
+                                break;
+                        }
+                        err = temp_pre - err;
+                        if (err < old_err) {
+                                old_err = err;
+                                *pre = temp_pre;
+                        }
+                }
+                *post = (div + *pre - 1) / *pre;
+        } else if (div <= 8) {
+                *pre = div;
+                *post = 1;
+        } else {
+                *pre = 1;
+                *post = div;
+        }
+}
+
+static struct clk mcu_pll_clk;
+static struct clk mcu_main_clk;
+static struct clk usb_pll_clk;
+static struct clk serial_pll_clk;
+static struct clk ipg_clk;
+static struct clk ckih_clk;
+static struct clk ahb_clk;
+
+static int _clk_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 3 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void _clk_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(3 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static void _clk_emi_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(3 << clk->enable_shift);
+        reg |= (1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+        signed long pd = 1;     /* Pre-divider */
+        signed long mfi;        /* Multiplication Factor (Integer part) */
+        signed long mfn;        /* Multiplication Factor (Integer part) */
+        signed long mfd;        /* Multiplication Factor (Denominator Part) */
+        signed long tmp;
+        u32 ref_freq = clk_get_rate(clk->parent);
+
+        while (((ref_freq / pd) * 10) > rate)
+                pd++;
+
+        if ((ref_freq / pd) < PRE_DIV_MIN_FREQ)
+                return -EINVAL;
+
+        /* the ref_freq/2 in the following is to round up */
+        mfi = (((rate / 2) * pd) + (ref_freq / 2)) / ref_freq;
+        if (mfi < 5 || mfi > 15)
+                return -EINVAL;
+
+        /* pick a mfd value that will work
+         * then solve for mfn */
+        mfd = ref_freq / 50000;
+
+        /*
+         *          pll_freq * pd * mfd
+         *   mfn = --------------------  -  (mfi * mfd)
+         *           2 * ref_freq
+         */
+        /* the tmp/2 is for rounding */
+        tmp = ref_freq / 10000;
+        mfn =
+            ((((((rate / 2) + (tmp / 2)) / tmp) * pd) * mfd) / 10000) -
+            (mfi * mfd);
+
+        mfn = mfn & 0x3ff;
+        pd--;
+        mfd--;
+
+        /* Change the Pll value */
+        reg = (mfi << MXC_CCM_PCTL_MFI_OFFSET) |
+            (mfn << MXC_CCM_PCTL_MFN_OFFSET) |
+            (mfd << MXC_CCM_PCTL_MFD_OFFSET) | (pd << MXC_CCM_PCTL_PD_OFFSET);
+
+        if (clk == &mcu_pll_clk)
+                __raw_writel(reg, MXC_CCM_MPCTL);
+        else if (clk == &usb_pll_clk)
+                __raw_writel(reg, MXC_CCM_UPCTL);
+        else if (clk == &serial_pll_clk)
+                __raw_writel(reg, MXC_CCM_SRPCTL);
+
+        return 0;
+}
+
+static unsigned long _clk_pll_get_rate(struct clk *clk)
+{
+        long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
+        unsigned long reg, ccmr;
+        s64 temp;
+        unsigned int prcs;
+
+        ccmr = __raw_readl(MXC_CCM_CCMR);
+        prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
+        if (prcs == 0x1)
+                ref_clk = CKIL_CLK_FREQ * 1024;
+        else
+                ref_clk = clk_get_rate(&ckih_clk);
+
+        if (clk == &mcu_pll_clk) {
+                if ((ccmr & MXC_CCM_CCMR_MPE) == 0)
+                        return ref_clk;
+                if ((ccmr & MXC_CCM_CCMR_MDS) != 0)
+                        return ref_clk;
+                reg = __raw_readl(MXC_CCM_MPCTL);
+        } else if (clk == &usb_pll_clk)
+                reg = __raw_readl(MXC_CCM_UPCTL);
+        else if (clk == &serial_pll_clk)
+                reg = __raw_readl(MXC_CCM_SRPCTL);
+        else {
+                BUG();
+                return 0;
+        }
+
+        pdf = (reg & MXC_CCM_PCTL_PD_MASK) >> MXC_CCM_PCTL_PD_OFFSET;
+        mfd = (reg & MXC_CCM_PCTL_MFD_MASK) >> MXC_CCM_PCTL_MFD_OFFSET;
+        mfi = (reg & MXC_CCM_PCTL_MFI_MASK) >> MXC_CCM_PCTL_MFI_OFFSET;
+        mfi = (mfi <= 5) ? 5 : mfi;
+        mfn = mfn_abs = reg & MXC_CCM_PCTL_MFN_MASK;
+
+        if (mfn >= 0x200) {
+                mfn |= 0xFFFFFE00;
+                mfn_abs = -mfn;
+        }
+
+        ref_clk *= 2;
+        ref_clk /= pdf + 1;
+
+        temp = (u64) ref_clk * mfn_abs;
+        do_div(temp, mfd + 1);
+        if (mfn < 0)
+                temp = -temp;
+        temp = (ref_clk * mfi) + temp;
+
+        return temp;
+}
+
+static int _clk_usb_pll_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CCMR);
+        reg |= MXC_CCM_CCMR_UPE;
+        __raw_writel(reg, MXC_CCM_CCMR);
+
+        /* No lock bit on MX31, so using max time from spec */
+        udelay(80);
+
+        return 0;
+}
+
+static void _clk_usb_pll_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CCMR);
+        reg &= ~MXC_CCM_CCMR_UPE;
+        __raw_writel(reg, MXC_CCM_CCMR);
+}
+
+static int _clk_serial_pll_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CCMR);
+        reg |= MXC_CCM_CCMR_SPE;
+        __raw_writel(reg, MXC_CCM_CCMR);
+
+        /* No lock bit on MX31, so using max time from spec */
+        udelay(80);
+
+        return 0;
+}
+
+static void _clk_serial_pll_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CCMR);
+        reg &= ~MXC_CCM_CCMR_SPE;
+        __raw_writel(reg, MXC_CCM_CCMR);
+}
+
+#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off)
+#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
+#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
+
+static unsigned long _clk_mcu_main_get_rate(struct clk *clk)
+{
+        u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
+
+        if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL)
+                return clk_get_rate(&serial_pll_clk);
+        else
+                return clk_get_rate(&mcu_pll_clk);
+}
+
+static unsigned long _clk_hclk_get_rate(struct clk *clk)
+{
+        unsigned long max_pdf;
+
+        max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK,
+                       MXC_CCM_PDR0_MAX_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (max_pdf + 1);
+}
+
+static unsigned long _clk_ipg_get_rate(struct clk *clk)
+{
+        unsigned long ipg_pdf;
+
+        ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK,
+                       MXC_CCM_PDR0_IPG_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (ipg_pdf + 1);
+}
+
+static unsigned long _clk_nfc_get_rate(struct clk *clk)
+{
+        unsigned long nfc_pdf;
+
+        nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK,
+                       MXC_CCM_PDR0_NFC_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (nfc_pdf + 1);
+}
+
+static unsigned long _clk_hsp_get_rate(struct clk *clk)
+{
+        unsigned long hsp_pdf;
+
+        hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK,
+                       MXC_CCM_PDR0_HSP_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (hsp_pdf + 1);
+}
+
+static unsigned long _clk_usb_get_rate(struct clk *clk)
+{
+        unsigned long usb_pdf, usb_prepdf;
+
+        usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK,
+                       MXC_CCM_PDR1_USB_PODF_OFFSET);
+        usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK,
+                          MXC_CCM_PDR1_USB_PRDF_OFFSET);
+        return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
+}
+
+static unsigned long _clk_csi_get_rate(struct clk *clk)
+{
+        u32 reg, pre, post;
+
+        reg = __raw_readl(MXC_CCM_PDR0);
+        pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >>
+            MXC_CCM_PDR0_CSI_PRDF_OFFSET;
+        pre++;
+        post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >>
+            MXC_CCM_PDR0_CSI_PODF_OFFSET;
+        post++;
+        return clk_get_rate(clk->parent) / (pre * post);
+}
+
+static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 pre, post, parent = clk_get_rate(clk->parent);
+        u32 div = parent / rate;
+
+        if (parent % rate)
+                div++;
+
+        __calc_pre_post_dividers(div, &pre, &post);
+
+        return parent / (pre * post);
+}
+
+static int _clk_csi_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
+
+        div = parent / rate;
+
+        if ((parent / div) != rate)
+                return -EINVAL;
+
+        __calc_pre_post_dividers(div, &pre, &post);
+
+        /* Set CSI clock divider */
+        reg = __raw_readl(MXC_CCM_PDR0) &
+            ~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK);
+        reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET;
+        reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET;
+        __raw_writel(reg, MXC_CCM_PDR0);
+
+        return 0;
+}
+
+static unsigned long _clk_per_get_rate(struct clk *clk)
+{
+        unsigned long per_pdf;
+
+        per_pdf = PDR0(MXC_CCM_PDR0_PER_PODF_MASK,
+                       MXC_CCM_PDR0_PER_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (per_pdf + 1);
+}
+
+static unsigned long _clk_ssi1_get_rate(struct clk *clk)
+{
+        unsigned long ssi1_pdf, ssi1_prepdf;
+
+        ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK,
+                        MXC_CCM_PDR1_SSI1_PODF_OFFSET);
+        ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK,
+                           MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
+}
+
+static unsigned long _clk_ssi2_get_rate(struct clk *clk)
+{
+        unsigned long ssi2_pdf, ssi2_prepdf;
+
+        ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK,
+                        MXC_CCM_PDR1_SSI2_PODF_OFFSET);
+        ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK,
+                           MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
+}
+
+static unsigned long _clk_firi_get_rate(struct clk *clk)
+{
+        unsigned long firi_pdf, firi_prepdf;
+
+        firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK,
+                        MXC_CCM_PDR1_FIRI_PODF_OFFSET);
+        firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK,
+                           MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET);
+        return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
+}
+
+static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 pre, post;
+        u32 parent = clk_get_rate(clk->parent);
+        u32 div = parent / rate;
+
+        if (parent % rate)
+                div++;
+
+        __calc_pre_post_dividers(div, &pre, &post);
+
+        return parent / (pre * post);
+
+}
+
+static int _clk_firi_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
+
+        div = parent / rate;
+
+        if ((parent / div) != rate)
+                return -EINVAL;
+
+        __calc_pre_post_dividers(div, &pre, &post);
+
+        /* Set FIRI clock divider */
+        reg = __raw_readl(MXC_CCM_PDR1) &
+            ~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK);
+        reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET;
+        reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET;
+        __raw_writel(reg, MXC_CCM_PDR1);
+
+        return 0;
+}
+
+static unsigned long _clk_mbx_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / 2;
+}
+
+static unsigned long _clk_mstick1_get_rate(struct clk *clk)
+{
+        unsigned long msti_pdf;
+
+        msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK,
+                        MXC_CCM_PDR2_MST1_PDF_OFFSET);
+        return clk_get_rate(clk->parent) / (msti_pdf + 1);
+}
+
+static unsigned long _clk_mstick2_get_rate(struct clk *clk)
+{
+        unsigned long msti_pdf;
+
+        msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK,
+                        MXC_CCM_PDR2_MST2_PDF_OFFSET);
+        return clk_get_rate(clk->parent) / (msti_pdf + 1);
+}
+
+static unsigned long ckih_rate;
+
+static unsigned long clk_ckih_get_rate(struct clk *clk)
+{
+        return ckih_rate;
+}
+
+static struct clk ckih_clk = {
+        .name = "ckih",
+        .get_rate = clk_ckih_get_rate,
+};
+
+static unsigned long clk_ckil_get_rate(struct clk *clk)
+{
+        return CKIL_CLK_FREQ;
+}
+
+static struct clk ckil_clk = {
+        .name = "ckil",
+        .get_rate = clk_ckil_get_rate,
+};
+
+static struct clk mcu_pll_clk = {
+        .name = "mcu_pll",
+        .parent = &ckih_clk,
+        .set_rate = _clk_pll_set_rate,
+        .get_rate = _clk_pll_get_rate,
+};
+
+static struct clk mcu_main_clk = {
+        .name = "mcu_main_clk",
+        .parent = &mcu_pll_clk,
+        .get_rate = _clk_mcu_main_get_rate,
+};
+
+static struct clk serial_pll_clk = {
+        .name = "serial_pll",
+        .parent = &ckih_clk,
+        .set_rate = _clk_pll_set_rate,
+        .get_rate = _clk_pll_get_rate,
+        .enable = _clk_serial_pll_enable,
+        .disable = _clk_serial_pll_disable,
+};
+
+static struct clk usb_pll_clk = {
+        .name = "usb_pll",
+        .parent = &ckih_clk,
+        .set_rate = _clk_pll_set_rate,
+        .get_rate = _clk_pll_get_rate,
+        .enable = _clk_usb_pll_enable,
+        .disable = _clk_usb_pll_disable,
+};
+
+static struct clk ahb_clk = {
+        .name = "ahb_clk",
+        .parent = &mcu_main_clk,
+        .get_rate = _clk_hclk_get_rate,
+};
+
+static struct clk per_clk = {
+        .name = "per_clk",
+        .parent = &usb_pll_clk,
+        .get_rate = _clk_per_get_rate,
+};
+
+static struct clk perclk_clk = {
+        .name = "perclk_clk",
+        .parent = &ipg_clk,
+};
+
+static struct clk cspi_clk[] = {
+        {
+         .name = "cspi_clk",
+         .id = 0,
+         .parent = &ipg_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR2,
+         .enable_shift = MXC_CCM_CGR2_CSPI1_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "cspi_clk",
+         .id = 1,
+         .parent = &ipg_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR2,
+         .enable_shift = MXC_CCM_CGR2_CSPI2_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "cspi_clk",
+         .id = 2,
+         .parent = &ipg_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_CSPI3_OFFSET,
+         .disable = _clk_disable,},
+};
+
+static struct clk ipg_clk = {
+        .name = "ipg_clk",
+        .parent = &ahb_clk,
+        .get_rate = _clk_ipg_get_rate,
+};
+
+static struct clk emi_clk = {
+        .name = "emi_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR2,
+        .enable_shift = MXC_CCM_CGR2_EMI_OFFSET,
+        .disable = _clk_emi_disable,
+};
+
+static struct clk gpt_clk = {
+        .name = "gpt_clk",
+        .parent = &perclk_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR0,
+        .enable_shift = MXC_CCM_CGR0_GPT_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk pwm_clk = {
+        .name = "pwm_clk",
+        .parent = &perclk_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR0,
+        .enable_shift = MXC_CCM_CGR1_PWM_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk epit_clk[] = {
+        {
+         .name = "epit_clk",
+         .id = 0,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_EPIT1_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "epit_clk",
+         .id = 1,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_EPIT2_OFFSET,
+         .disable = _clk_disable,},
+};
+
+static struct clk nfc_clk = {
+        .name = "nfc_clk",
+        .parent = &ahb_clk,
+        .get_rate = _clk_nfc_get_rate,
+};
+
+static struct clk scc_clk = {
+        .name = "scc_clk",
+        .parent = &ipg_clk,
+};
+
+static struct clk ipu_clk = {
+        .name = "ipu_clk",
+        .parent = &mcu_main_clk,
+        .get_rate = _clk_hsp_get_rate,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR1,
+        .enable_shift = MXC_CCM_CGR1_IPU_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk kpp_clk = {
+        .name = "kpp_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR1,
+        .enable_shift = MXC_CCM_CGR1_KPP_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk wdog_clk = {
+        .name = "wdog_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR1,
+        .enable_shift = MXC_CCM_CGR1_WDOG_OFFSET,
+        .disable = _clk_disable,
+};
+static struct clk rtc_clk = {
+        .name = "rtc_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR1,
+        .enable_shift = MXC_CCM_CGR1_RTC_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk usb_clk[] = {
+        {
+         .name = "usb_clk",
+         .parent = &usb_pll_clk,
+         .get_rate = _clk_usb_get_rate,},
+        {
+         .name = "usb_ahb_clk",
+         .parent = &ahb_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR1,
+         .enable_shift = MXC_CCM_CGR1_USBOTG_OFFSET,
+         .disable = _clk_disable,},
+};
+
+static struct clk csi_clk = {
+        .name = "csi_clk",
+        .parent = &serial_pll_clk,
+        .get_rate = _clk_csi_get_rate,
+        .round_rate = _clk_csi_round_rate,
+        .set_rate = _clk_csi_set_rate,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR1,
+        .enable_shift = MXC_CCM_CGR1_CSI_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk uart_clk[] = {
+        {
+         .name = "uart_clk",
+         .id = 0,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_UART1_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "uart_clk",
+         .id = 1,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_UART2_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "uart_clk",
+         .id = 2,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR1,
+         .enable_shift = MXC_CCM_CGR1_UART3_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "uart_clk",
+         .id = 3,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR1,
+         .enable_shift = MXC_CCM_CGR1_UART4_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "uart_clk",
+         .id = 4,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR1,
+         .enable_shift = MXC_CCM_CGR1_UART5_OFFSET,
+         .disable = _clk_disable,},
+};
+
+static struct clk i2c_clk[] = {
+        {
+         .name = "i2c_clk",
+         .id = 0,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_I2C1_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "i2c_clk",
+         .id = 1,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_I2C2_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "i2c_clk",
+         .id = 2,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_I2C3_OFFSET,
+         .disable = _clk_disable,},
+};
+
+static struct clk owire_clk = {
+        .name = "owire_clk",
+        .parent = &perclk_clk,
+        .enable_reg = MXC_CCM_CGR1,
+        .enable_shift = MXC_CCM_CGR1_OWIRE_OFFSET,
+        .enable = _clk_enable,
+        .disable = _clk_disable,
+};
+
+static struct clk sdhc_clk[] = {
+        {
+         .name = "sdhc_clk",
+         .id = 0,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_SD_MMC1_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "sdhc_clk",
+         .id = 1,
+         .parent = &perclk_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_SD_MMC2_OFFSET,
+         .disable = _clk_disable,},
+};
+
+static struct clk ssi_clk[] = {
+        {
+         .name = "ssi_clk",
+         .parent = &serial_pll_clk,
+         .get_rate = _clk_ssi1_get_rate,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_SSI1_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "ssi_clk",
+         .id = 1,
+         .parent = &serial_pll_clk,
+         .get_rate = _clk_ssi2_get_rate,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR2,
+         .enable_shift = MXC_CCM_CGR2_SSI2_OFFSET,
+         .disable = _clk_disable,},
+};
+
+static struct clk firi_clk = {
+        .name = "firi_clk",
+        .parent = &usb_pll_clk,
+        .round_rate = _clk_firi_round_rate,
+        .set_rate = _clk_firi_set_rate,
+        .get_rate = _clk_firi_get_rate,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR2,
+        .enable_shift = MXC_CCM_CGR2_FIRI_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk ata_clk = {
+        .name = "ata_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR0,
+        .enable_shift = MXC_CCM_CGR0_ATA_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk mbx_clk = {
+        .name = "mbx_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR2,
+        .enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
+        .get_rate = _clk_mbx_get_rate,
+};
+
+static struct clk vpu_clk = {
+        .name = "vpu_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR2,
+        .enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
+        .get_rate = _clk_mbx_get_rate,
+};
+
+static struct clk rtic_clk = {
+        .name = "rtic_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR2,
+        .enable_shift = MXC_CCM_CGR2_RTIC_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk rng_clk = {
+        .name = "rng_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR0,
+        .enable_shift = MXC_CCM_CGR0_RNG_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk sdma_clk[] = {
+        {
+         .name = "sdma_ahb_clk",
+         .parent = &ahb_clk,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR0,
+         .enable_shift = MXC_CCM_CGR0_SDMA_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "sdma_ipg_clk",
+         .parent = &ipg_clk,}
+};
+
+static struct clk mpeg4_clk = {
+        .name = "mpeg4_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR1,
+        .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk vl2cc_clk = {
+        .name = "vl2cc_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR1,
+        .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk mstick_clk[] = {
+        {
+         .name = "mstick_clk",
+         .id = 0,
+         .parent = &usb_pll_clk,
+         .get_rate = _clk_mstick1_get_rate,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR1,
+         .enable_shift = MXC_CCM_CGR1_MEMSTICK1_OFFSET,
+         .disable = _clk_disable,},
+        {
+         .name = "mstick_clk",
+         .id = 1,
+         .parent = &usb_pll_clk,
+         .get_rate = _clk_mstick2_get_rate,
+         .enable = _clk_enable,
+         .enable_reg = MXC_CCM_CGR1,
+         .enable_shift = MXC_CCM_CGR1_MEMSTICK2_OFFSET,
+         .disable = _clk_disable,},
+};
+
+static struct clk iim_clk = {
+        .name = "iim_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = MXC_CCM_CGR0,
+        .enable_shift = MXC_CCM_CGR0_IIM_OFFSET,
+        .disable = _clk_disable,
+};
+
+static unsigned long _clk_cko1_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 div, parent = clk_get_rate(clk->parent);
+
+        div = parent / rate;
+        if (parent % rate)
+                div++;
+
+        if (div > 8)
+                div = 16;
+        else if (div > 4)
+                div = 8;
+        else if (div > 2)
+                div = 4;
+
+        return parent / div;
+}
+
+static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg, div, parent = clk_get_rate(clk->parent);
+
+        div = parent / rate;
+
+        if (div == 16)
+                div = 4;
+        else if (div == 8)
+                div = 3;
+        else if (div == 4)
+                div = 2;
+        else if (div == 2)
+                div = 1;
+        else if (div == 1)
+                div = 0;
+        else
+                return -EINVAL;
+
+        reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOUTDIV_MASK;
+        reg |= div << MXC_CCM_COSR_CLKOUTDIV_OFFSET;
+        __raw_writel(reg, MXC_CCM_COSR);
+
+        return 0;
+}
+
+static unsigned long _clk_cko1_get_rate(struct clk *clk)
+{
+        u32 div;
+
+        div = __raw_readl(MXC_CCM_COSR) & MXC_CCM_COSR_CLKOUTDIV_MASK >>
+            MXC_CCM_COSR_CLKOUTDIV_OFFSET;
+
+        return clk_get_rate(clk->parent) / (1 << div);
+}
+
+static int _clk_cko1_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOSEL_MASK;
+
+        if (parent == &mcu_main_clk)
+                reg |= 0 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &ipg_clk)
+                reg |= 1 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &usb_pll_clk)
+                reg |= 2 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == mcu_main_clk.parent)
+                reg |= 3 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &ahb_clk)
+                reg |= 5 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &serial_pll_clk)
+                reg |= 7 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &ckih_clk)
+                reg |= 8 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &emi_clk)
+                reg |= 9 << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &ipu_clk)
+                reg |= 0xA << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &nfc_clk)
+                reg |= 0xB << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else if (parent == &uart_clk[0])
+                reg |= 0xC << MXC_CCM_COSR_CLKOSEL_OFFSET;
+        else
+                return -EINVAL;
+
+        __raw_writel(reg, MXC_CCM_COSR);
+
+        return 0;
+}
+
+static int _clk_cko1_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_COSR) | MXC_CCM_COSR_CLKOEN;
+        __raw_writel(reg, MXC_CCM_COSR);
+
+        return 0;
+}
+
+static void _clk_cko1_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOEN;
+        __raw_writel(reg, MXC_CCM_COSR);
+}
+
+static struct clk cko1_clk = {
+        .name = "cko1_clk",
+        .get_rate = _clk_cko1_get_rate,
+        .set_rate = _clk_cko1_set_rate,
+        .round_rate = _clk_cko1_round_rate,
+        .set_parent = _clk_cko1_set_parent,
+        .enable = _clk_cko1_enable,
+        .disable = _clk_cko1_disable,
+};
+
+static struct clk *mxc_clks[] = {
+        &ckih_clk,
+        &ckil_clk,
+        &mcu_pll_clk,
+        &usb_pll_clk,
+        &serial_pll_clk,
+        &mcu_main_clk,
+        &ahb_clk,
+        &per_clk,
+        &perclk_clk,
+        &cko1_clk,
+        &emi_clk,
+        &cspi_clk[0],
+        &cspi_clk[1],
+        &cspi_clk[2],
+        &ipg_clk,
+        &gpt_clk,
+        &pwm_clk,
+        &wdog_clk,
+        &rtc_clk,
+        &epit_clk[0],
+        &epit_clk[1],
+        &nfc_clk,
+        &ipu_clk,
+        &kpp_clk,
+        &usb_clk[0],
+        &usb_clk[1],
+        &csi_clk,
+        &uart_clk[0],
+        &uart_clk[1],
+        &uart_clk[2],
+        &uart_clk[3],
+        &uart_clk[4],
+        &i2c_clk[0],
+        &i2c_clk[1],
+        &i2c_clk[2],
+        &owire_clk,
+        &sdhc_clk[0],
+        &sdhc_clk[1],
+        &ssi_clk[0],
+        &ssi_clk[1],
+        &firi_clk,
+        &ata_clk,
+        &rtic_clk,
+        &rng_clk,
+        &sdma_clk[0],
+        &sdma_clk[1],
+        &mstick_clk[0],
+        &mstick_clk[1],
+        &scc_clk,
+        &iim_clk,
+};
+
+int __init mxc_clocks_init(unsigned long fref)
+{
+        u32 reg;
+        struct clk **clkp;
+
+        ckih_rate = fref;
+
+        for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
+                clk_register(*clkp);
+
+        if (cpu_is_mx31()) {
+                clk_register(&mpeg4_clk);
+                clk_register(&mbx_clk);
+        } else {
+                clk_register(&vpu_clk);
+                clk_register(&vl2cc_clk);
+        }
+
+        /* Turn off all possible clocks */
+        __raw_writel(MXC_CCM_CGR0_GPT_MASK, MXC_CCM_CGR0);
+        __raw_writel(0, MXC_CCM_CGR1);
+
+        __raw_writel(MXC_CCM_CGR2_EMI_MASK |
+                     MXC_CCM_CGR2_IPMUX1_MASK |
+                     MXC_CCM_CGR2_IPMUX2_MASK |
+                     MXC_CCM_CGR2_MXCCLKENSEL_MASK |    /* for MX32 */
+                     MXC_CCM_CGR2_CHIKCAMPEN_MASK |     /* for MX32 */
+                     MXC_CCM_CGR2_OVRVPUBUSY_MASK |     /* for MX32 */
+                     1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
+                                           MX32, but still required to be set */
+                     MXC_CCM_CGR2);
+
+        clk_disable(&cko1_clk);
+        clk_disable(&usb_pll_clk);
+
+        pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
+
+        clk_enable(&gpt_clk);
+        clk_enable(&emi_clk);
+        clk_enable(&iim_clk);
+
+        clk_enable(&serial_pll_clk);
+
+        if (mx31_revision() >= CHIP_REV_2_0) {
+                reg = __raw_readl(MXC_CCM_PMCR1);
+                /* No PLL restart on DVFS switch; enable auto EMI handshake */
+                reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
+                __raw_writel(reg, MXC_CCM_PMCR1);
+        }
+
+        return 0;
+}
+
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h
new file mode 100644
index 000000000000..4a0e0ede23bb
--- /dev/null
+++ b/arch/arm/mach-mx3/crm_regs.h
@@ -0,0 +1,401 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX3_CRM_REGS_H__
+
+#define CKIH_CLK_FREQ           26000000
+#define CKIH_CLK_FREQ_27MHZ     27000000
+#define CKIL_CLK_FREQ           32768
+
+#define MXC_CCM_BASE            IO_ADDRESS(CCM_BASE_ADDR)
+
+/* Register addresses */
+#define MXC_CCM_CCMR            (MXC_CCM_BASE + 0x00)
+#define MXC_CCM_PDR0            (MXC_CCM_BASE + 0x04)
+#define MXC_CCM_PDR1            (MXC_CCM_BASE + 0x08)
+#define MXC_CCM_RCSR            (MXC_CCM_BASE + 0x0C)
+#define MXC_CCM_MPCTL           (MXC_CCM_BASE + 0x10)
+#define MXC_CCM_UPCTL           (MXC_CCM_BASE + 0x14)
+#define MXC_CCM_SRPCTL          (MXC_CCM_BASE + 0x18)
+#define MXC_CCM_COSR            (MXC_CCM_BASE + 0x1C)
+#define MXC_CCM_CGR0            (MXC_CCM_BASE + 0x20)
+#define MXC_CCM_CGR1            (MXC_CCM_BASE + 0x24)
+#define MXC_CCM_CGR2            (MXC_CCM_BASE + 0x28)
+#define MXC_CCM_WIMR            (MXC_CCM_BASE + 0x2C)
+#define MXC_CCM_LDC             (MXC_CCM_BASE + 0x30)
+#define MXC_CCM_DCVR0           (MXC_CCM_BASE + 0x34)
+#define MXC_CCM_DCVR1           (MXC_CCM_BASE + 0x38)
+#define MXC_CCM_DCVR2           (MXC_CCM_BASE + 0x3C)
+#define MXC_CCM_DCVR3           (MXC_CCM_BASE + 0x40)
+#define MXC_CCM_LTR0            (MXC_CCM_BASE + 0x44)
+#define MXC_CCM_LTR1            (MXC_CCM_BASE + 0x48)
+#define MXC_CCM_LTR2            (MXC_CCM_BASE + 0x4C)
+#define MXC_CCM_LTR3            (MXC_CCM_BASE + 0x50)
+#define MXC_CCM_LTBR0           (MXC_CCM_BASE + 0x54)
+#define MXC_CCM_LTBR1           (MXC_CCM_BASE + 0x58)
+#define MXC_CCM_PMCR0           (MXC_CCM_BASE + 0x5C)
+#define MXC_CCM_PMCR1           (MXC_CCM_BASE + 0x60)
+#define MXC_CCM_PDR2            (MXC_CCM_BASE + 0x64)
+
+/* Register bit definitions */
+#define MXC_CCM_CCMR_WBEN                       (1 << 27)
+#define MXC_CCM_CCMR_CSCS                       (1 << 25)
+#define MXC_CCM_CCMR_PERCS                      (1 << 24)
+#define MXC_CCM_CCMR_SSI1S_OFFSET               18
+#define MXC_CCM_CCMR_SSI1S_MASK                 (0x3 << 18)
+#define MXC_CCM_CCMR_SSI2S_OFFSET               21
+#define MXC_CCM_CCMR_SSI2S_MASK                 (0x3 << 21)
+#define MXC_CCM_CCMR_LPM_OFFSET                 14
+#define MXC_CCM_CCMR_LPM_MASK                   (0x3 << 14)
+#define MXC_CCM_CCMR_FIRS_OFFSET                11
+#define MXC_CCM_CCMR_FIRS_MASK                  (0x3 << 11)
+#define MXC_CCM_CCMR_UPE                        (1 << 9)
+#define MXC_CCM_CCMR_SPE                        (1 << 8)
+#define MXC_CCM_CCMR_MDS                        (1 << 7)
+#define MXC_CCM_CCMR_SBYCS                      (1 << 4)
+#define MXC_CCM_CCMR_MPE                        (1 << 3)
+#define MXC_CCM_CCMR_PRCS_OFFSET                1
+#define MXC_CCM_CCMR_PRCS_MASK                  (0x3 << 1)
+
+#define MXC_CCM_PDR0_CSI_PODF_OFFSET            26
+#define MXC_CCM_PDR0_CSI_PODF_MASK              (0x3F << 26)
+#define MXC_CCM_PDR0_CSI_PRDF_OFFSET            23
+#define MXC_CCM_PDR0_CSI_PRDF_MASK              (0x7 << 23)
+#define MXC_CCM_PDR0_PER_PODF_OFFSET            16
+#define MXC_CCM_PDR0_PER_PODF_MASK              (0x1F << 16)
+#define MXC_CCM_PDR0_HSP_PODF_OFFSET            11
+#define MXC_CCM_PDR0_HSP_PODF_MASK              (0x7 << 11)
+#define MXC_CCM_PDR0_NFC_PODF_OFFSET            8
+#define MXC_CCM_PDR0_NFC_PODF_MASK              (0x7 << 8)
+#define MXC_CCM_PDR0_IPG_PODF_OFFSET            6
+#define MXC_CCM_PDR0_IPG_PODF_MASK              (0x3 << 6)
+#define MXC_CCM_PDR0_MAX_PODF_OFFSET            3
+#define MXC_CCM_PDR0_MAX_PODF_MASK              (0x7 << 3)
+#define MXC_CCM_PDR0_MCU_PODF_OFFSET            0
+#define MXC_CCM_PDR0_MCU_PODF_MASK              0x7
+
+#define MXC_CCM_PDR0_HSP_DIV_1                  (0x0 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_2                  (0x1 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_3                  (0x2 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_4                  (0x3 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_5                  (0x4 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_6                  (0x5 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_7                  (0x6 << 11)
+#define MXC_CCM_PDR0_HSP_DIV_8                  (0x7 << 11)
+
+#define MXC_CCM_PDR0_IPG_DIV_1                  (0x0 << 6)
+#define MXC_CCM_PDR0_IPG_DIV_2                  (0x1 << 6)
+#define MXC_CCM_PDR0_IPG_DIV_3                  (0x2 << 6)
+#define MXC_CCM_PDR0_IPG_DIV_4                  (0x3 << 6)
+
+#define MXC_CCM_PDR0_MAX_DIV_1                  (0x0 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_2                  (0x1 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_3                  (0x2 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_4                  (0x3 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_5                  (0x4 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_6                  (0x5 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_7                  (0x6 << 3)
+#define MXC_CCM_PDR0_MAX_DIV_8                  (0x7 << 3)
+
+#define MXC_CCM_PDR0_NFC_DIV_1                  (0x0 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_2                  (0x1 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_3                  (0x2 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_4                  (0x3 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_5                  (0x4 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_6                  (0x5 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_7                  (0x6 << 8)
+#define MXC_CCM_PDR0_NFC_DIV_8                  (0x7 << 8)
+
+#define MXC_CCM_PDR0_MCU_DIV_1                  0x0
+#define MXC_CCM_PDR0_MCU_DIV_2                  0x1
+#define MXC_CCM_PDR0_MCU_DIV_3                  0x2
+#define MXC_CCM_PDR0_MCU_DIV_4                  0x3
+#define MXC_CCM_PDR0_MCU_DIV_5                  0x4
+#define MXC_CCM_PDR0_MCU_DIV_6                  0x5
+#define MXC_CCM_PDR0_MCU_DIV_7                  0x6
+#define MXC_CCM_PDR0_MCU_DIV_8                  0x7
+
+#define MXC_CCM_PDR1_USB_PRDF_OFFSET            30
+#define MXC_CCM_PDR1_USB_PRDF_MASK              (0x3 << 30)
+#define MXC_CCM_PDR1_USB_PODF_OFFSET            27
+#define MXC_CCM_PDR1_USB_PODF_MASK              (0x7 << 27)
+#define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET       24
+#define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK         (0x7 << 24)
+#define MXC_CCM_PDR1_FIRI_PODF_OFFSET           18
+#define MXC_CCM_PDR1_FIRI_PODF_MASK             (0x3F << 18)
+#define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET       15
+#define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK         (0x7 << 15)
+#define MXC_CCM_PDR1_SSI2_PODF_OFFSET           9
+#define MXC_CCM_PDR1_SSI2_PODF_MASK             (0x3F << 9)
+#define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET       6
+#define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK         (0x7 << 6)
+#define MXC_CCM_PDR1_SSI1_PODF_OFFSET           0
+#define MXC_CCM_PDR1_SSI1_PODF_MASK             0x3F
+
+/* Bit definitions for RCSR */
+#define MXC_CCM_RCSR_NF16B                      0x80000000
+
+/* Bit definitions for both MCU, USB and SR PLL control registers */
+#define MXC_CCM_PCTL_BRM                        0x80000000
+#define MXC_CCM_PCTL_PD_OFFSET                  26
+#define MXC_CCM_PCTL_PD_MASK                    (0xF << 26)
+#define MXC_CCM_PCTL_MFD_OFFSET                 16
+#define MXC_CCM_PCTL_MFD_MASK                   (0x3FF << 16)
+#define MXC_CCM_PCTL_MFI_OFFSET                 10
+#define MXC_CCM_PCTL_MFI_MASK                   (0xF << 10)
+#define MXC_CCM_PCTL_MFN_OFFSET                 0
+#define MXC_CCM_PCTL_MFN_MASK                   0x3FF
+
+#define MXC_CCM_CGR0_SD_MMC1_OFFSET             0
+#define MXC_CCM_CGR0_SD_MMC1_MASK               (0x3 << 0)
+#define MXC_CCM_CGR0_SD_MMC2_OFFSET             2
+#define MXC_CCM_CGR0_SD_MMC2_MASK               (0x3 << 2)
+#define MXC_CCM_CGR0_GPT_OFFSET                 4
+#define MXC_CCM_CGR0_GPT_MASK                   (0x3 << 4)
+#define MXC_CCM_CGR0_EPIT1_OFFSET               6
+#define MXC_CCM_CGR0_EPIT1_MASK                 (0x3 << 6)
+#define MXC_CCM_CGR0_EPIT2_OFFSET               8
+#define MXC_CCM_CGR0_EPIT2_MASK                 (0x3 << 8)
+#define MXC_CCM_CGR0_IIM_OFFSET                 10
+#define MXC_CCM_CGR0_IIM_MASK                   (0x3 << 10)
+#define MXC_CCM_CGR0_ATA_OFFSET                 12
+#define MXC_CCM_CGR0_ATA_MASK                   (0x3 << 12)
+#define MXC_CCM_CGR0_SDMA_OFFSET                14
+#define MXC_CCM_CGR0_SDMA_MASK                  (0x3 << 14)
+#define MXC_CCM_CGR0_CSPI3_OFFSET               16
+#define MXC_CCM_CGR0_CSPI3_MASK                 (0x3 << 16)
+#define MXC_CCM_CGR0_RNG_OFFSET                 18
+#define MXC_CCM_CGR0_RNG_MASK                   (0x3 << 18)
+#define MXC_CCM_CGR0_UART1_OFFSET               20
+#define MXC_CCM_CGR0_UART1_MASK                 (0x3 << 20)
+#define MXC_CCM_CGR0_UART2_OFFSET               22
+#define MXC_CCM_CGR0_UART2_MASK                 (0x3 << 22)
+#define MXC_CCM_CGR0_SSI1_OFFSET                24
+#define MXC_CCM_CGR0_SSI1_MASK                  (0x3 << 24)
+#define MXC_CCM_CGR0_I2C1_OFFSET                26
+#define MXC_CCM_CGR0_I2C1_MASK                  (0x3 << 26)
+#define MXC_CCM_CGR0_I2C2_OFFSET                28
+#define MXC_CCM_CGR0_I2C2_MASK                  (0x3 << 28)
+#define MXC_CCM_CGR0_I2C3_OFFSET                30
+#define MXC_CCM_CGR0_I2C3_MASK                  (0x3 << 30)
+
+#define MXC_CCM_CGR1_HANTRO_OFFSET              0
+#define MXC_CCM_CGR1_HANTRO_MASK                (0x3 << 0)
+#define MXC_CCM_CGR1_MEMSTICK1_OFFSET           2
+#define MXC_CCM_CGR1_MEMSTICK1_MASK             (0x3 << 2)
+#define MXC_CCM_CGR1_MEMSTICK2_OFFSET           4
+#define MXC_CCM_CGR1_MEMSTICK2_MASK             (0x3 << 4)
+#define MXC_CCM_CGR1_CSI_OFFSET                 6
+#define MXC_CCM_CGR1_CSI_MASK                   (0x3 << 6)
+#define MXC_CCM_CGR1_RTC_OFFSET                 8
+#define MXC_CCM_CGR1_RTC_MASK                   (0x3 << 8)
+#define MXC_CCM_CGR1_WDOG_OFFSET                10
+#define MXC_CCM_CGR1_WDOG_MASK                  (0x3 << 10)
+#define MXC_CCM_CGR1_PWM_OFFSET                 12
+#define MXC_CCM_CGR1_PWM_MASK                   (0x3 << 12)
+#define MXC_CCM_CGR1_SIM_OFFSET                 14
+#define MXC_CCM_CGR1_SIM_MASK                   (0x3 << 14)
+#define MXC_CCM_CGR1_ECT_OFFSET                 16
+#define MXC_CCM_CGR1_ECT_MASK                   (0x3 << 16)
+#define MXC_CCM_CGR1_USBOTG_OFFSET              18
+#define MXC_CCM_CGR1_USBOTG_MASK                (0x3 << 18)
+#define MXC_CCM_CGR1_KPP_OFFSET                 20
+#define MXC_CCM_CGR1_KPP_MASK                   (0x3 << 20)
+#define MXC_CCM_CGR1_IPU_OFFSET                 22
+#define MXC_CCM_CGR1_IPU_MASK                   (0x3 << 22)
+#define MXC_CCM_CGR1_UART3_OFFSET               24
+#define MXC_CCM_CGR1_UART3_MASK                 (0x3 << 24)
+#define MXC_CCM_CGR1_UART4_OFFSET               26
+#define MXC_CCM_CGR1_UART4_MASK                 (0x3 << 26)
+#define MXC_CCM_CGR1_UART5_OFFSET               28
+#define MXC_CCM_CGR1_UART5_MASK                 (0x3 << 28)
+#define MXC_CCM_CGR1_OWIRE_OFFSET               30
+#define MXC_CCM_CGR1_OWIRE_MASK                 (0x3 << 30)
+
+#define MXC_CCM_CGR2_SSI2_OFFSET                0
+#define MXC_CCM_CGR2_SSI2_MASK                  (0x3 << 0)
+#define MXC_CCM_CGR2_CSPI1_OFFSET               2
+#define MXC_CCM_CGR2_CSPI1_MASK                 (0x3 << 2)
+#define MXC_CCM_CGR2_CSPI2_OFFSET               4
+#define MXC_CCM_CGR2_CSPI2_MASK                 (0x3 << 4)
+#define MXC_CCM_CGR2_GACC_OFFSET                6
+#define MXC_CCM_CGR2_GACC_MASK                  (0x3 << 6)
+#define MXC_CCM_CGR2_EMI_OFFSET                 8
+#define MXC_CCM_CGR2_EMI_MASK                   (0x3 << 8)
+#define MXC_CCM_CGR2_RTIC_OFFSET                10
+#define MXC_CCM_CGR2_RTIC_MASK                  (0x3 << 10)
+#define MXC_CCM_CGR2_FIRI_OFFSET                12
+#define MXC_CCM_CGR2_FIRI_MASK                  (0x3 << 12)
+#define MXC_CCM_CGR2_IPMUX1_OFFSET              14
+#define MXC_CCM_CGR2_IPMUX1_MASK                (0x3 << 14)
+#define MXC_CCM_CGR2_IPMUX2_OFFSET              16
+#define MXC_CCM_CGR2_IPMUX2_MASK                (0x3 << 16)
+
+/* These new CGR2 bits are added in MX32 */
+#define MXC_CCM_CGR2_APMSYSCLKSEL_OFFSET        18
+#define MXC_CCM_CGR2_APMSYSCLKSEL_MASK          (0x3 << 18)
+#define MXC_CCM_CGR2_APMSSICLKSEL_OFFSET        20
+#define MXC_CCM_CGR2_APMSSICLKSEL_MASK          (0x3 << 20)
+#define MXC_CCM_CGR2_APMPERCLKSEL_OFFSET        22
+#define MXC_CCM_CGR2_APMPERCLKSEL_MASK          (0x3 << 22)
+#define MXC_CCM_CGR2_MXCCLKENSEL_OFFSET         24
+#define MXC_CCM_CGR2_MXCCLKENSEL_MASK           (0x1 << 24)
+#define MXC_CCM_CGR2_CHIKCAMPEN_OFFSET          25
+#define MXC_CCM_CGR2_CHIKCAMPEN_MASK            (0x1 << 25)
+#define MXC_CCM_CGR2_OVRVPUBUSY_OFFSET          26
+#define MXC_CCM_CGR2_OVRVPUBUSY_MASK            (0x1 << 26)
+#define MXC_CCM_CGR2_APMENA_OFFSET              30
+#define MXC_CCM_CGR2_AOMENA_MASK                (0x1 << 30)
+
+/*
+ * LTR0 register offsets
+ */
+#define MXC_CCM_LTR0_DIV3CK_OFFSET              1
+#define MXC_CCM_LTR0_DIV3CK_MASK                (0x3 << 1)
+#define MXC_CCM_LTR0_DNTHR_OFFSET               16
+#define MXC_CCM_LTR0_DNTHR_MASK                 (0x3F << 16)
+#define MXC_CCM_LTR0_UPTHR_OFFSET               22
+#define MXC_CCM_LTR0_UPTHR_MASK                 (0x3F << 22)
+
+/*
+ * LTR1 register offsets
+ */
+#define MXC_CCM_LTR1_PNCTHR_OFFSET              0
+#define MXC_CCM_LTR1_PNCTHR_MASK                0x3F
+#define MXC_CCM_LTR1_UPCNT_OFFSET               6
+#define MXC_CCM_LTR1_UPCNT_MASK                 (0xFF << 6)
+#define MXC_CCM_LTR1_DNCNT_OFFSET               14
+#define MXC_CCM_LTR1_DNCNT_MASK                 (0xFF << 14)
+#define MXC_CCM_LTR1_LTBRSR_MASK                0x400000
+#define MXC_CCM_LTR1_LTBRSR_OFFSET              22
+#define MXC_CCM_LTR1_LTBRSR                     0x400000
+#define MXC_CCM_LTR1_LTBRSH                     0x800000
+
+/*
+ * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15
+ */
+#define MXC_CCM_LTR2_WSW_OFFSET(x)              (11 + (x) * 3)
+#define MXC_CCM_LTR2_WSW_MASK(x)                (0x7 << \
+                                        MXC_CCM_LTR2_WSW_OFFSET((x)))
+#define MXC_CCM_LTR2_EMAC_OFFSET                0
+#define MXC_CCM_LTR2_EMAC_MASK                  0x1FF
+
+/*
+ * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8
+ */
+#define MXC_CCM_LTR3_WSW_OFFSET(x)              (5 + (x) * 3)
+#define MXC_CCM_LTR3_WSW_MASK(x)                (0x7 << \
+                                        MXC_CCM_LTR3_WSW_OFFSET((x)))
+
+#define MXC_CCM_PMCR0_DFSUP1                    0x80000000
+#define MXC_CCM_PMCR0_DFSUP1_SPLL               (0 << 31)
+#define MXC_CCM_PMCR0_DFSUP1_MPLL               (1 << 31)
+#define MXC_CCM_PMCR0_DFSUP0                    0x40000000
+#define MXC_CCM_PMCR0_DFSUP0_PLL                (0 << 30)
+#define MXC_CCM_PMCR0_DFSUP0_PDR                (1 << 30)
+#define MXC_CCM_PMCR0_DFSUP_MASK                (0x3 << 30)
+
+#define DVSUP_TURBO                             0
+#define DVSUP_HIGH                              1
+#define DVSUP_MEDIUM                            2
+#define DVSUP_LOW                               3
+#define MXC_CCM_PMCR0_DVSUP_TURBO               (DVSUP_TURBO << 28)
+#define MXC_CCM_PMCR0_DVSUP_HIGH                (DVSUP_HIGH << 28)
+#define MXC_CCM_PMCR0_DVSUP_MEDIUM              (DVSUP_MEDIUM << 28)
+#define MXC_CCM_PMCR0_DVSUP_LOW                 (DVSUP_LOW << 28)
+#define MXC_CCM_PMCR0_DVSUP_OFFSET              28
+#define MXC_CCM_PMCR0_DVSUP_MASK                (0x3 << 28)
+#define MXC_CCM_PMCR0_UDSC                      0x08000000
+#define MXC_CCM_PMCR0_UDSC_MASK                 (1 << 27)
+#define MXC_CCM_PMCR0_UDSC_UP                   (1 << 27)
+#define MXC_CCM_PMCR0_UDSC_DOWN                 (0 << 27)
+
+#define MXC_CCM_PMCR0_VSCNT_1                   (0x0 << 24)
+#define MXC_CCM_PMCR0_VSCNT_2                   (0x1 << 24)
+#define MXC_CCM_PMCR0_VSCNT_3                   (0x2 << 24)
+#define MXC_CCM_PMCR0_VSCNT_4                   (0x3 << 24)
+#define MXC_CCM_PMCR0_VSCNT_5                   (0x4 << 24)
+#define MXC_CCM_PMCR0_VSCNT_6                   (0x5 << 24)
+#define MXC_CCM_PMCR0_VSCNT_7                   (0x6 << 24)
+#define MXC_CCM_PMCR0_VSCNT_8                   (0x7 << 24)
+#define MXC_CCM_PMCR0_VSCNT_OFFSET              24
+#define MXC_CCM_PMCR0_VSCNT_MASK                (0x7 << 24)
+#define MXC_CCM_PMCR0_DVFEV                     0x00800000
+#define MXC_CCM_PMCR0_DVFIS                     0x00400000
+#define MXC_CCM_PMCR0_LBMI                      0x00200000
+#define MXC_CCM_PMCR0_LBFL                      0x00100000
+#define MXC_CCM_PMCR0_LBCF_4                    (0x0 << 18)
+#define MXC_CCM_PMCR0_LBCF_8                    (0x1 << 18)
+#define MXC_CCM_PMCR0_LBCF_12                   (0x2 << 18)
+#define MXC_CCM_PMCR0_LBCF_16                   (0x3 << 18)
+#define MXC_CCM_PMCR0_LBCF_OFFSET               18
+#define MXC_CCM_PMCR0_LBCF_MASK                 (0x3 << 18)
+#define MXC_CCM_PMCR0_PTVIS                     0x00020000
+#define MXC_CCM_PMCR0_UPDTEN                    0x00010000
+#define MXC_CCM_PMCR0_UPDTEN_MASK               (0x1 << 16)
+#define MXC_CCM_PMCR0_FSVAIM                    0x00008000
+#define MXC_CCM_PMCR0_FSVAI_OFFSET              13
+#define MXC_CCM_PMCR0_FSVAI_MASK                (0x3 << 13)
+#define MXC_CCM_PMCR0_DPVCR                     0x00001000
+#define MXC_CCM_PMCR0_DPVV                      0x00000800
+#define MXC_CCM_PMCR0_WFIM                      0x00000400
+#define MXC_CCM_PMCR0_DRCE3                     0x00000200
+#define MXC_CCM_PMCR0_DRCE2                     0x00000100
+#define MXC_CCM_PMCR0_DRCE1                     0x00000080
+#define MXC_CCM_PMCR0_DRCE0                     0x00000040
+#define MXC_CCM_PMCR0_DCR                       0x00000020
+#define MXC_CCM_PMCR0_DVFEN                     0x00000010
+#define MXC_CCM_PMCR0_PTVAIM                    0x00000008
+#define MXC_CCM_PMCR0_PTVAI_OFFSET              1
+#define MXC_CCM_PMCR0_PTVAI_MASK                (0x3 << 1)
+#define MXC_CCM_PMCR0_DPTEN                     0x00000001
+
+#define MXC_CCM_PMCR1_DVGP_OFFSET               0
+#define MXC_CCM_PMCR1_DVGP_MASK                 (0xF)
+
+#define MXC_CCM_PMCR1_PLLRDIS                      (0x1 << 7)
+#define MXC_CCM_PMCR1_EMIRQ_EN                      (0x1 << 8)
+
+#define MXC_CCM_DCVR_ULV_MASK                   (0x3FF << 22)
+#define MXC_CCM_DCVR_ULV_OFFSET                 22
+#define MXC_CCM_DCVR_LLV_MASK                   (0x3FF << 12)
+#define MXC_CCM_DCVR_LLV_OFFSET                 12
+#define MXC_CCM_DCVR_ELV_MASK                   (0x3FF << 2)
+#define MXC_CCM_DCVR_ELV_OFFSET                 2
+
+#define MXC_CCM_PDR2_MST2_PDF_MASK              (0x3F << 7)
+#define MXC_CCM_PDR2_MST2_PDF_OFFSET            7
+#define MXC_CCM_PDR2_MST1_PDF_MASK              0x3F
+#define MXC_CCM_PDR2_MST1_PDF_OFFSET            0
+
+#define MXC_CCM_COSR_CLKOSEL_MASK               0x0F
+#define MXC_CCM_COSR_CLKOSEL_OFFSET             0
+#define MXC_CCM_COSR_CLKOUTDIV_MASK             (0x07 << 6)
+#define MXC_CCM_COSR_CLKOUTDIV_OFFSET           6
+#define MXC_CCM_COSR_CLKOEN                     (1 << 9)
+
+/*
+ * PMCR0 register offsets
+ */
+#define MXC_CCM_PMCR0_LBFL_OFFSET   20
+#define MXC_CCM_PMCR0_DFSUP0_OFFSET 30
+#define MXC_CCM_PMCR0_DFSUP1_OFFSET 31
+
+#endif                          /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
new file mode 100644
index 000000000000..5c0320fce5b6
--- /dev/null
+++ b/arch/arm/mach-mx3/devices.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <linux/gpio.h>
+#include <asm/hardware.h>
+#include <asm/arch/imx-uart.h>
+
+static struct resource uart0[] = {
+        {
+                .start = UART1_BASE_ADDR,
+                .end = UART1_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART1,
+                .end = MXC_INT_UART1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device0 = {
+        .name = "imx-uart",
+        .id = 0,
+        .resource = uart0,
+        .num_resources = ARRAY_SIZE(uart0),
+};
+
+static struct resource uart1[] = {
+        {
+                .start = UART2_BASE_ADDR,
+                .end = UART2_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART2,
+                .end = MXC_INT_UART2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device1 = {
+        .name = "imx-uart",
+        .id = 1,
+        .resource = uart1,
+        .num_resources = ARRAY_SIZE(uart1),
+};
+
+static struct resource uart2[] = {
+        {
+                .start = UART3_BASE_ADDR,
+                .end = UART3_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART3,
+                .end = MXC_INT_UART3,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device2 = {
+        .name = "imx-uart",
+        .id = 2,
+        .resource = uart2,
+        .num_resources = ARRAY_SIZE(uart2),
+};
+
+static struct resource uart3[] = {
+        {
+                .start = UART4_BASE_ADDR,
+                .end = UART4_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART4,
+                .end = MXC_INT_UART4,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device3 = {
+        .name = "imx-uart",
+        .id = 3,
+        .resource = uart3,
+        .num_resources = ARRAY_SIZE(uart3),
+};
+
+static struct resource uart4[] = {
+        {
+                .start = UART5_BASE_ADDR,
+                .end = UART5_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART5,
+                .end = MXC_INT_UART5,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device4 = {
+        .name = "imx-uart",
+        .id = 4,
+        .resource = uart4,
+        .num_resources = ARRAY_SIZE(uart4),
+};
+
+/*
+ * Register only those UARTs that physically exist
+ */
+int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata)
+{
+        switch (uart_no) {
+        case 0:
+                mxc_uart_device0.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device0);
+                break;
+        case 1:
+                mxc_uart_device1.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device1);
+                break;
+        case 2:
+                mxc_uart_device2.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device2);
+                break;
+        case 3:
+                mxc_uart_device3.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device3);
+                break;
+        case 4:
+                mxc_uart_device4.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device4);
+                break;
+        default:
+                return -ENODEV;
+        }
+
+        return 0;
+}
+
+/* GPIO port description */
+static struct mxc_gpio_port imx_gpio_ports[] = {
+        [0] = {
+                .chip.label = "gpio-0",
+                .base = IO_ADDRESS(GPIO1_BASE_ADDR),
+                .irq = MXC_INT_GPIO1,
+                .virtual_irq_start = MXC_GPIO_INT_BASE
+        },
+        [1] = {
+                .chip.label = "gpio-1",
+                .base = IO_ADDRESS(GPIO2_BASE_ADDR),
+                .irq = MXC_INT_GPIO2,
+                .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN
+        },
+        [2] = {
+                .chip.label = "gpio-2",
+                .base = IO_ADDRESS(GPIO3_BASE_ADDR),
+                .irq = MXC_INT_GPIO3,
+                .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 2
+        }
+};
+
+int __init mxc_register_gpios(void)
+{
+        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
+}
diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c
new file mode 100644
index 000000000000..adc51feefc1d
--- /dev/null
+++ b/arch/arm/mach-mx3/iomux.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <asm/hardware.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/iomux-mx3.h>
+
+/*
+ * IOMUX register (base) addresses
+ */
+#define IOMUX_BASE      IO_ADDRESS(IOMUXC_BASE_ADDR)
+#define IOMUXINT_OBS1   (IOMUX_BASE + 0x000)
+#define IOMUXINT_OBS2   (IOMUX_BASE + 0x004)
+#define IOMUXGPR        (IOMUX_BASE + 0x008)
+#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C)
+#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154)
+
+static DEFINE_SPINLOCK(gpio_mux_lock);
+
+#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
+/*
+ * set the mode for a IOMUX pin.
+ */
+int mxc_iomux_mode(unsigned int pin_mode)
+{
+        u32 reg, field, l, mode, ret = 0;
+
+        reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
+        field = pin_mode & 0x3;
+        mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
+
+        pr_debug("%s: reg offset = 0x%x field = %d mode = 0x%02x\n",
+                        __func__, (pin_mode & IOMUX_REG_MASK), field, mode);
+
+        spin_lock(&gpio_mux_lock);
+
+        l = __raw_readl(reg);
+        l &= ~(0xff << (field * 8));
+        l |= mode << (field * 8);
+        __raw_writel(l, reg);
+
+        spin_unlock(&gpio_mux_lock);
+
+        return ret;
+}
+EXPORT_SYMBOL(mxc_iomux_mode);
+
+/*
+ * This function configures the pad value for a IOMUX pin.
+ */
+void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
+{
+        u32 reg, field, l;
+
+        reg = IOMUXSW_PAD_CTL + (pin + 2) / 3;
+        field = (pin + 2) % 3;
+
+        pr_debug("%s: reg offset = 0x%x field = %d\n",
+                        __func__, (pin + 2) / 3, field);
+
+        spin_lock(&gpio_mux_lock);
+
+        l = __raw_readl(reg);
+        l &= ~(0x1ff << (field * 9));
+        l |= config << (field * 9);
+        __raw_writel(l, reg);
+
+        spin_unlock(&gpio_mux_lock);
+}
+EXPORT_SYMBOL(mxc_iomux_set_pad);
+
+/*
+ * This function enables/disables the general purpose function for a particular
+ * signal.
+ */
+void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
+{
+        u32 l;
+
+        spin_lock(&gpio_mux_lock);
+        l = __raw_readl(IOMUXGPR);
+        if (en)
+                l |= gp;
+        else
+                l &= ~gp;
+
+        __raw_writel(l, IOMUXGPR);
+        spin_unlock(&gpio_mux_lock);
+}
+EXPORT_SYMBOL(mxc_iomux_set_gpr);
+
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
index 7e89bdc23a9f..eba3e0cd4283 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -26,9 +26,11 @@
 #include <asm/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <asm/arch/common.h>
+#include <asm/arch/board-mx31ads.h>
 
 /*!
  * @file mx31ads.c
@@ -126,6 +128,16 @@ static void __init mxc_board_init(void)
         mxc_init_extuart();
 }
 
+static void __init mx31ads_timer_init(void)
+{
+        mxc_clocks_init(26000000);
+        mxc_timer_init("ipg_clk.0");
+}
+
+struct sys_timer mx31ads_timer = {
+        .init   = mx31ads_timer_init,
+};
+
 /*
  * The following uses standard kernel macros defined in arch.h in order to
  * initialize __mach_desc_MX31ADS data structure.
@@ -138,5 +150,5 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS")
         .map_io         = mx31ads_map_io,
         .init_irq       = mxc_init_irq,
         .init_machine   = mxc_board_init,
-        .timer          = &mxc_timer,
+        .timer          = &mx31ads_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
new file mode 100644
index 000000000000..1372c1a1fc3f
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31lite.c
@@ -0,0 +1,107 @@
+/*
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/memory.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <asm/arch/common.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+#include <asm/arch/board-mx31lite.h>
+
+/*
+ * This file contains the board-specific initialization routines.
+ */
+
+/*
+ * This structure defines the MX31 memory map.
+ */
+static struct map_desc mx31lite_io_desc[] __initdata = {
+        {
+                .virtual = AIPS1_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
+                .length = AIPS1_SIZE,
+                .type = MT_NONSHARED_DEVICE
+        }, {
+                .virtual = SPBA0_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
+                .length = SPBA0_SIZE,
+                .type = MT_NONSHARED_DEVICE
+        }, {
+                .virtual = AIPS2_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
+                .length = AIPS2_SIZE,
+                .type = MT_NONSHARED_DEVICE
+        }, {
+                .virtual = CS4_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(CS4_BASE_ADDR),
+                .length = CS4_SIZE,
+                .type = MT_DEVICE
+        }
+};
+
+/*
+ * Set up static virtual mappings.
+ */
+void __init mx31lite_map_io(void)
+{
+        mxc_map_io();
+        iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
+}
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+}
+
+static void __init mx31lite_timer_init(void)
+{
+        mxc_clocks_init(26000000);
+        mxc_timer_init("ipg_clk.0");
+}
+
+struct sys_timer mx31lite_timer = {
+        .init   = mx31lite_timer_init,
+};
+
+/*
+ * The following uses standard kernel macros defined in arch.h in order to
+ * initialize __mach_desc_MX31LITE data structure.
+ */
+
+MACHINE_START(MX31LITE, "LogicPD MX31 LITEKIT")
+        /* Maintainer: Freescale Semiconductor, Inc. */
+        .phys_io        = AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx31lite_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = mxc_board_init,
+        .timer          = &mx31lite_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c
new file mode 100644
index 000000000000..a34ae6de266f
--- /dev/null
+++ b/arch/arm/mach-mx3/pcm037.c
@@ -0,0 +1,130 @@
+/*
+ *  Copyright (C) 2008 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/memory.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <asm/arch/common.h>
+#include <asm/arch/imx-uart.h>
+#include <asm/arch/iomux-mx3.h>
+#include <asm/arch/board-pcm037.h>
+
+static struct physmap_flash_data pcm037_flash_data = {
+        .width  = 2,
+};
+
+static struct resource pcm037_flash_resource = {
+        .start  = 0xa0000000,
+        .end    = 0xa1ffffff,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device pcm037_flash = {
+        .name   = "physmap-flash",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &pcm037_flash_data,
+        },
+        .resource = &pcm037_flash_resource,
+        .num_resources = 1,
+};
+
+static struct imxuart_platform_data uart_pdata = {
+        .flags = 0,
+};
+
+static struct platform_device *devices[] __initdata = {
+        &pcm037_flash,
+};
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+
+        mxc_iomux_mode(MX31_PIN_CTS1__CTS1);
+        mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
+        mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
+        mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
+
+        imx_init_uart(0, &uart_pdata);
+
+        mxc_iomux_mode(MX31_PIN_CSPI3_MOSI__RXD3);
+        mxc_iomux_mode(MX31_PIN_CSPI3_MISO__TXD3);
+
+        imx_init_uart(2, &uart_pdata);
+}
+
+/*
+ * This structure defines static mappings for the pcm037 board.
+ */
+static struct map_desc pcm037_io_desc[] __initdata = {
+        {
+                .virtual        = AIPS1_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(AIPS1_BASE_ADDR),
+                .length         = AIPS1_SIZE,
+                .type           = MT_DEVICE
+        }, {
+                .virtual        = AIPS2_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(AIPS2_BASE_ADDR),
+                .length         = AIPS2_SIZE,
+                .type           = MT_DEVICE
+        },
+};
+
+/*
+ * Set up static virtual mappings.
+ */
+void __init pcm037_map_io(void)
+{
+        mxc_map_io();
+        iotable_init(pcm037_io_desc, ARRAY_SIZE(pcm037_io_desc));
+}
+
+static void __init pcm037_timer_init(void)
+{
+        mxc_clocks_init(26000000);
+        mxc_timer_init("ipg_clk.0");
+}
+
+struct sys_timer pcm037_timer = {
+        .init   = pcm037_timer_init,
+};
+
+MACHINE_START(PCM037, "Phytec Phycore pcm037")
+        /* Maintainer: Pengutronix */
+        .phys_io        = AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = pcm037_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = mxc_board_init,
+        .timer          = &pcm037_timer,
+MACHINE_END
+
diff --git a/arch/arm/mach-mx3/time.c b/arch/arm/mach-mx3/time.c
deleted file mode 100644
index fb565c98dbfb..000000000000
--- a/arch/arm/mach-mx3/time.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * System Timer Interrupt reconfigured to run in free-run mode.
- * Author: Vitaly Wool
- * Copyright 2004 MontaVista Software Inc.
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/*!
- * @file time.c
- * @brief This file contains OS tick and wdog timer implementations.
- *
- * This file contains OS tick and wdog timer implementations.
- *
- * @ingroup Timers
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <asm/hardware.h>
-#include <asm/mach/time.h>
-#include <asm/io.h>
-#include <asm/arch/common.h>
-
-/*!
- * This is the timer interrupt service routine to do required tasks.
- * It also services the WDOG timer at the frequency of twice per WDOG
- * timeout value. For example, if the WDOG's timeout value is 4 (2
- * seconds since the WDOG runs at 0.5Hz), it will be serviced once
- * every 2/2=1 second.
- *
- * @param  irq          GPT interrupt source number (not used)
- * @param  dev_id       this parameter is not used
- * @return always returns \b IRQ_HANDLED as defined in
- *         include/linux/interrupt.h.
- */
-static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
-{
-        unsigned int next_match;
-
-        if (__raw_readl(MXC_GPT_GPTSR) & GPTSR_OF1) {
-                do {
-                        timer_tick();
-                        next_match = __raw_readl(MXC_GPT_GPTOCR1) + LATCH;
-                        __raw_writel(GPTSR_OF1, MXC_GPT_GPTSR);
-                        __raw_writel(next_match, MXC_GPT_GPTOCR1);
-                } while ((signed long)(next_match -
-                                       __raw_readl(MXC_GPT_GPTCNT)) <= 0);
-        }
-
-        return IRQ_HANDLED;
-}
-
-/*!
- * This function is used to obtain the number of microseconds since the last
- * timer interrupt. Note that interrupts is disabled by do_gettimeofday().
- *
- * @return the number of microseconds since the last timer interrupt.
- */
-static unsigned long mxc_gettimeoffset(void)
-{
-        unsigned long ticks_to_match, elapsed, usec, tick_usec, i;
-
-        /* Get ticks before next timer match */
-        ticks_to_match =
-            __raw_readl(MXC_GPT_GPTOCR1) - __raw_readl(MXC_GPT_GPTCNT);
-
-        /* We need elapsed ticks since last match */
-        elapsed = LATCH - ticks_to_match;
-
-        /* Now convert them to usec */
-        /* Insure no overflow when calculating the usec below */
-        for (i = 1, tick_usec = tick_nsec / 1000;; i *= 2) {
-                tick_usec /= i;
-                if ((0xFFFFFFFF / tick_usec) > elapsed)
-                        break;
-        }
-        usec = (unsigned long)(elapsed * tick_usec) / (LATCH / i);
-
-        return usec;
-}
-
-/*!
- * The OS tick timer interrupt structure.
- */
-static struct irqaction timer_irq = {
-        .name = "MXC Timer Tick",
-        .flags = IRQF_DISABLED | IRQF_TIMER,
-        .handler = mxc_timer_interrupt
-};
-
-/*!
- * This function is used to initialize the GPT to produce an interrupt
- * based on HZ.  It is called by start_kernel() during system startup.
- */
-void __init mxc_init_time(void)
-{
-        u32 reg, v;
-        reg = __raw_readl(MXC_GPT_GPTCR);
-        reg &= ~GPTCR_ENABLE;
-        __raw_writel(reg, MXC_GPT_GPTCR);
-        reg |= GPTCR_SWR;
-        __raw_writel(reg, MXC_GPT_GPTCR);
-
-        while ((__raw_readl(MXC_GPT_GPTCR) & GPTCR_SWR) != 0)
-                cpu_relax();
-
-        reg = GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ;
-        __raw_writel(reg, MXC_GPT_GPTCR);
-
-        /* TODO: get timer rate from clk driver */
-        v = 66500000;
-
-        __raw_writel((v / CLOCK_TICK_RATE) - 1, MXC_GPT_GPTPR);
-
-        if ((v % CLOCK_TICK_RATE) != 0) {
-                pr_info("\nWARNING: Can't generate CLOCK_TICK_RATE at %d Hz\n",
-                        CLOCK_TICK_RATE);
-        }
-        pr_info("Actual CLOCK_TICK_RATE is %d Hz\n",
-                v / ((__raw_readl(MXC_GPT_GPTPR) & 0xFFF) + 1));
-
-        reg = __raw_readl(MXC_GPT_GPTCNT);
-        reg += LATCH;
-        __raw_writel(reg, MXC_GPT_GPTOCR1);
-
-        setup_irq(MXC_INT_GPT, &timer_irq);
-
-        reg = __raw_readl(MXC_GPT_GPTCR);
-        reg =
-            GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ | GPTCR_STOPEN | GPTCR_DOZEN |
-            GPTCR_WAITEN | GPTCR_ENMOD | GPTCR_ENABLE;
-        __raw_writel(reg, MXC_GPT_GPTCR);
-
-        __raw_writel(GPTIR_OF1IE, MXC_GPT_GPTIR);
-}
-
-struct sys_timer mxc_timer = {
-        .init = mxc_init_time,
-        .offset = mxc_gettimeoffset,
-};
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index c06f5254c0f3..1bda8f5d7546 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -3,7 +3,9 @@
 #
 
 # Common support
-obj-y := io.o id.o clock.o irq.o mux.o serial.o devices.o
+obj-y := io.o id.o sram.o clock.o irq.o mux.o serial.o devices.o
+
+obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 
 obj-$(CONFIG_OMAP_MPU_TIMER)    += time.o
 obj-$(CONFIG_OMAP_32K_TIMER)    += timer32k.o
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index bcb984f2300f..3f39e0e79c9f 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -10,6 +10,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/mutex.h>
 #include <linux/platform_device.h>
 #include <linux/input.h>
 #include <linux/clk.h>
@@ -202,7 +203,7 @@ static struct omap_board_config_kernel nokia770_config[] __initdata = {
 #define AMPLIFIER_CTRL_GPIO     58
 
 static struct clk *dspxor_ck;
-static DECLARE_MUTEX(audio_pwr_sem);
+static DEFINE_MUTEX(audio_pwr_lock);
 /*
  * audio_pwr_state
  * +--+-------------------------+---------------------------------------+
@@ -218,7 +219,7 @@ static DECLARE_MUTEX(audio_pwr_sem);
 static int audio_pwr_state = -1;
 
 /*
- * audio_pwr_up / down should be called under audio_pwr_sem
+ * audio_pwr_up / down should be called under audio_pwr_lock
  */
 static void nokia770_audio_pwr_up(void)
 {
@@ -237,11 +238,11 @@ static void nokia770_audio_pwr_up(void)
 
 static void codec_delayed_power_down(struct work_struct *work)
 {
-        down(&audio_pwr_sem);
+        mutex_lock(&audio_pwr_lock);
         if (audio_pwr_state == -1)
                 aic23_power_down();
         clk_disable(dspxor_ck);
-        up(&audio_pwr_sem);
+        mutex_unlock(&audio_pwr_lock);
 }
 
 static DECLARE_DELAYED_WORK(codec_power_down_work, codec_delayed_power_down);
@@ -258,19 +259,19 @@ static void nokia770_audio_pwr_down(void)
 static int
 nokia770_audio_pwr_up_request(struct dsp_kfunc_device *kdev, int stage)
 {
-        down(&audio_pwr_sem);
+        mutex_lock(&audio_pwr_lock);
         if (audio_pwr_state == -1)
                 nokia770_audio_pwr_up();
         /* force audio_pwr_state = 0, even if it was 1. */
         audio_pwr_state = 0;
-        up(&audio_pwr_sem);
+        mutex_unlock(&audio_pwr_lock);
         return 0;
 }
 
 static int
 nokia770_audio_pwr_down_request(struct dsp_kfunc_device *kdev, int stage)
 {
-        down(&audio_pwr_sem);
+        mutex_lock(&audio_pwr_lock);
         switch (stage) {
         case 1:
                 if (audio_pwr_state == 0)
@@ -283,7 +284,7 @@ nokia770_audio_pwr_down_request(struct dsp_kfunc_device *kdev, int stage)
                 }
                 break;
         }
-        up(&audio_pwr_sem);
+        mutex_unlock(&audio_pwr_lock);
         return 0;
 }
 
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index a66505f58b15..845c66371ca3 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -267,13 +267,17 @@ static struct i2c_board_info __initdata osk_i2c_board_info[] = {
 
 static void __init osk_init_smc91x(void)
 {
+        u32 l;
+
         if ((gpio_request(0, "smc_irq")) < 0) {
                 printk("Error requesting gpio 0 for smc91x irq\n");
                 return;
         }
 
         /* Check EMIFS wait states to fix errors with SMC_GET_PKT_HDR */
-        EMIFS_CCS(1) |= 0x3;
+        l = omap_readl(EMIFS_CCS(1));
+        l |= 0x3;
+        omap_writel(l, EMIFS_CCS(1));
 }
 
 static void __init osk_init_cf(void)
@@ -526,20 +530,26 @@ static void __init osk_mistral_init(void) { }
 
 static void __init osk_init(void)
 {
+        u32 l;
+
         /* Workaround for wrong CS3 (NOR flash) timing
          * There are some U-Boot versions out there which configure
          * wrong CS3 memory timings. This mainly leads to CRC
          * or similar errors if you use NOR flash (e.g. with JFFS2)
          */
-        if (EMIFS_CCS(3) != EMIFS_CS3_VAL)
-                EMIFS_CCS(3) = EMIFS_CS3_VAL;
+        l = omap_readl(EMIFS_CCS(3));
+        if (l != EMIFS_CS3_VAL)
+                omap_writel(EMIFS_CS3_VAL, EMIFS_CCS(3));
 
         osk_flash_resource.end = osk_flash_resource.start = omap_cs3_phys();
         osk_flash_resource.end += SZ_32M - 1;
         platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices));
         omap_board_config = osk_config;
         omap_board_config_size = ARRAY_SIZE(osk_config);
-        USB_TRANSCEIVER_CTRL_REG |= (3 << 1);
+
+        l = omap_readl(USB_TRANSCEIVER_CTRL);
+        l |= (3 << 1);
+        omap_writel(l, USB_TRANSCEIVER_CTRL);
 
         /* irq for tps65010 chip */
         /* bootloader effectively does:  omap_cfg_reg(U19_1610_MPUIO1); */
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 30e188109046..0cf62ef5ecb7 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -32,7 +32,7 @@
 
 static void fpga_mask_irq(unsigned int irq)
 {
-        irq -= OMAP1510_IH_FPGA_BASE;
+        irq -= OMAP_FPGA_IRQ_BASE;
 
         if (irq < 8)
                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
@@ -65,7 +65,7 @@ static void fpga_ack_irq(unsigned int irq)
 
 static void fpga_unmask_irq(unsigned int irq)
 {
-        irq -= OMAP1510_IH_FPGA_BASE;
+        irq -= OMAP_FPGA_IRQ_BASE;
 
         if (irq < 8)
                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
@@ -95,8 +95,8 @@ void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
         if (!stat)
                 return;
 
-        for (fpga_irq = OMAP1510_IH_FPGA_BASE;
-             (fpga_irq < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS)) && stat;
+        for (fpga_irq = OMAP_FPGA_IRQ_BASE;
+             (fpga_irq < OMAP_FPGA_IRQ_END) && stat;
              fpga_irq++, stat >>= 1) {
                 if (stat & 1) {
                         d = irq_desc + fpga_irq;
@@ -151,7 +151,7 @@ void omap1510_fpga_init_irq(void)
         __raw_writeb(0, OMAP1510_FPGA_IMR_HI);
         __raw_writeb(0, INNOVATOR_FPGA_IMR2);
 
-        for (i = OMAP1510_IH_FPGA_BASE; i < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS); i++) {
+        for (i = OMAP_FPGA_IRQ_BASE; i < OMAP_FPGA_IRQ_END; i++) {
 
                 if (i == OMAP1510_INT_FPGA_TS) {
                         /*
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
new file mode 100644
index 000000000000..2d2c2522b048
--- /dev/null
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -0,0 +1,280 @@
+/*
+ * linux/arch/arm/mach-omap1/mcbsp.c
+ *
+ * Copyright (C) 2008 Instituto Nokia de Tecnologia
+ * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Multichannel mode not supported.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include <asm/arch/dma.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mcbsp.h>
+#include <asm/arch/dsp_common.h>
+
+#define DPS_RSTCT2_PER_EN       (1 << 0)
+#define DSP_RSTCT2_WD_PER_EN    (1 << 1)
+
+struct mcbsp_internal_clk {
+        struct clk clk;
+        struct clk **childs;
+        int n_childs;
+};
+
+#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
+static void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
+{
+        const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" };
+        int i;
+
+        mclk->n_childs = ARRAY_SIZE(clk_names);
+        mclk->childs = kzalloc(mclk->n_childs * sizeof(struct clk *),
+                                GFP_KERNEL);
+
+        for (i = 0; i < mclk->n_childs; i++) {
+                /* We fake a platform device to get correct device id */
+                struct platform_device pdev;
+
+                pdev.dev.bus = &platform_bus_type;
+                pdev.id = mclk->clk.id;
+                mclk->childs[i] = clk_get(&pdev.dev, clk_names[i]);
+                if (IS_ERR(mclk->childs[i]))
+                        printk(KERN_ERR "Could not get clock %s (%d).\n",
+                                clk_names[i], mclk->clk.id);
+        }
+}
+
+static int omap_mcbsp_clk_enable(struct clk *clk)
+{
+        struct mcbsp_internal_clk *mclk = container_of(clk,
+                                        struct mcbsp_internal_clk, clk);
+        int i;
+
+        for (i = 0; i < mclk->n_childs; i++)
+                clk_enable(mclk->childs[i]);
+        return 0;
+}
+
+static void omap_mcbsp_clk_disable(struct clk *clk)
+{
+        struct mcbsp_internal_clk *mclk = container_of(clk,
+                                        struct mcbsp_internal_clk, clk);
+        int i;
+
+        for (i = 0; i < mclk->n_childs; i++)
+                clk_disable(mclk->childs[i]);
+}
+
+static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
+        {
+                .clk = {
+                        .name           = "mcbsp_clk",
+                        .id             = 1,
+                        .enable         = omap_mcbsp_clk_enable,
+                        .disable        = omap_mcbsp_clk_disable,
+                },
+        },
+        {
+                .clk = {
+                        .name           = "mcbsp_clk",
+                        .id             = 3,
+                        .enable         = omap_mcbsp_clk_enable,
+                        .disable        = omap_mcbsp_clk_disable,
+                },
+        },
+};
+
+#define omap_mcbsp_clks_size    ARRAY_SIZE(omap_mcbsp_clks)
+#else
+#define omap_mcbsp_clks_size    0
+static struct mcbsp_internal_clk __initdata *omap_mcbsp_clks;
+static inline void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
+{ }
+#endif
+
+static int omap1_mcbsp_check(unsigned int id)
+{
+        /* REVISIT: Check correctly for number of registered McBSPs */
+        if (cpu_is_omap730()) {
+                if (id > OMAP_MAX_MCBSP_COUNT - 2) {
+                       printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
+                                id + 1);
+                       return -ENODEV;
+                }
+                return 0;
+        }
+
+        if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
+                if (id > OMAP_MAX_MCBSP_COUNT - 1) {
+                        printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
+                                id + 1);
+                        return -ENODEV;
+                }
+                return 0;
+        }
+
+        return -ENODEV;
+}
+
+static void omap1_mcbsp_request(unsigned int id)
+{
+        /*
+         * On 1510, 1610 and 1710, McBSP1 and McBSP3
+         * are DSP public peripherals.
+         */
+        if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
+                omap_dsp_request_mem();
+                /*
+                 * DSP external peripheral reset
+                 * FIXME: This should be moved to dsp code
+                 */
+                __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
+                                DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
+        }
+}
+
+static void omap1_mcbsp_free(unsigned int id)
+{
+        if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
+                omap_dsp_release_mem();
+}
+
+static struct omap_mcbsp_ops omap1_mcbsp_ops = {
+        .check          = omap1_mcbsp_check,
+        .request        = omap1_mcbsp_request,
+        .free           = omap1_mcbsp_free,
+};
+
+#ifdef CONFIG_ARCH_OMAP730
+static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
+        {
+                .virt_base      = io_p2v(OMAP730_MCBSP1_BASE),
+                .dma_rx_sync    = OMAP_DMA_MCBSP1_RX,
+                .dma_tx_sync    = OMAP_DMA_MCBSP1_TX,
+                .rx_irq         = INT_730_McBSP1RX,
+                .tx_irq         = INT_730_McBSP1TX,
+                .ops            = &omap1_mcbsp_ops,
+        },
+        {
+                .virt_base      = io_p2v(OMAP730_MCBSP2_BASE),
+                .dma_rx_sync    = OMAP_DMA_MCBSP3_RX,
+                .dma_tx_sync    = OMAP_DMA_MCBSP3_TX,
+                .rx_irq         = INT_730_McBSP2RX,
+                .tx_irq         = INT_730_McBSP2TX,
+                .ops            = &omap1_mcbsp_ops,
+        },
+};
+#define OMAP730_MCBSP_PDATA_SZ          ARRAY_SIZE(omap730_mcbsp_pdata)
+#else
+#define omap730_mcbsp_pdata             NULL
+#define OMAP730_MCBSP_PDATA_SZ          0
+#endif
+
+#ifdef CONFIG_ARCH_OMAP15XX
+static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
+        {
+                .virt_base      = OMAP1510_MCBSP1_BASE,
+                .dma_rx_sync    = OMAP_DMA_MCBSP1_RX,
+                .dma_tx_sync    = OMAP_DMA_MCBSP1_TX,
+                .rx_irq         = INT_McBSP1RX,
+                .tx_irq         = INT_McBSP1TX,
+                .ops            = &omap1_mcbsp_ops,
+                .clk_name       = "mcbsp_clk",
+                },
+        {
+                .virt_base      = io_p2v(OMAP1510_MCBSP2_BASE),
+                .dma_rx_sync    = OMAP_DMA_MCBSP2_RX,
+                .dma_tx_sync    = OMAP_DMA_MCBSP2_TX,
+                .rx_irq         = INT_1510_SPI_RX,
+                .tx_irq         = INT_1510_SPI_TX,
+                .ops            = &omap1_mcbsp_ops,
+        },
+        {
+                .virt_base      = OMAP1510_MCBSP3_BASE,
+                .dma_rx_sync    = OMAP_DMA_MCBSP3_RX,
+                .dma_tx_sync    = OMAP_DMA_MCBSP3_TX,
+                .rx_irq         = INT_McBSP3RX,
+                .tx_irq         = INT_McBSP3TX,
+                .ops            = &omap1_mcbsp_ops,
+                .clk_name       = "mcbsp_clk",
+        },
+};
+#define OMAP15XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap15xx_mcbsp_pdata)
+#else
+#define omap15xx_mcbsp_pdata            NULL
+#define OMAP15XX_MCBSP_PDATA_SZ         0
+#endif
+
+#ifdef CONFIG_ARCH_OMAP16XX
+static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
+        {
+                .virt_base      = OMAP1610_MCBSP1_BASE,
+                .dma_rx_sync    = OMAP_DMA_MCBSP1_RX,
+                .dma_tx_sync    = OMAP_DMA_MCBSP1_TX,
+                .rx_irq         = INT_McBSP1RX,
+                .tx_irq         = INT_McBSP1TX,
+                .ops            = &omap1_mcbsp_ops,
+                .clk_name       = "mcbsp_clk",
+        },
+        {
+                .virt_base      = io_p2v(OMAP1610_MCBSP2_BASE),
+                .dma_rx_sync    = OMAP_DMA_MCBSP2_RX,
+                .dma_tx_sync    = OMAP_DMA_MCBSP2_TX,
+                .rx_irq         = INT_1610_McBSP2_RX,
+                .tx_irq         = INT_1610_McBSP2_TX,
+                .ops            = &omap1_mcbsp_ops,
+        },
+        {
+                .virt_base      = OMAP1610_MCBSP3_BASE,
+                .dma_rx_sync    = OMAP_DMA_MCBSP3_RX,
+                .dma_tx_sync    = OMAP_DMA_MCBSP3_TX,
+                .rx_irq         = INT_McBSP3RX,
+                .tx_irq         = INT_McBSP3TX,
+                .ops            = &omap1_mcbsp_ops,
+                .clk_name       = "mcbsp_clk",
+        },
+};
+#define OMAP16XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap16xx_mcbsp_pdata)
+#else
+#define omap16xx_mcbsp_pdata            NULL
+#define OMAP16XX_MCBSP_PDATA_SZ         0
+#endif
+
+int __init omap1_mcbsp_init(void)
+{
+        int i;
+
+        for (i = 0; i < omap_mcbsp_clks_size; i++) {
+                if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
+                        omap_mcbsp_clk_init(&omap_mcbsp_clks[i]);
+                        clk_register(&omap_mcbsp_clks[i].clk);
+                }
+        }
+
+        if (cpu_is_omap730())
+                omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata,
+                                                OMAP730_MCBSP_PDATA_SZ);
+
+        if (cpu_is_omap15xx())
+                omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
+                                                OMAP15XX_MCBSP_PDATA_SZ);
+
+        if (cpu_is_omap16xx())
+                omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata,
+                                                OMAP16XX_MCBSP_PDATA_SZ);
+
+        return omap_mcbsp_init();
+}
+
+arch_initcall(omap1_mcbsp_init);
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index e6c64e10b7ec..742f79e73bd7 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -116,13 +116,6 @@ void omap_pm_idle(void)
                 return;
         }
 
-        /*
-         * Since an interrupt may set up a timer, we don't want to
-         * reprogram the hardware timer with interrupts enabled.
-         * Re-enable interrupts only after returning from idle.
-         */
-        timer_dyn_reprogram();
-
 #ifdef CONFIG_OMAP_MPU_TIMER
 #warning Enable 32kHz OS timer in order to allow sleep states in idle
         use_idlect1 = use_idlect1 & ~(1 << 9);
diff --git a/arch/arm/plat-omap/sram-fn.S b/arch/arm/mach-omap1/sram.S
index 9e1813c77e05..126d252062d7 100644
--- a/arch/arm/plat-omap/sram-fn.S
+++ b/arch/arm/mach-omap1/sram.S
@@ -18,7 +18,7 @@
 /*
  * Reprograms ULPD and CKCTL.
  */
-ENTRY(sram_reprogram_clock)
+ENTRY(omap1_sram_reprogram_clock)
         stmfd   sp!, {r0 - r12, lr}             @ save registers on stack
 
         mov     r2, #IO_ADDRESS(DPLL_CTL) & 0xff000000
@@ -53,5 +53,5 @@ lock:	ldrh	r4, [r2], #0			@ read back dpll value
 
 out:
         ldmfd   sp!, {r0 - r12, pc}             @ restore regs and return
-ENTRY(sram_reprogram_clock_sz)
-        .word   . - sram_reprogram_clock
+ENTRY(omap1_sram_reprogram_clock_sz)
+        .word   . - omap1_sram_reprogram_clock
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 2feb6870b735..93ee990618ef 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,9 +3,15 @@
 #
 
 # Common support
-obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o clock.o mux.o \
+obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \
                 devices.o serial.o gpmc.o timer-gp.o
 
+obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
+
+# Functions loaded to SRAM
+obj-$(CONFIG_ARCH_OMAP2420)             += sram242x.o
+obj-$(CONFIG_ARCH_OMAP2430)             += sram243x.o
+
 # Power Management
 obj-$(CONFIG_PM) += pm.o sleep.o
 
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ab9fc57d25f1..15675bce8012 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -41,6 +41,24 @@
 
 #define MAX_CLOCK_ENABLE_WAIT           100000
 
+/* DPLL rate rounding: minimum DPLL multiplier, divider values */
+#define DPLL_MIN_MULTIPLIER             1
+#define DPLL_MIN_DIVIDER                1
+
+/* Possible error results from _dpll_test_mult */
+#define DPLL_MULT_UNDERFLOW             (1 << 0)
+
+/*
+ * Scale factor to mitigate roundoff errors in DPLL rate rounding.
+ * The higher the scale factor, the greater the risk of arithmetic overflow,
+ * but the closer the rounded rate to the target rate.  DPLL_SCALE_FACTOR
+ * must be a power of DPLL_SCALE_BASE.
+ */
+#define DPLL_SCALE_FACTOR               64
+#define DPLL_SCALE_BASE                 2
+#define DPLL_ROUNDING_VAL               ((DPLL_SCALE_BASE / 2) * \
+                                         (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
+
 u8 cpu_mask;
 
 /*-------------------------------------------------------------------------
@@ -95,7 +113,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
 {
         long long dpll_clk;
         u32 dpll_mult, dpll_div, dpll;
-        const struct dpll_data *dd;
+        struct dpll_data *dd;
 
         dd = clk->dpll_data;
         /* REVISIT: What do we return on error? */
@@ -603,7 +621,8 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
         clk->rate = clk->parent->rate / new_div;
 
         if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
-                __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
+                prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
+                        OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
                 wmb();
         }
 
@@ -723,6 +742,184 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
         return 0;
 }
 
+/* DPLL rate rounding code */
+
+/**
+ * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
+ * @clk: struct clk * of the DPLL
+ * @tolerance: maximum rate error tolerance
+ *
+ * Set the maximum DPLL rate error tolerance for the rate rounding
+ * algorithm.  The rate tolerance is an attempt to balance DPLL power
+ * saving (the least divider value "n") vs. rate fidelity (the least
+ * difference between the desired DPLL target rate and the rounded
+ * rate out of the algorithm).  So, increasing the tolerance is likely
+ * to decrease DPLL power consumption and increase DPLL rate error.
+ * Returns -EINVAL if provided a null clock ptr or a clk that is not a
+ * DPLL; or 0 upon success.
+ */
+int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
+{
+        if (!clk || !clk->dpll_data)
+                return -EINVAL;
+
+        clk->dpll_data->rate_tolerance = tolerance;
+
+        return 0;
+}
+
+static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n)
+{
+        unsigned long long num;
+
+        num = (unsigned long long)parent_rate * m;
+        do_div(num, n);
+        return num;
+}
+
+/*
+ * _dpll_test_mult - test a DPLL multiplier value
+ * @m: pointer to the DPLL m (multiplier) value under test
+ * @n: current DPLL n (divider) value under test
+ * @new_rate: pointer to storage for the resulting rounded rate
+ * @target_rate: the desired DPLL rate
+ * @parent_rate: the DPLL's parent clock rate
+ *
+ * This code tests a DPLL multiplier value, ensuring that the
+ * resulting rate will not be higher than the target_rate, and that
+ * the multiplier value itself is valid for the DPLL.  Initially, the
+ * integer pointed to by the m argument should be prescaled by
+ * multiplying by DPLL_SCALE_FACTOR.  The code will replace this with
+ * a non-scaled m upon return.  This non-scaled m will result in a
+ * new_rate as close as possible to target_rate (but not greater than
+ * target_rate) given the current (parent_rate, n, prescaled m)
+ * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
+ * non-scaled m attempted to underflow, which can allow the calling
+ * function to bail out early; or 0 upon success.
+ */
+static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
+                           unsigned long target_rate,
+                           unsigned long parent_rate)
+{
+        int flags = 0, carry = 0;
+
+        /* Unscale m and round if necessary */
+        if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
+                carry = 1;
+        *m = (*m / DPLL_SCALE_FACTOR) + carry;
+
+        /*
+         * The new rate must be <= the target rate to avoid programming
+         * a rate that is impossible for the hardware to handle
+         */
+        *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
+        if (*new_rate > target_rate) {
+                (*m)--;
+                *new_rate = 0;
+        }
+
+        /* Guard against m underflow */
+        if (*m < DPLL_MIN_MULTIPLIER) {
+                *m = DPLL_MIN_MULTIPLIER;
+                *new_rate = 0;
+                flags = DPLL_MULT_UNDERFLOW;
+        }
+
+        if (*new_rate == 0)
+                *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
+
+        return flags;
+}
+
+/**
+ * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
+ * @clk: struct clk * for a DPLL
+ * @target_rate: desired DPLL clock rate
+ *
+ * Given a DPLL, a desired target rate, and a rate tolerance, round
+ * the target rate to a possible, programmable rate for this DPLL.
+ * Rate tolerance is assumed to be set by the caller before this
+ * function is called.  Attempts to select the minimum possible n
+ * within the tolerance to reduce power consumption.  Stores the
+ * computed (m, n) in the DPLL's dpll_data structure so set_rate()
+ * will not need to call this (expensive) function again.  Returns ~0
+ * if the target rate cannot be rounded, either because the rate is
+ * too low or because the rate tolerance is set too tightly; or the
+ * rounded rate upon success.
+ */
+long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
+{
+        int m, n, r, e, scaled_max_m;
+        unsigned long scaled_rt_rp, new_rate;
+        int min_e = -1, min_e_m = -1, min_e_n = -1;
+
+        if (!clk || !clk->dpll_data)
+                return ~0;
+
+        pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
+                 "%ld\n", clk->name, target_rate);
+
+        scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
+        scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR;
+
+        clk->dpll_data->last_rounded_rate = 0;
+
+        for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
+
+                /* Compute the scaled DPLL multiplier, based on the divider */
+                m = scaled_rt_rp * n;
+
+                /*
+                 * Since we're counting n down, a m overflow means we can
+                 * can immediately skip to the next n
+                 */
+                if (m > scaled_max_m)
+                        continue;
+
+                r = _dpll_test_mult(&m, n, &new_rate, target_rate,
+                                    clk->parent->rate);
+
+                e = target_rate - new_rate;
+                pr_debug("clock: n = %d: m = %d: rate error is %d "
+                         "(new_rate = %ld)\n", n, m, e, new_rate);
+
+                if (min_e == -1 ||
+                    min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) {
+                        min_e = e;
+                        min_e_m = m;
+                        min_e_n = n;
+
+                        pr_debug("clock: found new least error %d\n", min_e);
+                }
+
+                /*
+                 * Since we're counting n down, a m underflow means we
+                 * can bail out completely (since as n decreases in
+                 * the next iteration, there's no way that m can
+                 * increase beyond the current m)
+                 */
+                if (r & DPLL_MULT_UNDERFLOW)
+                        break;
+        }
+
+        if (min_e < 0) {
+                pr_debug("clock: error: target rate or tolerance too low\n");
+                return ~0;
+        }
+
+        clk->dpll_data->last_rounded_m = min_e_m;
+        clk->dpll_data->last_rounded_n = min_e_n;
+        clk->dpll_data->last_rounded_rate =
+                _dpll_compute_new_rate(clk->parent->rate, min_e_m,  min_e_n);
+
+        pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
+                 min_e, min_e_m, min_e_n);
+        pr_debug("clock: final rate: %ld  (target rate: %ld)\n",
+                 clk->dpll_data->last_rounded_rate, target_rate);
+
+        return clk->dpll_data->last_rounded_rate;
+}
+
 /*-------------------------------------------------------------------------
  * Omap2 clock reset and init functions
  *-------------------------------------------------------------------------*/
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index d5980a9e09a4..3cd37cb57c5a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -18,11 +18,16 @@
 
 #include <asm/arch/clock.h>
 
+/* The maximum error between a target DPLL rate and the rounded rate in Hz */
+#define DEFAULT_DPLL_RATE_TOLERANCE     50000
+
 int omap2_clk_enable(struct clk *clk);
 void omap2_clk_disable(struct clk *clk);
 long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
 int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
+int omap2_dpll_rate_tolerance_set(struct clk *clk, unsigned int tolerance);
+long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
 void omap2_clk_disable_unused(struct clk *clk);
@@ -42,6 +47,7 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 u32 omap2_get_dpll_rate(struct clk *clk);
 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
+void omap2_clk_prepare_for_reboot(void);
 
 extern u8 cpu_mask;
 
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index ece32d8acba4..aa567876651d 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -154,7 +154,7 @@ static void omap2_clk_fixed_disable(struct clk *clk)
  * Uses the current prcm set to tell if a rate is valid.
  * You can go slower, but not faster within a given rate set.
  */
-static u32 omap2_dpll_round_rate(unsigned long target_rate)
+long omap2_dpllcore_round_rate(unsigned long target_rate)
 {
         u32 high, low, core_clk_src;
 
@@ -183,14 +183,14 @@ static u32 omap2_dpll_round_rate(unsigned long target_rate)
 
 }
 
-static void omap2_dpll_recalc(struct clk *clk)
+static void omap2_dpllcore_recalc(struct clk *clk)
 {
         clk->rate = omap2_get_dpll_rate_24xx(clk);
 
         propagate_rate(clk);
 }
 
-static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate)
+static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
 {
         u32 cur_rate, low, mult, div, valid_rate, done_rate;
         u32 bypass = 0;
@@ -209,7 +209,7 @@ static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate)
         } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
         } else if (rate != cur_rate) {
-                valid_rate = omap2_dpll_round_rate(rate);
+                valid_rate = omap2_dpllcore_round_rate(rate);
                 if (valid_rate != rate)
                         goto dpll_exit;
 
@@ -256,7 +256,7 @@ static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate)
                 omap2_init_memory_params(omap2_dll_force_needed());
                 omap2_reprogram_sdrc(done_rate, 0);
         }
-        omap2_dpll_recalc(&dpll_ck);
+        omap2_dpllcore_recalc(&dpll_ck);
         ret = 0;
 
 dpll_exit:
@@ -383,7 +383,7 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 
                 local_irq_restore(flags);
         }
-        omap2_dpll_recalc(&dpll_ck);
+        omap2_dpllcore_recalc(&dpll_ck);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 88081ed13f96..be4e25554e05 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -30,12 +30,12 @@ static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
 static void omap2_sys_clk_recalc(struct clk *clk);
 static void omap2_osc_clk_recalc(struct clk *clk);
 static void omap2_sys_clk_recalc(struct clk *clk);
-static void omap2_dpll_recalc(struct clk *clk);
+static void omap2_dpllcore_recalc(struct clk *clk);
 static int omap2_clk_fixed_enable(struct clk *clk);
 static void omap2_clk_fixed_disable(struct clk *clk);
 static int omap2_enable_osc_ck(struct clk *clk);
 static void omap2_disable_osc_ck(struct clk *clk);
-static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
+static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
 
 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
@@ -665,20 +665,27 @@ static struct clk alt_ck = {		/* Typical 54M or 48M, may not exist */
  * deal with this
  */
 
-static const struct dpll_data dpll_dd = {
+static struct dpll_data dpll_dd = {
         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
+        .max_multiplier         = 1024,
+        .max_divider            = 16,
+        .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
+/*
+ * XXX Cannot add round_rate here yet, as this is still a composite clock,
+ * not just a DPLL
+ */
 static struct clk dpll_ck = {
         .name           = "dpll_ck",
         .parent         = &sys_ck,              /* Can be func_32k also */
         .dpll_data      = &dpll_dd,
         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
                                 RATE_PROPAGATES | ALWAYS_ENABLED,
-        .recalc         = &omap2_dpll_recalc,
-        .set_rate       = &omap2_reprogram_dpll,
+        .recalc         = &omap2_dpllcore_recalc,
+        .set_rate       = &omap2_reprogram_dpllcore,
 };
 
 static struct clk apll96_ck = {
@@ -1747,7 +1754,8 @@ static struct clk gpt12_fck = {
 };
 
 static struct clk mcbsp1_ick = {
-        .name           = "mcbsp1_ick",
+        .name           = "mcbsp_ick",
+        .id             = 1,
         .parent         = &l4_ck,
         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1756,7 +1764,8 @@ static struct clk mcbsp1_ick = {
 };
 
 static struct clk mcbsp1_fck = {
-        .name           = "mcbsp1_fck",
+        .name           = "mcbsp_fck",
+        .id             = 1,
         .parent         = &func_96m_ck,
         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1765,7 +1774,8 @@ static struct clk mcbsp1_fck = {
 };
 
 static struct clk mcbsp2_ick = {
-        .name           = "mcbsp2_ick",
+        .name           = "mcbsp_ick",
+        .id             = 2,
         .parent         = &l4_ck,
         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1774,7 +1784,8 @@ static struct clk mcbsp2_ick = {
 };
 
 static struct clk mcbsp2_fck = {
-        .name           = "mcbsp2_fck",
+        .name           = "mcbsp_fck",
+        .id             = 2,
         .parent         = &func_96m_ck,
         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1783,7 +1794,8 @@ static struct clk mcbsp2_fck = {
 };
 
 static struct clk mcbsp3_ick = {
-        .name           = "mcbsp3_ick",
+        .name           = "mcbsp_ick",
+        .id             = 3,
         .parent         = &l4_ck,
         .flags          = CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1792,7 +1804,8 @@ static struct clk mcbsp3_ick = {
 };
 
 static struct clk mcbsp3_fck = {
-        .name           = "mcbsp3_fck",
+        .name           = "mcbsp_fck",
+        .id             = 3,
         .parent         = &func_96m_ck,
         .flags          = CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1801,7 +1814,8 @@ static struct clk mcbsp3_fck = {
 };
 
 static struct clk mcbsp4_ick = {
-        .name           = "mcbsp4_ick",
+        .name           = "mcbsp_ick",
+        .id             = 4,
         .parent         = &l4_ck,
         .flags          = CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1810,7 +1824,8 @@ static struct clk mcbsp4_ick = {
 };
 
 static struct clk mcbsp4_fck = {
-        .name           = "mcbsp4_fck",
+        .name           = "mcbsp_fck",
+        .id             = 4,
         .parent         = &func_96m_ck,
         .flags          = CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1819,7 +1834,8 @@ static struct clk mcbsp4_fck = {
 };
 
 static struct clk mcbsp5_ick = {
-        .name           = "mcbsp5_ick",
+        .name           = "mcbsp_ick",
+        .id             = 5,
         .parent         = &l4_ck,
         .flags          = CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1828,7 +1844,8 @@ static struct clk mcbsp5_ick = {
 };
 
 static struct clk mcbsp5_fck = {
-        .name           = "mcbsp5_fck",
+        .name           = "mcbsp_fck",
+        .id             = 5,
         .parent         = &func_96m_ck,
         .flags          = CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index b42bdd6079a5..4263099b1ad3 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -1,10 +1,11 @@
 /*
  * OMAP3-specific clock framework functions
  *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
  *
  * Written by Paul Walmsley
+ * Testing and integration fixes by Jouni Högander
  *
  * Parts of this code are based on code written by
  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
@@ -23,6 +24,7 @@
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/limits.h>
 
 #include <asm/arch/clock.h>
 #include <asm/arch/sram.h>
@@ -37,8 +39,11 @@
 #include "cm.h"
 #include "cm-regbits-34xx.h"
 
-/* CM_CLKEN_PLL*.EN* bit values */
-#define DPLL_LOCKED             0x7
+/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
+#define DPLL_AUTOIDLE_DISABLE                   0x0
+#define DPLL_AUTOIDLE_LOW_POWER_STOP            0x1
+
+#define MAX_DPLL_WAIT_TRIES             1000000
 
 /**
  * omap3_dpll_recalc - recalculate DPLL rate
@@ -53,6 +58,290 @@ static void omap3_dpll_recalc(struct clk *clk)
         propagate_rate(clk);
 }
 
+/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
+static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
+{
+        const struct dpll_data *dd;
+
+        dd = clk->dpll_data;
+
+        cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask),
+                        dd->control_reg);
+}
+
+/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
+static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
+{
+        const struct dpll_data *dd;
+        int i = 0;
+        int ret = -EINVAL;
+        u32 idlest_mask;
+
+        dd = clk->dpll_data;
+
+        state <<= dd->idlest_bit;
+        idlest_mask = 1 << dd->idlest_bit;
+
+        while (((cm_read_reg(dd->idlest_reg) & idlest_mask) != state) &&
+               i < MAX_DPLL_WAIT_TRIES) {
+                i++;
+                udelay(1);
+        }
+
+        if (i == MAX_DPLL_WAIT_TRIES) {
+                printk(KERN_ERR "clock: %s failed transition to '%s'\n",
+                       clk->name, (state) ? "locked" : "bypassed");
+        } else {
+                pr_debug("clock: %s transition to '%s' in %d loops\n",
+                         clk->name, (state) ? "locked" : "bypassed", i);
+
+                ret = 0;
+        }
+
+        return ret;
+}
+
+/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
+
+/*
+ * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to lock.  Waits for the DPLL to report
+ * readiness before returning.  Will save and restore the DPLL's
+ * autoidle state across the enable, per the CDP code.  If the DPLL
+ * locked successfully, return 0; if the DPLL did not lock in the time
+ * allotted, or DPLL3 was passed in, return -EINVAL.
+ */
+static int _omap3_noncore_dpll_lock(struct clk *clk)
+{
+        u8 ai;
+        int r;
+
+        if (clk == &dpll3_ck)
+                return -EINVAL;
+
+        pr_debug("clock: locking DPLL %s\n", clk->name);
+
+        ai = omap3_dpll_autoidle_read(clk);
+
+        _omap3_dpll_write_clken(clk, DPLL_LOCKED);
+
+        if (ai) {
+                /*
+                 * If no downstream clocks are enabled, CM_IDLEST bit
+                 * may never become active, so don't wait for DPLL to lock.
+                 */
+                r = 0;
+                omap3_dpll_allow_idle(clk);
+        } else {
+                r = _omap3_wait_dpll_status(clk, 1);
+                omap3_dpll_deny_idle(clk);
+        };
+
+        return r;
+}
+
+/*
+ * omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
+ * bypass mode, the DPLL's rate is set equal to its parent clock's
+ * rate.  Waits for the DPLL to report readiness before returning.
+ * Will save and restore the DPLL's autoidle state across the enable,
+ * per the CDP code.  If the DPLL entered bypass mode successfully,
+ * return 0; if the DPLL did not enter bypass in the time allotted, or
+ * DPLL3 was passed in, or the DPLL does not support low-power bypass,
+ * return -EINVAL.
+ */
+static int _omap3_noncore_dpll_bypass(struct clk *clk)
+{
+        int r;
+        u8 ai;
+
+        if (clk == &dpll3_ck)
+                return -EINVAL;
+
+        if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
+                return -EINVAL;
+
+        pr_debug("clock: configuring DPLL %s for low-power bypass\n",
+                 clk->name);
+
+        ai = omap3_dpll_autoidle_read(clk);
+
+        _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
+
+        r = _omap3_wait_dpll_status(clk, 0);
+
+        if (ai)
+                omap3_dpll_allow_idle(clk);
+        else
+                omap3_dpll_deny_idle(clk);
+
+        return r;
+}
+
+/*
+ * _omap3_noncore_dpll_stop - instruct a DPLL to stop
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to enter low-power stop. Will save and
+ * restore the DPLL's autoidle state across the stop, per the CDP
+ * code.  If DPLL3 was passed in, or the DPLL does not support
+ * low-power stop, return -EINVAL; otherwise, return 0.
+ */
+static int _omap3_noncore_dpll_stop(struct clk *clk)
+{
+        u8 ai;
+
+        if (clk == &dpll3_ck)
+                return -EINVAL;
+
+        if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
+                return -EINVAL;
+
+        pr_debug("clock: stopping DPLL %s\n", clk->name);
+
+        ai = omap3_dpll_autoidle_read(clk);
+
+        _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
+
+        if (ai)
+                omap3_dpll_allow_idle(clk);
+        else
+                omap3_dpll_deny_idle(clk);
+
+        return 0;
+}
+
+/**
+ * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
+ * The choice of modes depends on the DPLL's programmed rate: if it is
+ * the same as the DPLL's parent clock, it will enter bypass;
+ * otherwise, it will enter lock.  This code will wait for the DPLL to
+ * indicate readiness before returning, unless the DPLL takes too long
+ * to enter the target state.  Intended to be used as the struct clk's
+ * enable function.  If DPLL3 was passed in, or the DPLL does not
+ * support low-power stop, or if the DPLL took too long to enter
+ * bypass or lock, return -EINVAL; otherwise, return 0.
+ */
+static int omap3_noncore_dpll_enable(struct clk *clk)
+{
+        int r;
+
+        if (clk == &dpll3_ck)
+                return -EINVAL;
+
+        if (clk->parent->rate == clk_get_rate(clk))
+                r = _omap3_noncore_dpll_bypass(clk);
+        else
+                r = _omap3_noncore_dpll_lock(clk);
+
+        return r;
+}
+
+/**
+ * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
+ * The choice of modes depends on the DPLL's programmed rate: if it is
+ * the same as the DPLL's parent clock, it will enter bypass;
+ * otherwise, it will enter lock.  This code will wait for the DPLL to
+ * indicate readiness before returning, unless the DPLL takes too long
+ * to enter the target state.  Intended to be used as the struct clk's
+ * enable function.  If DPLL3 was passed in, or the DPLL does not
+ * support low-power stop, or if the DPLL took too long to enter
+ * bypass or lock, return -EINVAL; otherwise, return 0.
+ */
+static void omap3_noncore_dpll_disable(struct clk *clk)
+{
+        if (clk == &dpll3_ck)
+                return;
+
+        _omap3_noncore_dpll_stop(clk);
+}
+
+/**
+ * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
+ * @clk: struct clk * of the DPLL to read
+ *
+ * Return the DPLL's autoidle bits, shifted down to bit 0.  Returns
+ * -EINVAL if passed a null pointer or if the struct clk does not
+ * appear to refer to a DPLL.
+ */
+static u32 omap3_dpll_autoidle_read(struct clk *clk)
+{
+        const struct dpll_data *dd;
+        u32 v;
+
+        if (!clk || !clk->dpll_data)
+                return -EINVAL;
+
+        dd = clk->dpll_data;
+
+        v = cm_read_reg(dd->autoidle_reg);
+        v &= dd->autoidle_mask;
+        v >>= __ffs(dd->autoidle_mask);
+
+        return v;
+}
+
+/**
+ * omap3_dpll_allow_idle - enable DPLL autoidle bits
+ * @clk: struct clk * of the DPLL to operate on
+ *
+ * Enable DPLL automatic idle control.  This automatic idle mode
+ * switching takes effect only when the DPLL is locked, at least on
+ * OMAP3430.  The DPLL will enter low-power stop when its downstream
+ * clocks are gated.  No return value.
+ */
+static void omap3_dpll_allow_idle(struct clk *clk)
+{
+        const struct dpll_data *dd;
+
+        if (!clk || !clk->dpll_data)
+                return;
+
+        dd = clk->dpll_data;
+
+        /*
+         * REVISIT: CORE DPLL can optionally enter low-power bypass
+         * by writing 0x5 instead of 0x1.  Add some mechanism to
+         * optionally enter this mode.
+         */
+        cm_rmw_reg_bits(dd->autoidle_mask,
+                        DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask),
+                        dd->autoidle_reg);
+}
+
+/**
+ * omap3_dpll_deny_idle - prevent DPLL from automatically idling
+ * @clk: struct clk * of the DPLL to operate on
+ *
+ * Disable DPLL automatic idle control.  No return value.
+ */
+static void omap3_dpll_deny_idle(struct clk *clk)
+{
+        const struct dpll_data *dd;
+
+        if (!clk || !clk->dpll_data)
+                return;
+
+        dd = clk->dpll_data;
+
+        cm_rmw_reg_bits(dd->autoidle_mask,
+                        DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask),
+                        dd->autoidle_reg);
+}
+
+/* Clock control for DPLL outputs */
+
 /**
  * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
  * @clk: DPLL output struct clk
@@ -89,6 +378,8 @@ static void omap3_clkoutx2_recalc(struct clk *clk)
                 propagate_rate(clk);
 }
 
+/* Common clock code */
+
 /*
  * As it is structured now, this will prevent an OMAP2/3 multiboot
  * kernel from compiling.  This will need further attention.
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index c9c5972a2e25..05757eb032bc 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1,14 +1,19 @@
 /*
  * OMAP3 clock framework
  *
- * Virtual clocks are introduced as a convenient tools.
- * They are sources for other clocks and not supposed
- * to be requested from drivers directly.
- *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
  * Copyright (C) 2007-2008 Nokia Corporation
  *
  * Written by Paul Walmsley
+ * With many device clock fixes by Kevin Hilman and Jouni Högander
+ * DPLL bypass clock support added by Roman Tereshonkov
+ *
+ */
+
+/*
+ * Virtual clocks are introduced as convenient tools.
+ * They are sources for other clocks and not supposed
+ * to be requested from drivers directly.
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
@@ -24,6 +29,15 @@
 
 static void omap3_dpll_recalc(struct clk *clk);
 static void omap3_clkoutx2_recalc(struct clk *clk);
+static void omap3_dpll_allow_idle(struct clk *clk);
+static void omap3_dpll_deny_idle(struct clk *clk);
+static u32 omap3_dpll_autoidle_read(struct clk *clk);
+static int omap3_noncore_dpll_enable(struct clk *clk);
+static void omap3_noncore_dpll_disable(struct clk *clk);
+
+/* Maximum DPLL multiplier, divider values for OMAP3 */
+#define OMAP3_MAX_DPLL_MULT             2048
+#define OMAP3_MAX_DPLL_DIV              128
 
 /*
  * DPLL1 supplies clock to the MPU.
@@ -33,6 +47,11 @@ static void omap3_clkoutx2_recalc(struct clk *clk);
  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  */
 
+/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
+#define DPLL_LOW_POWER_STOP             0x1
+#define DPLL_LOW_POWER_BYPASS           0x5
+#define DPLL_LOCKED                     0x7
+
 /* PRM CLOCKS */
 
 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
@@ -240,15 +259,23 @@ static const struct clksel_rate div16_dpll_rates[] = {
 /* DPLL1 */
 /* MPU clock source */
 /* Type: DPLL */
-static const struct dpll_data dpll1_dd = {
+static struct dpll_data dpll1_dd = {
         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+        .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+        .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll1_ck = {
@@ -256,6 +283,7 @@ static struct clk dpll1_ck = {
         .parent         = &sys_ck,
         .dpll_data      = &dpll1_dd,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .round_rate     = &omap2_dpll_round_rate,
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -297,22 +325,34 @@ static struct clk dpll1_x2m2_ck = {
 /* IVA2 clock source */
 /* Type: DPLL */
 
-static const struct dpll_data dpll2_dd = {
+static struct dpll_data dpll2_dd = {
         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
+                                (1 << DPLL_LOW_POWER_BYPASS),
         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+        .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
+        .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll2_ck = {
         .name           = "dpll2_ck",
         .parent         = &sys_ck,
         .dpll_data      = &dpll2_dd,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
+        .round_rate     = &omap2_dpll_round_rate,
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -338,10 +378,12 @@ static struct clk dpll2_m2_ck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
-/* DPLL3 */
-/* Source clock for all interfaces and for some device fclks */
-/* Type: DPLL */
-static const struct dpll_data dpll3_dd = {
+/*
+ * DPLL3
+ * Source clock for all interfaces and for some device fclks
+ * REVISIT: Also supports fast relock bypass - not included below
+ */
+static struct dpll_data dpll3_dd = {
         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
@@ -350,6 +392,11 @@ static const struct dpll_data dpll3_dd = {
         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+        .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll3_ck = {
@@ -357,6 +404,7 @@ static struct clk dpll3_ck = {
         .parent         = &sys_ck,
         .dpll_data      = &dpll3_dd,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .round_rate     = &omap2_dpll_round_rate,
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -439,7 +487,7 @@ static struct clk core_ck = {
         .name           = "core_ck",
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
         .clksel         = core_ck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                 PARENT_CONTROLS_CLOCK,
@@ -456,7 +504,7 @@ static struct clk dpll3_m2x2_ck = {
         .name           = "dpll3_m2x2_ck",
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
         .clksel         = dpll3_m2x2_ck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                 PARENT_CONTROLS_CLOCK,
@@ -503,7 +551,7 @@ static struct clk emu_core_alwon_ck = {
         .parent         = &dpll3_m3x2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
         .clksel         = emu_core_alwon_ck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                 PARENT_CONTROLS_CLOCK,
@@ -513,22 +561,33 @@ static struct clk emu_core_alwon_ck = {
 /* DPLL4 */
 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 /* Type: DPLL */
-static const struct dpll_data dpll4_dd = {
+static struct dpll_data dpll4_dd = {
         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll4_ck = {
         .name           = "dpll4_ck",
         .parent         = &sys_ck,
         .dpll_data      = &dpll4_dd,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
+        .round_rate     = &omap2_dpll_round_rate,
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -584,7 +643,7 @@ static struct clk omap_96m_alwon_fck = {
         .parent         = &dpll4_m2x2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .clksel         = omap_96m_alwon_fck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                  PARENT_CONTROLS_CLOCK,
@@ -610,7 +669,7 @@ static struct clk cm_96m_fck = {
         .parent         = &dpll4_m2x2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .clksel         = cm_96m_fck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                 PARENT_CONTROLS_CLOCK,
@@ -652,7 +711,7 @@ static struct clk virt_omap_54m_fck = {
         .parent         = &dpll4_m3x2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .clksel         = virt_omap_54m_fck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                 PARENT_CONTROLS_CLOCK,
@@ -804,23 +863,33 @@ static struct clk emu_per_alwon_ck = {
 /* Supplies 120MHz clock, USIM source clock */
 /* Type: DPLL */
 /* 3430ES2 only */
-static const struct dpll_data dpll5_dd = {
+static struct dpll_data dpll5_dd = {
         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
+        .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
+        .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll5_ck = {
         .name           = "dpll5_ck",
         .parent         = &sys_ck,
         .dpll_data      = &dpll5_dd,
-        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
-                                ALWAYS_ENABLED,
+        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
+        .round_rate     = &omap2_dpll_round_rate,
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -1365,7 +1434,8 @@ static const struct clksel mcbsp_15_clksel[] = {
 };
 
 static struct clk mcbsp5_fck = {
-        .name           = "mcbsp5_fck",
+        .name           = "mcbsp_fck",
+        .id             = 5,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
@@ -1377,7 +1447,8 @@ static struct clk mcbsp5_fck = {
 };
 
 static struct clk mcbsp1_fck = {
-        .name           = "mcbsp1_fck",
+        .name           = "mcbsp_fck",
+        .id             = 1,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
@@ -1789,7 +1860,8 @@ static struct clk gpt10_ick = {
 };
 
 static struct clk mcbsp5_ick = {
-        .name           = "mcbsp5_ick",
+        .name           = "mcbsp_ick",
+        .id             = 5,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
@@ -1798,7 +1870,8 @@ static struct clk mcbsp5_ick = {
 };
 
 static struct clk mcbsp1_ick = {
-        .name           = "mcbsp1_ick",
+        .name           = "mcbsp_ick",
+        .id             = 1,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
@@ -1935,7 +2008,7 @@ static struct clk dss1_alwon_fck = {
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .clksel         = dss1_alwon_fck_clksel,
         .flags          = CLOCK_IN_OMAP343X,
         .recalc         = &omap2_clksel_recalc,
@@ -1991,7 +2064,7 @@ static struct clk cam_mclk = {
         .parent         = &dpll4_m5x2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .clksel         = cam_mclk_clksel,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
@@ -2541,7 +2614,8 @@ static struct clk gpt2_ick = {
 };
 
 static struct clk mcbsp2_ick = {
-        .name           = "mcbsp2_ick",
+        .name           = "mcbsp_ick",
+        .id             = 2,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
@@ -2550,7 +2624,8 @@ static struct clk mcbsp2_ick = {
 };
 
 static struct clk mcbsp3_ick = {
-        .name           = "mcbsp3_ick",
+        .name           = "mcbsp_ick",
+        .id             = 3,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
@@ -2559,7 +2634,8 @@ static struct clk mcbsp3_ick = {
 };
 
 static struct clk mcbsp4_ick = {
-        .name           = "mcbsp4_ick",
+        .name           = "mcbsp_ick",
+        .id             = 4,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
@@ -2574,7 +2650,8 @@ static const struct clksel mcbsp_234_clksel[] = {
 };
 
 static struct clk mcbsp2_fck = {
-        .name           = "mcbsp2_fck",
+        .name           = "mcbsp_fck",
+        .id             = 2,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
@@ -2586,7 +2663,8 @@ static struct clk mcbsp2_fck = {
 };
 
 static struct clk mcbsp3_fck = {
-        .name           = "mcbsp3_fck",
+        .name           = "mcbsp_fck",
+        .id             = 3,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
@@ -2598,7 +2676,8 @@ static struct clk mcbsp3_fck = {
 };
 
 static struct clk mcbsp4_fck = {
-        .name           = "mcbsp4_fck",
+        .name           = "mcbsp_fck",
+        .id             = 4,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 3c38395f6442..ee4c0ca1a708 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -72,7 +72,8 @@
 #define OMAP3430_ST_IVA2                                (1 << 0)
 
 /* CM_IDLEST_PLL_IVA2 */
-#define OMAP3430_ST_IVA2_CLK                            (1 << 0)
+#define OMAP3430_ST_IVA2_CLK_SHIFT                      0
+#define OMAP3430_ST_IVA2_CLK_MASK                       (1 << 0)
 
 /* CM_AUTOIDLE_PLL_IVA2 */
 #define OMAP3430_AUTO_IVA2_DPLL_SHIFT                   0
@@ -115,10 +116,7 @@
 #define OMAP3430_ST_MPU                                 (1 << 0)
 
 /* CM_IDLEST_PLL_MPU */
-#define OMAP3430_ST_MPU_CLK                             (1 << 0)
-#define OMAP3430_ST_IVA2_CLK_MASK                       (1 << 0)
-
-/* CM_IDLEST_PLL_MPU */
+#define OMAP3430_ST_MPU_CLK_SHIFT                       0
 #define OMAP3430_ST_MPU_CLK_MASK                        (1 << 0)
 
 /* CM_AUTOIDLE_PLL_MPU */
@@ -408,8 +406,10 @@
 #define OMAP3430_ST_12M_CLK                             (1 << 4)
 #define OMAP3430_ST_48M_CLK                             (1 << 3)
 #define OMAP3430_ST_96M_CLK                             (1 << 2)
-#define OMAP3430_ST_PERIPH_CLK                          (1 << 1)
-#define OMAP3430_ST_CORE_CLK                            (1 << 0)
+#define OMAP3430_ST_PERIPH_CLK_SHIFT                    1
+#define OMAP3430_ST_PERIPH_CLK_MASK                     (1 << 1)
+#define OMAP3430_ST_CORE_CLK_SHIFT                      0
+#define OMAP3430_ST_CORE_CLK_MASK                       (1 << 0)
 
 /* CM_IDLEST2_CKGEN */
 #define OMAP3430ES2_ST_120M_CLK_SHIFT                   1
@@ -423,6 +423,10 @@
 #define OMAP3430_AUTO_CORE_DPLL_SHIFT                   0
 #define OMAP3430_AUTO_CORE_DPLL_MASK                    (0x7 << 0)
 
+/* CM_AUTOIDLE2_PLL */
+#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT             0
+#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK              (0x7 << 0)
+
 /* CM_CLKSEL1_PLL */
 /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT             27
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 8489f3029fed..87a44c715aa4 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -81,6 +81,7 @@
 #define OMAP3430ES2_CM_FCLKEN3                          0x0008
 #define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
 #define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
+#define OMAP3430ES2_CM_AUTOIDLE2_PLL                    CM_AUTOIDLE2
 #define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
 #define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
 #define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
@@ -96,15 +97,21 @@
 /* Clock management domain register get/set */
 
 #ifndef __ASSEMBLER__
-static inline void cm_write_mod_reg(u32 val, s16 module, s16 idx)
+
+extern u32 cm_read_mod_reg(s16 module, u16 idx);
+extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
+extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+
+static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
 {
-        __raw_writel(val, OMAP_CM_REGADDR(module, idx));
+        return cm_rmw_mod_reg_bits(bits, bits, module, idx);
 }
 
-static inline u32 cm_read_mod_reg(s16 module, s16 idx)
+static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 {
-        return __raw_readl(OMAP_CM_REGADDR(module, idx));
+        return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
 }
+
 #endif
 
 /* CM register bits shared between 24XX and 3430 */
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index a5d86a49c213..51f70300996f 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -13,22 +13,21 @@
 #undef DEBUG
 
 #include <linux/kernel.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
-
+#include <asm/arch/common.h>
 #include <asm/arch/control.h>
 
-static u32 omap2_ctrl_base;
+static void __iomem *omap2_ctrl_base;
 
-#define OMAP_CTRL_REGADDR(reg)  (void __iomem *)IO_ADDRESS(omap2_ctrl_base \
-                                                                + (reg))
+#define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
 
-void omap_ctrl_base_set(u32 base)
+void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
 {
-        omap2_ctrl_base = base;
+        omap2_ctrl_base = omap2_globals->ctrl;
 }
 
-u32 omap_ctrl_base_get(void)
+void __iomem *omap_ctrl_base_get(void)
 {
         return omap2_ctrl_base;
 }
@@ -50,25 +49,16 @@ u32 omap_ctrl_readl(u16 offset)
 
 void omap_ctrl_writeb(u8 val, u16 offset)
 {
-        pr_debug("omap_ctrl_writeb: writing 0x%0x to 0x%0x\n", val,
-                 (u32)OMAP_CTRL_REGADDR(offset));
-
         __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
 }
 
 void omap_ctrl_writew(u16 val, u16 offset)
 {
-        pr_debug("omap_ctrl_writew: writing 0x%0x to 0x%0x\n", val,
-                 (u32)OMAP_CTRL_REGADDR(offset));
-
         __raw_writew(val, OMAP_CTRL_REGADDR(offset));
 }
 
 void omap_ctrl_writel(u32 val, u16 offset)
 {
-        pr_debug("omap_ctrl_writel: writing 0x%0x to 0x%0x\n", val,
-                 (u32)OMAP_CTRL_REGADDR(offset));
-
         __raw_writel(val, OMAP_CTRL_REGADDR(offset));
 }
 
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 4dfd878d7968..dff4b16cead6 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -17,16 +17,23 @@
 
 #include <asm/io.h>
 
-#if defined(CONFIG_ARCH_OMAP2420)
-#define OMAP24XX_TAP_BASE       io_p2v(0x48014000)
-#endif
+#include <asm/arch/control.h>
+#include <asm/arch/cpu.h>
 
-#if defined(CONFIG_ARCH_OMAP2430)
-#define OMAP24XX_TAP_BASE       io_p2v(0x4900A000)
+#if defined(CONFIG_ARCH_OMAP2420)
+#define TAP_BASE        io_p2v(0x48014000)
+#elif defined(CONFIG_ARCH_OMAP2430)
+#define TAP_BASE        io_p2v(0x4900A000)
+#elif defined(CONFIG_ARCH_OMAP34XX)
+#define TAP_BASE        io_p2v(0x4830A000)
 #endif
 
 #define OMAP_TAP_IDCODE         0x0204
+#if defined(CONFIG_ARCH_OMAP34XX)
+#define OMAP_TAP_PROD_ID        0x0210
+#else
 #define OMAP_TAP_PROD_ID        0x0208
+#endif
 
 #define OMAP_TAP_DIE_ID_0       0x0218
 #define OMAP_TAP_DIE_ID_1       0x021C
@@ -56,9 +63,134 @@ static struct omap_id omap_ids[] __initdata = {
         { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
 };
 
+static struct omap_chip_id omap_chip;
+
+/**
+ * omap_chip_is - test whether currently running OMAP matches a chip type
+ * @oc: omap_chip_t to test against
+ *
+ * Test whether the currently-running OMAP chip matches the supplied
+ * chip type 'oc'.  Returns 1 upon a match; 0 upon failure.
+ */
+int omap_chip_is(struct omap_chip_id oci)
+{
+        return (oci.oc & omap_chip.oc) ? 1 : 0;
+}
+EXPORT_SYMBOL(omap_chip_is);
+
 static u32 __init read_tap_reg(int reg)
 {
-        return __raw_readl(OMAP24XX_TAP_BASE + reg);
+        unsigned int regval = 0;
+        u32 cpuid;
+
+        /* Reading the IDCODE register on 3430 ES1 results in a
+         * data abort as the register is not exposed on the OCP
+         * Hence reading the Cortex Rev
+         */
+        cpuid = read_cpuid(CPUID_ID);
+
+        /* If the processor type is Cortex-A8 and the revision is 0x0
+         * it means its Cortex r0p0 which is 3430 ES1
+         */
+        if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
+                switch (reg) {
+                case OMAP_TAP_IDCODE  : regval = 0x0B7AE02F; break;
+                /* Making DevType as 0xF in ES1 to differ from ES2 */
+                case OMAP_TAP_PROD_ID : regval = 0x000F00F0; break;
+                case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
+                case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
+                case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
+                case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
+                }
+        } else
+                regval = __raw_readl(TAP_BASE + reg);
+
+        return regval;
+
+}
+
+/*
+ * _set_system_rev - set the system_rev global based on current OMAP chip type
+ *
+ * Set the system_rev global.  This is primarily used by the cpu_is_omapxxxx()
+ * macros.
+ */
+static void __init _set_system_rev(u32 type, u8 rev)
+{
+        u32 i, ctrl_status;
+
+        /*
+         * system_rev encoding is as follows
+         * system_rev & 0xff000000 -> Omap Class (24xx/34xx)
+         * system_rev & 0xfff00000 -> Omap Sub Class (242x/343x)
+         * system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430)
+         * system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 )
+         * system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD )
+         * system_rev & 0x000000c0 -> IDCODE revision[6:7]
+         * system_rev & 0x0000003f -> sys_boot[0:5]
+         */
+        /* Embedding the ES revision info in type field */
+        system_rev = type;
+        /* Also add IDCODE revision info only two lower bits */
+        system_rev |= ((rev & 0x3) << 6);
+
+        /* Add in the device type and sys_boot fields (see above) */
+        if (cpu_is_omap24xx()) {
+                i = OMAP24XX_CONTROL_STATUS;
+        } else if (cpu_is_omap343x()) {
+                i = OMAP343X_CONTROL_STATUS;
+        } else {
+                printk(KERN_ERR "id: unknown CPU type\n");
+                BUG();
+        }
+        ctrl_status = omap_ctrl_readl(i);
+        system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK |
+                                      OMAP2_SYSBOOT_4_MASK |
+                                      OMAP2_SYSBOOT_3_MASK |
+                                      OMAP2_SYSBOOT_2_MASK |
+                                      OMAP2_SYSBOOT_1_MASK |
+                                      OMAP2_SYSBOOT_0_MASK));
+        system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK);
+}
+
+
+/*
+ * _set_omap_chip - set the omap_chip global based on OMAP chip type
+ *
+ * Build the omap_chip bits.  This variable is used by powerdomain and
+ * clockdomain code to indicate whether structures are applicable for
+ * the current OMAP chip type by ANDing it against a 'platform' bitfield
+ * in the structure.
+ */
+static void __init _set_omap_chip(void)
+{
+        if (cpu_is_omap343x()) {
+
+                omap_chip.oc = CHIP_IS_OMAP3430;
+                if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
+                        omap_chip.oc |= CHIP_IS_OMAP3430ES1;
+                else if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0))
+                        omap_chip.oc |= CHIP_IS_OMAP3430ES2;
+
+        } else if (cpu_is_omap243x()) {
+
+                /* Currently only supports 2430ES2.1 and 2430-all */
+                omap_chip.oc |= CHIP_IS_OMAP2430;
+
+        } else if (cpu_is_omap242x()) {
+
+                /* Currently only supports 2420ES2.1.1 and 2420-all */
+                omap_chip.oc |= CHIP_IS_OMAP2420;
+
+        } else {
+
+                /* Current CPU not supported by this code. */
+                printk(KERN_WARNING "OMAP chip type code does not yet support "
+                       "this CPU type.\n");
+                WARN_ON(1);
+
+        }
+
 }
 
 void __init omap2_check_revision(void)
@@ -76,21 +208,31 @@ void __init omap2_check_revision(void)
         rev = (idcode >> 28) & 0x0f;
         dev_type = (prod_id >> 16) & 0x0f;
 
-#ifdef DEBUG
-        printk(KERN_DEBUG "OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
-                idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
-        printk(KERN_DEBUG "OMAP_TAP_DIE_ID_0: 0x%08x\n",
-                read_tap_reg(OMAP_TAP_DIE_ID_0));
-        printk(KERN_DEBUG "OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
-                read_tap_reg(OMAP_TAP_DIE_ID_1),
-               (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
-        printk(KERN_DEBUG "OMAP_TAP_DIE_ID_2: 0x%08x\n",
-                read_tap_reg(OMAP_TAP_DIE_ID_2));
-        printk(KERN_DEBUG "OMAP_TAP_DIE_ID_3: 0x%08x\n",
-                read_tap_reg(OMAP_TAP_DIE_ID_3));
-        printk(KERN_DEBUG "OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
-                prod_id, dev_type);
-#endif
+        pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
+                 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
+        pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
+                 read_tap_reg(OMAP_TAP_DIE_ID_0));
+        pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
+                 read_tap_reg(OMAP_TAP_DIE_ID_1),
+                 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
+        pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
+                 read_tap_reg(OMAP_TAP_DIE_ID_2));
+        pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
+                 read_tap_reg(OMAP_TAP_DIE_ID_3));
+        pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
+                 prod_id, dev_type);
+
+        /*
+         * Detection for 34xx ES2.0 and above can be done with just
+         * hawkeye and rev. See TRM 1.5.2 Device Identification.
+         * Note that rev cannot be used directly as ES1.0 uses value 0.
+         */
+        if (hawkeye == 0xb7ae) {
+                system_rev = 0x34300000 | ((1 + rev) << 12);
+                pr_info("OMAP%04x ES2.%i\n", system_rev >> 16, rev);
+                _set_omap_chip();
+                return;
+        }
 
         /* Check hawkeye ids */
         for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
@@ -114,16 +256,15 @@ void __init omap2_check_revision(void)
                                 omap_ids[i].type >> 16);
                 j = i;
         }
-        system_rev = omap_ids[j].type;
 
-        system_rev |= rev << 8;
+        _set_system_rev(omap_ids[j].type, rev);
 
-        /* Add the cpu class info (24xx) */
-        system_rev |= 0x24;
+        _set_omap_chip();
 
         pr_info("OMAP%04x", system_rev >> 16);
         if ((system_rev >> 8) & 0x0f)
-                printk("%x", (system_rev >> 8) & 0x0f);
-        printk("\n");
+                pr_info("ES%x", (system_rev >> 12) & 0xf);
+        pr_info("\n");
+
 }
 
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
new file mode 100644
index 000000000000..17cf199d1130
--- /dev/null
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -0,0 +1,208 @@
+/*
+ * linux/arch/arm/mach-omap2/mcbsp.c
+ *
+ * Copyright (C) 2008 Instituto Nokia de Tecnologia
+ * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Multichannel mode not supported.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include <asm/arch/dma.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mcbsp.h>
+
+struct mcbsp_internal_clk {
+        struct clk clk;
+        struct clk **childs;
+        int n_childs;
+};
+
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+static void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
+{
+        const char *clk_names[] = { "mcbsp_ick", "mcbsp_fck" };
+        int i;
+
+        mclk->n_childs = ARRAY_SIZE(clk_names);
+        mclk->childs = kzalloc(mclk->n_childs * sizeof(struct clk *),
+                                GFP_KERNEL);
+
+        for (i = 0; i < mclk->n_childs; i++) {
+                /* We fake a platform device to get correct device id */
+                struct platform_device pdev;
+
+                pdev.dev.bus = &platform_bus_type;
+                pdev.id = mclk->clk.id;
+                mclk->childs[i] = clk_get(&pdev.dev, clk_names[i]);
+                if (IS_ERR(mclk->childs[i]))
+                        printk(KERN_ERR "Could not get clock %s (%d).\n",
+                                clk_names[i], mclk->clk.id);
+        }
+}
+
+static int omap_mcbsp_clk_enable(struct clk *clk)
+{
+        struct mcbsp_internal_clk *mclk = container_of(clk,
+                                        struct mcbsp_internal_clk, clk);
+        int i;
+
+        for (i = 0; i < mclk->n_childs; i++)
+                clk_enable(mclk->childs[i]);
+        return 0;
+}
+
+static void omap_mcbsp_clk_disable(struct clk *clk)
+{
+        struct mcbsp_internal_clk *mclk = container_of(clk,
+                                        struct mcbsp_internal_clk, clk);
+        int i;
+
+        for (i = 0; i < mclk->n_childs; i++)
+                clk_disable(mclk->childs[i]);
+}
+
+static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
+        {
+                .clk = {
+                        .name           = "mcbsp_clk",
+                        .id             = 1,
+                        .enable         = omap_mcbsp_clk_enable,
+                        .disable        = omap_mcbsp_clk_disable,
+                },
+        },
+        {
+                .clk = {
+                        .name           = "mcbsp_clk",
+                        .id             = 2,
+                        .enable         = omap_mcbsp_clk_enable,
+                        .disable        = omap_mcbsp_clk_disable,
+                },
+        },
+};
+
+#define omap_mcbsp_clks_size    ARRAY_SIZE(omap_mcbsp_clks)
+#else
+#define omap_mcbsp_clks_size    0
+static struct mcbsp_internal_clk __initdata *omap_mcbsp_clks;
+static inline void omap_mcbsp_clk_init(struct clk *clk)
+{ }
+#endif
+
+static void omap2_mcbsp2_mux_setup(void)
+{
+        omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
+        omap_cfg_reg(R14_24XX_MCBSP2_FSX);
+        omap_cfg_reg(W15_24XX_MCBSP2_DR);
+        omap_cfg_reg(V15_24XX_MCBSP2_DX);
+        omap_cfg_reg(V14_24XX_GPIO117);
+        /*
+         * TODO: Need to add MUX settings for OMAP 2430 SDP
+         */
+}
+
+static void omap2_mcbsp_request(unsigned int id)
+{
+        if (cpu_is_omap2420() && (id == OMAP_MCBSP2))
+                omap2_mcbsp2_mux_setup();
+}
+
+static int omap2_mcbsp_check(unsigned int id)
+{
+        if (id > OMAP_MAX_MCBSP_COUNT - 1) {
+                printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
+                return -ENODEV;
+        }
+        return 0;
+}
+
+static struct omap_mcbsp_ops omap2_mcbsp_ops = {
+        .request        = omap2_mcbsp_request,
+        .check          = omap2_mcbsp_check,
+};
+
+#ifdef CONFIG_ARCH_OMAP24XX
+static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = {
+        {
+                .virt_base      = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
+                .dma_rx_sync    = OMAP24XX_DMA_MCBSP1_RX,
+                .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
+                .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+                .clk_name       = "mcbsp_clk",
+        },
+        {
+                .virt_base      = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
+                .dma_rx_sync    = OMAP24XX_DMA_MCBSP2_RX,
+                .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
+                .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+                .clk_name       = "mcbsp_clk",
+        },
+};
+#define OMAP24XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap24xx_mcbsp_pdata)
+#else
+#define omap24xx_mcbsp_pdata            NULL
+#define OMAP24XX_MCBSP_PDATA_SZ         0
+#endif
+
+#ifdef CONFIG_ARCH_OMAP34XX
+static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
+        {
+                .virt_base      = IO_ADDRESS(OMAP34XX_MCBSP1_BASE),
+                .dma_rx_sync    = OMAP24XX_DMA_MCBSP1_RX,
+                .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
+                .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+                .clk_name       = "mcbsp_clk",
+        },
+        {
+                .virt_base      = IO_ADDRESS(OMAP34XX_MCBSP2_BASE),
+                .dma_rx_sync    = OMAP24XX_DMA_MCBSP2_RX,
+                .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
+                .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+                .clk_name       = "mcbsp_clk",
+        },
+};
+#define OMAP34XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap34xx_mcbsp_pdata)
+#else
+#define omap34xx_mcbsp_pdata            NULL
+#define OMAP34XX_MCBSP_PDATA_SZ         0
+#endif
+
+int __init omap2_mcbsp_init(void)
+{
+        int i;
+
+        for (i = 0; i < omap_mcbsp_clks_size; i++) {
+                /* Once we call clk_get inside init, we do not register it */
+                omap_mcbsp_clk_init(&omap_mcbsp_clks[i]);
+                clk_register(&omap_mcbsp_clks[i].clk);
+        }
+
+        if (cpu_is_omap24xx())
+                omap_mcbsp_register_board_cfg(omap24xx_mcbsp_pdata,
+                                                OMAP24XX_MCBSP_PDATA_SZ);
+
+        if (cpu_is_omap34xx())
+                omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
+                                                OMAP34XX_MCBSP_PDATA_SZ);
+
+        return omap_mcbsp_init();
+}
+arch_initcall(omap2_mcbsp_init);
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 12479081881a..73cadb2c75cf 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -24,6 +24,7 @@
 
 #include <asm/io.h>
 
+#include <asm/arch/common.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sram.h>
 
@@ -32,8 +33,8 @@
 #include "memory.h"
 #include "sdrc.h"
 
-unsigned long omap2_sdrc_base;
-unsigned long omap2_sms_base;
+void __iomem *omap2_sdrc_base;
+void __iomem *omap2_sms_base;
 
 static struct memory_timings mem_timings;
 static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
@@ -154,6 +155,12 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
         mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
 }
 
+void __init omap2_set_globals_memory(struct omap_globals *omap2_globals)
+{
+        omap2_sdrc_base = omap2_globals->sdrc;
+        omap2_sms_base = omap2_globals->sms;
+}
+
 /* turn on smart idle modes for SDRAM scheduler and controller */
 void __init omap2_init_memory(void)
 {
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 930770012a75..8f98b20f30a1 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -236,7 +236,7 @@ void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
         warn = (orig != reg);
         if (debug || warn)
                 printk(KERN_WARNING
-                        "MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
+                        "MUX: setup %s (0x%p): 0x%04x -> 0x%04x\n",
                         cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
                         orig, reg);
 }
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index aad781dcf1b1..d6c9de82ca0c 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -57,13 +57,6 @@ void omap2_pm_idle(void)
                 return;
         }
 
-        /*
-         * Since an interrupt may set up a timer, we don't want to
-         * reprogram the hardware timer with interrupts enabled.
-         * Re-enable interrupts only after returning from idle.
-         */
-        timer_dyn_reprogram();
-
         omap2_sram_idle();
         local_fiq_enable();
         local_irq_enable();
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index cacb34086e35..54c32f482131 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -32,6 +32,7 @@
 
 
 /* Chip-specific module offsets */
+#define OMAP24XX_GR_MOD                                 OCP_MOD
 #define OMAP24XX_DSP_MOD                                0x800
 
 #define OMAP2430_MDM_MOD                                0xc00
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index b12f423b8595..fd92a80f38f2 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -16,16 +16,21 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
+#include <asm/arch/common.h>
+#include <asm/arch/prcm.h>
 
+#include "clock.h"
 #include "prm.h"
 #include "prm-regbits-24xx.h"
 
-extern void omap2_clk_prepare_for_reboot(void);
+static void __iomem *prm_base;
+static void __iomem *cm_base;
 
 u32 omap_prcm_get_reset_sources(void)
 {
+        /* XXX This presumably needs modification for 34XX */
         return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
 }
 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
@@ -33,11 +38,90 @@ EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 /* Resets clock rates and reboots the system. Only called from system.h */
 void omap_prcm_arch_reset(char mode)
 {
-        u32 wkup;
+        s16 prcm_offs;
         omap2_clk_prepare_for_reboot();
 
-        if (cpu_is_omap24xx()) {
-                wkup = prm_read_mod_reg(WKUP_MOD, RM_RSTCTRL) | OMAP_RST_DPLL3;
-                prm_write_mod_reg(wkup, WKUP_MOD, RM_RSTCTRL);
-        }
+        if (cpu_is_omap24xx())
+                prcm_offs = WKUP_MOD;
+        else if (cpu_is_omap34xx())
+                prcm_offs = OMAP3430_GR_MOD;
+        else
+                WARN_ON(1);
+
+        prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
+}
+
+static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
+{
+        BUG_ON(!base);
+        return __raw_readl(base + module + reg);
+}
+
+static inline void __omap_prcm_write(u32 value, void __iomem *base,
+                                                s16 module, u16 reg)
+{
+        BUG_ON(!base);
+        __raw_writel(value, base + module + reg);
+}
+
+/* Read a register in a PRM module */
+u32 prm_read_mod_reg(s16 module, u16 idx)
+{
+        return __omap_prcm_read(prm_base, module, idx);
+}
+EXPORT_SYMBOL(prm_read_mod_reg);
+
+/* Write into a register in a PRM module */
+void prm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+        __omap_prcm_write(val, prm_base, module, idx);
+}
+EXPORT_SYMBOL(prm_write_mod_reg);
+
+/* Read-modify-write a register in a PRM module. Caller must lock */
+u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
+{
+        u32 v;
+
+        v = prm_read_mod_reg(module, idx);
+        v &= ~mask;
+        v |= bits;
+        prm_write_mod_reg(v, module, idx);
+
+        return v;
+}
+EXPORT_SYMBOL(prm_rmw_mod_reg_bits);
+
+/* Read a register in a CM module */
+u32 cm_read_mod_reg(s16 module, u16 idx)
+{
+        return __omap_prcm_read(cm_base, module, idx);
+}
+EXPORT_SYMBOL(cm_read_mod_reg);
+
+/* Write into a register in a CM module */
+void cm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+        __omap_prcm_write(val, cm_base, module, idx);
+}
+EXPORT_SYMBOL(cm_write_mod_reg);
+
+/* Read-modify-write a register in a CM module. Caller must lock */
+u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
+{
+        u32 v;
+
+        v = cm_read_mod_reg(module, idx);
+        v &= ~mask;
+        v |= bits;
+        cm_write_mod_reg(v, module, idx);
+
+        return v;
+}
+EXPORT_SYMBOL(cm_rmw_mod_reg_bits);
+
+void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
+{
+        prm_base = omap2_globals->prm;
+        cm_base = omap2_globals->cm;
 }
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 618f8111658a..bbf41fc8e9a9 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -38,13 +38,29 @@
  *
  */
 
+/* Global 24xx registers in GR_MOD (Same as OCP_MOD for 24xx) */
+#define OMAP24XX_PRCM_VOLTCTRL_OFFSET           0x0050
+#define OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET        0x0080
+
+/* 242x GR_MOD registers, use these only for assembly code */
+#define OMAP242X_PRCM_VOLTCTRL          OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD,   \
+                                                OMAP24XX_PRCM_VOLTCTRL_OFFSET)
+#define OMAP242X_PRCM_CLKCFG_CTRL       OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD,   \
+                                                OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET)
+
+/* 243x GR_MOD registers, use these only for assembly code */
+#define OMAP243X_PRCM_VOLTCTRL          OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD,   \
+                                                OMAP24XX_PRCM_VOLTCTRL_OFFSET)
+#define OMAP243X_PRCM_CLKCFG_CTRL       OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD,   \
+                                                OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET)
+
+/* These will disappear */
 #define OMAP24XX_PRCM_REVISION          OMAP_PRM_REGADDR(OCP_MOD, 0x0000)
 #define OMAP24XX_PRCM_SYSCONFIG         OMAP_PRM_REGADDR(OCP_MOD, 0x0010)
 
 #define OMAP24XX_PRCM_IRQSTATUS_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
 #define OMAP24XX_PRCM_IRQENABLE_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
 
-#define OMAP24XX_PRCM_VOLTCTRL          OMAP_PRM_REGADDR(OCP_MOD, 0x0050)
 #define OMAP24XX_PRCM_VOLTST            OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
 #define OMAP24XX_PRCM_CLKSRC_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
 #define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
@@ -150,15 +166,19 @@
 #ifndef __ASSEMBLER__
 
 /* Power/reset management domain register get/set */
+extern u32 prm_read_mod_reg(s16 module, u16 idx);
+extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
+extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
 
-static inline void prm_write_mod_reg(u32 val, s16 module, s16 idx)
+/* Read-modify-write bits in a PRM register (by domain) */
+static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
 {
-        __raw_writel(val, OMAP_PRM_REGADDR(module, idx));
+        return prm_rmw_mod_reg_bits(bits, bits, module, idx);
 }
 
-static inline u32 prm_read_mod_reg(s16 module, s16 idx)
+static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 {
-        return __raw_readl(OMAP_PRM_REGADDR(module, idx));
+        return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
 }
 
 #endif
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index d7f23bc9550a..1b1fe4f6e030 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -18,13 +18,11 @@
 #include <asm/arch/sdrc.h>
 
 #ifndef __ASSEMBLER__
-extern unsigned long omap2_sdrc_base;
-extern unsigned long omap2_sms_base;
+extern void __iomem *omap2_sdrc_base;
+extern void __iomem *omap2_sms_base;
 
-#define OMAP_SDRC_REGADDR(reg)                                          \
-                (void __iomem *)IO_ADDRESS(omap2_sdrc_base + (reg))
-#define OMAP_SMS_REGADDR(reg)                                           \
-                (void __iomem *)IO_ADDRESS(omap2_sms_base + (reg))
+#define OMAP_SDRC_REGADDR(reg)                  (omap2_sdrc_base + (reg))
+#define OMAP_SMS_REGADDR(reg)                   (omap2_sms_base + (reg))
 
 /* SDRC global register get/set */
 
diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram242x.S
index 4a9e49140716..4c274510f3e9 100644
--- a/arch/arm/mach-omap2/sram-fn.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-omap2/sram-fn.S
+ * linux/arch/arm/mach-omap2/sram242x.S
  *
  * Omap2 specific functions that need to be run in internal SRAM
  *
@@ -27,22 +27,20 @@
 #include <asm/arch/io.h>
 #include <asm/hardware.h>
 
-#include "sdrc.h"
 #include "prm.h"
 #include "cm.h"
-
-#define TIMER_32KSYNCT_CR_V     IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
+#include "sdrc.h"
 
         .text
 
-ENTRY(sram_ddr_init)
+ENTRY(omap242x_sram_ddr_init)
         stmfd   sp!, {r0 - r12, lr}     @ save registers on stack
 
         mov     r12, r2                 @ capture CS1 vs CS0
         mov     r8, r3                  @ capture force parameter
 
         /* frequency shift down */
-        ldr     r2, cm_clksel2_pll      @ get address of dpllout reg
+        ldr     r2, omap242x_sdi_cm_clksel2_pll @ get address of dpllout reg
         mov     r3, #0x1                @ value for 1x operation
         str     r3, [r2]                @ go to L1-freq operation
 
@@ -51,7 +49,7 @@ ENTRY(sram_ddr_init)
         bl voltage_shift                @ go drop voltage
 
         /* dll lock mode */
-        ldr     r11, sdrc_dlla_ctrl     @ addr of dlla ctrl
+        ldr     r11, omap242x_sdi_sdrc_dlla_ctrl        @ addr of dlla ctrl
         ldr     r10, [r11]              @ get current val
         cmp     r12, #0x1               @ cs1 base (2422 es2.05/1)
         addeq   r11, r11, #0x8          @ if cs1 base, move to DLLB
@@ -102,7 +100,7 @@ i_dll_delay:
          * wait for it to finish, use 32k sync counter, 1tick=31uS.
          */
 voltage_shift:
-        ldr     r4, prcm_voltctrl       @ get addr of volt ctrl.
+        ldr     r4, omap242x_sdi_prcm_voltctrl  @ get addr of volt ctrl.
         ldr     r5, [r4]                @ get value.
         ldr     r6, prcm_mask_val       @ get value of mask
         and     r5, r5, r6              @ apply mask to clear bits
@@ -112,7 +110,7 @@ voltage_shift:
         orr     r5, r5, r3              @ build value for force
         str     r5, [r4]                @ Force transition to L1
 
-        ldr     r3, timer_32ksynct_cr   @ get addr of counter
+        ldr     r3, omap242x_sdi_timer_32ksynct_cr      @ get addr of counter
         ldr     r5, [r3]                @ get value
         add     r5, r5, #0x3            @ give it at most 93uS
 volt_delay:
@@ -121,32 +119,31 @@ volt_delay:
         bhi     volt_delay              @ not yet->branch
         mov     pc, lr                  @ back to caller.
 
-/* relative load constants */
-cm_clksel2_pll:
+omap242x_sdi_cm_clksel2_pll:
         .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
-sdrc_dlla_ctrl:
+omap242x_sdi_sdrc_dlla_ctrl:
         .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-prcm_voltctrl:
-        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
+omap242x_sdi_prcm_voltctrl:
+        .word OMAP242X_PRCM_VOLTCTRL
 prcm_mask_val:
         .word 0xFFFF3FFC
-timer_32ksynct_cr:
-        .word TIMER_32KSYNCT_CR_V
-ENTRY(sram_ddr_init_sz)
-        .word   . - sram_ddr_init
+omap242x_sdi_timer_32ksynct_cr:
+        .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
+ENTRY(omap242x_sram_ddr_init_sz)
+        .word   . - omap242x_sram_ddr_init
 
 /*
  * Reprograms memory timings.
  * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
  * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
  */
-ENTRY(sram_reprogram_sdrc)
+ENTRY(omap242x_sram_reprogram_sdrc)
         stmfd   sp!, {r0 - r10, lr}     @ save registers on stack
         mov     r3, #0x0                @ clear for mrc call
         mcr     p15, 0, r3, c7, c10, 4  @ memory barrier, finish ARM SDR/DDR
         nop
         nop
-        ldr     r6, ddr_sdrc_rfr_ctrl   @ get addr of refresh reg
+        ldr     r6, omap242x_srs_sdrc_rfr_ctrl  @ get addr of refresh reg
         ldr     r5, [r6]                @ get value
         mov     r5, r5, lsr #8          @ isolate rfr field and drop burst
 
@@ -160,7 +157,7 @@ ENTRY(sram_reprogram_sdrc)
         movne   r5, r5, lsl #1          @ mult by 2 if to full
         mov     r5, r5, lsl #8          @ put rfr field back into place
         add     r5, r5, #0x1            @ turn on burst of 1
-        ldr     r4, ddr_cm_clksel2_pll  @ get address of out reg
+        ldr     r4, omap242x_srs_cm_clksel2_pll @ get address of out reg
         ldr     r3, [r4]                @ get curr value
         orr     r3, r3, #0x3
         bic     r3, r3, #0x3            @ clear lower bits
@@ -181,7 +178,7 @@ ENTRY(sram_reprogram_sdrc)
         bne     freq_out                @ leave if SDR, no DLL function
 
         /* With DDR, we need to take care of the DLL for the frequency change */
-        ldr     r2, ddr_sdrc_dlla_ctrl  @ addr of dlla ctrl
+        ldr     r2, omap242x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
         str     r1, [r2]                @ write out new SDRC_DLLA_CTRL
         add     r2, r2, #0x8            @ addr to SDRC_DLLB_CTRL
         str     r1, [r2]                @ commit to SDRC_DLLB_CTRL
@@ -197,7 +194,7 @@ freq_out:
      *  wait for it to finish, use 32k sync counter, 1tick=31uS.
      */
 voltage_shift_c:
-        ldr     r10, ddr_prcm_voltctrl  @ get addr of volt ctrl
+        ldr     r10, omap242x_srs_prcm_voltctrl @ get addr of volt ctrl
         ldr     r8, [r10]               @ get value
         ldr     r7, ddr_prcm_mask_val   @ get value of mask
         and     r8, r8, r7              @ apply mask to clear bits
@@ -207,7 +204,7 @@ voltage_shift_c:
         orr     r8, r8, r7              @ build value for force
         str     r8, [r10]               @ Force transition to L1
 
-        ldr     r10, ddr_timer_32ksynct @ get addr of counter
+        ldr     r10, omap242x_srs_timer_32ksynct        @ get addr of counter
         ldr     r8, [r10]               @ get value
         add     r8, r8, #0x2            @ give it at most 62uS (min 31+)
 volt_delay_c:
@@ -216,39 +213,39 @@ volt_delay_c:
         bhi     volt_delay_c            @ not yet->branch
         mov     pc, lr                  @ back to caller
 
-ddr_cm_clksel2_pll:
+omap242x_srs_cm_clksel2_pll:
         .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
-ddr_sdrc_dlla_ctrl:
+omap242x_srs_sdrc_dlla_ctrl:
         .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
-ddr_sdrc_rfr_ctrl:
+omap242x_srs_sdrc_rfr_ctrl:
         .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-ddr_prcm_voltctrl:
-        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
+omap242x_srs_prcm_voltctrl:
+        .word OMAP242X_PRCM_VOLTCTRL
 ddr_prcm_mask_val:
         .word 0xFFFF3FFC
-ddr_timer_32ksynct:
-        .word TIMER_32KSYNCT_CR_V
+omap242x_srs_timer_32ksynct:
+        .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
 
-ENTRY(sram_reprogram_sdrc_sz)
-        .word   . - sram_reprogram_sdrc
+ENTRY(omap242x_sram_reprogram_sdrc_sz)
+        .word   . - omap242x_sram_reprogram_sdrc
 
 /*
  * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
  */
-ENTRY(sram_set_prcm)
+ENTRY(omap242x_sram_set_prcm)
         stmfd   sp!, {r0-r12, lr}       @ regs to stack
         adr     r4, pbegin              @ addr of preload start
         adr     r8, pend                @ addr of preload end
         mcrr    p15, 1, r8, r4, c12     @ preload into icache
 pbegin:
         /* move into fast relock bypass */
-        ldr     r8, pll_ctl             @ get addr
+        ldr     r8, omap242x_ssp_pll_ctl        @ get addr
         ldr     r5, [r8]                @ get val
         mvn     r6, #0x3                @ clear mask
         and     r5, r5, r6              @ clear field
         orr     r7, r5, #0x2            @ fast relock val
         str     r7, [r8]                @ go to fast relock
-        ldr     r4, pll_stat            @ addr of stat
+        ldr     r4, omap242x_ssp_pll_stat       @ addr of stat
 block:
         /* wait for bypass */
         ldr     r8, [r4]                @ stat value
@@ -257,10 +254,10 @@ block:
         bne     block                   @ loop if not
 
         /* set new dpll dividers _after_ in bypass */
-        ldr     r4, pll_div             @ get addr
+        ldr     r4, omap242x_ssp_pll_div        @ get addr
         str     r0, [r4]                @ set dpll ctrl val
 
-        ldr     r4, set_config          @ get addr
+        ldr     r4, omap242x_ssp_set_config     @ get addr
         mov     r8, #1                  @ valid cfg msk
         str     r8, [r4]                @ make dividers take
 
@@ -274,8 +271,8 @@ wait_a_bit:
         beq     pend                    @ jump over dpll relock
 
         /* relock DPLL with new vals */
-        ldr     r5, pll_stat            @ get addr
-        ldr     r4, pll_ctl             @ get addr
+        ldr     r5, omap242x_ssp_pll_stat       @ get addr
+        ldr     r4, omap242x_ssp_pll_ctl        @ get addr
         orr     r8, r7, #0x3            @ val for lock dpll
         str     r8, [r4]                @ set val
         mov     r0, #1000               @ dead spin a bit
@@ -289,9 +286,9 @@ wait_lock:
         bne     wait_lock               @ wait if not
 pend:
         /* update memory timings & briefly lock dll */
-        ldr     r4, sdrc_rfr            @ get addr
+        ldr     r4, omap242x_ssp_sdrc_rfr       @ get addr
         str     r1, [r4]                @ update refresh timing
-        ldr     r11, dlla_ctrl          @ get addr of DLLA ctrl
+        ldr     r11, omap242x_ssp_dlla_ctrl     @ get addr of DLLA ctrl
         ldr     r10, [r11]              @ get current val
         mvn     r9, #0x4                @ mask to get clear bit2
         and     r10, r10, r9            @ clear bit2 for lock mode
@@ -307,18 +304,18 @@ wait_dll_lock:
         nop
         ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
 
-set_config:
-        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x80)
-pll_ctl:
-        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_FCLKEN1)
-pll_stat:
-        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST1)
-pll_div:
-        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL)
-sdrc_rfr:
+omap242x_ssp_set_config:
+        .word OMAP242X_PRCM_CLKCFG_CTRL
+omap242x_ssp_pll_ctl:
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
+omap242x_ssp_pll_stat:
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST)
+omap242x_ssp_pll_div:
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
+omap242x_ssp_sdrc_rfr:
         .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-dlla_ctrl:
+omap242x_ssp_dlla_ctrl:
         .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 
-ENTRY(sram_set_prcm_sz)
-        .word   . - sram_set_prcm
+ENTRY(omap242x_sram_set_prcm_sz)
+        .word   . - omap242x_sram_set_prcm
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
new file mode 100644
index 000000000000..a3fa48dc08cd
--- /dev/null
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -0,0 +1,321 @@
+/*
+ * linux/arch/arm/mach-omap2/sram243x.S
+ *
+ * Omap2 specific functions that need to be run in internal SRAM
+ *
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/arch/io.h>
+#include <asm/hardware.h>
+
+#include "prm.h"
+#include "cm.h"
+#include "sdrc.h"
+
+        .text
+
+ENTRY(omap243x_sram_ddr_init)
+        stmfd   sp!, {r0 - r12, lr}     @ save registers on stack
+
+        mov     r12, r2                 @ capture CS1 vs CS0
+        mov     r8, r3                  @ capture force parameter
+
+        /* frequency shift down */
+        ldr     r2, omap243x_sdi_cm_clksel2_pll @ get address of dpllout reg
+        mov     r3, #0x1                @ value for 1x operation
+        str     r3, [r2]                @ go to L1-freq operation
+
+        /* voltage shift down */
+        mov r9, #0x1                    @ set up for L1 voltage call
+        bl voltage_shift                @ go drop voltage
+
+        /* dll lock mode */
+        ldr     r11, omap243x_sdi_sdrc_dlla_ctrl        @ addr of dlla ctrl
+        ldr     r10, [r11]              @ get current val
+        cmp     r12, #0x1               @ cs1 base (2422 es2.05/1)
+        addeq   r11, r11, #0x8          @ if cs1 base, move to DLLB
+        mvn     r9, #0x4                @ mask to get clear bit2
+        and     r10, r10, r9            @ clear bit2 for lock mode.
+        orr     r10, r10, #0x8          @ make sure DLL on (es2 bit pos)
+        orr     r10, r10, #0x2          @ 90 degree phase for all below 133Mhz
+        str     r10, [r11]              @ commit to DLLA_CTRL
+        bl      i_dll_wait              @ wait for dll to lock
+
+        /* get dll value */
+        add     r11, r11, #0x4          @ get addr of status reg
+        ldr     r10, [r11]              @ get locked value
+
+        /* voltage shift up */
+        mov r9, #0x0                    @ shift back to L0-voltage
+        bl voltage_shift                @ go raise voltage
+
+        /* frequency shift up */
+        mov     r3, #0x2                @ value for 2x operation
+        str     r3, [r2]                @ go to L0-freq operation
+
+        /* reset entry mode for dllctrl */
+        sub     r11, r11, #0x4          @ move from status to ctrl
+        cmp     r12, #0x1               @ normalize if cs1 based
+        subeq   r11, r11, #0x8          @ possibly back to DLLA
+        cmp     r8, #0x1                @ if forced unlock exit
+        orreq   r1, r1, #0x4            @ make sure exit with unlocked value
+        str     r1, [r11]               @ restore DLLA_CTRL high value
+        add     r11, r11, #0x8          @ move to DLLB_CTRL addr
+        str     r1, [r11]               @ set value DLLB_CTRL
+        bl      i_dll_wait              @ wait for possible lock
+
+        /* set up for return, DDR should be good */
+        str r10, [r0]                   @ write dll_status and return counter
+        ldmfd   sp!, {r0 - r12, pc}     @ restore regs and return
+
+        /* ensure the DLL has relocked */
+i_dll_wait:
+        mov     r4, #0x800              @ delay DLL relock, min 0x400 L3 clocks
+i_dll_delay:
+        subs    r4, r4, #0x1
+        bne     i_dll_delay
+        mov     pc, lr
+
+        /*
+         * shift up or down voltage, use R9 as input to tell level.
+         * wait for it to finish, use 32k sync counter, 1tick=31uS.
+         */
+voltage_shift:
+        ldr     r4, omap243x_sdi_prcm_voltctrl  @ get addr of volt ctrl.
+        ldr     r5, [r4]                @ get value.
+        ldr     r6, prcm_mask_val       @ get value of mask
+        and     r5, r5, r6              @ apply mask to clear bits
+        orr     r5, r5, r9              @ bulld value for L0/L1-volt operation.
+        str     r5, [r4]                @ set up for change.
+        mov     r3, #0x4000             @ get val for force
+        orr     r5, r5, r3              @ build value for force
+        str     r5, [r4]                @ Force transition to L1
+
+        ldr     r3, omap243x_sdi_timer_32ksynct_cr      @ get addr of counter
+        ldr     r5, [r3]                @ get value
+        add     r5, r5, #0x3            @ give it at most 93uS
+volt_delay:
+        ldr     r7, [r3]                @ get timer value
+        cmp     r5, r7                  @ time up?
+        bhi     volt_delay              @ not yet->branch
+        mov     pc, lr                  @ back to caller.
+
+omap243x_sdi_cm_clksel2_pll:
+        .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
+omap243x_sdi_sdrc_dlla_ctrl:
+        .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
+omap243x_sdi_prcm_voltctrl:
+        .word OMAP243X_PRCM_VOLTCTRL
+prcm_mask_val:
+        .word 0xFFFF3FFC
+omap243x_sdi_timer_32ksynct_cr:
+        .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
+ENTRY(omap243x_sram_ddr_init_sz)
+        .word   . - omap243x_sram_ddr_init
+
+/*
+ * Reprograms memory timings.
+ * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
+ * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
+ */
+ENTRY(omap243x_sram_reprogram_sdrc)
+        stmfd   sp!, {r0 - r10, lr}     @ save registers on stack
+        mov     r3, #0x0                @ clear for mrc call
+        mcr     p15, 0, r3, c7, c10, 4  @ memory barrier, finish ARM SDR/DDR
+        nop
+        nop
+        ldr     r6, omap243x_srs_sdrc_rfr_ctrl  @ get addr of refresh reg
+        ldr     r5, [r6]                @ get value
+        mov     r5, r5, lsr #8          @ isolate rfr field and drop burst
+
+        cmp     r0, #0x1                @ going to half speed?
+        movne   r9, #0x0                @ if up set flag up for pre up, hi volt
+
+        blne    voltage_shift_c         @ adjust voltage
+
+        cmp     r0, #0x1                @ going to half speed (post branch link)
+        moveq   r5, r5, lsr #1          @ divide by 2 if to half
+        movne   r5, r5, lsl #1          @ mult by 2 if to full
+        mov     r5, r5, lsl #8          @ put rfr field back into place
+        add     r5, r5, #0x1            @ turn on burst of 1
+        ldr     r4, omap243x_srs_cm_clksel2_pll @ get address of out reg
+        ldr     r3, [r4]                @ get curr value
+        orr     r3, r3, #0x3
+        bic     r3, r3, #0x3            @ clear lower bits
+        orr     r3, r3, r0              @ new state value
+        str     r3, [r4]                @ set new state (pll/x, x=1 or 2)
+        nop
+        nop
+
+        moveq   r9, #0x1                @ if speed down, post down, drop volt
+        bleq    voltage_shift_c
+
+        mcr     p15, 0, r3, c7, c10, 4  @ memory barrier
+        str     r5, [r6]                @ set new RFR_1 value
+        add     r6, r6, #0x30           @ get RFR_2 addr
+        str     r5, [r6]                @ set RFR_2
+        nop
+        cmp     r2, #0x1                @ (SDR or DDR) do we need to adjust DLL
+        bne     freq_out                @ leave if SDR, no DLL function
+
+        /* With DDR, we need to take care of the DLL for the frequency change */
+        ldr     r2, omap243x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
+        str     r1, [r2]                @ write out new SDRC_DLLA_CTRL
+        add     r2, r2, #0x8            @ addr to SDRC_DLLB_CTRL
+        str     r1, [r2]                @ commit to SDRC_DLLB_CTRL
+        mov     r1, #0x2000             @ wait DLL relock, min 0x400 L3 clocks
+dll_wait:
+        subs    r1, r1, #0x1
+        bne     dll_wait
+freq_out:
+        ldmfd   sp!, {r0 - r10, pc}     @ restore regs and return
+
+    /*
+     * shift up or down voltage, use R9 as input to tell level.
+     *  wait for it to finish, use 32k sync counter, 1tick=31uS.
+     */
+voltage_shift_c:
+        ldr     r10, omap243x_srs_prcm_voltctrl @ get addr of volt ctrl
+        ldr     r8, [r10]               @ get value
+        ldr     r7, ddr_prcm_mask_val   @ get value of mask
+        and     r8, r8, r7              @ apply mask to clear bits
+        orr     r8, r8, r9              @ bulld value for L0/L1-volt operation.
+        str     r8, [r10]               @ set up for change.
+        mov     r7, #0x4000             @ get val for force
+        orr     r8, r8, r7              @ build value for force
+        str     r8, [r10]               @ Force transition to L1
+
+        ldr     r10, omap243x_srs_timer_32ksynct        @ get addr of counter
+        ldr     r8, [r10]               @ get value
+        add     r8, r8, #0x2            @ give it at most 62uS (min 31+)
+volt_delay_c:
+        ldr     r7, [r10]               @ get timer value
+        cmp     r8, r7                  @ time up?
+        bhi     volt_delay_c            @ not yet->branch
+        mov     pc, lr                  @ back to caller
+
+omap243x_srs_cm_clksel2_pll:
+        .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
+omap243x_srs_sdrc_dlla_ctrl:
+        .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
+omap243x_srs_sdrc_rfr_ctrl:
+        .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
+omap243x_srs_prcm_voltctrl:
+        .word OMAP243X_PRCM_VOLTCTRL
+ddr_prcm_mask_val:
+        .word 0xFFFF3FFC
+omap243x_srs_timer_32ksynct:
+        .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
+
+ENTRY(omap243x_sram_reprogram_sdrc_sz)
+        .word   . - omap243x_sram_reprogram_sdrc
+
+/*
+ * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
+ */
+ENTRY(omap243x_sram_set_prcm)
+        stmfd   sp!, {r0-r12, lr}       @ regs to stack
+        adr     r4, pbegin              @ addr of preload start
+        adr     r8, pend                @ addr of preload end
+        mcrr    p15, 1, r8, r4, c12     @ preload into icache
+pbegin:
+        /* move into fast relock bypass */
+        ldr     r8, omap243x_ssp_pll_ctl        @ get addr
+        ldr     r5, [r8]                @ get val
+        mvn     r6, #0x3                @ clear mask
+        and     r5, r5, r6              @ clear field
+        orr     r7, r5, #0x2            @ fast relock val
+        str     r7, [r8]                @ go to fast relock
+        ldr     r4, omap243x_ssp_pll_stat       @ addr of stat
+block:
+        /* wait for bypass */
+        ldr     r8, [r4]                @ stat value
+        and     r8, r8, #0x3            @ mask for stat
+        cmp     r8, #0x1                @ there yet
+        bne     block                   @ loop if not
+
+        /* set new dpll dividers _after_ in bypass */
+        ldr     r4, omap243x_ssp_pll_div        @ get addr
+        str     r0, [r4]                @ set dpll ctrl val
+
+        ldr     r4, omap243x_ssp_set_config     @ get addr
+        mov     r8, #1                  @ valid cfg msk
+        str     r8, [r4]                @ make dividers take
+
+        mov     r4, #100                @ dead spin a bit
+wait_a_bit:
+        subs    r4, r4, #1              @ dec loop
+        bne     wait_a_bit              @ delay done?
+
+        /* check if staying in bypass */
+        cmp     r2, #0x1                @ stay in bypass?
+        beq     pend                    @ jump over dpll relock
+
+        /* relock DPLL with new vals */
+        ldr     r5, omap243x_ssp_pll_stat       @ get addr
+        ldr     r4, omap243x_ssp_pll_ctl        @ get addr
+        orr     r8, r7, #0x3            @ val for lock dpll
+        str     r8, [r4]                @ set val
+        mov     r0, #1000               @ dead spin a bit
+wait_more:
+        subs    r0, r0, #1              @ dec loop
+        bne     wait_more               @ delay done?
+wait_lock:
+        ldr     r8, [r5]                @ get lock val
+        and     r8, r8, #3              @ isolate field
+        cmp     r8, #2                  @ locked?
+        bne     wait_lock               @ wait if not
+pend:
+        /* update memory timings & briefly lock dll */
+        ldr     r4, omap243x_ssp_sdrc_rfr       @ get addr
+        str     r1, [r4]                @ update refresh timing
+        ldr     r11, omap243x_ssp_dlla_ctrl     @ get addr of DLLA ctrl
+        ldr     r10, [r11]              @ get current val
+        mvn     r9, #0x4                @ mask to get clear bit2
+        and     r10, r10, r9            @ clear bit2 for lock mode
+        orr     r10, r10, #0x8          @ make sure DLL on (es2 bit pos)
+        str     r10, [r11]              @ commit to DLLA_CTRL
+        add     r11, r11, #0x8          @ move to dllb
+        str     r10, [r11]              @ hit DLLB also
+
+        mov     r4, #0x800              @ relock time (min 0x400 L3 clocks)
+wait_dll_lock:
+        subs    r4, r4, #0x1
+        bne     wait_dll_lock
+        nop
+        ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
+
+omap243x_ssp_set_config:
+        .word OMAP243X_PRCM_CLKCFG_CTRL
+omap243x_ssp_pll_ctl:
+        .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
+omap243x_ssp_pll_stat:
+        .word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST)
+omap243x_ssp_pll_div:
+        .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
+omap243x_ssp_sdrc_rfr:
+        .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
+omap243x_ssp_dlla_ctrl:
+        .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
+
+ENTRY(omap243x_sram_set_prcm_sz)
+        .word   . - omap243x_sram_set_prcm
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 78d05f203fff..557603f99313 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -59,8 +59,7 @@ static struct irqaction omap2_gp_timer_irq = {
 static int omap2_gp_timer_set_next_event(unsigned long cycles,
                                          struct clock_event_device *evt)
 {
-        omap_dm_timer_set_load(gptimer, 0, 0xffffffff - cycles);
-        omap_dm_timer_start(gptimer);
+        omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
 
         return 0;
 }
@@ -77,8 +76,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
                 period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
                 period -= 1;
 
-                omap_dm_timer_set_load(gptimer, 1, 0xffffffff - period);
-                omap_dm_timer_start(gptimer);
+                omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
                 break;
         case CLOCK_EVT_MODE_ONESHOT:
                 break;
@@ -172,8 +170,7 @@ static void __init omap2_gp_clocksource_init(void)
         tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
         tick_period = (tick_rate / HZ) - 1;
 
-        omap_dm_timer_set_load(gpt, 1, 0);
-        omap_dm_timer_start(gpt);
+        omap_dm_timer_set_load_start(gpt, 1, 0);
 
         clocksource_gpt.mult =
                 clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 93debf336155..ddcd41b15d17 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -44,6 +44,54 @@ config MACH_LINKSTATION_PRO
           Buffalo Linkstation Pro/Live platform. Both v1 and
           v2 devices are supported.
 
+config MACH_TS409
+        bool "QNAP TS-409"
+        help
+          Say 'Y' here if you want your kernel to support the
+          QNAP TS-409 platform.
+
+config MACH_WRT350N_V2
+        bool "Linksys WRT350N v2"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Linksys WRT350N v2 platform.
+
+config MACH_TS78XX
+        bool "Technologic Systems TS-78xx"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Technologic Systems TS-78xx platform.
+
+config MACH_MV2120
+        bool "HP Media Vault mv2120"
+        help
+          Say 'Y' here if you want your kernel to support the
+          HP Media Vault mv2120 or mv5100.
+
+config MACH_MSS2
+        bool "Maxtor Shared Storage II"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Maxtor Shared Storage II platform.
+
+config MACH_WNR854T
+        bool "Netgear WNR854T"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Netgear WNR854T platform.
+
+config MACH_RD88F5181L_GE
+        bool "Marvell Orion-VoIP GE Reference Design"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell Orion-VoIP GE (88F5181L) RD.
+
+config MACH_RD88F5181L_FXO
+        bool "Marvell Orion-VoIP FXO Reference Design"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell Orion-VoIP FXO (88F5181L) RD.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 9301bf55910b..fcc48a8864f3 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -1,7 +1,15 @@
-obj-y                           += common.o addr-map.o pci.o gpio.o irq.o
+obj-y                           += common.o addr-map.o pci.o gpio.o irq.o mpp.o
 obj-$(CONFIG_MACH_DB88F5281)    += db88f5281-setup.o
 obj-$(CONFIG_MACH_RD88F5182)    += rd88f5182-setup.o
 obj-$(CONFIG_MACH_KUROBOX_PRO)  += kurobox_pro-setup.o
 obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o
 obj-$(CONFIG_MACH_DNS323)       += dns323-setup.o
-obj-$(CONFIG_MACH_TS209)        += ts209-setup.o
+obj-$(CONFIG_MACH_TS209)        += ts209-setup.o tsx09-common.o
+obj-$(CONFIG_MACH_TS409)        += ts409-setup.o tsx09-common.o
+obj-$(CONFIG_MACH_WRT350N_V2)   += wrt350n-v2-setup.o
+obj-$(CONFIG_MACH_TS78XX)       += ts78xx-setup.o
+obj-$(CONFIG_MACH_MV2120)       += mv2120-setup.o
+obj-$(CONFIG_MACH_MSS2)         += mss2-setup.o
+obj-$(CONFIG_MACH_WNR854T)      += wnr854t-setup.o
+obj-$(CONFIG_MACH_RD88F5181L_GE)        += rd88f5181l-ge-setup.o
+obj-$(CONFIG_MACH_RD88F5181L_FXO)       += rd88f5181l-fxo-setup.o
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index e63fb05dc893..6f0dbda6c44c 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -70,6 +70,7 @@
 
 
 struct mbus_dram_target_info orion5x_mbus_dram_info;
+static int __initdata win_alloc_count;
 
 static int __init orion5x_cpu_win_can_remap(int win)
 {
@@ -87,16 +88,22 @@ static int __init orion5x_cpu_win_can_remap(int win)
 static void __init setup_cpu_win(int win, u32 base, u32 size,
                                  u8 target, u8 attr, int remap)
 {
-        orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000);
-        orion5x_write(CPU_WIN_CTRL(win),
-                ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1);
+        if (win >= 8) {
+                printk(KERN_ERR "setup_cpu_win: trying to allocate "
+                                "window %d\n", win);
+                return;
+        }
+
+        writel(base & 0xffff0000, CPU_WIN_BASE(win));
+        writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1,
+                CPU_WIN_CTRL(win));
 
         if (orion5x_cpu_win_can_remap(win)) {
                 if (remap < 0)
                         remap = base;
 
-                orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
-                orion5x_write(CPU_WIN_REMAP_HI(win), 0);
+                writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
+                writel(0, CPU_WIN_REMAP_HI(win));
         }
 }
 
@@ -109,11 +116,11 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
          * First, disable and clear windows.
          */
         for (i = 0; i < 8; i++) {
-                orion5x_write(CPU_WIN_BASE(i), 0);
-                orion5x_write(CPU_WIN_CTRL(i), 0);
+                writel(0, CPU_WIN_BASE(i));
+                writel(0, CPU_WIN_CTRL(i));
                 if (orion5x_cpu_win_can_remap(i)) {
-                        orion5x_write(CPU_WIN_REMAP_LO(i), 0);
-                        orion5x_write(CPU_WIN_REMAP_HI(i), 0);
+                        writel(0, CPU_WIN_REMAP_LO(i));
+                        writel(0, CPU_WIN_REMAP_HI(i));
                 }
         }
 
@@ -128,6 +135,7 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
                 TARGET_PCIE, ATTR_PCIE_MEM, -1);
         setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
                 TARGET_PCI, ATTR_PCI_MEM, -1);
+        win_alloc_count = 4;
 
         /*
          * Setup MBUS dram target info.
@@ -147,8 +155,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
                         w = &orion5x_mbus_dram_info.cs[cs++];
                         w->cs_index = i;
                         w->mbus_attr = 0xf & ~(1 << i);
-                        w->base = base & 0xff000000;
-                        w->size = (size | 0x00ffffff) + 1;
+                        w->base = base & 0xffff0000;
+                        w->size = (size | 0x0000ffff) + 1;
                 }
         }
         orion5x_mbus_dram_info.num_cs = cs;
@@ -156,25 +164,30 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
 
 void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
 {
-        setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
+        setup_cpu_win(win_alloc_count++, base, size,
+                      TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
 }
 
 void __init orion5x_setup_dev0_win(u32 base, u32 size)
 {
-        setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
+        setup_cpu_win(win_alloc_count++, base, size,
+                      TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
 }
 
 void __init orion5x_setup_dev1_win(u32 base, u32 size)
 {
-        setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
+        setup_cpu_win(win_alloc_count++, base, size,
+                      TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
 }
 
 void __init orion5x_setup_dev2_win(u32 base, u32 size)
 {
-        setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
+        setup_cpu_win(win_alloc_count++, base, size,
+                      TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
 }
 
 void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
 {
-        setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
+        setup_cpu_win(win_alloc_count++, base, size,
+                      TARGET_PCIE, ATTR_PCIE_WA, -1);
 }
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 4f13fd037f04..faf4e3211918 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -39,25 +39,22 @@ static struct map_desc orion5x_io_desc[] __initdata = {
                 .virtual        = ORION5X_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
                 .length         = ORION5X_REGS_SIZE,
-                .type           = MT_DEVICE
-        },
-        {
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = ORION5X_PCIE_IO_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
                 .length         = ORION5X_PCIE_IO_SIZE,
-                .type           = MT_DEVICE
-        },
-        {
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = ORION5X_PCI_IO_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
                 .length         = ORION5X_PCI_IO_SIZE,
-                .type           = MT_DEVICE
-        },
-        {
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = ORION5X_PCIE_WA_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
                 .length         = ORION5X_PCIE_WA_SIZE,
-                .type           = MT_DEVICE
+                .type           = MT_DEVICE,
         },
 };
 
@@ -66,101 +63,32 @@ void __init orion5x_map_io(void)
         iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
 }
 
+
 /*****************************************************************************
- * UART
+ * EHCI
  ****************************************************************************/
-
-static struct resource orion5x_uart_resources[] = {
-        {
-                .start          = UART0_PHYS_BASE,
-                .end            = UART0_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = IRQ_ORION5X_UART0,
-                .end            = IRQ_ORION5X_UART0,
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .start          = UART1_PHYS_BASE,
-                .end            = UART1_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = IRQ_ORION5X_UART1,
-                .end            = IRQ_ORION5X_UART1,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct plat_serial8250_port orion5x_uart_data[] = {
-        {
-                .mapbase        = UART0_PHYS_BASE,
-                .membase        = (char *)UART0_VIRT_BASE,
-                .irq            = IRQ_ORION5X_UART0,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = ORION5X_TCLK,
-        },
-        {
-                .mapbase        = UART1_PHYS_BASE,
-                .membase        = (char *)UART1_VIRT_BASE,
-                .irq            = IRQ_ORION5X_UART1,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = ORION5X_TCLK,
-        },
-        { },
+static struct orion_ehci_data orion5x_ehci_data = {
+        .dram           = &orion5x_mbus_dram_info,
 };
 
-static struct platform_device orion5x_uart = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = orion5x_uart_data,
-        },
-        .resource               = orion5x_uart_resources,
-        .num_resources          = ARRAY_SIZE(orion5x_uart_resources),
-};
+static u64 ehci_dmamask = 0xffffffffUL;
 
-/*******************************************************************************
- * USB Controller - 2 interfaces
- ******************************************************************************/
 
+/*****************************************************************************
+ * EHCI0
+ ****************************************************************************/
 static struct resource orion5x_ehci0_resources[] = {
         {
                 .start  = ORION5X_USB0_PHYS_BASE,
                 .end    = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
                 .flags  = IORESOURCE_MEM,
-        },
-        {
+        }, {
                 .start  = IRQ_ORION5X_USB0_CTRL,
                 .end    = IRQ_ORION5X_USB0_CTRL,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
-static struct resource orion5x_ehci1_resources[] = {
-        {
-                .start  = ORION5X_USB1_PHYS_BASE,
-                .end    = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = IRQ_ORION5X_USB1_CTRL,
-                .end    = IRQ_ORION5X_USB1_CTRL,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct orion_ehci_data orion5x_ehci_data = {
-        .dram           = &orion5x_mbus_dram_info,
-};
-
-static u64 ehci_dmamask = 0xffffffffUL;
-
 static struct platform_device orion5x_ehci0 = {
         .name           = "orion-ehci",
         .id             = 0,
@@ -173,6 +101,27 @@ static struct platform_device orion5x_ehci0 = {
         .num_resources  = ARRAY_SIZE(orion5x_ehci0_resources),
 };
 
+void __init orion5x_ehci0_init(void)
+{
+        platform_device_register(&orion5x_ehci0);
+}
+
+
+/*****************************************************************************
+ * EHCI1
+ ****************************************************************************/
+static struct resource orion5x_ehci1_resources[] = {
+        {
+                .start  = ORION5X_USB1_PHYS_BASE,
+                .end    = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_ORION5X_USB1_CTRL,
+                .end    = IRQ_ORION5X_USB1_CTRL,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
 static struct platform_device orion5x_ehci1 = {
         .name           = "orion-ehci",
         .id             = 1,
@@ -185,11 +134,15 @@ static struct platform_device orion5x_ehci1 = {
         .num_resources  = ARRAY_SIZE(orion5x_ehci1_resources),
 };
 
+void __init orion5x_ehci1_init(void)
+{
+        platform_device_register(&orion5x_ehci1);
+}
+
+
 /*****************************************************************************
- * Gigabit Ethernet port
- * (The Orion and Discovery (MV643xx) families use the same Ethernet driver)
+ * GigE
  ****************************************************************************/
-
 struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
         .dram           = &orion5x_mbus_dram_info,
         .t_clk          = ORION5X_TCLK,
@@ -219,7 +172,7 @@ static struct resource orion5x_eth_resources[] = {
                 .start  = IRQ_ORION5X_ETH_SUM,
                 .end    = IRQ_ORION5X_ETH_SUM,
                 .flags  = IORESOURCE_IRQ,
-        }
+        },
 };
 
 static struct platform_device orion5x_eth = {
@@ -238,11 +191,10 @@ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
         platform_device_register(&orion5x_eth);
 }
 
+
 /*****************************************************************************
- * I2C controller
- * (The Orion and Discovery (MV643xx) families share the same I2C controller)
+ * I2C
  ****************************************************************************/
-
 static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
         .freq_m         = 8, /* assumes 166 MHz TCLK */
         .freq_n         = 3,
@@ -251,16 +203,15 @@ static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
 
 static struct resource orion5x_i2c_resources[] = {
         {
-                .name   = "i2c base",
-                .start  = I2C_PHYS_BASE,
-                .end    = I2C_PHYS_BASE + 0x20 -1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "i2c irq",
-                .start  = IRQ_ORION5X_I2C,
-                .end    = IRQ_ORION5X_I2C,
-                .flags  = IORESOURCE_IRQ,
+                .name   = "i2c base",
+                .start  = I2C_PHYS_BASE,
+                .end    = I2C_PHYS_BASE + 0x1f,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "i2c irq",
+                .start  = IRQ_ORION5X_I2C,
+                .end    = IRQ_ORION5X_I2C,
+                .flags  = IORESOURCE_IRQ,
         },
 };
 
@@ -270,36 +221,41 @@ static struct platform_device orion5x_i2c = {
         .num_resources  = ARRAY_SIZE(orion5x_i2c_resources),
         .resource       = orion5x_i2c_resources,
         .dev            = {
-                .platform_data = &orion5x_i2c_pdata,
+                .platform_data  = &orion5x_i2c_pdata,
         },
 };
 
+void __init orion5x_i2c_init(void)
+{
+        platform_device_register(&orion5x_i2c);
+}
+
+
 /*****************************************************************************
- * Sata port
+ * SATA
  ****************************************************************************/
 static struct resource orion5x_sata_resources[] = {
-        {
-                .name   = "sata base",
-                .start  = ORION5X_SATA_PHYS_BASE,
-                .end    = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
         {
-                .name   = "sata irq",
-                .start  = IRQ_ORION5X_SATA,
-                .end    = IRQ_ORION5X_SATA,
-                .flags  = IORESOURCE_IRQ,
-        },
+                .name   = "sata base",
+                .start  = ORION5X_SATA_PHYS_BASE,
+                .end    = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "sata irq",
+                .start  = IRQ_ORION5X_SATA,
+                .end    = IRQ_ORION5X_SATA,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 
 static struct platform_device orion5x_sata = {
-        .name           = "sata_mv",
-        .id             = 0,
+        .name           = "sata_mv",
+        .id             = 0,
         .dev            = {
                 .coherent_dma_mask      = 0xffffffff,
         },
-        .num_resources  = ARRAY_SIZE(orion5x_sata_resources),
-        .resource       = orion5x_sata_resources,
+        .num_resources  = ARRAY_SIZE(orion5x_sata_resources),
+        .resource       = orion5x_sata_resources,
 };
 
 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
@@ -309,23 +265,111 @@ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
         platform_device_register(&orion5x_sata);
 }
 
+
 /*****************************************************************************
- * Time handling
+ * UART0
+ ****************************************************************************/
+static struct plat_serial8250_port orion5x_uart0_data[] = {
+        {
+                .mapbase        = UART0_PHYS_BASE,
+                .membase        = (char *)UART0_VIRT_BASE,
+                .irq            = IRQ_ORION5X_UART0,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = ORION5X_TCLK,
+        }, {
+        },
+};
+
+static struct resource orion5x_uart0_resources[] = {
+        {
+                .start          = UART0_PHYS_BASE,
+                .end            = UART0_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_ORION5X_UART0,
+                .end            = IRQ_ORION5X_UART0,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device orion5x_uart0 = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev                    = {
+                .platform_data  = orion5x_uart0_data,
+        },
+        .resource               = orion5x_uart0_resources,
+        .num_resources          = ARRAY_SIZE(orion5x_uart0_resources),
+};
+
+void __init orion5x_uart0_init(void)
+{
+        platform_device_register(&orion5x_uart0);
+}
+
+
+/*****************************************************************************
+ * UART1
  ****************************************************************************/
+static struct plat_serial8250_port orion5x_uart1_data[] = {
+        {
+                .mapbase        = UART1_PHYS_BASE,
+                .membase        = (char *)UART1_VIRT_BASE,
+                .irq            = IRQ_ORION5X_UART1,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = ORION5X_TCLK,
+        }, {
+        },
+};
+
+static struct resource orion5x_uart1_resources[] = {
+        {
+                .start          = UART1_PHYS_BASE,
+                .end            = UART1_PHYS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_ORION5X_UART1,
+                .end            = IRQ_ORION5X_UART1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device orion5x_uart1 = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM1,
+        .dev                    = {
+                .platform_data  = orion5x_uart1_data,
+        },
+        .resource               = orion5x_uart1_resources,
+        .num_resources          = ARRAY_SIZE(orion5x_uart1_resources),
+};
+
+void __init orion5x_uart1_init(void)
+{
+        platform_device_register(&orion5x_uart1);
+}
+
 
+/*****************************************************************************
+ * Time handling
+ ****************************************************************************/
 static void orion5x_timer_init(void)
 {
         orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK);
 }
 
 struct sys_timer orion5x_timer = {
-        .init = orion5x_timer_init,
+        .init = orion5x_timer_init,
 };
 
+
 /*****************************************************************************
  * General
  ****************************************************************************/
-
 /*
  * Identify device ID and rev from PCIe configuration header space '0'.
  */
@@ -350,8 +394,10 @@ static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
         } else if (*dev == MV88F5181_DEV_ID) {
                 if (*rev == MV88F5181_REV_B1) {
                         *dev_name = "MV88F5181-Rev-B1";
+                } else if (*rev == MV88F5181L_REV_A1) {
+                        *dev_name = "MV88F5181L-Rev-A1";
                 } else {
-                        *dev_name = "MV88F5181-Rev-Unsupported";
+                        *dev_name = "MV88F5181(L)-Rev-Unsupported";
                 }
         } else {
                 *dev_name = "Device-Unknown";
@@ -370,15 +416,6 @@ void __init orion5x_init(void)
          * Setup Orion address map
          */
         orion5x_setup_cpu_mbus_bridge();
-
-        /*
-         * Register devices.
-         */
-        platform_device_register(&orion5x_uart);
-        platform_device_register(&orion5x_ehci0);
-        if (dev == MV88F5182_DEV_ID)
-                platform_device_register(&orion5x_ehci1);
-        platform_device_register(&orion5x_i2c);
 }
 
 /*
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index bd0f05de6e18..f72cf0e77544 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -1,10 +1,12 @@
 #ifndef __ARCH_ORION5X_COMMON_H
 #define __ARCH_ORION5X_COMMON_H
 
+struct mv643xx_eth_platform_data;
+struct mv_sata_platform_data;
+
 /*
  * Basic Orion init functions used early by machine-setup.
  */
-
 void orion5x_map_io(void);
 void orion5x_init_irq(void);
 void orion5x_init(void);
@@ -23,15 +25,22 @@ void orion5x_setup_dev1_win(u32 base, u32 size);
 void orion5x_setup_dev2_win(u32 base, u32 size);
 void orion5x_setup_pcie_wa_win(u32 base, u32 size);
 
+void orion5x_ehci0_init(void);
+void orion5x_ehci1_init(void);
+void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
+void orion5x_i2c_init(void);
+void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
+void orion5x_uart0_init(void);
+void orion5x_uart1_init(void);
+
 /*
- * Shared code used internally by other Orion core functions.
- * (/mach-orion/pci.c)
+ * PCIe/PCI functions.
  */
-
-struct pci_sys_data;
 struct pci_bus;
+struct pci_sys_data;
 
 void orion5x_pcie_id(u32 *dev, u32 *rev);
+void orion5x_pci_set_cardbus_mode(void);
 int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
 struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
 int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
@@ -40,26 +49,9 @@ int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
  * Valid GPIO pins according to MPP setup, used by machine-setup.
  * (/mach-orion/gpio.c).
  */
-
-void orion5x_gpio_set_valid_pins(u32 pins);
+void orion5x_gpio_set_valid(unsigned pin, int valid);
 void gpio_display(void);        /* debug */
 
-/*
- * Pull in Orion Ethernet platform_data, used by machine-setup
- */
-
-struct mv643xx_eth_platform_data;
-
-void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
-
-/*
- * Orion Sata platform_data, used by machine-setup
- */
-
-struct mv_sata_platform_data;
-
-void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
-
 struct machine_desc;
 struct meminfo;
 struct tag;
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 44c64342dacb..88405e74e5e3 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -27,6 +27,7 @@
 #include <asm/arch/orion5x.h>
 #include <asm/plat-orion/orion_nand.h>
 #include "common.h"
+#include "mpp.h"
 
 /*****************************************************************************
  * DB-88F5281 on board devices
@@ -86,7 +87,7 @@ static struct platform_device db88f5281_boot_flash = {
         .name           = "physmap-flash",
         .id             = 0,
         .dev            = {
-                .platform_data = &db88f5281_boot_flash_data,
+                .platform_data  = &db88f5281_boot_flash_data,
         },
         .num_resources  = 1,
         .resource       = &db88f5281_boot_flash_resource,
@@ -110,7 +111,7 @@ static struct platform_device db88f5281_nor_flash = {
         .name           = "physmap-flash",
         .id             = 1,
         .dev            = {
-                .platform_data = &db88f5281_nor_flash_data,
+                .platform_data  = &db88f5281_nor_flash_data,
         },
         .num_resources  = 1,
         .resource       = &db88f5281_nor_flash_resource,
@@ -125,18 +126,15 @@ static struct mtd_partition db88f5281_nand_parts[] = {
                 .name = "kernel",
                 .offset = 0,
                 .size = SZ_2M,
-        },
-        {
+        }, {
                 .name = "root",
                 .offset = SZ_2M,
                 .size = (SZ_16M - SZ_2M),
-        },
-        {
+        }, {
                 .name = "user",
                 .offset = SZ_16M,
                 .size = SZ_8M,
-        },
-        {
+        }, {
                 .name = "recovery",
                 .offset = (SZ_16M + SZ_8M),
                 .size = SZ_8M,
@@ -288,7 +286,6 @@ subsys_initcall(db88f5281_pci_init);
  ****************************************************************************/
 static struct mv643xx_eth_platform_data db88f5281_eth_data = {
         .phy_addr       = 8,
-        .force_phy_addr = 1,
 };
 
 /*****************************************************************************
@@ -301,11 +298,28 @@ static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-
-static struct platform_device *db88f5281_devs[] __initdata = {
-        &db88f5281_boot_flash,
-        &db88f5281_nor_flash,
-        &db88f5281_nand_flash,
+static struct orion5x_mpp_mode db88f5281_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* USB Over Current */
+        {  1, MPP_GPIO },               /* USB Vbat input */
+        {  2, MPP_PCI_ARB },            /* PCI_REQn[2] */
+        {  3, MPP_PCI_ARB },            /* PCI_GNTn[2] */
+        {  4, MPP_PCI_ARB },            /* PCI_REQn[3] */
+        {  5, MPP_PCI_ARB },            /* PCI_GNTn[3] */
+        {  6, MPP_GPIO },               /* JP0, CON17.2 */
+        {  7, MPP_GPIO },               /* JP1, CON17.1 */
+        {  8, MPP_GPIO },               /* JP2, CON11.2 */
+        {  9, MPP_GPIO },               /* JP3, CON11.3 */
+        { 10, MPP_GPIO },               /* RTC int */
+        { 11, MPP_GPIO },               /* Baud Rate Generator */
+        { 12, MPP_GPIO },               /* PCI int 1 */
+        { 13, MPP_GPIO },               /* PCI int 2 */
+        { 14, MPP_NAND },               /* NAND_REn[2] */
+        { 15, MPP_NAND },               /* NAND_WEn[2] */
+        { 16, MPP_UART },               /* UART1_RX */
+        { 17, MPP_UART },               /* UART1_TX */
+        { 18, MPP_UART },               /* UART1_CTSn */
+        { 19, MPP_UART },               /* UART1_RTSn */
+        { -1 },
 };
 
 static void __init db88f5281_init(void)
@@ -315,39 +329,31 @@ static void __init db88f5281_init(void)
          */
         orion5x_init();
 
+        orion5x_mpp_conf(db88f5281_mpp_modes);
+        writel(0, MPP_DEV_CTRL);                /* DEV_D[31:16] */
+
         /*
-         * Setup the CPU address decode windows for our on-board devices
+         * Configure peripherals.
          */
+        orion5x_ehci0_init();
+        orion5x_eth_init(&db88f5281_eth_data);
+        orion5x_i2c_init();
+        orion5x_uart0_init();
+        orion5x_uart1_init();
+
         orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE,
                                 DB88F5281_NOR_BOOT_SIZE);
+        platform_device_register(&db88f5281_boot_flash);
+
         orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE);
-        orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
-        orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
 
-        /*
-         * Setup Multiplexing Pins:
-         * MPP0: GPIO (USB Over Current)        MPP1: GPIO (USB Vbat input)
-         * MPP2: PCI_REQn[2]                    MPP3: PCI_GNTn[2]
-         * MPP4: PCI_REQn[3]                    MPP5: PCI_GNTn[3]
-         * MPP6: GPIO (JP0, CON17.2)            MPP7: GPIO (JP1, CON17.1)
-         * MPP8: GPIO (JP2, CON11.2)            MPP9: GPIO (JP3, CON11.3)
-         * MPP10: GPIO (RTC int)                MPP11: GPIO (Baud Rate Generator)
-         * MPP12: GPIO (PCI int 1)              MPP13: GPIO (PCI int 2)
-         * MPP14: NAND_REn[2]                   MPP15: NAND_WEn[2]
-         * MPP16: UART1_RX                      MPP17: UART1_TX
-         * MPP18: UART1_CTS                     MPP19: UART1_RTS
-         * MPP-DEV: DEV_D[16:31]
-         */
-        orion5x_write(MPP_0_7_CTRL, 0x00222203);
-        orion5x_write(MPP_8_15_CTRL, 0x44000000);
-        orion5x_write(MPP_16_19_CTRL, 0);
-        orion5x_write(MPP_DEV_CTRL, 0);
+        orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
+        platform_device_register(&db88f5281_nor_flash);
 
-        orion5x_gpio_set_valid_pins(0x00003fc3);
+        orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
+        platform_device_register(&db88f5281_nand_flash);
 
-        platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs));
         i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
-        orion5x_eth_init(&db88f5281_eth_data);
 }
 
 MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 27ce967ab9e5..3791ca6f001a 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -27,6 +27,7 @@
 #include <asm/mach/pci.h>
 #include <asm/arch/orion5x.h>
 #include "common.h"
+#include "mpp.h"
 
 #define DNS323_GPIO_LED_RIGHT_AMBER     1
 #define DNS323_GPIO_LED_LEFT_AMBER      2
@@ -52,8 +53,6 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
         if (irq != -1)
                 return irq;
 
-        pr_err("%s: requested mapping for unknown device\n", __func__);
-
         return -1;
 }
 
@@ -81,7 +80,6 @@ subsys_initcall(dns323_pci_init);
 
 static struct mv643xx_eth_platform_data dns323_eth_data = {
         .phy_addr = 8,
-        .force_phy_addr = 1,
 };
 
 /****************************************************************************
@@ -119,7 +117,7 @@ static struct mtd_partition dns323_partitions[] = {
                 .name   = "u-boot",
                 .size   = 0x00030000,
                 .offset = 0x007d0000,
-        }
+        },
 };
 
 static struct physmap_flash_data dns323_nor_flash_data = {
@@ -137,7 +135,9 @@ static struct resource dns323_nor_flash_resource = {
 static struct platform_device dns323_nor_flash = {
         .name           = "physmap-flash",
         .id             = 0,
-        .dev            = { .platform_data = &dns323_nor_flash_data, },
+        .dev            = {
+                .platform_data  = &dns323_nor_flash_data,
+        },
         .resource       = &dns323_nor_flash_resource,
         .num_resources  = 1,
 };
@@ -170,7 +170,9 @@ static struct gpio_led_platform_data dns323_led_data = {
 static struct platform_device dns323_gpio_leds = {
         .name           = "leds-gpio",
         .id             = -1,
-        .dev            = { .platform_data = &dns323_led_data, },
+        .dev            = {
+                .platform_data  = &dns323_led_data,
+        },
 };
 
 /****************************************************************************
@@ -183,35 +185,53 @@ static struct gpio_keys_button dns323_buttons[] = {
                 .gpio           = DNS323_GPIO_KEY_RESET,
                 .desc           = "Reset Button",
                 .active_low     = 1,
-        },
-        {
+        }, {
                 .code           = KEY_POWER,
                 .gpio           = DNS323_GPIO_KEY_POWER,
                 .desc           = "Power Button",
                 .active_low     = 1,
-        }
+        },
 };
 
 static struct gpio_keys_platform_data dns323_button_data = {
         .buttons        = dns323_buttons,
-        .nbuttons       = ARRAY_SIZE(dns323_buttons),
+        .nbuttons       = ARRAY_SIZE(dns323_buttons),
 };
 
 static struct platform_device dns323_button_device = {
         .name           = "gpio-keys",
         .id             = -1,
         .num_resources  = 0,
-        .dev            = { .platform_data  = &dns323_button_data, },
+        .dev            = {
+                .platform_data  = &dns323_button_data,
+        },
 };
 
 /****************************************************************************
  * General Setup
  */
-
-static struct platform_device *dns323_plat_devices[] __initdata = {
-        &dns323_nor_flash,
-        &dns323_gpio_leds,
-        &dns323_button_device,
+static struct orion5x_mpp_mode dns323_mpp_modes[] __initdata = {
+        {  0, MPP_PCIE_RST_OUTn },
+        {  1, MPP_GPIO },               /* right amber LED (sata ch0) */
+        {  2, MPP_GPIO },               /* left amber LED (sata ch1) */
+        {  3, MPP_UNUSED },
+        {  4, MPP_GPIO },               /* power button LED */
+        {  5, MPP_GPIO },               /* power button LED */
+        {  6, MPP_GPIO },               /* GMT G751-2f overtemp */
+        {  7, MPP_GPIO },               /* M41T80 nIRQ/OUT/SQW */
+        {  8, MPP_GPIO },               /* triggers power off */
+        {  9, MPP_GPIO },               /* power button switch */
+        { 10, MPP_GPIO },               /* reset button switch */
+        { 11, MPP_UNUSED },
+        { 12, MPP_UNUSED },
+        { 13, MPP_UNUSED },
+        { 14, MPP_UNUSED },
+        { 15, MPP_UNUSED },
+        { 16, MPP_UNUSED },
+        { 17, MPP_UNUSED },
+        { 18, MPP_UNUSED },
+        { 19, MPP_UNUSED },
+        { -1 },
 };
 
 /*
@@ -225,17 +245,15 @@ static struct platform_device *dns323_plat_devices[] __initdata = {
 static struct i2c_board_info __initdata dns323_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("g760a", 0x3e),
-        },
 #if 0
         /* this entry requires the new-style driver model lm75 driver,
          * for the meantime "insmod lm75.ko force_lm75=0,0x48" is needed */
-        {
+        }, {
                 I2C_BOARD_INFO("g751", 0x48),
-        },
 #endif
-        {
+        }, {
                 I2C_BOARD_INFO("m41t80", 0x68),
-        }
+        },
 };
 
 /* DNS-323 specific power off method */
@@ -250,62 +268,35 @@ static void __init dns323_init(void)
         /* Setup basic Orion functions. Need to be called early. */
         orion5x_init();
 
+        orion5x_mpp_conf(dns323_mpp_modes);
+        writel(0, MPP_DEV_CTRL);                /* DEV_D[31:16] */
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_eth_init(&dns323_eth_data);
+        orion5x_i2c_init();
+        orion5x_uart0_init();
+
         /* setup flash mapping
          * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
          */
         orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
+        platform_device_register(&dns323_nor_flash);
 
-        /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIe
-         *
-         * Open a special address decode windows for the PCIe WA.
-         */
-        orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
-                                ORION5X_PCIE_WA_SIZE);
-
-        /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
-        orion5x_write(MPP_0_7_CTRL, 0);
-        orion5x_write(MPP_8_15_CTRL, 0);
-        orion5x_write(MPP_16_19_CTRL, 0);
-        orion5x_write(MPP_DEV_CTRL, 0);
-
-        /* Define used GPIO pins
-
-          GPIO Map:
-
-          |  0 |     | PEX_RST_OUT (not controlled by GPIO)
-          |  1 | Out | right amber LED (= sata ch0 LED)  (low-active)
-          |  2 | Out | left  amber LED (= sata ch1 LED)  (low-active)
-          |  3 | Out | //unknown//
-          |  4 | Out | power button LED (low-active, together with pin #5)
-          |  5 | Out | power button LED (low-active, together with pin #4)
-          |  6 | In  | GMT G751-2f overtemp. shutdown signal (low-active)
-          |  7 | In  | M41T80 nIRQ/OUT/SQW signal
-          |  8 | Out | triggers power off (high-active)
-          |  9 | In  | power button switch (low-active)
-          | 10 | In  | reset button switch (low-active)
-          | 11 | Out | //unknown//
-          | 12 | Out | //unknown//
-          | 13 | Out | //unknown//
-          | 14 | Out | //unknown//
-          | 15 | Out | //unknown//
-        */
-        orion5x_gpio_set_valid_pins(0x07f6);
-
-        /* register dns323 specific power-off method */
-        if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0)
-            || (gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0))
-                pr_err("DNS323: failed to setup power-off GPIO\n");
-
-        pm_power_off = dns323_power_off;
+        platform_device_register(&dns323_gpio_leds);
 
-        /* register flash and other platform devices */
-        platform_add_devices(dns323_plat_devices,
-                             ARRAY_SIZE(dns323_plat_devices));
+        platform_device_register(&dns323_button_device);
 
         i2c_register_board_info(0, dns323_i2c_devices,
                                 ARRAY_SIZE(dns323_i2c_devices));
 
-        orion5x_eth_init(&dns323_eth_data);
+        /* register dns323 specific power-off method */
+        if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+            gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
+                pr_err("DNS323: failed to setup power-off GPIO\n");
+        pm_power_off = dns323_power_off;
 }
 
 /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
diff --git a/arch/arm/mach-orion5x/gpio.c b/arch/arm/mach-orion5x/gpio.c
index 8108c316c426..d09797990f41 100644
--- a/arch/arm/mach-orion5x/gpio.c
+++ b/arch/arm/mach-orion5x/gpio.c
@@ -24,9 +24,12 @@ static DEFINE_SPINLOCK(gpio_lock);
 static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)];
 static const char *gpio_label[GPIO_MAX];  /* non null for allocated GPIOs */
 
-void __init orion5x_gpio_set_valid_pins(u32 pins)
+void __init orion5x_gpio_set_valid(unsigned pin, int valid)
 {
-        gpio_valid[0] = pins;
+        if (valid)
+                __set_bit(pin, gpio_valid);
+        else
+                __clear_bit(pin, gpio_valid);
 }
 
 /*
@@ -93,10 +96,10 @@ int gpio_get_value(unsigned pin)
 {
         int val, mask = 1 << pin;
 
-        if (orion5x_read(GPIO_IO_CONF) & mask)
-                val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL);
+        if (readl(GPIO_IO_CONF) & mask)
+                val = readl(GPIO_DATA_IN) ^ readl(GPIO_IN_POL);
         else
-                val = orion5x_read(GPIO_OUT);
+                val = readl(GPIO_OUT);
 
         return val & mask;
 }
@@ -188,39 +191,39 @@ void gpio_display(void)
                         printk("GPIO, free\n");
                 } else {
                         printk("GPIO, used by %s, ", gpio_label[i]);
-                        if (orion5x_read(GPIO_IO_CONF) & (1 << i)) {
+                        if (readl(GPIO_IO_CONF) & (1 << i)) {
                                 printk("input, active %s, level %s, edge %s\n",
-                                ((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
-                                ((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
-                                ((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
+                                ((readl(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
+                                ((readl(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
+                                ((readl(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
                         } else {
-                                printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1);
+                                printk("output, val=%d\n", (readl(GPIO_OUT) >> i) & 1);
                         }
                 }
         }
 
         printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n",
-                                MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL));
+                                MPP_0_7_CTRL, readl(MPP_0_7_CTRL));
         printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n",
-                                MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL));
+                                MPP_8_15_CTRL, readl(MPP_8_15_CTRL));
         printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n",
-                                MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL));
+                                MPP_16_19_CTRL, readl(MPP_16_19_CTRL));
         printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n",
-                                MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL));
+                                MPP_DEV_CTRL, readl(MPP_DEV_CTRL));
         printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n",
-                                GPIO_OUT, orion5x_read(GPIO_OUT));
+                                GPIO_OUT, readl(GPIO_OUT));
         printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n",
-                                GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF));
+                                GPIO_IO_CONF, readl(GPIO_IO_CONF));
         printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n",
-                                GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN));
+                                GPIO_BLINK_EN, readl(GPIO_BLINK_EN));
         printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n",
-                                GPIO_IN_POL, orion5x_read(GPIO_IN_POL));
+                                GPIO_IN_POL, readl(GPIO_IN_POL));
         printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n",
-                                GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN));
+                                GPIO_DATA_IN, readl(GPIO_DATA_IN));
         printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n",
-                                GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK));
+                                GPIO_LEVEL_MASK, readl(GPIO_LEVEL_MASK));
         printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n",
-                                GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE));
+                                GPIO_EDGE_CAUSE, readl(GPIO_EDGE_CAUSE));
         printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n",
-                                GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK));
+                                GPIO_EDGE_MASK, readl(GPIO_EDGE_MASK));
 }
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index dd21f38c5d37..e2a0084ab4a3 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -82,7 +82,7 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
         int pin = irq_to_gpio(irq);
         struct irq_desc *desc;
 
-        if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
+        if ((readl(GPIO_IO_CONF) & (1 << pin)) == 0) {
                 printk(KERN_ERR "orion5x_gpio_set_irq_type failed "
                                 "(irq %d, pin %d).\n", irq, pin);
                 return -EINVAL;
@@ -117,7 +117,7 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
                 /*
                  * set initial polarity based on current input level
                  */
-                if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN))
+                if ((readl(GPIO_IN_POL) ^ readl(GPIO_DATA_IN))
                     & (1 << pin))
                         orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
                 else
@@ -149,8 +149,8 @@ static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
         BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31);
         offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8;
-        cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) |
-                (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK));
+        cause = (readl(GPIO_DATA_IN) & readl(GPIO_LEVEL_MASK)) |
+                (readl(GPIO_EDGE_CAUSE) & readl(GPIO_EDGE_MASK));
 
         for (pin = offs; pin < offs + 8; pin++) {
                 if (cause & (1 << pin)) {
@@ -158,9 +158,9 @@ static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                         desc = irq_desc + irq;
                         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
                                 /* Swap polarity (race with GPIO line) */
-                                u32 polarity = orion5x_read(GPIO_IN_POL);
+                                u32 polarity = readl(GPIO_IN_POL);
                                 polarity ^= 1 << pin;
-                                orion5x_write(GPIO_IN_POL, polarity);
+                                writel(polarity, GPIO_IN_POL);
                         }
                         desc_handle_irq(irq, desc);
                 }
@@ -175,9 +175,9 @@ static void __init orion5x_init_gpio_irq(void)
         /*
          * Mask and clear GPIO IRQ interrupts
          */
-        orion5x_write(GPIO_LEVEL_MASK, 0x0);
-        orion5x_write(GPIO_EDGE_MASK, 0x0);
-        orion5x_write(GPIO_EDGE_CAUSE, 0x0);
+        writel(0x0, GPIO_LEVEL_MASK);
+        writel(0x0, GPIO_EDGE_MASK);
+        writel(0x0, GPIO_EDGE_CAUSE);
 
         /*
          * Register chained level handlers for GPIO IRQs by default.
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index f5074b877b7f..84feac4a1fe2 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -13,10 +13,12 @@
 #include <linux/platform_device.h>
 #include <linux/pci.h>
 #include <linux/irq.h>
+#include <linux/delay.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/nand.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/i2c.h>
+#include <linux/serial_reg.h>
 #include <linux/ata_platform.h>
 #include <asm/mach-types.h>
 #include <asm/gpio.h>
@@ -25,6 +27,7 @@
 #include <asm/arch/orion5x.h>
 #include <asm/plat-orion/orion_nand.h>
 #include "common.h"
+#include "mpp.h"
 
 /*****************************************************************************
  * KUROBOX-PRO Info
@@ -53,13 +56,11 @@ static struct mtd_partition kurobox_pro_nand_parts[] = {
                 .name   = "uImage",
                 .offset = 0,
                 .size   = SZ_4M,
-        },
-        {
+        }, {
                 .name   = "rootfs",
                 .offset = SZ_4M,
                 .size   = SZ_64M,
-        },
-        {
+        }, {
                 .name   = "extra",
                 .offset = SZ_4M + SZ_64M,
                 .size   = SZ_256M - (SZ_4M + SZ_64M),
@@ -132,8 +133,6 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
         /*
          * PCI isn't used on the Kuro
          */
-        printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n");
-
         return -1;
 }
 
@@ -161,7 +160,6 @@ subsys_initcall(kurobox_pro_pci_init);
 
 static struct mv643xx_eth_platform_data kurobox_pro_eth_data = {
         .phy_addr       = 8,
-        .force_phy_addr = 1,
 };
 
 /*****************************************************************************
@@ -175,12 +173,169 @@ static struct i2c_board_info __initdata kurobox_pro_i2c_rtc = {
  * SATA
  ****************************************************************************/
 static struct mv_sata_platform_data kurobox_pro_sata_data = {
-        .n_ports        = 2,
+        .n_ports        = 2,
 };
 
 /*****************************************************************************
+ * Kurobox Pro specific power off method via UART1-attached microcontroller
+ ****************************************************************************/
+
+#define UART1_REG(x)    (UART1_VIRT_BASE + ((UART_##x) << 2))
+
+static int kurobox_pro_miconread(unsigned char *buf, int count)
+{
+        int i;
+        int timeout;
+
+        for (i = 0; i < count; i++) {
+                timeout = 10;
+
+                while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {
+                        if (--timeout == 0)
+                                break;
+                        udelay(1000);
+                }
+
+                if (timeout == 0)
+                        break;
+                buf[i] = readl(UART1_REG(RX));
+        }
+
+        /* return read bytes */
+        return i;
+}
+
+static int kurobox_pro_miconwrite(const unsigned char *buf, int count)
+{
+        int i = 0;
+
+        while (count--) {
+                while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE))
+                        barrier();
+                writel(buf[i++], UART1_REG(TX));
+        }
+
+        return 0;
+}
+
+static int kurobox_pro_miconsend(const unsigned char *data, int count)
+{
+        int i;
+        unsigned char checksum = 0;
+        unsigned char recv_buf[40];
+        unsigned char send_buf[40];
+        unsigned char correct_ack[3];
+        int retry = 2;
+
+        /* Generate checksum */
+        for (i = 0; i < count; i++)
+                checksum -=  data[i];
+
+        do {
+                /* Send data */
+                kurobox_pro_miconwrite(data, count);
+
+                /* send checksum */
+                kurobox_pro_miconwrite(&checksum, 1);
+
+                if (kurobox_pro_miconread(recv_buf, sizeof(recv_buf)) <= 3) {
+                        printk(KERN_ERR ">%s: receive failed.\n", __func__);
+
+                        /* send preamble to clear the receive buffer */
+                        memset(&send_buf, 0xff, sizeof(send_buf));
+                        kurobox_pro_miconwrite(send_buf, sizeof(send_buf));
+
+                        /* make dummy reads */
+                        mdelay(100);
+                        kurobox_pro_miconread(recv_buf, sizeof(recv_buf));
+                } else {
+                        /* Generate expected ack */
+                        correct_ack[0] = 0x01;
+                        correct_ack[1] = data[1];
+                        correct_ack[2] = 0x00;
+
+                        /* checksum Check */
+                        if ((recv_buf[0] + recv_buf[1] + recv_buf[2] +
+                             recv_buf[3]) & 0xFF) {
+                                printk(KERN_ERR ">%s: Checksum Error : "
+                                        "Received data[%02x, %02x, %02x, %02x]"
+                                        "\n", __func__, recv_buf[0],
+                                        recv_buf[1], recv_buf[2], recv_buf[3]);
+                        } else {
+                                /* Check Received Data */
+                                if (correct_ack[0] == recv_buf[0] &&
+                                    correct_ack[1] == recv_buf[1] &&
+                                    correct_ack[2] == recv_buf[2]) {
+                                        /* Interval for next command */
+                                        mdelay(10);
+
+                                        /* Receive ACK */
+                                        return 0;
+                                }
+                        }
+                        /* Received NAK or illegal Data */
+                        printk(KERN_ERR ">%s: Error : NAK or Illegal Data "
+                                        "Received\n", __func__);
+                }
+        } while (retry--);
+
+        /* Interval for next command */
+        mdelay(10);
+
+        return -1;
+}
+
+static void kurobox_pro_power_off(void)
+{
+        const unsigned char watchdogkill[]      = {0x01, 0x35, 0x00};
+        const unsigned char shutdownwait[]      = {0x00, 0x0c};
+        const unsigned char poweroff[]          = {0x00, 0x06};
+        /* 38400 baud divisor */
+        const unsigned divisor = ((ORION5X_TCLK + (8 * 38400)) / (16 * 38400));
+
+        pr_info("%s: triggering power-off...\n", __func__);
+
+        /* hijack uart1 and reset into sane state (38400,8n1,even parity) */
+        writel(0x83, UART1_REG(LCR));
+        writel(divisor & 0xff, UART1_REG(DLL));
+        writel((divisor >> 8) & 0xff, UART1_REG(DLM));
+        writel(0x1b, UART1_REG(LCR));
+        writel(0x00, UART1_REG(IER));
+        writel(0x07, UART1_REG(FCR));
+        writel(0x00, UART1_REG(MCR));
+
+        /* Send the commands to shutdown the Kurobox Pro */
+        kurobox_pro_miconsend(watchdogkill, sizeof(watchdogkill)) ;
+        kurobox_pro_miconsend(shutdownwait, sizeof(shutdownwait)) ;
+        kurobox_pro_miconsend(poweroff, sizeof(poweroff));
+}
+
+/*****************************************************************************
  * General Setup
  ****************************************************************************/
+static struct orion5x_mpp_mode kurobox_pro_mpp_modes[] __initdata = {
+        {  0, MPP_UNUSED },
+        {  1, MPP_UNUSED },
+        {  2, MPP_GPIO },               /* GPIO Micon */
+        {  3, MPP_GPIO },               /* GPIO Rtc */
+        {  4, MPP_UNUSED },
+        {  5, MPP_UNUSED },
+        {  6, MPP_NAND },               /* NAND Flash REn */
+        {  7, MPP_NAND },               /* NAND Flash WEn */
+        {  8, MPP_UNUSED },
+        {  9, MPP_UNUSED },
+        { 10, MPP_UNUSED },
+        { 11, MPP_UNUSED },
+        { 12, MPP_SATA_LED },           /* SATA 0 presence */
+        { 13, MPP_SATA_LED },           /* SATA 1 presence */
+        { 14, MPP_SATA_LED },           /* SATA 0 active */
+        { 15, MPP_SATA_LED },           /* SATA 1 active */
+        { 16, MPP_UART },               /* UART1 RXD */
+        { 17, MPP_UART },               /* UART1 TXD */
+        { 18, MPP_UART },               /* UART1 CTSn */
+        { 19, MPP_UART },               /* UART1 RTSn */
+        { -1 },
+};
 
 static void __init kurobox_pro_init(void)
 {
@@ -189,46 +344,33 @@ static void __init kurobox_pro_init(void)
          */
         orion5x_init();
 
-        /*
-         * Setup the CPU address decode windows for our devices
-         */
-        orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE,
-                                KUROBOX_PRO_NOR_BOOT_SIZE);
-        orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE);
+        orion5x_mpp_conf(kurobox_pro_mpp_modes);
 
         /*
-         * Open a special address decode windows for the PCIe WA.
+         * Configure peripherals.
          */
-        orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
-                                ORION5X_PCIE_WA_SIZE);
-
-        /*
-         * Setup Multiplexing Pins --
-         * MPP[0-1] Not used
-         * MPP[2] GPIO Micon
-         * MPP[3] GPIO RTC
-         * MPP[4-5] Not used
-         * MPP[6] Nand Flash REn
-         * MPP[7] Nand Flash WEn
-         * MPP[8-11] Not used
-         * MPP[12] SATA 0 presence Indication
-         * MPP[13] SATA 1 presence Indication
-         * MPP[14] SATA 0 active Indication
-         * MPP[15] SATA 1 active indication
-         * MPP[16-19] Not used
-         */
-        orion5x_write(MPP_0_7_CTRL, 0x44220003);
-        orion5x_write(MPP_8_15_CTRL, 0x55550000);
-        orion5x_write(MPP_16_19_CTRL, 0x0);
-
-        orion5x_gpio_set_valid_pins(0x0000000c);
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        orion5x_eth_init(&kurobox_pro_eth_data);
+        orion5x_i2c_init();
+        orion5x_sata_init(&kurobox_pro_sata_data);
+        orion5x_uart0_init();
+        orion5x_uart1_init();
 
+        orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE,
+                                   KUROBOX_PRO_NOR_BOOT_SIZE);
         platform_device_register(&kurobox_pro_nor_flash);
-        if (machine_is_kurobox_pro())
+
+        if (machine_is_kurobox_pro()) {
+                orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE,
+                                       KUROBOX_PRO_NAND_SIZE);
                 platform_device_register(&kurobox_pro_nand_flash);
+        }
+
         i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
-        orion5x_eth_init(&kurobox_pro_eth_data);
-        orion5x_sata_init(&kurobox_pro_sata_data);
+
+        /* register Kurobox Pro specific power-off method */
+        pm_power_off = kurobox_pro_power_off;
 }
 
 #ifdef CONFIG_MACH_KUROBOX_PRO
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
new file mode 100644
index 000000000000..a48cadb01590
--- /dev/null
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -0,0 +1,163 @@
+/*
+ * arch/arm/mach-orion5x/mpp.c
+ *
+ * MPP functions for Marvell Orion 5x SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include "common.h"
+#include "mpp.h"
+
+static int is_5181l(void)
+{
+        u32 dev;
+        u32 rev;
+
+        orion5x_pcie_id(&dev, &rev);
+
+        return !!(dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0);
+}
+
+static int is_5182(void)
+{
+        u32 dev;
+        u32 rev;
+
+        orion5x_pcie_id(&dev, &rev);
+
+        return !!(dev == MV88F5182_DEV_ID);
+}
+
+static int is_5281(void)
+{
+        u32 dev;
+        u32 rev;
+
+        orion5x_pcie_id(&dev, &rev);
+
+        return !!(dev == MV88F5281_DEV_ID);
+}
+
+static int __init determine_type_encoding(int mpp, enum orion5x_mpp_type type)
+{
+        switch (type) {
+        case MPP_UNUSED:
+        case MPP_GPIO:
+                if (mpp == 0)
+                        return 3;
+                if (mpp >= 1 && mpp <= 15)
+                        return 0;
+                if (mpp >= 16 && mpp <= 19) {
+                        if (is_5182())
+                                return 5;
+                        if (type == MPP_UNUSED)
+                                return 0;
+                }
+                return -1;
+
+        case MPP_PCIE_RST_OUTn:
+                if (mpp == 0)
+                        return 0;
+                return -1;
+
+        case MPP_PCI_ARB:
+                if (mpp >= 0 && mpp <= 7)
+                        return 2;
+                return -1;
+
+        case MPP_PCI_PMEn:
+                if (mpp == 2)
+                        return 3;
+                return -1;
+
+        case MPP_GIGE:
+                if (mpp >= 8 && mpp <= 19)
+                        return 1;
+                return -1;
+
+        case MPP_NAND:
+                if (is_5182() || is_5281()) {
+                        if (mpp >= 4 && mpp <= 7)
+                                return 4;
+                        if (mpp >= 12 && mpp <= 17)
+                                return 4;
+                }
+                return -1;
+
+        case MPP_PCI_CLK:
+                if (is_5181l() && mpp >= 6 && mpp <= 7)
+                        return 5;
+                return -1;
+
+        case MPP_SATA_LED:
+                if (is_5182()) {
+                        if (mpp >= 4 && mpp <= 7)
+                                return 5;
+                        if (mpp >= 12 && mpp <= 15)
+                                return 5;
+                }
+                return -1;
+
+        case MPP_UART:
+                if (mpp >= 16 && mpp <= 19)
+                        return 0;
+                return -1;
+        }
+
+        printk(KERN_INFO "unknown MPP type %d\n", type);
+
+        return -1;
+}
+
+void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
+{
+        u32 mpp_0_7_ctrl = readl(MPP_0_7_CTRL);
+        u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
+        u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
+
+        while (mode->mpp >= 0) {
+                u32 *reg;
+                int num_type;
+                int shift;
+
+                if (mode->mpp >= 0 && mode->mpp <= 7)
+                        reg = &mpp_0_7_ctrl;
+                else if (mode->mpp >= 8 && mode->mpp <= 15)
+                        reg = &mpp_8_15_ctrl;
+                else if (mode->mpp >= 16 && mode->mpp <= 19)
+                        reg = &mpp_16_19_ctrl;
+                else {
+                        printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
+                                        "(%d)\n", mode->mpp);
+                        continue;
+                }
+
+                num_type = determine_type_encoding(mode->mpp, mode->type);
+                if (num_type < 0) {
+                        printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
+                                        "combination (%d, %d)\n", mode->mpp,
+                                        mode->type);
+                        continue;
+                }
+
+                shift = (mode->mpp & 7) << 2;
+                *reg &= ~(0xf << shift);
+                *reg |= (num_type & 0xf) << shift;
+
+                orion5x_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO));
+
+                mode++;
+        }
+
+        writel(mpp_0_7_ctrl, MPP_0_7_CTRL);
+        writel(mpp_8_15_ctrl, MPP_8_15_CTRL);
+        writel(mpp_16_19_ctrl, MPP_16_19_CTRL);
+}
diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h
new file mode 100644
index 000000000000..290e610dc012
--- /dev/null
+++ b/arch/arm/mach-orion5x/mpp.h
@@ -0,0 +1,74 @@
+#ifndef __ARCH_ORION5X_MPP_H
+#define __ARCH_ORION5X_MPP_H
+
+enum orion5x_mpp_type {
+        /*
+         * This MPP is unused.
+         */
+        MPP_UNUSED,
+
+        /*
+         * This MPP pin is used as a generic GPIO pin.  Valid for
+         * MPPs 0-15 and device bus data pins 16-31.  On 5182, also
+         * valid for MPPs 16-19.
+         */
+        MPP_GPIO,
+
+        /*
+         * This MPP is used as PCIe_RST_OUTn pin.  Valid for
+         * MPP 0 only.
+         */
+        MPP_PCIE_RST_OUTn,
+
+        /*
+         * This MPP is used as PCI arbiter pin (REQn/GNTn).
+         * Valid for MPPs 0-7 only.
+         */
+        MPP_PCI_ARB,
+
+        /*
+         * This MPP is used as PCI_PMEn pin.  Valid for MPP 2 only.
+         */
+        MPP_PCI_PMEn,
+
+        /*
+         * This MPP is used as GigE half-duplex (COL, CRS) or GMII
+         * (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin.  Valid for
+         * MPPs 8-19 only.
+         */
+        MPP_GIGE,
+
+        /*
+         * This MPP is used as NAND REn/WEn pin.  Valid for MPPs
+         * 4-7 and 12-17 only, and only on the 5181l/5182/5281.
+         */
+        MPP_NAND,
+
+        /*
+         * This MPP is used as a PCI clock output pin.  Valid for
+         * MPPs 6-7 only, and only on the 5181l.
+         */
+        MPP_PCI_CLK,
+
+        /*
+         * This MPP is used as a SATA presence/activity LED.
+         * Valid for MPPs 4-7 and 12-15 only, and only on the 5182.
+         */
+        MPP_SATA_LED,
+
+        /*
+         * This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin.
+         * Valid for MPPs 16-19 only.
+         */
+        MPP_UART,
+};
+
+struct orion5x_mpp_mode {
+        int                     mpp;
+        enum orion5x_mpp_type   type;
+};
+
+void orion5x_mpp_conf(struct orion5x_mpp_mode *mode);
+
+
+#endif
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
new file mode 100644
index 000000000000..7ce9e407d9d1
--- /dev/null
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -0,0 +1,270 @@
+/*
+ * Maxtor Shared Storage II Board Setup
+ *
+ * Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/leds.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+#define MSS2_NOR_BOOT_BASE      0xff800000
+#define MSS2_NOR_BOOT_SIZE      SZ_256K
+
+/*****************************************************************************
+ * Maxtor Shared Storage II Info
+ ****************************************************************************/
+
+/*
+ * Maxtor Shared Storage II hardware :
+ * - Marvell 88F5182-A2 C500
+ * - Marvell 88E1111 Gigabit Ethernet PHY
+ * - RTC M41T81 (@0x68) on I2C bus
+ * - 256KB NOR flash
+ * - 64MB of RAM
+ */
+
+/*****************************************************************************
+ * 256KB NOR Flash on BOOT Device
+ ****************************************************************************/
+
+static struct physmap_flash_data mss2_nor_flash_data = {
+        .width          = 1,
+};
+
+static struct resource mss2_nor_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = MSS2_NOR_BOOT_BASE,
+        .end            = MSS2_NOR_BOOT_BASE + MSS2_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device mss2_nor_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &mss2_nor_flash_data,
+        },
+        .resource       = &mss2_nor_flash_resource,
+        .num_resources  = 1,
+};
+
+/****************************************************************************
+ * PCI setup
+ ****************************************************************************/
+static int __init mss2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq;
+
+        /*
+         * Check for devices with hard-wired IRQs.
+         */
+        irq = orion5x_pci_map_irq(dev, slot, pin);
+        if (irq != -1)
+                return irq;
+
+        return -1;
+}
+
+static struct hw_pci mss2_pci __initdata = {
+        .nr_controllers = 2,
+        .swizzle        = pci_std_swizzle,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = mss2_pci_map_irq,
+};
+
+static int __init mss2_pci_init(void)
+{
+        if (machine_is_mss2())
+                pci_common_init(&mss2_pci);
+
+        return 0;
+}
+subsys_initcall(mss2_pci_init);
+
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+static struct mv643xx_eth_platform_data mss2_eth_data = {
+        .phy_addr       = 8,
+};
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+
+static struct mv_sata_platform_data mss2_sata_data = {
+        .n_ports        = 2,
+};
+
+/*****************************************************************************
+ * GPIO buttons
+ ****************************************************************************/
+
+#define MSS2_GPIO_KEY_RESET     12
+#define MSS2_GPIO_KEY_POWER     11
+
+static struct gpio_keys_button mss2_buttons[] = {
+        {
+                .code           = KEY_POWER,
+                .gpio           = MSS2_GPIO_KEY_POWER,
+                .desc           = "Power",
+                .active_low     = 1,
+        }, {
+                .code           = KEY_RESTART,
+                .gpio           = MSS2_GPIO_KEY_RESET,
+                .desc           = "Reset",
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data mss2_button_data = {
+        .buttons        = mss2_buttons,
+        .nbuttons       = ARRAY_SIZE(mss2_buttons),
+};
+
+static struct platform_device mss2_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &mss2_button_data,
+        },
+};
+
+/*****************************************************************************
+ * RTC m41t81 on I2C bus
+ ****************************************************************************/
+
+#define MSS2_GPIO_RTC_IRQ       3
+
+static struct i2c_board_info __initdata mss2_i2c_rtc = {
+        I2C_BOARD_INFO("m41t81", 0x68),
+};
+
+/*****************************************************************************
+ * MSS2 power off method
+ ****************************************************************************/
+/*
+ * On the Maxtor Shared Storage II, the shutdown process is the following :
+ * - Userland modifies U-boot env to tell U-boot to go idle at next boot
+ * - The board reboots
+ * - U-boot starts and go into an idle mode until the user press "power"
+ */
+static void mss2_power_off(void)
+{
+        u32 reg;
+
+        /*
+         * Enable and issue soft reset
+         */
+        reg = readl(CPU_RESET_MASK);
+        reg |= 1 << 2;
+        writel(reg, CPU_RESET_MASK);
+
+        reg = readl(CPU_SOFT_RESET);
+        reg |= 1;
+        writel(reg, CPU_SOFT_RESET);
+}
+
+/****************************************************************************
+ * General Setup
+ ****************************************************************************/
+static struct orion5x_mpp_mode mss2_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* Power LED */
+        {  1, MPP_GPIO },               /* Error LED */
+        {  2, MPP_UNUSED },
+        {  3, MPP_GPIO },               /* RTC interrupt */
+        {  4, MPP_GPIO },               /* HDD ind. (Single/Dual)*/
+        {  5, MPP_GPIO },               /* HD0 5V control */
+        {  6, MPP_GPIO },               /* HD0 12V control */
+        {  7, MPP_GPIO },               /* HD1 5V control */
+        {  8, MPP_GPIO },               /* HD1 12V control */
+        {  9, MPP_UNUSED },
+        { 10, MPP_GPIO },               /* Fan control */
+        { 11, MPP_GPIO },               /* Power button */
+        { 12, MPP_GPIO },               /* Reset button */
+        { 13, MPP_UNUSED },
+        { 14, MPP_SATA_LED },           /* SATA 0 active */
+        { 15, MPP_SATA_LED },           /* SATA 1 active */
+        { 16, MPP_UNUSED },
+        { 17, MPP_UNUSED },
+        { 18, MPP_UNUSED },
+        { 19, MPP_UNUSED },
+        { -1 },
+};
+
+static void __init mss2_init(void)
+{
+        /* Setup basic Orion functions. Need to be called early. */
+        orion5x_init();
+
+        orion5x_mpp_conf(mss2_mpp_modes);
+
+        /*
+         * MPP[20] Unused
+         * MPP[21] PCI clock
+         * MPP[22] USB 0 over current
+         * MPP[23] USB 1 over current
+         */
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        orion5x_eth_init(&mss2_eth_data);
+        orion5x_i2c_init();
+        orion5x_sata_init(&mss2_sata_data);
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(MSS2_NOR_BOOT_BASE, MSS2_NOR_BOOT_SIZE);
+        platform_device_register(&mss2_nor_flash);
+
+        platform_device_register(&mss2_button_device);
+
+        if (gpio_request(MSS2_GPIO_RTC_IRQ, "rtc") == 0) {
+                if (gpio_direction_input(MSS2_GPIO_RTC_IRQ) == 0)
+                        mss2_i2c_rtc.irq = gpio_to_irq(MSS2_GPIO_RTC_IRQ);
+                else
+                        gpio_free(MSS2_GPIO_RTC_IRQ);
+        }
+        i2c_register_board_info(0, &mss2_i2c_rtc, 1);
+
+        /* register mss2 specific power-off method */
+        pm_power_off = mss2_power_off;
+}
+
+MACHINE_START(MSS2, "Maxtor Shared Storage II")
+        /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = mss2_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
new file mode 100644
index 000000000000..55f3b0fdef8b
--- /dev/null
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
+ * Copyright (C) 2008 Martin Michlmayr <tbm@cyrius.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/leds.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/ata_platform.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+#include <asm/mach/arch.h>
+#include <asm/arch/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+#define MV2120_NOR_BOOT_BASE    0xf4000000
+#define MV2120_NOR_BOOT_SIZE    SZ_512K
+
+#define MV2120_GPIO_RTC_IRQ     3
+#define MV2120_GPIO_KEY_RESET   17
+#define MV2120_GPIO_KEY_POWER   18
+#define MV2120_GPIO_POWER_OFF   19
+
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+static struct mv643xx_eth_platform_data mv2120_eth_data = {
+        .phy_addr       = 8,
+};
+
+static struct mv_sata_platform_data mv2120_sata_data = {
+        .n_ports        = 2,
+};
+
+static struct mtd_partition mv2120_partitions[] = {
+        {
+                .name   = "firmware",
+                .size   = 0x00080000,
+                .offset = 0,
+        },
+};
+
+static struct physmap_flash_data mv2120_nor_flash_data = {
+        .width          = 1,
+        .parts          = mv2120_partitions,
+        .nr_parts       = ARRAY_SIZE(mv2120_partitions)
+};
+
+static struct resource mv2120_nor_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = MV2120_NOR_BOOT_BASE,
+        .end            = MV2120_NOR_BOOT_BASE + MV2120_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device mv2120_nor_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &mv2120_nor_flash_data,
+        },
+        .resource       = &mv2120_nor_flash_resource,
+        .num_resources  = 1,
+};
+
+static struct gpio_keys_button mv2120_buttons[] = {
+        {
+                .code           = KEY_RESTART,
+                .gpio           = MV2120_GPIO_KEY_RESET,
+                .desc           = "reset",
+                .active_low     = 1,
+        }, {
+                .code           = KEY_POWER,
+                .gpio           = MV2120_GPIO_KEY_POWER,
+                .desc           = "power",
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data mv2120_button_data = {
+        .buttons        = mv2120_buttons,
+        .nbuttons       = ARRAY_SIZE(mv2120_buttons),
+};
+
+static struct platform_device mv2120_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &mv2120_button_data,
+        },
+};
+
+
+/****************************************************************************
+ * General Setup
+ ****************************************************************************/
+static struct orion5x_mpp_mode mv2120_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* Sys status LED */
+        {  1, MPP_GPIO },               /* Sys error LED */
+        {  2, MPP_GPIO },               /* OverTemp interrupt */
+        {  3, MPP_GPIO },               /* RTC interrupt */
+        {  4, MPP_GPIO },               /* V_LED 5V */
+        {  5, MPP_GPIO },               /* V_LED 3.3V */
+        {  6, MPP_UNUSED },
+        {  7, MPP_UNUSED },
+        {  8, MPP_GPIO },               /* SATA 0 fail LED */
+        {  9, MPP_GPIO },               /* SATA 1 fail LED */
+        { 10, MPP_UNUSED },
+        { 11, MPP_UNUSED },
+        { 12, MPP_SATA_LED },           /* SATA 0 presence */
+        { 13, MPP_SATA_LED },           /* SATA 1 presence */
+        { 14, MPP_SATA_LED },           /* SATA 0 active */
+        { 15, MPP_SATA_LED },           /* SATA 1 active */
+        { 16, MPP_UNUSED },
+        { 17, MPP_GPIO },               /* Reset button */
+        { 18, MPP_GPIO },               /* Power button */
+        { 19, MPP_GPIO },               /* Power off */
+        { -1 },
+};
+
+static struct i2c_board_info __initdata mv2120_i2c_rtc = {
+        I2C_BOARD_INFO("pcf8563", 0x51),
+        .irq    = 0,
+};
+
+static struct gpio_led mv2120_led_pins[] = {
+        {
+                .name                   = "mv2120:blue:health",
+                .gpio                   = 0,
+        },
+        {
+                .name                   = "mv2120:red:health",
+                .gpio                   = 1,
+        },
+        {
+                .name                   = "mv2120:led:bright",
+                .gpio                   = 4,
+                .default_trigger        = "default-on",
+        },
+        {
+                .name                   = "mv2120:led:dimmed",
+                .gpio                   = 5,
+        },
+        {
+                .name                   = "mv2120:red:sata0",
+                .gpio                   = 8,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "mv2120:red:sata1",
+                .gpio                   = 9,
+                .active_low             = 1,
+        },
+
+};
+
+static struct gpio_led_platform_data mv2120_led_data = {
+        .leds           = mv2120_led_pins,
+        .num_leds       = ARRAY_SIZE(mv2120_led_pins),
+};
+
+static struct platform_device mv2120_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &mv2120_led_data,
+        }
+};
+
+static void mv2120_power_off(void)
+{
+        pr_info("%s: triggering power-off...\n", __func__);
+        gpio_set_value(MV2120_GPIO_POWER_OFF, 0);
+}
+
+static void __init mv2120_init(void)
+{
+        /* Setup basic Orion functions. Need to be called early. */
+        orion5x_init();
+
+        orion5x_mpp_conf(mv2120_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        orion5x_eth_init(&mv2120_eth_data);
+        orion5x_i2c_init();
+        orion5x_sata_init(&mv2120_sata_data);
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(MV2120_NOR_BOOT_BASE, MV2120_NOR_BOOT_SIZE);
+        platform_device_register(&mv2120_nor_flash);
+
+        platform_device_register(&mv2120_button_device);
+
+        if (gpio_request(MV2120_GPIO_RTC_IRQ, "rtc") == 0) {
+                if (gpio_direction_input(MV2120_GPIO_RTC_IRQ) == 0)
+                        mv2120_i2c_rtc.irq = gpio_to_irq(MV2120_GPIO_RTC_IRQ);
+                else
+                        gpio_free(MV2120_GPIO_RTC_IRQ);
+        }
+        i2c_register_board_info(0, &mv2120_i2c_rtc, 1);
+        platform_device_register(&mv2120_leds);
+
+        /* register mv2120 specific power-off method */
+        if (gpio_request(MV2120_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+            gpio_direction_output(MV2120_GPIO_POWER_OFF, 1) != 0)
+                pr_err("mv2120: failed to setup power-off GPIO\n");
+        pm_power_off = mv2120_power_off;
+}
+
+/* Warning: HP uses a wrong mach-type (=526) in their bootloader */
+MACHINE_START(MV2120, "HP Media Vault mv2120")
+        /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = mv2120_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 9d5d39fa19c3..256a4f680935 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -152,6 +152,8 @@ static int __init pcie_setup(struct pci_sys_data *sys)
         if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
                 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
                                    "read transaction workaround\n");
+                orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
+                                          ORION5X_PCIE_WA_SIZE);
                 pcie_ops.read = pcie_rd_conf_wa;
         }
 
@@ -240,13 +242,13 @@ static int __init pcie_setup(struct pci_sys_data *sys)
  * PCI Address Decode Windows registers
  */
 #define PCI_BAR_SIZE_DDR_CS(n)  (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
-                                ((n) == 1) ? ORION5X_PCI_REG(0xd08) :  \
-                                ((n) == 2) ? ORION5X_PCI_REG(0xc0c) :  \
-                                ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
-#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) :  \
-                                ((n) == 1) ? ORION5X_PCI_REG(0xd48) :  \
-                                ((n) == 2) ? ORION5X_PCI_REG(0xc4c) :  \
-                                ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
+                                 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
+                                 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
+                                 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
+#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
+                                 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
+                                 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
+                                 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
 #define PCI_BAR_ENABLE          ORION5X_PCI_REG(0xc3c)
 #define PCI_ADDR_DECODE_CTRL    ORION5X_PCI_REG(0xd3c)
 
@@ -264,9 +266,11 @@ static int __init pcie_setup(struct pci_sys_data *sys)
  */
 static DEFINE_SPINLOCK(orion5x_pci_lock);
 
+static int orion5x_pci_cardbus_mode;
+
 static int orion5x_pci_local_bus_nr(void)
 {
-        u32 conf = orion5x_read(PCI_P2P_CONF);
+        u32 conf = readl(PCI_P2P_CONF);
         return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
 }
 
@@ -276,11 +280,11 @@ static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
         unsigned long flags;
         spin_lock_irqsave(&orion5x_pci_lock, flags);
 
-        orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
-                        PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
-                        PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
+        writel(PCI_CONF_BUS(bus) |
+                PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
+                PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
 
-        *val = orion5x_read(PCI_CONF_DATA);
+        *val = readl(PCI_CONF_DATA);
 
         if (size == 1)
                 *val = (*val >> (8*(where & 0x3))) & 0xff;
@@ -300,9 +304,9 @@ static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
 
         spin_lock_irqsave(&orion5x_pci_lock, flags);
 
-        orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
-                        PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
-                        PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
+        writel(PCI_CONF_BUS(bus) |
+                PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
+                PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
 
         if (size == 4) {
                 __raw_writel(val, PCI_CONF_DATA);
@@ -319,14 +323,30 @@ static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
         return ret;
 }
 
+static int orion5x_pci_valid_config(int bus, u32 devfn)
+{
+        if (bus == orion5x_pci_local_bus_nr()) {
+                /*
+                 * Don't go out for local device
+                 */
+                if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
+                        return 0;
+
+                /*
+                 * When the PCI signals are directly connected to a
+                 * Cardbus slot, ignore all but device IDs 0 and 1.
+                 */
+                if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
+                        return 0;
+        }
+
+        return 1;
+}
+
 static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
                                 int where, int size, u32 *val)
 {
-        /*
-         * Don't go out for local device
-         */
-        if (bus->number == orion5x_pci_local_bus_nr() &&
-            PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) {
+        if (!orion5x_pci_valid_config(bus->number, devfn)) {
                 *val = 0xffffffff;
                 return PCIBIOS_DEVICE_NOT_FOUND;
         }
@@ -338,8 +358,7 @@ static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
 static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
                                 int where, int size, u32 val)
 {
-        if (bus->number == orion5x_pci_local_bus_nr() &&
-            PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
+        if (!orion5x_pci_valid_config(bus->number, devfn))
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
         return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
@@ -353,9 +372,9 @@ static struct pci_ops pci_ops = {
 
 static void __init orion5x_pci_set_bus_nr(int nr)
 {
-        u32 p2p = orion5x_read(PCI_P2P_CONF);
+        u32 p2p = readl(PCI_P2P_CONF);
 
-        if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) {
+        if (readl(PCI_MODE) & PCI_MODE_PCIX) {
                 /*
                  * PCI-X mode
                  */
@@ -372,7 +391,7 @@ static void __init orion5x_pci_set_bus_nr(int nr)
                  */
                 p2p &= ~PCI_P2P_BUS_MASK;
                 p2p |= (nr << PCI_P2P_BUS_OFFS);
-                orion5x_write(PCI_P2P_CONF, p2p);
+                writel(p2p, PCI_P2P_CONF);
         }
 }
 
@@ -399,7 +418,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
          * First, disable windows.
          */
         win_enable = 0xffffffff;
-        orion5x_write(PCI_BAR_ENABLE, win_enable);
+        writel(win_enable, PCI_BAR_ENABLE);
 
         /*
          * Setup windows for DDR banks.
@@ -425,10 +444,10 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
                  */
                 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
                 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
-                orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index),
-                                (cs->size - 1) & 0xfffff000);
-                orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index),
-                                cs->base & 0xfffff000);
+                writel((cs->size - 1) & 0xfffff000,
+                        PCI_BAR_SIZE_DDR_CS(cs->cs_index));
+                writel(cs->base & 0xfffff000,
+                        PCI_BAR_REMAP_DDR_CS(cs->cs_index));
 
                 /*
                  * Enable decode window for this chip select.
@@ -439,7 +458,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
         /*
          * Re-enable decode windows.
          */
-        orion5x_write(PCI_BAR_ENABLE, win_enable);
+        writel(win_enable, PCI_BAR_ENABLE);
 
         /*
          * Disable automatic update of address remaping when writing to BARs.
@@ -522,6 +541,11 @@ static void __devinit rc_pci_fixup(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
 
+void __init orion5x_pci_set_cardbus_mode(void)
+{
+        orion5x_pci_cardbus_mode = 1;
+}
+
 int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
 {
         int ret = 0;
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
new file mode 100644
index 000000000000..d50e3650a09e
--- /dev/null
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -0,0 +1,161 @@
+/*
+ * arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+ *
+ * Marvell Orion-VoIP FXO Reference Design Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+#include <asm/leds.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+/*****************************************************************************
+ * RD-88F5181L FXO Info
+ ****************************************************************************/
+/*
+ * 8M NOR flash Device bus boot chip select
+ */
+#define RD88F5181L_FXO_NOR_BOOT_BASE            0xff800000
+#define RD88F5181L_FXO_NOR_BOOT_SIZE            SZ_8M
+
+
+/*****************************************************************************
+ * 8M NOR Flash on Device bus Boot chip select
+ ****************************************************************************/
+static struct physmap_flash_data rd88f5181l_fxo_nor_boot_flash_data = {
+        .width          = 1,
+};
+
+static struct resource rd88f5181l_fxo_nor_boot_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = RD88F5181L_FXO_NOR_BOOT_BASE,
+        .end            = RD88F5181L_FXO_NOR_BOOT_BASE +
+                          RD88F5181L_FXO_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device rd88f5181l_fxo_nor_boot_flash = {
+        .name                   = "physmap-flash",
+        .id                     = 0,
+        .dev            = {
+                .platform_data  = &rd88f5181l_fxo_nor_boot_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &rd88f5181l_fxo_nor_boot_flash_resource,
+};
+
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* LED1 CardBus LED (front panel) */
+        {  1, MPP_GPIO },               /* PCI_intA */
+        {  2, MPP_GPIO },               /* Hard Reset / Factory Init*/
+        {  3, MPP_GPIO },               /* FXS or DAA select */
+        {  4, MPP_GPIO },               /* LED6 - phone LED (front panel) */
+        {  5, MPP_GPIO },               /* LED5 - phone LED (front panel) */
+        {  6, MPP_PCI_CLK },            /* CPU PCI refclk */
+        {  7, MPP_PCI_CLK },            /* PCI/PCIe refclk */
+        {  8, MPP_GPIO },               /* CardBus reset */
+        {  9, MPP_GPIO },               /* GE_RXERR */
+        { 10, MPP_GPIO },               /* LED2 MiniPCI LED (front panel) */
+        { 11, MPP_GPIO },               /* Lifeline control */
+        { 12, MPP_GIGE },               /* GE_TXD[4] */
+        { 13, MPP_GIGE },               /* GE_TXD[5] */
+        { 14, MPP_GIGE },               /* GE_TXD[6] */
+        { 15, MPP_GIGE },               /* GE_TXD[7] */
+        { 16, MPP_GIGE },               /* GE_RXD[4] */
+        { 17, MPP_GIGE },               /* GE_RXD[5] */
+        { 18, MPP_GIGE },               /* GE_RXD[6] */
+        { 19, MPP_GIGE },               /* GE_RXD[7] */
+        { -1 },
+};
+
+static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = {
+        .phy_addr       = -1,
+};
+
+static void __init rd88f5181l_fxo_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(rd88f5181l_fxo_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_eth_init(&rd88f5181l_fxo_eth_data);
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(RD88F5181L_FXO_NOR_BOOT_BASE,
+                                   RD88F5181L_FXO_NOR_BOOT_SIZE);
+        platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
+}
+
+static int __init
+rd88f5181l_fxo_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq;
+
+        /*
+         * Check for devices with hard-wired IRQs.
+         */
+        irq = orion5x_pci_map_irq(dev, slot, pin);
+        if (irq != -1)
+                return irq;
+
+        /*
+         * Mini-PCI / Cardbus slot.
+         */
+        return gpio_to_irq(1);
+}
+
+static struct hw_pci rd88f5181l_fxo_pci __initdata = {
+        .nr_controllers = 2,
+        .swizzle        = pci_std_swizzle,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = rd88f5181l_fxo_pci_map_irq,
+};
+
+static int __init rd88f5181l_fxo_pci_init(void)
+{
+        if (machine_is_rd88f5181l_fxo()) {
+                orion5x_pci_set_cardbus_mode();
+                pci_common_init(&rd88f5181l_fxo_pci);
+        }
+
+        return 0;
+}
+subsys_initcall(rd88f5181l_fxo_pci_init);
+
+MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
+        /* Maintainer: Nicolas Pitre <nico@marvell.com> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = rd88f5181l_fxo_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
new file mode 100644
index 000000000000..b56447d32e17
--- /dev/null
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -0,0 +1,172 @@
+/*
+ * arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+ *
+ * Marvell Orion-VoIP GE Reference Design Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/i2c.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+#include <asm/leds.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+/*****************************************************************************
+ * RD-88F5181L GE Info
+ ****************************************************************************/
+/*
+ * 16M NOR flash Device bus boot chip select
+ */
+#define RD88F5181L_GE_NOR_BOOT_BASE             0xff000000
+#define RD88F5181L_GE_NOR_BOOT_SIZE             SZ_16M
+
+
+/*****************************************************************************
+ * 16M NOR Flash on Device bus Boot chip select
+ ****************************************************************************/
+static struct physmap_flash_data rd88f5181l_ge_nor_boot_flash_data = {
+        .width          = 1,
+};
+
+static struct resource rd88f5181l_ge_nor_boot_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = RD88F5181L_GE_NOR_BOOT_BASE,
+        .end            = RD88F5181L_GE_NOR_BOOT_BASE +
+                          RD88F5181L_GE_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device rd88f5181l_ge_nor_boot_flash = {
+        .name                   = "physmap-flash",
+        .id                     = 0,
+        .dev            = {
+                .platform_data  = &rd88f5181l_ge_nor_boot_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &rd88f5181l_ge_nor_boot_flash_resource,
+};
+
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+static struct orion5x_mpp_mode rd88f5181l_ge_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* LED1 */
+        {  1, MPP_GPIO },               /* LED5 */
+        {  2, MPP_GPIO },               /* LED4 */
+        {  3, MPP_GPIO },               /* LED3 */
+        {  4, MPP_GPIO },               /* PCI_intA */
+        {  5, MPP_GPIO },               /* RTC interrupt */
+        {  6, MPP_PCI_CLK },            /* CPU PCI refclk */
+        {  7, MPP_PCI_CLK },            /* PCI/PCIe refclk */
+        {  8, MPP_GPIO },               /* 88e6131 interrupt */
+        {  9, MPP_GPIO },               /* GE_RXERR */
+        { 10, MPP_GPIO },               /* PCI_intB */
+        { 11, MPP_GPIO },               /* LED2 */
+        { 12, MPP_GIGE },               /* GE_TXD[4] */
+        { 13, MPP_GIGE },               /* GE_TXD[5] */
+        { 14, MPP_GIGE },               /* GE_TXD[6] */
+        { 15, MPP_GIGE },               /* GE_TXD[7] */
+        { 16, MPP_GIGE },               /* GE_RXD[4] */
+        { 17, MPP_GIGE },               /* GE_RXD[5] */
+        { 18, MPP_GIGE },               /* GE_RXD[6] */
+        { 19, MPP_GIGE },               /* GE_RXD[7] */
+        { -1 },
+};
+
+static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
+        .phy_addr       = -1,
+};
+
+static struct i2c_board_info __initdata rd88f5181l_ge_i2c_rtc = {
+        I2C_BOARD_INFO("ds1338", 0x68),
+};
+
+static void __init rd88f5181l_ge_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(rd88f5181l_ge_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_eth_init(&rd88f5181l_ge_eth_data);
+        orion5x_i2c_init();
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(RD88F5181L_GE_NOR_BOOT_BASE,
+                                   RD88F5181L_GE_NOR_BOOT_SIZE);
+        platform_device_register(&rd88f5181l_ge_nor_boot_flash);
+
+        i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
+}
+
+static int __init
+rd88f5181l_ge_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq;
+
+        /*
+         * Check for devices with hard-wired IRQs.
+         */
+        irq = orion5x_pci_map_irq(dev, slot, pin);
+        if (irq != -1)
+                return irq;
+
+        /*
+         * Cardbus slot.
+         */
+        if (pin == 1)
+                return gpio_to_irq(4);
+        else
+                return gpio_to_irq(10);
+}
+
+static struct hw_pci rd88f5181l_ge_pci __initdata = {
+        .nr_controllers = 2,
+        .swizzle        = pci_std_swizzle,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = rd88f5181l_ge_pci_map_irq,
+};
+
+static int __init rd88f5181l_ge_pci_init(void)
+{
+        if (machine_is_rd88f5181l_ge()) {
+                orion5x_pci_set_cardbus_mode();
+                pci_common_init(&rd88f5181l_ge_pci);
+        }
+
+        return 0;
+}
+subsys_initcall(rd88f5181l_ge_pci_init);
+
+MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
+        /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = rd88f5181l_ge_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 81abc1003aae..10ae62864269 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -26,6 +26,7 @@
 #include <asm/mach/pci.h>
 #include <asm/arch/orion5x.h>
 #include "common.h"
+#include "mpp.h"
 
 /*****************************************************************************
  * RD-88F5182 Info
@@ -125,6 +126,7 @@ static int __init rd88f5182_dbgled_init(void)
 
                 leds_event = rd88f5182_dbgled_event;
         }
+
         return 0;
 }
 
@@ -220,7 +222,6 @@ subsys_initcall(rd88f5182_pci_init);
 
 static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
         .phy_addr       = 8,
-        .force_phy_addr = 1,
 };
 
 /*****************************************************************************
@@ -234,15 +235,34 @@ static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
  * Sata
  ****************************************************************************/
 static struct mv_sata_platform_data rd88f5182_sata_data = {
-        .n_ports        = 2,
+        .n_ports        = 2,
 };
 
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-
-static struct platform_device *rd88f5182_devices[] __initdata = {
-        &rd88f5182_nor_flash,
+static struct orion5x_mpp_mode rd88f5182_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* Debug Led */
+        {  1, MPP_GPIO },               /* Reset Switch */
+        {  2, MPP_UNUSED },
+        {  3, MPP_GPIO },               /* RTC Int */
+        {  4, MPP_GPIO },
+        {  5, MPP_GPIO },
+        {  6, MPP_GPIO },               /* PCI_intA */
+        {  7, MPP_GPIO },               /* PCI_intB */
+        {  8, MPP_UNUSED },
+        {  9, MPP_UNUSED },
+        { 10, MPP_UNUSED },
+        { 11, MPP_UNUSED },
+        { 12, MPP_SATA_LED },           /* SATA 0 presence */
+        { 13, MPP_SATA_LED },           /* SATA 1 presence */
+        { 14, MPP_SATA_LED },           /* SATA 0 active */
+        { 15, MPP_SATA_LED },           /* SATA 1 active */
+        { 16, MPP_UNUSED },
+        { 17, MPP_UNUSED },
+        { 18, MPP_UNUSED },
+        { 19, MPP_UNUSED },
+        { -1 },
 };
 
 static void __init rd88f5182_init(void)
@@ -252,35 +272,9 @@ static void __init rd88f5182_init(void)
          */
         orion5x_init();
 
-        /*
-         * Setup the CPU address decode windows for our devices
-         */
-        orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
-                                RD88F5182_NOR_BOOT_SIZE);
-        orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
-
-        /*
-         * Open a special address decode windows for the PCIe WA.
-         */
-        orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
-                                ORION5X_PCIE_WA_SIZE);
+        orion5x_mpp_conf(rd88f5182_mpp_modes);
 
         /*
-         * Setup Multiplexing Pins --
-         * MPP[0] Debug Led (GPIO - Out)
-         * MPP[1] Debug Led (GPIO - Out)
-         * MPP[2] N/A
-         * MPP[3] RTC_Int (GPIO - In)
-         * MPP[4] GPIO
-         * MPP[5] GPIO
-         * MPP[6] PCI_intA (GPIO - In)
-         * MPP[7] PCI_intB (GPIO - In)
-         * MPP[8-11] N/A
-         * MPP[12] SATA 0 presence Indication
-         * MPP[13] SATA 1 presence Indication
-         * MPP[14] SATA 0 active Indication
-         * MPP[15] SATA 1 active indication
-         * MPP[16-19] Not used
          * MPP[20] PCI Clock to MV88F5182
          * MPP[21] PCI Clock to mini PCI CON11
          * MPP[22] USB 0 over current indication
@@ -289,16 +283,23 @@ static void __init rd88f5182_init(void)
          * MPP[25] USB 0 over current enable
          */
 
-        orion5x_write(MPP_0_7_CTRL, 0x00000003);
-        orion5x_write(MPP_8_15_CTRL, 0x55550000);
-        orion5x_write(MPP_16_19_CTRL, 0x5555);
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        orion5x_eth_init(&rd88f5182_eth_data);
+        orion5x_i2c_init();
+        orion5x_sata_init(&rd88f5182_sata_data);
+        orion5x_uart0_init();
 
-        orion5x_gpio_set_valid_pins(0x000000fb);
+        orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
+                                   RD88F5182_NOR_BOOT_SIZE);
+
+        orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
+        platform_device_register(&rd88f5182_nor_flash);
 
-        platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
         i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
-        orion5x_eth_init(&rd88f5182_eth_data);
-        orion5x_sata_init(&rd88f5182_sata_data);
 }
 
 MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 9afb41ee6e07..a9cef9703d5b 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -28,6 +28,8 @@
 #include <asm/mach/pci.h>
 #include <asm/arch/orion5x.h>
 #include "common.h"
+#include "mpp.h"
+#include "tsx09-common.h"
 
 #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000
 #define QNAP_TS209_NOR_BOOT_SIZE SZ_8M
@@ -47,52 +49,54 @@
  ***************************************************************************/
 static struct mtd_partition qnap_ts209_partitions[] = {
         {
-                .name       = "U-Boot",
-                .size       = 0x00080000,
-                .offset     = 0x00780000,
-                .mask_flags = MTD_WRITEABLE,
+                .name           = "U-Boot",
+                .size           = 0x00080000,
+                .offset         = 0x00780000,
+                .mask_flags     = MTD_WRITEABLE,
         }, {
-                .name   = "Kernel",
-                .size   = 0x00200000,
-                .offset = 0,
+                .name           = "Kernel",
+                .size           = 0x00200000,
+                .offset         = 0,
         }, {
-                .name   = "RootFS1",
-                .size   = 0x00400000,
-                .offset = 0x00200000,
+                .name           = "RootFS1",
+                .size           = 0x00400000,
+                .offset         = 0x00200000,
         }, {
-                .name   = "RootFS2",
-                .size   = 0x00100000,
-                .offset = 0x00600000,
+                .name           = "RootFS2",
+                .size           = 0x00100000,
+                .offset         = 0x00600000,
         }, {
-                .name   = "U-Boot Config",
-                .size   = 0x00020000,
-                .offset = 0x00760000,
+                .name           = "U-Boot Config",
+                .size           = 0x00020000,
+                .offset         = 0x00760000,
         }, {
-                .name       = "NAS Config",
-                .size       = 0x00060000,
-                .offset     = 0x00700000,
-                .mask_flags = MTD_WRITEABLE,
-        }
+                .name           = "NAS Config",
+                .size           = 0x00060000,
+                .offset         = 0x00700000,
+                .mask_flags     = MTD_WRITEABLE,
+        },
 };
 
 static struct physmap_flash_data qnap_ts209_nor_flash_data = {
-        .width    = 1,
-        .parts    = qnap_ts209_partitions,
-        .nr_parts = ARRAY_SIZE(qnap_ts209_partitions)
+        .width          = 1,
+        .parts          = qnap_ts209_partitions,
+        .nr_parts       = ARRAY_SIZE(qnap_ts209_partitions)
 };
 
 static struct resource qnap_ts209_nor_flash_resource = {
-        .flags = IORESOURCE_MEM,
-        .start = QNAP_TS209_NOR_BOOT_BASE,
-        .end   = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1,
+        .flags  = IORESOURCE_MEM,
+        .start  = QNAP_TS209_NOR_BOOT_BASE,
+        .end    = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1,
 };
 
 static struct platform_device qnap_ts209_nor_flash = {
-        .name          = "physmap-flash",
-        .id            = 0,
-        .dev           = { .platform_data = &qnap_ts209_nor_flash_data, },
-        .resource      = &qnap_ts209_nor_flash_resource,
-        .num_resources = 1,
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &qnap_ts209_nor_flash_data,
+        },
+        .resource       = &qnap_ts209_nor_flash_resource,
+        .num_resources  = 1,
 };
 
 /*****************************************************************************
@@ -164,12 +168,12 @@ static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 }
 
 static struct hw_pci qnap_ts209_pci __initdata = {
-        .nr_controllers = 2,
-        .preinit        = qnap_ts209_pci_preinit,
-        .swizzle        = pci_std_swizzle,
-        .setup          = orion5x_pci_sys_setup,
-        .scan           = orion5x_pci_sys_scan_bus,
-        .map_irq        = qnap_ts209_pci_map_irq,
+        .nr_controllers = 2,
+        .preinit        = qnap_ts209_pci_preinit,
+        .swizzle        = pci_std_swizzle,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = qnap_ts209_pci_map_irq,
 };
 
 static int __init qnap_ts209_pci_init(void)
@@ -183,96 +187,6 @@ static int __init qnap_ts209_pci_init(void)
 subsys_initcall(qnap_ts209_pci_init);
 
 /*****************************************************************************
- * Ethernet
- ****************************************************************************/
-
-static struct mv643xx_eth_platform_data qnap_ts209_eth_data = {
-        .phy_addr       = 8,
-        .force_phy_addr = 1,
-};
-
-static int __init parse_hex_nibble(char n)
-{
-        if (n >= '0' && n <= '9')
-                return n - '0';
-
-        if (n >= 'A' && n <= 'F')
-                return n - 'A' + 10;
-
-        if (n >= 'a' && n <= 'f')
-                return n - 'a' + 10;
-
-        return -1;
-}
-
-static int __init parse_hex_byte(const char *b)
-{
-        int hi;
-        int lo;
-
-        hi = parse_hex_nibble(b[0]);
-        lo = parse_hex_nibble(b[1]);
-
-        if (hi < 0 || lo < 0)
-                return -1;
-
-        return (hi << 4) | lo;
-}
-
-static int __init check_mac_addr(const char *addr_str)
-{
-        u_int8_t addr[6];
-        int i;
-
-        for (i = 0; i < 6; i++) {
-                int byte;
-
-                /*
-                 * Enforce "xx:xx:xx:xx:xx:xx\n" format.
-                 */
-                if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n'))
-                        return -1;
-
-                byte = parse_hex_byte(addr_str + (i * 3));
-                if (byte < 0)
-                        return -1;
-                addr[i] = byte;
-        }
-
-        printk(KERN_INFO "ts209: found ethernet mac address ");
-        for (i = 0; i < 6; i++)
-                printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
-
-        memcpy(qnap_ts209_eth_data.mac_addr, addr, 6);
-
-        return 0;
-}
-
-/*
- * The 'NAS Config' flash partition has an ext2 filesystem which
- * contains a file that has the ethernet MAC address in plain text
- * (format "xx:xx:xx:xx:xx:xx\n".)
- */
-static void __init ts209_find_mac_addr(void)
-{
-        unsigned long addr;
-
-        for (addr = 0x00700000; addr < 0x00760000; addr += 1024) {
-                char *nor_page;
-                int ret = 0;
-
-                nor_page = ioremap(QNAP_TS209_NOR_BOOT_BASE + addr, 1024);
-                if (nor_page != NULL) {
-                        ret = check_mac_addr(nor_page);
-                        iounmap(nor_page);
-                }
-
-                if (ret == 0)
-                        break;
-        }
-}
-
-/*****************************************************************************
  * RTC S35390A on I2C bus
  ****************************************************************************/
 
@@ -280,7 +194,7 @@ static void __init ts209_find_mac_addr(void)
 
 static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = {
         I2C_BOARD_INFO("s35390a", 0x30),
-       .irq         = 0,
+        .irq    = 0,
 };
 
 /****************************************************************************
@@ -297,70 +211,63 @@ static struct gpio_keys_button qnap_ts209_buttons[] = {
                 .gpio           = QNAP_TS209_GPIO_KEY_MEDIA,
                 .desc           = "USB Copy Button",
                 .active_low     = 1,
-        },
-        {
+        }, {
                 .code           = KEY_POWER,
                 .gpio           = QNAP_TS209_GPIO_KEY_RESET,
                 .desc           = "Reset Button",
                 .active_low     = 1,
-        }
+        },
 };
 
 static struct gpio_keys_platform_data qnap_ts209_button_data = {
         .buttons        = qnap_ts209_buttons,
-        .nbuttons       = ARRAY_SIZE(qnap_ts209_buttons),
+        .nbuttons       = ARRAY_SIZE(qnap_ts209_buttons),
 };
 
 static struct platform_device qnap_ts209_button_device = {
         .name           = "gpio-keys",
         .id             = -1,
         .num_resources  = 0,
-        .dev            = { .platform_data  = &qnap_ts209_button_data, },
+        .dev            = {
+                .platform_data  = &qnap_ts209_button_data,
+        },
 };
 
 /*****************************************************************************
  * SATA
  ****************************************************************************/
 static struct mv_sata_platform_data qnap_ts209_sata_data = {
-        .n_ports        = 2,
+        .n_ports        = 2,
 };
 
 /*****************************************************************************
 
  * General Setup
  ****************************************************************************/
-
-static struct platform_device *qnap_ts209_devices[] __initdata = {
-        &qnap_ts209_nor_flash,
-        &qnap_ts209_button_device,
+static struct orion5x_mpp_mode ts209_mpp_modes[] __initdata = {
+        {  0, MPP_UNUSED },
+        {  1, MPP_GPIO },               /* USB copy button */
+        {  2, MPP_GPIO },               /* Load defaults button */
+        {  3, MPP_GPIO },               /* GPIO RTC */
+        {  4, MPP_UNUSED },
+        {  5, MPP_UNUSED },
+        {  6, MPP_GPIO },               /* PCI Int A */
+        {  7, MPP_GPIO },               /* PCI Int B */
+        {  8, MPP_UNUSED },
+        {  9, MPP_UNUSED },
+        { 10, MPP_UNUSED },
+        { 11, MPP_UNUSED },
+        { 12, MPP_SATA_LED },           /* SATA 0 presence */
+        { 13, MPP_SATA_LED },           /* SATA 1 presence */
+        { 14, MPP_SATA_LED },           /* SATA 0 active */
+        { 15, MPP_SATA_LED },           /* SATA 1 active */
+        { 16, MPP_UART },               /* UART1 RXD */
+        { 17, MPP_UART },               /* UART1 TXD */
+        { 18, MPP_GPIO },               /* SW_RST */
+        { 19, MPP_UNUSED },
+        { -1 },
 };
 
-/*
- * QNAP TS-[12]09 specific power off method via UART1-attached PIC
- */
-
-#define UART1_REG(x)  (UART1_VIRT_BASE + ((UART_##x) << 2))
-
-static void qnap_ts209_power_off(void)
-{
-        /* 19200 baud divisor */
-        const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200));
-
-        pr_info("%s: triggering power-off...\n", __func__);
-
-        /* hijack uart1 and reset into sane state (19200,8n1) */
-        orion5x_write(UART1_REG(LCR), 0x83);
-        orion5x_write(UART1_REG(DLL), divisor & 0xff);
-        orion5x_write(UART1_REG(DLM), (divisor >> 8) & 0xff);
-        orion5x_write(UART1_REG(LCR), 0x03);
-        orion5x_write(UART1_REG(IER), 0x00);
-        orion5x_write(UART1_REG(FCR), 0x00);
-        orion5x_write(UART1_REG(MCR), 0x00);
-
-        /* send the power-off command 'A' to PIC */
-        orion5x_write(UART1_REG(TX), 'A');
-}
-
 static void __init qnap_ts209_init(void)
 {
         /*
@@ -368,51 +275,33 @@ static void __init qnap_ts209_init(void)
          */
         orion5x_init();
 
-        /*
-         * Setup flash mapping
-         */
-        orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
-                            QNAP_TS209_NOR_BOOT_SIZE);
-
-        /*
-         * Open a special address decode windows for the PCIe WA.
-         */
-        orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
-                                ORION5X_PCIE_WA_SIZE);
+        orion5x_mpp_conf(ts209_mpp_modes);
 
         /*
-         * Setup Multiplexing Pins --
-         * MPP[0] Reserved
-         * MPP[1] USB copy button (0 active)
-         * MPP[2] Load defaults button (0 active)
-         * MPP[3] GPIO RTC
-         * MPP[4-5] Reserved
-         * MPP[6] PCI Int A
-         * MPP[7] PCI Int B
-         * MPP[8-11] Reserved
-         * MPP[12] SATA 0 presence
-         * MPP[13] SATA 1 presence
-         * MPP[14] SATA 0 active
-         * MPP[15] SATA 1 active
-         * MPP[16] UART1 RXD
-         * MPP[17] UART1 TXD
-         * MPP[18] SW_RST (0 active)
-         * MPP[19] Reserved
          * MPP[20] PCI clock 0
          * MPP[21] PCI clock 1
          * MPP[22] USB 0 over current
          * MPP[23-25] Reserved
          */
-        orion5x_write(MPP_0_7_CTRL, 0x3);
-        orion5x_write(MPP_8_15_CTRL, 0x55550000);
-        orion5x_write(MPP_16_19_CTRL, 0x5500);
-        orion5x_gpio_set_valid_pins(0x3cc0fff);
 
-        /* register ts209 specific power-off method */
-        pm_power_off = qnap_ts209_power_off;
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        qnap_tsx09_find_mac_addr(QNAP_TS209_NOR_BOOT_BASE +
+                                 qnap_ts209_partitions[5].offset,
+                                 qnap_ts209_partitions[5].size);
+        orion5x_eth_init(&qnap_tsx09_eth_data);
+        orion5x_i2c_init();
+        orion5x_sata_init(&qnap_ts209_sata_data);
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
+                                   QNAP_TS209_NOR_BOOT_SIZE);
+        platform_device_register(&qnap_ts209_nor_flash);
 
-        platform_add_devices(qnap_ts209_devices,
-                                ARRAY_SIZE(qnap_ts209_devices));
+        platform_device_register(&qnap_ts209_button_device);
 
         /* Get RTC IRQ and register the chip */
         if (gpio_request(TS209_RTC_GPIO, "rtc") == 0) {
@@ -425,14 +314,12 @@ static void __init qnap_ts209_init(void)
                 pr_warning("qnap_ts209_init: failed to get RTC IRQ\n");
         i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
 
-        ts209_find_mac_addr();
-        orion5x_eth_init(&qnap_ts209_eth_data);
-
-        orion5x_sata_init(&qnap_ts209_sata_data);
+        /* register tsx09 specific power-off method */
+        pm_power_off = qnap_tsx09_power_off;
 }
 
 MACHINE_START(TS209, "QNAP TS-109/TS-209")
-        /* Maintainer:  Byron Bradley <byron.bbradley@gmail.com> */
+        /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
         .phys_io        = ORION5X_REGS_PHYS_BASE,
         .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
new file mode 100644
index 000000000000..32f0ff073b7e
--- /dev/null
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -0,0 +1,273 @@
+/*
+ * QNAP TS-409 Board Setup
+ *
+ * Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/serial_reg.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+#include "tsx09-common.h"
+
+/*****************************************************************************
+ * QNAP TS-409 Info
+ ****************************************************************************/
+
+/*
+ * QNAP TS-409 hardware :
+ * - Marvell 88F5281-D0
+ * - Marvell 88SX7042 SATA controller (PCIe)
+ * - Marvell 88E1118 Gigabit Ethernet PHY
+ * - RTC S35390A (@0x30) on I2C bus
+ * - 8MB NOR flash
+ * - 256MB of DDR-2 RAM
+ */
+
+/*
+ * 8MB NOR flash Device bus boot chip select
+ */
+
+#define QNAP_TS409_NOR_BOOT_BASE 0xff800000
+#define QNAP_TS409_NOR_BOOT_SIZE SZ_8M
+
+/****************************************************************************
+ * 8MiB NOR flash. The struct mtd_partition is not in the same order as the
+ *     partitions on the device because we want to keep compatability with
+ *     existing QNAP firmware.
+ *
+ * Layout as used by QNAP:
+ *  [2] 0x00000000-0x00200000 : "Kernel"
+ *  [3] 0x00200000-0x00600000 : "RootFS1"
+ *  [4] 0x00600000-0x00700000 : "RootFS2"
+ *  [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
+ *  [5] 0x00760000-0x00780000 : "U-Boot Config"
+ *  [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
+ ***************************************************************************/
+static struct mtd_partition qnap_ts409_partitions[] = {
+        {
+                .name           = "U-Boot",
+                .size           = 0x00080000,
+                .offset         = 0x00780000,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "Kernel",
+                .size           = 0x00200000,
+                .offset         = 0,
+        }, {
+                .name           = "RootFS1",
+                .size           = 0x00400000,
+                .offset         = 0x00200000,
+        }, {
+                .name           = "RootFS2",
+                .size           = 0x00100000,
+                .offset         = 0x00600000,
+        }, {
+                .name           = "U-Boot Config",
+                .size           = 0x00020000,
+                .offset         = 0x00760000,
+        }, {
+                .name           = "NAS Config",
+                .size           = 0x00060000,
+                .offset         = 0x00700000,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+};
+
+static struct physmap_flash_data qnap_ts409_nor_flash_data = {
+        .width          = 1,
+        .parts          = qnap_ts409_partitions,
+        .nr_parts       = ARRAY_SIZE(qnap_ts409_partitions)
+};
+
+static struct resource qnap_ts409_nor_flash_resource = {
+        .flags  = IORESOURCE_MEM,
+        .start  = QNAP_TS409_NOR_BOOT_BASE,
+        .end    = QNAP_TS409_NOR_BOOT_BASE + QNAP_TS409_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device qnap_ts409_nor_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = { .platform_data = &qnap_ts409_nor_flash_data, },
+        .num_resources  = 1,
+        .resource       = &qnap_ts409_nor_flash_resource,
+};
+
+/*****************************************************************************
+ * PCI
+ ****************************************************************************/
+
+static int __init qnap_ts409_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq;
+
+        /*
+         * Check for devices with hard-wired IRQs.
+         */
+        irq = orion5x_pci_map_irq(dev, slot, pin);
+        if (irq != -1)
+                return irq;
+
+        /*
+         * PCI isn't used on the TS-409
+         */
+        return -1;
+}
+
+static struct hw_pci qnap_ts409_pci __initdata = {
+        .nr_controllers = 2,
+        .swizzle        = pci_std_swizzle,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = qnap_ts409_pci_map_irq,
+};
+
+static int __init qnap_ts409_pci_init(void)
+{
+        if (machine_is_ts409())
+                pci_common_init(&qnap_ts409_pci);
+
+        return 0;
+}
+
+subsys_initcall(qnap_ts409_pci_init);
+
+/*****************************************************************************
+ * RTC S35390A on I2C bus
+ ****************************************************************************/
+
+#define TS409_RTC_GPIO  10
+
+static struct i2c_board_info __initdata qnap_ts409_i2c_rtc = {
+        I2C_BOARD_INFO("s35390a", 0x30),
+};
+
+/****************************************************************************
+ * GPIO Attached Keys
+ *     Power button is attached to the PIC microcontroller
+ ****************************************************************************/
+
+#define QNAP_TS409_GPIO_KEY_MEDIA       15
+
+static struct gpio_keys_button qnap_ts409_buttons[] = {
+        {
+                .code           = KEY_RESTART,
+                .gpio           = QNAP_TS409_GPIO_KEY_MEDIA,
+                .desc           = "USB Copy Button",
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data qnap_ts409_button_data = {
+        .buttons        = qnap_ts409_buttons,
+        .nbuttons       = ARRAY_SIZE(qnap_ts409_buttons),
+};
+
+static struct platform_device qnap_ts409_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &qnap_ts409_button_data,
+        },
+};
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+static struct orion5x_mpp_mode ts409_mpp_modes[] __initdata = {
+        {  0, MPP_UNUSED },
+        {  1, MPP_UNUSED },
+        {  2, MPP_UNUSED },
+        {  3, MPP_UNUSED },
+        {  4, MPP_GPIO },               /* HDD 1 status */
+        {  5, MPP_GPIO },               /* HDD 2 status */
+        {  6, MPP_GPIO },               /* HDD 3 status */
+        {  7, MPP_GPIO },               /* HDD 4 status */
+        {  8, MPP_UNUSED },
+        {  9, MPP_UNUSED },
+        { 10, MPP_GPIO },               /* RTC int */
+        { 11, MPP_UNUSED },
+        { 12, MPP_UNUSED },
+        { 13, MPP_UNUSED },
+        { 14, MPP_GPIO },               /* SW_RST */
+        { 15, MPP_GPIO },               /* USB copy button */
+        { 16, MPP_UART },               /* UART1 RXD */
+        { 17, MPP_UART },               /* UART1 TXD */
+        { 18, MPP_UNUSED },
+        { 19, MPP_UNUSED },
+        { -1 },
+};
+
+static void __init qnap_ts409_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(ts409_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        qnap_tsx09_find_mac_addr(QNAP_TS409_NOR_BOOT_BASE +
+                                 qnap_ts409_partitions[5].offset,
+                                 qnap_ts409_partitions[5].size);
+        orion5x_eth_init(&qnap_tsx09_eth_data);
+        orion5x_i2c_init();
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE,
+                                   QNAP_TS409_NOR_BOOT_SIZE);
+        platform_device_register(&qnap_ts409_nor_flash);
+
+        platform_device_register(&qnap_ts409_button_device);
+
+        /* Get RTC IRQ and register the chip */
+        if (gpio_request(TS409_RTC_GPIO, "rtc") == 0) {
+                if (gpio_direction_input(TS409_RTC_GPIO) == 0)
+                        qnap_ts409_i2c_rtc.irq = gpio_to_irq(TS409_RTC_GPIO);
+                else
+                        gpio_free(TS409_RTC_GPIO);
+        }
+        if (qnap_ts409_i2c_rtc.irq == 0)
+                pr_warning("qnap_ts409_init: failed to get RTC IRQ\n");
+        i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1);
+
+        /* register tsx09 specific power-off method */
+        pm_power_off = qnap_tsx09_power_off;
+}
+
+MACHINE_START(TS409, "QNAP TS-409")
+        /* Maintainer:  Sylver Bruneau <sylver.bruneau@gmail.com> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = qnap_ts409_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
new file mode 100644
index 000000000000..77e9f351f07a
--- /dev/null
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -0,0 +1,277 @@
+/*
+ * arch/arm/mach-orion5x/ts78xx-setup.c
+ *
+ * Maintainer: Alexander Clouter <alex@digriz.org.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ata_platform.h>
+#include <linux/m48t86.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/arch/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+/*****************************************************************************
+ * TS-78xx Info
+ ****************************************************************************/
+
+/*
+ * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
+ */
+#define TS78XX_FPGA_REGS_PHYS_BASE      0xe8000000
+#define TS78XX_FPGA_REGS_VIRT_BASE      0xff900000
+#define TS78XX_FPGA_REGS_SIZE           SZ_1M
+
+#define TS78XX_FPGA_REGS_SYSCON_ID      (TS78XX_FPGA_REGS_VIRT_BASE | 0x000)
+#define TS78XX_FPGA_REGS_SYSCON_LCDI    (TS78XX_FPGA_REGS_VIRT_BASE | 0x004)
+#define TS78XX_FPGA_REGS_SYSCON_LCDO    (TS78XX_FPGA_REGS_VIRT_BASE | 0x008)
+
+#define TS78XX_FPGA_REGS_RTC_CTRL       (TS78XX_FPGA_REGS_VIRT_BASE | 0x808)
+#define TS78XX_FPGA_REGS_RTC_DATA       (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c)
+
+/*
+ * 512kB NOR flash Device
+ */
+#define TS78XX_NOR_BOOT_BASE            0xff800000
+#define TS78XX_NOR_BOOT_SIZE            SZ_512K
+
+/*****************************************************************************
+ * I/O Address Mapping
+ ****************************************************************************/
+static struct map_desc ts78xx_io_desc[] __initdata = {
+        {
+                .virtual        = TS78XX_FPGA_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
+                .length         = TS78XX_FPGA_REGS_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+void __init ts78xx_map_io(void)
+{
+        orion5x_map_io();
+        iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
+}
+
+/*****************************************************************************
+ * 512kB NOR Boot Flash - the chip is a M25P40
+ ****************************************************************************/
+static struct mtd_partition ts78xx_nor_boot_flash_resources[] = {
+        {
+                .name           = "ts-bootrom",
+                .offset         = 0,
+                /* only the first 256kB is used */
+                .size           = SZ_256K,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+};
+
+static struct physmap_flash_data ts78xx_nor_boot_flash_data = {
+        .width          = 1,
+        .parts          = ts78xx_nor_boot_flash_resources,
+        .nr_parts       = ARRAY_SIZE(ts78xx_nor_boot_flash_resources),
+};
+
+static struct resource ts78xx_nor_boot_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = TS78XX_NOR_BOOT_BASE,
+        .end            = TS78XX_NOR_BOOT_BASE + TS78XX_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device ts78xx_nor_boot_flash = {
+        .name           = "physmap-flash",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &ts78xx_nor_boot_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &ts78xx_nor_boot_flash_resource,
+};
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+static struct mv643xx_eth_platform_data ts78xx_eth_data = {
+        .phy_addr       = 0,
+        .force_phy_addr = 1,
+};
+
+/*****************************************************************************
+ * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
+ ****************************************************************************/
+#ifdef CONFIG_RTC_DRV_M48T86
+static unsigned char ts78xx_rtc_readbyte(unsigned long addr)
+{
+        writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL);
+        return readb(TS78XX_FPGA_REGS_RTC_DATA);
+}
+
+static void ts78xx_rtc_writebyte(unsigned char value, unsigned long addr)
+{
+        writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL);
+        writeb(value, TS78XX_FPGA_REGS_RTC_DATA);
+}
+
+static struct m48t86_ops ts78xx_rtc_ops = {
+        .readbyte       = ts78xx_rtc_readbyte,
+        .writebyte      = ts78xx_rtc_writebyte,
+};
+
+static struct platform_device ts78xx_rtc_device = {
+        .name           = "rtc-m48t86",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &ts78xx_rtc_ops,
+        },
+        .num_resources  = 0,
+};
+
+/*
+ * TS uses some of the user storage space on the RTC chip so see if it is
+ * present; as it's an optional feature at purchase time and not all boards
+ * will have it present
+ *
+ * I've used the method TS use in their rtc7800.c example for the detection
+ *
+ * TODO: track down a guinea pig without an RTC to see if we can work out a
+ *              better RTC detection routine
+ */
+static int __init ts78xx_rtc_init(void)
+{
+        unsigned char tmp_rtc0, tmp_rtc1;
+
+        tmp_rtc0 = ts78xx_rtc_readbyte(126);
+        tmp_rtc1 = ts78xx_rtc_readbyte(127);
+
+        ts78xx_rtc_writebyte(0x00, 126);
+        ts78xx_rtc_writebyte(0x55, 127);
+        if (ts78xx_rtc_readbyte(127) == 0x55) {
+                ts78xx_rtc_writebyte(0xaa, 127);
+                if (ts78xx_rtc_readbyte(127) == 0xaa
+                                && ts78xx_rtc_readbyte(126) == 0x00) {
+                        ts78xx_rtc_writebyte(tmp_rtc0, 126);
+                        ts78xx_rtc_writebyte(tmp_rtc1, 127);
+                        platform_device_register(&ts78xx_rtc_device);
+                        return 1;
+                }
+        }
+
+        return 0;
+};
+#else
+static int __init ts78xx_rtc_init(void)
+{
+        return 0;
+}
+#endif
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct mv_sata_platform_data ts78xx_sata_data = {
+        .n_ports        = 2,
+};
+
+/*****************************************************************************
+ * print some information regarding the board
+ ****************************************************************************/
+static void __init ts78xx_print_board_id(void)
+{
+        unsigned int board_info;
+
+        board_info = readl(TS78XX_FPGA_REGS_SYSCON_ID);
+        printk(KERN_INFO "TS-78xx Info: FPGA rev=%.2x, Board Magic=%.6x, ",
+                                board_info & 0xff,
+                                (board_info >> 8) & 0xffffff);
+        board_info = readl(TS78XX_FPGA_REGS_SYSCON_LCDI);
+        printk("JP1=%d, JP2=%d\n",
+                                (board_info >> 30) & 0x1,
+                                (board_info >> 31) & 0x1);
+};
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = {
+        {  0, MPP_UNUSED },
+        {  1, MPP_GPIO },               /* JTAG Clock */
+        {  2, MPP_GPIO },               /* JTAG Data In */
+        {  3, MPP_GPIO },               /* Lat ECP2 256 FPGA - PB2B */
+        {  4, MPP_GPIO },               /* JTAG Data Out */
+        {  5, MPP_GPIO },               /* JTAG TMS */
+        {  6, MPP_GPIO },               /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
+        {  7, MPP_GPIO },               /* Lat ECP2 256 FPGA - PB22B */
+        {  8, MPP_UNUSED },
+        {  9, MPP_UNUSED },
+        { 10, MPP_UNUSED },
+        { 11, MPP_UNUSED },
+        { 12, MPP_UNUSED },
+        { 13, MPP_UNUSED },
+        { 14, MPP_UNUSED },
+        { 15, MPP_UNUSED },
+        { 16, MPP_UART },
+        { 17, MPP_UART },
+        { 18, MPP_UART },
+        { 19, MPP_UART },
+        { -1 },
+};
+
+static void __init ts78xx_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        ts78xx_print_board_id();
+
+        orion5x_mpp_conf(ts78xx_mpp_modes);
+
+        /*
+         * MPP[20] PCI Clock Out 1
+         * MPP[21] PCI Clock Out 0
+         * MPP[22] Unused
+         * MPP[23] Unused
+         * MPP[24] Unused
+         * MPP[25] Unused
+         */
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        orion5x_eth_init(&ts78xx_eth_data);
+        orion5x_sata_init(&ts78xx_sata_data);
+        orion5x_uart0_init();
+        orion5x_uart1_init();
+
+        orion5x_setup_dev_boot_win(TS78XX_NOR_BOOT_BASE,
+                                   TS78XX_NOR_BOOT_SIZE);
+        platform_device_register(&ts78xx_nor_boot_flash);
+
+        if (!ts78xx_rtc_init())
+                printk(KERN_INFO "TS-78xx RTC not detected or enabled\n");
+}
+
+MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
+        /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = ts78xx_init,
+        .map_io         = ts78xx_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/tsx09-common.c b/arch/arm/mach-orion5x/tsx09-common.c
new file mode 100644
index 000000000000..83feac3147a6
--- /dev/null
+++ b/arch/arm/mach-orion5x/tsx09-common.c
@@ -0,0 +1,133 @@
+/*
+ * QNAP TS-x09 Boards common functions
+ *
+ * Maintainers: Lennert Buytenhek <buytenh@marvell.com>
+ *              Byron Bradley <byron.bbradley@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/timex.h>
+#include <linux/serial_reg.h>
+#include "tsx09-common.h"
+
+/*****************************************************************************
+ * QNAP TS-x09 specific power off method via UART1-attached PIC
+ ****************************************************************************/
+
+#define UART1_REG(x)    (UART1_VIRT_BASE + ((UART_##x) << 2))
+
+void qnap_tsx09_power_off(void)
+{
+        /* 19200 baud divisor */
+        const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200));
+
+        pr_info("%s: triggering power-off...\n", __func__);
+
+        /* hijack uart1 and reset into sane state (19200,8n1) */
+        writel(0x83, UART1_REG(LCR));
+        writel(divisor & 0xff, UART1_REG(DLL));
+        writel((divisor >> 8) & 0xff, UART1_REG(DLM));
+        writel(0x03, UART1_REG(LCR));
+        writel(0x00, UART1_REG(IER));
+        writel(0x00, UART1_REG(FCR));
+        writel(0x00, UART1_REG(MCR));
+
+        /* send the power-off command 'A' to PIC */
+        writel('A', UART1_REG(TX));
+}
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+struct mv643xx_eth_platform_data qnap_tsx09_eth_data = {
+        .phy_addr       = 8,
+};
+
+static int __init qnap_tsx09_parse_hex_nibble(char n)
+{
+        if (n >= '0' && n <= '9')
+                return n - '0';
+
+        if (n >= 'A' && n <= 'F')
+                return n - 'A' + 10;
+
+        if (n >= 'a' && n <= 'f')
+                return n - 'a' + 10;
+
+        return -1;
+}
+
+static int __init qnap_tsx09_parse_hex_byte(const char *b)
+{
+        int hi;
+        int lo;
+
+        hi = qnap_tsx09_parse_hex_nibble(b[0]);
+        lo = qnap_tsx09_parse_hex_nibble(b[1]);
+
+        if (hi < 0 || lo < 0)
+                return -1;
+
+        return (hi << 4) | lo;
+}
+
+static int __init qnap_tsx09_check_mac_addr(const char *addr_str)
+{
+        u_int8_t addr[6];
+        int i;
+
+        for (i = 0; i < 6; i++) {
+                int byte;
+
+                /*
+                 * Enforce "xx:xx:xx:xx:xx:xx\n" format.
+                 */
+                if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n'))
+                        return -1;
+
+                byte = qnap_tsx09_parse_hex_byte(addr_str + (i * 3));
+                if (byte < 0)
+                        return -1;
+                addr[i] = byte;
+        }
+
+        printk(KERN_INFO "tsx09: found ethernet mac address ");
+        for (i = 0; i < 6; i++)
+                printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
+
+        memcpy(qnap_tsx09_eth_data.mac_addr, addr, 6);
+
+        return 0;
+}
+
+/*
+ * The 'NAS Config' flash partition has an ext2 filesystem which
+ * contains a file that has the ethernet MAC address in plain text
+ * (format "xx:xx:xx:xx:xx:xx\n").
+ */
+void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size)
+{
+        unsigned long addr;
+
+        for (addr = mem_base; addr < (mem_base + size); addr += 1024) {
+                char *nor_page;
+                int ret = 0;
+
+                nor_page = ioremap(addr, 1024);
+                if (nor_page != NULL) {
+                        ret = qnap_tsx09_check_mac_addr(nor_page);
+                        iounmap(nor_page);
+                }
+
+                if (ret == 0)
+                        break;
+        }
+}
diff --git a/arch/arm/mach-orion5x/tsx09-common.h b/arch/arm/mach-orion5x/tsx09-common.h
new file mode 100644
index 000000000000..0984264616f0
--- /dev/null
+++ b/arch/arm/mach-orion5x/tsx09-common.h
@@ -0,0 +1,20 @@
+#ifndef __ARCH_ORION5X_TSX09_COMMON_H
+#define __ARCH_ORION5X_TSX09_COMMON_H
+
+/*
+ * QNAP TS-x09 Boards power-off function
+ */
+extern void qnap_tsx09_power_off(void);
+
+/*
+ * QNAP TS-x09 Boards function to find Ethernet MAC address in flash memory
+ */
+extern void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size);
+
+/*
+ * QNAP TS-x09 Boards ethernet declaration
+ */
+extern struct mv643xx_eth_platform_data qnap_tsx09_eth_data;
+
+
+#endif
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
new file mode 100644
index 000000000000..1af093ff8cf3
--- /dev/null
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -0,0 +1,164 @@
+/*
+ * arch/arm/mach-orion5x/wnr854t-setup.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct orion5x_mpp_mode wnr854t_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* Power LED green (0=on) */
+        {  1, MPP_GPIO },               /* Reset Button (0=off) */
+        {  2, MPP_GPIO },               /* Power LED blink (0=off) */
+        {  3, MPP_GPIO },               /* WAN Status LED amber (0=off) */
+        {  4, MPP_GPIO },               /* PCI int */
+        {  5, MPP_GPIO },               /* ??? */
+        {  6, MPP_GPIO },               /* ??? */
+        {  7, MPP_GPIO },               /* ??? */
+        {  8, MPP_UNUSED },             /* ??? */
+        {  9, MPP_GIGE },               /* GE_RXERR */
+        { 10, MPP_UNUSED },             /* ??? */
+        { 11, MPP_UNUSED },             /* ??? */
+        { 12, MPP_GIGE },               /* GE_TXD[4] */
+        { 13, MPP_GIGE },               /* GE_TXD[5] */
+        { 14, MPP_GIGE },               /* GE_TXD[6] */
+        { 15, MPP_GIGE },               /* GE_TXD[7] */
+        { 16, MPP_GIGE },               /* GE_RXD[4] */
+        { 17, MPP_GIGE },               /* GE_RXD[5] */
+        { 18, MPP_GIGE },               /* GE_RXD[6] */
+        { 19, MPP_GIGE },               /* GE_RXD[7] */
+        { -1 },
+};
+
+/*
+ * 8M NOR flash Device bus boot chip select
+ */
+#define WNR854T_NOR_BOOT_BASE   0xf4000000
+#define WNR854T_NOR_BOOT_SIZE   SZ_8M
+
+static struct mtd_partition wnr854t_nor_flash_partitions[] = {
+        {
+                .name           = "kernel",
+                .offset         = 0x00000000,
+                .size           = 0x00100000,
+        }, {
+                .name           = "rootfs",
+                .offset         = 0x00100000,
+                .size           = 0x00660000,
+        }, {
+                .name           = "uboot",
+                .offset         = 0x00760000,
+                .size           = 0x00040000,
+        },
+};
+
+static struct physmap_flash_data wnr854t_nor_flash_data = {
+        .width          = 2,
+        .parts          = wnr854t_nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(wnr854t_nor_flash_partitions),
+};
+
+static struct resource wnr854t_nor_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = WNR854T_NOR_BOOT_BASE,
+        .end            = WNR854T_NOR_BOOT_BASE + WNR854T_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device wnr854t_nor_flash = {
+        .name                   = "physmap-flash",
+        .id                     = 0,
+        .dev            = {
+                .platform_data  = &wnr854t_nor_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &wnr854t_nor_flash_resource,
+};
+
+static struct mv643xx_eth_platform_data wnr854t_eth_data = {
+        .phy_addr       = -1,
+};
+
+static void __init wnr854t_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(wnr854t_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_eth_init(&wnr854t_eth_data);
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(WNR854T_NOR_BOOT_BASE,
+                                   WNR854T_NOR_BOOT_SIZE);
+        platform_device_register(&wnr854t_nor_flash);
+}
+
+static int __init wnr854t_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq;
+
+        /*
+         * Check for devices with hard-wired IRQs.
+         */
+        irq = orion5x_pci_map_irq(dev, slot, pin);
+        if (irq != -1)
+                return irq;
+
+        /*
+         * Mini-PCI slot.
+         */
+        if (slot == 7)
+                return gpio_to_irq(4);
+
+        return -1;
+}
+
+static struct hw_pci wnr854t_pci __initdata = {
+        .nr_controllers = 2,
+        .swizzle        = pci_std_swizzle,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = wnr854t_pci_map_irq,
+};
+
+static int __init wnr854t_pci_init(void)
+{
+        if (machine_is_wnr854t())
+                pci_common_init(&wnr854t_pci);
+
+        return 0;
+}
+subsys_initcall(wnr854t_pci_init);
+
+MACHINE_START(WNR854T, "Netgear WNR854T")
+        /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = wnr854t_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
new file mode 100644
index 000000000000..aeab55c6a82d
--- /dev/null
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -0,0 +1,173 @@
+/*
+ * arch/arm/mach-orion5x/wrt350n-v2-setup.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <asm/arch/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* Power LED green (0=on) */
+        {  1, MPP_GPIO },               /* Security LED (0=on) */
+        {  2, MPP_GPIO },               /* Internal Button (0=on) */
+        {  3, MPP_GPIO },               /* Reset Button (0=on) */
+        {  4, MPP_GPIO },               /* PCI int */
+        {  5, MPP_GPIO },               /* Power LED orange (0=on) */
+        {  6, MPP_GPIO },               /* USB LED (0=on) */
+        {  7, MPP_GPIO },               /* Wireless LED (0=on) */
+        {  8, MPP_UNUSED },             /* ??? */
+        {  9, MPP_GIGE },               /* GE_RXERR */
+        { 10, MPP_UNUSED },             /* ??? */
+        { 11, MPP_UNUSED },             /* ??? */
+        { 12, MPP_GIGE },               /* GE_TXD[4] */
+        { 13, MPP_GIGE },               /* GE_TXD[5] */
+        { 14, MPP_GIGE },               /* GE_TXD[6] */
+        { 15, MPP_GIGE },               /* GE_TXD[7] */
+        { 16, MPP_GIGE },               /* GE_RXD[4] */
+        { 17, MPP_GIGE },               /* GE_RXD[5] */
+        { 18, MPP_GIGE },               /* GE_RXD[6] */
+        { 19, MPP_GIGE },               /* GE_RXD[7] */
+        { -1 },
+};
+
+/*
+ * 8M NOR flash Device bus boot chip select
+ */
+#define WRT350N_V2_NOR_BOOT_BASE        0xf4000000
+#define WRT350N_V2_NOR_BOOT_SIZE        SZ_8M
+
+static struct mtd_partition wrt350n_v2_nor_flash_partitions[] = {
+        {
+                .name           = "kernel",
+                .offset         = 0x00000000,
+                .size           = 0x00760000,
+        }, {
+                .name           = "rootfs",
+                .offset         = 0x001a0000,
+                .size           = 0x005c0000,
+        }, {
+                .name           = "lang",
+                .offset         = 0x00760000,
+                .size           = 0x00040000,
+        }, {
+                .name           = "nvram",
+                .offset         = 0x007a0000,
+                .size           = 0x00020000,
+        }, {
+                .name           = "u-boot",
+                .offset         = 0x007c0000,
+                .size           = 0x00040000,
+        },
+};
+
+static struct physmap_flash_data wrt350n_v2_nor_flash_data = {
+        .width          = 1,
+        .parts          = wrt350n_v2_nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(wrt350n_v2_nor_flash_partitions),
+};
+
+static struct resource wrt350n_v2_nor_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = WRT350N_V2_NOR_BOOT_BASE,
+        .end            = WRT350N_V2_NOR_BOOT_BASE + WRT350N_V2_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device wrt350n_v2_nor_flash = {
+        .name                   = "physmap-flash",
+        .id                     = 0,
+        .dev            = {
+                .platform_data  = &wrt350n_v2_nor_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &wrt350n_v2_nor_flash_resource,
+};
+
+static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = {
+        .phy_addr       = -1,
+};
+
+static void __init wrt350n_v2_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(wrt350n_v2_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_eth_init(&wrt350n_v2_eth_data);
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE,
+                                   WRT350N_V2_NOR_BOOT_SIZE);
+        platform_device_register(&wrt350n_v2_nor_flash);
+}
+
+static int __init wrt350n_v2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq;
+
+        /*
+         * Check for devices with hard-wired IRQs.
+         */
+        irq = orion5x_pci_map_irq(dev, slot, pin);
+        if (irq != -1)
+                return irq;
+
+        /*
+         * Mini-PCI slot.
+         */
+        if (slot == 7)
+                return gpio_to_irq(4);
+
+        return -1;
+}
+
+static struct hw_pci wrt350n_v2_pci __initdata = {
+        .nr_controllers = 2,
+        .swizzle        = pci_std_swizzle,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = wrt350n_v2_pci_map_irq,
+};
+
+static int __init wrt350n_v2_pci_init(void)
+{
+        if (machine_is_wrt350n_v2())
+                pci_common_init(&wrt350n_v2_pci);
+
+        return 0;
+}
+subsys_initcall(wrt350n_v2_pci_init);
+
+MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
+        /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = wrt350n_v2_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 5da7a6820492..914bb33dab92 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -20,8 +20,7 @@ endmenu
 
 endif
 
-choice
-        prompt "Select target board"
+menu "Select target boards"
 
 config ARCH_GUMSTIX
         bool "Gumstix XScale boards"
@@ -37,10 +36,12 @@ config ARCH_LUBBOCK
 config MACH_LOGICPD_PXA270
         bool "LogicPD PXA270 Card Engine Development Platform"
         select PXA27x
+        select HAVE_PWM
 
 config MACH_MAINSTONE
         bool "Intel HCDDBBVA0 Development Platform"
         select PXA27x
+        select HAVE_PWM
 
 config ARCH_PXA_IDP
         bool "Accelent Xscale IDP"
@@ -116,6 +117,7 @@ config MACH_COLIBRI
 config MACH_ZYLONITE
         bool "PXA3xx Development Platform"
         select PXA3xx
+        select HAVE_PWM
 
 config MACH_LITTLETON
         bool "PXA3xx Form Factor Platform (aka Littleton)"
@@ -138,7 +140,7 @@ config MACH_PCM027
         select PXA27x
         select IWMMXT
 
-endchoice
+endmenu
 
 choice
         prompt "Used baseboard"
@@ -146,25 +148,24 @@ choice
 
 config MACH_PCM990_BASEBOARD
         bool "PHYTEC PCM-990 development board"
+        select HAVE_PWM
 
 endchoice
 
-if PXA_SHARPSL
-
 choice
-        prompt "Select target Sharp Zaurus device range"
+        prompt "display on pcm990"
+        depends on MACH_PCM990_BASEBOARD
 
-config PXA_SHARPSL_25x
-        bool "Sharp PXA25x models (SL-5600, SL-C7xx and SL-C6000x)"
-        select PXA25x
+config PCM990_DISPLAY_SHARP
+        bool "sharp lq084v1dg21 stn display"
 
-config PXA_SHARPSL_27x
-        bool "Sharp PXA270 models (SL-Cxx00)"
-        select PXA27x
+config PCM990_DISPLAY_NEC
+        bool "nec nl6448bc20_18d tft display"
 
-endchoice
+config PCM990_DISPLAY_NONE
+        bool "no display"
 
-endif
+endchoice
 
 if ARCH_GUMSTIX
 
@@ -199,28 +200,33 @@ endmenu
 
 config MACH_POODLE
         bool "Enable Sharp SL-5600 (Poodle) Support"
-        depends on PXA_SHARPSL_25x
+        depends on PXA_SHARPSL
+        select PXA25x
         select SHARP_LOCOMO
         select PXA_SSP
 
 config MACH_CORGI
         bool "Enable Sharp SL-C700 (Corgi) Support"
-        depends on PXA_SHARPSL_25x
+        depends on PXA_SHARPSL
+        select PXA25x
         select PXA_SHARP_C7xx
 
 config MACH_SHEPHERD
         bool "Enable Sharp SL-C750 (Shepherd) Support"
-        depends on PXA_SHARPSL_25x
+        depends on PXA_SHARPSL
+        select PXA25x
         select PXA_SHARP_C7xx
 
 config MACH_HUSKY
         bool "Enable Sharp SL-C760 (Husky) Support"
-        depends on PXA_SHARPSL_25x
+        depends on PXA_SHARPSL
+        select PXA25x
         select PXA_SHARP_C7xx
 
 config MACH_AKITA
         bool "Enable Sharp SL-1000 (Akita) Support"
-        depends on PXA_SHARPSL_27x
+        depends on PXA_SHARPSL
+        select PXA27x
         select PXA_SHARP_Cxx00
         select MACH_SPITZ
         select I2C
@@ -228,17 +234,20 @@ config MACH_AKITA
 
 config MACH_SPITZ
         bool "Enable Sharp Zaurus SL-3000 (Spitz) Support"
-        depends on PXA_SHARPSL_27x
+        depends on PXA_SHARPSL
+        select PXA27x
         select PXA_SHARP_Cxx00
 
 config MACH_BORZOI
         bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support"
-        depends on PXA_SHARPSL_27x
+        depends on PXA_SHARPSL
+        select PXA27x
         select PXA_SHARP_Cxx00
 
 config MACH_TOSA
         bool "Enable Sharp SL-6000x (Tosa) Support"
-        depends on PXA_SHARPSL_25x
+        depends on PXA_SHARPSL
+        select PXA25x
 
 config PXA25x
         bool
@@ -273,4 +282,10 @@ config PXA_SSP
         tristate
         help
           Enable support for PXA2xx SSP ports
+
+config PXA_PWM
+        tristate
+        default BACKLIGHT_PWM
+        help
+          Enable support for PXA2xx/PXA3xx PWM controllers
 endif
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 0e6d05bb81aa..c4dfbe87fc4e 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -10,10 +10,11 @@ obj-$(CONFIG_CPU_FREQ)		+= cpu-pxa.o
 
 # Generic drivers that other drivers may depend upon
 obj-$(CONFIG_PXA_SSP)           += ssp.o
+obj-$(CONFIG_PXA_PWM)           += pwm.o
 
 # SoC-specific code
-obj-$(CONFIG_PXA25x)            += mfp-pxa2xx.o pxa25x.o
-obj-$(CONFIG_PXA27x)            += mfp-pxa2xx.o pxa27x.o
+obj-$(CONFIG_PXA25x)            += mfp-pxa2xx.o pxa2xx.o pxa25x.o
+obj-$(CONFIG_PXA27x)            += mfp-pxa2xx.o pxa2xx.o pxa27x.o
 obj-$(CONFIG_PXA3xx)            += mfp-pxa3xx.o pxa3xx.o smemc.o
 obj-$(CONFIG_CPU_PXA300)        += pxa300.o
 obj-$(CONFIG_CPU_PXA320)        += pxa320.o
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index e97dc59813c8..b4d04955dcb0 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -12,7 +12,7 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 
-#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
 #include <asm/hardware.h>
 
@@ -47,6 +47,9 @@ struct clk *clk_get(struct device *dev, const char *id)
                 clk = p;
         mutex_unlock(&clocks_mutex);
 
+        if (!IS_ERR(clk) && clk->ops == NULL)
+                clk = clk->other;
+
         return clk;
 }
 EXPORT_SYMBOL(clk_get);
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index bc6b77e1592e..83cbfaba485d 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -15,6 +15,7 @@ struct clk {
         unsigned int            cken;
         unsigned int            delay;
         unsigned int            enabled;
+        struct clk              *other;
 };
 
 #define INIT_CKEN(_name, _cken, _rate, _delay, _dev)    \
@@ -35,6 +36,17 @@ struct clk {
                 .cken   = CKEN_##_cken,                 \
         }
 
+/*
+ * This is a placeholder to alias one clock device+name pair
+ * to another struct clk.
+ */
+#define INIT_CKOTHER(_name, _other, _dev)               \
+        {                                               \
+                .name   = _name,                        \
+                .dev    = _dev,                         \
+                .other  = _other,                       \
+        }
+
 extern const struct clkops clk_cken_ops;
 
 void clk_cken_enable(struct clk *clk);
diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c
index ac7f05f9f3eb..319c9ff3ab9a 100644
--- a/arch/arm/mach-pxa/cm-x270-pci.c
+++ b/arch/arm/mach-pxa/cm-x270-pci.c
@@ -41,18 +41,20 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
 {
         unsigned int sz = SZ_64M >> PAGE_SHIFT;
 
-        pr_info("Adjusting zones for CM-x270\n");
-
-        /*
-         * Only adjust if > 64M on current system
-         */
-        if (node || (zone_size[0] <= sz))
-                return;
-
-        zone_size[1] = zone_size[0] - sz;
-        zone_size[0] = sz;
-        zhole_size[1] = zhole_size[0];
-        zhole_size[0] = 0;
+        if (machine_is_armcore()) {
+                pr_info("Adjusting zones for CM-x270\n");
+
+                /*
+                 * Only adjust if > 64M on current system
+                 */
+                if (node || (zone_size[0] <= sz))
+                        return;
+
+                zone_size[1] = zone_size[0] - sz;
+                zone_size[0] = sz;
+                zhole_size[1] = zhole_size[0];
+                zhole_size[0] = 0;
+        }
 }
 
 static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index f5851d1adc25..01b9964acec1 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -31,6 +31,7 @@
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
+#include <asm/arch/audio.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/mmc.h>
@@ -81,12 +82,6 @@ static struct platform_device cmx270_device_dm9k = {
         }
 };
 
-/* audio device */
-static struct platform_device cmx270_audio_device = {
-        .name           = "pxa2xx-ac97",
-        .id             = -1,
-};
-
 /* touchscreen controller */
 static struct platform_device cmx270_ts_device = {
         .name           = "ucb1400_ts",
@@ -219,7 +214,6 @@ static struct platform_device cmx270_ata = {
 /* platform devices */
 static struct platform_device *platform_devices[] __initdata = {
         &cmx270_device_dm9k,
-        &cmx270_audio_device,
         &cmx270_rtc_device,
         &cmx270_2700G,
         &cmx270_led_device,
@@ -594,6 +588,7 @@ static void __init cmx270_init(void)
 
         /* register CM-X270 platform devices */
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        pxa_set_ac97_info(NULL);
 
         /* set MCI and OHCI platform parameters */
         pxa_set_mci_info(&cmx270_mci_platform_data);
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index b757dd756655..b37671b71886 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -36,6 +36,7 @@
 #include <asm/mach/irq.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/irda.h>
 #include <asm/arch/mmc.h>
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
index 0a85f706e887..e91c0f26c412 100644
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ b/arch/arm/mach-pxa/corgi_pm.c
@@ -26,6 +26,7 @@
 #include <asm/arch/sharpsl.h>
 #include <asm/arch/corgi.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
 #include "sharpsl.h"
 
@@ -204,7 +205,9 @@ static struct sharpsl_charger_machinfo corgi_pm_machinfo = {
         .read_devdata    = corgipm_read_devdata,
         .charger_wakeup  = corgi_charger_wakeup,
         .should_wakeup   = corgi_should_wakeup,
+#ifdef CONFIG_BACKLIGHT_CORGI
         .backlight_limit = corgibl_limit_intensity,
+#endif
         .charge_on_volt   = SHARPSL_CHARGE_ON_VOLT,
         .charge_on_temp   = SHARPSL_CHARGE_ON_TEMP,
         .charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH,
@@ -226,6 +229,10 @@ static int __devinit corgipm_init(void)
 {
         int ret;
 
+        if (!machine_is_corgi() && !machine_is_shepherd()
+                        && !machine_is_husky())
+                return -ENODEV;
+
         corgipm_device = platform_device_alloc("sharpsl-pm", -1);
         if (!corgipm_device)
                 return -ENOMEM;
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index d6c05b6eab35..a6f2390ce662 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -10,11 +10,14 @@
 #include <asm/arch/mmc.h>
 #include <asm/arch/irda.h>
 #include <asm/arch/i2c.h>
+#include <asm/arch/mfp-pxa27x.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/pxa27x_keypad.h>
 #include <asm/arch/camera.h>
+#include <asm/arch/audio.h>
 
 #include "devices.h"
+#include "generic.h"
 
 void __init pxa_register_device(struct platform_device *dev, void *data)
 {
@@ -91,8 +94,19 @@ static struct resource pxa2xx_udc_resources[] = {
 
 static u64 udc_dma_mask = ~(u32)0;
 
-struct platform_device pxa_device_udc = {
-        .name           = "pxa2xx-udc",
+struct platform_device pxa25x_device_udc = {
+        .name           = "pxa25x-udc",
+        .id             = -1,
+        .resource       = pxa2xx_udc_resources,
+        .num_resources  = ARRAY_SIZE(pxa2xx_udc_resources),
+        .dev            =  {
+                .platform_data  = &pxa_udc_info,
+                .dma_mask       = &udc_dma_mask,
+        }
+};
+
+struct platform_device pxa27x_device_udc = {
+        .name           = "pxa27x-udc",
         .id             = -1,
         .resource       = pxa2xx_udc_resources,
         .num_resources  = ARRAY_SIZE(pxa2xx_udc_resources),
@@ -233,8 +247,15 @@ struct platform_device pxa_device_i2c = {
         .num_resources  = ARRAY_SIZE(pxai2c_resources),
 };
 
+static unsigned long pxa27x_i2c_mfp_cfg[] = {
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+};
+
 void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
 {
+        if (cpu_is_pxa27x())
+                pxa2xx_mfp_config(ARRAY_AND_SIZE(pxa27x_i2c_mfp_cfg));
         pxa_register_device(&pxa_device_i2c, info);
 }
 
@@ -278,8 +299,69 @@ struct platform_device pxa_device_rtc = {
         .id             = -1,
 };
 
+static struct resource pxa_ac97_resources[] = {
+        [0] = {
+                .start  = 0x40500000,
+                .end    = 0x40500000 + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_AC97,
+                .end    = IRQ_AC97,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 pxa_ac97_dmamask = 0xffffffffUL;
+
+struct platform_device pxa_device_ac97 = {
+        .name           = "pxa2xx-ac97",
+        .id             = -1,
+        .dev            = {
+                .dma_mask = &pxa_ac97_dmamask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(pxa_ac97_resources),
+        .resource       = pxa_ac97_resources,
+};
+
+void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
+{
+        pxa_register_device(&pxa_device_ac97, ops);
+}
+
 #ifdef CONFIG_PXA25x
 
+static struct resource pxa25x_resource_pwm0[] = {
+        [0] = {
+                .start  = 0x40b00000,
+                .end    = 0x40b0000f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device pxa25x_device_pwm0 = {
+        .name           = "pxa25x-pwm",
+        .id             = 0,
+        .resource       = pxa25x_resource_pwm0,
+        .num_resources  = ARRAY_SIZE(pxa25x_resource_pwm0),
+};
+
+static struct resource pxa25x_resource_pwm1[] = {
+        [0] = {
+                .start  = 0x40c00000,
+                .end    = 0x40c0000f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device pxa25x_device_pwm1 = {
+        .name           = "pxa25x-pwm",
+        .id             = 1,
+        .resource       = pxa25x_resource_pwm1,
+        .num_resources  = ARRAY_SIZE(pxa25x_resource_pwm1),
+};
+
 static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
 
 static struct resource pxa25x_resource_ssp[] = {
@@ -568,6 +650,36 @@ struct platform_device pxa27x_device_ssp3 = {
         .num_resources  = ARRAY_SIZE(pxa27x_resource_ssp3),
 };
 
+static struct resource pxa27x_resource_pwm0[] = {
+        [0] = {
+                .start  = 0x40b00000,
+                .end    = 0x40b0001f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device pxa27x_device_pwm0 = {
+        .name           = "pxa27x-pwm",
+        .id             = 0,
+        .resource       = pxa27x_resource_pwm0,
+        .num_resources  = ARRAY_SIZE(pxa27x_resource_pwm0),
+};
+
+static struct resource pxa27x_resource_pwm1[] = {
+        [0] = {
+                .start  = 0x40c00000,
+                .end    = 0x40c0001f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device pxa27x_device_pwm1 = {
+        .name           = "pxa27x-pwm",
+        .id             = 1,
+        .resource       = pxa27x_resource_pwm1,
+        .num_resources  = ARRAY_SIZE(pxa27x_resource_pwm1),
+};
+
 static struct resource pxa27x_resource_camera[] = {
         [0] = {
                 .start  = 0x50000000,
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index fcab017f27ee..b852eb18daa5 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -1,7 +1,8 @@
 extern struct platform_device pxa_device_mci;
 extern struct platform_device pxa3xx_device_mci2;
 extern struct platform_device pxa3xx_device_mci3;
-extern struct platform_device pxa_device_udc;
+extern struct platform_device pxa25x_device_udc;
+extern struct platform_device pxa27x_device_udc;
 extern struct platform_device pxa_device_fb;
 extern struct platform_device pxa_device_ffuart;
 extern struct platform_device pxa_device_btuart;
@@ -11,6 +12,7 @@ extern struct platform_device pxa_device_i2c;
 extern struct platform_device pxa_device_i2s;
 extern struct platform_device pxa_device_ficp;
 extern struct platform_device pxa_device_rtc;
+extern struct platform_device pxa_device_ac97;
 
 extern struct platform_device pxa27x_device_i2c_power;
 extern struct platform_device pxa27x_device_ohci;
@@ -24,4 +26,9 @@ extern struct platform_device pxa27x_device_ssp2;
 extern struct platform_device pxa27x_device_ssp3;
 extern struct platform_device pxa3xx_device_ssp4;
 
+extern struct platform_device pxa25x_device_pwm0;
+extern struct platform_device pxa25x_device_pwm1;
+extern struct platform_device pxa27x_device_pwm0;
+extern struct platform_device pxa27x_device_pwm1;
+
 void __init pxa_register_device(struct platform_device *dev, void *data);
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 9c57700ee5c2..1bf680749928 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -24,6 +24,8 @@
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
+#include <asm/arch/pxa27x-udc.h>
+#include <asm/arch/audio.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/mmc.h>
@@ -72,12 +74,6 @@ static struct platform_device em_x270_dm9k = {
         }
 };
 
-/* audio device */
-static struct platform_device em_x270_audio = {
-        .name           = "pxa2xx-ac97",
-        .id             = -1,
-};
-
 /* WM9712 touchscreen controller. Hopefully the driver will make it to
  * the mainstream sometime */
 static struct platform_device em_x270_ts = {
@@ -217,7 +213,6 @@ static struct platform_device em_x270_nand = {
 /* platform devices */
 static struct platform_device *platform_devices[] __initdata = {
         &em_x270_dm9k,
-        &em_x270_audio,
         &em_x270_ts,
         &em_x270_rtc,
         &em_x270_nand,
@@ -325,6 +320,7 @@ static void __init em_x270_init(void)
 
         /* register EM-X270 platform devices */
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        pxa_set_ac97_info(NULL);
 
         /* set MCI and OHCI platform parameters */
         pxa_set_mci_info(&em_x270_mci_platform_data);
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 44617938f3f1..ca053226fba0 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -60,23 +60,6 @@ unsigned int get_memclk_frequency_10khz(void)
 EXPORT_SYMBOL(get_memclk_frequency_10khz);
 
 /*
- * Routine to safely enable or disable a clock in the CKEN
- */
-void __pxa_set_cken(int clock, int enable)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-
-        if (enable)
-                CKEN |= (1 << clock);
-        else
-                CKEN &= ~(1 << clock);
-
-        local_irq_restore(flags);
-}
-EXPORT_SYMBOL(__pxa_set_cken);
-
-/*
  * Intel PXA2xx internal register mapping.
  *
  * Note 1: not all PXA2xx variants implement all those addresses.
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index a9a0c3fab159..fbff557bb225 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -21,7 +21,6 @@
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index a20e4b1649d6..cc1c4fa06145 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -23,6 +23,7 @@
 #include <linux/ioport.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/pwm_backlight.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -134,9 +135,12 @@ static struct sys_device lpd270_irq_device = {
 
 static int __init lpd270_irq_device_init(void)
 {
-        int ret = sysdev_class_register(&lpd270_irq_sysclass);
-        if (ret == 0)
-                ret = sysdev_register(&lpd270_irq_device);
+        int ret = -ENODEV;
+        if (machine_is_logicpd_pxa270()) {
+                ret = sysdev_class_register(&lpd270_irq_sysclass);
+                if (ret == 0)
+                        ret = sysdev_register(&lpd270_irq_device);
+        }
         return ret;
 }
 
@@ -164,11 +168,6 @@ static struct platform_device smc91x_device = {
         .resource       = smc91x_resources,
 };
 
-static struct platform_device lpd270_audio_device = {
-        .name           = "pxa2xx-ac97",
-        .id             = -1,
-};
-
 static struct resource lpd270_flash_resources[] = {
         [0] = {
                 .start  = PXA_CS0_PHYS,
@@ -233,21 +232,20 @@ static struct platform_device lpd270_flash_device[2] = {
         },
 };
 
-static void lpd270_backlight_power(int on)
-{
-        if (on) {
-                pxa_gpio_mode(GPIO16_PWM0_MD);
-                pxa_set_cken(CKEN_PWM0, 1);
-                PWM_CTRL0 = 0;
-                PWM_PWDUTY0 = 0x3ff;
-                PWM_PERVAL0 = 0x3ff;
-        } else {
-                PWM_CTRL0 = 0;
-                PWM_PWDUTY0 = 0x0;
-                PWM_PERVAL0 = 0x3FF;
-                pxa_set_cken(CKEN_PWM0, 0);
-        }
-}
+static struct platform_pwm_backlight_data lpd270_backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = 1,
+        .dft_brightness = 1,
+        .pwm_period_ns  = 78770,
+};
+
+static struct platform_device lpd270_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent = &pxa27x_device_pwm0.dev,
+                .platform_data = &lpd270_backlight_data,
+        },
+};
 
 /* 5.7" TFT QVGA (LoLo display number 1) */
 static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
@@ -269,7 +267,6 @@ static struct pxafb_mach_info sharp_lq057q3dc02 = {
         .num_modes              = 1,
         .lccr0                  = 0x07800080,
         .lccr3                  = 0x00400000,
-        .pxafb_backlight_power  = lpd270_backlight_power,
 };
 
 /* 12.1" TFT SVGA (LoLo display number 2) */
@@ -292,7 +289,6 @@ static struct pxafb_mach_info sharp_lq121s1dg31 = {
         .num_modes              = 1,
         .lccr0                  = 0x07800080,
         .lccr3                  = 0x00400000,
-        .pxafb_backlight_power  = lpd270_backlight_power,
 };
 
 /* 3.6" TFT QVGA (LoLo display number 3) */
@@ -315,7 +311,6 @@ static struct pxafb_mach_info sharp_lq036q1da01 = {
         .num_modes              = 1,
         .lccr0                  = 0x07800080,
         .lccr3                  = 0x00400000,
-        .pxafb_backlight_power  = lpd270_backlight_power,
 };
 
 /* 6.4" TFT VGA (LoLo display number 5) */
@@ -338,7 +333,6 @@ static struct pxafb_mach_info sharp_lq64d343 = {
         .num_modes              = 1,
         .lccr0                  = 0x07800080,
         .lccr3                  = 0x00400000,
-        .pxafb_backlight_power  = lpd270_backlight_power,
 };
 
 /* 10.4" TFT VGA (LoLo display number 7) */
@@ -361,7 +355,6 @@ static struct pxafb_mach_info sharp_lq10d368 = {
         .num_modes              = 1,
         .lccr0                  = 0x07800080,
         .lccr3                  = 0x00400000,
-        .pxafb_backlight_power  = lpd270_backlight_power,
 };
 
 /* 3.5" TFT QVGA (LoLo display number 8) */
@@ -384,7 +377,6 @@ static struct pxafb_mach_info sharp_lq035q7db02_20 = {
         .num_modes              = 1,
         .lccr0                  = 0x07800080,
         .lccr3                  = 0x00400000,
-        .pxafb_backlight_power  = lpd270_backlight_power,
 };
 
 static struct pxafb_mach_info *lpd270_lcd_to_use;
@@ -414,7 +406,7 @@ __setup("lcd=", lpd270_set_lcd);
 
 static struct platform_device *platform_devices[] __initdata = {
         &smc91x_device,
-        &lpd270_audio_device,
+        &lpd270_backlight_device,
         &lpd270_flash_device[0],
         &lpd270_flash_device[1],
 };
@@ -454,9 +446,12 @@ static void __init lpd270_init(void)
          * On LogicPD PXA270, we route AC97_SYSCLK via GPIO45.
          */
         pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
+        pxa_gpio_mode(GPIO16_PWM0_MD);
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
+        pxa_set_ac97_info(NULL);
+
         if (lpd270_lcd_to_use != NULL)
                 set_pxa_fb_info(lpd270_lcd_to_use);
 
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 7b9bdd0c6665..a3fae4139203 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -43,6 +43,7 @@
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/mfp-pxa25x.h>
+#include <asm/arch/audio.h>
 #include <asm/arch/lubbock.h>
 #include <asm/arch/udc.h>
 #include <asm/arch/irda.h>
@@ -196,11 +197,6 @@ static struct pxa2xx_udc_mach_info udc_info __initdata = {
         // no D+ pullup; lubbock can't connect/disconnect in software
 };
 
-static struct platform_device lub_audio_device = {
-        .name           = "pxa2xx-ac97",
-        .id             = -1,
-};
-
 static struct resource sa1111_resources[] = {
         [0] = {
                 .start  = 0x10000000,
@@ -368,7 +364,6 @@ static struct platform_device lubbock_flash_device[2] = {
 
 static struct platform_device *devices[] __initdata = {
         &sa1111_device,
-        &lub_audio_device,
         &smc91x_device,
         &lubbock_flash_device[0],
         &lubbock_flash_device[1],
@@ -494,6 +489,7 @@ static void __init lubbock_init(void)
         set_pxa_fb_info(&sharp_lm8v31);
         pxa_set_mci_info(&lubbock_mci_platform_data);
         pxa_set_ficp_info(&lubbock_ficp_platform_data);
+        pxa_set_ac97_info(NULL);
 
         lubbock_flash_data[0].width = lubbock_flash_data[1].width =
                 (BOOT_DEF & 1) ? 2 : 4;
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index badba064dc04..01b2fa790217 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -25,6 +25,7 @@
 #include <linux/mtd/map.h>
 #include <linux/mtd/physmap.h>
 #include <linux/pda_power.h>
+#include <linux/pwm_backlight.h>
 
 #include <asm/gpio.h>
 #include <asm/hardware.h>
@@ -33,12 +34,14 @@
 #include <asm/arch/magician.h>
 #include <asm/arch/mfp-pxa27x.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/i2c.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/irda.h>
 #include <asm/arch/ohci.h>
 
+#include "devices.h"
 #include "generic.h"
 
 static unsigned long magician_pin_config[] = {
@@ -348,40 +351,58 @@ static struct pxafb_mach_info samsung_info = {
  * Backlight
  */
 
-static void magician_set_bl_intensity(int intensity)
+static int magician_backlight_init(struct device *dev)
 {
-        if (intensity) {
-                PWM_CTRL0 = 1;
-                PWM_PERVAL0 = 0xc8;
-                if (intensity > 0xc7) {
-                        PWM_PWDUTY0 = intensity - 0x48;
-                        gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 1);
-                } else {
-                        PWM_PWDUTY0 = intensity;
-                        gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 0);
-                }
-                gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 1);
-                pxa_set_cken(CKEN_PWM0, 1);
+        int ret;
+
+        ret = gpio_request(EGPIO_MAGICIAN_BL_POWER, "BL_POWER");
+        if (ret)
+                goto err;
+        ret = gpio_request(EGPIO_MAGICIAN_BL_POWER2, "BL_POWER2");
+        if (ret)
+                goto err2;
+        return 0;
+
+err2:
+        gpio_free(EGPIO_MAGICIAN_BL_POWER);
+err:
+        return ret;
+}
+
+static int magician_backlight_notify(int brightness)
+{
+        gpio_set_value(EGPIO_MAGICIAN_BL_POWER, brightness);
+        if (brightness >= 200) {
+                gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 1);
+                return brightness - 72;
         } else {
-                /* PWM_PWDUTY0 = intensity; */
-                gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 0);
-                pxa_set_cken(CKEN_PWM0, 0);
+                gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 0);
+                return brightness;
         }
 }
 
-static struct generic_bl_info backlight_info = {
-        .default_intensity = 0x64,
-        .limit_mask        = 0x0b,
-        .max_intensity     = 0xc7+0x48,
-        .set_bl_intensity  = magician_set_bl_intensity,
+static void magician_backlight_exit(struct device *dev)
+{
+        gpio_free(EGPIO_MAGICIAN_BL_POWER);
+        gpio_free(EGPIO_MAGICIAN_BL_POWER2);
+}
+
+static struct platform_pwm_backlight_data backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = 272,
+        .dft_brightness = 100,
+        .pwm_period_ns  = 30923,
+        .init           = magician_backlight_init,
+        .notify         = magician_backlight_notify,
+        .exit           = magician_backlight_exit,
 };
 
 static struct platform_device backlight = {
-        .name = "generic-bl",
+        .name = "pwm-backlight",
         .dev  = {
-                .platform_data = &backlight_info,
+                .parent        = &pxa27x_device_pwm0.dev,
+                .platform_data = &backlight_data,
         },
-        .id   = -1,
 };
 
 /*
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 7399fb34da4e..f2e9e7c4da8e 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -23,9 +23,9 @@
 #include <linux/ioport.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
-#include <linux/backlight.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
+#include <linux/pwm_backlight.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -280,12 +280,6 @@ static pxa2xx_audio_ops_t mst_audio_ops = {
         .resume         = mst_audio_resume,
 };
 
-static struct platform_device mst_audio_device = {
-        .name           = "pxa2xx-ac97",
-        .id             = -1,
-        .dev            = { .platform_data = &mst_audio_ops },
-};
-
 static struct resource flash_resources[] = {
         [0] = {
                 .start  = PXA_CS0_PHYS,
@@ -349,56 +343,27 @@ static struct platform_device mst_flash_device[2] = {
         },
 };
 
-#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
-static int mainstone_backlight_update_status(struct backlight_device *bl)
-{
-        int brightness = bl->props.brightness;
-
-        if (bl->props.power != FB_BLANK_UNBLANK ||
-            bl->props.fb_blank != FB_BLANK_UNBLANK)
-                brightness = 0;
-
-        if (brightness != 0)
-                pxa_set_cken(CKEN_PWM0, 1);
-
-        PWM_CTRL0 = 0;
-        PWM_PWDUTY0 = brightness;
-        PWM_PERVAL0 = bl->props.max_brightness;
-
-        if (brightness == 0)
-                pxa_set_cken(CKEN_PWM0, 0);
-        return 0; /* pointless return value */
-}
-
-static int mainstone_backlight_get_brightness(struct backlight_device *bl)
-{
-        return PWM_PWDUTY0;
-}
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static struct platform_pwm_backlight_data mainstone_backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = 1023,
+        .dft_brightness = 1023,
+        .pwm_period_ns  = 78770,
+};
 
-static /*const*/ struct backlight_ops mainstone_backlight_ops = {
-        .update_status  = mainstone_backlight_update_status,
-        .get_brightness = mainstone_backlight_get_brightness,
+static struct platform_device mainstone_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent = &pxa27x_device_pwm0.dev,
+                .platform_data = &mainstone_backlight_data,
+        },
 };
 
 static void __init mainstone_backlight_register(void)
 {
-        struct backlight_device *bl;
-
-        bl = backlight_device_register("mainstone-bl", &pxa_device_fb.dev,
-                                       NULL, &mainstone_backlight_ops);
-        if (IS_ERR(bl)) {
-                printk(KERN_ERR "mainstone: unable to register backlight: %ld\n",
-                       PTR_ERR(bl));
-                return;
-        }
-
-        /*
-         * broken design - register-then-setup interfaces are
-         * utterly broken by definition.
-         */
-        bl->props.max_brightness = 1023;
-        bl->props.brightness = 1023;
-        backlight_update_status(bl);
+        int ret = platform_device_register(&mainstone_backlight_device);
+        if (ret)
+                printk(KERN_ERR "mainstone: failed to register backlight device: %d\n", ret);
 }
 #else
 #define mainstone_backlight_register()  do { } while (0)
@@ -528,7 +493,6 @@ static struct platform_device mst_gpio_keys_device = {
 
 static struct platform_device *platform_devices[] __initdata = {
         &smc91x_device,
-        &mst_audio_device,
         &mst_flash_device[0],
         &mst_flash_device[1],
         &mst_gpio_keys_device,
@@ -638,6 +602,7 @@ static void __init mainstone_init(void)
         pxa_set_ficp_info(&mainstone_ficp_platform_data);
         pxa_set_ohci_info(&mainstone_ohci_platform_data);
         pxa_set_i2c_info(NULL);
+        pxa_set_ac97_info(&mst_audio_ops);
 
         mainstone_init_keypad();
 }
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index 22097a1707cc..d1cdb4ecb0b8 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -20,6 +20,7 @@
 
 #include <asm/arch/hardware.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/mfp-pxa2xx.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 49d951db0f3d..5d87c7c866e4 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -24,6 +24,7 @@
 #include <linux/platform_device.h>
 #include <linux/ide.h>
 #include <linux/i2c.h>
+#include <linux/pwm_backlight.h>
 
 #include <media/soc_camera.h>
 
@@ -33,12 +34,103 @@
 #include <asm/mach/map.h>
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
+#include <asm/arch/audio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/pcm990_baseboard.h>
+#include <asm/arch/pxafb.h>
+
+#include "devices.h"
 
 /*
- * The PCM-990 development baseboard uses PCM-027's hardeware in the
+ * pcm990_lcd_power - control power supply to the LCD
+ * @on: 0 = switch off, 1 = switch on
+ *
+ * Called by the pxafb driver
+ */
+#ifndef CONFIG_PCM990_DISPLAY_NONE
+static void pcm990_lcd_power(int on, struct fb_var_screeninfo *var)
+{
+        if (on) {
+                /* enable LCD-Latches
+                 * power on LCD
+                 */
+                __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) =
+                        PCM990_CTRL_LCDPWR + PCM990_CTRL_LCDON;
+        } else {
+                /* disable LCD-Latches
+                 * power off LCD
+                 */
+                __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) = 0x00;
+        }
+}
+#endif
+
+#if defined(CONFIG_PCM990_DISPLAY_SHARP)
+static struct pxafb_mode_info fb_info_sharp_lq084v1dg21 = {
+        .pixclock               = 28000,
+        .xres                   = 640,
+        .yres                   = 480,
+        .bpp                    = 16,
+        .hsync_len              = 20,
+        .left_margin            = 103,
+        .right_margin           = 47,
+        .vsync_len              = 6,
+        .upper_margin           = 28,
+        .lower_margin           = 5,
+        .sync                   = 0,
+        .cmap_greyscale         = 0,
+};
+
+static struct pxafb_mach_info pcm990_fbinfo __initdata = {
+        .modes                  = &fb_info_sharp_lq084v1dg21,
+        .num_modes              = 1,
+        .lccr0                  = LCCR0_PAS,
+        .lccr3                  = LCCR3_PCP,
+        .pxafb_lcd_power        = pcm990_lcd_power,
+};
+#elif defined(CONFIG_PCM990_DISPLAY_NEC)
+struct pxafb_mode_info fb_info_nec_nl6448bc20_18d = {
+        .pixclock               = 39720,
+        .xres                   = 640,
+        .yres                   = 480,
+        .bpp                    = 16,
+        .hsync_len              = 32,
+        .left_margin            = 16,
+        .right_margin           = 48,
+        .vsync_len              = 2,
+        .upper_margin           = 12,
+        .lower_margin           = 17,
+        .sync                   = 0,
+        .cmap_greyscale         = 0,
+};
+
+static struct pxafb_mach_info pcm990_fbinfo __initdata = {
+        .modes                  = &fb_info_nec_nl6448bc20_18d,
+        .num_modes              = 1,
+        .lccr0                  = LCCR0_Act,
+        .lccr3                  = LCCR3_PixFlEdg,
+        .pxafb_lcd_power        = pcm990_lcd_power,
+};
+#endif
+
+static struct platform_pwm_backlight_data pcm990_backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = 1023,
+        .dft_brightness = 1023,
+        .pwm_period_ns  = 78770,
+};
+
+static struct platform_device pcm990_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent = &pxa27x_device_pwm0.dev,
+                .platform_data = &pcm990_backlight_data,
+        },
+};
+
+/*
+ * The PCM-990 development baseboard uses PCM-027's hardware in the
  * following way:
  *
  * - LCD support is in use
@@ -333,36 +425,6 @@ static struct i2c_board_info __initdata pcm990_i2c_devices[] = {
 #endif /* CONFIG_VIDEO_PXA27x ||CONFIG_VIDEO_PXA27x_MODULE */
 
 /*
- * AC97 support
- * Note: The connected AC97 mixer also reports interrupts at PCM990_AC97_IRQ
- */
-static struct resource pxa27x_ac97_resources[] = {
-        [0] = {
-                .start  = 0x40500000,
-                .end    = 0x40500000 + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_AC97,
-                .end    = IRQ_AC97,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static u64 pxa_ac97_dmamask = 0xffffffffUL;
-
-static struct platform_device pxa27x_device_ac97 = {
-        .name           = "pxa2xx-ac97",
-        .id             = -1,
-        .dev            = {
-                .dma_mask = &pxa_ac97_dmamask,
-                .coherent_dma_mask = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(pxa27x_ac97_resources),
-        .resource       = pxa27x_ac97_resources,
-};
-
-/*
  * enable generic access to the base board control CPLDs U6 and U7
  */
 static struct map_desc pcm990_io_desc[] __initdata = {
@@ -393,7 +455,11 @@ void __init pcm990_baseboard_init(void)
         /* register CPLD's IRQ controller */
         pcm990_init_irq();
 
-        platform_device_register(&pxa27x_device_ac97);
+#ifndef CONFIG_PCM990_DISPLAY_NONE
+        set_pxa_fb_info(&pcm990_fbinfo);
+#endif
+        pxa_gpio_mode(GPIO16_PWM0_MD);
+        platform_device_register(&pcm990_backlight_device);
 
         /* MMC */
         pxa_set_mci_info(&pcm990_mci_platform_data);
@@ -402,6 +468,7 @@ void __init pcm990_baseboard_init(void)
         pxa_set_ohci_info(&pcm990_ohci_platform_data);
 
         pxa_set_i2c_info(NULL);
+        pxa_set_ac97_info(NULL);
 
 #if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
         pxa_set_camera_info(&pcm990_pxacamera_platform_data);
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 0b30f25cff3c..f81c10cafd48 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -32,6 +32,7 @@
 #include <asm/mach/irq.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/udc.h>
diff --git a/arch/arm/mach-pxa/pwm.c b/arch/arm/mach-pxa/pwm.c
new file mode 100644
index 000000000000..ce28cd9fed16
--- /dev/null
+++ b/arch/arm/mach-pxa/pwm.c
@@ -0,0 +1,319 @@
+/*
+ * linux/arch/arm/mach-pxa/pwm.c
+ *
+ * simple driver for PWM (Pulse Width Modulator) controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * 2008-02-13   initial version
+ *              eric miao <eric.miao@marvell.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/pwm.h>
+
+#include <asm/div64.h>
+#include <asm/arch/pxa-regs.h>
+
+/* PWM registers and bits definitions */
+#define PWMCR           (0x00)
+#define PWMDCR          (0x04)
+#define PWMPCR          (0x08)
+
+#define PWMCR_SD        (1 << 6)
+#define PWMDCR_FD       (1 << 10)
+
+struct pwm_device {
+        struct list_head        node;
+        struct platform_device *pdev;
+
+        const char      *label;
+        struct clk      *clk;
+        int             clk_enabled;
+        void __iomem    *mmio_base;
+
+        unsigned int    use_count;
+        unsigned int    pwm_id;
+};
+
+/*
+ * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE
+ * duty_ns   = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
+ */
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+        unsigned long long c;
+        unsigned long period_cycles, prescale, pv, dc;
+
+        if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
+                return -EINVAL;
+
+        c = clk_get_rate(pwm->clk);
+        c = c * period_ns;
+        do_div(c, 1000000000);
+        period_cycles = c;
+
+        if (period_cycles < 0)
+                period_cycles = 1;
+        prescale = (period_cycles - 1) / 1024;
+        pv = period_cycles / (prescale + 1) - 1;
+
+        if (prescale > 63)
+                return -EINVAL;
+
+        if (duty_ns == period_ns)
+                dc = PWMDCR_FD;
+        else
+                dc = (pv + 1) * duty_ns / period_ns;
+
+        /* NOTE: the clock to PWM has to be enabled first
+         * before writing to the registers
+         */
+        clk_enable(pwm->clk);
+        __raw_writel(prescale, pwm->mmio_base + PWMCR);
+        __raw_writel(dc, pwm->mmio_base + PWMDCR);
+        __raw_writel(pv, pwm->mmio_base + PWMPCR);
+        clk_disable(pwm->clk);
+
+        return 0;
+}
+EXPORT_SYMBOL(pwm_config);
+
+int pwm_enable(struct pwm_device *pwm)
+{
+        int rc = 0;
+
+        if (!pwm->clk_enabled) {
+                rc = clk_enable(pwm->clk);
+                if (!rc)
+                        pwm->clk_enabled = 1;
+        }
+        return rc;
+}
+EXPORT_SYMBOL(pwm_enable);
+
+void pwm_disable(struct pwm_device *pwm)
+{
+        if (pwm->clk_enabled) {
+                clk_disable(pwm->clk);
+                pwm->clk_enabled = 0;
+        }
+}
+EXPORT_SYMBOL(pwm_disable);
+
+static DEFINE_MUTEX(pwm_lock);
+static LIST_HEAD(pwm_list);
+
+struct pwm_device *pwm_request(int pwm_id, const char *label)
+{
+        struct pwm_device *pwm;
+        int found = 0;
+
+        mutex_lock(&pwm_lock);
+
+        list_for_each_entry(pwm, &pwm_list, node) {
+                if (pwm->pwm_id == pwm_id) {
+                        found = 1;
+                        break;
+                }
+        }
+
+        if (found) {
+                if (pwm->use_count == 0) {
+                        pwm->use_count++;
+                        pwm->label = label;
+                } else
+                        pwm = ERR_PTR(-EBUSY);
+        } else
+                pwm = ERR_PTR(-ENOENT);
+
+        mutex_unlock(&pwm_lock);
+        return pwm;
+}
+EXPORT_SYMBOL(pwm_request);
+
+void pwm_free(struct pwm_device *pwm)
+{
+        mutex_lock(&pwm_lock);
+
+        if (pwm->use_count) {
+                pwm->use_count--;
+                pwm->label = NULL;
+        } else
+                pr_warning("PWM device already freed\n");
+
+        mutex_unlock(&pwm_lock);
+}
+EXPORT_SYMBOL(pwm_free);
+
+static inline void __add_pwm(struct pwm_device *pwm)
+{
+        mutex_lock(&pwm_lock);
+        list_add_tail(&pwm->node, &pwm_list);
+        mutex_unlock(&pwm_lock);
+}
+
+static struct pwm_device *pwm_probe(struct platform_device *pdev,
+                unsigned int pwm_id, struct pwm_device *parent_pwm)
+{
+        struct pwm_device *pwm;
+        struct resource *r;
+        int ret = 0;
+
+        pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
+        if (pwm == NULL) {
+                dev_err(&pdev->dev, "failed to allocate memory\n");
+                return ERR_PTR(-ENOMEM);
+        }
+
+        pwm->clk = clk_get(&pdev->dev, "PWMCLK");
+        if (IS_ERR(pwm->clk)) {
+                ret = PTR_ERR(pwm->clk);
+                goto err_free;
+        }
+        pwm->clk_enabled = 0;
+
+        pwm->use_count = 0;
+        pwm->pwm_id = pwm_id;
+        pwm->pdev = pdev;
+
+        if (parent_pwm != NULL) {
+                /* registers for the second PWM has offset of 0x10 */
+                pwm->mmio_base = parent_pwm->mmio_base + 0x10;
+                __add_pwm(pwm);
+                return pwm;
+        }
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (r == NULL) {
+                dev_err(&pdev->dev, "no memory resource defined\n");
+                ret = -ENODEV;
+                goto err_free_clk;
+        }
+
+        r = request_mem_region(r->start, r->end - r->start + 1, pdev->name);
+        if (r == NULL) {
+                dev_err(&pdev->dev, "failed to request memory resource\n");
+                ret = -EBUSY;
+                goto err_free_clk;
+        }
+
+        pwm->mmio_base = ioremap(r->start, r->end - r->start + 1);
+        if (pwm->mmio_base == NULL) {
+                dev_err(&pdev->dev, "failed to ioremap() registers\n");
+                ret = -ENODEV;
+                goto err_free_mem;
+        }
+
+        __add_pwm(pwm);
+        platform_set_drvdata(pdev, pwm);
+        return pwm;
+
+err_free_mem:
+        release_mem_region(r->start, r->end - r->start + 1);
+err_free_clk:
+        clk_put(pwm->clk);
+err_free:
+        kfree(pwm);
+        return ERR_PTR(ret);
+}
+
+static int __devinit pxa25x_pwm_probe(struct platform_device *pdev)
+{
+        struct pwm_device *pwm = pwm_probe(pdev, pdev->id, NULL);
+
+        if (IS_ERR(pwm))
+                return PTR_ERR(pwm);
+
+        return 0;
+}
+
+static int __devinit pxa27x_pwm_probe(struct platform_device *pdev)
+{
+        struct pwm_device *pwm;
+
+        pwm = pwm_probe(pdev, pdev->id, NULL);
+        if (IS_ERR(pwm))
+                return PTR_ERR(pwm);
+
+        pwm = pwm_probe(pdev, pdev->id + 2, pwm);
+        if (IS_ERR(pwm))
+                return PTR_ERR(pwm);
+
+        return 0;
+}
+
+static int __devexit pwm_remove(struct platform_device *pdev)
+{
+        struct pwm_device *pwm;
+        struct resource *r;
+
+        pwm = platform_get_drvdata(pdev);
+        if (pwm == NULL)
+                return -ENODEV;
+
+        mutex_lock(&pwm_lock);
+        list_del(&pwm->node);
+        mutex_unlock(&pwm_lock);
+
+        iounmap(pwm->mmio_base);
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(r->start, r->end - r->start + 1);
+
+        clk_put(pwm->clk);
+        kfree(pwm);
+        return 0;
+}
+
+static struct platform_driver pxa25x_pwm_driver = {
+        .driver         = {
+                .name   = "pxa25x-pwm",
+        },
+        .probe          = pxa25x_pwm_probe,
+        .remove         = __devexit_p(pwm_remove),
+};
+
+static struct platform_driver pxa27x_pwm_driver = {
+        .driver         = {
+                .name   = "pxa27x-pwm",
+        },
+        .probe          = pxa27x_pwm_probe,
+        .remove         = __devexit_p(pwm_remove),
+};
+
+static int __init pwm_init(void)
+{
+        int ret = 0;
+
+        ret = platform_driver_register(&pxa25x_pwm_driver);
+        if (ret) {
+                printk(KERN_ERR "failed to register pxa25x_pwm_driver\n");
+                return ret;
+        }
+
+        ret = platform_driver_register(&pxa27x_pwm_driver);
+        if (ret) {
+                printk(KERN_ERR "failed to register pxa27x_pwm_driver\n");
+                return ret;
+        }
+
+        return ret;
+}
+arch_initcall(pwm_init);
+
+static void __exit pwm_exit(void)
+{
+        platform_driver_unregister(&pxa25x_pwm_driver);
+        platform_driver_unregister(&pxa27x_pwm_driver);
+}
+module_exit(pwm_exit);
+
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index e5b417d14bb0..4cd50e3005e9 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -26,6 +26,7 @@
 #include <asm/hardware.h>
 #include <asm/arch/irqs.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/mfp-pxa25x.h>
 #include <asm/arch/pm.h>
 #include <asm/arch/dma.h>
@@ -117,29 +118,35 @@ static struct clk pxa25x_hwuart_clk =
         INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev)
 ;
 
+/*
+ * PXA 2xx clock declarations. Order is important (see aliases below)
+ * Please be careful not to disrupt the ordering.
+ */
 static struct clk pxa25x_clks[] = {
         INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
         INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
         INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
         INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
-        INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
+        INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa25x_device_udc.dev),
         INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
         INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
 
         INIT_CKEN("SSPCLK",  SSP, 3686400, 0, &pxa25x_device_ssp.dev),
         INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
         INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
+        INIT_CKEN("PWMCLK", PWM0, 3686400, 0, &pxa25x_device_pwm0.dev),
+        INIT_CKEN("PWMCLK", PWM1, 3686400, 0, &pxa25x_device_pwm1.dev),
 
         INIT_CKEN("AC97CLK",     AC97,     24576000, 0, NULL),
 
         /*
-        INIT_CKEN("PWMCLK",  PWM0, 3686400,  0, NULL),
-        INIT_CKEN("PWMCLK",  PWM0, 3686400,  0, NULL),
         INIT_CKEN("I2SCLK",  I2S,  14745600, 0, NULL),
         */
         INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
 };
 
+static struct clk gpio7_clk = INIT_CKOTHER("GPIO7_CK", &pxa25x_clks[4], NULL);
+
 #ifdef CONFIG_PM
 
 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
@@ -260,7 +267,7 @@ void __init pxa25x_init_irq(void)
 }
 
 static struct platform_device *pxa25x_devices[] __initdata = {
-        &pxa_device_udc,
+        &pxa25x_device_udc,
         &pxa_device_ffuart,
         &pxa_device_btuart,
         &pxa_device_stuart,
@@ -269,6 +276,8 @@ static struct platform_device *pxa25x_devices[] __initdata = {
         &pxa25x_device_ssp,
         &pxa25x_device_nssp,
         &pxa25x_device_assp,
+        &pxa25x_device_pwm0,
+        &pxa25x_device_pwm1,
 };
 
 static struct sys_device pxa25x_sysdev[] = {
@@ -311,6 +320,8 @@ static int __init pxa25x_init(void)
         if (cpu_is_pxa25x())
                 ret = platform_device_register(&pxa_device_hwuart);
 
+        clks_register(&gpio7_clk, 1);
+
         return ret;
 }
 
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 7e945836e129..d5d14ea33f27 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -146,7 +146,7 @@ static struct clk pxa27x_clks[] = {
 
         INIT_CKEN("I2SCLK",  I2S,  14682000, 0, &pxa_device_i2s.dev),
         INIT_CKEN("I2CCLK",  I2C,  32842000, 0, &pxa_device_i2c.dev),
-        INIT_CKEN("UDCCLK",  USB,  48000000, 5, &pxa_device_udc.dev),
+        INIT_CKEN("UDCCLK",  USB,  48000000, 5, &pxa27x_device_udc.dev),
         INIT_CKEN("MMCCLK",  MMC,  19500000, 0, &pxa_device_mci.dev),
         INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev),
 
@@ -157,12 +157,13 @@ static struct clk pxa27x_clks[] = {
         INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
         INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
         INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
+        INIT_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
+        INIT_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),
 
         INIT_CKEN("AC97CLK",     AC97,     24576000, 0, NULL),
         INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL),
 
         /*
-        INIT_CKEN("PWMCLK",  PWM0, 13000000, 0, NULL),
         INIT_CKEN("MSLCLK",  MSL,  48000000, 0, NULL),
         INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
         INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
@@ -349,11 +350,14 @@ struct platform_device pxa27x_device_i2c_power = {
 
 void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 {
+        local_irq_disable();
+        PCFR |= PCFR_PI2CEN;
+        local_irq_enable();
         pxa27x_device_i2c_power.dev.platform_data = info;
 }
 
 static struct platform_device *devices[] __initdata = {
-        &pxa_device_udc,
+        &pxa27x_device_udc,
         &pxa_device_ffuart,
         &pxa_device_btuart,
         &pxa_device_stuart,
@@ -363,6 +367,8 @@ static struct platform_device *devices[] __initdata = {
         &pxa27x_device_ssp1,
         &pxa27x_device_ssp2,
         &pxa27x_device_ssp3,
+        &pxa27x_device_pwm0,
+        &pxa27x_device_pwm1,
 };
 
 static struct sys_device pxa27x_sysdev[] = {
diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c
new file mode 100644
index 000000000000..d4f6415e8413
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa2xx.c
@@ -0,0 +1,46 @@
+/*
+ * linux/arch/arm/mach-pxa/pxa2xx.c
+ *
+ * code specific to pxa2xx
+ *
+ * Copyright (C) 2008 Dmitry Baryshkov
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+
+#include <asm/arch/mfp-pxa2xx.h>
+#include <asm/arch/mfp-pxa25x.h>
+#include <asm/arch/irda.h>
+
+static unsigned long pxa2xx_mfp_fir[] = {
+        GPIO46_FICP_RXD,
+        GPIO47_FICP_TXD,
+};
+
+static unsigned long pxa2xx_mfp_sir[] = {
+        GPIO46_STUART_RXD,
+        GPIO47_STUART_TXD,
+};
+
+static unsigned long pxa2xx_mfp_off[] = {
+        GPIO46_GPIO | MFP_LPM_DRIVE_LOW,
+        GPIO47_GPIO | MFP_LPM_DRIVE_LOW,
+};
+
+void pxa2xx_transceiver_mode(struct device *dev, int mode)
+{
+        if (mode & IR_OFF) {
+                pxa2xx_mfp_config(pxa2xx_mfp_off, ARRAY_SIZE(pxa2xx_mfp_off));
+        } else if (mode & IR_SIRMODE) {
+                pxa2xx_mfp_config(pxa2xx_mfp_sir, ARRAY_SIZE(pxa2xx_mfp_sir));
+        } else if (mode & IR_FIRMODE) {
+                pxa2xx_mfp_config(pxa2xx_mfp_fir, ARRAY_SIZE(pxa2xx_mfp_fir));
+        } else
+                BUG();
+}
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 644550bfa330..15685d2b8f8c 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -231,7 +231,7 @@ static struct clk pxa3xx_clks[] = {
         PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
 
         PXA3xx_CKEN("I2CCLK", I2C,  32842000, 0, &pxa_device_i2c.dev),
-        PXA3xx_CKEN("UDCCLK", UDC,  48000000, 5, &pxa_device_udc.dev),
+        PXA3xx_CKEN("UDCCLK", UDC,  48000000, 5, &pxa27x_device_udc.dev),
         PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
         PXA3xx_CKEN("KBDCLK", KEYPAD,  32768, 0, &pxa27x_device_keypad.dev),
 
@@ -239,6 +239,8 @@ static struct clk pxa3xx_clks[] = {
         PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
         PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
         PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
+        PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
+        PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),
 
         PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
         PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
@@ -520,7 +522,7 @@ void __init pxa3xx_init_irq(void)
  */
 
 static struct platform_device *devices[] __initdata = {
-        &pxa_device_udc,
+/*      &pxa_device_udc,        The UDC driver is PXA25x only */
         &pxa_device_ffuart,
         &pxa_device_btuart,
         &pxa_device_stuart,
@@ -530,6 +532,8 @@ static struct platform_device *devices[] __initdata = {
         &pxa27x_device_ssp2,
         &pxa27x_device_ssp3,
         &pxa3xx_device_ssp4,
+        &pxa27x_device_pwm0,
+        &pxa27x_device_pwm1,
 };
 
 static struct sys_device pxa3xx_sysdev[] = {
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 23f050feb208..360354084ae4 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -26,6 +26,7 @@
 #include <asm/arch/sharpsl.h>
 #include <asm/arch/spitz.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
 #include "sharpsl.h"
 
@@ -207,7 +208,9 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = {
         .read_devdata     = spitzpm_read_devdata,
         .charger_wakeup   = spitz_charger_wakeup,
         .should_wakeup    = spitz_should_wakeup,
+#ifdef CONFIG_BACKLIGHT_CORGI
         .backlight_limit  = corgibl_limit_intensity,
+#endif
         .charge_on_volt   = SHARPSL_CHARGE_ON_VOLT,
         .charge_on_temp   = SHARPSL_CHARGE_ON_TEMP,
         .charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH,
@@ -229,6 +232,10 @@ static int __devinit spitzpm_init(void)
 {
         int ret;
 
+        if (!machine_is_spitz() && !machine_is_akita()
+                        && !machine_is_borzoi())
+                return -ENODEV;
+
         spitzpm_device = platform_device_alloc("sharpsl-pm", -1);
         if (!spitzpm_device)
                 return -ENOMEM;
diff --git a/arch/arm/mach-pxa/standby.S b/arch/arm/mach-pxa/standby.S
index 167412e6bec8..40bb70eff3fe 100644
--- a/arch/arm/mach-pxa/standby.S
+++ b/arch/arm/mach-pxa/standby.S
@@ -14,6 +14,7 @@
 #include <asm/hardware.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 
                 .text
 
@@ -35,20 +36,20 @@ ENTRY(pxa_cpu_standby)
 
 #ifdef CONFIG_PXA3xx
 
-#define MDCNFG          0x0000
-#define MDCNFG_DMCEN    (1 << 30)
-#define DDR_HCAL        0x0060
-#define DDR_HCAL_HCRNG  0x1f
-#define DDR_HCAL_HCPROG (1 << 28)
-#define DDR_HCAL_HCEN   (1 << 31)
-#define DMCIER          0x0070
-#define DMCIER_EDLP     (1 << 29)
-#define DMCISR          0x0078
-#define RCOMP           0x0100
-#define RCOMP_SWEVAL    (1 << 31)
+#define PXA3_MDCNFG             0x0000
+#define PXA3_MDCNFG_DMCEN       (1 << 30)
+#define PXA3_DDR_HCAL           0x0060
+#define PXA3_DDR_HCAL_HCRNG     0x1f
+#define PXA3_DDR_HCAL_HCPROG    (1 << 28)
+#define PXA3_DDR_HCAL_HCEN      (1 << 31)
+#define PXA3_DMCIER             0x0070
+#define PXA3_DMCIER_EDLP        (1 << 29)
+#define PXA3_DMCISR             0x0078
+#define PXA3_RCOMP              0x0100
+#define PXA3_RCOMP_SWEVAL       (1 << 31)
 
 ENTRY(pm_enter_standby_start)
-        mov     r1, #0xf6000000         @ DMEMC_REG_BASE (MDCNFG)
+        mov     r1, #0xf6000000                 @ DMEMC_REG_BASE (PXA3_MDCNFG)
         add     r1, r1, #0x00100000
 
         /*
@@ -59,54 +60,54 @@ ENTRY(pm_enter_standby_start)
          * This also means that only the dynamic memory controller
          * can be reliably accessed in the code following standby.
          */
-        ldr     r2, [r1]                @ Dummy read MDCNFG
+        ldr     r2, [r1]                        @ Dummy read PXA3_MDCNFG
 
         mcr     p14, 0, r0, c7, c0, 0
         .rept   8
         nop
         .endr
 
-        ldr     r0, [r1, #DDR_HCAL]     @ Clear (and wait for) HCEN
-        bic     r0, r0, #DDR_HCAL_HCEN
-        str     r0, [r1, #DDR_HCAL]
-1:      ldr     r0, [r1, #DDR_HCAL]
-        tst     r0, #DDR_HCAL_HCEN
+        ldr     r0, [r1, #PXA3_DDR_HCAL]        @ Clear (and wait for) HCEN
+        bic     r0, r0, #PXA3_DDR_HCAL_HCEN
+        str     r0, [r1, #PXA3_DDR_HCAL]
+1:      ldr     r0, [r1, #PXA3_DDR_HCAL]
+        tst     r0, #PXA3_DDR_HCAL_HCEN
         bne     1b
 
-        ldr     r0, [r1, #RCOMP]        @ Initiate RCOMP
-        orr     r0, r0, #RCOMP_SWEVAL
-        str     r0, [r1, #RCOMP]
+        ldr     r0, [r1, #PXA3_RCOMP]           @ Initiate RCOMP
+        orr     r0, r0, #PXA3_RCOMP_SWEVAL
+        str     r0, [r1, #PXA3_RCOMP]
 
-        mov     r0, #~0                 @ Clear interrupts
-        str     r0, [r1, #DMCISR]
+        mov     r0, #~0                         @ Clear interrupts
+        str     r0, [r1, #PXA3_DMCISR]
 
-        ldr     r0, [r1, #DMCIER]       @ set DMIER[EDLP]
-        orr     r0, r0, #DMCIER_EDLP
-        str     r0, [r1, #DMCIER]
+        ldr     r0, [r1, #PXA3_DMCIER]          @ set DMIER[EDLP]
+        orr     r0, r0, #PXA3_DMCIER_EDLP
+        str     r0, [r1, #PXA3_DMCIER]
 
-        ldr     r0, [r1, #DDR_HCAL]     @ clear HCRNG, set HCPROG, HCEN
-        bic     r0, r0, #DDR_HCAL_HCRNG
-        orr     r0, r0, #DDR_HCAL_HCEN | DDR_HCAL_HCPROG
-        str     r0, [r1, #DDR_HCAL]
+        ldr     r0, [r1, #PXA3_DDR_HCAL]        @ clear HCRNG, set HCPROG, HCEN
+        bic     r0, r0, #PXA3_DDR_HCAL_HCRNG
+        orr     r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG
+        str     r0, [r1, #PXA3_DDR_HCAL]
 
-1:      ldr     r0, [r1, #DMCISR]
-        tst     r0, #DMCIER_EDLP
+1:      ldr     r0, [r1, #PXA3_DMCISR]
+        tst     r0, #PXA3_DMCIER_EDLP
         beq     1b
 
-        ldr     r0, [r1, #MDCNFG]       @ set MDCNFG[DMCEN]
-        orr     r0, r0, #MDCNFG_DMCEN
-        str     r0, [r1, #MDCNFG]
-1:      ldr     r0, [r1, #MDCNFG]
-        tst     r0, #MDCNFG_DMCEN
+        ldr     r0, [r1, #PXA3_MDCNFG]          @ set PXA3_MDCNFG[DMCEN]
+        orr     r0, r0, #PXA3_MDCNFG_DMCEN
+        str     r0, [r1, #PXA3_MDCNFG]
+1:      ldr     r0, [r1, #PXA3_MDCNFG]
+        tst     r0, #PXA3_MDCNFG_DMCEN
         beq     1b
 
-        ldr     r0, [r1, #DDR_HCAL]     @ set DDR_HCAL[HCRNG]
+        ldr     r0, [r1, #PXA3_DDR_HCAL]        @ set PXA3_DDR_HCAL[HCRNG]
         orr     r0, r0, #2 @ HCRNG
-        str     r0, [r1, #DDR_HCAL]
+        str     r0, [r1, #PXA3_DDR_HCAL]
 
-        ldr     r0, [r1, #DMCIER]       @ Clear the interrupt
+        ldr     r0, [r1, #PXA3_DMCIER]          @ Clear the interrupt
         bic     r0, r0, #0x20000000
-        str     r0, [r1, #DMCIER]
+        str     r0, [r1, #PXA3_DMCIER]
 
         mov     pc, lr
 ENTRY(pm_enter_standby_end)
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 931885d86b91..61e244023089 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -41,6 +41,7 @@
 #include <asm/mach/flash.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/trizeps4.h>
 #include <asm/arch/audio.h>
@@ -175,19 +176,10 @@ static struct platform_device uart_devices = {
         .resource       = NULL,
 };
 
-/********************************************************************************************
- * PXA270 ac97 sound codec
- ********************************************************************************************/
-static struct platform_device ac97_audio_device = {
-        .name           = "pxa2xx-ac97",
-        .id             = -1,
-};
-
 static struct platform_device * trizeps4_devices[] __initdata = {
         &flash_device,
         &uart_devices,
         &dm9000_device,
-        &ac97_audio_device,
 };
 
 #ifdef CONFIG_MACH_TRIZEPS4_CONXS
@@ -438,6 +430,7 @@ static void __init trizeps4_init(void)
         pxa_set_mci_info(&trizeps4_mci_platform_data);
         pxa_set_ficp_info(&trizeps4_ficp_platform_data);
         pxa_set_ohci_info(&trizeps4_ohci_platform_data);
+        pxa_set_ac97_info(NULL);
 }
 
 static void __init trizeps4_map_io(void)
@@ -487,6 +480,7 @@ static void __init trizeps4_map_io(void)
         ConXS_BCR = trizeps_conxs_bcr;
 #endif
 
+#warning FIXME - accessing PM registers directly is deprecated
         PWER  = 0x00000002;
         PFER  = 0x00000000;
         PRER  = 0x00000002;
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 4a0028087ea6..66b446ca273d 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -18,22 +18,24 @@
 #include <linux/interrupt.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/pwm_backlight.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/hardware.h>
+#include <asm/arch/audio.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/zylonite.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/pxa27x_keypad.h>
 
+#include "devices.h"
 #include "generic.h"
 
 #define MAX_SLOTS       3
 struct platform_mmc_slot zylonite_mmc_slot[MAX_SLOTS];
 
-int gpio_backlight;
 int gpio_eth_irq;
 
 int wm9713_irq;
@@ -62,10 +64,20 @@ static struct platform_device smc91x_device = {
 };
 
 #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static void zylonite_backlight_power(int on)
-{
-        gpio_set_value(gpio_backlight, on);
-}
+static struct platform_pwm_backlight_data zylonite_backlight_data = {
+        .pwm_id         = 3,
+        .max_brightness = 100,
+        .dft_brightness = 100,
+        .pwm_period_ns  = 10000,
+};
+
+static struct platform_device zylonite_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent = &pxa27x_device_pwm1.dev,
+                .platform_data  = &zylonite_backlight_data,
+        },
+};
 
 static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
         .pixclock               = 110000,
@@ -98,7 +110,6 @@ static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
 static struct pxafb_mach_info zylonite_toshiba_lcd_info = {
         .num_modes              = 1,
         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
-        .pxafb_backlight_power  = zylonite_backlight_power,
 };
 
 static struct pxafb_mode_info sharp_ls037_modes[] = {
@@ -134,13 +145,11 @@ static struct pxafb_mach_info zylonite_sharp_lcd_info = {
         .modes                  = sharp_ls037_modes,
         .num_modes              = 2,
         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
-        .pxafb_backlight_power  = zylonite_backlight_power,
 };
 
 static void __init zylonite_init_lcd(void)
 {
-        /* backlight GPIO: output, default on */
-        gpio_direction_output(gpio_backlight, 1);
+        platform_device_register(&zylonite_backlight_device);
 
         if (lcd_id & 0x20) {
                 set_pxa_fb_info(&zylonite_sharp_lcd_info);
@@ -329,6 +338,7 @@ static void __init zylonite_init(void)
         smc91x_resources[1].end   = gpio_to_irq(gpio_eth_irq);
         platform_device_register(&smc91x_device);
 
+        pxa_set_ac97_info(NULL);
         zylonite_init_lcd();
         zylonite_init_mmc();
         zylonite_init_keypad();
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index 324fb9daae28..6f7ae972b8db 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -50,6 +50,7 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
         GPIO75_LCD_BIAS,
         GPIO76_LCD_VSYNC,
         GPIO127_LCD_CS_N,
+        GPIO20_PWM3_OUT,        /* backlight */
 
         /* BTUART */
         GPIO111_UART2_RTS,
@@ -200,9 +201,6 @@ void __init zylonite_pxa300_init(void)
                 /* detect LCD panel */
                 zylonite_detect_lcd_panel();
 
-                /* GPIO pin assignment */
-                gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO20);
-
                 /* MMC card detect & write protect for controller 0 */
                 zylonite_mmc_slot[0].gpio_cd  = EXT_GPIO(0);
                 zylonite_mmc_slot[0].gpio_wp  = EXT_GPIO(2);
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
index 193d07903b06..2b4fc34919ac 100644
--- a/arch/arm/mach-pxa/zylonite_pxa320.c
+++ b/arch/arm/mach-pxa/zylonite_pxa320.c
@@ -49,6 +49,7 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
         GPIO15_2_LCD_LCLK,
         GPIO16_2_LCD_PCLK,
         GPIO17_2_LCD_BIAS,
+        GPIO14_PWM3_OUT,        /* backlight */
 
         /* FFUART */
         GPIO41_UART1_RXD | MFP_LPM_EDGE_FALL,
@@ -187,7 +188,6 @@ void __init zylonite_pxa320_init(void)
                 zylonite_detect_lcd_panel();
 
                 /* GPIO pin assignment */
-                gpio_backlight  = mfp_to_gpio(MFP_PIN_GPIO14);
                 gpio_eth_irq    = mfp_to_gpio(MFP_PIN_GPIO9);
 
                 /* MMC card detect & write protect for controller 0 */
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index cd3dc0834b3b..99fdc736698c 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -37,6 +37,17 @@ config S3C2410_CLOCK
         help
           Clock code for the S3C2410, and similar processors
 
+config SIMTEC_NOR
+        bool
+        help
+          Internal node to specify machine has simtec NOR mapping
+
+config MACH_BAST_IDE
+        bool
+        select HAVE_PATA_PLATFORM
+        help
+          Internal node for machines with an BAST style IDE
+          interface
 
 menu "S3C2410 Machines"
 
@@ -61,15 +72,18 @@ config PM_H1940
           Internal node for H1940 and related PM
 
 config MACH_N30
-        bool "Acer N30"
+        bool "Acer N30 family"
         select CPU_S3C2410
         help
-          Say Y here if you are using the Acer N30
+          Say Y here if you want suppt for the Acer N30, Acer N35,
+          Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
 
 config ARCH_BAST
         bool "Simtec Electronics BAST (EB2410ITX)"
         select CPU_S3C2410
         select PM_SIMTEC if PM
+        select SIMTEC_NOR
+        select MACH_BAST_IDE
         select ISA
         help
           Say Y here if you are using the Simtec Electronics EB2410ITX
@@ -107,6 +121,8 @@ config MACH_TCT_HAMMER
 config MACH_VR1000
         bool "Thorcom VR1000"
         select PM_SIMTEC if PM
+        select SIMTEC_NOR
+        select MACH_BAST_IDE
         select CPU_S3C2410
         help
           Say Y here if you are using the Thorcom VR1000 board.
@@ -118,4 +134,3 @@ config MACH_QT2410
            Say Y here if you are using the Armzone QT2410
 
 endmenu
-
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index cabc13ce09e4..00f31f8c4e78 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -30,3 +30,11 @@ obj-$(CONFIG_BAST_PC104_IRQ)	+= bast-irq.o
 obj-$(CONFIG_MACH_TCT_HAMMER)   += mach-tct_hammer.o
 obj-$(CONFIG_MACH_VR1000)       += mach-vr1000.o usb-simtec.o
 obj-$(CONFIG_MACH_QT2410)       += mach-qt2410.o
+
+# Common bits of machine support
+
+obj-$(CONFIG_SIMTEC_NOR)        += nor-simtec.o
+
+# machine additions
+
+obj-$(CONFIG_MACH_BAST_IDE)     += bast-ide.o
diff --git a/arch/arm/mach-s3c2410/bast-ide.c b/arch/arm/mach-s3c2410/bast-ide.c
new file mode 100644
index 000000000000..df95fe37cdc8
--- /dev/null
+++ b/arch/arm/mach-s3c2410/bast-ide.c
@@ -0,0 +1,112 @@
+/* linux/arch/arm/mach-s3c2410/bast-ide.c
+ *
+ * Copyright 2007 Simtec Electronics
+ *      http://www.simtec.co.uk/products/EB2410ITX/
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+
+#include <asm/mach-types.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/map.h>
+#include <asm/arch/bast-map.h>
+#include <asm/arch/bast-irq.h>
+
+/* IDE ports */
+
+static struct pata_platform_info bast_ide_platdata = {
+        .ioport_shift   = 5,
+};
+
+#define IDE_CS  S3C2410_CS5
+
+static struct resource bast_ide0_resource[] = {
+        [0]     = {
+                .start  = IDE_CS + BAST_PA_IDEPRI,
+                .end    = IDE_CS + BAST_PA_IDEPRI + (8 * 0x20) - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1]     = {
+                .start  = IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20) ,
+                .end    = IDE_CS + BAST_PA_IDEPRIAUX + (7 * 0x20) - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2]     = {
+                .start  = IRQ_IDE0,
+                .end    = IRQ_IDE0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device bast_device_ide0 = {
+        .name           = "pata_platform",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(bast_ide0_resource),
+        .resource       = bast_ide0_resource,
+        .dev            = {
+                .platform_data = &bast_ide_platdata,
+                .coherent_dma_mask = ~0,
+        }
+
+};
+
+static struct resource bast_ide1_resource[] = {
+        [0]     = {
+                .start  = IDE_CS + BAST_PA_IDESEC,
+                .end    = IDE_CS + BAST_PA_IDESEC + (8 * 0x20) - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1]     = {
+                .start  = IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20),
+                .end    = IDE_CS + BAST_PA_IDESECAUX + (7 * 0x20) - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2]     = {
+                .start  = IRQ_IDE1,
+                .end    = IRQ_IDE1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device bast_device_ide1 = {
+        .name           = "pata_platform",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(bast_ide1_resource),
+        .resource       = bast_ide1_resource,
+        .dev            = {
+                .platform_data = &bast_ide_platdata,
+                .coherent_dma_mask = ~0,
+        }
+};
+
+static struct platform_device *bast_ide_devices[] __initdata = {
+        &bast_device_ide0,
+        &bast_device_ide1,
+};
+
+static __init int bast_ide_init(void)
+{
+        if (machine_is_bast() || machine_is_vr1000())
+                return platform_add_devices(bast_ide_devices,
+                                            ARRAY_SIZE(bast_ide_devices));
+
+        return 0;
+}
+
+fs_initcall(bast_ide_init);
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 27f63d5d3a7b..965f27129707 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2410/mach-bast.c
  *
- * Copyright (c) 2003-2005 Simtec Electronics
+ * Copyright (c) 2003-2005,2008 Simtec Electronics
  *   Ben Dooks <ben@simtec.co.uk>
  *
  * http://www.simtec.co.uk/products/EB2410ITX/
@@ -20,6 +20,8 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/dm9000.h>
+#include <linux/ata_platform.h>
+#include <linux/i2c.h>
 
 #include <net/ax88796.h>
 
@@ -56,7 +58,9 @@
 #include <asm/plat-s3c24xx/clock.h>
 #include <asm/plat-s3c24xx/devs.h>
 #include <asm/plat-s3c24xx/cpu.h>
+
 #include "usb-simtec.h"
+#include "nor-simtec.h"
 
 #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
 
@@ -134,37 +138,21 @@ static struct map_desc bast_iodesc[] __initdata = {
   { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
   { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
   { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
-  { VA_C2(BAST_VA_IDEPRI),  PA_CS3(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
-  { VA_C2(BAST_VA_IDESEC),  PA_CS3(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
-  { VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
-  { VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
 
   /* slow, word */
   { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
   { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
   { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
-  { VA_C3(BAST_VA_IDEPRI),  PA_CS3(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
-  { VA_C3(BAST_VA_IDESEC),  PA_CS3(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
-  { VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
-  { VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
 
   /* fast, byte */
   { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
   { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
   { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
-  { VA_C4(BAST_VA_IDEPRI),  PA_CS5(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
-  { VA_C4(BAST_VA_IDESEC),  PA_CS5(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
-  { VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
-  { VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
 
   /* fast, word */
   { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
   { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
   { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
-  { VA_C5(BAST_VA_IDEPRI),  PA_CS5(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
-  { VA_C5(BAST_VA_IDESEC),  PA_CS5(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
-  { VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
-  { VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
 };
 
 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
@@ -218,23 +206,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
         }
 };
 
-/* NOR Flash on BAST board */
-
-static struct resource bast_nor_resource[] = {
-        [0] = {
-                .start = S3C2410_CS1 + 0x4000000,
-                .end   = S3C2410_CS1 + 0x4000000 + (32*1024*1024) - 1,
-                .flags = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device bast_device_nor = {
-        .name           = "bast-nor",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(bast_nor_resource),
-        .resource       = bast_nor_resource,
-};
-
 /* NAND Flash on BAST board */
 
 #ifdef CONFIG_PM
@@ -374,7 +345,7 @@ static struct resource bast_dm9k_resource[] = {
         [2] = {
                 .start = IRQ_DM9000,
                 .end   = IRQ_DM9000,
-                .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
         }
 
 };
@@ -564,6 +535,18 @@ static struct s3c2410fb_mach_info __initdata bast_fb_info = {
         .default_display = 1,
 };
 
+/* I2C devices fitted. */
+
+static struct i2c_board_info bast_i2c_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        }, {
+                I2C_BOARD_INFO("simtec-pmu", 0x6b),
+        }, {
+                I2C_BOARD_INFO("ch7013", 0x75),
+        },
+};
+
 /* Standard BAST devices */
 
 static struct platform_device *bast_devices[] __initdata = {
@@ -573,7 +556,6 @@ static struct platform_device *bast_devices[] __initdata = {
         &s3c_device_i2c,
         &s3c_device_rtc,
         &s3c_device_nand,
-        &bast_device_nor,
         &bast_device_dm9k,
         &bast_device_asix,
         &bast_device_axpp,
@@ -622,6 +604,11 @@ static void __init bast_init(void)
 
         s3c24xx_fb_set_platdata(&bast_fb_info);
         platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
+
+        i2c_register_board_info(0, bast_i2c_devs,
+                                ARRAY_SIZE(bast_i2c_devs));
+
+        nor_simtec_init();
 }
 
 MACHINE_START(BAST, "Simtec-BAST")
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 621f548da610..43c2e915c5bf 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -1,9 +1,10 @@
-/* linux/arch/arm/mach-s3c2410/mach-n30.c
+/* Machine specific code for the Acer n30, Acer N35, Navman PiN 570,
+ * Yakumo AlphaX and Airis NC05 PDAs.
  *
  * Copyright (c) 2003-2005 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *
- * Copyright (c) 2005 Christer Weinigel <christer@weinigel.se>
+ * Copyright (c) 2005-2008 Christer Weinigel <christer@weinigel.se>
  *
  * There is a wiki with more information about the n30 port at
  * http://handhelds.org/moin/moin.cgi/AcerN30Documentation .
@@ -11,36 +12,42 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
-*/
+ */
 
 #include <linux/kernel.h>
 #include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
+
 #include <linux/delay.h>
-#include <linux/serial_core.h>
+#include <linux/gpio_keys.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
 #include <linux/platform_device.h>
-#include <linux/kthread.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
+#include <linux/serial_core.h>
+#include <linux/timer.h>
 
 #include <asm/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/plat-s3c/regs-serial.h>
+#include <asm/arch/fb.h>
+#include <asm/arch/leds-gpio.h>
 #include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-lcd.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/map.h>
+
 #include <asm/plat-s3c/iic.h>
+#include <asm/plat-s3c/regs-serial.h>
 
-#include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/clock.h>
-#include <asm/plat-s3c24xx/devs.h>
 #include <asm/plat-s3c24xx/cpu.h>
+#include <asm/plat-s3c24xx/devs.h>
+#include <asm/plat-s3c24xx/s3c2410.h>
+#include <asm/plat-s3c24xx/udc.h>
 
 static struct map_desc n30_iodesc[] __initdata = {
         /* nothing here yet */
@@ -64,7 +71,8 @@ static struct s3c2410_uartcfg n30_uartcfgs[] = {
                 .ulcon       = 0x43,
                 .ufcon       = 0x51,
         },
-        /* The BlueTooth controller is connected to port 2 */
+        /* On the N30 the bluetooth controller is connected here.
+         * On the N35 and variants the GPS receiver is connected here. */
         [2] = {
                 .hwport      = 2,
                 .flags       = 0,
@@ -74,13 +82,260 @@ static struct s3c2410_uartcfg n30_uartcfgs[] = {
         },
 };
 
+static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
+{
+        switch (cmd) {
+        case S3C2410_UDC_P_ENABLE :
+                s3c2410_gpio_setpin(S3C2410_GPB3, 1);
+                break;
+        case S3C2410_UDC_P_DISABLE :
+                s3c2410_gpio_setpin(S3C2410_GPB3, 0);
+                break;
+        case S3C2410_UDC_P_RESET :
+                break;
+        default:
+                break;
+        }
+}
+
+static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = {
+        .udc_command            = n30_udc_pullup,
+        .vbus_pin               = S3C2410_GPG1,
+        .vbus_pin_inverted      = 0,
+};
+
+static struct gpio_keys_button n30_buttons[] = {
+        {
+                .gpio           = S3C2410_GPF0,
+                .code           = KEY_POWER,
+                .desc           = "Power",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG9,
+                .code           = KEY_UP,
+                .desc           = "Thumbwheel Up",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG8,
+                .code           = KEY_DOWN,
+                .desc           = "Thumbwheel Down",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG7,
+                .code           = KEY_ENTER,
+                .desc           = "Thumbwheel Press",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF7,
+                .code           = KEY_HOMEPAGE,
+                .desc           = "Home",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF6,
+                .code           = KEY_CALENDAR,
+                .desc           = "Calendar",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF5,
+                .code           = KEY_ADDRESSBOOK,
+                .desc           = "Contacts",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF4,
+                .code           = KEY_MAIL,
+                .desc           = "Mail",
+                .active_low     = 0,
+        },
+};
+
+static struct gpio_keys_platform_data n30_button_data = {
+        .buttons        = n30_buttons,
+        .nbuttons       = ARRAY_SIZE(n30_buttons),
+};
+
+static struct platform_device n30_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &n30_button_data,
+        }
+};
+
+static struct gpio_keys_button n35_buttons[] = {
+        {
+                .gpio           = S3C2410_GPF0,
+                .code           = KEY_POWER,
+                .desc           = "Power",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG9,
+                .code           = KEY_UP,
+                .desc           = "Joystick Up",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG8,
+                .code           = KEY_DOWN,
+                .desc           = "Joystick Down",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG6,
+                .code           = KEY_DOWN,
+                .desc           = "Joystick Left",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG5,
+                .code           = KEY_DOWN,
+                .desc           = "Joystick Right",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG7,
+                .code           = KEY_ENTER,
+                .desc           = "Joystick Press",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF7,
+                .code           = KEY_HOMEPAGE,
+                .desc           = "Home",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF6,
+                .code           = KEY_CALENDAR,
+                .desc           = "Calendar",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF5,
+                .code           = KEY_ADDRESSBOOK,
+                .desc           = "Contacts",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF4,
+                .code           = KEY_MAIL,
+                .desc           = "Mail",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPF3,
+                .code           = SW_RADIO,
+                .desc           = "GPS Antenna",
+                .active_low     = 0,
+        },
+        {
+                .gpio           = S3C2410_GPG2,
+                .code           = SW_HEADPHONE_INSERT,
+                .desc           = "Headphone",
+                .active_low     = 0,
+        },
+};
+
+static struct gpio_keys_platform_data n35_button_data = {
+        .buttons        = n35_buttons,
+        .nbuttons       = ARRAY_SIZE(n35_buttons),
+};
+
+static struct platform_device n35_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &n35_button_data,
+        }
+};
+
+/* This is the bluetooth LED on the device. */
+static struct s3c24xx_led_platdata n30_blue_led_pdata = {
+        .name           = "blue_led",
+        .gpio           = S3C2410_GPG6,
+        .def_trigger    = "",
+};
+
+/* This LED is driven by the battery microcontroller, and is blinking
+ * red, blinking green or solid green when the battery is low,
+ * charging or full respectively.  By driving GPD9 low, it's possible
+ * to force the LED to blink red, so call that warning LED.  */
+static struct s3c24xx_led_platdata n30_warning_led_pdata = {
+        .name           = "warning_led",
+        .flags          = S3C24XX_LEDF_ACTLOW,
+        .gpio           = S3C2410_GPD9,
+        .def_trigger    = "",
+};
+
+static struct platform_device n30_blue_led = {
+        .name           = "s3c24xx_led",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &n30_blue_led_pdata,
+        },
+};
+
+static struct platform_device n30_warning_led = {
+        .name           = "s3c24xx_led",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &n30_warning_led_pdata,
+        },
+};
+
+static struct s3c2410fb_display n30_display __initdata = {
+        .type           = S3C2410_LCDCON1_TFT,
+        .width          = 240,
+        .height         = 320,
+        .pixclock       = 170000,
+
+        .xres           = 240,
+        .yres           = 320,
+        .bpp            = 16,
+        .left_margin    = 3,
+        .right_margin   = 40,
+        .hsync_len      = 40,
+        .upper_margin   = 2,
+        .lower_margin   = 3,
+        .vsync_len      = 2,
+
+        .lcdcon5 = S3C2410_LCDCON5_INVVLINE | S3C2410_LCDCON5_INVVFRAME,
+};
+
+static struct s3c2410fb_mach_info n30_fb_info __initdata = {
+        .displays       = &n30_display,
+        .num_displays   = 1,
+        .default_display = 0,
+        .lpcsel         = 0x06,
+};
+
 static struct platform_device *n30_devices[] __initdata = {
+        &s3c_device_lcd,
+        &s3c_device_wdt,
+        &s3c_device_i2c,
+        &s3c_device_iis,
         &s3c_device_usb,
+        &s3c_device_usbgadget,
+        &n30_button_device,
+        &n30_blue_led,
+        &n30_warning_led,
+};
+
+static struct platform_device *n35_devices[] __initdata = {
         &s3c_device_lcd,
         &s3c_device_wdt,
         &s3c_device_i2c,
         &s3c_device_iis,
         &s3c_device_usbgadget,
+        &n35_button_device,
 };
 
 static struct s3c2410_platform_i2c n30_i2ccfg = {
@@ -90,9 +345,148 @@ static struct s3c2410_platform_i2c n30_i2ccfg = {
         .max_freq       = 10*1000,
 };
 
+/* Lots of hardcoded stuff, but it sets up the hardware in a useful
+ * state so that we can boot Linux directly from flash. */
+static void __init n30_hwinit(void)
+{
+        /* GPA0-11 special functions -- unknown what they do
+         * GPA12 N30 special function -- unknown what it does
+         *       N35/PiN output -- unknown what it does
+         *
+         * A12 is nGCS1 on the N30 and an output on the N35/PiN.  I
+         * don't think it does anything useful on the N30, so I ought
+         * to make it an output there too since it always driven to 0
+         * as far as I can tell. */
+        if (machine_is_n30())
+                __raw_writel(0x007fffff, S3C2410_GPACON);
+        if (machine_is_n35())
+                __raw_writel(0x007fefff, S3C2410_GPACON);
+        __raw_writel(0x00000000, S3C2410_GPADAT);
+
+        /* GPB0 TOUT0 backlight level
+         * GPB1 output 1=backlight on
+         * GPB2 output IrDA enable 0=transceiver enabled, 1=disabled
+         * GPB3 output USB D+ pull up 0=disabled, 1=enabled
+         * GPB4 N30 output -- unknown function
+         *      N30/PiN GPS control 0=GPS enabled, 1=GPS disabled
+         * GPB5 output -- unknown function
+         * GPB6 input -- unknown function
+         * GPB7 output -- unknown function
+         * GPB8 output -- probably LCD driver enable
+         * GPB9 output -- probably LCD VSYNC driver enable
+         * GPB10 output -- probably LCD HSYNC driver enable
+         */
+        __raw_writel(0x00154556, S3C2410_GPBCON);
+        __raw_writel(0x00000750, S3C2410_GPBDAT);
+        __raw_writel(0x00000073, S3C2410_GPBUP);
+
+        /* GPC0 input RS232 DCD/DSR/RI
+         * GPC1 LCD
+         * GPC2 output RS232 DTR?
+         * GPC3 input RS232 DCD/DSR/RI
+         * GPC4 LCD
+         * GPC5 output 0=NAND write enabled, 1=NAND write protect
+         * GPC6 input -- unknown function
+         * GPC7 input charger status 0=charger connected
+         *      this input can be triggered by power on the USB device
+         *      port too, but will go back to disconnected soon after.
+         * GPC8 N30/N35 output -- unknown function, always driven to 1
+         *      PiN input -- unknown function, always read as 1
+         *      Make it an input with a pull up for all models.
+         * GPC9-15 LCD
+         */
+        __raw_writel(0xaaa80618, S3C2410_GPCCON);
+        __raw_writel(0x0000014c, S3C2410_GPCDAT);
+        __raw_writel(0x0000fef2, S3C2410_GPCUP);
+
+        /* GPD0 input -- unknown function
+         * GPD1-D7 LCD
+         * GPD8 N30 output -- unknown function
+         *      N35/PiN output 1=GPS LED on
+         * GPD9 output 0=power led blinks red, 1=normal power led function
+         * GPD10 output -- unknown function
+         * GPD11-15 LCD drivers
+         */
+        __raw_writel(0xaa95aaa4, S3C2410_GPDCON);
+        __raw_writel(0x00000601, S3C2410_GPDDAT);
+        __raw_writel(0x0000fbfe, S3C2410_GPDUP);
+
+        /* GPE0-4 I2S audio bus
+         * GPE5-10 SD/MMC bus
+         * E11-13 outputs -- unknown function, probably power management
+         * E14-15 I2C bus connected to the battery controller
+         */
+        __raw_writel(0xa56aaaaa, S3C2410_GPECON);
+        __raw_writel(0x0000efc5, S3C2410_GPEDAT);
+        __raw_writel(0x0000f81f, S3C2410_GPEUP);
+
+        /* GPF0  input 0=power button pressed
+         * GPF1  input SD/MMC switch 0=card present
+         * GPF2  N30 1=reset button pressed (inverted compared to the rest)
+         *       N35/PiN 0=reset button pressed
+         * GPF3  N30/PiN input -- unknown function
+         *       N35 input GPS antenna position, 0=antenna closed, 1=open
+         * GPF4  input 0=button 4 pressed
+         * GPF5  input 0=button 3 pressed
+         * GPF6  input 0=button 2 pressed
+         * GPF7  input 0=button 1 pressed
+         */
+        __raw_writel(0x0000aaaa, S3C2410_GPFCON);
+        __raw_writel(0x00000000, S3C2410_GPFDAT);
+        __raw_writel(0x000000ff, S3C2410_GPFUP);
+
+        /* GPG0  input RS232 DCD/DSR/RI
+         * GPG1  input 1=USB gadget port has power from a host
+         * GPG2  N30 input -- unknown function
+         *       N35/PiN input 0=headphones plugged in, 1=not plugged in
+         * GPG3  N30 output -- unknown function
+         *       N35/PiN input with unknown function
+         * GPG4  N30 output 0=MMC enabled, 1=MMC disabled
+         * GPG5  N30 output 0=BlueTooth chip disabled, 1=enabled
+         *       N35/PiN input joystick right
+         * GPG6  N30 output 0=blue led on, 1=off
+         *       N35/PiN input joystick left
+         * GPG7  input 0=thumbwheel pressed
+         * GPG8  input 0=thumbwheel down
+         * GPG9  input 0=thumbwheel up
+         * GPG10 input SD/MMC write protect switch
+         * GPG11 N30 input -- unknown function
+         *       N35 output 0=GPS antenna powered, 1=not powered
+         *       PiN output -- unknown function
+         * GPG12-15 touch screen functions
+         *
+         * The pullups differ between the models, so enable all
+         * pullups that are enabled on any of the models.
+         */
+        if (machine_is_n30())
+                __raw_writel(0xff0a956a, S3C2410_GPGCON);
+        if (machine_is_n35())
+                __raw_writel(0xff4aa92a, S3C2410_GPGCON);
+        __raw_writel(0x0000e800, S3C2410_GPGDAT);
+        __raw_writel(0x0000f86f, S3C2410_GPGUP);
+
+        /* GPH0/1/2/3 RS232 serial port
+         * GPH4/5 IrDA serial port
+         * GPH6/7  N30 BlueTooth serial port
+         *         N35/PiN GPS receiver
+         * GPH8 input -- unknown function
+         * GPH9 CLKOUT0 HCLK -- unknown use
+         * GPH10 CLKOUT1 FCLK -- unknown use
+         *
+         * The pull ups for H6/H7 are enabled on N30 but not on the
+         * N35/PiN.  I suppose is useful for a budget model of the N30
+         * with no bluetooh.  It doesn't hurt to have the pull ups
+         * enabled on the N35, so leave them enabled for all models.
+         */
+        __raw_writel(0x0028aaaa, S3C2410_GPHCON);
+        __raw_writel(0x000005ef, S3C2410_GPHDAT);
+        __raw_writel(0x0000063f, S3C2410_GPHUP);
+}
+
 static void __init n30_map_io(void)
 {
         s3c24xx_init_io(n30_iodesc, ARRAY_SIZE(n30_iodesc));
+        n30_hwinit();
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
 }
@@ -106,7 +500,9 @@ static void __init n30_init_irq(void)
 
 static void __init n30_init(void)
 {
+        s3c24xx_fb_set_platdata(&n30_fb_info);
         s3c_device_i2c.dev.platform_data = &n30_i2ccfg;
+        s3c24xx_udc_set_platdata(&n30_udc_cfg);
 
         /* Turn off suspend on both USB ports, and switch the
          * selectable USB port to USB device mode. */
@@ -115,7 +511,32 @@ static void __init n30_init(void)
                               S3C2410_MISCCR_USBSUSPND0 |
                               S3C2410_MISCCR_USBSUSPND1, 0x0);
 
-        platform_add_devices(n30_devices, ARRAY_SIZE(n30_devices));
+        if (machine_is_n30()) {
+                /* Turn off suspend on both USB ports, and switch the
+                 * selectable USB port to USB device mode. */
+                s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
+                                      S3C2410_MISCCR_USBSUSPND0 |
+                                      S3C2410_MISCCR_USBSUSPND1, 0x0);
+
+                platform_add_devices(n30_devices, ARRAY_SIZE(n30_devices));
+        }
+
+        if (machine_is_n35()) {
+                /* Turn off suspend and switch the selectable USB port
+                 * to USB device mode.  Turn on suspend for the host
+                 * port since it is not connected on the N35.
+                 *
+                 * Actually, the host port is available at some pads
+                 * on the back of the device, so it would actually be
+                 * possible to add a USB device inside the N35 if you
+                 * are willing to do some hardware modifications. */
+                s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
+                                      S3C2410_MISCCR_USBSUSPND0 |
+                                      S3C2410_MISCCR_USBSUSPND1,
+                                      S3C2410_MISCCR_USBSUSPND1);
+
+                platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices));
+        }
 }
 
 MACHINE_START(N30, "Acer-N30")
@@ -131,9 +552,14 @@ MACHINE_START(N30, "Acer-N30")
         .map_io         = n30_map_io,
 MACHINE_END
 
-/*
-    Local variables:
-        compile-command: "make ARCH=arm CROSS_COMPILE=/usr/local/arm/3.3.2/bin/arm-linux- -k -C ../../.."
-        c-basic-offset: 8
-    End:
-*/
+MACHINE_START(N35, "Acer-N35")
+        /* Maintainer: Christer Weinigel <christer@weinigel.se>
+        */
+        .phys_io        = S3C2410_PA_UART,
+        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .timer          = &s3c24xx_timer,
+        .init_machine   = n30_init,
+        .init_irq       = n30_init_irq,
+        .map_io         = n30_map_io,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 4c4b5c4207c4..9a0965ac5e11 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2410/mach-vr1000.c
  *
- * Copyright (c) 2003-2005 Simtec Electronics
+ * Copyright (c) 2003-2005,2008 Simtec Electronics
  *   Ben Dooks <ben@simtec.co.uk>
  *
  * Machine support for Thorcom VR1000 board. Designed for Thorcom by
@@ -19,6 +19,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/dm9000.h>
+#include <linux/i2c.h>
 
 #include <linux/serial.h>
 #include <linux/tty.h>
@@ -46,7 +47,9 @@
 #include <asm/plat-s3c24xx/clock.h>
 #include <asm/plat-s3c24xx/devs.h>
 #include <asm/plat-s3c24xx/cpu.h>
+
 #include "usb-simtec.h"
+#include "nor-simtec.h"
 
 /* macros for virtual address mods for the io space entries */
 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
@@ -97,34 +100,6 @@ static struct map_desc vr1000_iodesc[] __initdata = {
           .length       = SZ_1M,
           .type         = MT_DEVICE,
   },
-
-  /* peripheral space... one for each of fast/slow/byte/16bit */
-  /* note, ide is only decoded in word space, even though some registers
-   * are only 8bit */
-
-  /* slow, byte */
-  { VA_C2(VR1000_VA_IDEPRI),  PA_CS3(VR1000_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
-  { VA_C2(VR1000_VA_IDESEC),  PA_CS3(VR1000_PA_IDESEC),   SZ_1M,  MT_DEVICE },
-  { VA_C2(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
-  { VA_C2(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
-
-  /* slow, word */
-  { VA_C3(VR1000_VA_IDEPRI),  PA_CS3(VR1000_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
-  { VA_C3(VR1000_VA_IDESEC),  PA_CS3(VR1000_PA_IDESEC),   SZ_1M,  MT_DEVICE },
-  { VA_C3(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
-  { VA_C3(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
-
-  /* fast, byte */
-  { VA_C4(VR1000_VA_IDEPRI),  PA_CS5(VR1000_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
-  { VA_C4(VR1000_VA_IDESEC),  PA_CS5(VR1000_PA_IDESEC),   SZ_1M,  MT_DEVICE },
-  { VA_C4(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
-  { VA_C4(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
-
-  /* fast, word */
-  { VA_C5(VR1000_VA_IDEPRI),  PA_CS5(VR1000_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
-  { VA_C5(VR1000_VA_IDESEC),  PA_CS5(VR1000_PA_IDESEC),   SZ_1M,  MT_DEVICE },
-  { VA_C5(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
-  { VA_C5(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
 };
 
 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
@@ -230,23 +205,6 @@ static struct platform_device serial_device = {
         },
 };
 
-/* MTD NOR Flash */
-
-static struct resource vr1000_nor_resource[] = {
-        [0] = {
-                .start  = S3C2410_CS1 + 0x4000000,
-                .end    = S3C2410_CS1 + 0x4000000 + SZ_16M - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device vr1000_nor = {
-        .name           = "bast-nor",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(vr1000_nor_resource),
-        .resource       = vr1000_nor_resource,
-};
-
 /* DM9000 ethernet devices */
 
 static struct resource vr1000_dm9k0_resource[] = {
@@ -263,7 +221,7 @@ static struct resource vr1000_dm9k0_resource[] = {
         [2] = {
                 .start = IRQ_VR1000_DM9000A,
                 .end   = IRQ_VR1000_DM9000A,
-                .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
         }
 
 };
@@ -282,7 +240,7 @@ static struct resource vr1000_dm9k1_resource[] = {
         [2] = {
                 .start = IRQ_VR1000_DM9000N,
                 .end   = IRQ_VR1000_DM9000N,
-                .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
         }
 };
 
@@ -358,6 +316,18 @@ static struct platform_device vr1000_led3 = {
         },
 };
 
+/* I2C devices. */
+
+static struct i2c_board_info vr1000_i2c_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        }, {
+                I2C_BOARD_INFO("tmp101", 0x48),
+        }, {
+                I2C_BOARD_INFO("m41st87", 0x68),
+        },
+};
+
 /* devices for this board */
 
 static struct platform_device *vr1000_devices[] __initdata = {
@@ -367,7 +337,6 @@ static struct platform_device *vr1000_devices[] __initdata = {
         &s3c_device_i2c,
         &s3c_device_adc,
         &serial_device,
-        &vr1000_nor,
         &vr1000_dm9k0,
         &vr1000_dm9k1,
         &vr1000_led1,
@@ -416,6 +385,11 @@ static void __init vr1000_map_io(void)
 static void __init vr1000_init(void)
 {
         platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices));
+
+        i2c_register_board_info(0, vr1000_i2c_devs,
+                                ARRAY_SIZE(vr1000_i2c_devs));
+
+        nor_simtec_init();
 }
 
 MACHINE_START(VR1000, "Thorcom-VR1000")
diff --git a/arch/arm/mach-s3c2410/nor-simtec.c b/arch/arm/mach-s3c2410/nor-simtec.c
new file mode 100644
index 000000000000..f44e21b9c3ba
--- /dev/null
+++ b/arch/arm/mach-s3c2410/nor-simtec.c
@@ -0,0 +1,86 @@
+/* linux/arch/arm/mach-s3c2410/nor-simtec.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Simtec NOR mapping
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/map.h>
+#include <asm/arch/bast-map.h>
+#include <asm/arch/bast-cpld.h>
+
+
+static void simtec_nor_vpp(struct map_info *map, int vpp)
+{
+        unsigned int val;
+        unsigned long flags;
+
+        local_irq_save(flags);
+        val = __raw_readb(BAST_VA_CTRL3);
+
+        printk(KERN_DEBUG "%s(%d)\n", __func__, vpp);
+
+        if (vpp)
+                val |= BAST_CPLD_CTRL3_ROMWEN;
+        else
+                val &= ~BAST_CPLD_CTRL3_ROMWEN;
+
+        __raw_writeb(val, BAST_VA_CTRL3);
+        local_irq_restore(flags);
+}
+
+struct physmap_flash_data simtec_nor_pdata = {
+        .width          = 2,
+        .set_vpp        = simtec_nor_vpp,
+        .nr_parts       = 0,
+};
+
+static struct resource simtec_nor_resource[] = {
+        [0] = {
+                .start = S3C2410_CS1 + 0x4000000,
+                .end   = S3C2410_CS1 + 0x4000000 + SZ_8M - 1,
+                .flags = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device simtec_device_nor = {
+        .name           = "physmap-flash",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(simtec_nor_resource),
+        .resource       = simtec_nor_resource,
+        .dev            = {
+                .platform_data = &simtec_nor_pdata,
+        },
+};
+
+void __init nor_simtec_init(void)
+{
+        int ret;
+
+        ret = platform_device_register(&simtec_device_nor);
+        if (ret < 0)
+                printk(KERN_ERR "failed to register physmap-flash device\n");
+        else
+                simtec_nor_vpp(NULL, 1);
+}
diff --git a/arch/arm/mach-s3c2410/nor-simtec.h b/arch/arm/mach-s3c2410/nor-simtec.h
new file mode 100644
index 000000000000..f619c1e0d0c8
--- /dev/null
+++ b/arch/arm/mach-s3c2410/nor-simtec.h
@@ -0,0 +1,14 @@
+/* linux/arch/arm/mach-s3c2410/nor-simtec.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Simtec NOR mapping
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+extern void nor_simtec_init(void);
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index 0b43431d4b75..c59a9d2ee9a6 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -34,6 +34,16 @@ config S3C2412_PM
 
 menu "S3C2412 Machines"
 
+config MACH_JIVE
+        bool "Logitech Jive"
+        select CPU_S3C2412
+        help
+          Say Y here if you are using the Logitech Jive.
+
+config MACH_JIVE_SHOW_BOOTLOADER
+        bool "Allow access to bootloader partitions in MTD"
+        depends on MACH_JIVE && EXPERIMENTAL
+
 config MACH_SMDK2413
         bool "SMDK2413"
         select CPU_S3C2412
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 267f3348301e..20918d5dc6a9 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_S3C2412_PM)	+= pm.o sleep.o
 
 # Machine support
 
+obj-$(CONFIG_MACH_JIVE)         += mach-jive.o
 obj-$(CONFIG_MACH_SMDK2413)     += mach-smdk2413.o
 obj-$(CONFIG_MACH_VSTMS)        += mach-vstms.o
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 2697a65ba727..1157b5a16263 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -631,6 +631,17 @@ static struct clk_init clks_src[] __initdata = {
                 .bit    = S3C2412_CLKSRC_USBCLK_HCLK,
                 .src_0  = &clk_usysclk,
                 .src_1  = &clk_h,
+        /* here we assume  OM[4] select xtal */
+        }, {
+                .clk    = &clk_erefclk,
+                .bit    = S3C2412_CLKSRC_EREFCLK_EXTCLK,
+                .src_0  = &clk_xtal,
+                .src_1  = &clk_ext,
+        }, {
+                .clk    = &clk_urefclk,
+                .bit    = S3C2412_CLKSRC_UREFCLK_EXTCLK,
+                .src_0  = &clk_xtal,
+                .src_1  = &clk_ext,
         },
 };
 
@@ -666,8 +677,6 @@ static void __init s3c2412_clk_initparents(void)
 static struct clk *clks[] __initdata = {
         &clk_ext,
         &clk_usb_bus,
-        &clk_erefclk,
-        &clk_urefclk,
         &clk_mrefclk,
         &clk_armclk,
 };
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
new file mode 100644
index 000000000000..7f5924713485
--- /dev/null
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -0,0 +1,687 @@
+/* linux/arch/arm/mach-s3c2410/mach-jive.c
+ *
+ * Copyright 2007 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/sysdev.h>
+#include <linux/delay.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+
+#include <video/ili9320.h>
+
+#include <linux/spi/spi.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/plat-s3c/regs-serial.h>
+#include <asm/plat-s3c/nand.h>
+#include <asm/plat-s3c/iic.h>
+
+#include <asm/arch/regs-power.h>
+#include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-mem.h>
+#include <asm/arch/regs-lcd.h>
+#include <asm/arch/spi-gpio.h>
+#include <asm/arch/fb.h>
+
+#include <asm/mach-types.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/plat-s3c24xx/clock.h>
+#include <asm/plat-s3c24xx/devs.h>
+#include <asm/plat-s3c24xx/cpu.h>
+#include <asm/plat-s3c24xx/pm.h>
+#include <asm/plat-s3c24xx/udc.h>
+
+static struct map_desc jive_iodesc[] __initdata = {
+};
+
+#define UCON S3C2410_UCON_DEFAULT
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
+static struct s3c2410_uartcfg jive_uartcfgs[] = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        }
+};
+
+/* Jive flash assignment
+ *
+ * 0x00000000-0x00028000 : uboot
+ * 0x00028000-0x0002c000 : uboot env
+ * 0x0002c000-0x00030000 : spare
+ * 0x00030000-0x00200000 : zimage A
+ * 0x00200000-0x01600000 : cramfs A
+ * 0x01600000-0x017d0000 : zimage B
+ * 0x017d0000-0x02bd0000 : cramfs B
+ * 0x02bd0000-0x03fd0000 : yaffs
+ */
+static struct mtd_partition jive_imageA_nand_part[] = {
+
+#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
+        /* Don't allow access to the bootloader from linux */
+        {
+                .name           = "uboot",
+                .offset         = 0,
+                .size           = (160 * SZ_1K),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        },
+
+        /* spare */
+        {
+                .name           = "spare",
+                .offset         = (176 * SZ_1K),
+                .size           = (16 * SZ_1K),
+        },
+#endif
+
+        /* booted images */
+        {
+                .name           = "kernel (ro)",
+                .offset         = (192 * SZ_1K),
+                .size           = (SZ_2M) - (192 * SZ_1K),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        }, {
+                .name           = "root (ro)",
+                .offset         = (SZ_2M),
+                .size           = (20 * SZ_1M),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        },
+
+        /* yaffs */
+        {
+                .name           = "yaffs",
+                .offset         = (44 * SZ_1M),
+                .size           = (20 * SZ_1M),
+        },
+
+        /* bootloader environment */
+        {
+                .name           = "env",
+                .offset         = (160 * SZ_1K),
+                .size           = (16 * SZ_1K),
+        },
+
+        /* upgrade images */
+        {
+                .name           = "zimage",
+                .offset         = (22 * SZ_1M),
+                .size           = (2 * SZ_1M) - (192 * SZ_1K),
+        }, {
+                .name           = "cramfs",
+                .offset         = (24 * SZ_1M) - (192*SZ_1K),
+                .size           = (20 * SZ_1M),
+        },
+};
+
+static struct mtd_partition jive_imageB_nand_part[] = {
+
+#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
+        /* Don't allow access to the bootloader from linux */
+        {
+                .name           = "uboot",
+                .offset         = 0,
+                .size           = (160 * SZ_1K),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        },
+
+        /* spare */
+        {
+                .name           = "spare",
+                .offset         = (176 * SZ_1K),
+                .size           = (16 * SZ_1K),
+        },
+#endif
+
+        /* booted images */
+        {
+                .name           = "kernel (ro)",
+                .offset         = (22 * SZ_1M),
+                .size           = (2 * SZ_1M) - (192 * SZ_1K),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        },
+        {
+                .name           = "root (ro)",
+                .offset         = (24 * SZ_1M) - (192 * SZ_1K),
+                .size           = (20 * SZ_1M),
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        },
+
+        /* yaffs */
+        {
+                .name           = "yaffs",
+                .offset         = (44 * SZ_1M),
+                .size           = (20 * SZ_1M),
+        },
+
+        /* bootloader environment */
+        {
+                .name           = "env",
+                .offset         = (160 * SZ_1K),
+                .size           = (16 * SZ_1K),
+        },
+
+        /* upgrade images */
+        {
+                .name           = "zimage",
+                .offset         = (192 * SZ_1K),
+                .size           = (2 * SZ_1M) - (192 * SZ_1K),
+        }, {
+                .name           = "cramfs",
+                .offset         = (2 * SZ_1M),
+                .size           = (20 * SZ_1M),
+        },
+};
+
+static struct s3c2410_nand_set jive_nand_sets[] = {
+        [0] = {
+                .name           = "flash",
+                .nr_chips       = 1,
+                .nr_partitions  = ARRAY_SIZE(jive_imageA_nand_part),
+                .partitions     = jive_imageA_nand_part,
+        },
+};
+
+static struct s3c2410_platform_nand jive_nand_info = {
+        /* set taken from osiris nand timings, possibly still conservative */
+        .tacls          = 30,
+        .twrph0         = 55,
+        .twrph1         = 40,
+        .sets           = jive_nand_sets,
+        .nr_sets        = ARRAY_SIZE(jive_nand_sets),
+};
+
+static int __init jive_mtdset(char *options)
+{
+        struct s3c2410_nand_set *nand = &jive_nand_sets[0];
+        unsigned long set;
+
+        if (options == NULL || options[0] == '\0')
+                return 0;
+
+        if (strict_strtoul(options, 10, &set)) {
+                printk(KERN_ERR "failed to parse mtdset=%s\n", options);
+                return 0;
+        }
+
+        switch (set) {
+        case 1:
+                nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
+                nand->partitions = jive_imageB_nand_part;
+        case 0:
+                /* this is already setup in the nand info */
+                break;
+        default:
+                printk(KERN_ERR "Unknown mtd set %ld specified,"
+                       "using default.", set);
+        }
+
+        return 0;
+}
+
+/* parse the mtdset= option given to the kernel command line */
+__setup("mtdset=", jive_mtdset);
+
+/* LCD timing and setup */
+
+#define LCD_XRES         (240)
+#define LCD_YRES         (320)
+#define LCD_LEFT_MARGIN  (12)
+#define LCD_RIGHT_MARGIN (12)
+#define LCD_LOWER_MARGIN (12)
+#define LCD_UPPER_MARGIN (12)
+#define LCD_VSYNC        (2)
+#define LCD_HSYNC        (2)
+
+#define LCD_REFRESH      (60)
+
+#define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
+#define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
+
+struct s3c2410fb_display jive_vgg2432a4_display[] = {
+        [0] = {
+                .width          = LCD_XRES,
+                .height         = LCD_YRES,
+                .xres           = LCD_XRES,
+                .yres           = LCD_YRES,
+                .left_margin    = LCD_LEFT_MARGIN,
+                .right_margin   = LCD_RIGHT_MARGIN,
+                .upper_margin   = LCD_UPPER_MARGIN,
+                .lower_margin   = LCD_LOWER_MARGIN,
+                .hsync_len      = LCD_HSYNC,
+                .vsync_len      = LCD_VSYNC,
+
+                .pixclock       = (1000000000000LL /
+                                   (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
+
+                .bpp            = 16,
+                .type           = (S3C2410_LCDCON1_TFT16BPP |
+                                   S3C2410_LCDCON1_TFT),
+
+                .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
+                                   S3C2410_LCDCON5_INVVLINE |
+                                   S3C2410_LCDCON5_INVVFRAME |
+                                   S3C2410_LCDCON5_INVVDEN |
+                                   S3C2410_LCDCON5_PWREN),
+        },
+};
+
+/* todo - put into gpio header */
+
+#define S3C2410_GPCCON_MASK(x)  (3 << ((x) * 2))
+#define S3C2410_GPDCON_MASK(x)  (3 << ((x) * 2))
+
+struct s3c2410fb_mach_info jive_lcd_config = {
+        .displays        = jive_vgg2432a4_display,
+        .num_displays    = ARRAY_SIZE(jive_vgg2432a4_display),
+        .default_display = 0,
+
+        /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
+         * and disable the pull down resistors on pins we are using for LCD
+         * data. */
+
+        .gpcup          = (0xf << 1) | (0x3f << 10),
+
+        .gpccon         = (S3C2410_GPC1_VCLK   | S3C2410_GPC2_VLINE |
+                           S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
+                           S3C2410_GPC10_VD2   | S3C2410_GPC11_VD3 |
+                           S3C2410_GPC12_VD4   | S3C2410_GPC13_VD5 |
+                           S3C2410_GPC14_VD6   | S3C2410_GPC15_VD7),
+
+        .gpccon_mask    = (S3C2410_GPCCON_MASK(1)  | S3C2410_GPCCON_MASK(2)  |
+                           S3C2410_GPCCON_MASK(3)  | S3C2410_GPCCON_MASK(4)  |
+                           S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
+                           S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
+                           S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
+
+        .gpdup          = (0x3f << 2) | (0x3f << 10),
+
+        .gpdcon         = (S3C2410_GPD2_VD10  | S3C2410_GPD3_VD11 |
+                           S3C2410_GPD4_VD12  | S3C2410_GPD5_VD13 |
+                           S3C2410_GPD6_VD14  | S3C2410_GPD7_VD15 |
+                           S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
+                           S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
+                           S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
+
+        .gpdcon_mask    = (S3C2410_GPDCON_MASK(2)  | S3C2410_GPDCON_MASK(3) |
+                           S3C2410_GPDCON_MASK(4)  | S3C2410_GPDCON_MASK(5) |
+                           S3C2410_GPDCON_MASK(6)  | S3C2410_GPDCON_MASK(7) |
+                           S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
+                           S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
+                           S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
+};
+
+/* ILI9320 support. */
+
+static void jive_lcm_reset(unsigned int set)
+{
+        printk(KERN_DEBUG "%s(%d)\n", __func__, set);
+
+        s3c2410_gpio_setpin(S3C2410_GPG13, set);
+        s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
+}
+
+#undef LCD_UPPER_MARGIN
+#define LCD_UPPER_MARGIN 2
+
+static struct ili9320_platdata jive_lcm_config = {
+        .hsize          = LCD_XRES,
+        .vsize          = LCD_YRES,
+
+        .reset          = jive_lcm_reset,
+        .suspend        = ILI9320_SUSPEND_DEEP,
+
+        .entry_mode     = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
+        .display2       = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
+                           ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
+        .display3       = 0x0,
+        .display4       = 0x0,
+        .rgb_if1        = (ILI9320_RGBIF1_RIM_RGB18 |
+                           ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
+        .rgb_if2        = ILI9320_RGBIF2_DPL,
+        .interface2     = 0x0,
+        .interface3     = 0x3,
+        .interface4     = (ILI9320_INTERFACE4_RTNE(16) |
+                           ILI9320_INTERFACE4_DIVE(1)),
+        .interface5     = 0x0,
+        .interface6     = 0x0,
+};
+
+/* LCD SPI support */
+
+static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
+{
+        s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1);
+}
+
+static struct s3c2410_spigpio_info jive_lcd_spi = {
+        .bus_num        = 0,
+        .pin_clk        = S3C2410_GPG8,
+        .pin_mosi       = S3C2410_GPB8,
+        .chip_select    = jive_lcd_spi_chipselect,
+};
+
+static struct platform_device jive_device_lcdspi = {
+        .name           = "s3c24xx-spi-gpio",
+        .id             = 1,
+        .num_resources  = 0,
+        .dev.platform_data = &jive_lcd_spi,
+};
+
+/* WM8750 audio code SPI definition */
+
+static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
+{
+        s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1);
+}
+
+static struct s3c2410_spigpio_info jive_wm8750_spi = {
+        .bus_num        = 2,
+        .pin_clk        = S3C2410_GPB4,
+        .pin_mosi       = S3C2410_GPB9,
+        .chip_select    = jive_wm8750_chipselect,
+};
+
+static struct platform_device jive_device_wm8750 = {
+        .name           = "s3c24xx-spi-gpio",
+        .id             = 2,
+        .num_resources  = 0,
+        .dev.platform_data = &jive_wm8750_spi,
+};
+
+/* JIVE SPI devices. */
+
+static struct spi_board_info __initdata jive_spi_devs[] = {
+        [0] = {
+                .modalias       = "VGG2432A4",
+                .bus_num        = 1,
+                .chip_select    = 0,
+                .mode           = SPI_MODE_3,   /* CPOL=1, CPHA=1 */
+                .max_speed_hz   = 100000,
+                .platform_data  = &jive_lcm_config,
+        }, {
+                .modalias       = "WM8750",
+                .bus_num        = 2,
+                .chip_select    = 0,
+                .mode           = SPI_MODE_0,   /* CPOL=0, CPHA=0 */
+                .max_speed_hz   = 100000,
+        },
+};
+
+/* I2C bus and device configuration. */
+
+static struct s3c2410_platform_i2c jive_i2c_cfg = {
+        .max_freq       = 80 * 1000,
+        .bus_freq       = 50 * 1000,
+        .flags          = S3C_IICFLG_FILTER,
+        .sda_delay      = 2,
+};
+
+static struct i2c_board_info jive_i2c_devs[] = {
+        [0] = {
+                I2C_BOARD_INFO("lis302dl", 0x1c),
+                .irq    = IRQ_EINT14,
+        },
+};
+
+/* The platform devices being used. */
+
+static struct platform_device *jive_devices[] __initdata = {
+        &s3c_device_usb,
+        &s3c_device_rtc,
+        &s3c_device_wdt,
+        &s3c_device_i2c,
+        &s3c_device_lcd,
+        &jive_device_lcdspi,
+        &jive_device_wm8750,
+        &s3c_device_nand,
+        &s3c_device_usbgadget,
+};
+
+static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
+        .vbus_pin       = S3C2410_GPG1,         /* detect is on GPG1 */
+};
+
+/* Jive power management device */
+
+#ifdef CONFIG_PM
+static int jive_pm_suspend(struct sys_device *sd, pm_message_t state)
+{
+        /* Write the magic value u-boot uses to check for resume into
+         * the INFORM0 register, and ensure INFORM1 is set to the
+         * correct address to resume from. */
+
+        __raw_writel(0x2BED, S3C2412_INFORM0);
+        __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1);
+
+        return 0;
+}
+
+static int jive_pm_resume(struct sys_device *sd)
+{
+        __raw_writel(0x0, S3C2412_INFORM0);
+        return 0;
+}
+
+#else
+#define jive_pm_suspend NULL
+#define jive_pm_resume NULL
+#endif
+
+static struct sysdev_class jive_pm_sysclass = {
+        .name           = "jive-pm",
+        .suspend        = jive_pm_suspend,
+        .resume         = jive_pm_resume,
+};
+
+static struct sys_device jive_pm_sysdev = {
+        .cls            = &jive_pm_sysclass,
+};
+
+static void __init jive_map_io(void)
+{
+        s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
+}
+
+static void jive_power_off(void)
+{
+        printk(KERN_INFO "powering system down...\n");
+
+        s3c2410_gpio_setpin(S3C2410_GPC5, 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPC5, S3C2410_GPIO_OUTPUT);
+}
+
+static void __init jive_machine_init(void)
+{
+        /* register system devices for managing low level suspend */
+
+        sysdev_class_register(&jive_pm_sysclass);
+        sysdev_register(&jive_pm_sysdev);
+
+        /* write our sleep configurations for the IO. Pull down all unused
+         * IO, ensure that we have turned off all peripherals we do not
+         * need, and configure the ones we do need. */
+
+        /* Port B sleep */
+
+        __raw_writel(S3C2412_SLPCON_IN(0)   |
+                     S3C2412_SLPCON_PULL(1) |
+                     S3C2412_SLPCON_HIGH(2) |
+                     S3C2412_SLPCON_PULL(3) |
+                     S3C2412_SLPCON_PULL(4) |
+                     S3C2412_SLPCON_PULL(5) |
+                     S3C2412_SLPCON_PULL(6) |
+                     S3C2412_SLPCON_HIGH(7) |
+                     S3C2412_SLPCON_PULL(8) |
+                     S3C2412_SLPCON_PULL(9) |
+                     S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
+
+        /* Port C sleep */
+
+        __raw_writel(S3C2412_SLPCON_PULL(0) |
+                     S3C2412_SLPCON_PULL(1) |
+                     S3C2412_SLPCON_PULL(2) |
+                     S3C2412_SLPCON_PULL(3) |
+                     S3C2412_SLPCON_PULL(4) |
+                     S3C2412_SLPCON_PULL(5) |
+                     S3C2412_SLPCON_LOW(6)  |
+                     S3C2412_SLPCON_PULL(6) |
+                     S3C2412_SLPCON_PULL(7) |
+                     S3C2412_SLPCON_PULL(8) |
+                     S3C2412_SLPCON_PULL(9) |
+                     S3C2412_SLPCON_PULL(10) |
+                     S3C2412_SLPCON_PULL(11) |
+                     S3C2412_SLPCON_PULL(12) |
+                     S3C2412_SLPCON_PULL(13) |
+                     S3C2412_SLPCON_PULL(14) |
+                     S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
+
+        /* Port D sleep */
+
+        __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
+
+        /* Port F sleep */
+
+        __raw_writel(S3C2412_SLPCON_LOW(0)  |
+                     S3C2412_SLPCON_LOW(1)  |
+                     S3C2412_SLPCON_LOW(2)  |
+                     S3C2412_SLPCON_EINT(3) |
+                     S3C2412_SLPCON_EINT(4) |
+                     S3C2412_SLPCON_EINT(5) |
+                     S3C2412_SLPCON_EINT(6) |
+                     S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
+
+        /* Port G sleep */
+
+        __raw_writel(S3C2412_SLPCON_IN(0)    |
+                     S3C2412_SLPCON_IN(1)    |
+                     S3C2412_SLPCON_IN(2)    |
+                     S3C2412_SLPCON_IN(3)    |
+                     S3C2412_SLPCON_IN(4)    |
+                     S3C2412_SLPCON_IN(5)    |
+                     S3C2412_SLPCON_IN(6)    |
+                     S3C2412_SLPCON_IN(7)    |
+                     S3C2412_SLPCON_PULL(8)  |
+                     S3C2412_SLPCON_PULL(9)  |
+                     S3C2412_SLPCON_IN(10)   |
+                     S3C2412_SLPCON_PULL(11) |
+                     S3C2412_SLPCON_PULL(12) |
+                     S3C2412_SLPCON_PULL(13) |
+                     S3C2412_SLPCON_IN(14)   |
+                     S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
+
+        /* Port H sleep */
+
+        __raw_writel(S3C2412_SLPCON_PULL(0) |
+                     S3C2412_SLPCON_PULL(1) |
+                     S3C2412_SLPCON_PULL(2) |
+                     S3C2412_SLPCON_PULL(3) |
+                     S3C2412_SLPCON_PULL(4) |
+                     S3C2412_SLPCON_PULL(5) |
+                     S3C2412_SLPCON_PULL(6) |
+                     S3C2412_SLPCON_IN(7)   |
+                     S3C2412_SLPCON_IN(8)   |
+                     S3C2412_SLPCON_PULL(9) |
+                     S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
+
+        /* initialise the power management now we've setup everything. */
+
+        s3c2410_pm_init();
+
+        s3c_device_nand.dev.platform_data = &jive_nand_info;
+
+        /* initialise the spi */
+
+        s3c2410_gpio_setpin(S3C2410_GPG13, 0);
+        s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
+
+        s3c2410_gpio_setpin(S3C2410_GPB7, 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT);
+
+        s3c2410_gpio_setpin(S3C2410_GPB6, 0);
+        s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT);
+
+        s3c2410_gpio_setpin(S3C2410_GPG8, 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT);
+
+        /* initialise the WM8750 spi */
+
+        s3c2410_gpio_setpin(S3C2410_GPH10, 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT);
+
+        /* Turn off suspend on both USB ports, and switch the
+         * selectable USB port to USB device mode. */
+
+        s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
+                              S3C2410_MISCCR_USBSUSPND0 |
+                              S3C2410_MISCCR_USBSUSPND1, 0x0);
+
+        s3c24xx_udc_set_platdata(&jive_udc_cfg);
+        s3c24xx_fb_set_platdata(&jive_lcd_config);
+
+        spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
+
+        s3c_device_i2c.dev.platform_data = &jive_i2c_cfg;
+        i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
+
+        pm_power_off = jive_power_off;
+
+        platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
+}
+
+MACHINE_START(JIVE, "JIVE")
+        /* Maintainer: Ben Dooks <ben@fluff.org> */
+        .phys_io        = S3C2410_PA_UART,
+        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+
+        .init_irq       = s3c24xx_init_irq,
+        .map_io         = jive_map_io,
+        .init_machine   = jive_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index f1915bd61d15..25de042ab996 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -29,6 +29,7 @@ config MACH_ANUBIS
         bool "Simtec Electronics ANUBIS"
         select CPU_S3C2440
         select PM_SIMTEC if PM
+        select HAVE_PATA_PLATFORM
         help
           Say Y here if you are using the Simtec Electronics ANUBIS
           development system
@@ -67,6 +68,11 @@ config SMDK2440_CPU2440
         default y if ARCH_S3C2440
         select CPU_S3C2440
 
+config MACH_AT2440EVB
+        bool "Avantech AT2440EVB development board"
+        select CPU_S3C2440
+        help
+          Say Y here if you are using the AT2440EVB development board
 
 endmenu
 
diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile
index c81ed6248dcb..0b4440e79b90 100644
--- a/arch/arm/mach-s3c2440/Makefile
+++ b/arch/arm/mach-s3c2440/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_OSIRIS)	+= mach-osiris.o
 obj-$(CONFIG_MACH_RX3715)       += mach-rx3715.o
 obj-$(CONFIG_ARCH_S3C2440)      += mach-smdk2440.o
 obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
+obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 47258915a2f9..09af8b23500b 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2440/mach-anubis.c
  *
- * Copyright (c) 2003-2005 Simtec Electronics
+ * Copyright (c) 2003-2005,2008 Simtec Electronics
  *      http://armlinux.simtec.co.uk/
  *      Ben Dooks <ben@simtec.co.uk>
  *
@@ -17,6 +17,8 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/i2c.h>
 
 #include <linux/sm501.h>
 #include <linux/sm501-regs.h>
@@ -241,14 +243,18 @@ static struct s3c2410_platform_nand anubis_nand_info = {
 
 /* IDE channels */
 
+struct pata_platform_info anubis_ide_platdata = {
+        .ioport_shift   = 5,
+};
+
 static struct resource anubis_ide0_resource[] = {
         {
                 .start  = S3C2410_CS3,
                 .end    = S3C2410_CS3 + (8*32) - 1,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = S3C2410_CS3 + (1<<26),
-                .end    = S3C2410_CS3 + (1<<26) + (8*32) - 1,
+                .start  = S3C2410_CS3 + (1<<26) + (6*32),
+                .end    = S3C2410_CS3 + (1<<26) + (7*32) - 1,
                 .flags  = IORESOURCE_MEM,
         }, {
                 .start  = IRQ_IDE0,
@@ -258,10 +264,14 @@ static struct resource anubis_ide0_resource[] = {
 };
 
 static struct platform_device anubis_device_ide0 = {
-        .name           = "simtec-ide",
+        .name           = "pata_platform",
         .id             = 0,
         .num_resources  = ARRAY_SIZE(anubis_ide0_resource),
         .resource       = anubis_ide0_resource,
+        .dev    = {
+                .platform_data = &anubis_ide_platdata,
+                .coherent_dma_mask = ~0,
+        },
 };
 
 static struct resource anubis_ide1_resource[] = {
@@ -270,8 +280,8 @@ static struct resource anubis_ide1_resource[] = {
                 .end    = S3C2410_CS4 + (8*32) - 1,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = S3C2410_CS4 + (1<<26),
-                .end    = S3C2410_CS4 + (1<<26) + (8*32) - 1,
+                .start  = S3C2410_CS4 + (1<<26) + (6*32),
+                .end    = S3C2410_CS4 + (1<<26) + (7*32) - 1,
                 .flags  = IORESOURCE_MEM,
         }, {
                 .start  = IRQ_IDE0,
@@ -280,12 +290,15 @@ static struct resource anubis_ide1_resource[] = {
         },
 };
 
-
 static struct platform_device anubis_device_ide1 = {
-        .name           = "simtec-ide",
+        .name           = "pata_platform",
         .id             = 1,
         .num_resources  = ARRAY_SIZE(anubis_ide1_resource),
         .resource       = anubis_ide1_resource,
+        .dev    = {
+                .platform_data = &anubis_ide_platdata,
+                .coherent_dma_mask = ~0,
+        },
 };
 
 /* Asix AX88796 10/100 ethernet controller */
@@ -409,6 +422,15 @@ static struct clk *anubis_clocks[] = {
         &s3c24xx_uclk,
 };
 
+/* I2C devices. */
+
+static struct i2c_board_info anubis_i2c_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("tps65011", 0x48),
+                .irq    = IRQ_EINT20,
+        }
+};
+
 static void __init anubis_map_io(void)
 {
         /* initialise the clocks */
@@ -448,6 +470,9 @@ static void __init anubis_map_io(void)
 static void __init anubis_init(void)
 {
         platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
+
+        i2c_register_board_info(0, anubis_i2c_devs,
+                                ARRAY_SIZE(anubis_i2c_devs));
 }
 
 
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
new file mode 100644
index 000000000000..f5e3c7f27639
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -0,0 +1,198 @@
+/* linux/arch/arm/mach-s3c2440/mach-at2440evb.c
+ *
+ * Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com>
+ *      Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk>
+ *      and modifications by SBZ <sbz@spgui.org> and
+ *      Weibing <http://weibing.blogbus.com>
+ *
+ * For product information, visit http://www.arm9e.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/serial_core.h>
+#include <linux/dm9000.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <asm/plat-s3c/regs-serial.h>
+#include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-mem.h>
+#include <asm/arch/regs-lcd.h>
+#include <asm/plat-s3c/nand.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/plat-s3c24xx/clock.h>
+#include <asm/plat-s3c24xx/devs.h>
+#include <asm/plat-s3c24xx/cpu.h>
+
+static struct map_desc at2440evb_iodesc[] __initdata = {
+        /* Nothing here */
+};
+
+#define UCON S3C2410_UCON_DEFAULT
+#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
+#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
+
+static struct s3c24xx_uart_clksrc at2440evb_serial_clocks[] = {
+        [0] = {
+                .name           = "uclk",
+                .divisor        = 1,
+                .min_baud       = 0,
+                .max_baud       = 0,
+        },
+        [1] = {
+                .name           = "pclk",
+                .divisor        = 1,
+                .min_baud       = 0,
+                .max_baud       = 0,
+        }
+};
+
+
+static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+                .clocks      = at2440evb_serial_clocks,
+                .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+                .clocks      = at2440evb_serial_clocks,
+                .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
+        },
+};
+
+/* NAND Flash on AT2440EVB board */
+
+static struct mtd_partition at2440evb_default_nand_part[] = {
+        [0] = {
+                .name   = "Boot Agent",
+                .size   = SZ_256K,
+                .offset = 0,
+        },
+        [1] = {
+                .name   = "Kernel",
+                .size   = SZ_2M,
+                .offset = SZ_256K,
+        },
+        [2] = {
+                .name   = "Root",
+                .offset = SZ_256K + SZ_2M,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct s3c2410_nand_set at2440evb_nand_sets[] = {
+        [0] = {
+                .name           = "nand",
+                .nr_chips       = 1,
+                .nr_partitions  = ARRAY_SIZE(at2440evb_default_nand_part),
+                .partitions     = at2440evb_default_nand_part,
+        },
+};
+
+static struct s3c2410_platform_nand at2440evb_nand_info = {
+        .tacls          = 25,
+        .twrph0         = 55,
+        .twrph1         = 40,
+        .nr_sets        = ARRAY_SIZE(at2440evb_nand_sets),
+        .sets           = at2440evb_nand_sets,
+};
+
+/* DM9000AEP 10/100 ethernet controller */
+
+static struct resource at2440evb_dm9k_resource[] = {
+        [0] = {
+                .start = S3C2410_CS3,
+                .end   = S3C2410_CS3 + 3,
+                .flags = IORESOURCE_MEM
+        },
+        [1] = {
+                .start = S3C2410_CS3 + 4,
+                .end   = S3C2410_CS3 + 7,
+                .flags = IORESOURCE_MEM
+        },
+        [2] = {
+                .start = IRQ_EINT7,
+                .end   = IRQ_EINT7,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        }
+};
+
+static struct dm9000_plat_data at2440evb_dm9k_pdata = {
+        .flags          = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
+};
+
+static struct platform_device at2440evb_device_eth = {
+        .name           = "dm9000",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(at2440evb_dm9k_resource),
+        .resource       = at2440evb_dm9k_resource,
+        .dev            = {
+                .platform_data  = &at2440evb_dm9k_pdata,
+        },
+};
+
+static struct platform_device *at2440evb_devices[] __initdata = {
+        &s3c_device_usb,
+        &s3c_device_wdt,
+        &s3c_device_adc,
+        &s3c_device_i2c,
+        &s3c_device_rtc,
+        &s3c_device_nand,
+        &at2440evb_device_eth,
+};
+
+static void __init at2440evb_map_io(void)
+{
+        s3c_device_nand.dev.platform_data = &at2440evb_nand_info;
+
+        s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
+        s3c24xx_init_clocks(16934400);
+        s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
+}
+
+static void __init at2440evb_init(void)
+{
+        platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
+}
+
+
+MACHINE_START(AT2440EVB, "AT2440EVB")
+        .phys_io        = S3C2410_PA_UART,
+        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .map_io         = at2440evb_map_io,
+        .init_machine   = at2440evb_init,
+        .init_irq       = s3c24xx_init_irq,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 8a8acdbd072d..af996b0e91e8 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2440/mach-osiris.c
  *
- * Copyright (c) 2005 Simtec Electronics
+ * Copyright (c) 2005,2008 Simtec Electronics
  *      http://armlinux.simtec.co.uk/
  *      Ben Dooks <ben@simtec.co.uk>
  *
@@ -19,6 +19,7 @@
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
 #include <linux/clk.h>
+#include <linux/i2c.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -322,6 +323,15 @@ static struct sys_device osiris_pm_sysdev = {
         .cls            = &osiris_pm_sysclass,
 };
 
+/* I2C devices fitted. */
+
+static struct i2c_board_info osiris_i2c_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("tps65011", 0x48),
+                .irq    = IRQ_EINT20,
+        },
+};
+
 /* Standard Osiris devices */
 
 static struct platform_device *osiris_devices[] __initdata = {
@@ -388,6 +398,9 @@ static void __init osiris_init(void)
         sysdev_class_register(&osiris_pm_sysclass);
         sysdev_register(&osiris_pm_sysdev);
 
+        i2c_register_board_info(0, osiris_i2c_devs,
+                                ARRAY_SIZE(osiris_i2c_devs));
+
         platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
 };
 
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index b42f956738d0..17f064fabdaf 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -81,7 +81,7 @@ static int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
         else
                 clkcon &= ~clocks;
 
-        __raw_writel(clkcon, S3C2443_HCLKCON);
+        __raw_writel(clkcon, S3C2443_PCLKCON);
 
         return 0;
 }
@@ -221,7 +221,6 @@ static struct clk clk_mdivclk = {
         .get_rate       = s3c2443_getrate_mdivclk,
 };
 
-
 static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent)
 {
         unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
@@ -249,6 +248,46 @@ static struct clk clk_msysclk = {
         .set_parent     = s3c2443_setparent_msysclk,
 };
 
+/* armdiv
+ *
+ * this clock is sourced from msysclk and can have a number of
+ * divider values applied to it to then be fed into armclk.
+*/
+
+static struct clk clk_armdiv = {
+        .name           = "armdiv",
+        .id             = -1,
+        .parent         = &clk_msysclk,
+};
+
+/* armclk
+ *
+ * this is the clock fed into the ARM core itself, either from
+ * armdiv or from hclk.
+ */
+
+static int s3c2443_setparent_armclk(struct clk *clk, struct clk *parent)
+{
+        unsigned long clkdiv0;
+
+        clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+
+        if (parent == &clk_armdiv)
+                clkdiv0 &= ~S3C2443_CLKDIV0_DVS;
+        else if (parent == &clk_h)
+                clkdiv0 |= S3C2443_CLKDIV0_DVS;
+        else
+                return -EINVAL;
+
+        __raw_writel(clkdiv0, S3C2443_CLKDIV0);
+        return 0;
+}
+
+static struct clk clk_arm = {
+        .name           = "armclk",
+        .id             = -1,
+        .set_parent     = s3c2443_setparent_armclk,
+};
 
 /* esysclk
  *
@@ -639,6 +678,29 @@ static struct clk clk_display = {
         .round_rate     = s3c2443_roundrate_clksrc256,
 };
 
+/* prediv
+ *
+ * this divides the msysclk down to pass to h/p/etc.
+ */
+
+static unsigned long s3c2443_prediv_getrate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+
+        clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
+        clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
+
+        return rate / (clkdiv0 + 1);
+}
+
+static struct clk clk_prediv = {
+        .name           = "prediv",
+        .id             = -1,
+        .parent         = &clk_msysclk,
+        .get_rate       = s3c2443_prediv_getrate,
+};
+
 /* standard clock definitions */
 
 static struct clk init_clocks_disable[] = {
@@ -887,6 +949,15 @@ static void __init s3c2443_clk_initparents(void)
         }
 
         clk_init_set_parent(&clk_msysclk, parent);
+
+        /* arm */
+
+        if (__raw_readl(S3C2443_CLKDIV0) & S3C2443_CLKDIV0_DVS)
+                parent = &clk_h;
+        else
+                parent = &clk_armdiv;
+
+        clk_init_set_parent(&clk_arm, parent);
 }
 
 /* armdiv divisor table */
@@ -909,10 +980,9 @@ static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
         return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
 }
 
-static inline unsigned long s3c2443_get_prediv(unsigned long clkcon0)
+static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
 {
-        clkcon0 &= S3C2443_CLKDIV0_PREDIV_MASK;
-        clkcon0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
+        clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
 
         return clkcon0 + 1;
 }
@@ -936,6 +1006,9 @@ static struct clk *clks[] __initdata = {
         &clk_hsspi,
         &clk_hsmmc_div,
         &clk_hsmmc,
+        &clk_armdiv,
+        &clk_arm,
+        &clk_prediv,
 };
 
 void __init s3c2443_init_clocks(int xtal)
@@ -951,10 +1024,16 @@ void __init s3c2443_init_clocks(int xtal)
         int ret;
         int ptr;
 
+        /* s3c2443 parents h and p clocks from prediv */
+        clk_h.parent = &clk_prediv;
+        clk_p.parent = &clk_prediv;
+
         pll = s3c2443_get_mpll(mpllcon, xtal);
+        clk_msysclk.rate = pll;
 
         fclk = pll / s3c2443_fclk_div(clkdiv0);
-        hclk = fclk / s3c2443_get_prediv(clkdiv0);
+        hclk = s3c2443_prediv_getrate(&clk_prediv);
+        hclk = hclk / s3c2443_get_hdiv(clkdiv0);
         hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1);
         pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
 
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 33ed048502a3..3a6c8ec34cd9 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -180,8 +180,21 @@ config CPU_ARM925T
 # ARM926T
 config CPU_ARM926T
         bool "Support ARM926T processor"
-        depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
-        default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
+        depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || \
+                MACH_VERSATILE_AB || ARCH_OMAP730 || \
+                ARCH_OMAP16XX || MACH_REALVIEW_EB || \
+                ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
+                ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
+                ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
+                ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
+                ARCH_NS9XXX || ARCH_DAVINCI
+        default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || \
+                ARCH_OMAP730 || ARCH_OMAP16XX || \
+                ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
+                ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
+                ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
+                ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
+                ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2
         select CPU_32v5
         select CPU_ABRT_EV5TJ
         select CPU_PABRT_NOIFAR
@@ -365,7 +378,7 @@ config CPU_XSC3
 # Feroceon
 config CPU_FEROCEON
         bool
-        depends on ARCH_ORION5X
+        depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD || ARCH_MV78XX0
         default y
         select CPU_32v5
         select CPU_ABRT_EV5T
@@ -373,7 +386,7 @@ config CPU_FEROCEON
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_COPY_FEROCEON if MMU
-        select CPU_TLB_V4WBI if MMU
+        select CPU_TLB_FEROCEON if MMU
 
 config CPU_FEROCEON_OLD_ID
         bool "Accept early Feroceon cores with an ARM926 ID"
@@ -551,6 +564,11 @@ config CPU_TLB_V4WBI
           ARM Architecture Version 4 TLB with writeback cache and invalidate
           instruction cache entry.
 
+config CPU_TLB_FEROCEON
+        bool
+        help
+          Feroceon TLB (v4wbi with non-outer-cachable page table walks).
+
 config CPU_TLB_V6
         bool
 
@@ -709,6 +727,14 @@ config OUTER_CACHE
         bool
         default n
 
+config CACHE_FEROCEON_L2
+        bool "Enable the Feroceon L2 cache controller"
+        depends on ARCH_KIRKWOOD || ARCH_MV78XX0
+        default y
+        select OUTER_CACHE
+        help
+          This option enables the Feroceon L2 cache controller.
+
 config CACHE_L2X0
         bool "Enable the L2x0 outer cache controller"
         depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 32b2d2d213a6..f64b92557b11 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CPU_TLB_V3)	+= tlb-v3.o
 obj-$(CONFIG_CPU_TLB_V4WT)      += tlb-v4.o
 obj-$(CONFIG_CPU_TLB_V4WB)      += tlb-v4wb.o
 obj-$(CONFIG_CPU_TLB_V4WBI)     += tlb-v4wbi.o
+obj-$(CONFIG_CPU_TLB_FEROCEON)  += tlb-v4wbi.o  # reuse v4wbi TLB functions
 obj-$(CONFIG_CPU_TLB_V6)        += tlb-v6.o
 obj-$(CONFIG_CPU_TLB_V7)        += tlb-v7.o
 
@@ -73,4 +74,5 @@ obj-$(CONFIG_CPU_FEROCEON)	+= proc-feroceon.o
 obj-$(CONFIG_CPU_V6)            += proc-v6.o
 obj-$(CONFIG_CPU_V7)            += proc-v7.o
 
+obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
new file mode 100644
index 000000000000..20eec4ba173f
--- /dev/null
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -0,0 +1,318 @@
+/*
+ * arch/arm/mm/cache-feroceon-l2.c - Feroceon L2 cache controller support
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * References:
+ * - Unified Layer 2 Cache for Feroceon CPU Cores,
+ *   Document ID MV-S104858-00, Rev. A, October 23 2007.
+ */
+
+#include <linux/init.h>
+#include <asm/cacheflush.h>
+#include <asm/plat-orion/cache-feroceon-l2.h>
+
+
+/*
+ * Low-level cache maintenance operations.
+ *
+ * As well as the regular 'clean/invalidate/flush L2 cache line by
+ * MVA' instructions, the Feroceon L2 cache controller also features
+ * 'clean/invalidate L2 range by MVA' operations.
+ *
+ * Cache range operations are initiated by writing the start and
+ * end addresses to successive cp15 registers, and process every
+ * cache line whose first byte address lies in the inclusive range
+ * [start:end].
+ *
+ * The cache range operations stall the CPU pipeline until completion.
+ *
+ * The range operations require two successive cp15 writes, in
+ * between which we don't want to be preempted.
+ */
+static inline void l2_clean_pa(unsigned long addr)
+{
+        __asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr));
+}
+
+static inline void l2_clean_mva_range(unsigned long start, unsigned long end)
+{
+        unsigned long flags;
+
+        /*
+         * Make sure 'start' and 'end' reference the same page, as
+         * L2 is PIPT and range operations only do a TLB lookup on
+         * the start address.
+         */
+        BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
+
+        raw_local_irq_save(flags);
+        __asm__("mcr p15, 1, %0, c15, c9, 4" : : "r" (start));
+        __asm__("mcr p15, 1, %0, c15, c9, 5" : : "r" (end));
+        raw_local_irq_restore(flags);
+}
+
+static inline void l2_clean_pa_range(unsigned long start, unsigned long end)
+{
+        l2_clean_mva_range(__phys_to_virt(start), __phys_to_virt(end));
+}
+
+static inline void l2_clean_inv_pa(unsigned long addr)
+{
+        __asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr));
+}
+
+static inline void l2_inv_pa(unsigned long addr)
+{
+        __asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr));
+}
+
+static inline void l2_inv_mva_range(unsigned long start, unsigned long end)
+{
+        unsigned long flags;
+
+        /*
+         * Make sure 'start' and 'end' reference the same page, as
+         * L2 is PIPT and range operations only do a TLB lookup on
+         * the start address.
+         */
+        BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
+
+        raw_local_irq_save(flags);
+        __asm__("mcr p15, 1, %0, c15, c11, 4" : : "r" (start));
+        __asm__("mcr p15, 1, %0, c15, c11, 5" : : "r" (end));
+        raw_local_irq_restore(flags);
+}
+
+static inline void l2_inv_pa_range(unsigned long start, unsigned long end)
+{
+        l2_inv_mva_range(__phys_to_virt(start), __phys_to_virt(end));
+}
+
+
+/*
+ * Linux primitives.
+ *
+ * Note that the end addresses passed to Linux primitives are
+ * noninclusive, while the hardware cache range operations use
+ * inclusive start and end addresses.
+ */
+#define CACHE_LINE_SIZE         32
+#define MAX_RANGE_SIZE          1024
+
+static int l2_wt_override;
+
+static unsigned long calc_range_end(unsigned long start, unsigned long end)
+{
+        unsigned long range_end;
+
+        BUG_ON(start & (CACHE_LINE_SIZE - 1));
+        BUG_ON(end & (CACHE_LINE_SIZE - 1));
+
+        /*
+         * Try to process all cache lines between 'start' and 'end'.
+         */
+        range_end = end;
+
+        /*
+         * Limit the number of cache lines processed at once,
+         * since cache range operations stall the CPU pipeline
+         * until completion.
+         */
+        if (range_end > start + MAX_RANGE_SIZE)
+                range_end = start + MAX_RANGE_SIZE;
+
+        /*
+         * Cache range operations can't straddle a page boundary.
+         */
+        if (range_end > (start | (PAGE_SIZE - 1)) + 1)
+                range_end = (start | (PAGE_SIZE - 1)) + 1;
+
+        return range_end;
+}
+
+static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
+{
+        /*
+         * Clean and invalidate partial first cache line.
+         */
+        if (start & (CACHE_LINE_SIZE - 1)) {
+                l2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
+                start = (start | (CACHE_LINE_SIZE - 1)) + 1;
+        }
+
+        /*
+         * Clean and invalidate partial last cache line.
+         */
+        if (end & (CACHE_LINE_SIZE - 1)) {
+                l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
+                end &= ~(CACHE_LINE_SIZE - 1);
+        }
+
+        /*
+         * Invalidate all full cache lines between 'start' and 'end'.
+         */
+        while (start != end) {
+                unsigned long range_end = calc_range_end(start, end);
+                l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
+                start = range_end;
+        }
+
+        dsb();
+}
+
+static void feroceon_l2_clean_range(unsigned long start, unsigned long end)
+{
+        /*
+         * If L2 is forced to WT, the L2 will always be clean and we
+         * don't need to do anything here.
+         */
+        if (!l2_wt_override) {
+                start &= ~(CACHE_LINE_SIZE - 1);
+                end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
+                while (start != end) {
+                        unsigned long range_end = calc_range_end(start, end);
+                        l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE);
+                        start = range_end;
+                }
+        }
+
+        dsb();
+}
+
+static void feroceon_l2_flush_range(unsigned long start, unsigned long end)
+{
+        start &= ~(CACHE_LINE_SIZE - 1);
+        end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
+        while (start != end) {
+                unsigned long range_end = calc_range_end(start, end);
+                if (!l2_wt_override)
+                        l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE);
+                l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
+                start = range_end;
+        }
+
+        dsb();
+}
+
+
+/*
+ * Routines to disable and re-enable the D-cache and I-cache at run
+ * time.  These are necessary because the L2 cache can only be enabled
+ * or disabled while the L1 Dcache and Icache are both disabled.
+ */
+static void __init invalidate_and_disable_dcache(void)
+{
+        u32 cr;
+
+        cr = get_cr();
+        if (cr & CR_C) {
+                unsigned long flags;
+
+                raw_local_irq_save(flags);
+                flush_cache_all();
+                set_cr(cr & ~CR_C);
+                raw_local_irq_restore(flags);
+        }
+}
+
+static void __init enable_dcache(void)
+{
+        u32 cr;
+
+        cr = get_cr();
+        if (!(cr & CR_C))
+                set_cr(cr | CR_C);
+}
+
+static void __init __invalidate_icache(void)
+{
+        int dummy;
+
+        __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0\n" : "=r" (dummy));
+}
+
+static void __init invalidate_and_disable_icache(void)
+{
+        u32 cr;
+
+        cr = get_cr();
+        if (cr & CR_I) {
+                set_cr(cr & ~CR_I);
+                __invalidate_icache();
+        }
+}
+
+static void __init enable_icache(void)
+{
+        u32 cr;
+
+        cr = get_cr();
+        if (!(cr & CR_I))
+                set_cr(cr | CR_I);
+}
+
+static inline u32 read_extra_features(void)
+{
+        u32 u;
+
+        __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));
+
+        return u;
+}
+
+static inline void write_extra_features(u32 u)
+{
+        __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
+}
+
+static void __init disable_l2_prefetch(void)
+{
+        u32 u;
+
+        /*
+         * Read the CPU Extra Features register and verify that the
+         * Disable L2 Prefetch bit is set.
+         */
+        u = read_extra_features();
+        if (!(u & 0x01000000)) {
+                printk(KERN_INFO "Feroceon L2: Disabling L2 prefetch.\n");
+                write_extra_features(u | 0x01000000);
+        }
+}
+
+static void __init enable_l2(void)
+{
+        u32 u;
+
+        u = read_extra_features();
+        if (!(u & 0x00400000)) {
+                printk(KERN_INFO "Feroceon L2: Enabling L2\n");
+
+                invalidate_and_disable_dcache();
+                invalidate_and_disable_icache();
+                write_extra_features(u | 0x00400000);
+                enable_icache();
+                enable_dcache();
+        }
+}
+
+void __init feroceon_l2_init(int __l2_wt_override)
+{
+        l2_wt_override = __l2_wt_override;
+
+        disable_l2_prefetch();
+
+        outer_cache.inv_range = feroceon_l2_inv_range;
+        outer_cache.clean_range = feroceon_l2_clean_range;
+        outer_cache.flush_range = feroceon_l2_flush_range;
+
+        enable_l2();
+
+        printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n",
+                         l2_wt_override ? ", in WT override mode" : "");
+}
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 44558d5f9313..fbfa26058442 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -144,13 +144,17 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
         page = pfn_to_page(pfn);
         mapping = page_mapping(page);
         if (mapping) {
+#ifndef CONFIG_SMP
                 int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
 
                 if (dirty)
                         __flush_dcache_page(mapping, page);
+#endif
 
                 if (cache_is_vivt())
                         make_coherent(mapping, vma, addr, pfn);
+                else if (vma->vm_flags & VM_EXEC)
+                        __flush_icache_all();
         }
 }
 
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 9df507d36e0b..029ee65fda2b 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -199,6 +199,8 @@ void flush_dcache_page(struct page *page)
                 __flush_dcache_page(mapping, page);
                 if (mapping && cache_is_vivt())
                         __flush_dcache_aliases(mapping, page);
+                else if (mapping)
+                        __flush_icache_all();
         }
 }
 EXPORT_SYMBOL(flush_dcache_page);
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index a02c1712b52d..f2e5884c513a 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -44,11 +44,31 @@
  */
 #define CACHE_DLINESIZE 32
 
+        .bss
+        .align 3
+__cache_params_loc:
+        .space  8
+
         .text
+__cache_params:
+        .word   __cache_params_loc
+
 /*
  * cpu_feroceon_proc_init()
  */
 ENTRY(cpu_feroceon_proc_init)
+        mrc     p15, 0, r0, c0, c0, 1           @ read cache type register
+        ldr     r1, __cache_params
+        mov     r2, #(16 << 5)
+        tst     r0, #(1 << 16)                  @ get way
+        mov     r0, r0, lsr #18                 @ get cache size order
+        movne   r3, #((4 - 1) << 30)            @ 4-way
+        and     r0, r0, #0xf
+        moveq   r3, #0                          @ 1-way
+        mov     r2, r2, lsl r0                  @ actual cache size
+        movne   r2, r2, lsr #2                  @ turned into # of sets
+        sub     r2, r2, #(1 << 5)
+        stmia   r1, {r2, r3}
         mov     pc, lr
 
 /*
@@ -59,6 +79,13 @@ ENTRY(cpu_feroceon_proc_fin)
         mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
         msr     cpsr_c, ip
         bl      feroceon_flush_kern_cache_all
+
+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+        mov     r0, #0
+        mcr     p15, 1, r0, c15, c9, 0          @ clean L2
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+#endif
+
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
@@ -117,11 +144,19 @@ ENTRY(feroceon_flush_user_cache_all)
  */
 ENTRY(feroceon_flush_kern_cache_all)
         mov     r2, #VM_EXEC
-        mov     ip, #0
+
 __flush_whole_cache:
-1:      mrc     p15, 0, r15, c7, c14, 3         @ test,clean,invalidate
-        bne     1b
+        ldr     r1, __cache_params
+        ldmia   r1, {r1, r3}
+1:      orr     ip, r1, r3
+2:      mcr     p15, 0, ip, c7, c14, 2          @ clean + invalidate D set/way
+        subs    ip, ip, #(1 << 30)              @ next way
+        bcs     2b
+        subs    r1, r1, #(1 << 5)               @ next set
+        bcs     1b
+
         tst     r2, #VM_EXEC
+        mov     ip, #0
         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
         mov     pc, lr
@@ -138,7 +173,6 @@ __flush_whole_cache:
  */
         .align  5
 ENTRY(feroceon_flush_user_cache_range)
-        mov     ip, #0
         sub     r3, r1, r0                      @ calculate total size
         cmp     r3, #CACHE_DLIMIT
         bgt     __flush_whole_cache
@@ -152,6 +186,7 @@ ENTRY(feroceon_flush_user_cache_range)
         cmp     r0, r1
         blo     1b
         tst     r2, #VM_EXEC
+        mov     ip, #0
         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
         mov     pc, lr
 
@@ -209,6 +244,20 @@ ENTRY(feroceon_flush_kern_dcache_page)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+        .align  5
+ENTRY(feroceon_range_flush_kern_dcache_page)
+        mrs     r2, cpsr
+        add     r1, r0, #PAGE_SZ - CACHE_DLINESIZE      @ top addr is inclusive
+        orr     r3, r2, #PSR_I_BIT
+        msr     cpsr_c, r3                      @ disable interrupts
+        mcr     p15, 5, r0, c15, c15, 0         @ D clean/inv range start
+        mcr     p15, 5, r1, c15, c15, 1         @ D clean/inv range top
+        msr     cpsr_c, r2                      @ restore interrupts
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     pc, lr
+
 /*
  *      dma_inv_range(start, end)
  *
@@ -225,10 +274,10 @@ ENTRY(feroceon_flush_kern_dcache_page)
         .align  5
 ENTRY(feroceon_dma_inv_range)
         tst     r0, #CACHE_DLINESIZE - 1
+        bic     r0, r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
         tst     r1, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
-        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
@@ -236,6 +285,22 @@ ENTRY(feroceon_dma_inv_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+        .align  5
+ENTRY(feroceon_range_dma_inv_range)
+        mrs     r2, cpsr
+        tst     r0, #CACHE_DLINESIZE - 1
+        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
+        tst     r1, #CACHE_DLINESIZE - 1
+        mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
+        cmp     r1, r0
+        subne   r1, r1, #1                      @ top address is inclusive
+        orr     r3, r2, #PSR_I_BIT
+        msr     cpsr_c, r3                      @ disable interrupts
+        mcr     p15, 5, r0, c15, c14, 0         @ D inv range start
+        mcr     p15, 5, r1, c15, c14, 1         @ D inv range top
+        msr     cpsr_c, r2                      @ restore interrupts
+        mov     pc, lr
+
 /*
  *      dma_clean_range(start, end)
  *
@@ -256,6 +321,19 @@ ENTRY(feroceon_dma_clean_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+        .align  5
+ENTRY(feroceon_range_dma_clean_range)
+        mrs     r2, cpsr
+        cmp     r1, r0
+        subne   r1, r1, #1                      @ top address is inclusive
+        orr     r3, r2, #PSR_I_BIT
+        msr     cpsr_c, r3                      @ disable interrupts
+        mcr     p15, 5, r0, c15, c13, 0         @ D clean range start
+        mcr     p15, 5, r1, c15, c13, 1         @ D clean range top
+        msr     cpsr_c, r2                      @ restore interrupts
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     pc, lr
+
 /*
  *      dma_flush_range(start, end)
  *
@@ -274,6 +352,19 @@ ENTRY(feroceon_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+        .align  5
+ENTRY(feroceon_range_dma_flush_range)
+        mrs     r2, cpsr
+        cmp     r1, r0
+        subne   r1, r1, #1                      @ top address is inclusive
+        orr     r3, r2, #PSR_I_BIT
+        msr     cpsr_c, r3                      @ disable interrupts
+        mcr     p15, 5, r0, c15, c15, 0         @ D clean/inv range start
+        mcr     p15, 5, r1, c15, c15, 1         @ D clean/inv range top
+        msr     cpsr_c, r2                      @ restore interrupts
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     pc, lr
+
 ENTRY(feroceon_cache_fns)
         .long   feroceon_flush_kern_cache_all
         .long   feroceon_flush_user_cache_all
@@ -285,12 +376,33 @@ ENTRY(feroceon_cache_fns)
         .long   feroceon_dma_clean_range
         .long   feroceon_dma_flush_range
 
+ENTRY(feroceon_range_cache_fns)
+        .long   feroceon_flush_kern_cache_all
+        .long   feroceon_flush_user_cache_all
+        .long   feroceon_flush_user_cache_range
+        .long   feroceon_coherent_kern_range
+        .long   feroceon_coherent_user_range
+        .long   feroceon_range_flush_kern_dcache_page
+        .long   feroceon_range_dma_inv_range
+        .long   feroceon_range_dma_clean_range
+        .long   feroceon_range_dma_flush_range
+
         .align  5
 ENTRY(cpu_feroceon_dcache_clean_area)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+        mov     r2, r0
+        mov     r3, r1
+#endif
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHE_DLINESIZE
         subs    r1, r1, #CACHE_DLINESIZE
         bhi     1b
+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+1:      mcr     p15, 1, r2, c15, c9, 1          @ clean L2 entry
+        add     r2, r2, #CACHE_DLINESIZE
+        subs    r3, r3, #CACHE_DLINESIZE
+        bhi     1b
+#endif
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
@@ -306,16 +418,25 @@ ENTRY(cpu_feroceon_dcache_clean_area)
         .align  5
 ENTRY(cpu_feroceon_switch_mm)
 #ifdef CONFIG_MMU
-        mov     ip, #0
-@ && 'Clean & Invalidate whole DCache'
-1:      mrc     p15, 0, r15, c7, c14, 3         @ test,clean,invalidate
-        bne     1b
-        mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
-        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
+        /*
+         * Note: we wish to call __flush_whole_cache but we need to preserve
+         * lr to do so.  The only way without touching main memory is to
+         * use r2 which is normally used to test the VM_EXEC flag, and
+         * compensate locally for the skipped ops if it is not set.
+         */
+        mov     r2, lr                          @ abuse r2 to preserve lr
+        bl      __flush_whole_cache
+        @ if r2 contains the VM_EXEC bit then the next 2 ops are done already
+        tst     r2, #VM_EXEC
+        mcreq   p15, 0, ip, c7, c5, 0           @ invalidate I cache
+        mcreq   p15, 0, ip, c7, c10, 4          @ drain WB
+
         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
-#endif
+        mov     pc, r2
+#else
         mov     pc, lr
+#endif
 
 /*
  * cpu_feroceon_set_pte_ext(ptep, pte, ext)
@@ -345,6 +466,9 @@ ENTRY(cpu_feroceon_set_pte_ext)
         str     r2, [r0]                        @ hardware version
         mov     r0, r0
         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+        mcr     p15, 1, r0, c15, c9, 1          @ clean L2 entry
+#endif
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 #endif
         mov     pc, lr
@@ -369,14 +493,15 @@ __feroceon_setup:
         .size   __feroceon_setup, . - __feroceon_setup
 
         /*
-         *  R
-         * .RVI ZFRS BLDP WCAM
-         * .011 0001 ..11 0101
+         *      B
+         *  R   P
+         * .RVI UFRS BLDP WCAM
+         * .011 .001 ..11 0101
          *
          */
         .type   feroceon_crval, #object
 feroceon_crval:
-        crval   clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
+        crval   clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134
 
         __INITDATA
 
@@ -414,6 +539,21 @@ cpu_feroceon_name:
         .asciz  "Feroceon"
         .size   cpu_feroceon_name, . - cpu_feroceon_name
 
+        .type   cpu_88fr531_name, #object
+cpu_88fr531_name:
+        .asciz  "Feroceon 88FR531-vd"
+        .size   cpu_88fr531_name, . - cpu_88fr531_name
+
+        .type   cpu_88fr571_name, #object
+cpu_88fr571_name:
+        .asciz  "Feroceon 88FR571-vd"
+        .size   cpu_88fr571_name, . - cpu_88fr571_name
+
+        .type   cpu_88fr131_name, #object
+cpu_88fr131_name:
+        .asciz  "Feroceon 88FR131"
+        .size   cpu_88fr131_name, . - cpu_88fr131_name
+
         .align
 
         .section ".proc.info.init", #alloc, #execinstr
@@ -421,15 +561,15 @@ cpu_feroceon_name:
 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
         .type   __feroceon_old_id_proc_info,#object
 __feroceon_old_id_proc_info:
-        .long   0x41069260
-        .long   0xfffffff0
-        .long   PMD_TYPE_SECT | \
+        .long   0x41009260
+        .long   0xff00fff0
+        .long   PMD_TYPE_SECT | \
                 PMD_SECT_BUFFERABLE | \
                 PMD_SECT_CACHEABLE | \
                 PMD_BIT4 | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ
-        .long   PMD_TYPE_SECT | \
+        .long   PMD_TYPE_SECT | \
                 PMD_BIT4 | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ
@@ -445,17 +585,17 @@ __feroceon_old_id_proc_info:
         .size   __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
 #endif
 
-        .type   __feroceon_proc_info,#object
-__feroceon_proc_info:
+        .type   __88fr531_proc_info,#object
+__88fr531_proc_info:
         .long   0x56055310
         .long   0xfffffff0
-        .long   PMD_TYPE_SECT | \
+        .long   PMD_TYPE_SECT | \
                 PMD_SECT_BUFFERABLE | \
                 PMD_SECT_CACHEABLE | \
                 PMD_BIT4 | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ
-        .long   PMD_TYPE_SECT | \
+        .long   PMD_TYPE_SECT | \
                 PMD_BIT4 | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ
@@ -463,9 +603,59 @@ __feroceon_proc_info:
         .long   cpu_arch_name
         .long   cpu_elf_name
         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-        .long   cpu_feroceon_name
+        .long   cpu_88fr531_name
         .long   feroceon_processor_functions
         .long   v4wbi_tlb_fns
         .long   feroceon_user_fns
         .long   feroceon_cache_fns
-        .size   __feroceon_proc_info, . - __feroceon_proc_info
+        .size   __88fr531_proc_info, . - __88fr531_proc_info
+
+        .type   __88fr571_proc_info,#object
+__88fr571_proc_info:
+        .long   0x56155710
+        .long   0xfffffff0
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_BUFFERABLE | \
+                PMD_SECT_CACHEABLE | \
+                PMD_BIT4 | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        .long   PMD_TYPE_SECT | \
+                PMD_BIT4 | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        b       __feroceon_setup
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   cpu_88fr571_name
+        .long   feroceon_processor_functions
+        .long   v4wbi_tlb_fns
+        .long   feroceon_user_fns
+        .long   feroceon_range_cache_fns
+        .size   __88fr571_proc_info, . - __88fr571_proc_info
+
+        .type   __88fr131_proc_info,#object
+__88fr131_proc_info:
+        .long   0x56251310
+        .long   0xfffffff0
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_BUFFERABLE | \
+                PMD_SECT_CACHEABLE | \
+                PMD_BIT4 | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        .long   PMD_TYPE_SECT | \
+                PMD_BIT4 | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        b       __feroceon_setup
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   cpu_88fr131_name
+        .long   feroceon_processor_functions
+        .long   v4wbi_tlb_fns
+        .long   feroceon_user_fns
+        .long   feroceon_range_cache_fns
+        .size   __88fr131_proc_info, . - __88fr131_proc_info
diff --git a/arch/arm/plat-iop/gpio.c b/arch/arm/plat-iop/gpio.c
index eda436083417..640e498c12ef 100644
--- a/arch/arm/plat-iop/gpio.c
+++ b/arch/arm/plat-iop/gpio.c
@@ -11,6 +11,10 @@
  */
 
 #include <linux/device.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/gpio.h>
 #include <asm/hardware/iop3xx.h>
 
 void gpio_line_config(int line, int direction)
@@ -46,3 +50,42 @@ void gpio_line_set(int line, int value)
         local_irq_restore(flags);
 }
 EXPORT_SYMBOL(gpio_line_set);
+
+static int iop3xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+        gpio_line_config(gpio, GPIO_IN);
+        return 0;
+}
+
+static int iop3xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
+{
+        gpio_line_set(gpio, level);
+        gpio_line_config(gpio, GPIO_OUT);
+        return 0;
+}
+
+static int iop3xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
+{
+        return gpio_line_get(gpio);
+}
+
+static void iop3xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
+{
+        gpio_line_set(gpio, value);
+}
+
+static struct gpio_chip iop3xx_chip = {
+        .label                  = "iop3xx",
+        .direction_input        = iop3xx_gpio_direction_input,
+        .get                    = iop3xx_gpio_get_value,
+        .direction_output       = iop3xx_gpio_direction_output,
+        .set                    = iop3xx_gpio_set_value,
+        .base                   = 0,
+        .ngpio                  = IOP3XX_N_GPIOS,
+};
+
+static int __init iop3xx_gpio_setup(void)
+{
+        return gpiochip_add(&iop3xx_chip);
+}
+arch_initcall(iop3xx_gpio_setup);
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index bb6e12738fb3..e14eaad11dd5 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -3,9 +3,14 @@ if ARCH_MXC
 menu "Freescale MXC Implementations"
 
 choice
-        prompt "MXC/iMX System Type"
+        prompt "MXC/iMX Base Type"
         default ARCH_MX3
 
+config ARCH_MX2
+        bool "MX2-based"
+        help
+          This enables support for systems based on the Freescale i.MX2 family
+
 config ARCH_MX3
         bool "MX3-based"
         help
@@ -13,6 +18,7 @@ config ARCH_MX3
 
 endchoice
 
+source "arch/arm/mach-mx2/Kconfig"
 source "arch/arm/mach-mx3/Kconfig"
 
 endmenu
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index f96dc0362068..db66e9ae8414 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,4 +3,6 @@
 #
 
 # Common support
-obj-y := irq.o
+obj-y := irq.o clock.o gpio.o time.o
+
+obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
new file mode 100644
index 000000000000..1aa86fd60d71
--- /dev/null
+++ b/arch/arm/plat-mxc/clock.c
@@ -0,0 +1,331 @@
+/*
+ * Based on arch/arm/plat-omap/clock.c
+ *
+ * Copyright (C) 2004 - 2005 Nokia corporation
+ * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+/* #define DEBUG */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/proc_fs.h>
+#include <linux/semaphore.h>
+#include <linux/string.h>
+#include <linux/version.h>
+
+#include <asm/arch/clock.h>
+
+static LIST_HEAD(clocks);
+static DEFINE_MUTEX(clocks_mutex);
+
+/*-------------------------------------------------------------------------
+ * Standard clock functions defined in include/linux/clk.h
+ *-------------------------------------------------------------------------*/
+
+/*
+ * Retrieve a clock by name.
+ *
+ * Note that we first try to use device id on the bus
+ * and clock name. If this fails, we try to use "<name>.<id>". If this fails,
+ * we try to use clock name only.
+ * The reference count to the clock's module owner ref count is incremented.
+ */
+struct clk *clk_get(struct device *dev, const char *id)
+{
+        struct clk *p, *clk = ERR_PTR(-ENOENT);
+        int idno;
+        const char *str;
+
+        if (id == NULL)
+                return clk;
+
+        if (dev == NULL || dev->bus != &platform_bus_type)
+                idno = -1;
+        else
+                idno = to_platform_device(dev)->id;
+
+        mutex_lock(&clocks_mutex);
+
+        list_for_each_entry(p, &clocks, node) {
+                if (p->id == idno &&
+                    strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
+                        clk = p;
+                        goto found;
+                }
+        }
+
+        str = strrchr(id, '.');
+        if (str) {
+                int cnt = str - id;
+                str++;
+                idno = simple_strtol(str, NULL, 10);
+                list_for_each_entry(p, &clocks, node) {
+                        if (p->id == idno &&
+                            strlen(p->name) == cnt &&
+                            strncmp(id, p->name, cnt) == 0 &&
+                            try_module_get(p->owner)) {
+                                clk = p;
+                                goto found;
+                        }
+                }
+        }
+
+        list_for_each_entry(p, &clocks, node) {
+                if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
+                        clk = p;
+                        goto found;
+                }
+        }
+
+        printk(KERN_WARNING "clk: Unable to get requested clock: %s\n", id);
+
+found:
+        mutex_unlock(&clocks_mutex);
+
+        return clk;
+}
+EXPORT_SYMBOL(clk_get);
+
+static void __clk_disable(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return;
+
+        __clk_disable(clk->parent);
+        __clk_disable(clk->secondary);
+
+        if (!(--clk->usecount) && clk->disable)
+                clk->disable(clk);
+}
+
+static int __clk_enable(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        __clk_enable(clk->parent);
+        __clk_enable(clk->secondary);
+
+        if (clk->usecount++ == 0 && clk->enable)
+                clk->enable(clk);
+
+        return 0;
+}
+
+/* This function increments the reference count on the clock and enables the
+ * clock if not already enabled. The parent clock tree is recursively enabled
+ */
+int clk_enable(struct clk *clk)
+{
+        int ret = 0;
+
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        mutex_lock(&clocks_mutex);
+        ret = __clk_enable(clk);
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+/* This function decrements the reference count on the clock and disables
+ * the clock when reference count is 0. The parent clock tree is
+ * recursively disabled
+ */
+void clk_disable(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return;
+
+        mutex_lock(&clocks_mutex);
+        __clk_disable(clk);
+        mutex_unlock(&clocks_mutex);
+}
+EXPORT_SYMBOL(clk_disable);
+
+/* Retrieve the *current* clock rate. If the clock itself
+ * does not provide a special calculation routine, ask
+ * its parent and so on, until one is able to return
+ * a valid clock rate
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return 0UL;
+
+        if (clk->get_rate)
+                return clk->get_rate(clk);
+
+        return clk_get_rate(clk->parent);
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+/* Decrement the clock's module reference count */
+void clk_put(struct clk *clk)
+{
+        if (clk && !IS_ERR(clk))
+                module_put(clk->owner);
+}
+EXPORT_SYMBOL(clk_put);
+
+/* Round the requested clock rate to the nearest supported
+ * rate that is less than or equal to the requested rate.
+ * This is dependent on the clock's current parent.
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
+                return 0;
+
+        return clk->round_rate(clk, rate);
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+/* Set the clock to the requested clock rate. The rate must
+ * match a supported rate exactly based on what clk_round_rate returns
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret = -EINVAL;
+
+        if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
+                return ret;
+
+        mutex_lock(&clocks_mutex);
+        ret = clk->set_rate(clk, rate);
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+/* Set the clock's parent to another clock source */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        int ret = -EINVAL;
+
+        if (clk == NULL || IS_ERR(clk) || parent == NULL ||
+            IS_ERR(parent) || clk->set_parent == NULL)
+                return ret;
+
+        mutex_lock(&clocks_mutex);
+        ret = clk->set_parent(clk, parent);
+        if (ret == 0)
+                clk->parent = parent;
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+/* Retrieve the clock's parent clock source */
+struct clk *clk_get_parent(struct clk *clk)
+{
+        struct clk *ret = NULL;
+
+        if (clk == NULL || IS_ERR(clk))
+                return ret;
+
+        return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
+/*
+ * Add a new clock to the clock tree.
+ */
+int clk_register(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        mutex_lock(&clocks_mutex);
+        list_add(&clk->node, &clocks);
+        mutex_unlock(&clocks_mutex);
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_register);
+
+/* Remove a clock from the clock tree */
+void clk_unregister(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return;
+
+        mutex_lock(&clocks_mutex);
+        list_del(&clk->node);
+        mutex_unlock(&clocks_mutex);
+}
+EXPORT_SYMBOL(clk_unregister);
+
+#ifdef CONFIG_PROC_FS
+static int mxc_clock_read_proc(char *page, char **start, off_t off,
+                                int count, int *eof, void *data)
+{
+        struct clk *clkp;
+        char *p = page;
+        int len;
+
+        list_for_each_entry(clkp, &clocks, node) {
+                p += sprintf(p, "%s-%d:\t\t%lu, %d", clkp->name, clkp->id,
+                                clk_get_rate(clkp), clkp->usecount);
+                if (clkp->parent)
+                        p += sprintf(p, ", %s-%d\n", clkp->parent->name,
+                                     clkp->parent->id);
+                else
+                        p += sprintf(p, "\n");
+        }
+
+        len = (p - page) - off;
+        if (len < 0)
+                len = 0;
+
+        *eof = (len <= count) ? 1 : 0;
+        *start = page + off;
+
+        return len;
+}
+
+static int __init mxc_setup_proc_entry(void)
+{
+        struct proc_dir_entry *res;
+
+        res = create_proc_read_entry("cpu/clocks", 0, NULL,
+                                     mxc_clock_read_proc, NULL);
+        if (!res) {
+                printk(KERN_ERR "Failed to create proc/cpu/clocks\n");
+                return -ENOMEM;
+        }
+        return 0;
+}
+
+late_initcall(mxc_setup_proc_entry);
+#endif
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
new file mode 100644
index 000000000000..4a7736717d86
--- /dev/null
+++ b/arch/arm/plat-mxc/gpio.c
@@ -0,0 +1,253 @@
+/*
+ * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * Based on code from Freescale,
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <asm/hardware.h>
+#include <asm-generic/bug.h>
+
+static struct mxc_gpio_port *mxc_gpio_ports;
+static int gpio_table_size;
+
+/* Note: This driver assumes 32 GPIOs are handled in one register */
+
+static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
+{
+        __raw_writel(1 << index, port->base + GPIO_ISR);
+}
+
+static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
+                                int enable)
+{
+        u32 l;
+
+        l = __raw_readl(port->base + GPIO_IMR);
+        l = (l & (~(1 << index))) | (!!enable << index);
+        __raw_writel(l, port->base + GPIO_IMR);
+}
+
+static void gpio_ack_irq(u32 irq)
+{
+        u32 gpio = irq_to_gpio(irq);
+        _clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f);
+}
+
+static void gpio_mask_irq(u32 irq)
+{
+        u32 gpio = irq_to_gpio(irq);
+        _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0);
+}
+
+static void gpio_unmask_irq(u32 irq)
+{
+        u32 gpio = irq_to_gpio(irq);
+        _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
+}
+
+static int gpio_set_irq_type(u32 irq, u32 type)
+{
+        u32 gpio = irq_to_gpio(irq);
+        struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
+        u32 bit, val;
+        int edge;
+        void __iomem *reg = port->base;
+
+        switch (type) {
+        case IRQT_RISING:
+                edge = GPIO_INT_RISE_EDGE;
+                break;
+        case IRQT_FALLING:
+                edge = GPIO_INT_FALL_EDGE;
+                break;
+        case IRQT_LOW:
+                edge = GPIO_INT_LOW_LEV;
+                break;
+        case IRQT_HIGH:
+                edge = GPIO_INT_HIGH_LEV;
+                break;
+        default:        /* this includes IRQT_BOTHEDGE */
+                return -EINVAL;
+        }
+
+        reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
+        bit = gpio & 0xf;
+        val = __raw_readl(reg) & ~(0x3 << (bit << 1));
+        __raw_writel(val | (edge << (bit << 1)), reg);
+        _clear_gpio_irqstatus(port, gpio & 0x1f);
+
+        return 0;
+}
+
+/* handle n interrupts in one status register */
+static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
+{
+        u32 gpio_irq_no;
+
+        gpio_irq_no = port->virtual_irq_start;
+        for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) {
+
+                if ((irq_stat & 1) == 0)
+                        continue;
+
+                BUG_ON(!(irq_desc[gpio_irq_no].handle_irq));
+                irq_desc[gpio_irq_no].handle_irq(gpio_irq_no,
+                                &irq_desc[gpio_irq_no]);
+        }
+}
+
+#ifdef CONFIG_ARCH_MX3
+/* MX3 has one interrupt *per* gpio port */
+static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+        u32 irq_stat;
+        struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
+
+        irq_stat = __raw_readl(port->base + GPIO_ISR) &
+                        __raw_readl(port->base + GPIO_IMR);
+        BUG_ON(!irq_stat);
+        mxc_gpio_irq_handler(port, irq_stat);
+}
+#endif
+
+#ifdef CONFIG_ARCH_MX2
+/* MX2 has one interrupt *for all* gpio ports */
+static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+        int i;
+        u32 irq_msk, irq_stat;
+        struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
+
+        /* walk through all interrupt status registers */
+        for (i = 0; i < gpio_table_size; i++) {
+                irq_msk = __raw_readl(port[i].base + GPIO_IMR);
+                if (!irq_msk)
+                        continue;
+
+                irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk;
+                if (irq_stat)
+                        mxc_gpio_irq_handler(&port[i], irq_stat);
+        }
+}
+#endif
+
+static struct irq_chip gpio_irq_chip = {
+        .ack = gpio_ack_irq,
+        .mask = gpio_mask_irq,
+        .unmask = gpio_unmask_irq,
+        .set_type = gpio_set_irq_type,
+};
+
+static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
+                                int dir)
+{
+        struct mxc_gpio_port *port =
+                container_of(chip, struct mxc_gpio_port, chip);
+        u32 l;
+
+        l = __raw_readl(port->base + GPIO_GDIR);
+        if (dir)
+                l |= 1 << offset;
+        else
+                l &= ~(1 << offset);
+        __raw_writel(l, port->base + GPIO_GDIR);
+}
+
+static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct mxc_gpio_port *port =
+                container_of(chip, struct mxc_gpio_port, chip);
+        void __iomem *reg = port->base + GPIO_DR;
+        u32 l;
+
+        l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
+        __raw_writel(l, reg);
+}
+
+static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct mxc_gpio_port *port =
+                container_of(chip, struct mxc_gpio_port, chip);
+
+        return (__raw_readl(port->base + GPIO_DR) >> offset) & 1;
+}
+
+static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        _set_gpio_direction(chip, offset, 0);
+        return 0;
+}
+
+static int mxc_gpio_direction_output(struct gpio_chip *chip,
+                                     unsigned offset, int value)
+{
+        _set_gpio_direction(chip, offset, 1);
+        mxc_gpio_set(chip, offset, value);
+        return 0;
+}
+
+int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
+{
+        int i, j;
+
+        /* save for local usage */
+        mxc_gpio_ports = port;
+        gpio_table_size = cnt;
+
+        printk(KERN_INFO "MXC GPIO hardware\n");
+
+        for (i = 0; i < cnt; i++) {
+                /* disable the interrupt and clear the status */
+                __raw_writel(0, port[i].base + GPIO_IMR);
+                __raw_writel(~0, port[i].base + GPIO_ISR);
+                for (j = port[i].virtual_irq_start;
+                        j < port[i].virtual_irq_start + 32; j++) {
+                        set_irq_chip(j, &gpio_irq_chip);
+                        set_irq_handler(j, handle_edge_irq);
+                        set_irq_flags(j, IRQF_VALID);
+                }
+
+                /* register gpio chip */
+                port[i].chip.direction_input = mxc_gpio_direction_input;
+                port[i].chip.direction_output = mxc_gpio_direction_output;
+                port[i].chip.get = mxc_gpio_get;
+                port[i].chip.set = mxc_gpio_set;
+                port[i].chip.base = i * 32;
+                port[i].chip.ngpio = 32;
+
+                /* its a serious configuration bug when it fails */
+                BUG_ON( gpiochip_add(&port[i].chip) < 0 );
+
+#ifdef CONFIG_ARCH_MX3
+                /* setup one handler for each entry */
+                set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
+                set_irq_data(port[i].irq, &port[i]);
+#endif
+        }
+
+#ifdef CONFIG_ARCH_MX2
+        /* setup one handler for all GPIO interrupts */
+        set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
+        set_irq_data(port[0].irq, port);
+#endif
+        return 0;
+}
diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c
new file mode 100644
index 000000000000..1985571eb40c
--- /dev/null
+++ b/arch/arm/plat-mxc/iomux-mx1-mx2.c
@@ -0,0 +1,156 @@
+/*
+ *  arch/arm/mach-mxc/generic.c
+ *
+ *  author: Sascha Hauer
+ *  Created: april 20th, 2004
+ *  Copyright: Synertronixx GmbH
+ *
+ *  Common code for i.MX machines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/gpio.h>
+
+#include <asm/hardware.h>
+#include <asm/mach/map.h>
+#include <asm/arch/iomux-mx1-mx2.h>
+
+void mxc_gpio_mode(int gpio_mode)
+{
+        unsigned int pin = gpio_mode & GPIO_PIN_MASK;
+        unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+        unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
+        unsigned int tmp;
+
+        /* Pullup enable */
+        tmp = __raw_readl(VA_GPIO_BASE + MXC_PUEN(port));
+        if (gpio_mode & GPIO_PUEN)
+                tmp |= (1 << pin);
+        else
+                tmp &= ~(1 << pin);
+        __raw_writel(tmp, VA_GPIO_BASE + MXC_PUEN(port));
+
+        /* Data direction */
+        tmp = __raw_readl(VA_GPIO_BASE + MXC_DDIR(port));
+        if (gpio_mode & GPIO_OUT)
+                tmp |= 1 << pin;
+        else
+                tmp &= ~(1 << pin);
+        __raw_writel(tmp, VA_GPIO_BASE + MXC_DDIR(port));
+
+        /* Primary / alternate function */
+        tmp = __raw_readl(VA_GPIO_BASE + MXC_GPR(port));
+        if (gpio_mode & GPIO_AF)
+                tmp |= (1 << pin);
+        else
+                tmp &= ~(1 << pin);
+        __raw_writel(tmp, VA_GPIO_BASE + MXC_GPR(port));
+
+        /* use as gpio? */
+        tmp = __raw_readl(VA_GPIO_BASE + MXC_GIUS(port));
+        if (gpio_mode & (GPIO_PF | GPIO_AF))
+                tmp &= ~(1 << pin);
+        else
+                tmp |= (1 << pin);
+        __raw_writel(tmp, VA_GPIO_BASE + MXC_GIUS(port));
+
+        if (pin < 16) {
+                tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR1(port));
+                tmp &= ~(3 << (pin * 2));
+                tmp |= (ocr << (pin * 2));
+                __raw_writel(tmp, VA_GPIO_BASE + MXC_OCR1(port));
+
+                tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA1(port));
+                tmp &= ~(3 << (pin * 2));
+                tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
+                __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA1(port));
+
+                tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB1(port));
+                tmp &= ~(3 << (pin * 2));
+                tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
+                __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB1(port));
+        } else {
+                pin -= 16;
+
+                tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR2(port));
+                tmp &= ~(3 << (pin * 2));
+                tmp |= (ocr << (pin * 2));
+                __raw_writel(tmp, VA_GPIO_BASE + MXC_OCR2(port));
+
+                tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA2(port));
+                tmp &= ~(3 << (pin * 2));
+                tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
+                __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA2(port));
+
+                tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB2(port));
+                tmp &= ~(3 << (pin * 2));
+                tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
+                __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB2(port));
+        }
+}
+EXPORT_SYMBOL(mxc_gpio_mode);
+
+int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
+                                int alloc_mode, const char *label)
+{
+        const int *p = pin_list;
+        int i;
+        unsigned gpio;
+        unsigned mode;
+
+        for (i = 0; i < count; i++) {
+                gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
+                mode = *p & ~(GPIO_PIN_MASK | GPIO_PORT_MASK);
+
+                if (gpio >= (GPIO_PORT_MAX + 1) * 32)
+                        goto setup_error;
+
+                if (alloc_mode & MXC_GPIO_ALLOC_MODE_RELEASE)
+                        gpio_free(gpio);
+                else if (!(alloc_mode & MXC_GPIO_ALLOC_MODE_NO_ALLOC))
+                        if (gpio_request(gpio, label)
+                           && !(alloc_mode & MXC_GPIO_ALLOC_MODE_TRY_ALLOC))
+                                goto setup_error;
+
+                if (!(alloc_mode & (MXC_GPIO_ALLOC_MODE_ALLOC_ONLY |
+                                    MXC_GPIO_ALLOC_MODE_RELEASE)))
+                        mxc_gpio_mode(gpio | mode);
+
+                p++;
+        }
+        return 0;
+
+setup_error:
+        if (alloc_mode & (MXC_GPIO_ALLOC_MODE_NO_ALLOC |
+            MXC_GPIO_ALLOC_MODE_TRY_ALLOC))
+                return -EINVAL;
+
+        while (p != pin_list) {
+                p--;
+                gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
+                gpio_free(gpio);
+        }
+
+        return -EINVAL;
+}
+EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
+
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 2ad5a6917b3f..1fbe01da6925 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -1,24 +1,59 @@
 /*
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
  */
 
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <asm/hardware.h>
+#include <linux/irq.h>
 #include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
 #include <asm/arch/common.h>
 
+#define AVIC_BASE               IO_ADDRESS(AVIC_BASE_ADDR)
+#define AVIC_INTCNTL            (AVIC_BASE + 0x00)      /* int control reg */
+#define AVIC_NIMASK             (AVIC_BASE + 0x04)      /* int mask reg */
+#define AVIC_INTENNUM           (AVIC_BASE + 0x08)      /* int enable number reg */
+#define AVIC_INTDISNUM          (AVIC_BASE + 0x0C)      /* int disable number reg */
+#define AVIC_INTENABLEH         (AVIC_BASE + 0x10)      /* int enable reg high */
+#define AVIC_INTENABLEL         (AVIC_BASE + 0x14)      /* int enable reg low */
+#define AVIC_INTTYPEH           (AVIC_BASE + 0x18)      /* int type reg high */
+#define AVIC_INTTYPEL           (AVIC_BASE + 0x1C)      /* int type reg low */
+#define AVIC_NIPRIORITY7        (AVIC_BASE + 0x20)      /* norm int priority lvl7 */
+#define AVIC_NIPRIORITY6        (AVIC_BASE + 0x24)      /* norm int priority lvl6 */
+#define AVIC_NIPRIORITY5        (AVIC_BASE + 0x28)      /* norm int priority lvl5 */
+#define AVIC_NIPRIORITY4        (AVIC_BASE + 0x2C)      /* norm int priority lvl4 */
+#define AVIC_NIPRIORITY3        (AVIC_BASE + 0x30)      /* norm int priority lvl3 */
+#define AVIC_NIPRIORITY2        (AVIC_BASE + 0x34)      /* norm int priority lvl2 */
+#define AVIC_NIPRIORITY1        (AVIC_BASE + 0x38)      /* norm int priority lvl1 */
+#define AVIC_NIPRIORITY0        (AVIC_BASE + 0x3C)      /* norm int priority lvl0 */
+#define AVIC_NIVECSR            (AVIC_BASE + 0x40)      /* norm int vector/status */
+#define AVIC_FIVECSR            (AVIC_BASE + 0x44)      /* fast int vector/status */
+#define AVIC_INTSRCH            (AVIC_BASE + 0x48)      /* int source reg high */
+#define AVIC_INTSRCL            (AVIC_BASE + 0x4C)      /* int source reg low */
+#define AVIC_INTFRCH            (AVIC_BASE + 0x50)      /* int force reg high */
+#define AVIC_INTFRCL            (AVIC_BASE + 0x54)      /* int force reg low */
+#define AVIC_NIPNDH             (AVIC_BASE + 0x58)      /* norm int pending high */
+#define AVIC_NIPNDL             (AVIC_BASE + 0x5C)      /* norm int pending low */
+#define AVIC_FIPNDH             (AVIC_BASE + 0x60)      /* fast int pending high */
+#define AVIC_FIPNDL             (AVIC_BASE + 0x64)      /* fast int pending low */
+
+#define SYSTEM_PREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x20)
+#define SYSTEM_SREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x24)
+#define IIM_PROD_REV_SH         3
+#define IIM_PROD_REV_LEN        5
+
 /* Disable interrupt number "irq" in the AVIC */
 static void mxc_mask_irq(unsigned int irq)
 {
@@ -32,7 +67,7 @@ static void mxc_unmask_irq(unsigned int irq)
 }
 
 static struct irq_chip mxc_avic_chip = {
-        .mask_ack = mxc_mask_irq,
+        .ack = mxc_mask_irq,
         .mask = mxc_mask_irq,
         .unmask = mxc_unmask_irq,
 };
@@ -71,5 +106,8 @@ void __init mxc_init_irq(void)
         reg |= (0xF << 28);
         __raw_writel(reg, AVIC_NIPRIORITY6);
 
+        /* init architectures chained interrupt handler */
+        mxc_register_gpios();
+
         printk(KERN_INFO "MXC IRQ initialized\n");
 }
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
new file mode 100644
index 000000000000..3bf86343fdf4
--- /dev/null
+++ b/arch/arm/plat-mxc/time.c
@@ -0,0 +1,228 @@
+/*
+ *  linux/arch/arm/plat-mxc/time.c
+ *
+ *  Copyright (C) 2000-2001 Deep Blue Solutions
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
+ *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+
+#include <asm/hardware.h>
+#include <asm/mach/time.h>
+#include <asm/arch/common.h>
+#include <asm/arch/mxc_timer.h>
+
+static struct clock_event_device clockevent_mxc;
+static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
+
+/* clock source for the timer */
+static struct clk *timer_clk;
+
+/* clock source */
+
+static cycle_t mxc_get_cycles(void)
+{
+        return __raw_readl(TIMER_BASE + MXC_TCN);
+}
+
+static struct clocksource clocksource_mxc = {
+        .name           = "mxc_timer1",
+        .rating         = 200,
+        .read           = mxc_get_cycles,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .shift          = 20,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static int __init mxc_clocksource_init(void)
+{
+        unsigned int clock;
+
+        clock = clk_get_rate(timer_clk);
+
+        clocksource_mxc.mult = clocksource_hz2mult(clock,
+                                        clocksource_mxc.shift);
+        clocksource_register(&clocksource_mxc);
+
+        return 0;
+}
+
+/* clock event */
+
+static int mxc_set_next_event(unsigned long evt,
+                              struct clock_event_device *unused)
+{
+        unsigned long tcmp;
+
+        tcmp = __raw_readl(TIMER_BASE + MXC_TCN) + evt;
+        __raw_writel(tcmp, TIMER_BASE + MXC_TCMP);
+
+        return (int)(tcmp - __raw_readl(TIMER_BASE + MXC_TCN)) < 0 ?
+                                -ETIME : 0;
+}
+
+#ifdef DEBUG
+static const char *clock_event_mode_label[] = {
+        [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
+        [CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
+        [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
+        [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED"
+};
+#endif /* DEBUG */
+
+static void mxc_set_mode(enum clock_event_mode mode,
+                                struct clock_event_device *evt)
+{
+        unsigned long flags;
+
+        /*
+         * The timer interrupt generation is disabled at least
+         * for enough time to call mxc_set_next_event()
+         */
+        local_irq_save(flags);
+
+        /* Disable interrupt in GPT module */
+        gpt_irq_disable();
+
+        if (mode != clockevent_mode) {
+                /* Set event time into far-far future */
+                __raw_writel(__raw_readl(TIMER_BASE + MXC_TCN) - 3,
+                                TIMER_BASE + MXC_TCMP);
+                /* Clear pending interrupt */
+                gpt_irq_acknowledge();
+        }
+
+#ifdef DEBUG
+        printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
+                clock_event_mode_label[clockevent_mode],
+                clock_event_mode_label[mode]);
+#endif /* DEBUG */
+
+        /* Remember timer mode */
+        clockevent_mode = mode;
+        local_irq_restore(flags);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
+                                "supported for i.MX\n");
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+        /*
+         * Do not put overhead of interrupt enable/disable into
+         * mxc_set_next_event(), the core has about 4 minutes
+         * to call mxc_set_next_event() or shutdown clock after
+         * mode switching
+         */
+                local_irq_save(flags);
+                gpt_irq_enable();
+                local_irq_restore(flags);
+                break;
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_RESUME:
+                /* Left event sources disabled, no more interrupts appear */
+                break;
+        }
+}
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = &clockevent_mxc;
+        uint32_t tstat;
+
+        tstat = __raw_readl(TIMER_BASE + MXC_TSTAT);
+
+        gpt_irq_acknowledge();
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction mxc_timer_irq = {
+        .name           = "i.MX Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = mxc_timer_interrupt,
+};
+
+static struct clock_event_device clockevent_mxc = {
+        .name           = "mxc_timer1",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .set_mode       = mxc_set_mode,
+        .set_next_event = mxc_set_next_event,
+        .rating         = 200,
+};
+
+static int __init mxc_clockevent_init(void)
+{
+        unsigned int clock;
+
+        clock = clk_get_rate(timer_clk);
+
+        clockevent_mxc.mult = div_sc(clock, NSEC_PER_SEC,
+                                        clockevent_mxc.shift);
+        clockevent_mxc.max_delta_ns =
+                        clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
+        clockevent_mxc.min_delta_ns =
+                        clockevent_delta2ns(0xff, &clockevent_mxc);
+
+        clockevent_mxc.cpumask = cpumask_of_cpu(0);
+
+        clockevents_register_device(&clockevent_mxc);
+
+        return 0;
+}
+
+void __init mxc_timer_init(const char *clk_timer)
+{
+        timer_clk = clk_get(NULL, clk_timer);
+        if (!timer_clk) {
+                printk(KERN_ERR"Cannot determine timer clock. Giving up.\n");
+                return;
+        }
+
+        clk_enable(timer_clk);
+
+        /*
+         * Initialise to a known state (all timers off, and timing reset)
+         */
+        __raw_writel(0, TIMER_BASE + MXC_TCTL);
+        __raw_writel(0, TIMER_BASE + MXC_TPRER); /* see datasheet note */
+
+        __raw_writel(TCTL_FRR | /* free running */
+                     TCTL_VAL | /* set clocksource and arch specific bits */
+                     TCTL_TEN,  /* start the timer */
+                     TIMER_BASE + MXC_TCTL);
+
+        /* init and register the timer to the framework */
+        mxc_clocksource_init();
+        mxc_clockevent_init();
+
+        /* Make irqs happen */
+        setup_irq(TIMER_INTERRUPT, &mxc_timer_irq);
+}
+
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index bc639a30d6d1..2c4051cc79a1 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Common support
-obj-y := common.o sram.o sram-fn.o clock.o devices.o dma.o mux.o gpio.o \
+obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
          usb.o fb.o
 obj-m :=
 obj-n :=
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 2db5580048d8..c2e741de0203 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -1,7 +1,7 @@
 /*
  *  linux/arch/arm/plat-omap/clock.c
  *
- *  Copyright (C) 2004 - 2005 Nokia corporation
+ *  Copyright (C) 2004 - 2008 Nokia corporation
  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  *
  *  Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
@@ -22,6 +22,7 @@
 #include <linux/mutex.h>
 #include <linux/platform_device.h>
 #include <linux/cpufreq.h>
+#include <linux/debugfs.h>
 
 #include <asm/io.h>
 
@@ -33,41 +34,6 @@ static DEFINE_SPINLOCK(clockfw_lock);
 
 static struct clk_functions *arch_clock;
 
-#ifdef CONFIG_PM_DEBUG
-
-static void print_parents(struct clk *clk)
-{
-        struct clk *p;
-        int printed = 0;
-
-        list_for_each_entry(p, &clocks, node) {
-                if (p->parent == clk && p->usecount) {
-                        if (!clk->usecount && !printed) {
-                                printk("MISMATCH: %s\n", clk->name);
-                                printed = 1;
-                        }
-                        printk("\t%-15s\n", p->name);
-                }
-        }
-}
-
-void clk_print_usecounts(void)
-{
-        unsigned long flags;
-        struct clk *p;
-
-        spin_lock_irqsave(&clockfw_lock, flags);
-        list_for_each_entry(p, &clocks, node) {
-                if (p->usecount)
-                        printk("%-15s: %d\n", p->name, p->usecount);
-                print_parents(p);
-
-        }
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-}
-
-#endif
-
 /*-------------------------------------------------------------------------
  * Standard clock functions defined in include/linux/clk.h
  *-------------------------------------------------------------------------*/
@@ -446,3 +412,93 @@ int __init clk_init(struct clk_functions * custom_clocks)
         return 0;
 }
 
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+/*
+ *      debugfs support to trace clock tree hierarchy and attributes
+ */
+static struct dentry *clk_debugfs_root;
+
+static int clk_debugfs_register_one(struct clk *c)
+{
+        int err;
+        struct dentry *d, *child;
+        struct clk *pa = c->parent;
+        char s[255];
+        char *p = s;
+
+        p += sprintf(p, "%s", c->name);
+        if (c->id != 0)
+                sprintf(p, ":%d", c->id);
+        d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
+        if (IS_ERR(d))
+                return PTR_ERR(d);
+        c->dent = d;
+
+        d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
+        if (IS_ERR(d)) {
+                err = PTR_ERR(d);
+                goto err_out;
+        }
+        d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
+        if (IS_ERR(d)) {
+                err = PTR_ERR(d);
+                goto err_out;
+        }
+        d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
+        if (IS_ERR(d)) {
+                err = PTR_ERR(d);
+                goto err_out;
+        }
+        return 0;
+
+err_out:
+        d = c->dent;
+        list_for_each_entry(child, &d->d_subdirs, d_u.d_child)
+                debugfs_remove(child);
+        debugfs_remove(c->dent);
+        return err;
+}
+
+static int clk_debugfs_register(struct clk *c)
+{
+        int err;
+        struct clk *pa = c->parent;
+
+        if (pa && !pa->dent) {
+                err = clk_debugfs_register(pa);
+                if (err)
+                        return err;
+        }
+
+        if (!c->dent) {
+                err = clk_debugfs_register_one(c);
+                if (err)
+                        return err;
+        }
+        return 0;
+}
+
+static int __init clk_debugfs_init(void)
+{
+        struct clk *c;
+        struct dentry *d;
+        int err;
+
+        d = debugfs_create_dir("clock", NULL);
+        if (IS_ERR(d))
+                return PTR_ERR(d);
+        clk_debugfs_root = d;
+
+        list_for_each_entry(c, &clocks, node) {
+                err = clk_debugfs_register(c);
+                if (err)
+                        goto err_out;
+        }
+        return 0;
+err_out:
+        debugfs_remove(clk_debugfs_root); /* REVISIT: Cleanup correctly */
+        return err;
+}
+late_initcall(clk_debugfs_init);
+
+#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index bd1cef2c3c14..8d04929a3c75 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -26,6 +26,7 @@
 #include <asm/io.h>
 #include <asm/setup.h>
 
+#include <asm/arch/common.h>
 #include <asm/arch/board.h>
 #include <asm/arch/control.h>
 #include <asm/arch/mux.h>
@@ -241,30 +242,70 @@ arch_initcall(omap_init_clocksource_32k);
 
 /* Global address base setup code */
 
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+
+static struct omap_globals *omap2_globals;
+
+static void __init __omap2_set_globals(void)
+{
+        omap2_set_globals_memory(omap2_globals);
+        omap2_set_globals_control(omap2_globals);
+        omap2_set_globals_prcm(omap2_globals);
+}
+
+#endif
+
 #if defined(CONFIG_ARCH_OMAP2420)
+
+static struct omap_globals omap242x_globals = {
+        .tap    = (__force void __iomem *)OMAP2_IO_ADDRESS(0x48014000),
+        .sdrc   = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
+        .sms    = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
+        .ctrl   = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
+        .prm    = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
+        .cm     = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
+};
+
 void __init omap2_set_globals_242x(void)
 {
-        omap2_sdrc_base = OMAP2420_SDRC_BASE;
-        omap2_sms_base = OMAP2420_SMS_BASE;
-        omap_ctrl_base_set(OMAP2420_CTRL_BASE);
+        omap2_globals = &omap242x_globals;
+        __omap2_set_globals();
 }
 #endif
 
 #if defined(CONFIG_ARCH_OMAP2430)
+
+static struct omap_globals omap243x_globals = {
+        .tap    = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4900a000),
+        .sdrc   = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
+        .sms    = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
+        .ctrl   = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE),
+        .prm    = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE),
+        .cm     = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_CM_BASE),
+};
+
 void __init omap2_set_globals_243x(void)
 {
-        omap2_sdrc_base = OMAP243X_SDRC_BASE;
-        omap2_sms_base = OMAP243X_SMS_BASE;
-        omap_ctrl_base_set(OMAP243X_CTRL_BASE);
+        omap2_globals = &omap243x_globals;
+        __omap2_set_globals();
 }
 #endif
 
 #if defined(CONFIG_ARCH_OMAP3430)
+
+static struct omap_globals omap343x_globals = {
+        .tap    = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4830A000),
+        .sdrc   = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
+        .sms    = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
+        .ctrl   = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE),
+        .prm    = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE),
+        .cm     = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_CM_BASE),
+};
+
 void __init omap2_set_globals_343x(void)
 {
-        omap2_sdrc_base = OMAP343X_SDRC_BASE;
-        omap2_sms_base = OMAP343X_SMS_BASE;
-        omap_ctrl_base_set(OMAP343X_CTRL_BASE);
+        omap2_globals = &omap343x_globals;
+        __omap2_set_globals();
 }
 #endif
 
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 4a53f9ba6c43..81002b722da1 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -24,6 +24,7 @@
 #include <asm/arch/mux.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/menelaus.h>
+#include <asm/arch/mcbsp.h>
 
 #if     defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
 
@@ -145,6 +146,53 @@ static inline void omap_init_kp(void) {}
 #endif
 
 /*-------------------------------------------------------------------------*/
+#if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE)
+
+static struct platform_device **omap_mcbsp_devices;
+
+void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
+                                        int size)
+{
+        int i;
+
+        if (size > OMAP_MAX_MCBSP_COUNT) {
+                printk(KERN_WARNING "Registered too many McBSPs platform_data."
+                        " Using maximum (%d) available.\n",
+                        OMAP_MAX_MCBSP_COUNT);
+                size = OMAP_MAX_MCBSP_COUNT;
+        }
+
+        omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *),
+                                     GFP_KERNEL);
+        if (!omap_mcbsp_devices) {
+                printk(KERN_ERR "Could not register McBSP devices\n");
+                return;
+        }
+
+        for (i = 0; i < size; i++) {
+                struct platform_device *new_mcbsp;
+                int ret;
+
+                new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
+                if (!new_mcbsp)
+                        continue;
+                new_mcbsp->dev.platform_data = &config[i];
+                ret = platform_device_add(new_mcbsp);
+                if (ret) {
+                        platform_device_put(new_mcbsp);
+                        continue;
+                }
+                omap_mcbsp_devices[i] = new_mcbsp;
+        }
+}
+
+#else
+void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
+                                        int size)
+{  }
+#endif
+
+/*-------------------------------------------------------------------------*/
 
 #if     defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
 
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 39c637b0ffea..fac8e994f588 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1,7 +1,7 @@
 /*
  * linux/arch/arm/plat-omap/dma.c
  *
- * Copyright (C) 2003 Nokia Corporation
+ * Copyright (C) 2003 - 2008 Nokia Corporation
  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
  * Graphics DMA and LCD DMA graphics tranformations
@@ -25,11 +25,11 @@
 #include <linux/errno.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 
 #include <asm/system.h>
 #include <asm/hardware.h>
 #include <asm/dma.h>
-#include <asm/io.h>
 
 #include <asm/arch/tc.h>
 
@@ -43,13 +43,13 @@ enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
 #endif
 
-#define OMAP_DMA_ACTIVE         0x01
-#define OMAP_DMA_CCR_EN         (1 << 7)
+#define OMAP_DMA_ACTIVE                 0x01
+#define OMAP_DMA_CCR_EN                 (1 << 7)
 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
 
-#define OMAP_FUNC_MUX_ARM_BASE  (0xfffe1000 + 0xec)
+#define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
 
-static int enable_1510_mode = 0;
+static int enable_1510_mode;
 
 struct omap_dma_lch {
         int next_lch;
@@ -57,7 +57,7 @@ struct omap_dma_lch {
         u16 saved_csr;
         u16 enabled_irqs;
         const char *dev_name;
-        void (* callback)(int lch, u16 ch_status, void *data);
+        void (*callback)(int lch, u16 ch_status, void *data);
         void *data;
 
 #ifndef CONFIG_ARCH_OMAP1
@@ -72,7 +72,6 @@ struct omap_dma_lch {
         long flags;
 };
 
-#ifndef CONFIG_ARCH_OMAP1
 struct dma_link_info {
         int *linked_dmach_q;
         int no_of_lchs_linked;
@@ -86,7 +85,9 @@ struct dma_link_info {
 
 };
 
-static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT];
+static struct dma_link_info *dma_linked_lch;
+
+#ifndef CONFIG_ARCH_OMAP1
 
 /* Chain handling macros */
 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
@@ -119,12 +120,15 @@ static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT];
                 dma_linked_lch[chain_id].q_count++; \
         } while (0)
 #endif
+
+static int dma_lch_count;
 static int dma_chan_count;
 
 static spinlock_t dma_chan_lock;
-static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
+static struct omap_dma_lch *dma_chan;
+static void __iomem *omap_dma_base;
 
-static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
+static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
@@ -139,6 +143,24 @@ static inline void omap_enable_channel_irq(int lch);
 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
                                                 __func__);
 
+#define dma_read(reg)                                                   \
+({                                                                      \
+        u32 __val;                                                      \
+        if (cpu_class_is_omap1())                                       \
+                __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
+        else                                                            \
+                __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
+        __val;                                                          \
+})
+
+#define dma_write(val, reg)                                             \
+({                                                                      \
+        if (cpu_class_is_omap1())                                       \
+                __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
+        else                                                            \
+                __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
+})
+
 #ifdef CONFIG_ARCH_OMAP15XX
 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 int omap_dma_in_1510_mode(void)
@@ -173,13 +195,14 @@ static inline void set_gdma_dev(int req, int dev)
 #define set_gdma_dev(req, dev)  do {} while (0)
 #endif
 
+/* Omap1 only */
 static void clear_lch_regs(int lch)
 {
         int i;
-        u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
+        void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
 
         for (i = 0; i < 0x2c; i += 2)
-                omap_writew(0, lch_base + i);
+                __raw_writew(0, lch_base + i);
 }
 
 void omap_set_dma_priority(int lch, int dst_port, int priority)
@@ -212,33 +235,49 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
         }
 
         if (cpu_class_is_omap2()) {
+                u32 ccr;
+
+                ccr = dma_read(CCR(lch));
                 if (priority)
-                        OMAP_DMA_CCR_REG(lch) |= (1 << 6);
+                        ccr |= (1 << 6);
                 else
-                        OMAP_DMA_CCR_REG(lch) &= ~(1 << 6);
+                        ccr &= ~(1 << 6);
+                dma_write(ccr, CCR(lch));
         }
 }
+EXPORT_SYMBOL(omap_set_dma_priority);
 
 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
                                   int frame_count, int sync_mode,
                                   int dma_trigger, int src_or_dst_synch)
 {
-        OMAP_DMA_CSDP_REG(lch) &= ~0x03;
-        OMAP_DMA_CSDP_REG(lch) |= data_type;
+        u32 l;
+
+        l = dma_read(CSDP(lch));
+        l &= ~0x03;
+        l |= data_type;
+        dma_write(l, CSDP(lch));
 
         if (cpu_class_is_omap1()) {
-                OMAP_DMA_CCR_REG(lch) &= ~(1 << 5);
+                u16 ccr;
+
+                ccr = dma_read(CCR(lch));
+                ccr &= ~(1 << 5);
                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
-                        OMAP_DMA_CCR_REG(lch) |= 1 << 5;
+                        ccr |= 1 << 5;
+                dma_write(ccr, CCR(lch));
 
-                OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2);
+                ccr = dma_read(CCR2(lch));
+                ccr &= ~(1 << 2);
                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
-                        OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
+                        ccr |= 1 << 2;
+                dma_write(ccr, CCR2(lch));
         }
 
         if (cpu_class_is_omap2() && dma_trigger) {
-                u32 val = OMAP_DMA_CCR_REG(lch);
+                u32 val;
 
+                val = dma_read(CCR(lch));
                 val &= ~(3 << 19);
                 if (dma_trigger > 63)
                         val |= 1 << 20;
@@ -263,12 +302,13 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
                 else
                         val &= ~(1 << 24);      /* dest synch */
 
-                OMAP_DMA_CCR_REG(lch) = val;
+                dma_write(val, CCR(lch));
         }
 
-        OMAP_DMA_CEN_REG(lch) = elem_count;
-        OMAP_DMA_CFN_REG(lch) = frame_count;
+        dma_write(elem_count, CEN(lch));
+        dma_write(frame_count, CFN(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_transfer_params);
 
 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 {
@@ -281,7 +321,9 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
                 return;
         }
 
-        w = OMAP1_DMA_CCR2_REG(lch) & ~0x03;
+        w = dma_read(CCR2(lch));
+        w &= ~0x03;
+
         switch (mode) {
         case OMAP_DMA_CONSTANT_FILL:
                 w |= 0x01;
@@ -294,52 +336,81 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
         default:
                 BUG();
         }
-        OMAP1_DMA_CCR2_REG(lch) = w;
+        dma_write(w, CCR2(lch));
 
-        w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f;
+        w = dma_read(LCH_CTRL(lch));
+        w &= ~0x0f;
         /* Default is channel type 2D */
         if (mode) {
-                OMAP1_DMA_COLOR_L_REG(lch) = (u16)color;
-                OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16);
+                dma_write((u16)color, COLOR_L(lch));
+                dma_write((u16)(color >> 16), COLOR_U(lch));
                 w |= 1;         /* Channel type G */
         }
-        OMAP1_DMA_LCH_CTRL_REG(lch) = w;
+        dma_write(w, LCH_CTRL(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_color_mode);
 
 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 {
         if (cpu_class_is_omap2()) {
-                OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16);
-                OMAP_DMA_CSDP_REG(lch) |= (mode << 16);
+                u32 csdp;
+
+                csdp = dma_read(CSDP(lch));
+                csdp &= ~(0x3 << 16);
+                csdp |= (mode << 16);
+                dma_write(csdp, CSDP(lch));
+        }
+}
+EXPORT_SYMBOL(omap_set_dma_write_mode);
+
+void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
+{
+        if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
+                u32 l;
+
+                l = dma_read(LCH_CTRL(lch));
+                l &= ~0x7;
+                l |= mode;
+                dma_write(l, LCH_CTRL(lch));
         }
 }
+EXPORT_SYMBOL(omap_set_dma_channel_mode);
 
 /* Note that src_port is only for omap1 */
 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
                              unsigned long src_start,
                              int src_ei, int src_fi)
 {
+        u32 l;
+
         if (cpu_class_is_omap1()) {
-                OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2);
-                OMAP_DMA_CSDP_REG(lch) |= src_port << 2;
+                u16 w;
+
+                w = dma_read(CSDP(lch));
+                w &= ~(0x1f << 2);
+                w |= src_port << 2;
+                dma_write(w, CSDP(lch));
         }
 
-        OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12);
-        OMAP_DMA_CCR_REG(lch) |= src_amode << 12;
+        l = dma_read(CCR(lch));
+        l &= ~(0x03 << 12);
+        l |= src_amode << 12;
+        dma_write(l, CCR(lch));
 
         if (cpu_class_is_omap1()) {
-                OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16;
-                OMAP1_DMA_CSSA_L_REG(lch) = src_start;
+                dma_write(src_start >> 16, CSSA_U(lch));
+                dma_write((u16)src_start, CSSA_L(lch));
         }
 
         if (cpu_class_is_omap2())
-                OMAP2_DMA_CSSA_REG(lch) = src_start;
+                dma_write(src_start, CSSA(lch));
 
-        OMAP_DMA_CSEI_REG(lch) = src_ei;
-        OMAP_DMA_CSFI_REG(lch) = src_fi;
+        dma_write(src_ei, CSEI(lch));
+        dma_write(src_fi, CSFI(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_src_params);
 
-void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
+void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 {
         omap_set_dma_transfer_params(lch, params->data_type,
                                      params->elem_count, params->frame_count,
@@ -356,28 +427,37 @@ void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
                 omap_dma_set_prio_lch(lch, params->read_prio,
                                       params->write_prio);
 }
+EXPORT_SYMBOL(omap_set_dma_params);
 
 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 {
-        if (cpu_class_is_omap2()) {
-                REVISIT_24XX();
+        if (cpu_class_is_omap2())
                 return;
-        }
-        OMAP_DMA_CSEI_REG(lch) = eidx;
-        OMAP_DMA_CSFI_REG(lch) = fidx;
+
+        dma_write(eidx, CSEI(lch));
+        dma_write(fidx, CSFI(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_src_index);
 
 void omap_set_dma_src_data_pack(int lch, int enable)
 {
-        OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6);
+        u32 l;
+
+        l = dma_read(CSDP(lch));
+        l &= ~(1 << 6);
         if (enable)
-                OMAP_DMA_CSDP_REG(lch) |= (1 << 6);
+                l |= (1 << 6);
+        dma_write(l, CSDP(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 
 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 {
         unsigned int burst = 0;
-        OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
+        u32 l;
+
+        l = dma_read(CSDP(lch));
+        l &= ~(0x03 << 7);
 
         switch (burst_mode) {
         case OMAP_DMA_DATA_BURST_DIS:
@@ -408,55 +488,73 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
         default:
                 BUG();
         }
-        OMAP_DMA_CSDP_REG(lch) |= (burst << 7);
+
+        l |= (burst << 7);
+        dma_write(l, CSDP(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 
 /* Note that dest_port is only for OMAP1 */
 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
                               unsigned long dest_start,
                               int dst_ei, int dst_fi)
 {
+        u32 l;
+
         if (cpu_class_is_omap1()) {
-                OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9);
-                OMAP_DMA_CSDP_REG(lch) |= dest_port << 9;
+                l = dma_read(CSDP(lch));
+                l &= ~(0x1f << 9);
+                l |= dest_port << 9;
+                dma_write(l, CSDP(lch));
         }
 
-        OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14);
-        OMAP_DMA_CCR_REG(lch) |= dest_amode << 14;
+        l = dma_read(CCR(lch));
+        l &= ~(0x03 << 14);
+        l |= dest_amode << 14;
+        dma_write(l, CCR(lch));
 
         if (cpu_class_is_omap1()) {
-                OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16;
-                OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
+                dma_write(dest_start >> 16, CDSA_U(lch));
+                dma_write(dest_start, CDSA_L(lch));
         }
 
         if (cpu_class_is_omap2())
-                OMAP2_DMA_CDSA_REG(lch) = dest_start;
+                dma_write(dest_start, CDSA(lch));
 
-        OMAP_DMA_CDEI_REG(lch) = dst_ei;
-        OMAP_DMA_CDFI_REG(lch) = dst_fi;
+        dma_write(dst_ei, CDEI(lch));
+        dma_write(dst_fi, CDFI(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_dest_params);
 
 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 {
-        if (cpu_class_is_omap2()) {
-                REVISIT_24XX();
+        if (cpu_class_is_omap2())
                 return;
-        }
-        OMAP_DMA_CDEI_REG(lch) = eidx;
-        OMAP_DMA_CDFI_REG(lch) = fidx;
+
+        dma_write(eidx, CDEI(lch));
+        dma_write(fidx, CDFI(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_dest_index);
 
 void omap_set_dma_dest_data_pack(int lch, int enable)
 {
-        OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13);
+        u32 l;
+
+        l = dma_read(CSDP(lch));
+        l &= ~(1 << 13);
         if (enable)
-                OMAP_DMA_CSDP_REG(lch) |= 1 << 13;
+                l |= 1 << 13;
+        dma_write(l, CSDP(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 
 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 {
         unsigned int burst = 0;
-        OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
+        u32 l;
+
+        l = dma_read(CSDP(lch));
+        l &= ~(0x03 << 14);
 
         switch (burst_mode) {
         case OMAP_DMA_DATA_BURST_DIS:
@@ -486,8 +584,10 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
                 BUG();
                 return;
         }
-        OMAP_DMA_CSDP_REG(lch) |= (burst << 14);
+        l |= (burst << 14);
+        dma_write(l, CSDP(lch));
 }
+EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 
 static inline void omap_enable_channel_irq(int lch)
 {
@@ -495,62 +595,74 @@ static inline void omap_enable_channel_irq(int lch)
 
         /* Clear CSR */
         if (cpu_class_is_omap1())
-                status = OMAP_DMA_CSR_REG(lch);
+                status = dma_read(CSR(lch));
         else if (cpu_class_is_omap2())
-                OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
+                dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 
         /* Enable some nice interrupts. */
-        OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
+        dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
 }
 
 static void omap_disable_channel_irq(int lch)
 {
         if (cpu_class_is_omap2())
-                OMAP_DMA_CICR_REG(lch) = 0;
+                dma_write(0, CICR(lch));
 }
 
 void omap_enable_dma_irq(int lch, u16 bits)
 {
         dma_chan[lch].enabled_irqs |= bits;
 }
+EXPORT_SYMBOL(omap_enable_dma_irq);
 
 void omap_disable_dma_irq(int lch, u16 bits)
 {
         dma_chan[lch].enabled_irqs &= ~bits;
 }
+EXPORT_SYMBOL(omap_disable_dma_irq);
 
 static inline void enable_lnk(int lch)
 {
+        u32 l;
+
+        l = dma_read(CLNK_CTRL(lch));
+
         if (cpu_class_is_omap1())
-                OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14);
+                l &= ~(1 << 14);
 
         /* Set the ENABLE_LNK bits */
         if (dma_chan[lch].next_lch != -1)
-                OMAP_DMA_CLNK_CTRL_REG(lch) =
-                        dma_chan[lch].next_lch | (1 << 15);
+                l = dma_chan[lch].next_lch | (1 << 15);
 
 #ifndef CONFIG_ARCH_OMAP1
-        if (dma_chan[lch].next_linked_ch != -1)
-                OMAP_DMA_CLNK_CTRL_REG(lch) =
-                        dma_chan[lch].next_linked_ch | (1 << 15);
+        if (cpu_class_is_omap2())
+                if (dma_chan[lch].next_linked_ch != -1)
+                        l = dma_chan[lch].next_linked_ch | (1 << 15);
 #endif
+
+        dma_write(l, CLNK_CTRL(lch));
 }
 
 static inline void disable_lnk(int lch)
 {
+        u32 l;
+
+        l = dma_read(CLNK_CTRL(lch));
+
         /* Disable interrupts */
         if (cpu_class_is_omap1()) {
-                OMAP_DMA_CICR_REG(lch) = 0;
+                dma_write(0, CICR(lch));
                 /* Set the STOP_LNK bit */
-                OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
+                l |= 1 << 14;
         }
 
         if (cpu_class_is_omap2()) {
                 omap_disable_channel_irq(lch);
                 /* Clear the ENABLE_LNK bit */
-                OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
+                l &= ~(1 << 15);
         }
 
+        dma_write(l, CLNK_CTRL(lch));
         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 }
 
@@ -561,13 +673,13 @@ static inline void omap2_enable_irq_lch(int lch)
         if (!cpu_class_is_omap2())
                 return;
 
-        val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
+        val = dma_read(IRQENABLE_L0);
         val |= 1 << lch;
-        omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
+        dma_write(val, IRQENABLE_L0);
 }
 
 int omap_request_dma(int dev_id, const char *dev_name,
-                     void (* callback)(int lch, u16 ch_status, void *data),
+                     void (*callback)(int lch, u16 ch_status, void *data),
                      void *data, int *dma_ch_out)
 {
         int ch, free_ch = -1;
@@ -600,10 +712,14 @@ int omap_request_dma(int dev_id, const char *dev_name,
         chan->dev_name = dev_name;
         chan->callback = callback;
         chan->data = data;
+
 #ifndef CONFIG_ARCH_OMAP1
-        chan->chain_id = -1;
-        chan->next_linked_ch = -1;
+        if (cpu_class_is_omap2()) {
+                chan->chain_id = -1;
+                chan->next_linked_ch = -1;
+        }
 #endif
+
         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 
         if (cpu_class_is_omap1())
@@ -618,26 +734,28 @@ int omap_request_dma(int dev_id, const char *dev_name,
                         set_gdma_dev(free_ch + 1, dev_id);
                         dev_id = free_ch + 1;
                 }
-                /* Disable the 1510 compatibility mode and set the sync device
-                 * id. */
-                OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10);
+                /*
+                 * Disable the 1510 compatibility mode and set the sync device
+                 * id.
+                 */
+                dma_write(dev_id | (1 << 10), CCR(free_ch));
         } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
-                OMAP_DMA_CCR_REG(free_ch) = dev_id;
+                dma_write(dev_id, CCR(free_ch));
         }
 
         if (cpu_class_is_omap2()) {
                 omap2_enable_irq_lch(free_ch);
-
                 omap_enable_channel_irq(free_ch);
                 /* Clear the CSR register and IRQ status register */
-                OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK;
-                omap_writel(1 << free_ch, OMAP_DMA4_IRQSTATUS_L0);
+                dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
+                dma_write(1 << free_ch, IRQSTATUS_L0);
         }
 
         *dma_ch_out = free_ch;
 
         return 0;
 }
+EXPORT_SYMBOL(omap_request_dma);
 
 void omap_free_dma(int lch)
 {
@@ -645,11 +763,12 @@ void omap_free_dma(int lch)
 
         spin_lock_irqsave(&dma_chan_lock, flags);
         if (dma_chan[lch].dev_id == -1) {
-                printk("omap_dma: trying to free nonallocated DMA channel %d\n",
+                pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
                        lch);
                 spin_unlock_irqrestore(&dma_chan_lock, flags);
                 return;
         }
+
         dma_chan[lch].dev_id = -1;
         dma_chan[lch].next_lch = -1;
         dma_chan[lch].callback = NULL;
@@ -657,30 +776,31 @@ void omap_free_dma(int lch)
 
         if (cpu_class_is_omap1()) {
                 /* Disable all DMA interrupts for the channel. */
-                OMAP_DMA_CICR_REG(lch) = 0;
+                dma_write(0, CICR(lch));
                 /* Make sure the DMA transfer is stopped. */
-                OMAP_DMA_CCR_REG(lch) = 0;
+                dma_write(0, CCR(lch));
         }
 
         if (cpu_class_is_omap2()) {
                 u32 val;
                 /* Disable interrupts */
-                val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
+                val = dma_read(IRQENABLE_L0);
                 val &= ~(1 << lch);
-                omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
+                dma_write(val, IRQENABLE_L0);
 
                 /* Clear the CSR register and IRQ status register */
-                OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
-                omap_writel(1 << lch, OMAP_DMA4_IRQSTATUS_L0);
+                dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
+                dma_write(1 << lch, IRQSTATUS_L0);
 
                 /* Disable all DMA interrupts for the channel. */
-                OMAP_DMA_CICR_REG(lch) = 0;
+                dma_write(0, CICR(lch));
 
                 /* Make sure the DMA transfer is stopped. */
-                OMAP_DMA_CCR_REG(lch) = 0;
+                dma_write(0, CCR(lch));
                 omap_clear_dma(lch);
         }
 }
+EXPORT_SYMBOL(omap_free_dma);
 
 /**
  * @brief omap_dma_set_global_params : Set global priority settings for dma
@@ -708,7 +828,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
         reg = (arb_rate & 0xff) << 16;
         reg |= (0xff & max_fifo_depth);
 
-        omap_writel(reg, OMAP_DMA4_GCR_REG);
+        dma_write(reg, GCR);
 }
 EXPORT_SYMBOL(omap_dma_set_global_params);
 
@@ -725,20 +845,21 @@ int
 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
                       unsigned char write_prio)
 {
-        u32 w;
+        u32 l;
 
-        if (unlikely((lch < 0 || lch >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+        if (unlikely((lch < 0 || lch >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid channel id\n");
                 return -EINVAL;
         }
-        w = OMAP_DMA_CCR_REG(lch);
-        w &= ~((1 << 6) | (1 << 26));
+        l = dma_read(CCR(lch));
+        l &= ~((1 << 6) | (1 << 26));
         if (cpu_is_omap2430() || cpu_is_omap34xx())
-                w |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
+                l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
         else
-                w |= ((read_prio & 0x1) << 6);
+                l |= ((read_prio & 0x1) << 6);
+
+        dma_write(l, CCR(lch));
 
-        OMAP_DMA_CCR_REG(lch) = w;
         return 0;
 }
 EXPORT_SYMBOL(omap_dma_set_prio_lch);
@@ -754,28 +875,34 @@ void omap_clear_dma(int lch)
         local_irq_save(flags);
 
         if (cpu_class_is_omap1()) {
-                int status;
-                OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
+                u32 l;
+
+                l = dma_read(CCR(lch));
+                l &= ~OMAP_DMA_CCR_EN;
+                dma_write(l, CCR(lch));
 
                 /* Clear pending interrupts */
-                status = OMAP_DMA_CSR_REG(lch);
+                l = dma_read(CSR(lch));
         }
 
         if (cpu_class_is_omap2()) {
                 int i;
-                u32 lch_base = OMAP_DMA4_BASE + lch * 0x60 + 0x80;
+                void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
                 for (i = 0; i < 0x44; i += 4)
-                        omap_writel(0, lch_base + i);
+                        __raw_writel(0, lch_base + i);
         }
 
         local_irq_restore(flags);
 }
+EXPORT_SYMBOL(omap_clear_dma);
 
 void omap_start_dma(int lch)
 {
+        u32 l;
+
         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                 int next_lch, cur_lch;
-                char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
+                char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 
                 dma_chan_link_map[lch] = 1;
                 /* Set the link register of the first channel */
@@ -799,27 +926,34 @@ void omap_start_dma(int lch)
                 } while (next_lch != -1);
         } else if (cpu_class_is_omap2()) {
                 /* Errata: Need to write lch even if not using chaining */
-                OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
+                dma_write(lch, CLNK_CTRL(lch));
         }
 
         omap_enable_channel_irq(lch);
 
-        /* Errata: On ES2.0 BUFFERING disable must be set.
-         * This will always fail on ES1.0 */
-        if (cpu_is_omap24xx()) {
-                OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
-        }
+        l = dma_read(CCR(lch));
+
+        /*
+         * Errata: On ES2.0 BUFFERING disable must be set.
+         * This will always fail on ES1.0
+         */
+        if (cpu_is_omap24xx())
+                l |= OMAP_DMA_CCR_EN;
 
-        OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
+        l |= OMAP_DMA_CCR_EN;
+        dma_write(l, CCR(lch));
 
         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 }
+EXPORT_SYMBOL(omap_start_dma);
 
 void omap_stop_dma(int lch)
 {
+        u32 l;
+
         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                 int next_lch, cur_lch = lch;
-                char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
+                char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 
                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
                 do {
@@ -840,18 +974,22 @@ void omap_stop_dma(int lch)
 
         /* Disable all interrupts on the channel */
         if (cpu_class_is_omap1())
-                OMAP_DMA_CICR_REG(lch) = 0;
+                dma_write(0, CICR(lch));
+
+        l = dma_read(CCR(lch));
+        l &= ~OMAP_DMA_CCR_EN;
+        dma_write(l, CCR(lch));
 
-        OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 }
+EXPORT_SYMBOL(omap_stop_dma);
 
 /*
  * Allows changing the DMA callback function or data. This may be needed if
  * the driver shares a single DMA channel for multiple dma triggers.
  */
 int omap_set_dma_callback(int lch,
-                          void (* callback)(int lch, u16 ch_status, void *data),
+                          void (*callback)(int lch, u16 ch_status, void *data),
                           void *data)
 {
         unsigned long flags;
@@ -871,6 +1009,7 @@ int omap_set_dma_callback(int lch,
 
         return 0;
 }
+EXPORT_SYMBOL(omap_set_dma_callback);
 
 /*
  * Returns current physical source address for the given DMA channel.
@@ -884,15 +1023,24 @@ dma_addr_t omap_get_dma_src_pos(int lch)
 {
         dma_addr_t offset = 0;
 
-        if (cpu_class_is_omap1())
-                offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
-                                       (OMAP1_DMA_CSSA_U_REG(lch) << 16));
+        if (cpu_is_omap15xx())
+                offset = dma_read(CPC(lch));
+        else
+                offset = dma_read(CSAC(lch));
 
-        if (cpu_class_is_omap2())
-                offset = OMAP_DMA_CSAC_REG(lch);
+        /*
+         * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
+         * read before the DMA controller finished disabling the channel.
+         */
+        if (!cpu_is_omap15xx() && offset == 0)
+                offset = dma_read(CSAC(lch));
+
+        if (cpu_class_is_omap1())
+                offset |= (dma_read(CSSA_U(lch)) << 16);
 
         return offset;
 }
+EXPORT_SYMBOL(omap_get_dma_src_pos);
 
 /*
  * Returns current physical destination address for the given DMA channel.
@@ -906,25 +1054,30 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
 {
         dma_addr_t offset = 0;
 
-        if (cpu_class_is_omap1())
-                offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
-                                       (OMAP1_DMA_CDSA_U_REG(lch) << 16));
+        if (cpu_is_omap15xx())
+                offset = dma_read(CPC(lch));
+        else
+                offset = dma_read(CDAC(lch));
 
-        if (cpu_class_is_omap2())
-                offset = OMAP_DMA_CDAC_REG(lch);
+        /*
+         * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
+         * read before the DMA controller finished disabling the channel.
+         */
+        if (!cpu_is_omap15xx() && offset == 0)
+                offset = dma_read(CDAC(lch));
+
+        if (cpu_class_is_omap1())
+                offset |= (dma_read(CDSA_U(lch)) << 16);
 
         return offset;
 }
+EXPORT_SYMBOL(omap_get_dma_dst_pos);
 
-/*
- * Returns current source transfer counting for the given DMA channel.
- * Can be used to monitor the progress of a transfer inside a block.
- * It must be called with disabled interrupts.
- */
-int omap_get_dma_src_addr_counter(int lch)
+int omap_get_dma_active_status(int lch)
 {
-        return (dma_addr_t) OMAP_DMA_CSAC_REG(lch);
+        return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
 }
+EXPORT_SYMBOL(omap_get_dma_active_status);
 
 int omap_dma_running(void)
 {
@@ -936,7 +1089,7 @@ int omap_dma_running(void)
                         return 1;
 
         for (lch = 0; lch < dma_chan_count; lch++)
-                if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN)
+                if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
                         return 1;
 
         return 0;
@@ -947,7 +1100,7 @@ int omap_dma_running(void)
  * For this DMA link to start, you still need to start (see omap_start_dma)
  * the first one. That will fire up the entire queue.
  */
-void omap_dma_link_lch (int lch_head, int lch_queue)
+void omap_dma_link_lch(int lch_head, int lch_queue)
 {
         if (omap_dma_in_1510_mode()) {
                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
@@ -964,11 +1117,12 @@ void omap_dma_link_lch (int lch_head, int lch_queue)
 
         dma_chan[lch_head].next_lch = lch_queue;
 }
+EXPORT_SYMBOL(omap_dma_link_lch);
 
 /*
  * Once the DMA queue is stopped, we can destroy it.
  */
-void omap_dma_unlink_lch (int lch_head, int lch_queue)
+void omap_dma_unlink_lch(int lch_head, int lch_queue)
 {
         if (omap_dma_in_1510_mode()) {
                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
@@ -983,7 +1137,6 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue)
                 dump_stack();
         }
 
-
         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
@@ -993,12 +1146,15 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue)
 
         dma_chan[lch_head].next_lch = -1;
 }
+EXPORT_SYMBOL(omap_dma_unlink_lch);
+
+/*----------------------------------------------------------------------------*/
 
 #ifndef CONFIG_ARCH_OMAP1
 /* Create chain of DMA channesls */
 static void create_dma_lch_chain(int lch_head, int lch_queue)
 {
-        u32 w;
+        u32 l;
 
         /* Check if this is the first link in chain */
         if (dma_chan[lch_head].next_linked_ch == -1) {
@@ -1018,15 +1174,15 @@ static void create_dma_lch_chain(int lch_head, int lch_queue)
                                         lch_queue;
         }
 
-        w = OMAP_DMA_CLNK_CTRL_REG(lch_head);
-        w &= ~(0x1f);
-        w |= lch_queue;
-        OMAP_DMA_CLNK_CTRL_REG(lch_head) = w;
+        l = dma_read(CLNK_CTRL(lch_head));
+        l &= ~(0x1f);
+        l |= lch_queue;
+        dma_write(l, CLNK_CTRL(lch_head));
 
-        w = OMAP_DMA_CLNK_CTRL_REG(lch_queue);
-        w &= ~(0x1f);
-        w |= (dma_chan[lch_queue].next_linked_ch);
-        OMAP_DMA_CLNK_CTRL_REG(lch_queue) = w;
+        l = dma_read(CLNK_CTRL(lch_queue));
+        l &= ~(0x1f);
+        l |= (dma_chan[lch_queue].next_linked_ch);
+        dma_write(l, CLNK_CTRL(lch_queue));
 }
 
 /**
@@ -1061,7 +1217,7 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
         }
 
         if (unlikely((no_of_chans < 1
-                        || no_of_chans > OMAP_LOGICAL_DMA_CH_COUNT))) {
+                        || no_of_chans > dma_lch_count))) {
                 printk(KERN_ERR "Invalid Number of channels requested\n");
                 return -EINVAL;
         }
@@ -1116,6 +1272,7 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
                 for (i = 0; i < (no_of_chans - 1); i++)
                         create_dma_lch_chain(channels[i], channels[i + 1]);
         }
+
         return 0;
 }
 EXPORT_SYMBOL(omap_request_dma_chain);
@@ -1138,7 +1295,7 @@ int omap_modify_dma_chain_params(int chain_id,
 
         /* Check for input params */
         if (unlikely((chain_id < 0
-                        || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+                        || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1158,6 +1315,7 @@ int omap_modify_dma_chain_params(int chain_id,
                  */
                 omap_set_dma_params(channels[i], &params);
         }
+
         return 0;
 }
 EXPORT_SYMBOL(omap_modify_dma_chain_params);
@@ -1176,7 +1334,7 @@ int omap_free_dma_chain(int chain_id)
         u32 i;
 
         /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1201,6 +1359,7 @@ int omap_free_dma_chain(int chain_id)
         dma_linked_lch[chain_id].linked_dmach_q = NULL;
         dma_linked_lch[chain_id].chain_mode = -1;
         dma_linked_lch[chain_id].chain_state = -1;
+
         return (0);
 }
 EXPORT_SYMBOL(omap_free_dma_chain);
@@ -1216,7 +1375,7 @@ EXPORT_SYMBOL(omap_free_dma_chain);
 int omap_dma_chain_status(int chain_id)
 {
         /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1231,6 +1390,7 @@ int omap_dma_chain_status(int chain_id)
 
         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
                 return OMAP_DMA_CHAIN_INACTIVE;
+
         return OMAP_DMA_CHAIN_ACTIVE;
 }
 EXPORT_SYMBOL(omap_dma_chain_status);
@@ -1253,11 +1413,13 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                         int elem_count, int frame_count, void *callbk_data)
 {
         int *channels;
-        u32 w, lch;
+        u32 l, lch;
         int start_dma = 0;
 
-        /* if buffer size is less than 1 then there is
-         * no use of starting the chain */
+        /*
+         * if buffer size is less than 1 then there is
+         * no use of starting the chain
+         */
         if (elem_count < 1) {
                 printk(KERN_ERR "Invalid buffer size\n");
                 return -EINVAL;
@@ -1265,7 +1427,7 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
 
         /* Check for input params */
         if (unlikely((chain_id < 0
-                        || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+                        || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1294,20 +1456,24 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
 
         /* Set the params to the free channel */
         if (src_start != 0)
-                OMAP2_DMA_CSSA_REG(lch) = src_start;
+                dma_write(src_start, CSSA(lch));
         if (dest_start != 0)
-                OMAP2_DMA_CDSA_REG(lch) = dest_start;
+                dma_write(dest_start, CDSA(lch));
 
         /* Write the buffer size */
-        OMAP_DMA_CEN_REG(lch) = elem_count;
-        OMAP_DMA_CFN_REG(lch) = frame_count;
+        dma_write(elem_count, CEN(lch));
+        dma_write(frame_count, CFN(lch));
 
-        /* If the chain is dynamically linked,
-         * then we may have to start the chain if its not active */
+        /*
+         * If the chain is dynamically linked,
+         * then we may have to start the chain if its not active
+         */
         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
 
-                /* In Dynamic chain, if the chain is not started,
-                 * queue the channel */
+                /*
+                 * In Dynamic chain, if the chain is not started,
+                 * queue the channel
+                 */
                 if (dma_linked_lch[chain_id].chain_state ==
                                                 DMA_CHAIN_NOTSTARTED) {
                         /* Enable the link in previous channel */
@@ -1317,8 +1483,10 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                         dma_chan[lch].state = DMA_CH_QUEUED;
                 }
 
-                /* Chain is already started, make sure its active,
-                 * if not then start the chain */
+                /*
+                 * Chain is already started, make sure its active,
+                 * if not then start the chain
+                 */
                 else {
                         start_dma = 1;
 
@@ -1327,8 +1495,8 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                                 enable_lnk(dma_chan[lch].prev_linked_ch);
                                 dma_chan[lch].state = DMA_CH_QUEUED;
                                 start_dma = 0;
-                                if (0 == ((1 << 7) & (OMAP_DMA_CCR_REG
-                                        (dma_chan[lch].prev_linked_ch)))) {
+                                if (0 == ((1 << 7) & dma_read(
+                                        CCR(dma_chan[lch].prev_linked_ch)))) {
                                         disable_lnk(dma_chan[lch].
                                                     prev_linked_ch);
                                         pr_debug("\n prev ch is stopped\n");
@@ -1344,27 +1512,28 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                         }
                         omap_enable_channel_irq(lch);
 
-                        w = OMAP_DMA_CCR_REG(lch);
+                        l = dma_read(CCR(lch));
 
-                        if ((0 == (w & (1 << 24))))
-                                w &= ~(1 << 25);
+                        if ((0 == (l & (1 << 24))))
+                                l &= ~(1 << 25);
                         else
-                                w |= (1 << 25);
+                                l |= (1 << 25);
                         if (start_dma == 1) {
-                                if (0 == (w & (1 << 7))) {
-                                        w |= (1 << 7);
+                                if (0 == (l & (1 << 7))) {
+                                        l |= (1 << 7);
                                         dma_chan[lch].state = DMA_CH_STARTED;
                                         pr_debug("starting %d\n", lch);
-                                        OMAP_DMA_CCR_REG(lch) = w;
+                                        dma_write(l, CCR(lch));
                                 } else
                                         start_dma = 0;
                         } else {
-                                if (0 == (w & (1 << 7)))
-                                        OMAP_DMA_CCR_REG(lch) = w;
+                                if (0 == (l & (1 << 7)))
+                                        dma_write(l, CCR(lch));
                         }
                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
                 }
         }
+
         return 0;
 }
 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
@@ -1380,9 +1549,9 @@ EXPORT_SYMBOL(omap_dma_chain_a_transfer);
 int omap_start_dma_chain_transfers(int chain_id)
 {
         int *channels;
-        u32 w, i;
+        u32 l, i;
 
-        if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1404,18 +1573,19 @@ int omap_start_dma_chain_transfers(int chain_id)
                 omap_enable_channel_irq(channels[0]);
         }
 
-        w = OMAP_DMA_CCR_REG(channels[0]);
-        w |= (1 << 7);
+        l = dma_read(CCR(channels[0]));
+        l |= (1 << 7);
         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
         dma_chan[channels[0]].state = DMA_CH_STARTED;
 
-        if ((0 == (w & (1 << 24))))
-                w &= ~(1 << 25);
+        if ((0 == (l & (1 << 24))))
+                l &= ~(1 << 25);
         else
-                w |= (1 << 25);
-        OMAP_DMA_CCR_REG(channels[0]) = w;
+                l |= (1 << 25);
+        dma_write(l, CCR(channels[0]));
 
         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
+
         return 0;
 }
 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
@@ -1431,11 +1601,11 @@ EXPORT_SYMBOL(omap_start_dma_chain_transfers);
 int omap_stop_dma_chain_transfers(int chain_id)
 {
         int *channels;
-        u32 w, i;
+        u32 l, i;
         u32 sys_cf;
 
         /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1447,21 +1617,22 @@ int omap_stop_dma_chain_transfers(int chain_id)
         }
         channels = dma_linked_lch[chain_id].linked_dmach_q;
 
-        /* DMA Errata:
+        /*
+         * DMA Errata:
          * Special programming model needed to disable DMA before end of block
          */
-        sys_cf = omap_readl(OMAP_DMA4_OCP_SYSCONFIG);
-        w = sys_cf;
+        sys_cf = dma_read(OCP_SYSCONFIG);
+        l = sys_cf;
         /* Middle mode reg set no Standby */
-        w &= ~((1 << 12)|(1 << 13));
-        omap_writel(w, OMAP_DMA4_OCP_SYSCONFIG);
+        l &= ~((1 << 12)|(1 << 13));
+        dma_write(l, OCP_SYSCONFIG);
 
         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
 
                 /* Stop the Channel transmission */
-                w = OMAP_DMA_CCR_REG(channels[i]);
-                w &= ~(1 << 7);
-                OMAP_DMA_CCR_REG(channels[i]) = w;
+                l = dma_read(CCR(channels[i]));
+                l &= ~(1 << 7);
+                dma_write(l, CCR(channels[i]));
 
                 /* Disable the link in all the channels */
                 disable_lnk(channels[i]);
@@ -1474,7 +1645,8 @@ int omap_stop_dma_chain_transfers(int chain_id)
         OMAP_DMA_CHAIN_QINIT(chain_id);
 
         /* Errata - put in the old value */
-        omap_writel(sys_cf, OMAP_DMA4_OCP_SYSCONFIG);
+        dma_write(sys_cf, OCP_SYSCONFIG);
+
         return 0;
 }
 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
@@ -1497,7 +1669,7 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
         int *channels;
 
         /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1515,8 +1687,8 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
         /* Get the current channel */
         lch = channels[dma_linked_lch[chain_id].q_head];
 
-        *ei = OMAP2_DMA_CCEN_REG(lch);
-        *fi = OMAP2_DMA_CCFN_REG(lch);
+        *ei = dma_read(CCEN(lch));
+        *fi = dma_read(CCFN(lch));
 
         return 0;
 }
@@ -1537,7 +1709,7 @@ int omap_get_dma_chain_dst_pos(int chain_id)
         int *channels;
 
         /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1553,7 +1725,7 @@ int omap_get_dma_chain_dst_pos(int chain_id)
         /* Get the current channel */
         lch = channels[dma_linked_lch[chain_id].q_head];
 
-        return (OMAP_DMA_CDAC_REG(lch));
+        return dma_read(CDAC(lch));
 }
 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
 
@@ -1571,7 +1743,7 @@ int omap_get_dma_chain_src_pos(int chain_id)
         int *channels;
 
         /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
+        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
                 printk(KERN_ERR "Invalid chain id\n");
                 return -EINVAL;
         }
@@ -1587,10 +1759,10 @@ int omap_get_dma_chain_src_pos(int chain_id)
         /* Get the current channel */
         lch = channels[dma_linked_lch[chain_id].q_head];
 
-        return (OMAP_DMA_CSAC_REG(lch));
+        return dma_read(CSAC(lch));
 }
 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
-#endif
+#endif  /* ifndef CONFIG_ARCH_OMAP1 */
 
 /*----------------------------------------------------------------------------*/
 
@@ -1598,13 +1770,13 @@ EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
 
 static int omap1_dma_handle_ch(int ch)
 {
-        u16 csr;
+        u32 csr;
 
         if (enable_1510_mode && ch >= 6) {
                 csr = dma_chan[ch].saved_csr;
                 dma_chan[ch].saved_csr = 0;
         } else
-                csr = OMAP_DMA_CSR_REG(ch);
+                csr = dma_read(CSR(ch));
         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
                 dma_chan[ch + 6].saved_csr = csr >> 7;
                 csr &= 0x7f;
@@ -1626,6 +1798,7 @@ static int omap1_dma_handle_ch(int ch)
                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
         if (likely(dma_chan[ch].callback != NULL))
                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
+
         return 1;
 }
 
@@ -1656,12 +1829,13 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
 
 static int omap2_dma_handle_ch(int ch)
 {
-        u32 status = OMAP_DMA_CSR_REG(ch);
+        u32 status = dma_read(CSR(ch));
 
         if (!status) {
                 if (printk_ratelimit())
-                        printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch);
-                omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0);
+                        printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
+                                ch);
+                dma_write(1 << ch, IRQSTATUS_L0);
                 return 0;
         }
         if (unlikely(dma_chan[ch].dev_id == -1)) {
@@ -1684,14 +1858,14 @@ static int omap2_dma_handle_ch(int ch)
                 printk(KERN_INFO "DMA misaligned error with device %d\n",
                        dma_chan[ch].dev_id);
 
-        OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
-        omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0);
+        dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
+        dma_write(1 << ch, IRQSTATUS_L0);
 
         /* If the ch is not chained then chain_id will be -1 */
         if (dma_chan[ch].chain_id != -1) {
                 int chain_id = dma_chan[ch].chain_id;
                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
-                if (OMAP_DMA_CLNK_CTRL_REG(ch) & (1 << 15))
+                if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
                         dma_chan[dma_chan[ch].next_linked_ch].state =
                                                         DMA_CH_STARTED;
                 if (dma_linked_lch[chain_id].chain_mode ==
@@ -1701,13 +1875,13 @@ static int omap2_dma_handle_ch(int ch)
                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
 
-                status = OMAP_DMA_CSR_REG(ch);
+                status = dma_read(CSR(ch));
         }
 
         if (likely(dma_chan[ch].callback != NULL))
                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
 
-        OMAP_DMA_CSR_REG(ch) = status;
+        dma_write(status, CSR(ch));
 
         return 0;
 }
@@ -1718,13 +1892,13 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
         u32 val;
         int i;
 
-        val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
+        val = dma_read(IRQSTATUS_L0);
         if (val == 0) {
                 if (printk_ratelimit())
                         printk(KERN_WARNING "Spurious DMA IRQ\n");
                 return IRQ_HANDLED;
         }
-        for (i = 0; i < OMAP_LOGICAL_DMA_CH_COUNT && val != 0; i++) {
+        for (i = 0; i < dma_lch_count && val != 0; i++) {
                 if (val & 1)
                         omap2_dma_handle_ch(i);
                 val >>= 1;
@@ -1748,7 +1922,7 @@ static struct irqaction omap24xx_dma_irq;
 static struct lcd_dma_info {
         spinlock_t lock;
         int reserved;
-        void (* callback)(u16 status, void *data);
+        void (*callback)(u16 status, void *data);
         void *cb_data;
 
         int active;
@@ -1770,6 +1944,7 @@ void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
         lcd_dma.xres = fb_xres;
         lcd_dma.yres = fb_yres;
 }
+EXPORT_SYMBOL(omap_set_lcd_dma_b1);
 
 void omap_set_lcd_dma_src_port(int port)
 {
@@ -1780,12 +1955,13 @@ void omap_set_lcd_dma_ext_controller(int external)
 {
         lcd_dma.ext_ctrl = external;
 }
+EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
 
 void omap_set_lcd_dma_single_transfer(int single)
 {
         lcd_dma.single_transfer = single;
 }
-
+EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
 
 void omap_set_lcd_dma_b1_rotation(int rotate)
 {
@@ -1796,6 +1972,7 @@ void omap_set_lcd_dma_b1_rotation(int rotate)
         }
         lcd_dma.rotate = rotate;
 }
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
 
 void omap_set_lcd_dma_b1_mirror(int mirror)
 {
@@ -1805,6 +1982,7 @@ void omap_set_lcd_dma_b1_mirror(int mirror)
         }
         lcd_dma.mirror = mirror;
 }
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
 
 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
 {
@@ -1815,6 +1993,7 @@ void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
         }
         lcd_dma.vxres = vxres;
 }
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
 
 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
 {
@@ -1825,6 +2004,7 @@ void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
         lcd_dma.xscale = xscale;
         lcd_dma.yscale = yscale;
 }
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
 
 static void set_b1_regs(void)
 {
@@ -1855,8 +2035,11 @@ static void set_b1_regs(void)
         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
         BUG_ON(vxres < lcd_dma.xres);
-#define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
+
+#define PIXADDR(x, y) (lcd_dma.addr +                                   \
+                ((y) * vxres * yscale + (x) * xscale) * es)
 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
+
         switch (lcd_dma.rotate) {
         case 0:
                 if (!lcd_dma.mirror) {
@@ -1865,8 +2048,8 @@ static void set_b1_regs(void)
                         /* 1510 DMA requires the bottom address to be 2 more
                          * than the actual last memory access location. */
                         if (omap_dma_in_1510_mode() &&
-                            lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
-                                bottom += 2;
+                                lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
+                                        bottom += 2;
                         ei = PIXSTEP(0, 0, 1, 0);
                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
                 } else {
@@ -1993,7 +2176,7 @@ static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
+int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
                          void *data)
 {
         spin_lock_irq(&lcd_dma.lock);
@@ -2019,6 +2202,7 @@ int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
 
         return 0;
 }
+EXPORT_SYMBOL(omap_request_lcd_dma);
 
 void omap_free_lcd_dma(void)
 {
@@ -2035,12 +2219,14 @@ void omap_free_lcd_dma(void)
         lcd_dma.reserved = 0;
         spin_unlock(&lcd_dma.lock);
 }
+EXPORT_SYMBOL(omap_free_lcd_dma);
 
 void omap_enable_lcd_dma(void)
 {
         u16 w;
 
-        /* Set the Enable bit only if an external controller is
+        /*
+         * Set the Enable bit only if an external controller is
          * connected. Otherwise the OMAP internal controller will
          * start the transfer when it gets enabled.
          */
@@ -2057,6 +2243,7 @@ void omap_enable_lcd_dma(void)
         w |= 1 << 7;
         omap_writew(w, OMAP1610_DMA_LCD_CCR);
 }
+EXPORT_SYMBOL(omap_enable_lcd_dma);
 
 void omap_setup_lcd_dma(void)
 {
@@ -2072,16 +2259,18 @@ void omap_setup_lcd_dma(void)
                 u16 w;
 
                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
-                /* If DMA was already active set the end_prog bit to have
+                /*
+                 * If DMA was already active set the end_prog bit to have
                  * the programmed register set loaded into the active
                  * register set.
                  */
                 w |= 1 << 11;           /* End_prog */
                 if (!lcd_dma.single_transfer)
-                        w |= (3 << 8);  /* Auto_init, repeat */
+                        w |= (3 << 8);  /* Auto_init, repeat */
                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
         }
 }
+EXPORT_SYMBOL(omap_setup_lcd_dma);
 
 void omap_stop_lcd_dma(void)
 {
@@ -2099,6 +2288,7 @@ void omap_stop_lcd_dma(void)
         w &= ~(1 << 8);
         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
 }
+EXPORT_SYMBOL(omap_stop_lcd_dma);
 
 /*----------------------------------------------------------------------------*/
 
@@ -2106,27 +2296,55 @@ static int __init omap_init_dma(void)
 {
         int ch, r;
 
+        if (cpu_class_is_omap1()) {
+                omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP1_DMA_BASE);
+                dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
+        } else if (cpu_is_omap24xx()) {
+                omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP24XX_DMA4_BASE);
+                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
+        } else if (cpu_is_omap34xx()) {
+                omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP34XX_DMA4_BASE);
+                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
+        } else {
+                pr_err("DMA init failed for unsupported omap\n");
+                return -ENODEV;
+        }
+
+        dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
+                                GFP_KERNEL);
+        if (!dma_chan)
+                return -ENOMEM;
+
+        if (cpu_class_is_omap2()) {
+                dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
+                                                dma_lch_count, GFP_KERNEL);
+                if (!dma_linked_lch) {
+                        kfree(dma_chan);
+                        return -ENOMEM;
+                }
+        }
+
         if (cpu_is_omap15xx()) {
                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
                 dma_chan_count = 9;
                 enable_1510_mode = 1;
         } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
-                       omap_readw(OMAP_DMA_HW_ID));
+                       dma_read(HW_ID));
                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
-                       (omap_readw(OMAP_DMA_CAPS_0_U) << 16) |
-                       omap_readw(OMAP_DMA_CAPS_0_L),
-                       (omap_readw(OMAP_DMA_CAPS_1_U) << 16) |
-                       omap_readw(OMAP_DMA_CAPS_1_L),
-                       omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
-                       omap_readw(OMAP_DMA_CAPS_4));
+                       (dma_read(CAPS_0_U) << 16) |
+                       dma_read(CAPS_0_L),
+                       (dma_read(CAPS_1_U) << 16) |
+                       dma_read(CAPS_1_L),
+                       dma_read(CAPS_2), dma_read(CAPS_3),
+                       dma_read(CAPS_4));
                 if (!enable_1510_mode) {
                         u16 w;
 
                         /* Disable OMAP 3.0/3.1 compatibility mode. */
-                        w = omap_readw(OMAP_DMA_GSCR);
+                        w = dma_read(GSCR);
                         w |= 1 << 3;
-                        omap_writew(w, OMAP_DMA_GSCR);
+                        dma_write(w, GSCR);
                         dma_chan_count = 16;
                 } else
                         dma_chan_count = 9;
@@ -2139,19 +2357,17 @@ static int __init omap_init_dma(void)
                         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
                 }
         } else if (cpu_class_is_omap2()) {
-                u8 revision = omap_readb(OMAP_DMA4_REVISION);
+                u8 revision = dma_read(REVISION) & 0xff;
                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
                        revision >> 4, revision & 0xf);
-                dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
+                dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
         } else {
                 dma_chan_count = 0;
                 return 0;
         }
 
-        memset(&lcd_dma, 0, sizeof(lcd_dma));
         spin_lock_init(&lcd_dma.lock);
         spin_lock_init(&dma_chan_lock);
-        memset(&dma_chan, 0, sizeof(dma_chan));
 
         for (ch = 0; ch < dma_chan_count; ch++) {
                 omap_clear_dma(ch);
@@ -2162,8 +2378,10 @@ static int __init omap_init_dma(void)
                         continue;
 
                 if (cpu_class_is_omap1()) {
-                        /* request_irq() doesn't like dev_id (ie. ch) being
-                         * zero, so we have to kludge around this. */
+                        /*
+                         * request_irq() doesn't like dev_id (ie. ch) being
+                         * zero, so we have to kludge around this.
+                         */
                         r = request_irq(omap1_dma_irq[ch],
                                         omap1_dma_irq_handler, 0, "DMA",
                                         (void *) (ch + 1));
@@ -2208,48 +2426,4 @@ static int __init omap_init_dma(void)
 
 arch_initcall(omap_init_dma);
 
-EXPORT_SYMBOL(omap_get_dma_src_pos);
-EXPORT_SYMBOL(omap_get_dma_dst_pos);
-EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
-EXPORT_SYMBOL(omap_clear_dma);
-EXPORT_SYMBOL(omap_set_dma_priority);
-EXPORT_SYMBOL(omap_request_dma);
-EXPORT_SYMBOL(omap_free_dma);
-EXPORT_SYMBOL(omap_start_dma);
-EXPORT_SYMBOL(omap_stop_dma);
-EXPORT_SYMBOL(omap_set_dma_callback);
-EXPORT_SYMBOL(omap_enable_dma_irq);
-EXPORT_SYMBOL(omap_disable_dma_irq);
-
-EXPORT_SYMBOL(omap_set_dma_transfer_params);
-EXPORT_SYMBOL(omap_set_dma_color_mode);
-EXPORT_SYMBOL(omap_set_dma_write_mode);
-
-EXPORT_SYMBOL(omap_set_dma_src_params);
-EXPORT_SYMBOL(omap_set_dma_src_index);
-EXPORT_SYMBOL(omap_set_dma_src_data_pack);
-EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
-
-EXPORT_SYMBOL(omap_set_dma_dest_params);
-EXPORT_SYMBOL(omap_set_dma_dest_index);
-EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
-EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
-
-EXPORT_SYMBOL(omap_set_dma_params);
-
-EXPORT_SYMBOL(omap_dma_link_lch);
-EXPORT_SYMBOL(omap_dma_unlink_lch);
-
-EXPORT_SYMBOL(omap_request_lcd_dma);
-EXPORT_SYMBOL(omap_free_lcd_dma);
-EXPORT_SYMBOL(omap_enable_lcd_dma);
-EXPORT_SYMBOL(omap_setup_lcd_dma);
-EXPORT_SYMBOL(omap_stop_lcd_dma);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1);
-EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
-EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
 
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 302ad8dff2cb..f22506af0e67 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -38,34 +38,113 @@
 #include <asm/arch/irqs.h>
 
 /* register offsets */
-#define OMAP_TIMER_ID_REG               0x00
-#define OMAP_TIMER_OCP_CFG_REG          0x10
-#define OMAP_TIMER_SYS_STAT_REG         0x14
-#define OMAP_TIMER_STAT_REG             0x18
-#define OMAP_TIMER_INT_EN_REG           0x1c
-#define OMAP_TIMER_WAKEUP_EN_REG        0x20
-#define OMAP_TIMER_CTRL_REG             0x24
-#define OMAP_TIMER_COUNTER_REG          0x28
-#define OMAP_TIMER_LOAD_REG             0x2c
-#define OMAP_TIMER_TRIGGER_REG          0x30
-#define OMAP_TIMER_WRITE_PEND_REG       0x34
-#define OMAP_TIMER_MATCH_REG            0x38
-#define OMAP_TIMER_CAPTURE_REG          0x3c
-#define OMAP_TIMER_IF_CTRL_REG          0x40
-
-/* timer control reg bits */
-#define OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
-#define OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
-#define OMAP_TIMER_CTRL_PT              (1 << 12)
-#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
-#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
-#define OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
-#define OMAP_TIMER_CTRL_SCPWM           (1 << 7)
-#define OMAP_TIMER_CTRL_CE              (1 << 6)        /* compare enable */
-#define OMAP_TIMER_CTRL_PRE             (1 << 5)        /* prescaler enable */
-#define OMAP_TIMER_CTRL_PTV_SHIFT       2               /* how much to shift the prescaler value */
-#define OMAP_TIMER_CTRL_AR              (1 << 1)        /* auto-reload enable */
-#define OMAP_TIMER_CTRL_ST              (1 << 0)        /* start timer */
+#define _OMAP_TIMER_ID_OFFSET           0x00
+#define _OMAP_TIMER_OCP_CFG_OFFSET      0x10
+#define _OMAP_TIMER_SYS_STAT_OFFSET     0x14
+#define _OMAP_TIMER_STAT_OFFSET         0x18
+#define _OMAP_TIMER_INT_EN_OFFSET       0x1c
+#define _OMAP_TIMER_WAKEUP_EN_OFFSET    0x20
+#define _OMAP_TIMER_CTRL_OFFSET         0x24
+#define         OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
+#define         OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
+#define         OMAP_TIMER_CTRL_PT              (1 << 12)
+#define         OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
+#define         OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
+#define         OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
+#define         OMAP_TIMER_CTRL_SCPWM           (1 << 7)
+#define         OMAP_TIMER_CTRL_CE              (1 << 6) /* compare enable */
+#define         OMAP_TIMER_CTRL_PRE             (1 << 5) /* prescaler enable */
+#define         OMAP_TIMER_CTRL_PTV_SHIFT       2 /* prescaler value shift */
+#define         OMAP_TIMER_CTRL_POSTED          (1 << 2)
+#define         OMAP_TIMER_CTRL_AR              (1 << 1) /* auto-reload enable */
+#define         OMAP_TIMER_CTRL_ST              (1 << 0) /* start timer */
+#define _OMAP_TIMER_COUNTER_OFFSET      0x28
+#define _OMAP_TIMER_LOAD_OFFSET         0x2c
+#define _OMAP_TIMER_TRIGGER_OFFSET      0x30
+#define _OMAP_TIMER_WRITE_PEND_OFFSET   0x34
+#define         WP_NONE                 0       /* no write pending bit */
+#define         WP_TCLR                 (1 << 0)
+#define         WP_TCRR                 (1 << 1)
+#define         WP_TLDR                 (1 << 2)
+#define         WP_TTGR                 (1 << 3)
+#define         WP_TMAR                 (1 << 4)
+#define         WP_TPIR                 (1 << 5)
+#define         WP_TNIR                 (1 << 6)
+#define         WP_TCVR                 (1 << 7)
+#define         WP_TOCR                 (1 << 8)
+#define         WP_TOWR                 (1 << 9)
+#define _OMAP_TIMER_MATCH_OFFSET        0x38
+#define _OMAP_TIMER_CAPTURE_OFFSET      0x3c
+#define _OMAP_TIMER_IF_CTRL_OFFSET      0x40
+#define _OMAP_TIMER_CAPTURE2_OFFSET             0x44    /* TCAR2, 34xx only */
+#define _OMAP_TIMER_TICK_POS_OFFSET             0x48    /* TPIR, 34xx only */
+#define _OMAP_TIMER_TICK_NEG_OFFSET             0x4c    /* TNIR, 34xx only */
+#define _OMAP_TIMER_TICK_COUNT_OFFSET           0x50    /* TCVR, 34xx only */
+#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET    0x54    /* TOCR, 34xx only */
+#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET  0x58    /* TOWR, 34xx only */
+
+/* register offsets with the write pending bit encoded */
+#define WPSHIFT                                 16
+
+#define OMAP_TIMER_ID_REG                       (_OMAP_TIMER_ID_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_OCP_CFG_REG                  (_OMAP_TIMER_OCP_CFG_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_SYS_STAT_REG                 (_OMAP_TIMER_SYS_STAT_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_STAT_REG                     (_OMAP_TIMER_STAT_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_INT_EN_REG                   (_OMAP_TIMER_INT_EN_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_WAKEUP_EN_REG                (_OMAP_TIMER_WAKEUP_EN_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_CTRL_REG                     (_OMAP_TIMER_CTRL_OFFSET \
+                                                        | (WP_TCLR << WPSHIFT))
+
+#define OMAP_TIMER_COUNTER_REG                  (_OMAP_TIMER_COUNTER_OFFSET \
+                                                        | (WP_TCRR << WPSHIFT))
+
+#define OMAP_TIMER_LOAD_REG                     (_OMAP_TIMER_LOAD_OFFSET \
+                                                        | (WP_TLDR << WPSHIFT))
+
+#define OMAP_TIMER_TRIGGER_REG                  (_OMAP_TIMER_TRIGGER_OFFSET \
+                                                        | (WP_TTGR << WPSHIFT))
+
+#define OMAP_TIMER_WRITE_PEND_REG               (_OMAP_TIMER_WRITE_PEND_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_MATCH_REG                    (_OMAP_TIMER_MATCH_OFFSET \
+                                                        | (WP_TMAR << WPSHIFT))
+
+#define OMAP_TIMER_CAPTURE_REG                  (_OMAP_TIMER_CAPTURE_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_IF_CTRL_REG                  (_OMAP_TIMER_IF_CTRL_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_CAPTURE2_REG                 (_OMAP_TIMER_CAPTURE2_OFFSET \
+                                                        | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_TICK_POS_REG                 (_OMAP_TIMER_TICK_POS_OFFSET \
+                                                        | (WP_TPIR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_NEG_REG                 (_OMAP_TIMER_TICK_NEG_OFFSET \
+                                                        | (WP_TNIR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_COUNT_REG               (_OMAP_TIMER_TICK_COUNT_OFFSET \
+                                                        | (WP_TCVR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_INT_MASK_SET_REG                                \
+                (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG                              \
+                (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
 
 struct omap_dm_timer {
         unsigned long phys_base;
@@ -76,6 +155,7 @@ struct omap_dm_timer {
         void __iomem *io_base;
         unsigned reserved:1;
         unsigned enabled:1;
+        unsigned posted:1;
 };
 
 #ifdef CONFIG_ARCH_OMAP1
@@ -181,16 +261,34 @@ static struct clk **dm_source_clocks;
 
 static spinlock_t dm_timer_lock;
 
-static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
+/*
+ * Reads timer registers in posted and non-posted mode. The posted mode bit
+ * is encoded in reg. Note that in posted mode write pending bit must be
+ * checked. Otherwise a read of a non completed write will produce an error.
+ */
+static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
 {
-        return readl(timer->io_base + reg);
+        if (timer->posted)
+                while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
+                                & (reg >> WPSHIFT))
+                        cpu_relax();
+        return readl(timer->io_base + (reg & 0xff));
 }
 
-static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
+/*
+ * Writes timer registers in posted and non-posted mode. The posted mode bit
+ * is encoded in reg. Note that in posted mode the write pending bit must be
+ * checked. Otherwise a write on a register which has a pending write will be
+ * lost.
+ */
+static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
+                                                u32 value)
 {
-        writel(value, timer->io_base + reg);
-        while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
-                ;
+        if (timer->posted)
+                while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
+                                & (reg >> WPSHIFT))
+                        cpu_relax();
+        writel(value, timer->io_base + (reg & 0xff));
 }
 
 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
@@ -217,17 +315,23 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
         }
         omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
 
-        /* Set to smart-idle mode */
         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
-        l |= 0x02 << 3;
-
-        if (cpu_class_is_omap2() && timer == &dm_timers[0]) {
-                /* Enable wake-up only for GPT1 on OMAP2 CPUs*/
+        l |= 0x02 << 3;  /* Set to smart-idle mode */
+        l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
+
+        /*
+         * Enable wake-up only for GPT1 on OMAP2 CPUs.
+         * FIXME: All timers should have wake-up enabled and clear
+         * PRCM status.
+         */
+        if (cpu_class_is_omap2() && (timer == &dm_timers[0]))
                 l |= 1 << 2;
-                /* Non-posted mode */
-                omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0);
-        }
         omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
+
+        /* Match hardware reset default of posted mode */
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
+                        OMAP_TIMER_CTRL_POSTED);
+        timer->posted = 1;
 }
 
 static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
@@ -434,9 +538,32 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
                 l &= ~OMAP_TIMER_CTRL_AR;
         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
+
+        /* REVISIT: hw feature, ttgr overtaking tldr? */
+        while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)))
+                cpu_relax();
+
         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 }
 
+/* Optimized set_load which removes costly spin wait in timer_start */
+void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
+                            unsigned int load)
+{
+        u32 l;
+
+        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+        if (autoreload)
+                l |= OMAP_TIMER_CTRL_AR;
+        else
+                l &= ~OMAP_TIMER_CTRL_AR;
+        l |= OMAP_TIMER_CTRL_ST;
+
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+}
+
 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
                              unsigned int match)
 {
@@ -451,7 +578,6 @@ void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
 }
 
-
 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
                            int toggle, int trigger)
 {
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 9cf83c4da9fa..c7f74064696c 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -15,95 +15,66 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/device.h>
+#include <linux/platform_device.h>
 #include <linux/wait.h>
 #include <linux/completion.h>
 #include <linux/interrupt.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
+#include <linux/io.h>
 
 #include <asm/arch/dma.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/dsp_common.h>
 #include <asm/arch/mcbsp.h>
 
-#ifdef CONFIG_MCBSP_DEBUG
-#define DBG(x...)       printk(x)
-#else
-#define DBG(x...)                       do { } while (0)
-#endif
-
-struct omap_mcbsp {
-        u32                          io_base;
-        u8                           id;
-        u8                           free;
-        omap_mcbsp_word_length       rx_word_length;
-        omap_mcbsp_word_length       tx_word_length;
-
-        omap_mcbsp_io_type_t         io_type; /* IRQ or poll */
-        /* IRQ based TX/RX */
-        int                          rx_irq;
-        int                          tx_irq;
-
-        /* DMA stuff */
-        u8                           dma_rx_sync;
-        short                        dma_rx_lch;
-        u8                           dma_tx_sync;
-        short                        dma_tx_lch;
-
-        /* Completion queues */
-        struct completion            tx_irq_completion;
-        struct completion            rx_irq_completion;
-        struct completion            tx_dma_completion;
-        struct completion            rx_dma_completion;
-
-        spinlock_t                   lock;
-};
-
 static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
-#ifdef CONFIG_ARCH_OMAP1
-static struct clk *mcbsp_dsp_ck = 0;
-static struct clk *mcbsp_api_ck = 0;
-static struct clk *mcbsp_dspxor_ck = 0;
-#endif
-#ifdef CONFIG_ARCH_OMAP2
-static struct clk *mcbsp1_ick = 0;
-static struct clk *mcbsp1_fck = 0;
-static struct clk *mcbsp2_ick = 0;
-static struct clk *mcbsp2_fck = 0;
-#endif
+
+#define omap_mcbsp_check_valid_id(id)   (mcbsp[id].pdata && \
+                                        mcbsp[id].pdata->ops && \
+                                        mcbsp[id].pdata->ops->check && \
+                                        (mcbsp[id].pdata->ops->check(id) == 0))
 
 static void omap_mcbsp_dump_reg(u8 id)
 {
-        DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);
-        DBG("DRR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
-        DBG("DRR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
-        DBG("DXR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
-        DBG("DXR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
-        DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
-        DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
-        DBG("RCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
-        DBG("RCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
-        DBG("XCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
-        DBG("XCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
-        DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
-        DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
-        DBG("PCR0:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
-        DBG("***********************\n");
+        dev_dbg(mcbsp[id].dev, "**** McBSP%d regs ****\n", mcbsp[id].id);
+        dev_dbg(mcbsp[id].dev, "DRR2:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
+        dev_dbg(mcbsp[id].dev, "DRR1:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
+        dev_dbg(mcbsp[id].dev, "DXR2:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
+        dev_dbg(mcbsp[id].dev, "DXR1:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
+        dev_dbg(mcbsp[id].dev, "SPCR2: 0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
+        dev_dbg(mcbsp[id].dev, "SPCR1: 0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
+        dev_dbg(mcbsp[id].dev, "RCR2:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
+        dev_dbg(mcbsp[id].dev, "RCR1:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
+        dev_dbg(mcbsp[id].dev, "XCR2:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
+        dev_dbg(mcbsp[id].dev, "XCR1:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
+        dev_dbg(mcbsp[id].dev, "SRGR2: 0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
+        dev_dbg(mcbsp[id].dev, "SRGR1: 0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
+        dev_dbg(mcbsp[id].dev, "PCR0:  0x%04x\n",
+                        OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
+        dev_dbg(mcbsp[id].dev, "***********************\n");
 }
 
 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 {
         struct omap_mcbsp *mcbsp_tx = dev_id;
 
-        DBG("TX IRQ callback : 0x%x\n",
-            OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
+        dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n",
+                OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
 
         complete(&mcbsp_tx->tx_irq_completion);
+
         return IRQ_HANDLED;
 }
 
@@ -111,10 +82,11 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 {
         struct omap_mcbsp *mcbsp_rx = dev_id;
 
-        DBG("RX IRQ callback : 0x%x\n",
-            OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
+        dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n",
+                OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
 
         complete(&mcbsp_rx->rx_irq_completion);
+
         return IRQ_HANDLED;
 }
 
@@ -122,8 +94,8 @@ static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 {
         struct omap_mcbsp *mcbsp_dma_tx = data;
 
-        DBG("TX DMA callback : 0x%x\n",
-            OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
+        dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
+                OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
 
         /* We can free the channels */
         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
@@ -136,8 +108,8 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 {
         struct omap_mcbsp *mcbsp_dma_rx = data;
 
-        DBG("RX DMA callback : 0x%x\n",
-            OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
+        dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
+                OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
 
         /* We can free the channels */
         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
@@ -146,19 +118,24 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
         complete(&mcbsp_dma_rx->rx_dma_completion);
 }
 
-
 /*
  * omap_mcbsp_config simply write a config to the
  * appropriate McBSP.
  * You either call this function or set the McBSP registers
  * by yourself before calling omap_mcbsp_start().
  */
-
-void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config)
+void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 {
-        u32 io_base = mcbsp[id].io_base;
+        u32 io_base;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return;
+        }
 
-        DBG("OMAP-McBSP: McBSP%d  io_base: 0x%8x\n", id+1, io_base);
+        io_base = mcbsp[id].io_base;
+        dev_dbg(mcbsp[id].dev, "Configuring McBSP%d  io_base: 0x%8x\n",
+                        mcbsp[id].id, io_base);
 
         /* We write the given config */
         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
@@ -173,83 +150,7 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config
         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
 }
-
-
-
-static int omap_mcbsp_check(unsigned int id)
-{
-        if (cpu_is_omap730()) {
-                if (id > OMAP_MAX_MCBSP_COUNT - 1) {
-                       printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
-                       return -1;
-                }
-                return 0;
-        }
-
-        if (cpu_is_omap15xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) {
-                if (id > OMAP_MAX_MCBSP_COUNT) {
-                        printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
-                        return -1;
-                }
-                return 0;
-        }
-
-        return -1;
-}
-
-#ifdef CONFIG_ARCH_OMAP1
-static void omap_mcbsp_dsp_request(void)
-{
-        if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
-                int ret;
-
-                ret = omap_dsp_request_mem();
-                if (ret < 0) {
-                        printk(KERN_ERR "Could not get dsp memory: %i\n", ret);
-                        return;
-                }
-
-                clk_enable(mcbsp_dsp_ck);
-                clk_enable(mcbsp_api_ck);
-
-                /* enable 12MHz clock to mcbsp 1 & 3 */
-                clk_enable(mcbsp_dspxor_ck);
-
-                /*
-                 * DSP external peripheral reset
-                 * FIXME: This should be moved to dsp code
-                 */
-                __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
-                             DSP_RSTCT2);
-        }
-}
-
-static void omap_mcbsp_dsp_free(void)
-{
-        if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
-                omap_dsp_release_mem();
-                clk_disable(mcbsp_dspxor_ck);
-                clk_disable(mcbsp_dsp_ck);
-                clk_disable(mcbsp_api_ck);
-        }
-}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2
-static void omap2_mcbsp2_mux_setup(void)
-{
-        if (cpu_is_omap2420()) {
-                omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
-                omap_cfg_reg(R14_24XX_MCBSP2_FSX);
-                omap_cfg_reg(W15_24XX_MCBSP2_DR);
-                omap_cfg_reg(V15_24XX_MCBSP2_DX);
-                omap_cfg_reg(V14_24XX_GPIO117);
-        }
-        /*
-         * Need to add MUX settings for OMAP 2430 SDP
-         */
-}
-#endif
+EXPORT_SYMBOL(omap_mcbsp_config);
 
 /*
  * We can choose between IRQ based or polled IO.
@@ -257,13 +158,16 @@ static void omap2_mcbsp2_mux_setup(void)
  */
 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 {
-        if (omap_mcbsp_check(id) < 0)
-                return -EINVAL;
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
 
         spin_lock(&mcbsp[id].lock);
 
         if (!mcbsp[id].free) {
-                printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
+                dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",
+                        mcbsp[id].id);
                 spin_unlock(&mcbsp[id].lock);
                 return -EINVAL;
         }
@@ -274,38 +178,26 @@ int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 
         return 0;
 }
+EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 
 int omap_mcbsp_request(unsigned int id)
 {
         int err;
 
-        if (omap_mcbsp_check(id) < 0)
-                return -EINVAL;
-
-#ifdef CONFIG_ARCH_OMAP1
-        /*
-         * On 1510, 1610 and 1710, McBSP1 and McBSP3
-         * are DSP public peripherals.
-         */
-        if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
-                omap_mcbsp_dsp_request();
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2
-        if (cpu_is_omap24xx()) {
-                if (id == OMAP_MCBSP1) {
-                        clk_enable(mcbsp1_ick);
-                        clk_enable(mcbsp1_fck);
-                } else {
-                        clk_enable(mcbsp2_ick);
-                        clk_enable(mcbsp2_fck);
-                }
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
         }
-#endif
+
+        if (mcbsp[id].pdata->ops->request)
+                mcbsp[id].pdata->ops->request(id);
+
+        clk_enable(mcbsp[id].clk);
 
         spin_lock(&mcbsp[id].lock);
         if (!mcbsp[id].free) {
-                printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
+                dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",
+                        mcbsp[id].id);
                 spin_unlock(&mcbsp[id].lock);
                 return -1;
         }
@@ -315,24 +207,23 @@ int omap_mcbsp_request(unsigned int id)
 
         if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
                 /* We need to get IRQs here */
-                err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0,
-                                  "McBSP",
-                                  (void *) (&mcbsp[id]));
+                err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler,
+                                        0, "McBSP", (void *) (&mcbsp[id]));
                 if (err != 0) {
-                        printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for McBSP%d\n",
-                               mcbsp[id].tx_irq, mcbsp[id].id);
+                        dev_err(mcbsp[id].dev, "Unable to request TX IRQ %d "
+                                        "for McBSP%d\n", mcbsp[id].tx_irq,
+                                        mcbsp[id].id);
                         return err;
                 }
 
                 init_completion(&(mcbsp[id].tx_irq_completion));
 
-
-                err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0,
-                                  "McBSP",
-                                  (void *) (&mcbsp[id]));
+                err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler,
+                                        0, "McBSP", (void *) (&mcbsp[id]));
                 if (err != 0) {
-                        printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for McBSP%d\n",
-                               mcbsp[id].rx_irq, mcbsp[id].id);
+                        dev_err(mcbsp[id].dev, "Unable to request RX IRQ %d "
+                                        "for McBSP%d\n", mcbsp[id].rx_irq,
+                                        mcbsp[id].id);
                         free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
                         return err;
                 }
@@ -341,36 +232,25 @@ int omap_mcbsp_request(unsigned int id)
         }
 
         return 0;
-
 }
+EXPORT_SYMBOL(omap_mcbsp_request);
 
 void omap_mcbsp_free(unsigned int id)
 {
-        if (omap_mcbsp_check(id) < 0)
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
                 return;
-
-#ifdef CONFIG_ARCH_OMAP1
-        if (cpu_class_is_omap1()) {
-                if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
-                        omap_mcbsp_dsp_free();
         }
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2
-        if (cpu_is_omap24xx()) {
-                if (id == OMAP_MCBSP1) {
-                        clk_disable(mcbsp1_ick);
-                        clk_disable(mcbsp1_fck);
-                } else {
-                        clk_disable(mcbsp2_ick);
-                        clk_disable(mcbsp2_fck);
-                }
-        }
-#endif
+
+        if (mcbsp[id].pdata->ops->free)
+                mcbsp[id].pdata->ops->free(id);
+
+        clk_disable(mcbsp[id].clk);
 
         spin_lock(&mcbsp[id].lock);
         if (mcbsp[id].free) {
-                printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 1);
+                dev_err(mcbsp[id].dev, "McBSP%d was not reserved\n",
+                        mcbsp[id].id);
                 spin_unlock(&mcbsp[id].lock);
                 return;
         }
@@ -384,6 +264,7 @@ void omap_mcbsp_free(unsigned int id)
                 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
         }
 }
+EXPORT_SYMBOL(omap_mcbsp_free);
 
 /*
  * Here we start the McBSP, by enabling the sample
@@ -395,13 +276,15 @@ void omap_mcbsp_start(unsigned int id)
         u32 io_base;
         u16 w;
 
-        if (omap_mcbsp_check(id) < 0)
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
                 return;
+        }
 
         io_base = mcbsp[id].io_base;
 
-        mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7);
-        mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7);
+        mcbsp[id].rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
+        mcbsp[id].tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
 
         /* Start the sample generator */
         w = OMAP_MCBSP_READ(io_base, SPCR2);
@@ -422,20 +305,22 @@ void omap_mcbsp_start(unsigned int id)
 
         /* Dump McBSP Regs */
         omap_mcbsp_dump_reg(id);
-
 }
+EXPORT_SYMBOL(omap_mcbsp_start);
 
 void omap_mcbsp_stop(unsigned int id)
 {
         u32 io_base;
         u16 w;
 
-        if (omap_mcbsp_check(id) < 0)
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
                 return;
+        }
 
         io_base = mcbsp[id].io_base;
 
-        /* Reset transmitter */
+        /* Reset transmitter */
         w = OMAP_MCBSP_READ(io_base, SPCR2);
         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
 
@@ -447,12 +332,19 @@ void omap_mcbsp_stop(unsigned int id)
         w = OMAP_MCBSP_READ(io_base, SPCR2);
         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
 }
-
+EXPORT_SYMBOL(omap_mcbsp_stop);
 
 /* polled mcbsp i/o operations */
 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 {
-        u32 base = mcbsp[id].io_base;
+        u32 base;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        base = mcbsp[id].io_base;
         writew(buf, base + OMAP_MCBSP_REG_DXR1);
         /* if frame sync error - clear the error */
         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
@@ -474,18 +366,27 @@ int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
                                        (XRST),
                                        base + OMAP_MCBSP_REG_SPCR2);
                                 udelay(10);
-                                printk(KERN_ERR
-                                       " Could not write to McBSP Register\n");
+                                dev_err(mcbsp[id].dev, "Could not write to"
+                                        " McBSP%d Register\n", mcbsp[id].id);
                                 return -2;
                         }
                 }
         }
+
         return 0;
 }
+EXPORT_SYMBOL(omap_mcbsp_pollwrite);
 
-int omap_mcbsp_pollread(unsigned int id, u16 * buf)
+int omap_mcbsp_pollread(unsigned int id, u16 *buf)
 {
-        u32 base = mcbsp[id].io_base;
+        u32 base;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        base = mcbsp[id].io_base;
         /* if frame sync error - clear the error */
         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
                 /* clear error */
@@ -506,15 +407,17 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf)
                                        (RRST),
                                        base + OMAP_MCBSP_REG_SPCR1);
                                 udelay(10);
-                                printk(KERN_ERR
-                                       " Could not read from McBSP Register\n");
+                                dev_err(mcbsp[id].dev, "Could not read from"
+                                        " McBSP%d Register\n", mcbsp[id].id);
                                 return -2;
                         }
                 }
         }
         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
+
         return 0;
 }
+EXPORT_SYMBOL(omap_mcbsp_pollread);
 
 /*
  * IRQ based word transmission.
@@ -522,12 +425,15 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf)
 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 {
         u32 io_base;
-        omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;
+        omap_mcbsp_word_length word_length;
 
-        if (omap_mcbsp_check(id) < 0)
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
                 return;
+        }
 
         io_base = mcbsp[id].io_base;
+        word_length = mcbsp[id].tx_word_length;
 
         wait_for_completion(&(mcbsp[id].tx_irq_completion));
 
@@ -535,16 +441,20 @@ void omap_mcbsp_xmit_word(unsigned int id, u32 word)
                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 }
+EXPORT_SYMBOL(omap_mcbsp_xmit_word);
 
 u32 omap_mcbsp_recv_word(unsigned int id)
 {
         u32 io_base;
         u16 word_lsb, word_msb = 0;
-        omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;
+        omap_mcbsp_word_length word_length;
 
-        if (omap_mcbsp_check(id) < 0)
-                return -EINVAL;
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
 
+        word_length = mcbsp[id].rx_word_length;
         io_base = mcbsp[id].io_base;
 
         wait_for_completion(&(mcbsp[id].rx_irq_completion));
@@ -555,15 +465,24 @@ u32 omap_mcbsp_recv_word(unsigned int id)
 
         return (word_lsb | (word_msb << 16));
 }
-
+EXPORT_SYMBOL(omap_mcbsp_recv_word);
 
 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 {
-        u32 io_base = mcbsp[id].io_base;
-        omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
-        omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
+        u32 io_base;
+        omap_mcbsp_word_length tx_word_length;
+        omap_mcbsp_word_length rx_word_length;
         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        io_base = mcbsp[id].io_base;
+        tx_word_length = mcbsp[id].tx_word_length;
+        rx_word_length = mcbsp[id].rx_word_length;
+
         if (tx_word_length != rx_word_length)
                 return -EINVAL;
 
@@ -577,7 +496,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
                         udelay(10);
                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
                         udelay(10);
-                        printk("McBSP transmitter not ready\n");
+                        dev_err(mcbsp[id].dev, "McBSP%d transmitter not "
+                                "ready\n", mcbsp[id].id);
                         return -EAGAIN;
                 }
         }
@@ -597,7 +517,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
                         udelay(10);
                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
                         udelay(10);
-                        printk("McBSP receiver not ready\n");
+                        dev_err(mcbsp[id].dev, "McBSP%d receiver not "
+                                "ready\n", mcbsp[id].id);
                         return -EAGAIN;
                 }
         }
@@ -609,14 +530,24 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 
         return 0;
 }
+EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
 
-int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
+int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
 {
-        u32 io_base = mcbsp[id].io_base, clock_word = 0;
-        omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
-        omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
+        u32 io_base, clock_word = 0;
+        omap_mcbsp_word_length tx_word_length;
+        omap_mcbsp_word_length rx_word_length;
         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+
+        io_base = mcbsp[id].io_base;
+        tx_word_length = mcbsp[id].tx_word_length;
+        rx_word_length = mcbsp[id].rx_word_length;
+
         if (tx_word_length != rx_word_length)
                 return -EINVAL;
 
@@ -630,7 +561,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
                         udelay(10);
                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
                         udelay(10);
-                        printk("McBSP transmitter not ready\n");
+                        dev_err(mcbsp[id].dev, "McBSP%d transmitter not "
+                                "ready\n", mcbsp[id].id);
                         return -EAGAIN;
                 }
         }
@@ -650,7 +582,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
                         udelay(10);
                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
                         udelay(10);
-                        printk("McBSP receiver not ready\n");
+                        dev_err(mcbsp[id].dev, "McBSP%d receiver not "
+                                "ready\n", mcbsp[id].id);
                         return -EAGAIN;
                 }
         }
@@ -664,7 +597,7 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
 
         return 0;
 }
-
+EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
 
 /*
  * Simple DMA based buffer rx/tx routines.
@@ -673,25 +606,32 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
  * For anything fancier, you should use your own customized DMA
  * routines and callbacks.
  */
-int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
+int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
+                                unsigned int length)
 {
         int dma_tx_ch;
         int src_port = 0;
         int dest_port = 0;
         int sync_dev = 0;
 
-        if (omap_mcbsp_check(id) < 0)
-                return -EINVAL;
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
 
-        if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", omap_mcbsp_tx_dma_callback,
-                             &mcbsp[id],
-                             &dma_tx_ch)) {
-                printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d TX. Trying IRQ based TX\n", id+1);
+        if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX",
+                                omap_mcbsp_tx_dma_callback,
+                                &mcbsp[id],
+                                &dma_tx_ch)) {
+                dev_err(mcbsp[id].dev, " Unable to request DMA channel for "
+                                "McBSP%d TX. Trying IRQ based TX\n",
+                                mcbsp[id].id);
                 return -EAGAIN;
         }
         mcbsp[id].dma_tx_lch = dma_tx_ch;
 
-        DBG("TX DMA on channel %d\n", dma_tx_ch);
+        dev_err(mcbsp[id].dev, "McBSP%d TX DMA on channel %d\n", mcbsp[id].id,
+                dma_tx_ch);
 
         init_completion(&(mcbsp[id].tx_dma_completion));
 
@@ -699,7 +639,7 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
                 src_port = OMAP_DMA_PORT_TIPB;
                 dest_port = OMAP_DMA_PORT_EMIFF;
         }
-        if (cpu_is_omap24xx())
+        if (cpu_class_is_omap2())
                 sync_dev = mcbsp[id].dma_tx_sync;
 
         omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
@@ -722,29 +662,37 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
 
         omap_start_dma(mcbsp[id].dma_tx_lch);
         wait_for_completion(&(mcbsp[id].tx_dma_completion));
+
         return 0;
 }
+EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
 
-
-int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
+int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
+                                unsigned int length)
 {
         int dma_rx_ch;
         int src_port = 0;
         int dest_port = 0;
         int sync_dev = 0;
 
-        if (omap_mcbsp_check(id) < 0)
-                return -EINVAL;
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
 
-        if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", omap_mcbsp_rx_dma_callback,
-                             &mcbsp[id],
-                             &dma_rx_ch)) {
-                printk("Unable to request DMA channel for McBSP%d RX. Trying IRQ based RX\n", id+1);
+        if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX",
+                                omap_mcbsp_rx_dma_callback,
+                                &mcbsp[id],
+                                &dma_rx_ch)) {
+                dev_err(mcbsp[id].dev, "Unable to request DMA channel for "
+                                "McBSP%d RX. Trying IRQ based RX\n",
+                                mcbsp[id].id);
                 return -EAGAIN;
         }
         mcbsp[id].dma_rx_lch = dma_rx_ch;
 
-        DBG("RX DMA on channel %d\n", dma_rx_ch);
+        dev_err(mcbsp[id].dev, "McBSP%d RX DMA on channel %d\n", mcbsp[id].id,
+                dma_rx_ch);
 
         init_completion(&(mcbsp[id].rx_dma_completion));
 
@@ -752,14 +700,14 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
                 src_port = OMAP_DMA_PORT_TIPB;
                 dest_port = OMAP_DMA_PORT_EMIFF;
         }
-        if (cpu_is_omap24xx())
+        if (cpu_class_is_omap2())
                 sync_dev = mcbsp[id].dma_rx_sync;
 
         omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
-                                     OMAP_DMA_DATA_TYPE_S16,
-                                     length >> 1, 1,
-                                     OMAP_DMA_SYNC_ELEMENT,
-         sync_dev, 0);
+                                        OMAP_DMA_DATA_TYPE_S16,
+                                        length >> 1, 1,
+                                        OMAP_DMA_SYNC_ELEMENT,
+                                        sync_dev, 0);
 
         omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
                                 src_port,
@@ -768,16 +716,17 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
                                 0, 0);
 
         omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
-                                 dest_port,
-                                 OMAP_DMA_AMODE_POST_INC,
-                                 buffer,
-                                 0, 0);
+                                        dest_port,
+                                        OMAP_DMA_AMODE_POST_INC,
+                                        buffer,
+                                        0, 0);
 
         omap_start_dma(mcbsp[id].dma_rx_lch);
         wait_for_completion(&(mcbsp[id].rx_dma_completion));
+
         return 0;
 }
-
+EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
 
 /*
  * SPI wrapper.
@@ -785,12 +734,15 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
  * Once this is done, you can call omap_mcbsp_start().
  */
-void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg)
+void omap_mcbsp_set_spi_mode(unsigned int id,
+                                const struct omap_mcbsp_spi_cfg *spi_cfg)
 {
         struct omap_mcbsp_reg_cfg mcbsp_cfg;
 
-        if (omap_mcbsp_check(id) < 0)
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
                 return;
+        }
 
         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
 
@@ -798,7 +750,7 @@ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg *
         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
 
-        /* Clock stop mode */
+        /* Clock stop mode */
         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
                 mcbsp_cfg.spcr1 |= (1 << 12);
         else
@@ -827,13 +779,12 @@ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg *
 
         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
                 mcbsp_cfg.pcr0 |= CLKXM;
-                mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1);
+                mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
                 mcbsp_cfg.pcr0 |= FSXM;
                 mcbsp_cfg.srgr2 &= ~FSGM;
                 mcbsp_cfg.xcr2 |= XDATDLY(1);
                 mcbsp_cfg.rcr2 |= RDATDLY(1);
-        }
-        else {
+        } else {
                 mcbsp_cfg.pcr0 &= ~CLKXM;
                 mcbsp_cfg.srgr1 |= CLKGDV(1);
                 mcbsp_cfg.pcr0 &= ~FSXM;
@@ -846,199 +797,99 @@ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg *
 
         omap_mcbsp_config(id, &mcbsp_cfg);
 }
-
+EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
 
 /*
  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
  * 730 has only 2 McBSP, and both of them are MPU peripherals.
  */
-struct omap_mcbsp_info {
-        u32 virt_base;
-        u8 dma_rx_sync, dma_tx_sync;
-        u16 rx_irq, tx_irq;
-};
+static int __init omap_mcbsp_probe(struct platform_device *pdev)
+{
+        struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
+        int id = pdev->id - 1;
+        int ret = 0;
 
-#ifdef CONFIG_ARCH_OMAP730
-static const struct omap_mcbsp_info mcbsp_730[] = {
-        [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
-                .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
-                .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
-                .rx_irq = INT_730_McBSP1RX,
-                .tx_irq = INT_730_McBSP1TX },
-        [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
-                .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
-                .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
-                .rx_irq = INT_730_McBSP2RX,
-                .tx_irq = INT_730_McBSP2TX },
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP15XX
-static const struct omap_mcbsp_info mcbsp_1510[] = {
-        [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
-                .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
-                .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
-                .rx_irq = INT_McBSP1RX,
-                .tx_irq = INT_McBSP1TX },
-        [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
-                .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
-                .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
-                .rx_irq = INT_1510_SPI_RX,
-                .tx_irq = INT_1510_SPI_TX },
-        [2] = { .virt_base = OMAP1510_MCBSP3_BASE,
-                .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
-                .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
-                .rx_irq = INT_McBSP3RX,
-                .tx_irq = INT_McBSP3TX },
-};
-#endif
-
-#if defined(CONFIG_ARCH_OMAP16XX)
-static const struct omap_mcbsp_info mcbsp_1610[] = {
-        [0] = { .virt_base = OMAP1610_MCBSP1_BASE,
-                .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
-                .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
-                .rx_irq = INT_McBSP1RX,
-                .tx_irq = INT_McBSP1TX },
-        [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
-                .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
-                .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
-                .rx_irq = INT_1610_McBSP2_RX,
-                .tx_irq = INT_1610_McBSP2_TX },
-        [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
-                .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
-                .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
-                .rx_irq = INT_McBSP3RX,
-                .tx_irq = INT_McBSP3TX },
-};
-#endif
-
-#if defined(CONFIG_ARCH_OMAP24XX)
-static const struct omap_mcbsp_info mcbsp_24xx[] = {
-        [0] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
-                .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
-                .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
-                .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
-                .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
-                },
-        [1] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
-                .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
-                .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
-                .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
-                .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
-                },
-};
-#endif
+        if (!pdata) {
+                dev_err(&pdev->dev, "McBSP device initialized without"
+                                "platform data\n");
+                ret = -EINVAL;
+                goto exit;
+        }
+
+        dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
+
+        if (id >= OMAP_MAX_MCBSP_COUNT) {
+                dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
+                ret = -EINVAL;
+                goto exit;
+        }
+
+        spin_lock_init(&mcbsp[id].lock);
+        mcbsp[id].id = id + 1;
+        mcbsp[id].free = 1;
+        mcbsp[id].dma_tx_lch = -1;
+        mcbsp[id].dma_rx_lch = -1;
+
+        mcbsp[id].io_base = pdata->virt_base;
+        /* Default I/O is IRQ based */
+        mcbsp[id].io_type = OMAP_MCBSP_IRQ_IO;
+        mcbsp[id].tx_irq = pdata->tx_irq;
+        mcbsp[id].rx_irq = pdata->rx_irq;
+        mcbsp[id].dma_rx_sync = pdata->dma_rx_sync;
+        mcbsp[id].dma_tx_sync = pdata->dma_tx_sync;
+
+        if (pdata->clk_name)
+                mcbsp[id].clk = clk_get(&pdev->dev, pdata->clk_name);
+        if (IS_ERR(mcbsp[id].clk)) {
+                mcbsp[id].free = 0;
+                dev_err(&pdev->dev,
+                        "Invalid clock configuration for McBSP%d.\n",
+                        mcbsp[id].id);
+                ret = -EINVAL;
+                goto exit;
+        }
+
+        mcbsp[id].pdata = pdata;
+        mcbsp[id].dev = &pdev->dev;
+        platform_set_drvdata(pdev, &mcbsp[id]);
+
+exit:
+        return ret;
+}
 
-static int __init omap_mcbsp_init(void)
+static int omap_mcbsp_remove(struct platform_device *pdev)
 {
-        int mcbsp_count = 0, i;
-        static const struct omap_mcbsp_info *mcbsp_info;
+        struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 
-        printk("Initializing OMAP McBSP system\n");
+        platform_set_drvdata(pdev, NULL);
+        if (mcbsp) {
 
-#ifdef CONFIG_ARCH_OMAP1
-        mcbsp_dsp_ck = clk_get(0, "dsp_ck");
-        if (IS_ERR(mcbsp_dsp_ck)) {
-                printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
-                return PTR_ERR(mcbsp_dsp_ck);
-        }
-        mcbsp_api_ck = clk_get(0, "api_ck");
-        if (IS_ERR(mcbsp_api_ck)) {
-                printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
-                return PTR_ERR(mcbsp_api_ck);
-        }
-        mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
-        if (IS_ERR(mcbsp_dspxor_ck)) {
-                printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
-                return PTR_ERR(mcbsp_dspxor_ck);
-        }
-#endif
-#ifdef CONFIG_ARCH_OMAP2
-        mcbsp1_ick = clk_get(0, "mcbsp1_ick");
-        if (IS_ERR(mcbsp1_ick)) {
-                printk(KERN_ERR "mcbsp: could not acquire mcbsp1_ick handle.\n");
-                return PTR_ERR(mcbsp1_ick);
-        }
-        mcbsp1_fck = clk_get(0, "mcbsp1_fck");
-        if (IS_ERR(mcbsp1_fck)) {
-                printk(KERN_ERR "mcbsp: could not acquire mcbsp1_fck handle.\n");
-                return PTR_ERR(mcbsp1_fck);
-        }
-        mcbsp2_ick = clk_get(0, "mcbsp2_ick");
-        if (IS_ERR(mcbsp2_ick)) {
-                printk(KERN_ERR "mcbsp: could not acquire mcbsp2_ick handle.\n");
-                return PTR_ERR(mcbsp2_ick);
-        }
-        mcbsp2_fck = clk_get(0, "mcbsp2_fck");
-        if (IS_ERR(mcbsp2_fck)) {
-                printk(KERN_ERR "mcbsp: could not acquire mcbsp2_fck handle.\n");
-                return PTR_ERR(mcbsp2_fck);
-        }
-#endif
+                if (mcbsp->pdata && mcbsp->pdata->ops &&
+                                mcbsp->pdata->ops->free)
+                        mcbsp->pdata->ops->free(mcbsp->id);
 
-#ifdef CONFIG_ARCH_OMAP730
-        if (cpu_is_omap730()) {
-                mcbsp_info = mcbsp_730;
-                mcbsp_count = ARRAY_SIZE(mcbsp_730);
-        }
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        if (cpu_is_omap15xx()) {
-                mcbsp_info = mcbsp_1510;
-                mcbsp_count = ARRAY_SIZE(mcbsp_1510);
-        }
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
-        if (cpu_is_omap16xx()) {
-                mcbsp_info = mcbsp_1610;
-                mcbsp_count = ARRAY_SIZE(mcbsp_1610);
-        }
-#endif
-#if defined(CONFIG_ARCH_OMAP24XX)
-        if (cpu_is_omap24xx()) {
-                mcbsp_info = mcbsp_24xx;
-                mcbsp_count = ARRAY_SIZE(mcbsp_24xx);
-                omap2_mcbsp2_mux_setup();
-        }
-#endif
-        for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
-                if (i >= mcbsp_count) {
-                        mcbsp[i].io_base = 0;
-                        mcbsp[i].free = 0;
-                        continue;
-                }
-                mcbsp[i].id = i + 1;
-                mcbsp[i].free = 1;
-                mcbsp[i].dma_tx_lch = -1;
-                mcbsp[i].dma_rx_lch = -1;
-
-                mcbsp[i].io_base = mcbsp_info[i].virt_base;
-                mcbsp[i].io_type = OMAP_MCBSP_IRQ_IO; /* Default I/O is IRQ based */
-                mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
-                mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
-                mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
-                mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
-                spin_lock_init(&mcbsp[i].lock);
+                clk_disable(mcbsp->clk);
+                clk_put(mcbsp->clk);
+
+                mcbsp->clk = NULL;
+                mcbsp->free = 0;
+                mcbsp->dev = NULL;
         }
 
         return 0;
 }
 
-arch_initcall(omap_mcbsp_init);
+static struct platform_driver omap_mcbsp_driver = {
+        .probe          = omap_mcbsp_probe,
+        .remove         = omap_mcbsp_remove,
+        .driver         = {
+                .name   = "omap-mcbsp",
+        },
+};
+
+int __init omap_mcbsp_init(void)
+{
+        /* Register the McBSP driver */
+        return platform_driver_register(&omap_mcbsp_driver);
+}
 
-EXPORT_SYMBOL(omap_mcbsp_config);
-EXPORT_SYMBOL(omap_mcbsp_request);
-EXPORT_SYMBOL(omap_mcbsp_set_io_type);
-EXPORT_SYMBOL(omap_mcbsp_free);
-EXPORT_SYMBOL(omap_mcbsp_start);
-EXPORT_SYMBOL(omap_mcbsp_stop);
-EXPORT_SYMBOL(omap_mcbsp_pollread);
-EXPORT_SYMBOL(omap_mcbsp_pollwrite);
-EXPORT_SYMBOL(omap_mcbsp_xmit_word);
-EXPORT_SYMBOL(omap_mcbsp_recv_word);
-EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
-EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
-EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
-EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
-EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 1f23f0459e5f..554ee58e1294 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -10,6 +10,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#undef DEBUG
 
 #include <linux/module.h>
 #include <linux/kernel.h>
@@ -24,25 +25,43 @@
 #include <asm/arch/sram.h>
 #include <asm/arch/board.h>
 
+#include <asm/arch/control.h>
+
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+# include "../mach-omap2/prm.h"
+# include "../mach-omap2/cm.h"
+# include "../mach-omap2/sdrc.h"
+#endif
+
 #define OMAP1_SRAM_PA           0x20000000
-#define OMAP1_SRAM_VA           0xd0000000
+#define OMAP1_SRAM_VA           VMALLOC_END
 #define OMAP2_SRAM_PA           0x40200000
 #define OMAP2_SRAM_PUB_PA       0x4020f800
-#define OMAP2_SRAM_VA           0xd0000000
-#define OMAP2_SRAM_PUB_VA       0xd0000800
-
-#if defined(CONFIG_ARCH_OMAP24XX)
+#define OMAP2_SRAM_VA           VMALLOC_END
+#define OMAP2_SRAM_PUB_VA       (VMALLOC_END + 0x800)
+#define OMAP3_SRAM_PA           0x40200000
+#define OMAP3_SRAM_VA           0xd7000000
+#define OMAP3_SRAM_PUB_PA       0x40208000
+#define OMAP3_SRAM_PUB_VA       0xd7008000
+
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 #define SRAM_BOOTLOADER_SZ      0x00
 #else
 #define SRAM_BOOTLOADER_SZ      0x80
 #endif
 
-#define VA_REQINFOPERM0         IO_ADDRESS(0x68005048)
-#define VA_READPERM0            IO_ADDRESS(0x68005050)
-#define VA_WRITEPERM0           IO_ADDRESS(0x68005058)
-#define VA_CONTROL_STAT         IO_ADDRESS(0x480002F8)
+#define OMAP24XX_VA_REQINFOPERM0        IO_ADDRESS(0x68005048)
+#define OMAP24XX_VA_READPERM0           IO_ADDRESS(0x68005050)
+#define OMAP24XX_VA_WRITEPERM0          IO_ADDRESS(0x68005058)
+
+#define OMAP34XX_VA_REQINFOPERM0        IO_ADDRESS(0x68012848)
+#define OMAP34XX_VA_READPERM0           IO_ADDRESS(0x68012850)
+#define OMAP34XX_VA_WRITEPERM0          IO_ADDRESS(0x68012858)
+#define OMAP34XX_VA_ADDR_MATCH2         IO_ADDRESS(0x68012880)
+#define OMAP34XX_VA_SMS_RG_ATT0         IO_ADDRESS(0x6C000048)
+#define OMAP34XX_VA_CONTROL_STAT        IO_ADDRESS(0x480022F0)
+
 #define GP_DEVICE               0x300
-#define TYPE_MASK               0x700
 
 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
 
@@ -68,14 +87,21 @@ static int is_sram_locked(void)
         int type = 0;
 
         if (cpu_is_omap242x())
-                type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK;
+                type = system_rev & OMAP2_DEVICETYPE_MASK;
 
         if (type == GP_DEVICE) {
                 /* RAMFW: R/W access to all initiators for all qualifier sets */
                 if (cpu_is_omap242x()) {
-                        __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */
-                        __raw_writel(0xCFDE, VA_READPERM0);  /* all i-read */
-                        __raw_writel(0xCFDE, VA_WRITEPERM0); /* all i-write */
+                        __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
+                        __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
+                        __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
+                }
+                if (cpu_is_omap34xx()) {
+                        __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
+                        __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
+                        __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
+                        __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
+                        __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
                 }
                 return 0;
         } else
@@ -92,18 +118,30 @@ void __init omap_detect_sram(void)
 {
         unsigned long reserved;
 
-        if (cpu_is_omap24xx()) {
+        if (cpu_class_is_omap2()) {
                 if (is_sram_locked()) {
-                        omap_sram_base = OMAP2_SRAM_PUB_VA;
-                        omap_sram_start = OMAP2_SRAM_PUB_PA;
-                        omap_sram_size = 0x800; /* 2K */
+                        if (cpu_is_omap34xx()) {
+                                omap_sram_base = OMAP3_SRAM_PUB_VA;
+                                omap_sram_start = OMAP3_SRAM_PUB_PA;
+                                omap_sram_size = 0x8000; /* 32K */
+                        } else {
+                                omap_sram_base = OMAP2_SRAM_PUB_VA;
+                                omap_sram_start = OMAP2_SRAM_PUB_PA;
+                                omap_sram_size = 0x800; /* 2K */
+                        }
                 } else {
-                        omap_sram_base = OMAP2_SRAM_VA;
-                        omap_sram_start = OMAP2_SRAM_PA;
-                        if (cpu_is_omap242x())
-                                omap_sram_size = 0xa0000; /* 640K */
-                        else if (cpu_is_omap243x())
+                        if (cpu_is_omap34xx()) {
+                                omap_sram_base = OMAP3_SRAM_VA;
+                                omap_sram_start = OMAP3_SRAM_PA;
                                 omap_sram_size = 0x10000; /* 64K */
+                        } else {
+                                omap_sram_base = OMAP2_SRAM_VA;
+                                omap_sram_start = OMAP2_SRAM_PA;
+                                if (cpu_is_omap242x())
+                                        omap_sram_size = 0xa0000; /* 640K */
+                                else if (cpu_is_omap243x())
+                                        omap_sram_size = 0x10000; /* 64K */
+                        }
                 }
         } else {
                 omap_sram_base = OMAP1_SRAM_VA;
@@ -157,6 +195,13 @@ void __init omap_map_sram(void)
                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
         }
 
+        if (cpu_is_omap34xx()) {
+                omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
+                base = OMAP3_SRAM_PA;
+                base = ROUND_DOWN(base, PAGE_SIZE);
+                omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
+        }
+
         omap_sram_io_desc[0].length = 1024 * 1024;      /* Use section desc */
         iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
 
@@ -191,6 +236,7 @@ void * omap_sram_push(void * start, unsigned long size)
         omap_sram_ceil -= size;
         omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
         memcpy((void *)omap_sram_ceil, start, size);
+        flush_icache_range((unsigned long)start, (unsigned long)(start + size));
 
         return (void *)omap_sram_ceil;
 }
@@ -214,8 +260,9 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 
 int __init omap1_sram_init(void)
 {
-        _omap_sram_reprogram_clock = omap_sram_push(sram_reprogram_clock,
-                                                    sram_reprogram_clock_sz);
+        _omap_sram_reprogram_clock =
+                        omap_sram_push(omap1_sram_reprogram_clock,
+                                        omap1_sram_reprogram_clock_sz);
 
         return 0;
 }
@@ -224,7 +271,7 @@ int __init omap1_sram_init(void)
 #define omap1_sram_init()       do {} while (0)
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 
 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
                               u32 base_cs, u32 force_unlock);
@@ -259,19 +306,109 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 
         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 }
+#endif
+
+#ifdef CONFIG_ARCH_OMAP2420
+int __init omap242x_sram_init(void)
+{
+        _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
+                                        omap242x_sram_ddr_init_sz);
+
+        _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
+                                            omap242x_sram_reprogram_sdrc_sz);
+
+        _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
+                                         omap242x_sram_set_prcm_sz);
+
+        return 0;
+}
+#else
+static inline int omap242x_sram_init(void)
+{
+        return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP2430
+int __init omap243x_sram_init(void)
+{
+        _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
+                                        omap243x_sram_ddr_init_sz);
+
+        _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
+                                            omap243x_sram_reprogram_sdrc_sz);
+
+        _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
+                                         omap243x_sram_set_prcm_sz);
+
+        return 0;
+}
+#else
+static inline int omap243x_sram_init(void)
+{
+        return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+
+static u32 (*_omap2_sram_reprogram_gpmc)(u32 perf_level);
+u32 omap2_sram_reprogram_gpmc(u32 perf_level)
+{
+        if (!_omap2_sram_reprogram_gpmc)
+                omap_sram_error();
+
+        return _omap2_sram_reprogram_gpmc(perf_level);
+}
+
+static u32 (*_omap2_sram_configure_core_dpll)(u32 m, u32 n,
+                                                u32 freqsel, u32 m2);
+u32 omap2_sram_configure_core_dpll(u32 m, u32 n, u32 freqsel, u32 m2)
+{
+        if (!_omap2_sram_configure_core_dpll)
+                omap_sram_error();
+
+        return _omap2_sram_configure_core_dpll(m, n, freqsel, m2);
+}
 
-int __init omap2_sram_init(void)
+/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
+void restore_sram_functions(void)
 {
-        _omap2_sram_ddr_init = omap_sram_push(sram_ddr_init, sram_ddr_init_sz);
+        omap_sram_ceil = omap_sram_base + omap_sram_size;
 
-        _omap2_sram_reprogram_sdrc = omap_sram_push(sram_reprogram_sdrc,
-                                                    sram_reprogram_sdrc_sz);
-        _omap2_set_prcm = omap_sram_push(sram_set_prcm, sram_set_prcm_sz);
+        _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
+                omap34xx_sram_reprogram_gpmc_sz);
+
+        _omap2_sram_configure_core_dpll =
+                        omap_sram_push(omap34xx_sram_configure_core_dpll,
+                                        omap34xx_sram_configure_core_dpll_sz);
+}
+
+int __init omap34xx_sram_init(void)
+{
+        _omap2_sram_ddr_init = omap_sram_push(omap34xx_sram_ddr_init,
+                                        omap34xx_sram_ddr_init_sz);
+
+        _omap2_sram_reprogram_sdrc = omap_sram_push(omap34xx_sram_reprogram_sdrc,
+                                        omap34xx_sram_reprogram_sdrc_sz);
+
+        _omap2_set_prcm = omap_sram_push(omap34xx_sram_set_prcm,
+                                        omap34xx_sram_set_prcm_sz);
+
+        _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
+                                        omap34xx_sram_reprogram_gpmc_sz);
+
+        _omap2_sram_configure_core_dpll =
+                                omap_sram_push(omap34xx_sram_configure_core_dpll,
+                                        omap34xx_sram_configure_core_dpll_sz);
 
         return 0;
 }
 #else
-#define omap2_sram_init()       do {} while (0)
+static inline int omap34xx_sram_init(void)
+{
+        return 0;
+}
 #endif
 
 int __init omap_sram_init(void)
@@ -279,10 +416,14 @@ int __init omap_sram_init(void)
         omap_detect_sram();
         omap_map_sram();
 
-        if (!cpu_is_omap24xx())
+        if (!(cpu_class_is_omap2()))
                 omap1_sram_init();
-        else
-                omap2_sram_init();
+        else if (cpu_is_omap242x())
+                omap242x_sram_init();
+        else if (cpu_is_omap2430())
+                omap243x_sram_init();
+        else if (cpu_is_omap34xx())
+                omap34xx_sram_init();
 
         return 0;
 }
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index a619475c4b76..2699c16d4da0 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -1,4 +1,4 @@
-/*
+ /*
  * arch/arm/plat-omap/usb.c -- platform level USB initialization
  *
  * Copyright (C) 2004 Texas Instruments, Inc.
@@ -156,8 +156,12 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 
         if (nwires == 0) {
                 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
+                        u32 l;
+
                         /* pulldown D+/D- */
-                        USB_TRANSCEIVER_CTRL_REG &= ~(3 << 1);
+                        l = omap_readl(USB_TRANSCEIVER_CTRL);
+                        l &= ~(3 << 1);
+                        omap_writel(l, USB_TRANSCEIVER_CTRL);
                 }
                 return 0;
         }
@@ -171,6 +175,8 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 
         /* internal transceiver (unavailable on 17xx, 24xx) */
         if (!cpu_class_is_omap2() && nwires == 2) {
+                u32 l;
+
                 // omap_cfg_reg(P9_USB_DP);
                 // omap_cfg_reg(R8_USB_DM);
 
@@ -185,9 +191,11 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
                  *  - OTG support on this port not yet written
                  */
 
-                USB_TRANSCEIVER_CTRL_REG &= ~(7 << 4);
+                l = omap_readl(USB_TRANSCEIVER_CTRL);
+                l &= ~(7 << 4);
                 if (!is_device)
-                        USB_TRANSCEIVER_CTRL_REG |= (3 << 1);
+                        l |= (3 << 1);
+                omap_writel(l, USB_TRANSCEIVER_CTRL);
 
                 return 3 << 16;
         }
@@ -217,8 +225,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
          * with VBUS switching and overcurrent detection.
          */
 
-        if (cpu_class_is_omap1() && nwires != 6)
-                USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R;
+        if (cpu_class_is_omap1() && nwires != 6) {
+                u32 l;
+
+                l = omap_readl(USB_TRANSCEIVER_CTRL);
+                l &= ~CONF_USB2_UNI_R;
+                omap_writel(l, USB_TRANSCEIVER_CTRL);
+        }
 
         switch (nwires) {
         case 3:
@@ -238,9 +251,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
                         omap_cfg_reg(K20_24XX_USB0_VM);
                         omap2_usb_devconf_set(0, USB_UNIDIR);
                 } else {
+                        u32 l;
+
                         omap_cfg_reg(AA9_USB0_VP);
                         omap_cfg_reg(R9_USB0_VM);
-                        USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R;
+                        l = omap_readl(USB_TRANSCEIVER_CTRL);
+                        l |= CONF_USB2_UNI_R;
+                        omap_writel(l, USB_TRANSCEIVER_CTRL);
                 }
                 break;
         default:
@@ -254,8 +271,13 @@ static u32 __init omap_usb1_init(unsigned nwires)
 {
         u32     syscon1 = 0;
 
-        if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6)
-                USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R;
+        if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
+                u32 l;
+
+                l = omap_readl(USB_TRANSCEIVER_CTRL);
+                l &= ~CONF_USB1_UNI_R;
+                omap_writel(l, USB_TRANSCEIVER_CTRL);
+        }
         if (cpu_is_omap24xx())
                 omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
 
@@ -316,8 +338,13 @@ static u32 __init omap_usb1_init(unsigned nwires)
                 syscon1 = 3;
                 omap_cfg_reg(USB1_VP);
                 omap_cfg_reg(USB1_VM);
-                if (!cpu_is_omap15xx())
-                        USB_TRANSCEIVER_CTRL_REG |= CONF_USB1_UNI_R;
+                if (!cpu_is_omap15xx()) {
+                        u32 l;
+
+                        l = omap_readl(USB_TRANSCEIVER_CTRL);
+                        l |= CONF_USB1_UNI_R;
+                        omap_writel(l, USB_TRANSCEIVER_CTRL);
+                }
                 break;
         default:
 bad:
@@ -340,8 +367,13 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
         if (alt_pingroup || nwires == 0)
                 return 0;
 
-        if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6)
-                USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R;
+        if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
+                u32 l;
+
+                l = omap_readl(USB_TRANSCEIVER_CTRL);
+                l &= ~CONF_USB2_UNI_R;
+                omap_writel(l, USB_TRANSCEIVER_CTRL);
+        }
 
         /* external transceiver */
         if (cpu_is_omap15xx()) {
@@ -410,9 +442,13 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
                         omap_cfg_reg(USB2_VP);
                         omap_cfg_reg(USB2_VM);
                 } else {
+                        u32 l;
+
                         omap_cfg_reg(AA9_USB2_VP);
                         omap_cfg_reg(R9_USB2_VM);
-                        USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R;
+                        l = omap_readl(USB_TRANSCEIVER_CTRL);
+                        l |= CONF_USB2_UNI_R;
+                        omap_writel(l, USB_TRANSCEIVER_CTRL);
                 }
                 break;
         default:
@@ -531,10 +567,6 @@ static struct platform_device otg_device = {
 
 /*-------------------------------------------------------------------------*/
 
-#define ULPD_CLOCK_CTRL_REG     __REG16(ULPD_CLOCK_CTRL)
-#define ULPD_SOFT_REQ_REG       __REG16(ULPD_SOFT_REQ)
-
-
 // FIXME correct answer depends on hmc_mode,
 // as does (on omap1) any nonzero value for config->otg port number
 #ifdef  CONFIG_USB_GADGET_OMAP
@@ -550,17 +582,17 @@ static struct platform_device otg_device = {
 void __init
 omap_otg_init(struct omap_usb_config *config)
 {
-        u32             syscon = OTG_SYSCON_1_REG & 0xffff;
+        u32             syscon;
         int             status;
         int             alt_pingroup = 0;
 
         /* NOTE:  no bus or clock setup (yet?) */
 
-        syscon = OTG_SYSCON_1_REG & 0xffff;
+        syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
         if (!(syscon & OTG_RESET_DONE))
                 pr_debug("USB resets not complete?\n");
 
-        // OTG_IRQ_EN_REG = 0;
+        //omap_writew(0, OTG_IRQ_EN);
 
         /* pin muxing and transceiver pinouts */
         if (config->pins[0] > 2)        /* alt pingroup 2 */
@@ -568,8 +600,8 @@ omap_otg_init(struct omap_usb_config *config)
         syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config));
         syscon |= omap_usb1_init(config->pins[1]);
         syscon |= omap_usb2_init(config->pins[2], alt_pingroup);
-        pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon);
-        OTG_SYSCON_1_REG = syscon;
+        pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
+        omap_writel(syscon, OTG_SYSCON_1);
 
         syscon = config->hmc_mode;
         syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
@@ -578,9 +610,10 @@ omap_otg_init(struct omap_usb_config *config)
                 syscon |= OTG_EN;
 #endif
         if (cpu_class_is_omap1())
-                pr_debug("USB_TRANSCEIVER_CTRL_REG = %03x\n", USB_TRANSCEIVER_CTRL_REG);
-        pr_debug("OTG_SYSCON_2_REG = %08x\n", syscon);
-        OTG_SYSCON_2_REG = syscon;
+                pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
+                         omap_readl(USB_TRANSCEIVER_CTRL));
+        pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
+        omap_writel(syscon, OTG_SYSCON_2);
 
         printk("USB: hmc %d", config->hmc_mode);
         if (!alt_pingroup)
@@ -597,12 +630,19 @@ omap_otg_init(struct omap_usb_config *config)
         printk("\n");
 
         if (cpu_class_is_omap1()) {
+                u16 w;
+
                 /* leave USB clocks/controllers off until needed */
-                ULPD_SOFT_REQ_REG &= ~SOFT_USB_CLK_REQ;
-                ULPD_CLOCK_CTRL_REG &= ~USB_MCLK_EN;
-                ULPD_CLOCK_CTRL_REG |= DIS_USB_PVCI_CLK;
+                w = omap_readw(ULPD_SOFT_REQ);
+                w &= ~SOFT_USB_CLK_REQ;
+                omap_writew(w, ULPD_SOFT_REQ);
+
+                w = omap_readw(ULPD_CLOCK_CTRL);
+                w &= ~USB_MCLK_EN;
+                w |= DIS_USB_PVCI_CLK;
+                omap_writew(w, ULPD_CLOCK_CTRL);
         }
-        syscon = OTG_SYSCON_1_REG;
+        syscon = omap_readl(OTG_SYSCON_1);
         syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
 
 #ifdef  CONFIG_USB_GADGET_OMAP
@@ -639,8 +679,8 @@ omap_otg_init(struct omap_usb_config *config)
                         pr_debug("can't register OTG device, %d\n", status);
         }
 #endif
-        pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon);
-        OTG_SYSCON_1_REG = syscon;
+        pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
+        omap_writel(syscon, OTG_SYSCON_1);
 
         status = 0;
 }
@@ -653,18 +693,19 @@ static inline void omap_otg_init(struct omap_usb_config *config) {}
 
 #ifdef  CONFIG_ARCH_OMAP15XX
 
-#define ULPD_DPLL_CTRL_REG      __REG16(ULPD_DPLL_CTRL)
+/* ULPD_DPLL_CTRL */
 #define DPLL_IOB                (1 << 13)
 #define DPLL_PLL_ENABLE         (1 << 4)
 #define DPLL_LOCK               (1 << 0)
 
-#define ULPD_APLL_CTRL_REG      __REG16(ULPD_APLL_CTRL)
+/* ULPD_APLL_CTRL */
 #define APLL_NDPLL_SWITCH       (1 << 0)
 
 
 static void __init omap_1510_usb_init(struct omap_usb_config *config)
 {
         unsigned int val;
+        u16 w;
 
         omap_usb0_init(config->pins[0], is_usb0_device(config));
         omap_usb1_init(config->pins[1]);
@@ -685,12 +726,22 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config)
         printk("\n");
 
         /* use DPLL for 48 MHz function clock */
-        pr_debug("APLL %04x DPLL %04x REQ %04x\n", ULPD_APLL_CTRL_REG,
-                        ULPD_DPLL_CTRL_REG, ULPD_SOFT_REQ_REG);
-        ULPD_APLL_CTRL_REG &= ~APLL_NDPLL_SWITCH;
-        ULPD_DPLL_CTRL_REG |= DPLL_IOB | DPLL_PLL_ENABLE;
-        ULPD_SOFT_REQ_REG |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
-        while (!(ULPD_DPLL_CTRL_REG & DPLL_LOCK))
+        pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL),
+                        omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
+
+        w = omap_readw(ULPD_APLL_CTRL);
+        w &= ~APLL_NDPLL_SWITCH;
+        omap_writew(w, ULPD_APLL_CTRL);
+
+        w = omap_readw(ULPD_DPLL_CTRL);
+        w |= DPLL_IOB | DPLL_PLL_ENABLE;
+        omap_writew(w, ULPD_DPLL_CTRL);
+
+        w = omap_readw(ULPD_SOFT_REQ);
+        w |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
+        omap_writew(w, ULPD_SOFT_REQ);
+
+        while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
                 cpu_relax();
 
 #ifdef  CONFIG_USB_GADGET_OMAP
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index c5b669d234bc..fe66a1835169 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -36,8 +36,8 @@ static void orion_irq_unmask(u32 irq)
 
 static struct irq_chip orion_irq_chip = {
         .name           = "orion_irq",
-        .ack            = orion_irq_mask,
         .mask           = orion_irq_mask,
+        .mask_ack       = orion_irq_mask,
         .unmask         = orion_irq_unmask,
 };
 
@@ -59,6 +59,7 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
                 set_irq_chip(irq, &orion_irq_chip);
                 set_irq_chip_data(irq, maskaddr);
                 set_irq_handler(irq, handle_level_irq);
+                irq_desc[irq].status |= IRQ_LEVEL;
                 set_irq_flags(irq, IRQF_VALID);
         }
 }
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index abfda53f1800..ca32c60e14d7 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -39,6 +39,7 @@
 #define PCIE_CONF_DATA_OFF      0x18fc
 #define PCIE_MASK_OFF           0x1910
 #define PCIE_CTRL_OFF           0x1a00
+#define  PCIE_CTRL_X1_MODE              0x0001
 #define PCIE_STAT_OFF           0x1a04
 #define  PCIE_STAT_DEV_OFFS             20
 #define  PCIE_STAT_DEV_MASK             0x1f
@@ -62,6 +63,11 @@ int orion_pcie_link_up(void __iomem *base)
         return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
 }
 
+int __init orion_pcie_x4_mode(void __iomem *base)
+{
+        return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE);
+}
+
 int orion_pcie_get_local_bus_nr(void __iomem *base)
 {
         u32 stat = readl(base + PCIE_STAT_OFF);
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 28b5285446e8..93c4ef9f0067 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -74,7 +74,7 @@ orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
         /*
          * Clear and enable clockevent timer interrupt.
          */
-        writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+        writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
 
         u = readl(BRIDGE_MASK);
         u |= BRIDGE_INT_TIMER1;
@@ -138,7 +138,7 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
                 /*
                  * ACK pending timer interrupt.
                  */
-                writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+                writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
 
         }
         local_irq_restore(flags);
@@ -159,7 +159,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
         /*
          * ACK timer interrupt and call event handler.
          */
-        writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+        writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
         orion_clkevt.event_handler(&orion_clkevt);
 
         return IRQ_HANDLED;
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index b66fb3c4e228..5e28c217b8c2 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -9,6 +9,7 @@ config PLAT_S3C24XX
         depends on ARCH_S3C2410
         default y if ARCH_S3C2410
         select NO_IOPORT
+        select HAVE_GPIO_LIB
         help
           Base platform code for any Samsung S3C24XX device
 
@@ -20,6 +21,13 @@ config CPU_S3C244X
         help
           Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
 
+config S3C24XX_PWM
+        bool "PWM device support"
+        select HAVE_PWM
+        help
+          Support for exporting the PWM timer blocks via the pwm device
+          system.
+
 config PM_SIMTEC
         bool
         help
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 131d20237dd7..d82767b2b833 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -16,8 +16,10 @@ obj-y				+= cpu.o
 obj-y                           += irq.o
 obj-y                           += devs.o
 obj-y                           += gpio.o
+obj-y                           += gpiolib.o
 obj-y                           += time.o
 obj-y                           += clock.o
+obj-y                           += pwm-clock.o
 
 # Architecture dependant builds
 
@@ -27,5 +29,6 @@ obj-$(CONFIG_CPU_S3C244X)	+= s3c244x-clock.o
 obj-$(CONFIG_PM_SIMTEC)         += pm-simtec.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_PM)                += sleep.o
+obj-$(CONFIG_HAVE_PWM)          += pwm.o
 obj-$(CONFIG_S3C2410_DMA)       += dma.o
 obj-$(CONFIG_MACH_SMDK)         += common-smdk.o
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index e546e933b3f7..eea3b32ff798 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -495,106 +495,6 @@ struct platform_device s3c_device_spi1 = {
 
 EXPORT_SYMBOL(s3c_device_spi1);
 
-/* pwm timer blocks */
-
-static struct resource s3c_timer0_resource[] = {
-        [0] = {
-                .start = S3C24XX_PA_TIMER + 0x0C,
-                .end   = S3C24XX_PA_TIMER + 0x0C + 0xB,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_TIMER0,
-                .end   = IRQ_TIMER0,
-                .flags = IORESOURCE_IRQ,
-        }
-
-};
-
-struct platform_device s3c_device_timer0 = {
-        .name             = "s3c2410-timer",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s3c_timer0_resource),
-        .resource         = s3c_timer0_resource,
-};
-
-EXPORT_SYMBOL(s3c_device_timer0);
-
-/* timer 1 */
-
-static struct resource s3c_timer1_resource[] = {
-        [0] = {
-                .start = S3C24XX_PA_TIMER + 0x18,
-                .end   = S3C24XX_PA_TIMER + 0x23,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_TIMER1,
-                .end   = IRQ_TIMER1,
-                .flags = IORESOURCE_IRQ,
-        }
-
-};
-
-struct platform_device s3c_device_timer1 = {
-        .name             = "s3c2410-timer",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s3c_timer1_resource),
-        .resource         = s3c_timer1_resource,
-};
-
-EXPORT_SYMBOL(s3c_device_timer1);
-
-/* timer 2 */
-
-static struct resource s3c_timer2_resource[] = {
-        [0] = {
-                .start = S3C24XX_PA_TIMER + 0x24,
-                .end   = S3C24XX_PA_TIMER + 0x2F,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_TIMER2,
-                .end   = IRQ_TIMER2,
-                .flags = IORESOURCE_IRQ,
-        }
-
-};
-
-struct platform_device s3c_device_timer2 = {
-        .name             = "s3c2410-timer",
-        .id               = 2,
-        .num_resources    = ARRAY_SIZE(s3c_timer2_resource),
-        .resource         = s3c_timer2_resource,
-};
-
-EXPORT_SYMBOL(s3c_device_timer2);
-
-/* timer 3 */
-
-static struct resource s3c_timer3_resource[] = {
-        [0] = {
-                .start = S3C24XX_PA_TIMER + 0x30,
-                .end   = S3C24XX_PA_TIMER + 0x3B,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_TIMER3,
-                .end   = IRQ_TIMER3,
-                .flags = IORESOURCE_IRQ,
-        }
-
-};
-
-struct platform_device s3c_device_timer3 = {
-        .name             = "s3c2410-timer",
-        .id               = 3,
-        .num_resources    = ARRAY_SIZE(s3c_timer3_resource),
-        .resource         = s3c_timer3_resource,
-};
-
-EXPORT_SYMBOL(s3c_device_timer3);
-
 #ifdef CONFIG_CPU_S3C2440
 
 /* Camif Controller */
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
new file mode 100644
index 000000000000..825d8d0c5ca2
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -0,0 +1,259 @@
+/* linux/arch/arm/plat-s3c24xx/gpiolib.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+
+#include <asm/arch/regs-gpio.h>
+
+struct s3c24xx_gpio_chip {
+        struct gpio_chip        chip;
+        void __iomem            *base;
+};
+
+static inline struct s3c24xx_gpio_chip *to_s3c_chip(struct gpio_chip *gpc)
+{
+        return container_of(gpc, struct s3c24xx_gpio_chip, chip);
+}
+
+/* these routines are exported for use by other parts of the platform
+ * and system support, but are not intended to be used directly by the
+ * drivers themsevles.
+ */
+
+int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long flags;
+        unsigned long con;
+
+        local_irq_save(flags);
+
+        con = __raw_readl(base + 0x00);
+        con &= ~(3 << (offset * 2));
+        con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
+
+        __raw_writel(con, base + 0x00);
+
+        local_irq_restore(flags);
+        return 0;
+}
+
+int s3c24xx_gpiolib_output(struct gpio_chip *chip,
+                                  unsigned offset, int value)
+{
+        struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long flags;
+        unsigned long dat;
+        unsigned long con;
+
+        local_irq_save(flags);
+
+        dat = __raw_readl(base + 0x04);
+        dat &= ~(1 << offset);
+        if (value)
+                dat |= 1 << offset;
+        __raw_writel(dat, base + 0x04);
+
+        con = __raw_readl(base + 0x00);
+        con &= ~(3 << (offset * 2));
+        con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
+
+        __raw_writel(con, base + 0x00);
+        __raw_writel(dat, base + 0x04);
+
+        local_irq_restore(flags);
+        return 0;
+}
+
+void s3c24xx_gpiolib_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long flags;
+        unsigned long dat;
+
+        local_irq_save(flags);
+
+        dat = __raw_readl(base + 0x04);
+        dat &= ~(1 << offset);
+        if (value)
+                dat |= 1 << offset;
+        __raw_writel(dat, base + 0x04);
+
+        local_irq_restore(flags);
+}
+
+int s3c24xx_gpiolib_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
+        unsigned long val;
+
+        val = __raw_readl(ourchip->base + 0x04);
+        val >>= offset;
+        val &= 1;
+
+        return val;
+}
+
+static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
+{
+        return -EINVAL;
+}
+
+static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
+                                        unsigned offset, int value)
+{
+        struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long flags;
+        unsigned long dat;
+        unsigned long con;
+
+        local_irq_save(flags);
+
+        con = __raw_readl(base + 0x00);
+        dat = __raw_readl(base + 0x04);
+
+        dat &= ~(1 << offset);
+        if (value)
+                dat |= 1 << offset;
+
+        __raw_writel(dat, base + 0x04);
+
+        con &= ~(1 << offset);
+
+        __raw_writel(con, base + 0x00);
+        __raw_writel(dat, base + 0x04);
+
+        local_irq_restore(flags);
+        return 0;
+}
+
+
+struct s3c24xx_gpio_chip gpios[] = {
+        [0] = {
+                .base   = S3C24XX_GPIO_BASE(S3C2410_GPA0),
+                .chip   = {
+                        .base                   = S3C2410_GPA0,
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOA",
+                        .ngpio                  = 24,
+                        .direction_input        = s3c24xx_gpiolib_banka_input,
+                        .direction_output       = s3c24xx_gpiolib_banka_output,
+                        .set                    = s3c24xx_gpiolib_set,
+                        .get                    = s3c24xx_gpiolib_get,
+                },
+        },
+        [1] = {
+                .base   = S3C24XX_GPIO_BASE(S3C2410_GPB0),
+                .chip   = {
+                        .base                   = S3C2410_GPB0,
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOB",
+                        .ngpio                  = 16,
+                        .direction_input        = s3c24xx_gpiolib_input,
+                        .direction_output       = s3c24xx_gpiolib_output,
+                        .set                    = s3c24xx_gpiolib_set,
+                        .get                    = s3c24xx_gpiolib_get,
+                },
+        },
+        [2] = {
+                .base   = S3C24XX_GPIO_BASE(S3C2410_GPC0),
+                .chip   = {
+                        .base                   = S3C2410_GPC0,
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOC",
+                        .ngpio                  = 16,
+                        .direction_input        = s3c24xx_gpiolib_input,
+                        .direction_output       = s3c24xx_gpiolib_output,
+                        .set                    = s3c24xx_gpiolib_set,
+                        .get                    = s3c24xx_gpiolib_get,
+                },
+        },
+        [3] = {
+                .base   = S3C24XX_GPIO_BASE(S3C2410_GPD0),
+                .chip   = {
+                        .base                   = S3C2410_GPD0,
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOD",
+                        .ngpio                  = 16,
+                        .direction_input        = s3c24xx_gpiolib_input,
+                        .direction_output       = s3c24xx_gpiolib_output,
+                        .set                    = s3c24xx_gpiolib_set,
+                        .get                    = s3c24xx_gpiolib_get,
+                },
+        },
+        [4] = {
+                .base   = S3C24XX_GPIO_BASE(S3C2410_GPE0),
+                .chip   = {
+                        .base                   = S3C2410_GPE0,
+                        .label                  = "GPIOE",
+                        .owner                  = THIS_MODULE,
+                        .ngpio                  = 16,
+                        .direction_input        = s3c24xx_gpiolib_input,
+                        .direction_output       = s3c24xx_gpiolib_output,
+                        .set                    = s3c24xx_gpiolib_set,
+                        .get                    = s3c24xx_gpiolib_get,
+                },
+        },
+        [5] = {
+                .base   = S3C24XX_GPIO_BASE(S3C2410_GPF0),
+                .chip   = {
+                        .base                   = S3C2410_GPF0,
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOF",
+                        .ngpio                  = 8,
+                        .direction_input        = s3c24xx_gpiolib_input,
+                        .direction_output       = s3c24xx_gpiolib_output,
+                        .set                    = s3c24xx_gpiolib_set,
+                        .get                    = s3c24xx_gpiolib_get,
+                },
+        },
+        [6] = {
+                .base   = S3C24XX_GPIO_BASE(S3C2410_GPG0),
+                .chip   = {
+                        .base                   = S3C2410_GPG0,
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOG",
+                        .ngpio                  = 10,
+                        .direction_input        = s3c24xx_gpiolib_input,
+                        .direction_output       = s3c24xx_gpiolib_output,
+                        .set                    = s3c24xx_gpiolib_set,
+                        .get                    = s3c24xx_gpiolib_get,
+                },
+        },
+};
+
+static __init int s3c24xx_gpiolib_init(void)
+{
+        struct s3c24xx_gpio_chip *chip = gpios;
+        int gpn;
+
+        for (gpn = 0; gpn < ARRAY_SIZE(gpios); gpn++, chip++)
+                gpiochip_add(&chip->chip);
+
+        return 0;
+}
+
+arch_initcall(s3c24xx_gpiolib_init);
diff --git a/arch/arm/plat-s3c24xx/pwm-clock.c b/arch/arm/plat-s3c24xx/pwm-clock.c
new file mode 100644
index 000000000000..2cda3e3c6786
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/pwm-clock.c
@@ -0,0 +1,437 @@
+/* linux/arch/arm/plat-s3c24xx/pwm-clock.c
+ *
+ * Copyright (c) 2007 Simtec Electronics
+ * Copyright (c) 2007, 2008 Ben Dooks
+ *      Ben Dooks <ben-linux@fluff.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+
+#include <asm/arch/regs-clock.h>
+#include <asm/arch/regs-gpio.h>
+
+#include <asm/plat-s3c24xx/clock.h>
+#include <asm/plat-s3c24xx/cpu.h>
+
+#include <asm/plat-s3c/regs-timer.h>
+
+/* Each of the timers 0 through 5 go through the following
+ * clock tree, with the inputs depending on the timers.
+ *
+ * pclk ---- [ prescaler 0 ] -+---> timer 0
+ *                            +---> timer 1
+ *
+ * pclk ---- [ prescaler 1 ] -+---> timer 2
+ *                            +---> timer 3
+ *                            \---> timer 4
+ *
+ * Which are fed into the timers as so:
+ *
+ * prescaled 0 ---- [ div 2,4,8,16 ] ---\
+ *                                     [mux] -> timer 0
+ * tclk 0 ------------------------------/
+ *
+ * prescaled 0 ---- [ div 2,4,8,16 ] ---\
+ *                                     [mux] -> timer 1
+ * tclk 0 ------------------------------/
+ *
+ *
+ * prescaled 1 ---- [ div 2,4,8,16 ] ---\
+ *                                     [mux] -> timer 2
+ * tclk 1 ------------------------------/
+ *
+ * prescaled 1 ---- [ div 2,4,8,16 ] ---\
+ *                                     [mux] -> timer 3
+ * tclk 1 ------------------------------/
+ *
+ * prescaled 1 ---- [ div 2,4,8, 16 ] --\
+ *                                     [mux] -> timer 4
+ * tclk 1 ------------------------------/
+ *
+ * Since the mux and the divider are tied together in the
+ * same register space, it is impossible to set the parent
+ * and the rate at the same time. To avoid this, we add an
+ * intermediate 'prescaled-and-divided' clock to select
+ * as the parent for the timer input clock called tdiv.
+ *
+ * prescaled clk --> pwm-tdiv ---\
+ *                             [ mux ] --> timer X
+ * tclk -------------------------/
+*/
+
+static unsigned long clk_pwm_scaler_getrate(struct clk *clk)
+{
+        unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
+
+        if (clk->id == 1) {
+                tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
+                tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
+        } else {
+                tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
+        }
+
+        return clk_get_rate(clk->parent) / (tcfg0 + 1);
+}
+
+/* TODO - add set rate calls. */
+
+struct clk clk_timer_scaler[] = {
+        [0]     = {
+                .name           = "pwm-scaler0",
+                .id             = -1,
+                .get_rate       = clk_pwm_scaler_getrate,
+        },
+        [1]     = {
+                .name           = "pwm-scaler1",
+                .id             = -1,
+                .get_rate       = clk_pwm_scaler_getrate,
+        },
+};
+
+struct clk clk_timer_tclk[] = {
+        [0]     = {
+                .name           = "pwm-tclk0",
+                .id             = -1,
+        },
+        [1]     = {
+                .name           = "pwm-tclk1",
+                .id             = -1,
+        },
+};
+
+struct pwm_tdiv_clk {
+        struct clk      clk;
+        unsigned int    divisor;
+};
+
+static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
+{
+        return container_of(clk, struct pwm_tdiv_clk, clk);
+}
+
+static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
+{
+        return 1 << (1 + tcfg1);
+}
+
+static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
+{
+        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+        unsigned int divisor;
+
+        tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
+        tcfg1 &= S3C2410_TCFG1_MUX_MASK;
+
+        if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
+                divisor = to_tdiv(clk)->divisor;
+        else
+                divisor = tcfg_to_divisor(tcfg1);
+
+        return clk_get_rate(clk->parent) / divisor;
+}
+
+static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
+                                             unsigned long rate)
+{
+        unsigned long parent_rate;
+        unsigned long divisor;
+
+        parent_rate = clk_get_rate(clk->parent);
+        divisor = parent_rate / rate;
+
+        if (divisor <= 2)
+                divisor = 2;
+        else if (divisor <= 4)
+                divisor = 4;
+        else if (divisor <= 8)
+                divisor = 8;
+        else
+                divisor = 16;
+
+        return parent_rate / divisor;
+}
+
+static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
+{
+        unsigned long bits;
+
+        switch (divclk->divisor) {
+        case 2:
+                bits = S3C2410_TCFG1_MUX_DIV2;
+                break;
+        case 4:
+                bits = S3C2410_TCFG1_MUX_DIV4;
+                break;
+        case 8:
+                bits = S3C2410_TCFG1_MUX_DIV8;
+                break;
+        case 16:
+        default:
+                bits = S3C2410_TCFG1_MUX_DIV16;
+                break;
+        }
+
+        return bits;
+}
+
+static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
+{
+        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+        unsigned long bits = clk_pwm_tdiv_bits(divclk);
+        unsigned long flags;
+        unsigned long shift =  S3C2410_TCFG1_SHIFT(divclk->clk.id);
+
+        local_irq_save(flags);
+
+        tcfg1 = __raw_readl(S3C2410_TCFG1);
+        tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
+        tcfg1 |= bits << shift;
+        __raw_writel(tcfg1, S3C2410_TCFG1);
+
+        local_irq_restore(flags);
+}
+
+static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
+{
+        struct pwm_tdiv_clk *divclk = to_tdiv(clk);
+        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long divisor;
+
+        tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
+        tcfg1 &= S3C2410_TCFG1_MUX_MASK;
+
+        rate = clk_round_rate(clk, rate);
+        divisor = parent_rate / rate;
+
+        if (divisor > 16)
+                return -EINVAL;
+
+        divclk->divisor = divisor;
+
+        /* Update the current MUX settings if we are currently
+         * selected as the clock source for this clock. */
+
+        if (tcfg1 != S3C2410_TCFG1_MUX_TCLK)
+                clk_pwm_tdiv_update(divclk);
+
+        return 0;
+}
+
+struct pwm_tdiv_clk clk_timer_tdiv[] = {
+        [0]     = {
+                .clk    = {
+                        .name           = "pwm-tdiv",
+                        .parent         = &clk_timer_scaler[0],
+                        .get_rate       = clk_pwm_tdiv_get_rate,
+                        .set_rate       = clk_pwm_tdiv_set_rate,
+                        .round_rate     = clk_pwm_tdiv_round_rate,
+                },
+        },
+        [1]     = {
+                .clk    = {
+                        .name           = "pwm-tdiv",
+                        .parent         = &clk_timer_scaler[0],
+                        .get_rate       = clk_pwm_tdiv_get_rate,
+                        .set_rate       = clk_pwm_tdiv_set_rate,
+                        .round_rate     = clk_pwm_tdiv_round_rate,
+                }
+        },
+        [2]     = {
+                .clk    = {
+                        .name           = "pwm-tdiv",
+                        .parent         = &clk_timer_scaler[1],
+                        .get_rate       = clk_pwm_tdiv_get_rate,
+                        .set_rate       = clk_pwm_tdiv_set_rate,
+                        .round_rate     = clk_pwm_tdiv_round_rate,
+                },
+        },
+        [3]     = {
+                .clk    = {
+                        .name           = "pwm-tdiv",
+                        .parent         = &clk_timer_scaler[1],
+                        .get_rate       = clk_pwm_tdiv_get_rate,
+                        .set_rate       = clk_pwm_tdiv_set_rate,
+                        .round_rate     = clk_pwm_tdiv_round_rate,
+                },
+        },
+        [4]     = {
+                .clk    = {
+                        .name           = "pwm-tdiv",
+                        .parent         = &clk_timer_scaler[1],
+                        .get_rate       = clk_pwm_tdiv_get_rate,
+                        .set_rate       = clk_pwm_tdiv_set_rate,
+                        .round_rate     = clk_pwm_tdiv_round_rate,
+                },
+        },
+};
+
+static int __init clk_pwm_tdiv_register(unsigned int id)
+{
+        struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
+        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+
+        tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
+        tcfg1 &= S3C2410_TCFG1_MUX_MASK;
+
+        divclk->clk.id = id;
+        divclk->divisor = tcfg_to_divisor(tcfg1);
+
+        return s3c24xx_register_clock(&divclk->clk);
+}
+
+static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
+{
+        return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
+}
+
+static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
+{
+        return &clk_timer_tdiv[id].clk;
+}
+
+static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
+{
+        unsigned int id = clk->id;
+        unsigned long tcfg1;
+        unsigned long flags;
+        unsigned long bits;
+        unsigned long shift = S3C2410_TCFG1_SHIFT(id);
+
+        if (parent == s3c24xx_pwmclk_tclk(id))
+                bits = S3C2410_TCFG1_MUX_TCLK << shift;
+        else if (parent == s3c24xx_pwmclk_tdiv(id))
+                bits = clk_pwm_tdiv_bits(to_tdiv(clk)) << shift;
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        local_irq_save(flags);
+
+        tcfg1 = __raw_readl(S3C2410_TCFG1);
+        tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
+        __raw_writel(tcfg1 | bits, S3C2410_TCFG1);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static struct clk clk_tin[] = {
+        [0]     = {
+                .name           = "pwm-tin",
+                .id             = 0,
+                .set_parent     = clk_pwm_tin_set_parent,
+        },
+        [1]     = {
+                .name           = "pwm-tin",
+                .id             = 1,
+                .set_parent     = clk_pwm_tin_set_parent,
+        },
+        [2]     = {
+                .name           = "pwm-tin",
+                .id             = 2,
+                .set_parent     = clk_pwm_tin_set_parent,
+        },
+        [3]     = {
+                .name           = "pwm-tin",
+                .id             = 3,
+                .set_parent     = clk_pwm_tin_set_parent,
+        },
+        [4]     = {
+                .name           = "pwm-tin",
+                .id             = 4,
+                .set_parent     = clk_pwm_tin_set_parent,
+        },
+};
+
+static __init int clk_pwm_tin_register(struct clk *pwm)
+{
+        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+        unsigned int id = pwm->id;
+
+        struct clk *parent;
+        int ret;
+
+        ret = s3c24xx_register_clock(pwm);
+        if (ret < 0)
+                return ret;
+
+        tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
+        tcfg1 &= S3C2410_TCFG1_MUX_MASK;
+
+        if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
+                parent = s3c24xx_pwmclk_tclk(id);
+        else
+                parent = s3c24xx_pwmclk_tdiv(id);
+
+        return clk_set_parent(pwm, parent);
+}
+
+static __init int s3c24xx_pwmclk_init(void)
+{
+        struct clk *clk_timers;
+        unsigned int clk;
+        int ret;
+
+        clk_timers = clk_get(NULL, "timers");
+        if (IS_ERR(clk_timers)) {
+                printk(KERN_ERR "%s: no parent clock\n", __func__);
+                return -EINVAL;
+        }
+
+        for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) {
+                clk_timer_scaler[clk].parent = clk_timers;
+                ret = s3c24xx_register_clock(&clk_timer_scaler[clk]);
+                if (ret < 0) {
+                        printk(KERN_ERR "error adding pwm scaler%d clock\n", clk);
+                        goto err;
+                }
+        }
+
+        for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) {
+                ret = s3c24xx_register_clock(&clk_timer_tclk[clk]);
+                if (ret < 0) {
+                        printk(KERN_ERR "error adding pww tclk%d\n", clk);
+                        goto err;
+                }
+        }
+
+        for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
+                ret = clk_pwm_tdiv_register(clk);
+                if (ret < 0) {
+                        printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
+                        goto err;
+                }
+        }
+
+        for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
+                ret = clk_pwm_tin_register(&clk_tin[clk]);
+                if (ret < 0) {
+                        printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
+                        goto err;
+                }
+        }
+
+        return 0;
+
+ err:
+        return ret;
+}
+
+arch_initcall(s3c24xx_pwmclk_init);
diff --git a/arch/arm/plat-s3c24xx/pwm.c b/arch/arm/plat-s3c24xx/pwm.c
new file mode 100644
index 000000000000..18c4bdc49a05
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/pwm.c
@@ -0,0 +1,402 @@
+/* arch/arm/plat-s3c24xx/pwm.c
+ *
+ * Copyright (c) 2007 Ben Dooks
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
+ *
+ * S3C24XX PWM device core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/pwm.h>
+
+#include <asm/plat-s3c/regs-timer.h>
+
+struct pwm_device {
+        struct list_head         list;
+        struct platform_device  *pdev;
+
+        struct clk              *clk_div;
+        struct clk              *clk;
+        const char              *label;
+
+        unsigned int             period_ns;
+        unsigned int             duty_ns;
+
+        unsigned char            tcon_base;
+        unsigned char            running;
+        unsigned char            use_count;
+        unsigned char            pwm_id;
+};
+
+#define pwm_dbg(_pwm, msg...) dev_info(&(_pwm)->pdev->dev, msg)
+
+static struct clk *clk_scaler[2];
+
+/* Standard setup for a timer block. */
+
+#define TIMER_RESOURCE_SIZE (1)
+
+#define TIMER_RESOURCE(_tmr, _irq)                      \
+        (struct resource [TIMER_RESOURCE_SIZE]) {       \
+                [0] = {                                 \
+                        .start  = _irq,                 \
+                        .end    = _irq,                 \
+                        .flags  = IORESOURCE_IRQ        \
+                }                                       \
+        }
+
+#define DEFINE_TIMER(_tmr_no, _irq)                     \
+        .name           = "s3c24xx-pwm",                \
+        .id             = _tmr_no,                      \
+        .num_resources  = TIMER_RESOURCE_SIZE,          \
+        .resource       = TIMER_RESOURCE(_tmr_no, _irq),        \
+
+/* since we already have an static mapping for the timer, we do not
+ * bother setting any IO resource for the base.
+ */
+
+struct platform_device s3c_device_timer[] = {
+        [0] = { DEFINE_TIMER(0, IRQ_TIMER0) },
+        [1] = { DEFINE_TIMER(1, IRQ_TIMER1) },
+        [2] = { DEFINE_TIMER(2, IRQ_TIMER2) },
+        [3] = { DEFINE_TIMER(3, IRQ_TIMER3) },
+        [4] = { DEFINE_TIMER(4, IRQ_TIMER4) },
+};
+
+static inline int pwm_is_tdiv(struct pwm_device *pwm)
+{
+        return clk_get_parent(pwm->clk) == pwm->clk_div;
+}
+
+static DEFINE_MUTEX(pwm_lock);
+static LIST_HEAD(pwm_list);
+
+struct pwm_device *pwm_request(int pwm_id, const char *label)
+{
+        struct pwm_device *pwm;
+        int found = 0;
+
+        mutex_lock(&pwm_lock);
+
+        list_for_each_entry(pwm, &pwm_list, list) {
+                if (pwm->pwm_id == pwm_id) {
+                        found = 1;
+                        break;
+                }
+        }
+
+        if (found) {
+                if (pwm->use_count == 0) {
+                        pwm->use_count = 1;
+                        pwm->label = label;
+                } else
+                        pwm = ERR_PTR(-EBUSY);
+        } else
+                pwm = ERR_PTR(-ENOENT);
+
+        mutex_unlock(&pwm_lock);
+        return pwm;
+}
+
+EXPORT_SYMBOL(pwm_request);
+
+
+void pwm_free(struct pwm_device *pwm)
+{
+        mutex_lock(&pwm_lock);
+
+        if (pwm->use_count) {
+                pwm->use_count--;
+                pwm->label = NULL;
+        } else
+                printk(KERN_ERR "PWM%d device already freed\n", pwm->pwm_id);
+
+        mutex_unlock(&pwm_lock);
+}
+
+EXPORT_SYMBOL(pwm_free);
+
+#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0))
+#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2))
+#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3))
+#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1))
+
+int pwm_enable(struct pwm_device *pwm)
+{
+        unsigned long flags;
+        unsigned long tcon;
+
+        local_irq_save(flags);
+
+        tcon = __raw_readl(S3C2410_TCON);
+        tcon |= pwm_tcon_start(pwm);
+        __raw_writel(tcon, S3C2410_TCON);
+
+        local_irq_restore(flags);
+
+        pwm->running = 1;
+        return 0;
+}
+
+EXPORT_SYMBOL(pwm_enable);
+
+void pwm_disable(struct pwm_device *pwm)
+{
+        unsigned long flags;
+        unsigned long tcon;
+
+        local_irq_save(flags);
+
+        tcon = __raw_readl(S3C2410_TCON);
+        tcon &= ~pwm_tcon_start(pwm);
+        __raw_writel(tcon, S3C2410_TCON);
+
+        local_irq_restore(flags);
+
+        pwm->running = 0;
+}
+
+EXPORT_SYMBOL(pwm_disable);
+
+unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq)
+{
+        unsigned long tin_parent_rate;
+        unsigned int div;
+
+        tin_parent_rate = clk_get_rate(clk_get_parent(pwm->clk_div));
+        pwm_dbg(pwm, "tin parent at %lu\n", tin_parent_rate);
+
+        for (div = 2; div <= 16; div *= 2) {
+                if ((tin_parent_rate / (div << 16)) < freq)
+                        return tin_parent_rate / div;
+        }
+
+        return tin_parent_rate / 16;
+}
+
+#define NS_IN_HZ (1000000000UL)
+
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+        unsigned long tin_rate;
+        unsigned long tin_ns;
+        unsigned long period;
+        unsigned long flags;
+        unsigned long tcon;
+        unsigned long tcnt;
+        long tcmp;
+
+        /* We currently avoid using 64bit arithmetic by using the
+         * fact that anything faster than 1Hz is easily representable
+         * by 32bits. */
+
+        if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
+                return -ERANGE;
+
+        if (duty_ns > period_ns)
+                return -EINVAL;
+
+        if (period_ns == pwm->period_ns &&
+            duty_ns == pwm->duty_ns)
+                return 0;
+
+        /* The TCMP and TCNT can be read without a lock, they're not
+         * shared between the timers. */
+
+        tcmp = __raw_readl(S3C2410_TCMPB(pwm->pwm_id));
+        tcnt = __raw_readl(S3C2410_TCNTB(pwm->pwm_id));
+
+        period = NS_IN_HZ / period_ns;
+
+        pwm_dbg(pwm, "duty_ns=%d, period_ns=%d (%lu)\n",
+                duty_ns, period_ns, period);
+
+        /* Check to see if we are changing the clock rate of the PWM */
+
+        if (pwm->period_ns != period_ns) {
+                if (pwm_is_tdiv(pwm)) {
+                        tin_rate = pwm_calc_tin(pwm, period);
+                        clk_set_rate(pwm->clk_div, tin_rate);
+                } else
+                        tin_rate = clk_get_rate(pwm->clk);
+
+                pwm->period_ns = period_ns;
+
+                pwm_dbg(pwm, "tin_rate=%lu\n", tin_rate);
+
+                tin_ns = NS_IN_HZ / tin_rate;
+                tcnt = period_ns / tin_ns;
+        } else
+                tin_ns = NS_IN_HZ / clk_get_rate(pwm->clk);
+
+        /* Note, counters count down */
+
+        tcmp = duty_ns / tin_ns;
+        tcmp = tcnt - tcmp;
+
+        pwm_dbg(pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);
+
+        if (tcmp < 0)
+                tcmp = 0;
+
+        /* Update the PWM register block. */
+
+        local_irq_save(flags);
+
+        __raw_writel(tcmp, S3C2410_TCMPB(pwm->pwm_id));
+        __raw_writel(tcnt, S3C2410_TCNTB(pwm->pwm_id));
+
+        tcon = __raw_readl(S3C2410_TCON);
+        tcon |= pwm_tcon_manulupdate(pwm);
+        tcon |= pwm_tcon_autoreload(pwm);
+        __raw_writel(tcon, S3C2410_TCON);
+
+        tcon &= ~pwm_tcon_manulupdate(pwm);
+        __raw_writel(tcon, S3C2410_TCON);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+EXPORT_SYMBOL(pwm_config);
+
+static int pwm_register(struct pwm_device *pwm)
+{
+        pwm->duty_ns = -1;
+        pwm->period_ns = -1;
+
+        mutex_lock(&pwm_lock);
+        list_add_tail(&pwm->list, &pwm_list);
+        mutex_unlock(&pwm_lock);
+
+        return 0;
+}
+
+static int s3c_pwm_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct pwm_device *pwm;
+        unsigned long flags;
+        unsigned long tcon;
+        unsigned int id = pdev->id;
+        int ret;
+
+        if (id == 4) {
+                dev_err(dev, "TIMER4 is currently not supported\n");
+                return -ENXIO;
+        }
+
+        pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
+        if (pwm == NULL) {
+                dev_err(dev, "failed to allocate pwm_device\n");
+                return -ENOMEM;
+        }
+
+        pwm->pdev = pdev;
+        pwm->pwm_id = id;
+
+        /* calculate base of control bits in TCON */
+        pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4;
+
+        pwm->clk = clk_get(dev, "pwm-tin");
+        if (IS_ERR(pwm->clk)) {
+                dev_err(dev, "failed to get pwm tin clk\n");
+                ret = PTR_ERR(pwm->clk);
+                goto err_alloc;
+        }
+
+        pwm->clk_div = clk_get(dev, "pwm-tdiv");
+        if (IS_ERR(pwm->clk_div)) {
+                dev_err(dev, "failed to get pwm tdiv clk\n");
+                ret = PTR_ERR(pwm->clk_div);
+                goto err_clk_tin;
+        }
+
+        local_irq_save(flags);
+
+        tcon = __raw_readl(S3C2410_TCON);
+        tcon |= pwm_tcon_invert(pwm);
+        __raw_writel(tcon, S3C2410_TCON);
+
+        local_irq_restore(flags);
+
+
+        ret = pwm_register(pwm);
+        if (ret) {
+                dev_err(dev, "failed to register pwm\n");
+                goto err_clk_tdiv;
+        }
+
+        pwm_dbg(pwm, "config bits %02x\n",
+                (__raw_readl(S3C2410_TCON) >> pwm->tcon_base) & 0x0f);
+
+        dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n",
+                 clk_get_rate(pwm->clk),
+                 clk_get_rate(pwm->clk_div),
+                 pwm_is_tdiv(pwm) ? "div" : "ext", pwm->tcon_base);
+
+        platform_set_drvdata(pdev, pwm);
+        return 0;
+
+ err_clk_tdiv:
+        clk_put(pwm->clk_div);
+
+ err_clk_tin:
+        clk_put(pwm->clk);
+
+ err_alloc:
+        kfree(pwm);
+        return ret;
+}
+
+static int s3c_pwm_remove(struct platform_device *pdev)
+{
+        struct pwm_device *pwm = platform_get_drvdata(pdev);
+
+        clk_put(pwm->clk_div);
+        clk_put(pwm->clk);
+        kfree(pwm);
+
+        return 0;
+}
+
+static struct platform_driver s3c_pwm_driver = {
+        .driver         = {
+                .name   = "s3c24xx-pwm",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = s3c_pwm_probe,
+        .remove         = __devexit_p(s3c_pwm_remove),
+};
+
+static int __init pwm_init(void)
+{
+        int ret;
+
+        clk_scaler[0] = clk_get(NULL, "pwm-scaler0");
+        clk_scaler[1] = clk_get(NULL, "pwm-scaler1");
+
+        if (IS_ERR(clk_scaler[0]) || IS_ERR(clk_scaler[1])) {
+                printk(KERN_ERR "%s: failed to get scaler clocks\n", __func__);
+                return -EINVAL;
+        }
+
+        ret = platform_driver_register(&s3c_pwm_driver);
+        if (ret)
+                printk(KERN_ERR "%s: failed to add pwm driver\n", __func__);
+
+        return ret;
+}
+
+arch_initcall(pwm_init);
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 207a8b5a0c4a..0be5630ff568 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Sat Apr 19 11:23:38 2008
+# Last update: Mon Jul 7 16:25:39 2008
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -560,7 +560,6 @@ husky			MACH_HUSKY		HUSKY			543
 boxer                   MACH_BOXER              BOXER                   544
 shepherd                MACH_SHEPHERD           SHEPHERD                545
 aml42800aa              MACH_AML42800AA         AML42800AA              546
-ml674001                MACH_MACH_TYPE_ML674001 MACH_TYPE_ML674001      547
 lpc2294                 MACH_LPC2294            LPC2294                 548
 switchgrass             MACH_SWITCHGRASS        SWITCHGRASS             549
 ens_cmu                 MACH_ENS_CMU            ENS_CMU                 550
@@ -748,7 +747,6 @@ anubis			MACH_ANUBIS		ANUBIS			734
 ite8152                 MACH_ITE8152            ITE8152                 735
 lpc3xxx                 MACH_LPC3XXX            LPC3XXX                 736
 puppeteer               MACH_PUPPETEER          PUPPETEER               737
-vt001                   MACH_MACH_VADATECH      MACH_VADATECH           738
 e570                    MACH_E570               E570                    739
 x50                     MACH_X50                X50                     740
 recon                   MACH_RECON              RECON                   741
@@ -839,7 +837,7 @@ ccxp270			MACH_CCXP		CCXP			825
 omap_gsample            MACH_OMAP_GSAMPLE       OMAP_GSAMPLE            826
 realview_eb             MACH_REALVIEW_EB        REALVIEW_EB             827
 samoa                   MACH_SAMOA              SAMOA                   828
-t3xscale                MACH_T3XSCALE           T3XSCALE                829
+palmt3                  MACH_PALMT3             PALMT3                  829
 i878                    MACH_I878               I878                    830
 borzoi                  MACH_BORZOI             BORZOI                  831
 gecko                   MACH_GECKO              GECKO                   832
@@ -895,7 +893,7 @@ mio8390			MACH_MIO8390		MIO8390			881
 omi_board               MACH_OMI_BOARD          OMI_BOARD               882
 mx21civ                 MACH_MX21CIV            MX21CIV                 883
 mahi_cdac               MACH_MAHI_CDAC          MAHI_CDAC               884
-xscale_palmtx           MACH_XSCALE_PALMTX      XSCALE_PALMTX           885
+palmtx                  MACH_PALMTX             PALMTX                  885
 s3c2413                 MACH_S3C2413            S3C2413                 887
 samsys_ep0              MACH_SAMSYS_EP0         SAMSYS_EP0              888
 wg302v1                 MACH_WG302V1            WG302V1                 889
@@ -918,7 +916,7 @@ nxdb500			MACH_NXDB500		NXDB500			905
 apf9328                 MACH_APF9328            APF9328                 906
 omap_wipoq              MACH_OMAP_WIPOQ         OMAP_WIPOQ              907
 omap_twip               MACH_OMAP_TWIP          OMAP_TWIP               908
-xscale_treo650          MACH_XSCALE_PALMTREO650 XSCALE_PALMTREO650      909
+palmtreo650             MACH_PALMTREO650        PALMTREO650             909
 acumen                  MACH_ACUMEN             ACUMEN                  910
 xp100                   MACH_XP100              XP100                   911
 fs2410                  MACH_FS2410             FS2410                  912
@@ -926,8 +924,8 @@ pxa270_cerf		MACH_PXA270_CERF	PXA270_CERF		913
 sq2ftlpalm              MACH_SQ2FTLPALM         SQ2FTLPALM              914
 bsemserver              MACH_BSEMSERVER         BSEMSERVER              915
 netclient               MACH_NETCLIENT          NETCLIENT               916
-xscale_palmtt5          MACH_XSCALE_PALMTT5     XSCALE_PALMTT5          917
-xscale_palmtc           MACH_OMAP_PALMTC        OMAP_PALMTC             918
+palmt5                  MACH_PALMT5             PALMT5                  917
+palmtc                  MACH_PALMTC             PALMTC                  918
 omap_apollon            MACH_OMAP_APOLLON       OMAP_APOLLON            919
 mxc30030evb             MACH_MXC30030EVB        MXC30030EVB             920
 rea_2d                  MACH_REA_2D             REA_2D                  921
@@ -1220,7 +1218,6 @@ empca400		MACH_EMPCA400		EMPCA400		1211
 em7210                  MACH_EM7210             EM7210                  1212
 htchermes               MACH_HTCHERMES          HTCHERMES               1213
 eti_c1                  MACH_ETI_C1             ETI_C1                  1214
-mach_dep2410            MACH_MACH_DEP2410       MACH_DEP2410            1215
 ac100                   MACH_AC100              AC100                   1216
 sneetch                 MACH_SNEETCH            SNEETCH                 1217
 studentmate             MACH_STUDENTMATE        STUDENTMATE             1218
@@ -1421,10 +1418,10 @@ looxc550		MACH_LOOXC550		LOOXC550		1417
 cnty_titan              MACH_CNTY_TITAN         CNTY_TITAN              1418
 app3xx                  MACH_APP3XX             APP3XX                  1419
 sideoatsgrama           MACH_SIDEOATSGRAMA      SIDEOATSGRAMA           1420
-xscale_palmt700p        MACH_XSCALE_PALMT700P   XSCALE_PALMT700P        1421
-xscale_palmt700w        MACH_XSCALE_PALMT700W   XSCALE_PALMT700W        1422
-xscale_palmt750         MACH_XSCALE_PALMT750    XSCALE_PALMT750         1423
-xscale_palmt755p        MACH_XSCALE_PALMT755P   XSCALE_PALMT755P        1424
+palmtreo700p            MACH_PALMTREO700P       PALMTREO700P            1421
+palmtreo700w            MACH_PALMTREO700W       PALMTREO700W            1422
+palmtreo750             MACH_PALMTREO750        PALMTREO750             1423
+palmtreo755p            MACH_PALMTREO755P       PALMTREO755P            1424
 ezreganut9200           MACH_EZREGANUT9200      EZREGANUT9200           1425
 sarge                   MACH_SARGE              SARGE                   1426
 a696                    MACH_A696               A696                    1427
@@ -1463,7 +1460,7 @@ artemis			MACH_ARTEMIS		ARTEMIS			1462
 htctitan                MACH_HTCTITAN           HTCTITAN                1463
 qranium                 MACH_QRANIUM            QRANIUM                 1464
 adx_wsc2                MACH_ADX_WSC2           ADX_WSC2                1465
-adx_medcom              MACH_ADX_MEDINET        ADX_MEDINET             1466
+adx_medcom              MACH_ADX_MEDCOM         ADX_MEDCOM              1466
 bboard                  MACH_BBOARD             BBOARD                  1467
 cambria                 MACH_CAMBRIA            CAMBRIA                 1468
 mt7xxx                  MACH_MT7XXX             MT7XXX                  1469
@@ -1519,7 +1516,7 @@ wp188			MACH_WP188		WP188			1518
 corsica                 MACH_CORSICA            CORSICA                 1519
 bigeye                  MACH_BIGEYE             BIGEYE                  1520
 tll5000                 MACH_TLL5000            TLL5000                 1522
-hni270                  MACH_HNI_X270           HNI_X270                1523
+bebot                   MACH_BEBOT              BEBOT                   1523
 qong                    MACH_QONG               QONG                    1524
 tcompact                MACH_TCOMPACT           TCOMPACT                1525
 puma5                   MACH_PUMA5              PUMA5                   1526
@@ -1636,7 +1633,6 @@ awlug4lcu		MACH_AWLUG4LCU		AWLUG4LCU		1637
 palermoc                MACH_PALERMOC           PALERMOC                1638
 omap_ldp                MACH_OMAP_LDP           OMAP_LDP                1639
 ip500                   MACH_IP500              IP500                   1640
-mx35ads                 MACH_MACH_MX35ADS       MACH_MX35ADS            1641
 ase2                    MACH_ASE2               ASE2                    1642
 mx35evb                 MACH_MX35EVB            MX35EVB                 1643
 aml_m8050               MACH_AML_M8050          AML_M8050               1644
@@ -1647,7 +1643,7 @@ badger			MACH_BADGER		BADGER			1648
 trizeps4wl              MACH_TRIZEPS4WL         TRIZEPS4WL              1649
 trizeps5                MACH_TRIZEPS5           TRIZEPS5                1650
 marlin                  MACH_MARLIN             MARLIN                  1651
-ts7800                  MACH_TS7800             TS7800                  1652
+ts78xx                  MACH_TS78XX             TS78XX                  1652
 hpipaq214               MACH_HPIPAQ214          HPIPAQ214               1653
 at572d940dcm            MACH_AT572D940DCM       AT572D940DCM            1654
 ne1board                MACH_NE1BOARD           NE1BOARD                1655
@@ -1720,3 +1716,99 @@ htc_kaiser		MACH_HTC_KAISER		HTC_KAISER		1724
 lg_ks20                 MACH_LG_KS20            LG_KS20                 1725
 hhgps                   MACH_HHGPS              HHGPS                   1726
 nokia_n810_wimax        MACH_NOKIA_N810_WIMAX   NOKIA_N810_WIMAX        1727
+insight                 MACH_INSIGHT            INSIGHT                 1728
+sapphire                MACH_SAPPHIRE           SAPPHIRE                1729
+csb637xo                MACH_CSB637XO           CSB637XO                1730
+evisiong                MACH_EVISIONG           EVISIONG                1731
+stmp37xx                MACH_STMP37XX           STMP37XX                1732
+stmp378x                MACH_STMP38XX           STMP38XX                1733
+tnt                     MACH_TNT                TNT                     1734
+tbxt                    MACH_TBXT               TBXT                    1735
+playmate                MACH_PLAYMATE           PLAYMATE                1736
+pns10                   MACH_PNS10              PNS10                   1737
+eznavi                  MACH_EZNAVI             EZNAVI                  1738
+ps4000                  MACH_PS4000             PS4000                  1739
+ezx_a780                MACH_EZX_A780           EZX_A780                1740
+ezx_e680                MACH_EZX_E680           EZX_E680                1741
+ezx_a1200               MACH_EZX_A1200          EZX_A1200               1742
+ezx_e6                  MACH_EZX_E6             EZX_E6                  1743
+ezx_e2                  MACH_EZX_E2             EZX_E2                  1744
+ezx_a910                MACH_EZX_A910           EZX_A910                1745
+cwmx31                  MACH_CWMX31             CWMX31                  1746
+sl2312                  MACH_SL2312             SL2312                  1747
+blenny                  MACH_BLENNY             BLENNY                  1748
+ds107                   MACH_DS107              DS107                   1749
+dsx07                   MACH_DSX07              DSX07                   1750
+picocom1                MACH_PICOCOM1           PICOCOM1                1751
+lynx_wolverine          MACH_LYNX_WOLVERINE     LYNX_WOLVERINE          1752
+ubisys_p9_sc19          MACH_UBISYS_P9_SC19     UBISYS_P9_SC19          1753
+kratos_low              MACH_KRATOS_LOW         KRATOS_LOW              1754
+m700                    MACH_M700               M700                    1755
+edmini_v2               MACH_EDMINI_V2          EDMINI_V2               1756
+zipit2                  MACH_ZIPIT2             ZIPIT2                  1757
+hslfemtocell            MACH_HSLFEMTOCELL       HSLFEMTOCELL            1758
+daintree_at91           MACH_DAINTREE_AT91      DAINTREE_AT91           1759
+sg560usb                MACH_SG560USB           SG560USB                1760
+omap3_pandora           MACH_OMAP3_PANDORA      OMAP3_PANDORA           1761
+usr8200                 MACH_USR8200            USR8200                 1762
+s1s65k                  MACH_S1S65K             S1S65K                  1763
+s2s65a                  MACH_S2S65A             S2S65A                  1764
+icore                   MACH_ICORE              ICORE                   1765
+mss2                    MACH_MSS2               MSS2                    1766
+belmont                 MACH_BELMONT            BELMONT                 1767
+asusp525                MACH_ASUSP525           ASUSP525                1768
+lb88rc8480              MACH_LB88RC8480         LB88RC8480              1769
+hipxa                   MACH_HIPXA              HIPXA                   1770
+mx25_3ds                MACH_MX25_3DS           MX25_3DS                1771
+m800                    MACH_M800               M800                    1772
+omap3530_lv_som         MACH_OMAP3530_LV_SOM    OMAP3530_LV_SOM         1773
+prima_evb               MACH_PRIMA_EVB          PRIMA_EVB               1774
+mx31bt1                 MACH_MX31BT1            MX31BT1                 1775
+atlas4_evb              MACH_ATLAS4_EVB         ATLAS4_EVB              1776
+mx31cicada              MACH_MX31CICADA         MX31CICADA              1777
+mi424wr                 MACH_MI424WR            MI424WR                 1778
+axs_ultrax              MACH_AXS_ULTRAX         AXS_ULTRAX              1779
+at572d940deb            MACH_AT572D940DEB       AT572D940DEB            1780
+davinci_da8xx_evm       MACH_DAVINCI_DA8XX_EVM  DAVINCI_DA8XX_EVM       1781
+ep9302                  MACH_EP9302             EP9302                  1782
+at572d940hfeb           MACH_AT572D940HFEB      AT572D940HFEB           1783
+cybook3                 MACH_CYBOOK3            CYBOOK3                 1784
+wdg002                  MACH_WDG002             WDG002                  1785
+sg560adsl               MACH_SG560ADSL          SG560ADSL               1786
+nextio_n2800_ica        MACH_NEXTIO_N2800_ICA   NEXTIO_N2800_ICA        1787
+marvell_newdb           MACH_MARVELL_NEWDB      MARVELL_NEWDB           1789
+vandihud                MACH_VANDIHUD           VANDIHUD                1790
+magx_e8                 MACH_MAGX_E8            MAGX_E8                 1791
+magx_z6                 MACH_MAGX_Z6            MAGX_Z6                 1792
+magx_v8                 MACH_MAGX_V8            MAGX_V8                 1793
+magx_u9                 MACH_MAGX_U9            MAGX_U9                 1794
+toughcf08               MACH_TOUGHCF08          TOUGHCF08               1795
+zw4400                  MACH_ZW4400             ZW4400                  1796
+marat91                 MACH_MARAT91            MARAT91                 1797
+overo                   MACH_OVERO              OVERO                   1798
+at2440evb               MACH_AT2440EVB          AT2440EVB               1799
+neocore926              MACH_NEOCORE926         NEOCORE926              1800
+wnr854t                 MACH_WNR854T            WNR854T                 1801
+imx27                   MACH_IMX27              IMX27                   1802
+moose_db                MACH_MOOSE_DB           MOOSE_DB                1803
+fab4                    MACH_FAB4               FAB4                    1804
+htcdiamond              MACH_HTCDIAMOND         HTCDIAMOND              1805
+fiona                   MACH_FIONA              FIONA                   1806
+mxc30030_x              MACH_MXC30030_X         MXC30030_X              1807
+bmp1000                 MACH_BMP1000            BMP1000                 1808
+logi9200                MACH_LOGI9200           LOGI9200                1809
+tqma31                  MACH_TQMA31             TQMA31                  1810
+ccw9p9215js             MACH_CCW9P9215JS        CCW9P9215JS             1811
+rd88f5181l_ge           MACH_RD88F5181L_GE      RD88F5181L_GE           1812
+sifmain                 MACH_SIFMAIN            SIFMAIN                 1813
+sam9_l9261              MACH_SAM9_L9261         SAM9_L9261              1814
+cc9m2443js              MACH_CC9M2443JS         CC9M2443JS              1815
+xaria300                MACH_XARIA300           XARIA300                1816
+it9200                  MACH_IT9200             IT9200                  1817
+rd88f5181l_fxo          MACH_RD88F5181L_FXO     RD88F5181L_FXO          1818
+kriss_sensor            MACH_KRISS_SENSOR       KRISS_SENSOR            1819
+pilz_pmi5               MACH_PILZ_PMI5          PILZ_PMI5               1820
+jade                    MACH_JADE               JADE                    1821
+ks8695_softplc          MACH_KS8695_SOFTPLC     KS8695_SOFTPLC          1822
+gprisc4                 MACH_GPRISC4            GPRISC4                 1823
+stamp9260               MACH_STAMP9260          STAMP9260               1824
diff --git a/arch/sh/configs/landisk_defconfig b/arch/sh/configs/landisk_defconfig
index f52db125432f..38f934ab50c7 100644
--- a/arch/sh/configs/landisk_defconfig
+++ b/arch/sh/configs/landisk_defconfig
@@ -226,7 +226,6 @@ CONFIG_CPU_HAS_PTEA=y
 #
 CONFIG_SH_TMU=y
 CONFIG_SH_TIMER_IRQ=16
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_SH_PCLK_FREQ=33333333
 
 #
diff --git a/arch/sh/configs/lboxre2_defconfig b/arch/sh/configs/lboxre2_defconfig
index 9fa66d92a4e7..b68b6cdbb78f 100644
--- a/arch/sh/configs/lboxre2_defconfig
+++ b/arch/sh/configs/lboxre2_defconfig
@@ -231,7 +231,6 @@ CONFIG_CPU_HAS_PTEA=y
 #
 CONFIG_SH_TMU=y
 CONFIG_SH_TIMER_IRQ=16
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_SH_PCLK_FREQ=40000000
 
 #
diff --git a/arch/sh/configs/se7705_defconfig b/arch/sh/configs/se7705_defconfig
index 84717d854867..490dcbc2ce33 100644
--- a/arch/sh/configs/se7705_defconfig
+++ b/arch/sh/configs/se7705_defconfig
@@ -239,7 +239,6 @@ CONFIG_CPU_HAS_SR_RB=y
 #
 CONFIG_SH_TMU=y
 CONFIG_SH_TIMER_IRQ=16
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_SH_PCLK_FREQ=33333333
 
 #
diff --git a/arch/sh/configs/se7712_defconfig b/arch/sh/configs/se7712_defconfig
index 240a1cef69aa..2dd83af988f0 100644
--- a/arch/sh/configs/se7712_defconfig
+++ b/arch/sh/configs/se7712_defconfig
@@ -236,7 +236,6 @@ CONFIG_CPU_HAS_SR_RB=y
 #
 CONFIG_SH_TMU=y
 CONFIG_SH_TIMER_IRQ=16
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_SH_PCLK_FREQ=66666666
 
 #
diff --git a/arch/sh/configs/se7750_defconfig b/arch/sh/configs/se7750_defconfig
index c60b6fd4fc42..167786f9a9bd 100644
--- a/arch/sh/configs/se7750_defconfig
+++ b/arch/sh/configs/se7750_defconfig
@@ -235,7 +235,6 @@ CONFIG_CPU_HAS_PTEA=y
 #
 CONFIG_SH_TMU=y
 CONFIG_SH_TIMER_IRQ=16
-# CONFIG_NO_IDLE_HZ is not set
 CONFIG_SH_PCLK_FREQ=33333333
 
 #
diff --git a/drivers/acorn/char/Makefile b/drivers/acorn/char/Makefile
deleted file mode 100644
index d006c9f168d2..000000000000
--- a/drivers/acorn/char/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the acorn character device drivers.
-#
-
-obj-$(CONFIG_L7200_KEYB)        += defkeymap-l7200.o keyb_l7200.o
diff --git a/drivers/acorn/char/defkeymap-l7200.c b/drivers/acorn/char/defkeymap-l7200.c
deleted file mode 100644
index 93d80a1c36f9..000000000000
--- a/drivers/acorn/char/defkeymap-l7200.c
+++ /dev/null
@@ -1,386 +0,0 @@
-/*
- * linux/drivers/acorn/char/defkeymap-l7200.c
- *
- * Default keyboard maps for LinkUp Systems L7200 board
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   08-04-2000 SJH     Created file
- */
-
-#include <linux/types.h>
-#include <linux/keyboard.h>
-#include <linux/kd.h>
-
-/* Normal (maps 1:1 with no processing) */
-#define KTn     0xF0
-/* Function keys */
-#define KTf     0xF1
-/* Special (Performs special house-keeping funcs) */
-#define KTs     0xF2
-#define KIGNORE         K(KTs, 0)       /* Ignore */
-#define KENTER          K(KTs, 1)       /* Enter */
-#define KREGS           K(KTs, 2)       /* Regs */
-#define KMEM            K(KTs, 3)       /* Mem */
-#define KSTAT           K(KTs, 4)       /* State */
-#define KINTR           K(KTs, 5)       /* Intr */
-#define Ksl     6       /* Last console */
-#define KCAPSLK         K(KTs, 7)       /* Caps lock */
-#define KNUMLK          K(KTs, 8)       /* Num-lock */
-#define KSCRLLK         K(KTs, 9)       /* Scroll-lock */
-#define KSCRLFOR        K(KTs,10)       /* Scroll forward */
-#define KSCRLBAK        K(KTs,11)       /* Scroll back */
-#define KREBOOT         K(KTs,12)       /* Reboot */
-#define KCAPSON         K(KTs,13)       /* Caps on */
-#define KCOMPOSE        K(KTs,14)       /* Compose */
-#define KSAK            K(KTs,15)       /* SAK */
-#define CONS_DEC        K(KTs,16)       /* Dec console */
-#define CONS_INC        K(KTs,17)       /* Incr console */
-#define KFLOPPY         K(KTs,18)       /* Floppy */
-/* Key pad (0-9 = digits, 10=+, 11=-, 12=*, 13=/, 14=enter, 16=., 17=# */
-#define KTp     0xF3
-#define KPAD_0          K(KTp, 0 )
-#define KPAD_1          K(KTp, 1 )
-#define KPAD_2          K(KTp, 2 )
-#define KPAD_3          K(KTp, 3 )
-#define KPAD_4          K(KTp, 4 )
-#define KPAD_5          K(KTp, 5 )
-#define KPAD_6          K(KTp, 6 )
-#define KPAD_7          K(KTp, 7 )
-#define KPAD_8          K(KTp, 8 )
-#define KPAD_9          K(KTp, 9 )
-#define KPAD_PL         K(KTp,10 )
-#define KPAD_MI         K(KTp,11 )
-#define KPAD_ML         K(KTp,12 )
-#define KPAD_DV         K(KTp,13 )
-#define KPAD_EN         K(KTp,14 )
-#define KPAD_DT         K(KTp,16 )
-#define KPAD_HS         K(KTp,20 )
-/* Console switching */
-#define KCn     0xF5
-/* Cursor */
-#define KTc     0xF6
-#define Kcd     0       /* Cursor down */
-#define Kcl     1       /* Cursor left */
-#define Kcr     2       /* Cursor right */
-#define Kcu     3       /* Cursor up */
-/* Shift/alt modifiers etc */
-#define KMd     0xF7
-#define KSHIFT          K(KMd, 0 )
-#define KALTGR          K(KMd, 1 )
-#define KCTRL           K(KMd, 2 )
-#define KALT            K(KMd, 3 )
-/* Meta */
-#define KMt     0xF8
-#define KAs     0xF9
-#define KPADA_0         K(KAs, 0 )
-#define KPADA_1         K(KAs, 1 )
-#define KPADA_2         K(KAs, 2 )
-#define KPADA_3         K(KAs, 3 )
-#define KPADA_4         K(KAs, 4 )
-#define KPADA_5         K(KAs, 5 )
-#define KPADA_6         K(KAs, 6 )
-#define KPADA_7         K(KAs, 7 )
-#define KPADA_8         K(KAs, 8 )
-#define KPADA_9         K(KAs, 9 )
-#define KPADB_0         K(KAs,10 )
-#define KPADB_1         K(KAs,11 )
-#define KPADB_2         K(KAs,12 )
-#define KPADB_3         K(KAs,13 )
-#define KPADB_4         K(KAs,14 )
-#define KPADB_5         K(KAs,15 )
-#define KPADB_6         K(KAs,16 )
-#define KPADB_7         K(KAs,17 )
-#define KPADB_8         K(KAs,18 )
-#define KPADB_9         K(KAs,19 )
-/* Locking keys */
-#define KLk     0xFA
-/* Letters */
-#define KTl     0xFB
-
-/*
- * Here is the layout of the keys for the Fujitsu QWERTY
- * style keyboard:
- *
- *      static char Fujitsu_Key_Table[] =
- *      {
- *        KALT, '`' , KNUL, KCTL, KFUN, KESC, '1' , '2' ,
- *        '9' , '0' , '-' , '=' , KNUL, KBSP, KNUL, KNUL,
- *        KNUL, KBSL, KSHF, KNUL, KNUL, KDEL, KNUL, 't' ,
- *        'y' , 'u' , 'i' , KRET, KSHF, KPGD, KNUL, KNUL,
- *        KNUL, KTAB, KNUL, KNUL, KNUL, 'q' , 'w' , 'e' ,
- *        'r' , 'o' , 'p' , '[' , KNUL, ']' , KNUL, KNUL,
- *        KNUL, 'z' , KNUL, KNUL, KNUL, KSHL, KNUL, KNUL,
- *        'k' , 'l' , ';' , KSQT, KNUL, KPGU, KNUL, KNUL,
- *        KNUL, 'a' , KNUL, KNUL, KNUL, 's' , 'd' , 'f' ,
- *        'g' , 'h' , 'j' , '/' , KNUL, KHME, KNUL, KNUL,
- *        KNUL, 'x' , KNUL, KNUL, KNUL, 'c' , 'v' , 'b' ,
- *        'n' , 'm' , ',' , '.' , KNUL, ' ' , KNUL, KNUL,
- *        KNUL, KNUL, KNUL, KNUL, KNUL, '3' , '4' , '5' ,
- *        '6' , '7' , '8' , KNUL, KPRG, KNUL, KEND, KNUL,
- *      };
- */
-
-u_short plain_map[NR_KEYS]=
-{
-        0xf703, 0xf060, 0xf200, 0xf702, 0xf200, 0xf01b, 0xf031, 0xf032,
-        0xf039, 0xf030, 0xf02d, 0xf03d, 0xf200, 0xf07f, 0xf200, 0xf200,
-        0xf200, 0xf05c, 0xf700, 0xf200, 0xf200, 0xf116, 0xf000, 0xfb74,
-        0xfb79, 0xfb75, 0xfb69, 0xf201, 0xf700, 0xf600, 0xf200, 0xf200,
-        0xf200, 0xf009, 0xf200, 0xf200, 0xf200, 0xfb71, 0xfb77, 0xfb65,
-        0xfb72, 0xfb6f, 0xfb70, 0xf05b, 0xf200, 0xf05d, 0xf200, 0xf200,
-        0xf200, 0xfb7a, 0xf200, 0xf200, 0xf200, 0xf207, 0xf200, 0xf200,
-        0xfb6b, 0xfb6c, 0xf03b, 0xf027, 0xf200, 0xf603, 0xf200, 0xf200,
-        0xf200, 0xfb61, 0xf200, 0xf200, 0xf200, 0xfb73, 0xfb64, 0xfb66,
-        0xfb67, 0xfb68, 0xfb6a, 0xf02f, 0xf200, 0xf601, 0xf200, 0xf200,
-        0xf200, 0xfb78, 0xf200, 0xf200, 0xf200, 0xfb63, 0xfb76, 0xfb62,
-        0xfb6e, 0xfb6d, 0xf02c, 0xf02e, 0xf200, 0xf020, 0xf200, 0xf200,
-        0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf033, 0xf034, 0xf035, 
-        0xf036, 0xf037, 0xf038, 0xf200, 0xf200, 0xf200, 0xf602, 0xf200, 
-        0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 
-        0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 
-};
-
-u_short shift_map[NR_KEYS]=
-{
-        0xf703, 0xf07e, 0xf200, 0xf702, 0xf200, 0xf01b, 0xf021, 0xf040,
-        0xf028, 0xf029, 0xf05f, 0xf02b, 0xf200, 0xf07f, 0xf200, 0xf200,
-        0xf200, 0xf07c, 0xf700, 0xf200, 0xf200, 0xf116, 0xf000, 0xfb54,
-        0xfb59, 0xfb55, 0xfb49, 0xf201, 0xf700, 0xf600, 0xf200, 0xf200,
-        0xf200, 0xf009, 0xf200, 0xf200, 0xf200, 0xfb51, 0xfb57, 0xfb45,
-        0xfb52, 0xfb4f, 0xfb50, 0xf07b, 0xf200, 0xf07d, 0xf200, 0xf200,
-        0xf200, 0xfb5a, 0xf200, 0xf200, 0xf200, 0xf207, 0xf200, 0xf200,
-        0xfb4b, 0xfb4c, 0xf03a, 0xf022, 0xf200, 0xf603, 0xf200, 0xf200,
-        0xf200, 0xfb41, 0xf200, 0xf200, 0xf200, 0xfb53, 0xfb44, 0xfb46,
-        0xfb47, 0xfb48, 0xfb4a, 0xf03f, 0xf200, 0xf601, 0xf200, 0xf200,
-        0xf200, 0xfb58, 0xf200, 0xf200, 0xf200, 0xfb43, 0xfb56, 0xfb42,
-        0xfb4e, 0xfb4d, 0xf03c, 0xf03e, 0xf200, 0xf020, 0xf200, 0xf200,
-        0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf023, 0xf024, 0xf025, 
-        0xf05e, 0xf026, 0xf02a, 0xf200, 0xf200, 0xf200, 0xf602, 0xf200, 
-        0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 
-        0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 
-};
-
-u_short altgr_map[NR_KEYS]=
-{
-  KIGNORE   ,K(KCn,12 ),K(KCn,13 ),K(KCn,14  ),K(KCn,15 ),K(KCn,16 ),K(KCn,17  ),K(KCn, 18),
-  K(KCn, 19),K(KCn,20 ),K(KCn,21 ),K(KCn,22  ),K(KCn,23 ),KIGNORE   ,KREGS      ,KINTR     ,
-  KIGNORE   ,KIGNORE   ,K(KTn,'@'),KIGNORE    ,K(KTn,'$'),KIGNORE   ,KIGNORE    ,K(KTn,'{'),
-  K(KTn,'['),K(KTn,']'),K(KTn,'}'),K(KTn,'\\'),KIGNORE   ,KIGNORE   ,KIGNORE    ,K(KTf,21 ),
-  K(KTf,20 ),K(KTf,24 ),KNUMLK    ,KPAD_DV    ,KPAD_ML   ,KPAD_HS   ,KIGNORE    ,K(KTl,'q'),
-  K(KTl,'w'),K(KTl,'e'),K(KTl,'r'),K(KTl,'t' ),K(KTl,'y'),K(KTl,'u'),K(KTl,'i' ),K(KTl,'o'),
-  K(KTl,'p'),KIGNORE   ,K(KTn,'~'),KIGNORE    ,K(KTf,22 ),K(KTf,23 ),K(KTf,25  ),KPADB_7   ,
-  KPADB_8   ,KPADB_9   ,KPAD_MI   ,KCTRL      ,K(KAs,20 ),K(KTl,'s'),K(KAs,23  ),K(KAs,25 ),
-  K(KTl,'g'),K(KTl,'h'),K(KTl,'j'),K(KTl,'k' ),K(KTl,'l'),KIGNORE   ,KIGNORE    ,KENTER    ,
-  KPADB_4   ,KPADB_5   ,KPADB_6   ,KPAD_PL    ,KSHIFT    ,KIGNORE   ,K(KTl,'z' ),K(KTl,'x'),
-  K(KAs,22 ),K(KTl,'v'),K(KTl,21 ),K(KTl,'n' ),K(KTl,'m'),KIGNORE   ,KIGNORE    ,KIGNORE   ,
-  KSHIFT    ,K(KTc,Kcu),KPADB_1   ,KPADB_2    ,KPADB_3   ,KCAPSLK   ,KALT       ,KIGNORE   ,
-  KALTGR    ,KCTRL     ,K(KTc,Kcl),K(KTc,Kcd ),K(KTc,Kcr),KPADB_0   ,KPAD_DT    ,KPAD_EN   ,
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,
-};
-
-u_short ctrl_map[NR_KEYS]=
-{
-        0xf703, 0xf200, 0xf200, 0xf702, 0xf200, 0xf200, 0xf001, 0xf002,
-        0xf009, 0xf000, 0xf031, 0xf200, 0xf200, 0xf07f, 0xf200, 0xf200,
-        0xf200, 0xf01c, 0xf700, 0xf200, 0xf200, 0xf116, 0xf000, 0xf020,
-        0xf019, 0xf015, 0xf009, 0xf201, 0xf700, 0xf600, 0xf200, 0xf200,
-        0xf200, 0xf009, 0xf200, 0xf200, 0xf200, 0xf011, 0xf017, 0xf005,
-        0xf012, 0xf00f, 0xf010, 0xf01b, 0xf200, 0xf01d, 0xf200, 0xf200,
-        0xf200, 0xf01a, 0xf200, 0xf200, 0xf200, 0xf207, 0xf200, 0xf200,
-        0xf00b, 0xf00c, 0xf200, 0xf007, 0xf200, 0xf603, 0xf200, 0xf200,
-        0xf200, 0xf001, 0xf200, 0xf200, 0xf200, 0xf001, 0xf013, 0xf006,
-        0xf007, 0xf008, 0xf00a, 0xf07f, 0xf200, 0xf601, 0xf200, 0xf200,
-        0xf200, 0xf018, 0xf200, 0xf200, 0xf200, 0xf003, 0xf016, 0xf002,
-        0xf00e, 0xf00d, 0xf200, 0xf200, 0xf200, 0xf000, 0xf200, 0xf200,
-        0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf01b, 0xf01c, 0xf01d, 
-        0xf036, 0xf037, 0xf038, 0xf200, 0xf200, 0xf200, 0xf602, 0xf200, 
-        0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 
-        0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf602, 0xf200, 
-};
-
-u_short shift_ctrl_map[NR_KEYS]=
-{
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,KIGNORE   ,KFLOPPY    ,KINTR     ,
-  KIGNORE   ,KIGNORE   ,K(KTn, 0 ),KIGNORE    ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,K(KTn,31  ),KIGNORE   ,KIGNORE   ,KIGNORE    ,K(KTf,21 ),
-  K(KTf,20 ),K(KTf,24 ),KNUMLK    ,KPAD_DV    ,KPAD_ML   ,KPAD_HS   ,KIGNORE    ,K(KTn,17 ),
-  K(KTn,23 ),K(KTn, 5 ),K(KTn,18 ),K(KTn,20  ),K(KTn,25 ),K(KTn,21 ),K(KTn, 9  ),K(KTn,15 ),
-  K(KTn,16 ),KIGNORE   ,KIGNORE   ,KIGNORE    ,K(KTf,22 ),K(KTf,23 ),K(KTf,25  ),KPAD_7    ,
-  KPAD_8    ,KPAD_9    ,KPAD_MI   ,KCTRL      ,K(KTn, 1 ),K(KTn,19 ),K(KTn, 4  ),K(KTn, 6 ),
-  K(KTn, 7 ),K(KTn, 8 ),K(KTn,10 ),K(KTn,11  ),K(KTn,12 ),KIGNORE   ,K(KTn, 7  ),KENTER    ,
-  KPAD_4    ,KPAD_5    ,KPAD_6    ,KPAD_PL    ,KSHIFT    ,KIGNORE   ,K(KTn,26  ),K(KTn,24 ),
-  K(KTn, 3 ),K(KTn,22 ),K(KTn, 2 ),K(KTn,14  ),K(KTn,13 ),KIGNORE   ,KIGNORE    ,KIGNORE   ,
-  KSHIFT    ,K(KTc,Kcu),KPAD_1    ,KPAD_2     ,KPAD_3    ,KCAPSLK   ,KALT       ,K(KTn, 0 ),
-  KALTGR    ,KCTRL     ,K(KTc,Kcl),K(KTc,Kcd ),K(KTc,Kcr),KPAD_0    ,KPAD_DT    ,KPAD_EN   ,
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,
-};
-
-u_short alt_map[NR_KEYS]=
-{
-  K(KMt,27 ),K(KCn, 0 ),K(KCn, 1 ),K(KCn, 2  ),K(KCn, 3 ),K(KCn, 4 ),K(KCn, 5  ),K(KCn, 6 ),
-  K(KCn, 7 ),K(KCn, 8 ),K(KCn, 9 ),K(KCn,10  ),K(KCn,11 ),KIGNORE   ,KSCRLLK    ,KINTR     ,
-  K(KMt,'`'),K(KMt,'1'),K(KMt,'2'),K(KMt,'3' ),K(KMt,'4'),K(KMt,'5'),K(KMt,'6' ),K(KMt,'7'),
-  K(KMt,'8'),K(KMt,'9'),K(KMt,'0'),K(KMt,'-' ),K(KMt,'='),K(KMt,'£'),K(KMt,127 ),K(KTf,21 ),
-  K(KTf,20 ),K(KTf,24 ),KNUMLK    ,KPAD_DV    ,KPAD_ML   ,KPAD_HS   ,K(KMt, 9  ),K(KMt,'q'),
-  K(KMt,'w'),K(KMt,'e'),K(KMt,'r'),K(KMt,'t' ),K(KMt,'y'),K(KMt,'u'),K(KMt,'i' ),K(KMt,'o'),
-  K(KMt,'p'),K(KMt,'['),K(KMt,']'),K(KMt,'\\'),K(KTf,22 ),K(KTf,23 ),K(KTf,25  ),KPADA_7   ,
-  KPADA_8   ,KPADA_9   ,KPAD_MI   ,KCTRL      ,K(KMt,'a'),K(KMt,'s'),K(KMt,'d' ),K(KMt,'f'),
-  K(KMt,'g'),K(KMt,'h'),K(KMt,'j'),K(KMt,'k' ),K(KMt,'l'),K(KMt,';'),K(KMt,'\''),K(KMt,13 ),
-  KPADA_4   ,KPADA_5   ,KPADA_6   ,KPAD_PL    ,KSHIFT    ,KIGNORE   ,K(KMt,'z' ),K(KMt,'x'),
-  K(KMt,'c'),K(KMt,'v'),K(KMt,'b'),K(KMt,'n' ),K(KMt,'m'),K(KMt,','),K(KMt,'.' ),KIGNORE   ,
-  KSHIFT    ,K(KTc,Kcu),KPADA_1   ,KPADA_2    ,KPADA_3   ,KCAPSLK   ,KALT       ,K(KMt,' '),
-  KALTGR    ,KCTRL     ,CONS_DEC  ,K(KTc,Kcd ),CONS_INC  ,KPADA_0   ,KPAD_DT    ,KPAD_EN   ,
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,
-};
-
-u_short ctrl_alt_map[NR_KEYS]=
-{
-  KIGNORE   ,K(KCn, 0 ),K(KCn, 1 ),K(KCn, 2  ),K(KCn, 3 ),K(KCn, 4 ),K(KCn, 5  ),K(KCn, 6 ),
-  K(KCn, 7 ),K(KCn, 8 ),K(KCn, 9 ),K(KCn,10  ),K(KCn,11 ),KIGNORE   ,KIGNORE    ,KINTR     ,
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,KIGNORE   ,KIGNORE    ,K(KTf,21 ),
-  K(KTf,20 ),K(KTf,24 ),KNUMLK    ,KPAD_DV    ,KPAD_ML   ,KPAD_HS   ,KIGNORE    ,K(KMt,17 ),
-  K(KMt,23 ),K(KMt, 5 ),K(KMt,18 ),K(KMt,20  ),K(KMt,25 ),K(KMt,21 ),K(KMt, 9  ),K(KMt,15 ),
-  K(KMt,16 ),KIGNORE   ,KIGNORE   ,KIGNORE    ,KREBOOT   ,K(KTf,23 ),K(KTf,25  ),KPAD_7    ,
-  KPAD_8    ,KPAD_9    ,KPAD_MI   ,KCTRL      ,K(KMt, 1 ),K(KMt,19 ),K(KMt, 4  ),K(KMt, 6 ),
-  K(KMt, 7 ),K(KMt, 8 ),K(KMt,10 ),K(KMt,11  ),K(KMt,12 ),KIGNORE   ,KIGNORE    ,KENTER    ,
-  KPAD_4    ,KPAD_5    ,KPAD_6    ,KPAD_PL    ,KSHIFT    ,KIGNORE   ,K(KMt,26  ),K(KMt,24 ),
-  K(KMt, 3 ),K(KMt,22 ),K(KMt, 2 ),K(KMt,14  ),K(KMt,13 ),KIGNORE   ,KIGNORE    ,KIGNORE   ,
-  KSHIFT    ,K(KTc,Kcu),KPAD_1    ,KPAD_2     ,KPAD_3    ,KCAPSLK   ,KALT       ,KIGNORE   ,
-  KALTGR    ,KCTRL     ,K(KTc,Kcl),K(KTc,Kcd ),K(KTc,Kcr),KPAD_0    ,KREBOOT    ,KPAD_EN   ,
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,
-  KIGNORE   ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,KIGNORE   ,KIGNORE    ,KIGNORE   ,
-};
-
-ushort *key_maps[MAX_NR_KEYMAPS] = {
-        plain_map, shift_map, altgr_map, 0,
-        ctrl_map, shift_ctrl_map, 0, 0,
-        alt_map, 0, 0, 0,
-        ctrl_alt_map,   0
-};
-
-unsigned int keymap_count = 7;
-
-/*
- * Philosophy: most people do not define more strings, but they who do
- * often want quite a lot of string space. So, we statically allocate
- * the default and allocate dynamically in chunks of 512 bytes.
- */
-
-char func_buf[] = {
-        '\033', '[', '[', 'A', 0,
-        '\033', '[', '[', 'B', 0,
-        '\033', '[', '[', 'C', 0,
-        '\033', '[', '[', 'D', 0,
-        '\033', '[', '[', 'E', 0,
-        '\033', '[', '1', '7', '~', 0,
-        '\033', '[', '1', '8', '~', 0,
-        '\033', '[', '1', '9', '~', 0,
-        '\033', '[', '2', '0', '~', 0,
-        '\033', '[', '2', '1', '~', 0,
-        '\033', '[', '2', '3', '~', 0,
-        '\033', '[', '2', '4', '~', 0,
-        '\033', '[', '2', '5', '~', 0,
-        '\033', '[', '2', '6', '~', 0,
-        '\033', '[', '2', '8', '~', 0,
-        '\033', '[', '2', '9', '~', 0,
-        '\033', '[', '3', '1', '~', 0,
-        '\033', '[', '3', '2', '~', 0,
-        '\033', '[', '3', '3', '~', 0,
-        '\033', '[', '3', '4', '~', 0,
-        '\033', '[', '1', '~', 0,
-        '\033', '[', '2', '~', 0,
-        '\033', '[', '3', '~', 0,
-        '\033', '[', '4', '~', 0,
-        '\033', '[', '5', '~', 0,
-        '\033', '[', '6', '~', 0,
-        '\033', '[', 'M', 0,
-        '\033', '[', 'P', 0,
-};
-
-char *funcbufptr = func_buf;
-int funcbufsize = sizeof(func_buf);
-int funcbufleft = 0;          /* space left */
-
-char *func_table[MAX_NR_FUNC] = {
-        func_buf + 0,
-        func_buf + 5,
-        func_buf + 10,
-        func_buf + 15,
-        func_buf + 20,
-        func_buf + 25,
-        func_buf + 31,
-        func_buf + 37,
-        func_buf + 43,
-        func_buf + 49,
-        func_buf + 55,
-        func_buf + 61,
-        func_buf + 67,
-        func_buf + 73,
-        func_buf + 79,
-        func_buf + 85,
-        func_buf + 91,
-        func_buf + 97,
-        func_buf + 103,
-        func_buf + 109,
-        func_buf + 115,
-        func_buf + 120,
-        func_buf + 125,
-        func_buf + 130,
-        func_buf + 135,
-        func_buf + 140,
-        func_buf + 145,
-        0,
-        0,
-        func_buf + 149,
-        0,
-};
-
-struct kbdiacruc accent_table[MAX_DIACR] = {
-        {'`', 'A', 0300},       {'`', 'a', 0340},
-        {'\'', 'A', 0301},      {'\'', 'a', 0341},
-        {'^', 'A', 0302},       {'^', 'a', 0342},
-        {'~', 'A', 0303},       {'~', 'a', 0343},
-        {'"', 'A', 0304},       {'"', 'a', 0344},
-        {'O', 'A', 0305},       {'o', 'a', 0345},
-        {'0', 'A', 0305},       {'0', 'a', 0345},
-        {'A', 'A', 0305},       {'a', 'a', 0345},
-        {'A', 'E', 0306},       {'a', 'e', 0346},
-        {',', 'C', 0307},       {',', 'c', 0347},
-        {'`', 'E', 0310},       {'`', 'e', 0350},
-        {'\'', 'E', 0311},      {'\'', 'e', 0351},
-        {'^', 'E', 0312},       {'^', 'e', 0352},
-        {'"', 'E', 0313},       {'"', 'e', 0353},
-        {'`', 'I', 0314},       {'`', 'i', 0354},
-        {'\'', 'I', 0315},      {'\'', 'i', 0355},
-        {'^', 'I', 0316},       {'^', 'i', 0356},
-        {'"', 'I', 0317},       {'"', 'i', 0357},
-        {'-', 'D', 0320},       {'-', 'd', 0360},
-        {'~', 'N', 0321},       {'~', 'n', 0361},
-        {'`', 'O', 0322},       {'`', 'o', 0362},
-        {'\'', 'O', 0323},      {'\'', 'o', 0363},
-        {'^', 'O', 0324},       {'^', 'o', 0364},
-        {'~', 'O', 0325},       {'~', 'o', 0365},
-        {'"', 'O', 0326},       {'"', 'o', 0366},
-        {'/', 'O', 0330},       {'/', 'o', 0370},
-        {'`', 'U', 0331},       {'`', 'u', 0371},
-        {'\'', 'U', 0332},      {'\'', 'u', 0372},
-        {'^', 'U', 0333},       {'^', 'u', 0373},
-        {'"', 'U', 0334},       {'"', 'u', 0374},
-        {'\'', 'Y', 0335},      {'\'', 'y', 0375},
-        {'T', 'H', 0336},       {'t', 'h', 0376},
-        {'s', 's', 0337},       {'"', 'y', 0377},
-        {'s', 'z', 0337},       {'i', 'j', 0377},
-};
-
-unsigned int accent_table_size = 68;
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index eb69fbadc9cb..dde6ce963a19 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -39,7 +39,6 @@
 #include <asm/io.h>
 #include <asm/arch/i2c.h>
 #include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
 
 struct pxa_i2c {
         spinlock_t              lock;
@@ -945,32 +944,6 @@ static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
         .functionality  = i2c_pxa_functionality,
 };
 
-static void i2c_pxa_enable(struct platform_device *dev)
-{
-        if (cpu_is_pxa27x()) {
-                switch (dev->id) {
-                case 0:
-                        pxa_gpio_mode(GPIO117_I2CSCL_MD);
-                        pxa_gpio_mode(GPIO118_I2CSDA_MD);
-                        break;
-                case 1:
-                        local_irq_disable();
-                        PCFR |= PCFR_PI2CEN;
-                        local_irq_enable();
-                        break;
-                }
-        }
-}
-
-static void i2c_pxa_disable(struct platform_device *dev)
-{
-        if (cpu_is_pxa27x() && dev->id == 1) {
-                local_irq_disable();
-                PCFR &= ~PCFR_PI2CEN;
-                local_irq_enable();
-        }
-}
-
 #define res_len(r)              ((r)->end - (r)->start + 1)
 static int i2c_pxa_probe(struct platform_device *dev)
 {
@@ -1036,7 +1009,6 @@ static int i2c_pxa_probe(struct platform_device *dev)
 #endif
 
         clk_enable(i2c->clk);
-        i2c_pxa_enable(dev);
 
         if (plat) {
                 i2c->adap.class = plat->class;
@@ -1080,7 +1052,6 @@ eadapt:
                 free_irq(irq, i2c);
 ereqirq:
         clk_disable(i2c->clk);
-        i2c_pxa_disable(dev);
         iounmap(i2c->reg_base);
 eremap:
         clk_put(i2c->clk);
@@ -1103,7 +1074,6 @@ static int __exit i2c_pxa_remove(struct platform_device *dev)
 
         clk_disable(i2c->clk);
         clk_put(i2c->clk);
-        i2c_pxa_disable(dev);
 
         iounmap(i2c->reg_base);
         release_mem_region(i2c->iobase, i2c->iosize);
diff --git a/drivers/i2c/chips/isp1301_omap.c b/drivers/i2c/chips/isp1301_omap.c
index b1b45dddb17e..03a33f1b9cd3 100644
--- a/drivers/i2c/chips/isp1301_omap.c
+++ b/drivers/i2c/chips/isp1301_omap.c
@@ -72,7 +72,7 @@ struct isp1301 {
 };
 
 
-/* bits in OTG_CTRL_REG */
+/* bits in OTG_CTRL */
 
 #define OTG_XCEIV_OUTPUTS \
         (OTG_ASESSVLD|OTG_BSESSEND|OTG_BSESSVLD|OTG_VBUSVLD|OTG_ID)
@@ -186,8 +186,8 @@ isp1301_clear_bits(struct isp1301 *isp, u8 reg, u8 bits)
 
 /* operational registers */
 #define ISP1301_MODE_CONTROL_1          0x04    /* u8 read, set, +1 clear */
-#       define  MC1_SPEED_REG           (1 << 0)
-#       define  MC1_SUSPEND_REG         (1 << 1)
+#       define  MC1_SPEED               (1 << 0)
+#       define  MC1_SUSPEND             (1 << 1)
 #       define  MC1_DAT_SE0             (1 << 2)
 #       define  MC1_TRANSPARENT         (1 << 3)
 #       define  MC1_BDIS_ACON_EN        (1 << 4)
@@ -274,7 +274,7 @@ static void power_down(struct isp1301 *isp)
         isp->otg.state = OTG_STATE_UNDEFINED;
 
         // isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
-        isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND_REG);
+        isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND);
 
         isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_ID_PULLDOWN);
         isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0);
@@ -283,7 +283,7 @@ static void power_down(struct isp1301 *isp)
 static void power_up(struct isp1301 *isp)
 {
         // isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
-        isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND_REG);
+        isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND);
 
         /* do this only when cpu is driving transceiver,
          * so host won't see a low speed device...
@@ -360,6 +360,8 @@ isp1301_defer_work(struct isp1301 *isp, int work)
 /* called from irq handlers */
 static void a_idle(struct isp1301 *isp, const char *tag)
 {
+        u32 l;
+
         if (isp->otg.state == OTG_STATE_A_IDLE)
                 return;
 
@@ -373,13 +375,17 @@ static void a_idle(struct isp1301 *isp, const char *tag)
                 gadget_suspend(isp);
         }
         isp->otg.state = OTG_STATE_A_IDLE;
-        isp->last_otg_ctrl = OTG_CTRL_REG = OTG_CTRL_REG & OTG_XCEIV_OUTPUTS;
+        l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
+        omap_writel(l, OTG_CTRL);
+        isp->last_otg_ctrl = l;
         pr_debug("  --> %s/%s\n", state_name(isp), tag);
 }
 
 /* called from irq handlers */
 static void b_idle(struct isp1301 *isp, const char *tag)
 {
+        u32 l;
+
         if (isp->otg.state == OTG_STATE_B_IDLE)
                 return;
 
@@ -393,7 +399,9 @@ static void b_idle(struct isp1301 *isp, const char *tag)
                 gadget_suspend(isp);
         }
         isp->otg.state = OTG_STATE_B_IDLE;
-        isp->last_otg_ctrl = OTG_CTRL_REG = OTG_CTRL_REG & OTG_XCEIV_OUTPUTS;
+        l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
+        omap_writel(l, OTG_CTRL);
+        isp->last_otg_ctrl = l;
         pr_debug("  --> %s/%s\n", state_name(isp), tag);
 }
 
@@ -406,7 +414,7 @@ dump_regs(struct isp1301 *isp, const char *label)
         u8      src = isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE);
 
         pr_debug("otg: %06x, %s %s, otg/%02x stat/%02x.%02x\n",
-                OTG_CTRL_REG, label, state_name(isp),
+                omap_readl(OTG_CTRL), label, state_name(isp),
                 ctrl, status, src);
         /* mode control and irq enables don't change much */
 #endif
@@ -429,7 +437,7 @@ dump_regs(struct isp1301 *isp, const char *label)
 static void check_state(struct isp1301 *isp, const char *tag)
 {
         enum usb_otg_state      state = OTG_STATE_UNDEFINED;
-        u8                      fsm = OTG_TEST_REG & 0x0ff;
+        u8                      fsm = omap_readw(OTG_TEST) & 0x0ff;
         unsigned                extra = 0;
 
         switch (fsm) {
@@ -494,7 +502,8 @@ static void check_state(struct isp1301 *isp, const char *tag)
         if (isp->otg.state == state && !extra)
                 return;
         pr_debug("otg: %s FSM %s/%02x, %s, %06x\n", tag,
-                state_string(state), fsm, state_name(isp), OTG_CTRL_REG);
+                state_string(state), fsm, state_name(isp),
+                omap_readl(OTG_CTRL));
 }
 
 #else
@@ -508,10 +517,11 @@ static void update_otg1(struct isp1301 *isp, u8 int_src)
 {
         u32     otg_ctrl;
 
-        otg_ctrl = OTG_CTRL_REG
-                        & OTG_CTRL_MASK
-                        & ~OTG_XCEIV_INPUTS
-                        & ~(OTG_ID|OTG_ASESSVLD|OTG_VBUSVLD);
+        otg_ctrl = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
+        otg_ctrl &= ~OTG_XCEIV_INPUTS;
+        otg_ctrl &= ~(OTG_ID|OTG_ASESSVLD|OTG_VBUSVLD);
+
+
         if (int_src & INTR_SESS_VLD)
                 otg_ctrl |= OTG_ASESSVLD;
         else if (isp->otg.state == OTG_STATE_A_WAIT_VFALL) {
@@ -534,7 +544,7 @@ static void update_otg1(struct isp1301 *isp, u8 int_src)
                         return;
                 }
         }
-        OTG_CTRL_REG = otg_ctrl;
+        omap_writel(otg_ctrl, OTG_CTRL);
 }
 
 /* outputs from ISP1301_OTG_STATUS */
@@ -542,15 +552,14 @@ static void update_otg2(struct isp1301 *isp, u8 otg_status)
 {
         u32     otg_ctrl;
 
-        otg_ctrl = OTG_CTRL_REG
-                        & OTG_CTRL_MASK
-                        & ~OTG_XCEIV_INPUTS
-                        & ~(OTG_BSESSVLD|OTG_BSESSEND);
+        otg_ctrl = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
+        otg_ctrl &= ~OTG_XCEIV_INPUTS;
+        otg_ctrl &= ~(OTG_BSESSVLD | OTG_BSESSEND);
         if (otg_status & OTG_B_SESS_VLD)
                 otg_ctrl |= OTG_BSESSVLD;
         else if (otg_status & OTG_B_SESS_END)
                 otg_ctrl |= OTG_BSESSEND;
-        OTG_CTRL_REG = otg_ctrl;
+        omap_writel(otg_ctrl, OTG_CTRL);
 }
 
 /* inputs going to ISP1301 */
@@ -559,7 +568,7 @@ static void otg_update_isp(struct isp1301 *isp)
         u32     otg_ctrl, otg_change;
         u8      set = OTG1_DM_PULLDOWN, clr = OTG1_DM_PULLUP;
 
-        otg_ctrl = OTG_CTRL_REG;
+        otg_ctrl = omap_readl(OTG_CTRL);
         otg_change = otg_ctrl ^ isp->last_otg_ctrl;
         isp->last_otg_ctrl = otg_ctrl;
         otg_ctrl = otg_ctrl & OTG_XCEIV_INPUTS;
@@ -639,6 +648,8 @@ pulldown:
 
         /* HNP switch to host or peripheral; and SRP */
         if (otg_change & OTG_PULLUP) {
+                u32 l;
+
                 switch (isp->otg.state) {
                 case OTG_STATE_B_IDLE:
                         if (clr & OTG1_DP_PULLUP)
@@ -655,7 +666,9 @@ pulldown:
                 default:
                         break;
                 }
-                OTG_CTRL_REG |= OTG_PULLUP;
+                l = omap_readl(OTG_CTRL);
+                l |= OTG_PULLUP;
+                omap_writel(l, OTG_CTRL);
         }
 
         check_state(isp, __func__);
@@ -664,20 +677,20 @@ pulldown:
 
 static irqreturn_t omap_otg_irq(int irq, void *_isp)
 {
-        u16             otg_irq = OTG_IRQ_SRC_REG;
+        u16             otg_irq = omap_readw(OTG_IRQ_SRC);
         u32             otg_ctrl;
         int             ret = IRQ_NONE;
         struct isp1301  *isp = _isp;
 
         /* update ISP1301 transciever from OTG controller */
         if (otg_irq & OPRT_CHG) {
-                OTG_IRQ_SRC_REG = OPRT_CHG;
+                omap_writew(OPRT_CHG, OTG_IRQ_SRC);
                 isp1301_defer_work(isp, WORK_UPDATE_ISP);
                 ret = IRQ_HANDLED;
 
         /* SRP to become b_peripheral failed */
         } else if (otg_irq & B_SRP_TMROUT) {
-                pr_debug("otg: B_SRP_TIMEOUT, %06x\n", OTG_CTRL_REG);
+                pr_debug("otg: B_SRP_TIMEOUT, %06x\n", omap_readl(OTG_CTRL));
                 notresponding(isp);
 
                 /* gadget drivers that care should monitor all kinds of
@@ -687,31 +700,31 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp)
                 if (isp->otg.state == OTG_STATE_B_SRP_INIT)
                         b_idle(isp, "srp_timeout");
 
-                OTG_IRQ_SRC_REG = B_SRP_TMROUT;
+                omap_writew(B_SRP_TMROUT, OTG_IRQ_SRC);
                 ret = IRQ_HANDLED;
 
         /* HNP to become b_host failed */
         } else if (otg_irq & B_HNP_FAIL) {
                 pr_debug("otg: %s B_HNP_FAIL, %06x\n",
-                                state_name(isp), OTG_CTRL_REG);
+                                state_name(isp), omap_readl(OTG_CTRL));
                 notresponding(isp);
 
-                otg_ctrl = OTG_CTRL_REG;
+                otg_ctrl = omap_readl(OTG_CTRL);
                 otg_ctrl |= OTG_BUSDROP;
                 otg_ctrl &= OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
-                OTG_CTRL_REG = otg_ctrl;
+                omap_writel(otg_ctrl, OTG_CTRL);
 
                 /* subset of b_peripheral()... */
                 isp->otg.state = OTG_STATE_B_PERIPHERAL;
                 pr_debug("  --> b_peripheral\n");
 
-                OTG_IRQ_SRC_REG = B_HNP_FAIL;
+                omap_writew(B_HNP_FAIL, OTG_IRQ_SRC);
                 ret = IRQ_HANDLED;
 
         /* detect SRP from B-device ... */
         } else if (otg_irq & A_SRP_DETECT) {
                 pr_debug("otg: %s SRP_DETECT, %06x\n",
-                                state_name(isp), OTG_CTRL_REG);
+                                state_name(isp), omap_readl(OTG_CTRL));
 
                 isp1301_defer_work(isp, WORK_UPDATE_OTG);
                 switch (isp->otg.state) {
@@ -719,49 +732,49 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp)
                         if (!isp->otg.host)
                                 break;
                         isp1301_defer_work(isp, WORK_HOST_RESUME);
-                        otg_ctrl = OTG_CTRL_REG;
+                        otg_ctrl = omap_readl(OTG_CTRL);
                         otg_ctrl |= OTG_A_BUSREQ;
                         otg_ctrl &= ~(OTG_BUSDROP|OTG_B_BUSREQ)
                                         & ~OTG_XCEIV_INPUTS
                                         & OTG_CTRL_MASK;
-                        OTG_CTRL_REG = otg_ctrl;
+                        omap_writel(otg_ctrl, OTG_CTRL);
                         break;
                 default:
                         break;
                 }
 
-                OTG_IRQ_SRC_REG = A_SRP_DETECT;
+                omap_writew(A_SRP_DETECT, OTG_IRQ_SRC);
                 ret = IRQ_HANDLED;
 
         /* timer expired:  T(a_wait_bcon) and maybe T(a_wait_vrise)
          * we don't track them separately
          */
         } else if (otg_irq & A_REQ_TMROUT) {
-                otg_ctrl = OTG_CTRL_REG;
+                otg_ctrl = omap_readl(OTG_CTRL);
                 pr_info("otg: BCON_TMOUT from %s, %06x\n",
                                 state_name(isp), otg_ctrl);
                 notresponding(isp);
 
                 otg_ctrl |= OTG_BUSDROP;
                 otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
-                OTG_CTRL_REG = otg_ctrl;
+                omap_writel(otg_ctrl, OTG_CTRL);
                 isp->otg.state = OTG_STATE_A_WAIT_VFALL;
 
-                OTG_IRQ_SRC_REG = A_REQ_TMROUT;
+                omap_writew(A_REQ_TMROUT, OTG_IRQ_SRC);
                 ret = IRQ_HANDLED;
 
         /* A-supplied voltage fell too low; overcurrent */
         } else if (otg_irq & A_VBUS_ERR) {
-                otg_ctrl = OTG_CTRL_REG;
+                otg_ctrl = omap_readl(OTG_CTRL);
                 printk(KERN_ERR "otg: %s, VBUS_ERR %04x ctrl %06x\n",
                         state_name(isp), otg_irq, otg_ctrl);
 
                 otg_ctrl |= OTG_BUSDROP;
                 otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
-                OTG_CTRL_REG = otg_ctrl;
+                omap_writel(otg_ctrl, OTG_CTRL);
                 isp->otg.state = OTG_STATE_A_VBUS_ERR;
 
-                OTG_IRQ_SRC_REG = A_VBUS_ERR;
+                omap_writew(A_VBUS_ERR, OTG_IRQ_SRC);
                 ret = IRQ_HANDLED;
 
         /* switch driver; the transciever code activates it,
@@ -770,7 +783,7 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp)
         } else if (otg_irq & DRIVER_SWITCH) {
                 int     kick = 0;
 
-                otg_ctrl = OTG_CTRL_REG;
+                otg_ctrl = omap_readl(OTG_CTRL);
                 printk(KERN_NOTICE "otg: %s, SWITCH to %s, ctrl %06x\n",
                                 state_name(isp),
                                 (otg_ctrl & OTG_DRIVER_SEL)
@@ -793,7 +806,7 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp)
                 } else {
                         if (!(otg_ctrl & OTG_ID)) {
                                 otg_ctrl &= OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
-                                OTG_CTRL_REG = otg_ctrl | OTG_A_BUSREQ;
+                                omap_writel(otg_ctrl | OTG_A_BUSREQ, OTG_CTRL);
                         }
 
                         if (isp->otg.host) {
@@ -818,7 +831,7 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp)
                         }
                 }
 
-                OTG_IRQ_SRC_REG = DRIVER_SWITCH;
+                omap_writew(DRIVER_SWITCH, OTG_IRQ_SRC);
                 ret = IRQ_HANDLED;
 
                 if (kick)
@@ -834,12 +847,15 @@ static struct platform_device *otg_dev;
 
 static int otg_init(struct isp1301 *isp)
 {
+        u32 l;
+
         if (!otg_dev)
                 return -ENODEV;
 
         dump_regs(isp, __func__);
         /* some of these values are board-specific... */
-        OTG_SYSCON_2_REG |= OTG_EN
+        l = omap_readl(OTG_SYSCON_2);
+        l |= OTG_EN
                 /* for B-device: */
                 | SRP_GPDATA            /* 9msec Bdev D+ pulse */
                 | SRP_GPDVBUS           /* discharge after VBUS pulse */
@@ -849,18 +865,22 @@ static int otg_init(struct isp1301 *isp)
                 | SRP_DPW               /* detect 167+ns SRP pulses */
                 | SRP_DATA | SRP_VBUS   /* accept both kinds of SRP pulse */
                 ;
+        omap_writel(l, OTG_SYSCON_2);
 
         update_otg1(isp, isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE));
         update_otg2(isp, isp1301_get_u8(isp, ISP1301_OTG_STATUS));
 
         check_state(isp, __func__);
         pr_debug("otg: %s, %s %06x\n",
-                        state_name(isp), __func__, OTG_CTRL_REG);
+                        state_name(isp), __func__, omap_readl(OTG_CTRL));
 
-        OTG_IRQ_EN_REG = DRIVER_SWITCH | OPRT_CHG
+        omap_writew(DRIVER_SWITCH | OPRT_CHG
                         | B_SRP_TMROUT | B_HNP_FAIL
-                        | A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT;
-        OTG_SYSCON_2_REG |= OTG_EN;
+                        | A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT, OTG_IRQ_EN);
+
+        l = omap_readl(OTG_SYSCON_2);
+        l |= OTG_EN;
+        omap_writel(l, OTG_SYSCON_2);
 
         return 0;
 }
@@ -927,7 +947,11 @@ static void otg_unbind(struct isp1301 *isp)
 
 static void b_peripheral(struct isp1301 *isp)
 {
-        OTG_CTRL_REG = OTG_CTRL_REG & OTG_XCEIV_OUTPUTS;
+        u32 l;
+
+        l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
+        omap_writel(l, OTG_CTRL);
+
         usb_gadget_vbus_connect(isp->otg.gadget);
 
 #ifdef  CONFIG_USB_OTG
@@ -999,6 +1023,8 @@ static void isp_update_otg(struct isp1301 *isp, u8 stat)
                         isp_bstat = 0;
                 }
         } else {
+                u32 l;
+
                 /* if user unplugged mini-A end of cable,
                  * don't bypass A_WAIT_VFALL.
                  */
@@ -1019,8 +1045,9 @@ static void isp_update_otg(struct isp1301 *isp, u8 stat)
                                 isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1,
                                                 MC1_BDIS_ACON_EN);
                                 isp->otg.state = OTG_STATE_B_IDLE;
-                                OTG_CTRL_REG &= OTG_CTRL_REG & OTG_CTRL_MASK
-                                                & ~OTG_CTRL_BITS;
+                                l = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
+                                l &= ~OTG_CTRL_BITS;
+                                omap_writel(l, OTG_CTRL);
                                 break;
                         case OTG_STATE_B_IDLE:
                                 break;
@@ -1046,7 +1073,8 @@ static void isp_update_otg(struct isp1301 *isp, u8 stat)
                         /* FALLTHROUGH */
                 case OTG_STATE_B_SRP_INIT:
                         b_idle(isp, __func__);
-                        OTG_CTRL_REG &= OTG_CTRL_REG & OTG_XCEIV_OUTPUTS;
+                        l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
+                        omap_writel(l, OTG_CTRL);
                         /* FALLTHROUGH */
                 case OTG_STATE_B_IDLE:
                         if (isp->otg.gadget && (isp_bstat & OTG_B_SESS_VLD)) {
@@ -1130,11 +1158,11 @@ isp1301_work(struct work_struct *work)
                         case OTG_STATE_A_WAIT_VRISE:
                                 isp->otg.state = OTG_STATE_A_HOST;
                                 pr_debug("  --> a_host\n");
-                                otg_ctrl = OTG_CTRL_REG;
+                                otg_ctrl = omap_readl(OTG_CTRL);
                                 otg_ctrl |= OTG_A_BUSREQ;
                                 otg_ctrl &= ~(OTG_BUSDROP|OTG_B_BUSREQ)
                                                 & OTG_CTRL_MASK;
-                                OTG_CTRL_REG = otg_ctrl;
+                                omap_writel(otg_ctrl, OTG_CTRL);
                                 break;
                         case OTG_STATE_B_WAIT_ACON:
                                 isp->otg.state = OTG_STATE_B_HOST;
@@ -1274,7 +1302,7 @@ isp1301_set_host(struct otg_transceiver *otg, struct usb_bus *host)
                 return -ENODEV;
 
         if (!host) {
-                OTG_IRQ_EN_REG = 0;
+                omap_writew(0, OTG_IRQ_EN);
                 power_down(isp);
                 isp->otg.host = 0;
                 return 0;
@@ -1325,12 +1353,13 @@ static int
 isp1301_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget)
 {
         struct isp1301  *isp = container_of(otg, struct isp1301, otg);
+        u32 l;
 
         if (!otg || isp != the_transceiver)
                 return -ENODEV;
 
         if (!gadget) {
-                OTG_IRQ_EN_REG = 0;
+                omap_writew(0, OTG_IRQ_EN);
                 if (!isp->otg.default_a)
                         enable_vbus_draw(isp, 0);
                 usb_gadget_vbus_disconnect(isp->otg.gadget);
@@ -1351,9 +1380,11 @@ isp1301_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget)
         isp->otg.gadget = gadget;
         // FIXME update its refcount
 
-        OTG_CTRL_REG = (OTG_CTRL_REG & OTG_CTRL_MASK
-                                & ~(OTG_XCEIV_OUTPUTS|OTG_CTRL_BITS))
-                        | OTG_ID;
+        l = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
+        l &= ~(OTG_XCEIV_OUTPUTS|OTG_CTRL_BITS);
+        l |= OTG_ID;
+        omap_writel(l, OTG_CTRL);
+
         power_up(isp);
         isp->otg.state = OTG_STATE_B_IDLE;
 
@@ -1405,16 +1436,17 @@ isp1301_start_srp(struct otg_transceiver *dev)
                         || isp->otg.state != OTG_STATE_B_IDLE)
                 return -ENODEV;
 
-        otg_ctrl = OTG_CTRL_REG;
+        otg_ctrl = omap_readl(OTG_CTRL);
         if (!(otg_ctrl & OTG_BSESSEND))
                 return -EINVAL;
 
         otg_ctrl |= OTG_B_BUSREQ;
         otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK;
-        OTG_CTRL_REG = otg_ctrl;
+        omap_writel(otg_ctrl, OTG_CTRL);
         isp->otg.state = OTG_STATE_B_SRP_INIT;
 
-        pr_debug("otg: SRP, %s ... %06x\n", state_name(isp), OTG_CTRL_REG);
+        pr_debug("otg: SRP, %s ... %06x\n", state_name(isp),
+                        omap_readl(OTG_CTRL));
 #ifdef  CONFIG_USB_OTG
         check_state(isp, __func__);
 #endif
@@ -1426,6 +1458,7 @@ isp1301_start_hnp(struct otg_transceiver *dev)
 {
 #ifdef  CONFIG_USB_OTG
         struct isp1301  *isp = container_of(dev, struct isp1301, otg);
+        u32 l;
 
         if (!dev || isp != the_transceiver)
                 return -ENODEV;
@@ -1452,7 +1485,9 @@ isp1301_start_hnp(struct otg_transceiver *dev)
 #endif
                 /* caller must suspend then clear A_BUSREQ */
                 usb_gadget_vbus_connect(isp->otg.gadget);
-                OTG_CTRL_REG |= OTG_A_SETB_HNPEN;
+                l = omap_readl(OTG_CTRL);
+                l |= OTG_A_SETB_HNPEN;
+                omap_writel(l, OTG_CTRL);
 
                 break;
         case OTG_STATE_A_PERIPHERAL:
@@ -1462,7 +1497,7 @@ isp1301_start_hnp(struct otg_transceiver *dev)
                 return -EILSEQ;
         }
         pr_debug("otg: HNP %s, %06x ...\n",
-                state_name(isp), OTG_CTRL_REG);
+                state_name(isp), omap_readl(OTG_CTRL));
         check_state(isp, __func__);
         return 0;
 #else
diff --git a/drivers/mmc/host/imxmmc.c b/drivers/mmc/host/imxmmc.c
index 95f33e87a99c..eed211b2ac70 100644
--- a/drivers/mmc/host/imxmmc.c
+++ b/drivers/mmc/host/imxmmc.c
@@ -42,6 +42,7 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
 #include <linux/delay.h>
+#include <linux/clk.h>
 
 #include <asm/dma.h>
 #include <asm/io.h>
@@ -92,6 +93,8 @@ struct imxmci_host {
         unsigned char           actual_bus_width;
 
         int                     prev_cmd_code;
+
+        struct clk              *clk;
 };
 
 #define IMXMCI_PEND_IRQ_b       0
@@ -841,7 +844,7 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
                 /* The prescaler is 5 for PERCLK2 equal to 96MHz
                  * then 96MHz / 5 = 19.2 MHz
                  */
-                clk=imx_get_perclk2();
+                clk = clk_get_rate(host->clk);
                 prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE;
                 switch(prescaler) {
                 case 0:
@@ -994,6 +997,13 @@ static int imxmci_probe(struct platform_device *pdev)
         host->res = r;
         host->irq = irq;
 
+        host->clk = clk_get(&pdev->dev, "perclk2");
+        if (IS_ERR(host->clk)) {
+                ret = PTR_ERR(host->clk);
+                goto out;
+        }
+        clk_enable(host->clk);
+
         imx_gpio_mode(PB8_PF_SD_DAT0);
         imx_gpio_mode(PB9_PF_SD_DAT1);
         imx_gpio_mode(PB10_PF_SD_DAT2);
@@ -1017,8 +1027,8 @@ static int imxmci_probe(struct platform_device *pdev)
         host->imask = IMXMCI_INT_MASK_DEFAULT;
         MMC_INT_MASK = host->imask;
 
-
-        if(imx_dma_request_by_prio(&host->dma, DRIVER_NAME, DMA_PRIO_LOW)<0){
+        host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
+        if(host->dma < 0) {
                 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
                 ret = -EBUSY;
                 goto out;
@@ -1053,6 +1063,10 @@ out:
                         imx_dma_free(host->dma);
                         host->dma_allocated=0;
                 }
+                if (host->clk) {
+                        clk_disable(host->clk);
+                        clk_put(host->clk);
+                }
         }
         if (mmc)
                 mmc_free_host(mmc);
@@ -1082,6 +1096,9 @@ static int imxmci_remove(struct platform_device *pdev)
 
                 tasklet_kill(&host->tasklet);
 
+                clk_disable(host->clk);
+                clk_put(host->clk);
+
                 release_resource(host->res);
 
                 mmc_free_host(mmc);
diff --git a/drivers/mtd/maps/omap_nor.c b/drivers/mtd/maps/omap_nor.c
index c12d8056bebd..68eec6c6c517 100644
--- a/drivers/mtd/maps/omap_nor.c
+++ b/drivers/mtd/maps/omap_nor.c
@@ -60,13 +60,22 @@ struct omapflash_info {
 static void omap_set_vpp(struct map_info *map, int enable)
 {
         static int      count;
-
-        if (enable) {
-                if (count++ == 0)
-                        OMAP_EMIFS_CONFIG_REG |= OMAP_EMIFS_CONFIG_WP;
-        } else {
-                if (count && (--count == 0))
-                        OMAP_EMIFS_CONFIG_REG &= ~OMAP_EMIFS_CONFIG_WP;
+        u32 l;
+
+        if (cpu_class_is_omap1()) {
+                if (enable) {
+                        if (count++ == 0) {
+                                l = omap_readl(EMIFS_CONFIG);
+                                l |= OMAP_EMIFS_CONFIG_WP;
+                                omap_writel(l, EMIFS_CONFIG);
+                        }
+                } else {
+                        if (count && (--count == 0)) {
+                                l = omap_readl(EMIFS_CONFIG);
+                                l &= ~OMAP_EMIFS_CONFIG_WP;
+                                omap_writel(l, EMIFS_CONFIG);
+                        }
+                }
         }
 }
 
diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
index 59e05a1c50cf..ee2ac3948cd8 100644
--- a/drivers/mtd/nand/orion_nand.c
+++ b/drivers/mtd/nand/orion_nand.c
@@ -85,6 +85,9 @@ static int __init orion_nand_probe(struct platform_device *pdev)
         nc->cmd_ctrl = orion_nand_cmd_ctrl;
         nc->ecc.mode = NAND_ECC_SOFT;
 
+        if (board->chip_delay)
+                nc->chip_delay = board->chip_delay;
+
         if (board->width == 16)
                 nc->options |= NAND_BUSWIDTH_16;
 
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index f4182cfffe9d..45a41b597da9 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -217,7 +217,7 @@ config MII
 
 config MACB
         tristate "Atmel MACB support"
-        depends on AVR32 || ARCH_AT91SAM9260 || ARCH_AT91SAM9263 || ARCH_AT91CAP9
+        depends on AVR32 || ARCH_AT91SAM9260 || ARCH_AT91SAM9263 || ARCH_AT91SAM9G20 || ARCH_AT91CAP9
         select PHYLIB
         help
           The Atmel MACB ethernet interface is found on many AT32 and AT91
diff --git a/drivers/net/arm/etherh.c b/drivers/net/arm/etherh.c
index 00081d2b9cd5..e9d15eccad08 100644
--- a/drivers/net/arm/etherh.c
+++ b/drivers/net/arm/etherh.c
@@ -647,7 +647,7 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id)
         struct ei_device *ei_local;
         struct net_device *dev;
         struct etherh_priv *eh;
-        int i, ret;
+        int ret;
         DECLARE_MAC_BUF(mac);
 
         etherh_banner();
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index d5c2d27f3ea4..f76b0b6c277d 100644
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -13,16 +13,8 @@
  *
  */
 #include <linux/module.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/errno.h>
 #include <linux/netdevice.h>
-#include <linux/slab.h>
-#include <linux/rtnetlink.h>
-#include <linux/interrupt.h>
-#include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
-#include <linux/pm.h>
 #include <linux/clk.h>
 
 #include <net/irda/irda.h>
@@ -30,17 +22,9 @@
 #include <net/irda/wrapper.h>
 #include <net/irda/irda_device.h>
 
-#include <asm/irq.h>
 #include <asm/dma.h>
-#include <asm/delay.h>
-#include <asm/hardware.h>
 #include <asm/arch/irda.h>
 #include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-
-#ifdef CONFIG_MACH_MAINSTONE
-#include <asm/arch/mainstone.h>
-#endif
 
 #define IrSR_RXPL_NEG_IS_ZERO (1<<4)
 #define IrSR_RXPL_POS_IS_ZERO 0x0
@@ -163,10 +147,6 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
                         /* set board transceiver to SIR mode */
                         si->pdata->transceiver_mode(si->dev, IR_SIRMODE);
 
-                        /* configure GPIO46/47 */
-                        pxa_gpio_mode(GPIO46_STRXD_MD);
-                        pxa_gpio_mode(GPIO47_STTXD_MD);
-
                         /* enable the STUART clock */
                         pxa_irda_enable_sirclk(si);
                 }
@@ -201,10 +181,6 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
                 /* set board transceiver to FIR mode */
                 si->pdata->transceiver_mode(si->dev, IR_FIRMODE);
 
-                /* configure GPIO46/47 */
-                pxa_gpio_mode(GPIO46_ICPRXD_MD);
-                pxa_gpio_mode(GPIO47_ICPTXD_MD);
-
                 /* enable the FICP clock */
                 pxa_irda_enable_firclk(si);
 
diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c
index 46314b420765..569b746b5731 100644
--- a/drivers/pcmcia/omap_cf.c
+++ b/drivers/pcmcia/omap_cf.c
@@ -38,19 +38,19 @@
 #define CF_BASE 0xfffe2800
 
 /* status; read after IRQ */
-#define CF_STATUS_REG           __REG16(CF_BASE + 0x00)
+#define CF_STATUS                       (CF_BASE + 0x00)
 #       define  CF_STATUS_BAD_READ      (1 << 2)
 #       define  CF_STATUS_BAD_WRITE     (1 << 1)
 #       define  CF_STATUS_CARD_DETECT   (1 << 0)
 
 /* which chipselect (CS0..CS3) is used for CF (active low) */
-#define CF_CFG_REG              __REG16(CF_BASE + 0x02)
+#define CF_CFG                          (CF_BASE + 0x02)
 
 /* card reset */
-#define CF_CONTROL_REG          __REG16(CF_BASE + 0x04)
+#define CF_CONTROL                      (CF_BASE + 0x04)
 #       define  CF_CONTROL_RESET        (1 << 0)
 
-#define omap_cf_present() (!(CF_STATUS_REG & CF_STATUS_CARD_DETECT))
+#define omap_cf_present() (!(omap_readw(CF_STATUS) & CF_STATUS_CARD_DETECT))
 
 /*--------------------------------------------------------------------------*/
 
@@ -139,11 +139,11 @@ omap_cf_set_socket(struct pcmcia_socket *sock, struct socket_state_t *s)
                 return -EINVAL;
         }
 
-        control = CF_CONTROL_REG;
+        control = omap_readw(CF_CONTROL);
         if (s->flags & SS_RESET)
-                CF_CONTROL_REG = CF_CONTROL_RESET;
+                omap_writew(CF_CONTROL_RESET, CF_CONTROL);
         else
-                CF_CONTROL_REG = 0;
+                omap_writew(0, CF_CONTROL);
 
         pr_debug("%s: Vcc %d, io_irq %d, flags %04x csc %04x\n",
                 driver_name, s->Vcc, s->io_irq, s->flags, s->csc_mask);
@@ -270,7 +270,7 @@ static int __init omap_cf_probe(struct platform_device *pdev)
         omap_cfg_reg(V10_1610_CF_IREQ);
         omap_cfg_reg(W10_1610_CF_RESET);
 
-        CF_CFG_REG = ~(1 << seg);
+        omap_writew(~(1 << seg), CF_CFG);
 
         pr_info("%s: cs%d on irq %d\n", driver_name, seg, irq);
 
@@ -279,14 +279,15 @@ static int __init omap_cf_probe(struct platform_device *pdev)
          * CF/PCMCIA variants...
          */
         pr_debug("%s: cs%d, previous ccs %08x acs %08x\n", driver_name,
-                        seg, EMIFS_CCS(seg), EMIFS_ACS(seg));
-        EMIFS_CCS(seg) = 0x0004a1b3;    /* synch mode 4 etc */
-        EMIFS_ACS(seg) = 0x00000000;    /* OE hold/setup */
+                seg, omap_readl(EMIFS_CCS(seg)), omap_readl(EMIFS_ACS(seg)));
+        omap_writel(0x0004a1b3, EMIFS_CCS(seg));        /* synch mode 4 etc */
+        omap_writel(0x00000000, EMIFS_ACS(seg));        /* OE hold/setup */
 
         /* CF uses armxor_ck, which is "always" available */
 
         pr_debug("%s: sts %04x cfg %04x control %04x %s\n", driver_name,
-                CF_STATUS_REG, CF_CFG_REG, CF_CONTROL_REG,
+                omap_readw(CF_STATUS), omap_readw(CF_CFG),
+                omap_readw(CF_CONTROL),
                 omap_cf_present() ? "present" : "(not present)");
 
         cf->socket.owner = THIS_MODULE;
diff --git a/drivers/pcmcia/pxa2xx_cm_x270.c b/drivers/pcmcia/pxa2xx_cm_x270.c
index e7ab060ff118..f123fce65f2e 100644
--- a/drivers/pcmcia/pxa2xx_cm_x270.c
+++ b/drivers/pcmcia/pxa2xx_cm_x270.c
@@ -18,6 +18,7 @@
 
 #include <pcmcia/ss.h>
 #include <asm/hardware.h>
+#include <asm/mach-types.h>
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-gpio.h>
@@ -130,7 +131,7 @@ static void cmx270_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
 }
 
 
-static struct pcmcia_low_level cmx270_pcmcia_ops = {
+static struct pcmcia_low_level cmx270_pcmcia_ops __initdata = {
         .owner                  = THIS_MODULE,
         .hw_init                = cmx270_pcmcia_hw_init,
         .hw_shutdown            = cmx270_pcmcia_shutdown,
@@ -147,15 +148,21 @@ static int __init cmx270_pcmcia_init(void)
 {
         int ret;
 
+        if (!machine_is_armcore())
+                return -ENODEV;
+
         cmx270_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
 
         if (!cmx270_pcmcia_device)
                 return -ENOMEM;
 
-        cmx270_pcmcia_device->dev.platform_data = &cmx270_pcmcia_ops;
+        ret = platform_device_add_data(cmx270_pcmcia_device, &cmx270_pcmcia_ops,
+                                       sizeof(cmx270_pcmcia_ops));
 
-        printk(KERN_INFO "Registering cm-x270 PCMCIA interface.\n");
-        ret = platform_device_add(cmx270_pcmcia_device);
+        if (ret == 0) {
+                printk(KERN_INFO "Registering cm-x270 PCMCIA interface.\n");
+                ret = platform_device_add(cmx270_pcmcia_device);
+        }
 
         if (ret)
                 platform_device_put(cmx270_pcmcia_device);
diff --git a/drivers/pcmcia/pxa2xx_mainstone.c b/drivers/pcmcia/pxa2xx_mainstone.c
index 145b85e0f02c..92d1cc33808c 100644
--- a/drivers/pcmcia/pxa2xx_mainstone.c
+++ b/drivers/pcmcia/pxa2xx_mainstone.c
@@ -22,6 +22,7 @@
 #include <pcmcia/ss.h>
 
 #include <asm/hardware.h>
+#include <asm/mach-types.h>
 #include <asm/irq.h>
 
 #include <asm/arch/pxa-regs.h>
@@ -136,7 +137,7 @@ static void mst_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
 {
 }
 
-static struct pcmcia_low_level mst_pcmcia_ops = {
+static struct pcmcia_low_level mst_pcmcia_ops __initdata = {
         .owner                  = THIS_MODULE,
         .hw_init                = mst_pcmcia_hw_init,
         .hw_shutdown            = mst_pcmcia_hw_shutdown,
@@ -153,13 +154,17 @@ static int __init mst_pcmcia_init(void)
 {
         int ret;
 
+        if (!machine_is_mainstone())
+                return -ENODEV;
+
         mst_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
         if (!mst_pcmcia_device)
                 return -ENOMEM;
 
-        mst_pcmcia_device->dev.platform_data = &mst_pcmcia_ops;
-
-        ret = platform_device_add(mst_pcmcia_device);
+        ret = platform_device_add_data(mst_pcmcia_device, &mst_pcmcia_ops,
+                                       sizeof(mst_pcmcia_ops));
+        if (ret == 0)
+                ret = platform_device_add(mst_pcmcia_device);
 
         if (ret)
                 platform_device_put(mst_pcmcia_device);
diff --git a/drivers/pcmcia/pxa2xx_sharpsl.c b/drivers/pcmcia/pxa2xx_sharpsl.c
index d5c33bd78d68..d71f93d45833 100644
--- a/drivers/pcmcia/pxa2xx_sharpsl.c
+++ b/drivers/pcmcia/pxa2xx_sharpsl.c
@@ -222,7 +222,7 @@ static void sharpsl_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
         sharpsl_pcmcia_init_reset(skt);
 }
 
-static struct pcmcia_low_level sharpsl_pcmcia_ops = {
+static struct pcmcia_low_level sharpsl_pcmcia_ops __initdata = {
         .owner                  = THIS_MODULE,
         .hw_init                = sharpsl_pcmcia_hw_init,
         .hw_shutdown            = sharpsl_pcmcia_hw_shutdown,
@@ -261,10 +261,12 @@ static int __init sharpsl_pcmcia_init(void)
         if (!sharpsl_pcmcia_device)
                 return -ENOMEM;
 
-        sharpsl_pcmcia_device->dev.platform_data = &sharpsl_pcmcia_ops;
-        sharpsl_pcmcia_device->dev.parent = platform_scoop_config->devs[0].dev;
-
-        ret = platform_device_add(sharpsl_pcmcia_device);
+        ret = platform_device_add_data(sharpsl_pcmcia_device,
+                        &sharpsl_pcmcia_ops, sizeof(sharpsl_pcmcia_ops));
+        if (ret == 0) {
+                sharpsl_pcmcia_device->dev.parent = platform_scoop_config->devs[0].dev;
+                ret = platform_device_add(sharpsl_pcmcia_device);
+        }
 
         if (ret)
                 platform_device_put(sharpsl_pcmcia_device);
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 4949dc4859be..fc85bf2e4a97 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -469,6 +469,16 @@ config RTC_DRV_VR41XX
           To compile this driver as a module, choose M here: the
           module will be called rtc-vr41xx.
 
+config RTC_DRV_PL030
+        tristate "ARM AMBA PL030 RTC"
+        depends on ARM_AMBA
+        help
+          If you say Y here you will get access to ARM AMBA
+          PrimeCell PL030 RTC found on certain ARM SOCs.
+
+          To compile this driver as a module, choose M here: the
+          module will be called rtc-pl030.
+
 config RTC_DRV_PL031
         tristate "ARM AMBA PL031 RTC"
         depends on ARM_AMBA
@@ -495,12 +505,13 @@ config RTC_DRV_AT91RM9200
           this is powered by the backup power supply.
 
 config RTC_DRV_AT91SAM9
-        tristate "AT91SAM9x"
+        tristate "AT91SAM9x/AT91CAP9"
         depends on ARCH_AT91 && !(ARCH_AT91RM9200 || ARCH_AT91X40)
         help
-          RTC driver for the Atmel AT91SAM9x internal RTT (Real Time Timer).
-          These timers are powered by the backup power supply (such as a
-          small coin cell battery), but do not need to be used as RTCs.
+          RTC driver for the Atmel AT91SAM9x and AT91CAP9 internal RTT
+          (Real Time Timer). These timers are powered by the backup power
+          supply (such as a small coin cell battery), but do not need to
+          be used as RTCs.
 
           (On AT91SAM9rl chips you probably want to use the dedicated RTC
           module and leave the RTT available for other uses.)
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index b6e14d51670b..b5d9d67df887 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_RTC_DRV_MAX6902)	+= rtc-max6902.o
 obj-$(CONFIG_RTC_DRV_OMAP)      += rtc-omap.o
 obj-$(CONFIG_RTC_DRV_PCF8563)   += rtc-pcf8563.o
 obj-$(CONFIG_RTC_DRV_PCF8583)   += rtc-pcf8583.o
+obj-$(CONFIG_RTC_DRV_PL030)     += rtc-pl030.o
 obj-$(CONFIG_RTC_DRV_PL031)     += rtc-pl031.o
 obj-$(CONFIG_RTC_DRV_PPC)       += rtc-ppc.o
 obj-$(CONFIG_RTC_DRV_R9701)     += rtc-r9701.o
diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
index 39e64ab1ecb7..9c3db934cc24 100644
--- a/drivers/rtc/rtc-at91rm9200.c
+++ b/drivers/rtc/rtc-at91rm9200.c
@@ -29,10 +29,6 @@
 #include <linux/completion.h>
 
 #include <asm/uaccess.h>
-#include <asm/rtc.h>
-
-#include <asm/mach/time.h>
-
 #include <asm/arch/at91_rtc.h>
 
 
diff --git a/drivers/rtc/rtc-at91sam9.c b/drivers/rtc/rtc-at91sam9.c
index 38d8742a4bdf..f0246ef413a4 100644
--- a/drivers/rtc/rtc-at91sam9.c
+++ b/drivers/rtc/rtc-at91sam9.c
@@ -19,7 +19,6 @@
 #include <linux/interrupt.h>
 #include <linux/ioctl.h>
 
-#include <asm/mach/time.h>
 #include <asm/arch/board.h>
 #include <asm/arch/at91_rtt.h>
 
diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
index 58f81c774943..eb23d8423f42 100644
--- a/drivers/rtc/rtc-omap.c
+++ b/drivers/rtc/rtc-omap.c
@@ -22,7 +22,6 @@
 #include <linux/platform_device.h>
 
 #include <asm/io.h>
-#include <asm/mach/time.h>
 
 
 /* The OMAP1 RTC is a year/month/day/hours/minutes/seconds BCD clock
diff --git a/drivers/rtc/rtc-pl030.c b/drivers/rtc/rtc-pl030.c
new file mode 100644
index 000000000000..8448eeb9d675
--- /dev/null
+++ b/drivers/rtc/rtc-pl030.c
@@ -0,0 +1,217 @@
+/*
+ *  linux/drivers/rtc/rtc-pl030.c
+ *
+ *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/rtc.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/amba/bus.h>
+#include <linux/io.h>
+
+#define RTC_DR          (0)
+#define RTC_MR          (4)
+#define RTC_STAT        (8)
+#define RTC_EOI         (8)
+#define RTC_LR          (12)
+#define RTC_CR          (16)
+#define RTC_CR_MIE      (1 << 0)
+
+struct pl030_rtc {
+        struct rtc_device       *rtc;
+        void __iomem            *base;
+};
+
+static irqreturn_t pl030_interrupt(int irq, void *dev_id)
+{
+        struct pl030_rtc *rtc = dev_id;
+        writel(0, rtc->base + RTC_EOI);
+        return IRQ_HANDLED;
+}
+
+static int pl030_open(struct device *dev)
+{
+        return 0;
+}
+
+static void pl030_release(struct device *dev)
+{
+}
+
+static int pl030_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
+{
+        return -ENOIOCTLCMD;
+}
+
+static int pl030_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+        struct pl030_rtc *rtc = dev_get_drvdata(dev);
+
+        rtc_time_to_tm(readl(rtc->base + RTC_MR), &alrm->time);
+        return 0;
+}
+
+static int pl030_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+        struct pl030_rtc *rtc = dev_get_drvdata(dev);
+        unsigned long time;
+        int ret;
+
+        /*
+         * At the moment, we can only deal with non-wildcarded alarm times.
+         */
+        ret = rtc_valid_tm(&alrm->time);
+        if (ret == 0)
+                ret = rtc_tm_to_time(&alrm->time, &time);
+        if (ret == 0)
+                writel(time, rtc->base + RTC_MR);
+        return ret;
+}
+
+static int pl030_read_time(struct device *dev, struct rtc_time *tm)
+{
+        struct pl030_rtc *rtc = dev_get_drvdata(dev);
+
+        rtc_time_to_tm(readl(rtc->base + RTC_DR), tm);
+
+        return 0;
+}
+
+/*
+ * Set the RTC time.  Unfortunately, we can't accurately set
+ * the point at which the counter updates.
+ *
+ * Also, since RTC_LR is transferred to RTC_CR on next rising
+ * edge of the 1Hz clock, we must write the time one second
+ * in advance.
+ */
+static int pl030_set_time(struct device *dev, struct rtc_time *tm)
+{
+        struct pl030_rtc *rtc = dev_get_drvdata(dev);
+        unsigned long time;
+        int ret;
+
+        ret = rtc_tm_to_time(tm, &time);
+        if (ret == 0)
+                writel(time + 1, rtc->base + RTC_LR);
+
+        return ret;
+}
+
+static const struct rtc_class_ops pl030_ops = {
+        .open           = pl030_open,
+        .release        = pl030_release,
+        .ioctl          = pl030_ioctl,
+        .read_time      = pl030_read_time,
+        .set_time       = pl030_set_time,
+        .read_alarm     = pl030_read_alarm,
+        .set_alarm      = pl030_set_alarm,
+};
+
+static int pl030_probe(struct amba_device *dev, void *id)
+{
+        struct pl030_rtc *rtc;
+        int ret;
+
+        ret = amba_request_regions(dev, NULL);
+        if (ret)
+                goto err_req;
+
+        rtc = kmalloc(sizeof(*rtc), GFP_KERNEL);
+        if (!rtc) {
+                ret = -ENOMEM;
+                goto err_rtc;
+        }
+
+        rtc->base = ioremap(dev->res.start, SZ_4K);
+        if (!rtc->base) {
+                ret = -ENOMEM;
+                goto err_map;
+        }
+
+        __raw_writel(0, rtc->base + RTC_CR);
+        __raw_writel(0, rtc->base + RTC_EOI);
+
+        amba_set_drvdata(dev, rtc);
+
+        ret = request_irq(dev->irq[0], pl030_interrupt, IRQF_DISABLED,
+                          "rtc-pl030", rtc);
+        if (ret)
+                goto err_irq;
+
+        rtc->rtc = rtc_device_register("pl030", &dev->dev, &pl030_ops,
+                                       THIS_MODULE);
+        if (IS_ERR(rtc->rtc)) {
+                ret = PTR_ERR(rtc->rtc);
+                goto err_reg;
+        }
+
+        return 0;
+
+ err_reg:
+        free_irq(dev->irq[0], rtc);
+ err_irq:
+        iounmap(rtc->base);
+ err_map:
+        kfree(rtc);
+ err_rtc:
+        amba_release_regions(dev);
+ err_req:
+        return ret;
+}
+
+static int pl030_remove(struct amba_device *dev)
+{
+        struct pl030_rtc *rtc = amba_get_drvdata(dev);
+
+        amba_set_drvdata(dev, NULL);
+
+        writel(0, rtc->base + RTC_CR);
+
+        free_irq(dev->irq[0], rtc);
+        rtc_device_unregister(rtc->rtc);
+        iounmap(rtc->base);
+        kfree(rtc);
+        amba_release_regions(dev);
+
+        return 0;
+}
+
+static struct amba_id pl030_ids[] = {
+        {
+                .id     = 0x00041030,
+                .mask   = 0x000fffff,
+        },
+        { 0, 0 },
+};
+
+static struct amba_driver pl030_driver = {
+        .drv            = {
+                .name   = "rtc-pl030",
+        },
+        .probe          = pl030_probe,
+        .remove         = pl030_remove,
+        .id_table       = pl030_ids,
+};
+
+static int __init pl030_init(void)
+{
+        return amba_driver_register(&pl030_driver);
+}
+
+static void __exit pl030_exit(void)
+{
+        amba_driver_unregister(&pl030_driver);
+}
+
+module_init(pl030_init);
+module_exit(pl030_exit);
+
+MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
+MODULE_DESCRIPTION("ARM AMBA PL030 RTC Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-pl031.c b/drivers/rtc/rtc-pl031.c
index 2fd49edcc712..08b4610ec5a6 100644
--- a/drivers/rtc/rtc-pl031.c
+++ b/drivers/rtc/rtc-pl031.c
@@ -12,23 +12,12 @@
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
  */
-
-#include <linux/platform_device.h>
 #include <linux/module.h>
 #include <linux/rtc.h>
 #include <linux/init.h>
-#include <linux/fs.h>
 #include <linux/interrupt.h>
-#include <linux/string.h>
-#include <linux/pm.h>
-#include <linux/bitops.h>
-
 #include <linux/amba/bus.h>
-
-#include <asm/io.h>
-#include <asm/hardware.h>
-#include <asm/irq.h>
-#include <asm/rtc.h>
+#include <linux/io.h>
 
 /*
  * Register definitions
@@ -142,13 +131,12 @@ static int pl031_remove(struct amba_device *adev)
 {
         struct pl031_local *ldata = dev_get_drvdata(&adev->dev);
 
-        if (ldata) {
-                dev_set_drvdata(&adev->dev, NULL);
-                free_irq(adev->irq[0], ldata->rtc);
-                rtc_device_unregister(ldata->rtc);
-                iounmap(ldata->base);
-                kfree(ldata);
-        }
+        amba_set_drvdata(adev, NULL);
+        free_irq(adev->irq[0], ldata->rtc);
+        rtc_device_unregister(ldata->rtc);
+        iounmap(ldata->base);
+        kfree(ldata);
+        amba_release_regions(adev);
 
         return 0;
 }
@@ -158,13 +146,15 @@ static int pl031_probe(struct amba_device *adev, void *id)
         int ret;
         struct pl031_local *ldata;
 
+        ret = amba_request_regions(adev, NULL);
+        if (ret)
+                goto err_req;
 
         ldata = kmalloc(sizeof(struct pl031_local), GFP_KERNEL);
         if (!ldata) {
                 ret = -ENOMEM;
                 goto out;
         }
-        dev_set_drvdata(&adev->dev, ldata);
 
         ldata->base = ioremap(adev->res.start,
                               adev->res.end - adev->res.start + 1);
@@ -173,6 +163,8 @@ static int pl031_probe(struct amba_device *adev, void *id)
                 goto out_no_remap;
         }
 
+        amba_set_drvdata(adev, ldata);
+
         if (request_irq(adev->irq[0], pl031_interrupt, IRQF_DISABLED,
                         "rtc-pl031", ldata->rtc)) {
                 ret = -EIO;
@@ -192,10 +184,12 @@ out_no_rtc:
         free_irq(adev->irq[0], ldata->rtc);
 out_no_irq:
         iounmap(ldata->base);
+        amba_set_drvdata(adev, NULL);
 out_no_remap:
-        dev_set_drvdata(&adev->dev, NULL);
         kfree(ldata);
 out:
+        amba_release_regions(adev);
+err_req:
         return ret;
 }
 
diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
index f26e0cad8f16..fed86e507fdf 100644
--- a/drivers/rtc/rtc-s3c.c
+++ b/drivers/rtc/rtc-s3c.c
@@ -26,10 +26,6 @@
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/rtc.h>
-
-#include <asm/mach/time.h>
-
 #include <asm/plat-s3c/regs-rtc.h>
 
 /* I have yet to find an S3C implementation with more than one
diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c
index 67421b0d3a7b..f47294c60148 100644
--- a/drivers/rtc/rtc-sa1100.c
+++ b/drivers/rtc/rtc-sa1100.c
@@ -33,7 +33,6 @@
 
 #include <asm/hardware.h>
 #include <asm/irq.h>
-#include <asm/rtc.h>
 
 #ifdef CONFIG_ARCH_PXA
 #include <asm/arch/pxa-regs.h>
@@ -47,6 +46,42 @@ static unsigned long rtc_freq = 1024;
 static struct rtc_time rtc_alarm;
 static DEFINE_SPINLOCK(sa1100_rtc_lock);
 
+static inline int rtc_periodic_alarm(struct rtc_time *tm)
+{
+        return  (tm->tm_year == -1) ||
+                ((unsigned)tm->tm_mon >= 12) ||
+                ((unsigned)(tm->tm_mday - 1) >= 31) ||
+                ((unsigned)tm->tm_hour > 23) ||
+                ((unsigned)tm->tm_min > 59) ||
+                ((unsigned)tm->tm_sec > 59);
+}
+
+/*
+ * Calculate the next alarm time given the requested alarm time mask
+ * and the current time.
+ */
+static void rtc_next_alarm_time(struct rtc_time *next, struct rtc_time *now, struct rtc_time *alrm)
+{
+        unsigned long next_time;
+        unsigned long now_time;
+
+        next->tm_year = now->tm_year;
+        next->tm_mon = now->tm_mon;
+        next->tm_mday = now->tm_mday;
+        next->tm_hour = alrm->tm_hour;
+        next->tm_min = alrm->tm_min;
+        next->tm_sec = alrm->tm_sec;
+
+        rtc_tm_to_time(now, &now_time);
+        rtc_tm_to_time(next, &next_time);
+
+        if (next_time < now_time) {
+                /* Advance one day */
+                next_time += 60 * 60 * 24;
+                rtc_time_to_tm(next_time, next);
+        }
+}
+
 static int rtc_update_alarm(struct rtc_time *alrm)
 {
         struct rtc_time alarm_tm, now_tm;
diff --git a/drivers/scsi/arm/Kconfig b/drivers/scsi/arm/Kconfig
index 7236143941f3..a8587f1f5e7e 100644
--- a/drivers/scsi/arm/Kconfig
+++ b/drivers/scsi/arm/Kconfig
@@ -3,7 +3,7 @@
 #
 config SCSI_ACORNSCSI_3
         tristate "Acorn SCSI card (aka30) support"
-        depends on ARCH_ACORN && SCSI && BROKEN
+        depends on ARCH_ACORN && SCSI
         select SCSI_SPI_ATTRS
         help
           This enables support for the Acorn SCSI card (aka30). If you have an
diff --git a/drivers/scsi/arm/acornscsi-io.S b/drivers/scsi/arm/acornscsi-io.S
index 93467e6ac923..5cebe3105260 100644
--- a/drivers/scsi/arm/acornscsi-io.S
+++ b/drivers/scsi/arm/acornscsi-io.S
@@ -10,17 +10,10 @@
 #include <asm/assembler.h>
 #include <asm/hardware.h>
 
-#if (IO_BASE == (PCIO_BASE & 0xff000000))
-#define ADDR(off,reg)                                           \
-                tst     off, $0x80000000                        ;\
-                mov     reg, $IO_BASE                           ;\
-                orreq   reg, reg, $(PCIO_BASE & 0x00ff0000)
-#else
-#define ADDR(off,reg)                                           \
-                tst     off, $0x80000000                        ;\
-                movne   reg, $IO_BASE                           ;\
-                moveq   reg, $(PCIO_BASE & 0xff000000)          ;\
-                orreq   reg, reg, $(PCIO_BASE & 0x00ff0000)
+#if defined(__APCS_32__)
+#define LOADREGS(t,r,l...)      ldm##t  r, l
+#elif defined(__APCS_26__)
+#define LOADREGS(t,r,l...)      ldm##t  r, l##^
 #endif
 
 @ Purpose: transfer a block of data from the acorn scsi card to memory
diff --git a/drivers/scsi/arm/acornscsi.c b/drivers/scsi/arm/acornscsi.c
index 8e53f02cc311..918ccf818757 100644
--- a/drivers/scsi/arm/acornscsi.c
+++ b/drivers/scsi/arm/acornscsi.c
@@ -123,12 +123,6 @@
 #define DBG(cmd,xxx...) xxx
 #endif
 
-#ifndef STRINGIFY
-#define STRINGIFY(x) #x
-#endif
-#define STRx(x) STRINGIFY(x)
-#define NO_WRITE_STR STRx(NO_WRITE)
-
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/string.h>
@@ -141,9 +135,10 @@
 #include <linux/interrupt.h>
 #include <linux/init.h>
 #include <linux/bitops.h>
+#include <linux/stringify.h>
+#include <linux/io.h>
 
 #include <asm/system.h>
-#include <asm/io.h>
 #include <asm/ecard.h>
 
 #include "../scsi.h"
@@ -203,44 +198,46 @@ static void acornscsi_abortcmd(AS_Host *host, unsigned char tag);
  * Miscellaneous
  */
 
-static inline void
-sbic_arm_write(unsigned int io_port, int reg, int value)
+/* Offsets from MEMC base */
+#define SBIC_REGIDX     0x2000
+#define SBIC_REGVAL     0x2004
+#define DMAC_OFFSET     0x3000
+
+/* Offsets from FAST IOC base */
+#define INT_REG         0x2000
+#define PAGE_REG        0x3000
+
+static inline void sbic_arm_write(AS_Host *host, unsigned int reg, unsigned int value)
 {
-    __raw_writeb(reg, io_port);
-    __raw_writeb(value, io_port + 4);
+    writeb(reg, host->base + SBIC_REGIDX);
+    writeb(value, host->base + SBIC_REGVAL);
 }
 
-#define sbic_arm_writenext(io,val) \
-        __raw_writeb((val), (io) + 4)
-
-static inline
-int sbic_arm_read(unsigned int io_port, int reg)
+static inline int sbic_arm_read(AS_Host *host, unsigned int reg)
 {
     if(reg == SBIC_ASR)
-           return __raw_readl(io_port) & 255;
-    __raw_writeb(reg, io_port);
-    return __raw_readl(io_port + 4) & 255;
+           return readl(host->base + SBIC_REGIDX) & 255;
+    writeb(reg, host->base + SBIC_REGIDX);
+    return readl(host->base + SBIC_REGVAL) & 255;
 }
 
-#define sbic_arm_readnext(io) \
-        __raw_readb((io) + 4)
+#define sbic_arm_writenext(host, val)   writeb((val), (host)->base + SBIC_REGVAL)
+#define sbic_arm_readnext(host)         readb((host)->base + SBIC_REGVAL)
 
 #ifdef USE_DMAC
-#define dmac_read(io_port,reg) \
-        inb((io_port) + (reg))
+#define dmac_read(host,reg) \
+        readb((host)->base + DMAC_OFFSET + ((reg) << 2))
 
-#define dmac_write(io_port,reg,value) \
-        ({ outb((value), (io_port) + (reg)); })
+#define dmac_write(host,reg,value) \
+        ({ writeb((value), (host)->base + DMAC_OFFSET + ((reg) << 2)); })
 
-#define dmac_clearintr(io_port) \
-        ({ outb(0, (io_port)); })
+#define dmac_clearintr(host)    writeb(0, (host)->fast + INT_REG)
 
-static inline
-unsigned int dmac_address(unsigned int io_port)
+static inline unsigned int dmac_address(AS_Host *host)
 {
-    return dmac_read(io_port, DMAC_TXADRHI) << 16 |
-           dmac_read(io_port, DMAC_TXADRMD) << 8 |
-           dmac_read(io_port, DMAC_TXADRLO);
+    return dmac_read(host, DMAC_TXADRHI) << 16 |
+           dmac_read(host, DMAC_TXADRMD) << 8 |
+           dmac_read(host, DMAC_TXADRLO);
 }
 
 static
@@ -248,15 +245,15 @@ void acornscsi_dumpdma(AS_Host *host, char *where)
 {
         unsigned int mode, addr, len;
 
-        mode = dmac_read(host->dma.io_port, DMAC_MODECON);
-        addr = dmac_address(host->dma.io_port);
-        len  = dmac_read(host->dma.io_port, DMAC_TXCNTHI) << 8 |
-               dmac_read(host->dma.io_port, DMAC_TXCNTLO);
+        mode = dmac_read(host, DMAC_MODECON);
+        addr = dmac_address(host);
+        len  = dmac_read(host, DMAC_TXCNTHI) << 8 |
+               dmac_read(host, DMAC_TXCNTLO);
 
         printk("scsi%d: %s: DMAC %02x @%06x+%04x msk %02x, ",
                 host->host->host_no, where,
                 mode, addr, (len + 1) & 0xffff,
-                dmac_read(host->dma.io_port, DMAC_MASKREG));
+                dmac_read(host, DMAC_MASKREG));
 
         printk("DMA @%06x, ", host->dma.start_addr);
         printk("BH @%p +%04x, ", host->scsi.SCp.ptr,
@@ -272,9 +269,9 @@ unsigned long acornscsi_sbic_xfcount(AS_Host *host)
 {
     unsigned long length;
 
-    length = sbic_arm_read(host->scsi.io_port, SBIC_TRANSCNTH) << 16;
-    length |= sbic_arm_readnext(host->scsi.io_port) << 8;
-    length |= sbic_arm_readnext(host->scsi.io_port);
+    length = sbic_arm_read(host, SBIC_TRANSCNTH) << 16;
+    length |= sbic_arm_readnext(host) << 8;
+    length |= sbic_arm_readnext(host);
 
     return length;
 }
@@ -285,7 +282,7 @@ acornscsi_sbic_wait(AS_Host *host, int stat_mask, int stat, int timeout, char *m
         int asr;
 
         do {
-                asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR);
+                asr = sbic_arm_read(host, SBIC_ASR);
 
                 if ((asr & stat_mask) == stat)
                         return 0;
@@ -304,7 +301,7 @@ int acornscsi_sbic_issuecmd(AS_Host *host, int command)
     if (acornscsi_sbic_wait(host, ASR_CIP, 0, 1000, "issuing command"))
         return -1;
 
-    sbic_arm_write(host->scsi.io_port, SBIC_CMND, command);
+    sbic_arm_write(host, SBIC_CMND, command);
 
     return 0;
 }
@@ -331,20 +328,20 @@ void acornscsi_resetcard(AS_Host *host)
 
     /* assert reset line */
     host->card.page_reg = 0x80;
-    outb(host->card.page_reg, host->card.io_page);
+    writeb(host->card.page_reg, host->fast + PAGE_REG);
 
     /* wait 3 cs.  SCSI standard says 25ms. */
     acornscsi_csdelay(3);
 
     host->card.page_reg = 0;
-    outb(host->card.page_reg, host->card.io_page);
+    writeb(host->card.page_reg, host->fast + PAGE_REG);
 
     /*
      * Should get a reset from the card
      */
     timeout = 1000;
     do {
-        if (inb(host->card.io_intr) & 8)
+        if (readb(host->fast + INT_REG) & 8)
             break;
         udelay(1);
     } while (--timeout);
@@ -353,19 +350,19 @@ void acornscsi_resetcard(AS_Host *host)
         printk("scsi%d: timeout while resetting card\n",
                 host->host->host_no);
 
-    sbic_arm_read(host->scsi.io_port, SBIC_ASR);
-    sbic_arm_read(host->scsi.io_port, SBIC_SSR);
+    sbic_arm_read(host, SBIC_ASR);
+    sbic_arm_read(host, SBIC_SSR);
 
     /* setup sbic - WD33C93A */
-    sbic_arm_write(host->scsi.io_port, SBIC_OWNID, OWNID_EAF | host->host->this_id);
-    sbic_arm_write(host->scsi.io_port, SBIC_CMND, CMND_RESET);
+    sbic_arm_write(host, SBIC_OWNID, OWNID_EAF | host->host->this_id);
+    sbic_arm_write(host, SBIC_CMND, CMND_RESET);
 
     /*
      * Command should cause a reset interrupt
      */
     timeout = 1000;
     do {
-        if (inb(host->card.io_intr) & 8)
+        if (readb(host->fast + INT_REG) & 8)
             break;
         udelay(1);
     } while (--timeout);
@@ -374,26 +371,26 @@ void acornscsi_resetcard(AS_Host *host)
         printk("scsi%d: timeout while resetting card\n",
                 host->host->host_no);
 
-    sbic_arm_read(host->scsi.io_port, SBIC_ASR);
-    if (sbic_arm_read(host->scsi.io_port, SBIC_SSR) != 0x01)
+    sbic_arm_read(host, SBIC_ASR);
+    if (sbic_arm_read(host, SBIC_SSR) != 0x01)
         printk(KERN_CRIT "scsi%d: WD33C93A didn't give enhanced reset interrupt\n",
                 host->host->host_no);
 
-    sbic_arm_write(host->scsi.io_port, SBIC_CTRL, INIT_SBICDMA | CTRL_IDI);
-    sbic_arm_write(host->scsi.io_port, SBIC_TIMEOUT, TIMEOUT_TIME);
-    sbic_arm_write(host->scsi.io_port, SBIC_SYNCHTRANSFER, SYNCHTRANSFER_2DBA);
-    sbic_arm_write(host->scsi.io_port, SBIC_SOURCEID, SOURCEID_ER | SOURCEID_DSP);
+    sbic_arm_write(host, SBIC_CTRL, INIT_SBICDMA | CTRL_IDI);
+    sbic_arm_write(host, SBIC_TIMEOUT, TIMEOUT_TIME);
+    sbic_arm_write(host, SBIC_SYNCHTRANSFER, SYNCHTRANSFER_2DBA);
+    sbic_arm_write(host, SBIC_SOURCEID, SOURCEID_ER | SOURCEID_DSP);
 
     host->card.page_reg = 0x40;
-    outb(host->card.page_reg, host->card.io_page);
+    writeb(host->card.page_reg, host->fast + PAGE_REG);
 
     /* setup dmac - uPC71071 */
-    dmac_write(host->dma.io_port, DMAC_INIT, 0);
+    dmac_write(host, DMAC_INIT, 0);
 #ifdef USE_DMAC
-    dmac_write(host->dma.io_port, DMAC_INIT, INIT_8BIT);
-    dmac_write(host->dma.io_port, DMAC_CHANNEL, CHANNEL_0);
-    dmac_write(host->dma.io_port, DMAC_DEVCON0, INIT_DEVCON0);
-    dmac_write(host->dma.io_port, DMAC_DEVCON1, INIT_DEVCON1);
+    dmac_write(host, DMAC_INIT, INIT_8BIT);
+    dmac_write(host, DMAC_CHANNEL, CHANNEL_0);
+    dmac_write(host, DMAC_DEVCON0, INIT_DEVCON0);
+    dmac_write(host, DMAC_DEVCON1, INIT_DEVCON1);
 #endif
 
     host->SCpnt = NULL;
@@ -741,9 +738,9 @@ intr_ret_t acornscsi_kick(AS_Host *host)
      * If we have an interrupt pending, then we may have been reselected.
      * In this case, we don't want to write to the registers
      */
-    if (!(sbic_arm_read(host->scsi.io_port, SBIC_ASR) & (ASR_INT|ASR_BSY|ASR_CIP))) {
-        sbic_arm_write(host->scsi.io_port, SBIC_DESTID, SCpnt->device->id);
-        sbic_arm_write(host->scsi.io_port, SBIC_CMND, CMND_SELWITHATN);
+    if (!(sbic_arm_read(host, SBIC_ASR) & (ASR_INT|ASR_BSY|ASR_CIP))) {
+        sbic_arm_write(host, SBIC_DESTID, SCpnt->device->id);
+        sbic_arm_write(host, SBIC_CMND, CMND_SELWITHATN);
     }
 
     /*
@@ -807,7 +804,7 @@ static void acornscsi_done(AS_Host *host, struct scsi_cmnd **SCpntp,
         struct scsi_cmnd *SCpnt = *SCpntp;
 
     /* clean up */
-    sbic_arm_write(host->scsi.io_port, SBIC_SOURCEID, SOURCEID_ER | SOURCEID_DSP);
+    sbic_arm_write(host, SBIC_SOURCEID, SOURCEID_ER | SOURCEID_DSP);
 
     host->stats.fins += 1;
 
@@ -918,13 +915,13 @@ static
 void acornscsi_data_read(AS_Host *host, char *ptr,
                                  unsigned int start_addr, unsigned int length)
 {
-    extern void __acornscsi_in(int port, char *buf, int len);
+    extern void __acornscsi_in(void __iomem *, char *buf, int len);
     unsigned int page, offset, len = length;
 
     page = (start_addr >> 12);
     offset = start_addr & ((1 << 12) - 1);
 
-    outb((page & 0x3f) | host->card.page_reg, host->card.io_page);
+    writeb((page & 0x3f) | host->card.page_reg, host->fast + PAGE_REG);
 
     while (len > 0) {
         unsigned int this_len;
@@ -934,7 +931,7 @@ void acornscsi_data_read(AS_Host *host, char *ptr,
         else
             this_len = len;
 
-        __acornscsi_in(host->card.io_ram + (offset << 1), ptr, this_len);
+        __acornscsi_in(host->base + (offset << 1), ptr, this_len);
 
         offset += this_len;
         ptr += this_len;
@@ -943,10 +940,10 @@ void acornscsi_data_read(AS_Host *host, char *ptr,
         if (offset == (1 << 12)) {
             offset = 0;
             page ++;
-            outb((page & 0x3f) | host->card.page_reg, host->card.io_page);
+            writeb((page & 0x3f) | host->card.page_reg, host->fast + PAGE_REG);
         }
     }
-    outb(host->card.page_reg, host->card.io_page);
+    writeb(host->card.page_reg, host->fast + PAGE_REG);
 }
 
 /*
@@ -963,13 +960,13 @@ static
 void acornscsi_data_write(AS_Host *host, char *ptr,
                                  unsigned int start_addr, unsigned int length)
 {
-    extern void __acornscsi_out(int port, char *buf, int len);
+    extern void __acornscsi_out(void __iomem *, char *buf, int len);
     unsigned int page, offset, len = length;
 
     page = (start_addr >> 12);
     offset = start_addr & ((1 << 12) - 1);
 
-    outb((page & 0x3f) | host->card.page_reg, host->card.io_page);
+    writeb((page & 0x3f) | host->card.page_reg, host->fast + PAGE_REG);
 
     while (len > 0) {
         unsigned int this_len;
@@ -979,7 +976,7 @@ void acornscsi_data_write(AS_Host *host, char *ptr,
         else
             this_len = len;
 
-        __acornscsi_out(host->card.io_ram + (offset << 1), ptr, this_len);
+        __acornscsi_out(host->base + (offset << 1), ptr, this_len);
 
         offset += this_len;
         ptr += this_len;
@@ -988,10 +985,10 @@ void acornscsi_data_write(AS_Host *host, char *ptr,
         if (offset == (1 << 12)) {
             offset = 0;
             page ++;
-            outb((page & 0x3f) | host->card.page_reg, host->card.io_page);
+            writeb((page & 0x3f) | host->card.page_reg, host->fast + PAGE_REG);
         }
     }
-    outb(host->card.page_reg, host->card.io_page);
+    writeb(host->card.page_reg, host->fast + PAGE_REG);
 }
 
 /* =========================================================================================
@@ -1008,8 +1005,8 @@ void acornscsi_data_write(AS_Host *host, char *ptr,
 static inline
 void acornscsi_dma_stop(AS_Host *host)
 {
-    dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_ON);
-    dmac_clearintr(host->dma.io_intr_clear);
+    dmac_write(host, DMAC_MASKREG, MASK_ON);
+    dmac_clearintr(host);
 
 #if (DEBUG & DEBUG_DMA)
     DBG(host->SCpnt, acornscsi_dumpdma(host, "stop"));
@@ -1031,7 +1028,7 @@ void acornscsi_dma_setup(AS_Host *host, dmadir_t direction)
 
     host->dma.direction = direction;
 
-    dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_ON);
+    dmac_write(host, DMAC_MASKREG, MASK_ON);
 
     if (direction == DMA_OUT) {
 #if (DEBUG & DEBUG_NO_WRITE)
@@ -1062,13 +1059,13 @@ void acornscsi_dma_setup(AS_Host *host, dmadir_t direction)
                                 length);
 
         length -= 1;
-        dmac_write(host->dma.io_port, DMAC_TXCNTLO, length);
-        dmac_write(host->dma.io_port, DMAC_TXCNTHI, length >> 8);
-        dmac_write(host->dma.io_port, DMAC_TXADRLO, address);
-        dmac_write(host->dma.io_port, DMAC_TXADRMD, address >> 8);
-        dmac_write(host->dma.io_port, DMAC_TXADRHI, 0);
-        dmac_write(host->dma.io_port, DMAC_MODECON, mode);
-        dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_OFF);
+        dmac_write(host, DMAC_TXCNTLO, length);
+        dmac_write(host, DMAC_TXCNTHI, length >> 8);
+        dmac_write(host, DMAC_TXADRLO, address);
+        dmac_write(host, DMAC_TXADRMD, address >> 8);
+        dmac_write(host, DMAC_TXADRHI, 0);
+        dmac_write(host, DMAC_MODECON, mode);
+        dmac_write(host, DMAC_MASKREG, MASK_OFF);
 
 #if (DEBUG & DEBUG_DMA)
         DBG(host->SCpnt, acornscsi_dumpdma(host, "strt"));
@@ -1088,8 +1085,8 @@ void acornscsi_dma_setup(AS_Host *host, dmadir_t direction)
 static
 void acornscsi_dma_cleanup(AS_Host *host)
 {
-    dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_ON);
-    dmac_clearintr(host->dma.io_intr_clear);
+    dmac_write(host, DMAC_MASKREG, MASK_ON);
+    dmac_clearintr(host);
 
     /*
      * Check for a pending transfer
@@ -1116,7 +1113,7 @@ void acornscsi_dma_cleanup(AS_Host *host)
         /*
          * Calculate number of bytes transferred from DMA.
          */
-        transferred = dmac_address(host->dma.io_port) - host->dma.start_addr;
+        transferred = dmac_address(host) - host->dma.start_addr;
         host->dma.transferred += transferred;
 
         if (host->dma.direction == DMA_IN)
@@ -1152,13 +1149,13 @@ void acornscsi_dma_intr(AS_Host *host)
     DBG(host->SCpnt, acornscsi_dumpdma(host, "inti"));
 #endif
 
-    dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_ON);
-    dmac_clearintr(host->dma.io_intr_clear);
+    dmac_write(host, DMAC_MASKREG, MASK_ON);
+    dmac_clearintr(host);
 
     /*
      * Calculate amount transferred via DMA
      */
-    transferred = dmac_address(host->dma.io_port) - host->dma.start_addr;
+    transferred = dmac_address(host) - host->dma.start_addr;
     host->dma.transferred += transferred;
 
     /*
@@ -1190,12 +1187,12 @@ void acornscsi_dma_intr(AS_Host *host)
                                 length);
 
         length -= 1;
-        dmac_write(host->dma.io_port, DMAC_TXCNTLO, length);
-        dmac_write(host->dma.io_port, DMAC_TXCNTHI, length >> 8);
-        dmac_write(host->dma.io_port, DMAC_TXADRLO, address);
-        dmac_write(host->dma.io_port, DMAC_TXADRMD, address >> 8);
-        dmac_write(host->dma.io_port, DMAC_TXADRHI, 0);
-        dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_OFF);
+        dmac_write(host, DMAC_TXCNTLO, length);
+        dmac_write(host, DMAC_TXCNTHI, length >> 8);
+        dmac_write(host, DMAC_TXADRLO, address);
+        dmac_write(host, DMAC_TXADRMD, address >> 8);
+        dmac_write(host, DMAC_TXADRHI, 0);
+        dmac_write(host, DMAC_MASKREG, MASK_OFF);
 
 #if (DEBUG & DEBUG_DMA)
         DBG(host->SCpnt, acornscsi_dumpdma(host, "into"));
@@ -1209,15 +1206,15 @@ void acornscsi_dma_intr(AS_Host *host)
          * attention condition.  We continue giving one byte until
          * the device recognises the attention.
          */
-        if (dmac_read(host->dma.io_port, DMAC_STATUS) & STATUS_RQ0) {
+        if (dmac_read(host, DMAC_STATUS) & STATUS_RQ0) {
             acornscsi_abortcmd(host, host->SCpnt->tag);
 
-            dmac_write(host->dma.io_port, DMAC_TXCNTLO, 0);
-            dmac_write(host->dma.io_port, DMAC_TXCNTHI, 0);
-            dmac_write(host->dma.io_port, DMAC_TXADRLO, 0);
-            dmac_write(host->dma.io_port, DMAC_TXADRMD, 0);
-            dmac_write(host->dma.io_port, DMAC_TXADRHI, 0);
-            dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_OFF);
+            dmac_write(host, DMAC_TXCNTLO, 0);
+            dmac_write(host, DMAC_TXCNTHI, 0);
+            dmac_write(host, DMAC_TXADRLO, 0);
+            dmac_write(host, DMAC_TXADRMD, 0);
+            dmac_write(host, DMAC_TXADRHI, 0);
+            dmac_write(host, DMAC_MASKREG, MASK_OFF);
         }
 #endif
     }
@@ -1271,9 +1268,9 @@ void acornscsi_dma_adjust(AS_Host *host)
             host->dma.xfer_setup = 0;
         else {
             transferred += host->dma.start_addr;
-            dmac_write(host->dma.io_port, DMAC_TXADRLO, transferred);
-            dmac_write(host->dma.io_port, DMAC_TXADRMD, transferred >> 8);
-            dmac_write(host->dma.io_port, DMAC_TXADRHI, transferred >> 16);
+            dmac_write(host, DMAC_TXADRLO, transferred);
+            dmac_write(host, DMAC_TXADRMD, transferred >> 8);
+            dmac_write(host, DMAC_TXADRHI, transferred >> 16);
 #if (DEBUG & (DEBUG_DMA|DEBUG_WRITE))
             DBG(host->SCpnt, acornscsi_dumpdma(host, "adjo"));
 #endif
@@ -1292,12 +1289,12 @@ acornscsi_write_pio(AS_Host *host, char *bytes, int *ptr, int len, unsigned int
         int my_ptr = *ptr;
 
         while (my_ptr < len) {
-                asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR);
+                asr = sbic_arm_read(host, SBIC_ASR);
 
                 if (asr & ASR_DBR) {
                         timeout = max_timeout;
 
-                        sbic_arm_write(host->scsi.io_port, SBIC_DATA, bytes[my_ptr++]);
+                        sbic_arm_write(host, SBIC_DATA, bytes[my_ptr++]);
                 } else if (asr & ASR_INT)
                         break;
                 else if (--timeout == 0)
@@ -1320,9 +1317,9 @@ acornscsi_sendcommand(AS_Host *host)
 {
         struct scsi_cmnd *SCpnt = host->SCpnt;
 
-    sbic_arm_write(host->scsi.io_port, SBIC_TRANSCNTH, 0);
-    sbic_arm_writenext(host->scsi.io_port, 0);
-    sbic_arm_writenext(host->scsi.io_port, SCpnt->cmd_len - host->scsi.SCp.sent_command);
+    sbic_arm_write(host, SBIC_TRANSCNTH, 0);
+    sbic_arm_writenext(host, 0);
+    sbic_arm_writenext(host, SCpnt->cmd_len - host->scsi.SCp.sent_command);
 
     acornscsi_sbic_issuecmd(host, CMND_XFERINFO);
 
@@ -1351,7 +1348,7 @@ void acornscsi_sendmessage(AS_Host *host)
 
         acornscsi_sbic_wait(host, ASR_DBR, ASR_DBR, 1000, "sending message 1");
 
-        sbic_arm_write(host->scsi.io_port, SBIC_DATA, NOP);
+        sbic_arm_write(host, SBIC_DATA, NOP);
 
         host->scsi.last_message = NOP;
 #if (DEBUG & DEBUG_MESSAGES)
@@ -1365,7 +1362,7 @@ void acornscsi_sendmessage(AS_Host *host)
 
         acornscsi_sbic_wait(host, ASR_DBR, ASR_DBR, 1000, "sending message 2");
 
-        sbic_arm_write(host->scsi.io_port, SBIC_DATA, msg->msg[0]);
+        sbic_arm_write(host, SBIC_DATA, msg->msg[0]);
 
         host->scsi.last_message = msg->msg[0];
 #if (DEBUG & DEBUG_MESSAGES)
@@ -1382,9 +1379,9 @@ void acornscsi_sendmessage(AS_Host *host)
          *  initiator.  This provides an interlock so that the
          *  initiator can determine which message byte is rejected.
          */
-        sbic_arm_write(host->scsi.io_port, SBIC_TRANSCNTH, 0);
-        sbic_arm_writenext(host->scsi.io_port, 0);
-        sbic_arm_writenext(host->scsi.io_port, message_length);
+        sbic_arm_write(host, SBIC_TRANSCNTH, 0);
+        sbic_arm_writenext(host, 0);
+        sbic_arm_writenext(host, message_length);
         acornscsi_sbic_issuecmd(host, CMND_XFERINFO);
 
         msgnr = 0;
@@ -1421,7 +1418,7 @@ void acornscsi_readstatusbyte(AS_Host *host)
 {
     acornscsi_sbic_issuecmd(host, CMND_XFERINFO|CMND_SBT);
     acornscsi_sbic_wait(host, ASR_DBR, ASR_DBR, 1000, "reading status byte");
-    host->scsi.SCp.Status = sbic_arm_read(host->scsi.io_port, SBIC_DATA);
+    host->scsi.SCp.Status = sbic_arm_read(host, SBIC_DATA);
 }
 
 /*
@@ -1438,12 +1435,12 @@ unsigned char acornscsi_readmessagebyte(AS_Host *host)
 
     acornscsi_sbic_wait(host, ASR_DBR, ASR_DBR, 1000, "for message byte");
 
-    message = sbic_arm_read(host->scsi.io_port, SBIC_DATA);
+    message = sbic_arm_read(host, SBIC_DATA);
 
     /* wait for MSGIN-XFER-PAUSED */
     acornscsi_sbic_wait(host, ASR_INT, ASR_INT, 1000, "for interrupt after message byte");
 
-    sbic_arm_read(host->scsi.io_port, SBIC_SSR);
+    sbic_arm_read(host, SBIC_SSR);
 
     return message;
 }
@@ -1480,7 +1477,7 @@ void acornscsi_message(AS_Host *host)
 
             /* wait for next msg-in */
             acornscsi_sbic_wait(host, ASR_INT, ASR_INT, 1000, "for interrupt after negate ack");
-            sbic_arm_read(host->scsi.io_port, SBIC_SSR);
+            sbic_arm_read(host, SBIC_SSR);
         }
     } while (msgidx < msglen);
 
@@ -1602,7 +1599,7 @@ void acornscsi_message(AS_Host *host)
                     host->host->host_no, acornscsi_target(host));
             host->device[host->SCpnt->device->id].sync_xfer = SYNCHTRANSFER_2DBA;
             host->device[host->SCpnt->device->id].sync_state = SYNC_ASYNCHRONOUS;
-            sbic_arm_write(host->scsi.io_port, SBIC_SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer);
+            sbic_arm_write(host, SBIC_SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer);
             break;
 
         default:
@@ -1652,7 +1649,7 @@ void acornscsi_message(AS_Host *host)
                 host->device[host->SCpnt->device->id].sync_xfer =
                         calc_sync_xfer(period * 4, length);
             }
-            sbic_arm_write(host->scsi.io_port, SBIC_SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer);
+            sbic_arm_write(host, SBIC_SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer);
             break;
 #else
             /* We do not accept synchronous transfers.  Respond with a
@@ -1792,10 +1789,10 @@ int acornscsi_starttransfer(AS_Host *host)
 
     residual = scsi_bufflen(host->SCpnt) - host->scsi.SCp.scsi_xferred;
 
-    sbic_arm_write(host->scsi.io_port, SBIC_SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer);
-    sbic_arm_writenext(host->scsi.io_port, residual >> 16);
-    sbic_arm_writenext(host->scsi.io_port, residual >> 8);
-    sbic_arm_writenext(host->scsi.io_port, residual);
+    sbic_arm_write(host, SBIC_SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer);
+    sbic_arm_writenext(host, residual >> 16);
+    sbic_arm_writenext(host, residual >> 8);
+    sbic_arm_writenext(host, residual);
     acornscsi_sbic_issuecmd(host, CMND_XFERINFO);
     return 1;
 }
@@ -1816,7 +1813,7 @@ int acornscsi_reconnect(AS_Host *host)
 {
     unsigned int target, lun, ok = 0;
 
-    target = sbic_arm_read(host->scsi.io_port, SBIC_SOURCEID);
+    target = sbic_arm_read(host, SBIC_SOURCEID);
 
     if (!(target & 8))
         printk(KERN_ERR "scsi%d: invalid source id after reselection "
@@ -1832,7 +1829,7 @@ int acornscsi_reconnect(AS_Host *host)
         host->SCpnt = NULL;
     }
 
-    lun = sbic_arm_read(host->scsi.io_port, SBIC_DATA) & 7;
+    lun = sbic_arm_read(host, SBIC_DATA) & 7;
 
     host->scsi.reconnected.target = target;
     host->scsi.reconnected.lun = lun;
@@ -1952,7 +1949,7 @@ static
 void acornscsi_abortcmd(AS_Host *host, unsigned char tag)
 {
     host->scsi.phase = PHASE_ABORTED;
-    sbic_arm_write(host->scsi.io_port, SBIC_CMND, CMND_ASSERTATN);
+    sbic_arm_write(host, SBIC_CMND, CMND_ASSERTATN);
 
     msgqueue_flush(&host->scsi.msgs);
 #ifdef CONFIG_SCSI_ACORNSCSI_TAGGED_QUEUE
@@ -1979,11 +1976,11 @@ intr_ret_t acornscsi_sbicintr(AS_Host *host, int in_irq)
 {
     unsigned int asr, ssr;
 
-    asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR);
+    asr = sbic_arm_read(host, SBIC_ASR);
     if (!(asr & ASR_INT))
         return INTR_IDLE;
 
-    ssr = sbic_arm_read(host->scsi.io_port, SBIC_SSR);
+    ssr = sbic_arm_read(host, SBIC_SSR);
 
 #if (DEBUG & DEBUG_PHASES)
     print_sbic_status(asr, ssr, host->scsi.phase);
@@ -1999,15 +1996,15 @@ intr_ret_t acornscsi_sbicintr(AS_Host *host, int in_irq)
         printk(KERN_ERR "scsi%d: reset in standard mode but wanted advanced mode.\n",
                 host->host->host_no);
         /* setup sbic - WD33C93A */
-        sbic_arm_write(host->scsi.io_port, SBIC_OWNID, OWNID_EAF | host->host->this_id);
-        sbic_arm_write(host->scsi.io_port, SBIC_CMND, CMND_RESET);
+        sbic_arm_write(host, SBIC_OWNID, OWNID_EAF | host->host->this_id);
+        sbic_arm_write(host, SBIC_CMND, CMND_RESET);
         return INTR_IDLE;
 
     case 0x01:                          /* reset state - advanced                       */
-        sbic_arm_write(host->scsi.io_port, SBIC_CTRL, INIT_SBICDMA | CTRL_IDI);
-        sbic_arm_write(host->scsi.io_port, SBIC_TIMEOUT, TIMEOUT_TIME);
-        sbic_arm_write(host->scsi.io_port, SBIC_SYNCHTRANSFER, SYNCHTRANSFER_2DBA);
-        sbic_arm_write(host->scsi.io_port, SBIC_SOURCEID, SOURCEID_ER | SOURCEID_DSP);
+        sbic_arm_write(host, SBIC_CTRL, INIT_SBICDMA | CTRL_IDI);
+        sbic_arm_write(host, SBIC_TIMEOUT, TIMEOUT_TIME);
+        sbic_arm_write(host, SBIC_SYNCHTRANSFER, SYNCHTRANSFER_2DBA);
+        sbic_arm_write(host, SBIC_SOURCEID, SOURCEID_ER | SOURCEID_DSP);
         msgqueue_flush(&host->scsi.msgs);
         return INTR_IDLE;
 
@@ -2025,10 +2022,10 @@ intr_ret_t acornscsi_sbicintr(AS_Host *host, int in_irq)
             msgqueue_flush(&host->scsi.msgs);
             host->dma.transferred = host->scsi.SCp.scsi_xferred;
             /* 33C93 gives next interrupt indicating bus phase */
-            asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR);
+            asr = sbic_arm_read(host, SBIC_ASR);
             if (!(asr & ASR_INT))
                 break;
-            ssr = sbic_arm_read(host->scsi.io_port, SBIC_SSR);
+            ssr = sbic_arm_read(host, SBIC_SSR);
             ADD_STATUS(8, ssr, host->scsi.phase, 1);
             ADD_STATUS(host->SCpnt->device->id, ssr, host->scsi.phase, 1);
             goto connected;
@@ -2476,11 +2473,11 @@ acornscsi_intr(int irq, void *dev_id)
     do {
         ret = INTR_IDLE;
 
-        iostatus = inb(host->card.io_intr);
+        iostatus = readb(host->fast + INT_REG);
 
         if (iostatus & 2) {
             acornscsi_dma_intr(host);
-            iostatus = inb(host->card.io_intr);
+            iostatus = readb(host->fast + INT_REG);
         }
 
         if (iostatus & 8)
@@ -2655,7 +2652,7 @@ static enum res_abort acornscsi_do_abort(AS_Host *host, struct scsi_cmnd *SCpnt)
                  * busylun bit.
                  */
                 case PHASE_CONNECTED:
-                        sbic_arm_write(host->scsi.io_port, SBIC_CMND, CMND_DISCONNECT);
+                        sbic_arm_write(host, SBIC_CMND, CMND_DISCONNECT);
                         host->SCpnt = NULL;
                         res = res_success_clear;
                         break;
@@ -2699,8 +2696,8 @@ int acornscsi_abort(struct scsi_cmnd *SCpnt)
 #if (DEBUG & DEBUG_ABORT)
         {
                 int asr, ssr;
-                asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR);
-                ssr = sbic_arm_read(host->scsi.io_port, SBIC_SSR);
+                asr = sbic_arm_read(host, SBIC_ASR);
+                ssr = sbic_arm_read(host, SBIC_SSR);
 
                 printk(KERN_WARNING "acornscsi_abort: ");
                 print_sbic_status(asr, ssr, host->scsi.phase);
@@ -2731,9 +2728,7 @@ int acornscsi_abort(struct scsi_cmnd *SCpnt)
 //#if (DEBUG & DEBUG_ABORT)
                 printk("success\n");
 //#endif
-                SCpnt->result = DID_ABORT << 16;
-                SCpnt->scsi_done(SCpnt);
-                result = SCSI_ABORT_SUCCESS;
+                result = SUCCESS;
                 break;
 
         /*
@@ -2745,7 +2740,7 @@ int acornscsi_abort(struct scsi_cmnd *SCpnt)
 //#if (DEBUG & DEBUG_ABORT)
                 printk("snooze\n");
 //#endif
-                result = SCSI_ABORT_SNOOZE;
+                result = FAILED;
                 break;
 
         /*
@@ -2755,11 +2750,7 @@ int acornscsi_abort(struct scsi_cmnd *SCpnt)
         default:
         case res_not_running:
                 acornscsi_dumplog(host, SCpnt->device->id);
-#if (DEBUG & DEBUG_ABORT)
-                result = SCSI_ABORT_SNOOZE;
-#else
-                result = SCSI_ABORT_NOT_RUNNING;
-#endif
+                result = FAILED;
 //#if (DEBUG & DEBUG_ABORT)
                 printk("not running\n");
 //#endif
@@ -2770,13 +2761,12 @@ int acornscsi_abort(struct scsi_cmnd *SCpnt)
 }
 
 /*
- * Prototype: int acornscsi_reset(struct scsi_cmnd *SCpnt, unsigned int reset_flags)
+ * Prototype: int acornscsi_reset(struct scsi_cmnd *SCpnt)
  * Purpose  : reset a command on this host/reset this host
  * Params   : SCpnt  - command causing reset
- *            result - what type of reset to perform
  * Returns  : one of SCSI_RESET_ macros
  */
-int acornscsi_reset(struct scsi_cmnd *SCpnt, unsigned int reset_flags)
+int acornscsi_bus_reset(struct scsi_cmnd *SCpnt)
 {
         AS_Host *host = (AS_Host *)SCpnt->device->host->hostdata;
         struct scsi_cmnd *SCptr;
@@ -2787,8 +2777,8 @@ int acornscsi_reset(struct scsi_cmnd *SCpnt, unsigned int reset_flags)
     {
         int asr, ssr;
 
-        asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR);
-        ssr = sbic_arm_read(host->scsi.io_port, SBIC_SSR);
+        asr = sbic_arm_read(host, SBIC_ASR);
+        ssr = sbic_arm_read(host, SBIC_SSR);
 
         printk(KERN_WARNING "acornscsi_reset: ");
         print_sbic_status(asr, ssr, host->scsi.phase);
@@ -2798,28 +2788,16 @@ int acornscsi_reset(struct scsi_cmnd *SCpnt, unsigned int reset_flags)
 
     acornscsi_dma_stop(host);
 
-    SCptr = host->SCpnt;
-
     /*
      * do hard reset.  This resets all devices on this host, and so we
      * must set the reset status on all commands.
      */
     acornscsi_resetcard(host);
 
-    /*
-     * report reset on commands current connected/disconnected
-     */
-    acornscsi_reportstatus(&host->SCpnt, &SCptr, DID_RESET);
-
     while ((SCptr = queue_remove(&host->queues.disconnected)) != NULL)
-        acornscsi_reportstatus(&SCptr, &SCpnt, DID_RESET);
-
-    if (SCpnt) {
-        SCpnt->result = DID_RESET << 16;
-        SCpnt->scsi_done(SCpnt);
-    }
+        ;
 
-    return SCSI_RESET_BUS_RESET | SCSI_RESET_HOST_RESET | SCSI_RESET_SUCCESS;
+    return SUCCESS;
 }
 
 /*==============================================================================================
@@ -2850,7 +2828,7 @@ char *acornscsi_info(struct Scsi_Host *host)
     " LINK"
 #endif
 #if (DEBUG & DEBUG_NO_WRITE)
-    " NOWRITE ("NO_WRITE_STR")"
+    " NOWRITE (" __stringify(NO_WRITE) ")"
 #endif
                 , host->hostt->name, host->io_port, host->irq,
                 VER_MAJOR, VER_MINOR, VER_PATCH);
@@ -2881,15 +2859,15 @@ int acornscsi_proc_info(struct Scsi_Host *instance, char *buffer, char **start,
     " LINK"
 #endif
 #if (DEBUG & DEBUG_NO_WRITE)
-    " NOWRITE ("NO_WRITE_STR")"
+    " NOWRITE (" __stringify(NO_WRITE) ")"
 #endif
                 "\n\n", VER_MAJOR, VER_MINOR, VER_PATCH);
 
-    p += sprintf(p,     "SBIC: WD33C93A  Address: %08X  IRQ : %d\n",
-                        host->scsi.io_port, host->scsi.irq);
+    p += sprintf(p,     "SBIC: WD33C93A  Address: %p    IRQ : %d\n",
+                        host->base + SBIC_REGIDX, host->scsi.irq);
 #ifdef USE_DMAC
-    p += sprintf(p,     "DMAC: uPC71071  Address: %08X  IRQ : %d\n\n",
-                        host->dma.io_port, host->scsi.irq);
+    p += sprintf(p,     "DMAC: uPC71071  Address: %p  IRQ : %d\n\n",
+                        host->base + DMAC_OFFSET, host->scsi.irq);
 #endif
 
     p += sprintf(p,     "Statistics:\n"
@@ -2976,9 +2954,8 @@ static struct scsi_host_template acornscsi_template = {
         .name                   = "AcornSCSI",
         .info                   = acornscsi_info,
         .queuecommand           = acornscsi_queuecmd,
-#warning fixme
-        .abort                  = acornscsi_abort,
-        .reset                  = acornscsi_reset,
+        .eh_abort_handler       = acornscsi_abort,
+        .eh_bus_reset_handler   = acornscsi_bus_reset,
         .can_queue              = 16,
         .this_id                = 7,
         .sg_tablesize           = SG_ALL,
@@ -2992,48 +2969,37 @@ acornscsi_probe(struct expansion_card *ec, const struct ecard_id *id)
 {
         struct Scsi_Host *host;
         AS_Host *ashost;
-        int ret = -ENOMEM;
+        int ret;
 
-        host = scsi_host_alloc(&acornscsi_template, sizeof(AS_Host));
-        if (!host)
+        ret = ecard_request_resources(ec);
+        if (ret)
                 goto out;
 
+        host = scsi_host_alloc(&acornscsi_template, sizeof(AS_Host));
+        if (!host) {
+                ret = -ENOMEM;
+                goto out_release;
+        }
+
         ashost = (AS_Host *)host->hostdata;
 
-        host->io_port = ecard_address(ec, ECARD_MEMC, 0);
-        host->irq = ec->irq;
+        ashost->base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
+        ashost->fast = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
+        if (!ashost->base || !ashost->fast)
+                goto out_put;
 
-        ashost->host            = host;
-        ashost->scsi.io_port    = ioaddr(host->io_port + 0x800);
-        ashost->scsi.irq        = host->irq;
-        ashost->card.io_intr    = POD_SPACE(host->io_port) + 0x800;
-        ashost->card.io_page    = POD_SPACE(host->io_port) + 0xc00;
-        ashost->card.io_ram     = ioaddr(host->io_port);
-        ashost->dma.io_port     = host->io_port + 0xc00;
-        ashost->dma.io_intr_clear = POD_SPACE(host->io_port) + 0x800;
+        host->irq = ec->irq;
+        ashost->host = host;
+        ashost->scsi.irq = host->irq;
 
-        ec->irqaddr     = (char *)ioaddr(ashost->card.io_intr);
+        ec->irqaddr     = ashost->fast + INT_REG;
         ec->irqmask     = 0x0a;
 
-        ret = -EBUSY;
-        if (!request_region(host->io_port + 0x800, 2, "acornscsi(sbic)"))
-                goto err_1;
-        if (!request_region(ashost->card.io_intr, 1, "acornscsi(intr)"))
-                goto err_2;
-        if (!request_region(ashost->card.io_page, 1, "acornscsi(page)"))
-                goto err_3;
-#ifdef USE_DMAC
-        if (!request_region(ashost->dma.io_port, 256, "acornscsi(dmac)"))
-                goto err_4;
-#endif
-        if (!request_region(host->io_port, 2048, "acornscsi(ram)"))
-                goto err_5;
-
         ret = request_irq(host->irq, acornscsi_intr, IRQF_DISABLED, "acornscsi", ashost);
         if (ret) {
                 printk(KERN_CRIT "scsi%d: IRQ%d not free: %d\n",
                         host->host_no, ashost->scsi.irq, ret);
-                goto err_6;
+                goto out_put;
         }
 
         memset(&ashost->stats, 0, sizeof (ashost->stats));
@@ -3045,27 +3011,22 @@ acornscsi_probe(struct expansion_card *ec, const struct ecard_id *id)
 
         ret = scsi_add_host(host, &ec->dev);
         if (ret)
-                goto err_7;
+                goto out_irq;
 
         scsi_scan_host(host);
         goto out;
 
- err_7:
+ out_irq:
         free_irq(host->irq, ashost);
- err_6:
-        release_region(host->io_port, 2048);
- err_5:
-#ifdef USE_DMAC
-        release_region(ashost->dma.io_port, 256);
-#endif
- err_4:
-        release_region(ashost->card.io_page, 1);
- err_3:
-        release_region(ashost->card.io_intr, 1);    
- err_2:
-        release_region(host->io_port + 0x800, 2);
- err_1:
+        msgqueue_free(&ashost->scsi.msgs);
+        queue_free(&ashost->queues.disconnected);
+        queue_free(&ashost->queues.issue);
+ out_put:
+        ecardm_iounmap(ec, ashost->fast);
+        ecardm_iounmap(ec, ashost->base);
         scsi_host_put(host);
+ out_release:
+        ecard_release_resources(ec);
  out:
         return ret;
 }
@@ -3081,20 +3042,17 @@ static void __devexit acornscsi_remove(struct expansion_card *ec)
         /*
          * Put card into RESET state
          */
-        outb(0x80, ashost->card.io_page);
+        writeb(0x80, ashost->fast + PAGE_REG);
 
         free_irq(host->irq, ashost);
 
-        release_region(host->io_port + 0x800, 2);
-        release_region(ashost->card.io_intr, 1);
-        release_region(ashost->card.io_page, 1);
-        release_region(ashost->dma.io_port, 256);
-        release_region(host->io_port, 2048);
-
         msgqueue_free(&ashost->scsi.msgs);
         queue_free(&ashost->queues.disconnected);
         queue_free(&ashost->queues.issue);
+        ecardm_iounmap(ec, ashost->fast);
+        ecardm_iounmap(ec, ashost->base);
         scsi_host_put(host);
+        ecard_release_resources(ec);
 }
 
 static const struct ecard_id acornscsi_cids[] = {
diff --git a/drivers/scsi/arm/acornscsi.h b/drivers/scsi/arm/acornscsi.h
index d11424b89f42..8d2172a0b351 100644
--- a/drivers/scsi/arm/acornscsi.h
+++ b/drivers/scsi/arm/acornscsi.h
@@ -179,7 +179,6 @@
 
 /* miscellaneous internal variables */
 
-#define POD_SPACE(x)    ((x) + 0xd0000)
 #define MASK_ON         (MASKREG_M3|MASKREG_M2|MASKREG_M1|MASKREG_M0)
 #define MASK_OFF        (MASKREG_M3|MASKREG_M2|MASKREG_M1)
 
@@ -279,10 +278,11 @@ typedef struct acornscsi_hostdata {
     struct Scsi_Host    *host;                  /* host                                 */
     struct scsi_cmnd    *SCpnt;                 /* currently processing command         */
     struct scsi_cmnd    *origSCpnt;             /* original connecting command          */
+    void __iomem        *base;                  /* memc base address                    */
+    void __iomem        *fast;                  /* fast ioc base address                */
 
     /* driver information */
     struct {
-        unsigned int    io_port;                /* base address of WD33C93              */
         unsigned int    irq;                    /* interrupt                            */
         phase_t         phase;                  /* current phase                        */
 
@@ -329,8 +329,6 @@ typedef struct acornscsi_hostdata {
 
     /* DMA info */
     struct {
-        unsigned int    io_port;                /* base address of DMA controller       */
-        unsigned int    io_intr_clear;          /* address of DMA interrupt clear       */
         unsigned int    free_addr;              /* next free address                    */
         unsigned int    start_addr;             /* start address of current transfer    */
         dmadir_t        direction;              /* dma direction                        */
@@ -345,9 +343,6 @@ typedef struct acornscsi_hostdata {
 
     /* card info */
     struct {
-        unsigned int    io_intr;                /* base address of interrupt id reg     */
-        unsigned int    io_page;                /* base address of page reg             */
-        unsigned int    io_ram;                 /* base address of RAM access           */
         unsigned char   page_reg;               /* current setting of page reg          */
     } card;
 
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 9bc42763623c..18ca9075e131 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -448,22 +448,27 @@ config SERIAL_CLPS711X_CONSOLE
           your boot loader (lilo or loadlin) about how to pass options to the
           kernel at boot time.)
 
-config SERIAL_S3C2410
-        tristate "Samsung S3C2410/S3C2440/S3C2442/S3C2412 Serial port support"
-        depends on ARM && ARCH_S3C2410
-        select SERIAL_CORE
+config SERIAL_SAMSUNG
+        tristate "Samsung SoC serial support"
+        depends on ARM && PLAT_S3C24XX
         help
           Support for the on-chip UARTs on the Samsung S3C24XX series CPUs,
           providing /dev/ttySAC0, 1 and 2 (note, some machines may not
           provide all of these ports, depending on how the serial port
           pins are configured.
 
-          Currently this driver supports the UARTS on the S3C2410, S3C2440,
-          S3C2442, S3C2412 and S3C2413 CPUs.
+config SERIAL_SAMSUNG_DEBUG
+        bool "Samsung SoC serial debug"
+        depends on SERIAL_SAMSUNG
+        help
+          Add support for debugging the serial driver. Since this is
+          generally being used as a console, we use our own output
+          routines that go via the low-level debug printascii()
+          function.
 
-config SERIAL_S3C2410_CONSOLE
-        bool "Support for console on S3C2410 serial port"
-        depends on SERIAL_S3C2410=y
+config SERIAL_SAMSUNG_CONSOLE
+        bool "Support for console on Samsung SoC serial port"
+        depends on SERIAL_SAMSUNG=y
         select SERIAL_CORE_CONSOLE
         help
           Allow selection of the S3C24XX on-board serial ports for use as
@@ -476,6 +481,37 @@ config SERIAL_S3C2410_CONSOLE
           your boot loader about how to pass options to the kernel at
           boot time.)
 
+config SERIAL_S3C2400
+        tristate "Samsung S3C2410 Serial port support"
+        depends on ARM && SERIAL_SAMSUNG && CPU_S3C2400
+        default y if CPU_S3C2400
+        help
+          Serial port support for the Samsung S3C2400 SoC
+
+config SERIAL_S3C2410
+        tristate "Samsung S3C2410 Serial port support"
+        depends on SERIAL_SAMSUNG && CPU_S3C2410
+        default y if CPU_S3C2410
+        help
+          Serial port support for the Samsung S3C2410 SoC
+
+config SERIAL_S3C2412
+        tristate "Samsung S3C2412/S3C2413 Serial port support"
+        depends on SERIAL_SAMSUNG && CPU_S3C2412
+        default y if CPU_S3C2412
+        help
+          Serial port support for the Samsung S3C2412 and S3C2413 SoC
+
+config SERIAL_S3C2440
+        tristate "Samsung S3C2440/S3C2442 Serial port support"
+        depends on SERIAL_SAMSUNG && (CPU_S3C2440 || CPU_S3C2442)
+        default y if CPU_S3C2440
+        default y if CPU_S3C2442
+        help
+          Serial port support for the Samsung S3C2440 and S3C2442 SoC
+
+
+
 config SERIAL_DZ
         bool "DECstation DZ serial driver"
         depends on MACH_DECSTATION && 32BIT
@@ -753,7 +789,7 @@ config BFIN_UART3_CTSRTS
 
 config SERIAL_IMX
         bool "IMX serial port support"
-        depends on ARM && ARCH_IMX
+        depends on ARM && (ARCH_IMX || ARCH_MXC)
         select SERIAL_CORE
         help
           If you have a machine based on a Motorola IMX CPU you
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 0d9c09b1e836..7d85c1fbe7e0 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -28,7 +28,11 @@ obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o
 obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
 obj-$(CONFIG_SERIAL_BFIN) += bfin_5xx.o
 obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o
+obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o
+obj-$(CONFIG_SERIAL_S3C2400) += s3c2400.o
 obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o
+obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o
+obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o
 obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o
 obj-$(CONFIG_SERIAL_SUNHV) += sunhv.o
 obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c
index 5a375bf0ebf4..64acb39a51ba 100644
--- a/drivers/serial/imx.c
+++ b/drivers/serial/imx.c
@@ -40,6 +40,7 @@
 #include <linux/tty_flip.h>
 #include <linux/serial_core.h>
 #include <linux/serial.h>
+#include <linux/clk.h>
 
 #include <asm/io.h>
 #include <asm/irq.h>
@@ -61,6 +62,11 @@
 #define UBIR  0xa4 /* BRM Incremental Register */
 #define UBMR  0xa8 /* BRM Modulator Register */
 #define UBRC  0xac /* Baud Rate Count Register */
+#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
+#define ONEMS 0xb0 /* One Millisecond register */
+#define UTS   0xb4 /* UART Test Register */
+#endif
+#ifdef CONFIG_ARCH_IMX
 #define BIPR1 0xb0 /* Incremental Preset Register 1 */
 #define BIPR2 0xb4 /* Incremental Preset Register 2 */
 #define BIPR3 0xb8 /* Incremental Preset Register 3 */
@@ -70,6 +76,7 @@
 #define BMPR3 0xc8 /* BRM Modulator Register 3 */
 #define BMPR4 0xcc /* BRM Modulator Register 4 */
 #define UTS   0xd0 /* UART Test Register */
+#endif
 
 /* UART Control Register Bit Fields.*/
 #define  URXD_CHARRDY    (1<<15)
@@ -89,7 +96,12 @@
 #define  UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
 #define  UCR1_SNDBRK     (1<<4)  /* Send break */
 #define  UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
+#ifdef CONFIG_ARCH_IMX
 #define  UCR1_UARTCLKEN  (1<<2)  /* UART clock enabled */
+#endif
+#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
+#define  UCR1_UARTCLKEN  (0)     /* not present on mx2/mx3 */
+#endif
 #define  UCR1_DOZE       (1<<1)  /* Doze */
 #define  UCR1_UARTEN     (1<<0)  /* UART enabled */
 #define  UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
@@ -163,8 +175,19 @@
 #define  UTS_SOFTRST     (1<<0)  /* Software reset */
 
 /* We've been assigned a range on the "Low-density serial ports" major */
+#ifdef CONFIG_ARCH_IMX
 #define SERIAL_IMX_MAJOR        204
 #define MINOR_START             41
+#define DEV_NAME                "ttySMX"
+#define MAX_INTERNAL_IRQ        IMX_IRQS
+#endif
+
+#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
+#define SERIAL_IMX_MAJOR        207
+#define MINOR_START             16
+#define DEV_NAME                "ttymxc"
+#define MAX_INTERNAL_IRQ        MXC_MAX_INT_LINES
+#endif
 
 /*
  * This determines how often we check the modem status signals
@@ -176,12 +199,15 @@
 
 #define DRIVER_NAME "IMX-uart"
 
+#define UART_NR 8
+
 struct imx_port {
         struct uart_port        port;
         struct timer_list       timer;
         unsigned int            old_status;
         int                     txirq,rxirq,rtsirq;
         int                     have_rtscts:1;
+        struct clk              *clk;
 };
 
 /*
@@ -405,6 +431,26 @@ out:
         return IRQ_HANDLED;
 }
 
+static irqreturn_t imx_int(int irq, void *dev_id)
+{
+        struct imx_port *sport = dev_id;
+        unsigned int sts;
+
+        sts = readl(sport->port.membase + USR1);
+
+        if (sts & USR1_RRDY)
+                imx_rxint(irq, dev_id);
+
+        if (sts & USR1_TRDY &&
+                        readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
+                imx_txint(irq, dev_id);
+
+        if (sts & USR1_RTSS)
+                imx_rtsint(irq, dev_id);
+
+        return IRQ_HANDLED;
+}
+
 /*
  * Return TIOCSER_TEMT when transmitter is not busy.
  */
@@ -477,7 +523,8 @@ static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
          * RFDIV is set such way to satisfy requested uartclk value
          */
         val = TXTL << 10 | RXTL;
-        ufcr_rfdiv = (imx_get_perclk1() + sport->port.uartclk / 2) / sport->port.uartclk;
+        ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2)
+                        / sport->port.uartclk;
 
         if(!ufcr_rfdiv)
                 ufcr_rfdiv = 1;
@@ -509,21 +556,34 @@ static int imx_startup(struct uart_port *port)
         writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
 
         /*
-         * Allocate the IRQ
+         * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
+         * chips only have one interrupt.
          */
-        retval = request_irq(sport->rxirq, imx_rxint, 0,
-                             DRIVER_NAME, sport);
-        if (retval) goto error_out1;
-
-        retval = request_irq(sport->txirq, imx_txint, 0,
-                             DRIVER_NAME, sport);
-        if (retval) goto error_out2;
-
-        retval = request_irq(sport->rtsirq, imx_rtsint,
-                             (sport->rtsirq < IMX_IRQS) ? 0 :
+        if (sport->txirq > 0) {
+                retval = request_irq(sport->rxirq, imx_rxint, 0,
+                                DRIVER_NAME, sport);
+                if (retval)
+                        goto error_out1;
+
+                retval = request_irq(sport->txirq, imx_txint, 0,
+                                DRIVER_NAME, sport);
+                if (retval)
+                        goto error_out2;
+
+                retval = request_irq(sport->rtsirq, imx_rtsint,
+                             (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
                                IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
-                             DRIVER_NAME, sport);
-        if (retval) goto error_out3;
+                                DRIVER_NAME, sport);
+                if (retval)
+                        goto error_out3;
+        } else {
+                retval = request_irq(sport->port.irq, imx_int, 0,
+                                DRIVER_NAME, sport);
+                if (retval) {
+                        free_irq(sport->port.irq, sport);
+                        goto error_out1;
+                }
+        }
 
         /*
          * Finally, clear and enable interrupts
@@ -548,9 +608,11 @@ static int imx_startup(struct uart_port *port)
         return 0;
 
 error_out3:
-        free_irq(sport->txirq, sport);
+        if (sport->txirq)
+                free_irq(sport->txirq, sport);
 error_out2:
-        free_irq(sport->rxirq, sport);
+        if (sport->rxirq)
+                free_irq(sport->rxirq, sport);
 error_out1:
         return retval;
 }
@@ -568,9 +630,12 @@ static void imx_shutdown(struct uart_port *port)
         /*
          * Free the interrupts
          */
-        free_irq(sport->rtsirq, sport);
-        free_irq(sport->txirq, sport);
-        free_irq(sport->rxirq, sport);
+        if (sport->txirq > 0) {
+                free_irq(sport->rtsirq, sport);
+                free_irq(sport->txirq, sport);
+                free_irq(sport->rxirq, sport);
+        } else
+                free_irq(sport->port.irq, sport);
 
         /*
          * Disable all interrupts, port and break condition.
@@ -589,6 +654,7 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
         unsigned long flags;
         unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
+        unsigned int div, num, denom, ufcr;
 
         /*
          * If we don't support modem control lines, don't allow
@@ -634,7 +700,7 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
         /*
          * Ask the core to calculate the divisor for us.
          */
-        baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
+        baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
         quot = uart_get_divisor(port, baud);
 
         spin_lock_irqsave(&sport->port.lock, flags);
@@ -684,14 +750,41 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
                         sport->port.membase + UCR2);
         old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
 
-        /* set the baud rate. We assume uartclk = 16 MHz
-         *
-         * baud * 16   UBIR - 1
-         * --------- = --------
-         *  uartclk    UBMR - 1
-         */
-        writel((baud / 100) - 1, sport->port.membase + UBIR);
-        writel(10000 - 1, sport->port.membase + UBMR);
+        div = sport->port.uartclk / (baud * 16);
+        if (div > 7)
+                div = 7;
+        if (!div)
+                div = 1;
+
+        num = baud;
+        denom = port->uartclk / div / 16;
+
+        /* shift num and denom right until they fit into 16 bits */
+        while (num > 0x10000 || denom > 0x10000) {
+                num >>= 1;
+                denom >>= 1;
+        }
+        if (num > 0)
+                num -= 1;
+        if (denom > 0)
+                denom -= 1;
+
+        writel(num, sport->port.membase + UBIR);
+        writel(denom, sport->port.membase + UBMR);
+
+        if (div == 7)
+                div = 6; /* 6 in RFDIV means divide by 7 */
+        else
+                div = 6 - div;
+
+        ufcr = readl(sport->port.membase + UFCR);
+        ufcr = (ufcr & (~UFCR_RFDIV)) |
+            (div << 7);
+        writel(ufcr, sport->port.membase + UFCR);
+
+#ifdef ONEMS
+        writel(sport->port.uartclk / div / 1000, sport->port.membase + ONEMS);
+#endif
 
         writel(old_ucr1, sport->port.membase + UCR1);
 
@@ -801,65 +894,7 @@ static struct uart_ops imx_pops = {
         .verify_port    = imx_verify_port,
 };
 
-static struct imx_port imx_ports[] = {
-        {
-        .txirq  = UART1_MINT_TX,
-        .rxirq  = UART1_MINT_RX,
-        .rtsirq = UART1_MINT_RTS,
-        .port   = {
-                .type           = PORT_IMX,
-                .iotype         = UPIO_MEM,
-                .membase        = (void *)IMX_UART1_BASE,
-                .mapbase        = 0x00206000,
-                .irq            = UART1_MINT_RX,
-                .uartclk        = 16000000,
-                .fifosize       = 32,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .ops            = &imx_pops,
-                .line           = 0,
-        },
-        }, {
-        .txirq  = UART2_MINT_TX,
-        .rxirq  = UART2_MINT_RX,
-        .rtsirq = UART2_MINT_RTS,
-        .port   = {
-                .type           = PORT_IMX,
-                .iotype         = UPIO_MEM,
-                .membase        = (void *)IMX_UART2_BASE,
-                .mapbase        = 0x00207000,
-                .irq            = UART2_MINT_RX,
-                .uartclk        = 16000000,
-                .fifosize       = 32,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .ops            = &imx_pops,
-                .line           = 1,
-        },
-        }
-};
-
-/*
- * Setup the IMX serial ports.
- * Note also that we support "console=ttySMXx" where "x" is either 0 or 1.
- * Which serial port this ends up being depends on the machine you're
- * running this kernel on.  I'm not convinced that this is a good idea,
- * but that's the way it traditionally works.
- *
- */
-static void __init imx_init_ports(void)
-{
-        static int first = 1;
-        int i;
-
-        if (!first)
-                return;
-        first = 0;
-
-        for (i = 0; i < ARRAY_SIZE(imx_ports); i++) {
-                init_timer(&imx_ports[i].timer);
-                imx_ports[i].timer.function = imx_timeout;
-                imx_ports[i].timer.data     = (unsigned long)&imx_ports[i];
-        }
-}
+static struct imx_port *imx_ports[UART_NR];
 
 #ifdef CONFIG_SERIAL_IMX_CONSOLE
 static void imx_console_putchar(struct uart_port *port, int ch)
@@ -878,7 +913,7 @@ static void imx_console_putchar(struct uart_port *port, int ch)
 static void
 imx_console_write(struct console *co, const char *s, unsigned int count)
 {
-        struct imx_port *sport = &imx_ports[co->index];
+        struct imx_port *sport = imx_ports[co->index];
         unsigned int old_ucr1, old_ucr2;
 
         /*
@@ -944,7 +979,7 @@ imx_console_get_options(struct imx_port *sport, int *baud,
                 else
                         ucfr_rfdiv = 6 - ucfr_rfdiv;
 
-                uartclk = imx_get_perclk1();
+                uartclk = clk_get_rate(sport->clk);
                 uartclk /= ucfr_rfdiv;
 
                 {       /*
@@ -984,7 +1019,7 @@ imx_console_setup(struct console *co, char *options)
          */
         if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
                 co->index = 0;
-        sport = &imx_ports[co->index];
+        sport = imx_ports[co->index];
 
         if (options)
                 uart_parse_options(options, &baud, &parity, &bits, &flow);
@@ -998,7 +1033,7 @@ imx_console_setup(struct console *co, char *options)
 
 static struct uart_driver imx_reg;
 static struct console imx_console = {
-        .name           = "ttySMX",
+        .name           = DEV_NAME,
         .write          = imx_console_write,
         .device         = uart_console_device,
         .setup          = imx_console_setup,
@@ -1007,14 +1042,6 @@ static struct console imx_console = {
         .data           = &imx_reg,
 };
 
-static int __init imx_rs_console_init(void)
-{
-        imx_init_ports();
-        register_console(&imx_console);
-        return 0;
-}
-console_initcall(imx_rs_console_init);
-
 #define IMX_CONSOLE     &imx_console
 #else
 #define IMX_CONSOLE     NULL
@@ -1023,7 +1050,7 @@ console_initcall(imx_rs_console_init);
 static struct uart_driver imx_reg = {
         .owner          = THIS_MODULE,
         .driver_name    = DRIVER_NAME,
-        .dev_name       = "ttySMX",
+        .dev_name       = DEV_NAME,
         .major          = SERIAL_IMX_MAJOR,
         .minor          = MINOR_START,
         .nr             = ARRAY_SIZE(imx_ports),
@@ -1050,29 +1077,98 @@ static int serial_imx_resume(struct platform_device *dev)
         return 0;
 }
 
-static int serial_imx_probe(struct platform_device *dev)
+static int serial_imx_probe(struct platform_device *pdev)
 {
+        struct imx_port *sport;
         struct imxuart_platform_data *pdata;
+        void __iomem *base;
+        int ret = 0;
+        struct resource *res;
+
+        sport = kzalloc(sizeof(*sport), GFP_KERNEL);
+        if (!sport)
+                return -ENOMEM;
 
-        imx_ports[dev->id].port.dev = &dev->dev;
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                ret = -ENODEV;
+                goto free;
+        }
+
+        base = ioremap(res->start, PAGE_SIZE);
+        if (!base) {
+                ret = -ENOMEM;
+                goto free;
+        }
+
+        sport->port.dev = &pdev->dev;
+        sport->port.mapbase = res->start;
+        sport->port.membase = base;
+        sport->port.type = PORT_IMX,
+        sport->port.iotype = UPIO_MEM;
+        sport->port.irq = platform_get_irq(pdev, 0);
+        sport->rxirq = platform_get_irq(pdev, 0);
+        sport->txirq = platform_get_irq(pdev, 1);
+        sport->rtsirq = platform_get_irq(pdev, 2);
+        sport->port.fifosize = 32;
+        sport->port.ops = &imx_pops;
+        sport->port.flags = UPF_BOOT_AUTOCONF;
+        sport->port.line = pdev->id;
+        init_timer(&sport->timer);
+        sport->timer.function = imx_timeout;
+        sport->timer.data     = (unsigned long)sport;
+
+        sport->clk = clk_get(&pdev->dev, "uart_clk");
+        if (IS_ERR(sport->clk)) {
+                ret = PTR_ERR(sport->clk);
+                goto unmap;
+        }
+        clk_enable(sport->clk);
 
-        pdata = (struct imxuart_platform_data *)dev->dev.platform_data;
+        sport->port.uartclk = clk_get_rate(sport->clk);
+
+        imx_ports[pdev->id] = sport;
+
+        pdata = pdev->dev.platform_data;
         if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
-                imx_ports[dev->id].have_rtscts = 1;
+                sport->have_rtscts = 1;
+
+        if (pdata->init)
+                pdata->init(pdev);
+
+        uart_add_one_port(&imx_reg, &sport->port);
+        platform_set_drvdata(pdev, &sport->port);
 
-        uart_add_one_port(&imx_reg, &imx_ports[dev->id].port);
-        platform_set_drvdata(dev, &imx_ports[dev->id]);
         return 0;
+unmap:
+        iounmap(sport->port.membase);
+free:
+        kfree(sport);
+
+        return ret;
 }
 
-static int serial_imx_remove(struct platform_device *dev)
+static int serial_imx_remove(struct platform_device *pdev)
 {
-        struct imx_port *sport = platform_get_drvdata(dev);
+        struct imxuart_platform_data *pdata;
+        struct imx_port *sport = platform_get_drvdata(pdev);
 
-        platform_set_drvdata(dev, NULL);
+        pdata = pdev->dev.platform_data;
 
-        if (sport)
+        platform_set_drvdata(pdev, NULL);
+
+        if (sport) {
                 uart_remove_one_port(&imx_reg, &sport->port);
+                clk_put(sport->clk);
+        }
+
+        clk_disable(sport->clk);
+
+        if (pdata->exit)
+                pdata->exit(pdev);
+
+        iounmap(sport->port.membase);
+        kfree(sport);
 
         return 0;
 }
@@ -1095,8 +1191,6 @@ static int __init imx_serial_init(void)
 
         printk(KERN_INFO "Serial: IMX driver\n");
 
-        imx_init_ports();
-
         ret = uart_register_driver(&imx_reg);
         if (ret)
                 return ret;
diff --git a/drivers/serial/s3c2400.c b/drivers/serial/s3c2400.c
new file mode 100644
index 000000000000..a1102053e553
--- /dev/null
+++ b/drivers/serial/s3c2400.c
@@ -0,0 +1,106 @@
+/* linux/drivers/serial/s3c240.c
+ *
+ * Driver for Samsung SoC onboard UARTs.
+ *
+ * Ben Dooks, Copyright (c) 2003-2005 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include <asm/irq.h>
+
+#include <asm/hardware.h>
+
+#include <asm/plat-s3c/regs-serial.h>
+#include <asm/arch/regs-gpio.h>
+
+#include "samsung.h"
+
+static int s3c2400_serial_getsource(struct uart_port *port,
+                                    struct s3c24xx_uart_clksrc *clk)
+{
+        clk->divisor = 1;
+        clk->name = "pclk";
+
+        return 0;
+}
+
+static int s3c2400_serial_setsource(struct uart_port *port,
+                                    struct s3c24xx_uart_clksrc *clk)
+{
+        return 0;
+}
+
+static int s3c2400_serial_resetport(struct uart_port *port,
+                                    struct s3c2410_uartcfg *cfg)
+{
+        dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n",
+            port, port->mapbase, cfg);
+
+        wr_regl(port, S3C2410_UCON,  cfg->ucon);
+        wr_regl(port, S3C2410_ULCON, cfg->ulcon);
+
+        /* reset both fifos */
+
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon);
+
+        return 0;
+}
+
+static struct s3c24xx_uart_info s3c2400_uart_inf = {
+        .name           = "Samsung S3C2400 UART",
+        .type           = PORT_S3C2400,
+        .fifosize       = 16,
+        .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
+        .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
+        .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
+        .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
+        .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
+        .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
+        .get_clksrc     = s3c2400_serial_getsource,
+        .set_clksrc     = s3c2400_serial_setsource,
+        .reset_port     = s3c2400_serial_resetport,
+};
+
+static int s3c2400_serial_probe(struct platform_device *dev)
+{
+        return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
+}
+
+static struct platform_driver s3c2400_serial_drv = {
+        .probe          = s3c2400_serial_probe,
+        .remove         = s3c24xx_serial_remove,
+        .driver         = {
+                .name   = "s3c2400-uart",
+                .owner  = THIS_MODULE,
+        },
+};
+
+s3c24xx_console_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
+
+static inline int s3c2400_serial_init(void)
+{
+        return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
+}
+
+static inline void s3c2400_serial_exit(void)
+{
+        platform_driver_unregister(&s3c2400_serial_drv);
+}
+
+module_init(s3c2400_serial_init);
+module_exit(s3c2400_serial_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_DESCRIPTION("Samsung S3C2400 SoC Serial port driver");
+MODULE_ALIAS("platform:s3c2400-uart");
diff --git a/drivers/serial/s3c2410.c b/drivers/serial/s3c2410.c
index 2b6a013639e6..c5f03f41686f 100644
--- a/drivers/serial/s3c2410.c
+++ b/drivers/serial/s3c2410.c
@@ -1,1270 +1,30 @@
-/*
- * linux/drivers/serial/s3c2410.c
+/* linux/drivers/serial/s3c2410.c
  *
- * Driver for onboard UARTs on the Samsung S3C24XX
+ * Driver for Samsung S3C2410 SoC onboard UARTs.
  *
- * Based on drivers/char/serial.c and drivers/char/21285.c
+ * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
  *
- * Ben Dooks, (c) 2003-2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/SWLINUX/
- *
- * Changelog:
- *
- * 22-Jul-2004  BJD  Finished off device rewrite
- *
- * 21-Jul-2004  BJD  Thanks to <herbet@13thfloor.at> for pointing out
- *                   problems with baud rate and loss of IR settings. Update
- *                   to add configuration via platform_device structure
- *
- * 28-Sep-2004  BJD  Re-write for the following items
- *                   - S3C2410 and S3C2440 serial support
- *                   - Power Management support
- *                   - Fix console via IrDA devices
- *                   - SysReq (Herbert Pötzl)
- *                   - Break character handling (Herbert Pötzl)
- *                   - spin-lock initialisation (Dimitry Andric)
- *                   - added clock control
- *                   - updated init code to use platform_device info
- *
- * 06-Mar-2005  BJD  Add s3c2440 fclk clock source
- *
- * 09-Mar-2005  BJD  Add s3c2400 support
- *
- * 10-Mar-2005  LCVR Changed S3C2410_VA_UART to S3C24XX_VA_UART
-*/
-
-/* Note on 2440 fclk clock source handling
- *
- * Whilst it is possible to use the fclk as clock source, the method
- * of properly switching too/from this is currently un-implemented, so
- * whichever way is configured at startup is the one that will be used.
-*/
-
-/* Hote on 2410 error handling
- *
- * The s3c2410 manual has a love/hate affair with the contents of the
- * UERSTAT register in the UART blocks, and keeps marking some of the
- * error bits as reserved. Having checked with the s3c2410x01,
- * it copes with BREAKs properly, so I am happy to ignore the RESERVED
- * feature from the latter versions of the manual.
- *
- * If it becomes aparrent that latter versions of the 2410 remove these
- * bits, then action will have to be taken to differentiate the versions
- * and change the policy on BREAK
- *
- * BJD, 04-Nov-2004
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
 */
 
-
-#if defined(CONFIG_SERIAL_S3C2410_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
-#define SUPPORT_SYSRQ
-#endif
-
 #include <linux/module.h>
 #include <linux/ioport.h>
+#include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/init.h>
-#include <linux/sysrq.h>
-#include <linux/console.h>
-#include <linux/tty.h>
-#include <linux/tty_flip.h>
 #include <linux/serial_core.h>
 #include <linux/serial.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
-
 #include <asm/hardware.h>
 
 #include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 
-/* structures */
-
-struct s3c24xx_uart_info {
-        char                    *name;
-        unsigned int            type;
-        unsigned int            fifosize;
-        unsigned long           rx_fifomask;
-        unsigned long           rx_fifoshift;
-        unsigned long           rx_fifofull;
-        unsigned long           tx_fifomask;
-        unsigned long           tx_fifoshift;
-        unsigned long           tx_fifofull;
-
-        /* clock source control */
-
-        int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
-        int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
-
-        /* uart controls */
-        int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
-};
-
-struct s3c24xx_uart_port {
-        unsigned char                   rx_claimed;
-        unsigned char                   tx_claimed;
-
-        struct s3c24xx_uart_info        *info;
-        struct s3c24xx_uart_clksrc      *clksrc;
-        struct clk                      *clk;
-        struct clk                      *baudclk;
-        struct uart_port                port;
-};
-
-
-/* configuration defines */
-
-#if 0
-#if 1
-/* send debug to the low-level output routines */
-
-extern void printascii(const char *);
-
-static void
-s3c24xx_serial_dbg(const char *fmt, ...)
-{
-        va_list va;
-        char buff[256];
-
-        va_start(va, fmt);
-        vsprintf(buff, fmt, va);
-        va_end(va);
-
-        printascii(buff);
-}
-
-#define dbg(x...) s3c24xx_serial_dbg(x)
-
-#else
-#define dbg(x...) printk(KERN_DEBUG "s3c24xx: ");
-#endif
-#else /* no debug */
-#define dbg(x...) do {} while(0)
-#endif
-
-/* UART name and device definitions */
-
-#define S3C24XX_SERIAL_NAME     "ttySAC"
-#define S3C24XX_SERIAL_MAJOR    204
-#define S3C24XX_SERIAL_MINOR    64
-
-
-/* conversion functions */
-
-#define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
-#define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
-
-/* we can support 3 uarts, but not always use them */
-
-#ifdef CONFIG_CPU_S3C2400
-#define NR_PORTS (2)
-#else
-#define NR_PORTS (3)
-#endif
-
-/* port irq numbers */
-
-#define TX_IRQ(port) ((port)->irq + 1)
-#define RX_IRQ(port) ((port)->irq)
-
-/* register access controls */
-
-#define portaddr(port, reg) ((port)->membase + (reg))
-
-#define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
-#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
-
-#define wr_regb(port, reg, val) \
-  do { __raw_writeb(val, portaddr(port, reg)); } while(0)
-
-#define wr_regl(port, reg, val) \
-  do { __raw_writel(val, portaddr(port, reg)); } while(0)
-
-/* macros to change one thing to another */
-
-#define tx_enabled(port) ((port)->unused[0])
-#define rx_enabled(port) ((port)->unused[1])
-
-/* flag to ignore all characters comming in */
-#define RXSTAT_DUMMY_READ (0x10000000)
-
-static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
-{
-        return container_of(port, struct s3c24xx_uart_port, port);
-}
-
-/* translate a port to the device name */
-
-static inline const char *s3c24xx_serial_portname(struct uart_port *port)
-{
-        return to_platform_device(port->dev)->name;
-}
-
-static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
-{
-        return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
-}
-
-static void s3c24xx_serial_rx_enable(struct uart_port *port)
-{
-        unsigned long flags;
-        unsigned int ucon, ufcon;
-        int count = 10000;
-
-        spin_lock_irqsave(&port->lock, flags);
-
-        while (--count && !s3c24xx_serial_txempty_nofifo(port))
-                udelay(100);
-
-        ufcon = rd_regl(port, S3C2410_UFCON);
-        ufcon |= S3C2410_UFCON_RESETRX;
-        wr_regl(port, S3C2410_UFCON, ufcon);
-
-        ucon = rd_regl(port, S3C2410_UCON);
-        ucon |= S3C2410_UCON_RXIRQMODE;
-        wr_regl(port, S3C2410_UCON, ucon);
-
-        rx_enabled(port) = 1;
-        spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static void s3c24xx_serial_rx_disable(struct uart_port *port)
-{
-        unsigned long flags;
-        unsigned int ucon;
-
-        spin_lock_irqsave(&port->lock, flags);
-
-        ucon = rd_regl(port, S3C2410_UCON);
-        ucon &= ~S3C2410_UCON_RXIRQMODE;
-        wr_regl(port, S3C2410_UCON, ucon);
-
-        rx_enabled(port) = 0;
-        spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static void s3c24xx_serial_stop_tx(struct uart_port *port)
-{
-        if (tx_enabled(port)) {
-                disable_irq(TX_IRQ(port));
-                tx_enabled(port) = 0;
-                if (port->flags & UPF_CONS_FLOW)
-                        s3c24xx_serial_rx_enable(port);
-        }
-}
-
-static void s3c24xx_serial_start_tx(struct uart_port *port)
-{
-        if (!tx_enabled(port)) {
-                if (port->flags & UPF_CONS_FLOW)
-                        s3c24xx_serial_rx_disable(port);
-
-                enable_irq(TX_IRQ(port));
-                tx_enabled(port) = 1;
-        }
-}
-
-
-static void s3c24xx_serial_stop_rx(struct uart_port *port)
-{
-        if (rx_enabled(port)) {
-                dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
-                disable_irq(RX_IRQ(port));
-                rx_enabled(port) = 0;
-        }
-}
-
-static void s3c24xx_serial_enable_ms(struct uart_port *port)
-{
-}
-
-static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
-{
-        return to_ourport(port)->info;
-}
-
-static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
-{
-        if (port->dev == NULL)
-                return NULL;
-
-        return (struct s3c2410_uartcfg *)port->dev->platform_data;
-}
-
-static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
-                                     unsigned long ufstat)
-{
-        struct s3c24xx_uart_info *info = ourport->info;
-
-        if (ufstat & info->rx_fifofull)
-                return info->fifosize;
-
-        return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
-}
-
-
-/* ? - where has parity gone?? */
-#define S3C2410_UERSTAT_PARITY (0x1000)
-
-static irqreturn_t
-s3c24xx_serial_rx_chars(int irq, void *dev_id)
-{
-        struct s3c24xx_uart_port *ourport = dev_id;
-        struct uart_port *port = &ourport->port;
-        struct tty_struct *tty = port->info->tty;
-        unsigned int ufcon, ch, flag, ufstat, uerstat;
-        int max_count = 64;
-
-        while (max_count-- > 0) {
-                ufcon = rd_regl(port, S3C2410_UFCON);
-                ufstat = rd_regl(port, S3C2410_UFSTAT);
-
-                if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
-                        break;
-
-                uerstat = rd_regl(port, S3C2410_UERSTAT);
-                ch = rd_regb(port, S3C2410_URXH);
-
-                if (port->flags & UPF_CONS_FLOW) {
-                        int txe = s3c24xx_serial_txempty_nofifo(port);
-
-                        if (rx_enabled(port)) {
-                                if (!txe) {
-                                        rx_enabled(port) = 0;
-                                        continue;
-                                }
-                        } else {
-                                if (txe) {
-                                        ufcon |= S3C2410_UFCON_RESETRX;
-                                        wr_regl(port, S3C2410_UFCON, ufcon);
-                                        rx_enabled(port) = 1;
-                                        goto out;
-                                }
-                                continue;
-                        }
-                }
-
-                /* insert the character into the buffer */
-
-                flag = TTY_NORMAL;
-                port->icount.rx++;
-
-                if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
-                        dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
-                            ch, uerstat);
-
-                        /* check for break */
-                        if (uerstat & S3C2410_UERSTAT_BREAK) {
-                                dbg("break!\n");
-                                port->icount.brk++;
-                                if (uart_handle_break(port))
-                                    goto ignore_char;
-                        }
-
-                        if (uerstat & S3C2410_UERSTAT_FRAME)
-                                port->icount.frame++;
-                        if (uerstat & S3C2410_UERSTAT_OVERRUN)
-                                port->icount.overrun++;
-
-                        uerstat &= port->read_status_mask;
-
-                        if (uerstat & S3C2410_UERSTAT_BREAK)
-                                flag = TTY_BREAK;
-                        else if (uerstat & S3C2410_UERSTAT_PARITY)
-                                flag = TTY_PARITY;
-                        else if (uerstat & ( S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_OVERRUN))
-                                flag = TTY_FRAME;
-                }
-
-                if (uart_handle_sysrq_char(port, ch))
-                        goto ignore_char;
-
-                uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, ch, flag);
-
-        ignore_char:
-                continue;
-        }
-        tty_flip_buffer_push(tty);
-
- out:
-        return IRQ_HANDLED;
-}
-
-static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
-{
-        struct s3c24xx_uart_port *ourport = id;
-        struct uart_port *port = &ourport->port;
-        struct circ_buf *xmit = &port->info->xmit;
-        int count = 256;
-
-        if (port->x_char) {
-                wr_regb(port, S3C2410_UTXH, port->x_char);
-                port->icount.tx++;
-                port->x_char = 0;
-                goto out;
-        }
-
-        /* if there isnt anything more to transmit, or the uart is now
-         * stopped, disable the uart and exit
-        */
-
-        if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
-                s3c24xx_serial_stop_tx(port);
-                goto out;
-        }
-
-        /* try and drain the buffer... */
-
-        while (!uart_circ_empty(xmit) && count-- > 0) {
-                if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
-                        break;
-
-                wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
-                xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
-                port->icount.tx++;
-        }
-
-        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
-                uart_write_wakeup(port);
-
-        if (uart_circ_empty(xmit))
-                s3c24xx_serial_stop_tx(port);
-
- out:
-        return IRQ_HANDLED;
-}
-
-static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
-{
-        struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
-        unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
-        unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
-
-        if (ufcon & S3C2410_UFCON_FIFOMODE) {
-                if ((ufstat & info->tx_fifomask) != 0 ||
-                    (ufstat & info->tx_fifofull))
-                        return 0;
-
-                return 1;
-        }
-
-        return s3c24xx_serial_txempty_nofifo(port);
-}
-
-/* no modem control lines */
-static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
-{
-        unsigned int umstat = rd_regb(port,S3C2410_UMSTAT);
-
-        if (umstat & S3C2410_UMSTAT_CTS)
-                return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
-        else
-                return TIOCM_CAR | TIOCM_DSR;
-}
-
-static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
-{
-        /* todo - possibly remove AFC and do manual CTS */
-}
-
-static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
-{
-        unsigned long flags;
-        unsigned int ucon;
-
-        spin_lock_irqsave(&port->lock, flags);
-
-        ucon = rd_regl(port, S3C2410_UCON);
-
-        if (break_state)
-                ucon |= S3C2410_UCON_SBREAK;
-        else
-                ucon &= ~S3C2410_UCON_SBREAK;
-
-        wr_regl(port, S3C2410_UCON, ucon);
-
-        spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static void s3c24xx_serial_shutdown(struct uart_port *port)
-{
-        struct s3c24xx_uart_port *ourport = to_ourport(port);
-
-        if (ourport->tx_claimed) {
-                free_irq(TX_IRQ(port), ourport);
-                tx_enabled(port) = 0;
-                ourport->tx_claimed = 0;
-        }
-
-        if (ourport->rx_claimed) {
-                free_irq(RX_IRQ(port), ourport);
-                ourport->rx_claimed = 0;
-                rx_enabled(port) = 0;
-        }
-}
-
-
-static int s3c24xx_serial_startup(struct uart_port *port)
-{
-        struct s3c24xx_uart_port *ourport = to_ourport(port);
-        int ret;
-
-        dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
-            port->mapbase, port->membase);
-
-        rx_enabled(port) = 1;
-
-        ret = request_irq(RX_IRQ(port),
-                          s3c24xx_serial_rx_chars, 0,
-                          s3c24xx_serial_portname(port), ourport);
-
-        if (ret != 0) {
-                printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
-                return ret;
-        }
-
-        ourport->rx_claimed = 1;
-
-        dbg("requesting tx irq...\n");
-
-        tx_enabled(port) = 1;
-
-        ret = request_irq(TX_IRQ(port),
-                          s3c24xx_serial_tx_chars, 0,
-                          s3c24xx_serial_portname(port), ourport);
-
-        if (ret) {
-                printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
-                goto err;
-        }
-
-        ourport->tx_claimed = 1;
-
-        dbg("s3c24xx_serial_startup ok\n");
-
-        /* the port reset code should have done the correct
-         * register setup for the port controls */
-
-        return ret;
-
- err:
-        s3c24xx_serial_shutdown(port);
-        return ret;
-}
-
-/* power power management control */
-
-static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
-                              unsigned int old)
-{
-        struct s3c24xx_uart_port *ourport = to_ourport(port);
-
-        switch (level) {
-        case 3:
-                if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
-                        clk_disable(ourport->baudclk);
-
-                clk_disable(ourport->clk);
-                break;
-
-        case 0:
-                clk_enable(ourport->clk);
-
-                if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
-                        clk_enable(ourport->baudclk);
-
-                break;
-        default:
-                printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
-        }
-}
-
-/* baud rate calculation
- *
- * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
- * of different sources, including the peripheral clock ("pclk") and an
- * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
- * with a programmable extra divisor.
- *
- * The following code goes through the clock sources, and calculates the
- * baud clocks (and the resultant actual baud rates) and then tries to
- * pick the closest one and select that.
- *
-*/
-
-
-#define MAX_CLKS (8)
-
-static struct s3c24xx_uart_clksrc tmp_clksrc = {
-        .name           = "pclk",
-        .min_baud       = 0,
-        .max_baud       = 0,
-        .divisor        = 1,
-};
-
-static inline int
-s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
-{
-        struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
-
-        return (info->get_clksrc)(port, c);
-}
-
-static inline int
-s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
-{
-        struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
-
-        return (info->set_clksrc)(port, c);
-}
-
-struct baud_calc {
-        struct s3c24xx_uart_clksrc      *clksrc;
-        unsigned int                     calc;
-        unsigned int                     quot;
-        struct clk                      *src;
-};
-
-static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
-                                   struct uart_port *port,
-                                   struct s3c24xx_uart_clksrc *clksrc,
-                                   unsigned int baud)
-{
-        unsigned long rate;
-
-        calc->src = clk_get(port->dev, clksrc->name);
-        if (calc->src == NULL || IS_ERR(calc->src))
-                return 0;
-
-        rate = clk_get_rate(calc->src);
-        rate /= clksrc->divisor;
-
-        calc->clksrc = clksrc;
-        calc->quot = (rate + (8 * baud)) / (16 * baud);
-        calc->calc = (rate / (calc->quot * 16));
-
-        calc->quot--;
-        return 1;
-}
-
-static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
-                                          struct s3c24xx_uart_clksrc **clksrc,
-                                          struct clk **clk,
-                                          unsigned int baud)
-{
-        struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
-        struct s3c24xx_uart_clksrc *clkp;
-        struct baud_calc res[MAX_CLKS];
-        struct baud_calc *resptr, *best, *sptr;
-        int i;
-
-        clkp = cfg->clocks;
-        best = NULL;
-
-        if (cfg->clocks_size < 2) {
-                if (cfg->clocks_size == 0)
-                        clkp = &tmp_clksrc;
-
-                /* check to see if we're sourcing fclk, and if so we're
-                 * going to have to update the clock source
-                 */
-
-                if (strcmp(clkp->name, "fclk") == 0) {
-                        struct s3c24xx_uart_clksrc src;
-
-                        s3c24xx_serial_getsource(port, &src);
-
-                        /* check that the port already using fclk, and if
-                         * not, then re-select fclk
-                         */
-
-                        if (strcmp(src.name, clkp->name) == 0) {
-                                s3c24xx_serial_setsource(port, clkp);
-                                s3c24xx_serial_getsource(port, &src);
-                        }
-
-                        clkp->divisor = src.divisor;
-                }
-
-                s3c24xx_serial_calcbaud(res, port, clkp, baud);
-                best = res;
-                resptr = best + 1;
-        } else {
-                resptr = res;
-
-                for (i = 0; i < cfg->clocks_size; i++, clkp++) {
-                        if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
-                                resptr++;
-                }
-        }
-
-        /* ok, we now need to select the best clock we found */
-
-        if (!best) {
-                unsigned int deviation = (1<<30)|((1<<30)-1);
-                int calc_deviation;
-
-                for (sptr = res; sptr < resptr; sptr++) {
-                        printk(KERN_DEBUG
-                               "found clk %p (%s) quot %d, calc %d\n",
-                               sptr->clksrc, sptr->clksrc->name,
-                               sptr->quot, sptr->calc);
-
-                        calc_deviation = baud - sptr->calc;
-                        if (calc_deviation < 0)
-                                calc_deviation = -calc_deviation;
-
-                        if (calc_deviation < deviation) {
-                                best = sptr;
-                                deviation = calc_deviation;
-                        }
-                }
-
-                printk(KERN_DEBUG "best %p (deviation %d)\n", best, deviation);
-        }
-
-        printk(KERN_DEBUG "selected clock %p (%s) quot %d, calc %d\n",
-               best->clksrc, best->clksrc->name, best->quot, best->calc);
-
-        /* store results to pass back */
-
-        *clksrc = best->clksrc;
-        *clk    = best->src;
-
-        return best->quot;
-}
-
-static void s3c24xx_serial_set_termios(struct uart_port *port,
-                                       struct ktermios *termios,
-                                       struct ktermios *old)
-{
-        struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
-        struct s3c24xx_uart_port *ourport = to_ourport(port);
-        struct s3c24xx_uart_clksrc *clksrc = NULL;
-        struct clk *clk = NULL;
-        unsigned long flags;
-        unsigned int baud, quot;
-        unsigned int ulcon;
-        unsigned int umcon;
-
-        /*
-         * We don't support modem control lines.
-         */
-        termios->c_cflag &= ~(HUPCL | CMSPAR);
-        termios->c_cflag |= CLOCAL;
-
-        /*
-         * Ask the core to calculate the divisor for us.
-         */
-
-        baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
-
-        if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
-                quot = port->custom_divisor;
-        else
-                quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
-
-        /* check to see if we need  to change clock source */
-
-        if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
-                s3c24xx_serial_setsource(port, clksrc);
-
-                if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
-                        clk_disable(ourport->baudclk);
-                        ourport->baudclk  = NULL;
-                }
-
-                clk_enable(clk);
-
-                ourport->clksrc = clksrc;
-                ourport->baudclk = clk;
-        }
-
-        switch (termios->c_cflag & CSIZE) {
-        case CS5:
-                dbg("config: 5bits/char\n");
-                ulcon = S3C2410_LCON_CS5;
-                break;
-        case CS6:
-                dbg("config: 6bits/char\n");
-                ulcon = S3C2410_LCON_CS6;
-                break;
-        case CS7:
-                dbg("config: 7bits/char\n");
-                ulcon = S3C2410_LCON_CS7;
-                break;
-        case CS8:
-        default:
-                dbg("config: 8bits/char\n");
-                ulcon = S3C2410_LCON_CS8;
-                break;
-        }
-
-        /* preserve original lcon IR settings */
-        ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
-
-        if (termios->c_cflag & CSTOPB)
-                ulcon |= S3C2410_LCON_STOPB;
-
-        umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
-
-        if (termios->c_cflag & PARENB) {
-                if (termios->c_cflag & PARODD)
-                        ulcon |= S3C2410_LCON_PODD;
-                else
-                        ulcon |= S3C2410_LCON_PEVEN;
-        } else {
-                ulcon |= S3C2410_LCON_PNONE;
-        }
-
-        spin_lock_irqsave(&port->lock, flags);
-
-        dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
-
-        wr_regl(port, S3C2410_ULCON, ulcon);
-        wr_regl(port, S3C2410_UBRDIV, quot);
-        wr_regl(port, S3C2410_UMCON, umcon);
-
-        dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
-            rd_regl(port, S3C2410_ULCON),
-            rd_regl(port, S3C2410_UCON),
-            rd_regl(port, S3C2410_UFCON));
-
-        /*
-         * Update the per-port timeout.
-         */
-        uart_update_timeout(port, termios->c_cflag, baud);
-
-        /*
-         * Which character status flags are we interested in?
-         */
-        port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
-        if (termios->c_iflag & INPCK)
-                port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
-
-        /*
-         * Which character status flags should we ignore?
-         */
-        port->ignore_status_mask = 0;
-        if (termios->c_iflag & IGNPAR)
-                port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
-        if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
-                port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
-
-        /*
-         * Ignore all characters if CREAD is not set.
-         */
-        if ((termios->c_cflag & CREAD) == 0)
-                port->ignore_status_mask |= RXSTAT_DUMMY_READ;
-
-        spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static const char *s3c24xx_serial_type(struct uart_port *port)
-{
-        switch (port->type) {
-        case PORT_S3C2410:
-                return "S3C2410";
-        case PORT_S3C2440:
-                return "S3C2440";
-        case PORT_S3C2412:
-                return "S3C2412";
-        default:
-                return NULL;
-        }
-}
-
-#define MAP_SIZE (0x100)
-
-static void s3c24xx_serial_release_port(struct uart_port *port)
-{
-        release_mem_region(port->mapbase, MAP_SIZE);
-}
-
-static int s3c24xx_serial_request_port(struct uart_port *port)
-{
-        const char *name = s3c24xx_serial_portname(port);
-        return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
-}
-
-static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
-{
-        struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
-
-        if (flags & UART_CONFIG_TYPE &&
-            s3c24xx_serial_request_port(port) == 0)
-                port->type = info->type;
-}
-
-/*
- * verify the new serial_struct (for TIOCSSERIAL).
- */
-static int
-s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
-{
-        struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
-
-        if (ser->type != PORT_UNKNOWN && ser->type != info->type)
-                return -EINVAL;
-
-        return 0;
-}
-
-
-#ifdef CONFIG_SERIAL_S3C2410_CONSOLE
-
-static struct console s3c24xx_serial_console;
-
-#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
-#else
-#define S3C24XX_SERIAL_CONSOLE NULL
-#endif
-
-static struct uart_ops s3c24xx_serial_ops = {
-        .pm             = s3c24xx_serial_pm,
-        .tx_empty       = s3c24xx_serial_tx_empty,
-        .get_mctrl      = s3c24xx_serial_get_mctrl,
-        .set_mctrl      = s3c24xx_serial_set_mctrl,
-        .stop_tx        = s3c24xx_serial_stop_tx,
-        .start_tx       = s3c24xx_serial_start_tx,
-        .stop_rx        = s3c24xx_serial_stop_rx,
-        .enable_ms      = s3c24xx_serial_enable_ms,
-        .break_ctl      = s3c24xx_serial_break_ctl,
-        .startup        = s3c24xx_serial_startup,
-        .shutdown       = s3c24xx_serial_shutdown,
-        .set_termios    = s3c24xx_serial_set_termios,
-        .type           = s3c24xx_serial_type,
-        .release_port   = s3c24xx_serial_release_port,
-        .request_port   = s3c24xx_serial_request_port,
-        .config_port    = s3c24xx_serial_config_port,
-        .verify_port    = s3c24xx_serial_verify_port,
-};
-
-
-static struct uart_driver s3c24xx_uart_drv = {
-        .owner          = THIS_MODULE,
-        .dev_name       = "s3c2410_serial",
-        .nr             = 3,
-        .cons           = S3C24XX_SERIAL_CONSOLE,
-        .driver_name    = S3C24XX_SERIAL_NAME,
-        .major          = S3C24XX_SERIAL_MAJOR,
-        .minor          = S3C24XX_SERIAL_MINOR,
-};
-
-static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
-        [0] = {
-                .port = {
-                        .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
-                        .iotype         = UPIO_MEM,
-                        .irq            = IRQ_S3CUART_RX0,
-                        .uartclk        = 0,
-                        .fifosize       = 16,
-                        .ops            = &s3c24xx_serial_ops,
-                        .flags          = UPF_BOOT_AUTOCONF,
-                        .line           = 0,
-                }
-        },
-        [1] = {
-                .port = {
-                        .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
-                        .iotype         = UPIO_MEM,
-                        .irq            = IRQ_S3CUART_RX1,
-                        .uartclk        = 0,
-                        .fifosize       = 16,
-                        .ops            = &s3c24xx_serial_ops,
-                        .flags          = UPF_BOOT_AUTOCONF,
-                        .line           = 1,
-                }
-        },
-#if NR_PORTS > 2
-
-        [2] = {
-                .port = {
-                        .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
-                        .iotype         = UPIO_MEM,
-                        .irq            = IRQ_S3CUART_RX2,
-                        .uartclk        = 0,
-                        .fifosize       = 16,
-                        .ops            = &s3c24xx_serial_ops,
-                        .flags          = UPF_BOOT_AUTOCONF,
-                        .line           = 2,
-                }
-        }
-#endif
-};
-
-/* s3c24xx_serial_resetport
- *
- * wrapper to call the specific reset for this port (reset the fifos
- * and the settings)
-*/
-
-static inline int s3c24xx_serial_resetport(struct uart_port * port,
-                                           struct s3c2410_uartcfg *cfg)
-{
-        struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
-
-        return (info->reset_port)(port, cfg);
-}
-
-/* s3c24xx_serial_init_port
- *
- * initialise a single serial port from the platform device given
- */
-
-static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
-                                    struct s3c24xx_uart_info *info,
-                                    struct platform_device *platdev)
-{
-        struct uart_port *port = &ourport->port;
-        struct s3c2410_uartcfg *cfg;
-        struct resource *res;
-        int ret;
-
-        dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
-
-        if (platdev == NULL)
-                return -ENODEV;
-
-        cfg = s3c24xx_dev_to_cfg(&platdev->dev);
-
-        if (port->mapbase != 0)
-                return 0;
-
-        if (cfg->hwport > 3)
-                return -EINVAL;
-
-        /* setup info for port */
-        port->dev       = &platdev->dev;
-        ourport->info   = info;
-
-        /* copy the info in from provided structure */
-        ourport->port.fifosize = info->fifosize;
-
-        dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
-
-        port->uartclk = 1;
-
-        if (cfg->uart_flags & UPF_CONS_FLOW) {
-                dbg("s3c24xx_serial_init_port: enabling flow control\n");
-                port->flags |= UPF_CONS_FLOW;
-        }
-
-        /* sort our the physical and virtual addresses for each UART */
-
-        res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
-        if (res == NULL) {
-                printk(KERN_ERR "failed to find memory resource for uart\n");
-                return -EINVAL;
-        }
-
-        dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
-
-        port->mapbase   = res->start;
-        port->membase   = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART);
-        ret = platform_get_irq(platdev, 0);
-        if (ret < 0)
-                port->irq = 0;
-        else
-                port->irq = ret;
-
-        ourport->clk    = clk_get(&platdev->dev, "uart");
-
-        dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
-            port->mapbase, port->membase, port->irq, port->uartclk);
-
-        /* reset the fifos (and setup the uart) */
-        s3c24xx_serial_resetport(port, cfg);
-        return 0;
-}
-
-/* Device driver serial port probe */
-
-static int probe_index = 0;
-
-static int s3c24xx_serial_probe(struct platform_device *dev,
-                                struct s3c24xx_uart_info *info)
-{
-        struct s3c24xx_uart_port *ourport;
-        int ret;
-
-        dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index);
-
-        ourport = &s3c24xx_serial_ports[probe_index];
-        probe_index++;
-
-        dbg("%s: initialising port %p...\n", __func__, ourport);
-
-        ret = s3c24xx_serial_init_port(ourport, info, dev);
-        if (ret < 0)
-                goto probe_err;
-
-        dbg("%s: adding port\n", __func__);
-        uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
-        platform_set_drvdata(dev, &ourport->port);
-
-        return 0;
-
- probe_err:
-        return ret;
-}
-
-static int s3c24xx_serial_remove(struct platform_device *dev)
-{
-        struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
-
-        if (port)
-                uart_remove_one_port(&s3c24xx_uart_drv, port);
-
-        return 0;
-}
-
-/* UART power management code */
-
-#ifdef CONFIG_PM
-
-static int s3c24xx_serial_suspend(struct platform_device *dev, pm_message_t state)
-{
-        struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
-
-        if (port)
-                uart_suspend_port(&s3c24xx_uart_drv, port);
-
-        return 0;
-}
-
-static int s3c24xx_serial_resume(struct platform_device *dev)
-{
-        struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
-        struct s3c24xx_uart_port *ourport = to_ourport(port);
-
-        if (port) {
-                clk_enable(ourport->clk);
-                s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
-                clk_disable(ourport->clk);
-
-                uart_resume_port(&s3c24xx_uart_drv, port);
-        }
-
-        return 0;
-}
-
-#else
-#define s3c24xx_serial_suspend NULL
-#define s3c24xx_serial_resume  NULL
-#endif
-
-static int s3c24xx_serial_init(struct platform_driver *drv,
-                               struct s3c24xx_uart_info *info)
-{
-        dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
-        return platform_driver_register(drv);
-}
-
-
-/* now comes the code to initialise either the s3c2410 or s3c2440 serial
- * port information
-*/
-
-/* cpu specific variations on the serial port support */
-
-#ifdef CONFIG_CPU_S3C2400
-
-static int s3c2400_serial_getsource(struct uart_port *port,
-                                    struct s3c24xx_uart_clksrc *clk)
-{
-        clk->divisor = 1;
-        clk->name = "pclk";
-
-        return 0;
-}
-
-static int s3c2400_serial_setsource(struct uart_port *port,
-                                    struct s3c24xx_uart_clksrc *clk)
-{
-        return 0;
-}
-
-static int s3c2400_serial_resetport(struct uart_port *port,
-                                    struct s3c2410_uartcfg *cfg)
-{
-        dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n",
-            port, port->mapbase, cfg);
-
-        wr_regl(port, S3C2410_UCON,  cfg->ucon);
-        wr_regl(port, S3C2410_ULCON, cfg->ulcon);
-
-        /* reset both fifos */
-
-        wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
-        wr_regl(port, S3C2410_UFCON, cfg->ufcon);
-
-        return 0;
-}
-
-static struct s3c24xx_uart_info s3c2400_uart_inf = {
-        .name           = "Samsung S3C2400 UART",
-        .type           = PORT_S3C2400,
-        .fifosize       = 16,
-        .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
-        .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
-        .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
-        .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
-        .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
-        .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
-        .get_clksrc     = s3c2400_serial_getsource,
-        .set_clksrc     = s3c2400_serial_setsource,
-        .reset_port     = s3c2400_serial_resetport,
-};
-
-static int s3c2400_serial_probe(struct platform_device *dev)
-{
-        return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
-}
-
-static struct platform_driver s3c2400_serial_drv = {
-        .probe          = s3c2400_serial_probe,
-        .remove         = s3c24xx_serial_remove,
-        .suspend        = s3c24xx_serial_suspend,
-        .resume         = s3c24xx_serial_resume,
-        .driver         = {
-                .name   = "s3c2400-uart",
-                .owner  = THIS_MODULE,
-        },
-};
-
-static inline int s3c2400_serial_init(void)
-{
-        return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
-}
-
-static inline void s3c2400_serial_exit(void)
-{
-        platform_driver_unregister(&s3c2400_serial_drv);
-}
-
-#define s3c2400_uart_inf_at &s3c2400_uart_inf
-#else
-
-static inline int s3c2400_serial_init(void)
-{
-        return 0;
-}
-
-static inline void s3c2400_serial_exit(void)
-{
-}
-
-#define s3c2400_uart_inf_at NULL
-
-#endif /* CONFIG_CPU_S3C2400 */
-
-/* S3C2410 support */
-
-#ifdef CONFIG_CPU_S3C2410
+#include "samsung.h"
 
 static int s3c2410_serial_setsource(struct uart_port *port,
                                     struct s3c24xx_uart_clksrc *clk)
@@ -1323,8 +83,6 @@ static struct s3c24xx_uart_info s3c2410_uart_inf = {
         .reset_port     = s3c2410_serial_resetport,
 };
 
-/* device management */
-
 static int s3c2410_serial_probe(struct platform_device *dev)
 {
         return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
@@ -1333,612 +91,28 @@ static int s3c2410_serial_probe(struct platform_device *dev)
 static struct platform_driver s3c2410_serial_drv = {
         .probe          = s3c2410_serial_probe,
         .remove         = s3c24xx_serial_remove,
-        .suspend        = s3c24xx_serial_suspend,
-        .resume         = s3c24xx_serial_resume,
         .driver         = {
                 .name   = "s3c2410-uart",
                 .owner  = THIS_MODULE,
         },
 };
 
-static inline int s3c2410_serial_init(void)
+s3c24xx_console_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
+
+static int __init s3c2410_serial_init(void)
 {
         return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
 }
 
-static inline void s3c2410_serial_exit(void)
+static void __exit s3c2410_serial_exit(void)
 {
         platform_driver_unregister(&s3c2410_serial_drv);
 }
 
-#define s3c2410_uart_inf_at &s3c2410_uart_inf
-#else
-
-static inline int s3c2410_serial_init(void)
-{
-        return 0;
-}
-
-static inline void s3c2410_serial_exit(void)
-{
-}
-
-#define s3c2410_uart_inf_at NULL
-
-#endif /* CONFIG_CPU_S3C2410 */
-
-#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
-
-static int s3c2440_serial_setsource(struct uart_port *port,
-                                     struct s3c24xx_uart_clksrc *clk)
-{
-        unsigned long ucon = rd_regl(port, S3C2410_UCON);
-
-        // todo - proper fclk<>nonfclk switch //
-
-        ucon &= ~S3C2440_UCON_CLKMASK;
-
-        if (strcmp(clk->name, "uclk") == 0)
-                ucon |= S3C2440_UCON_UCLK;
-        else if (strcmp(clk->name, "pclk") == 0)
-                ucon |= S3C2440_UCON_PCLK;
-        else if (strcmp(clk->name, "fclk") == 0)
-                ucon |= S3C2440_UCON_FCLK;
-        else {
-                printk(KERN_ERR "unknown clock source %s\n", clk->name);
-                return -EINVAL;
-        }
-
-        wr_regl(port, S3C2410_UCON, ucon);
-        return 0;
-}
-
-
-static int s3c2440_serial_getsource(struct uart_port *port,
-                                    struct s3c24xx_uart_clksrc *clk)
-{
-        unsigned long ucon = rd_regl(port, S3C2410_UCON);
-        unsigned long ucon0, ucon1, ucon2;
-
-        switch (ucon & S3C2440_UCON_CLKMASK) {
-        case S3C2440_UCON_UCLK:
-                clk->divisor = 1;
-                clk->name = "uclk";
-                break;
-
-        case S3C2440_UCON_PCLK:
-        case S3C2440_UCON_PCLK2:
-                clk->divisor = 1;
-                clk->name = "pclk";
-                break;
-
-        case S3C2440_UCON_FCLK:
-                /* the fun of calculating the uart divisors on
-                 * the s3c2440 */
-
-                ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
-                ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
-                ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
-
-                printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
-
-                ucon0 &= S3C2440_UCON0_DIVMASK;
-                ucon1 &= S3C2440_UCON1_DIVMASK;
-                ucon2 &= S3C2440_UCON2_DIVMASK;
-
-                if (ucon0 != 0) {
-                        clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
-                        clk->divisor += 6;
-                } else if (ucon1 != 0) {
-                        clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
-                        clk->divisor += 21;
-                } else if (ucon2 != 0) {
-                        clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
-                        clk->divisor += 36;
-                } else {
-                        /* manual calims 44, seems to be 9 */
-                        clk->divisor = 9;
-                }
-
-                clk->name = "fclk";
-                break;
-        }
-
-        return 0;
-}
-
-static int s3c2440_serial_resetport(struct uart_port *port,
-                                    struct s3c2410_uartcfg *cfg)
-{
-        unsigned long ucon = rd_regl(port, S3C2410_UCON);
-
-        dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
-            port, port->mapbase, cfg);
-
-        /* ensure we don't change the clock settings... */
-
-        ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
-
-        wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
-        wr_regl(port, S3C2410_ULCON, cfg->ulcon);
-
-        /* reset both fifos */
-
-        wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
-        wr_regl(port, S3C2410_UFCON, cfg->ufcon);
-
-        return 0;
-}
-
-static struct s3c24xx_uart_info s3c2440_uart_inf = {
-        .name           = "Samsung S3C2440 UART",
-        .type           = PORT_S3C2440,
-        .fifosize       = 64,
-        .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
-        .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
-        .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
-        .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
-        .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
-        .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
-        .get_clksrc     = s3c2440_serial_getsource,
-        .set_clksrc     = s3c2440_serial_setsource,
-        .reset_port     = s3c2440_serial_resetport,
-};
-
-/* device management */
-
-static int s3c2440_serial_probe(struct platform_device *dev)
-{
-        dbg("s3c2440_serial_probe: dev=%p\n", dev);
-        return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
-}
-
-static struct platform_driver s3c2440_serial_drv = {
-        .probe          = s3c2440_serial_probe,
-        .remove         = s3c24xx_serial_remove,
-        .suspend        = s3c24xx_serial_suspend,
-        .resume         = s3c24xx_serial_resume,
-        .driver         = {
-                .name   = "s3c2440-uart",
-                .owner  = THIS_MODULE,
-        },
-};
-
-
-static inline int s3c2440_serial_init(void)
-{
-        return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
-}
-
-static inline void s3c2440_serial_exit(void)
-{
-        platform_driver_unregister(&s3c2440_serial_drv);
-}
-
-#define s3c2440_uart_inf_at &s3c2440_uart_inf
-#else
-
-static inline int s3c2440_serial_init(void)
-{
-        return 0;
-}
-
-static inline void s3c2440_serial_exit(void)
-{
-}
-
-#define s3c2440_uart_inf_at NULL
-#endif /* CONFIG_CPU_S3C2440 */
-
-#if defined(CONFIG_CPU_S3C2412)
-
-static int s3c2412_serial_setsource(struct uart_port *port,
-                                     struct s3c24xx_uart_clksrc *clk)
-{
-        unsigned long ucon = rd_regl(port, S3C2410_UCON);
-
-        ucon &= ~S3C2412_UCON_CLKMASK;
-
-        if (strcmp(clk->name, "uclk") == 0)
-                ucon |= S3C2440_UCON_UCLK;
-        else if (strcmp(clk->name, "pclk") == 0)
-                ucon |= S3C2440_UCON_PCLK;
-        else if (strcmp(clk->name, "usysclk") == 0)
-                ucon |= S3C2412_UCON_USYSCLK;
-        else {
-                printk(KERN_ERR "unknown clock source %s\n", clk->name);
-                return -EINVAL;
-        }
-
-        wr_regl(port, S3C2410_UCON, ucon);
-        return 0;
-}
-
-
-static int s3c2412_serial_getsource(struct uart_port *port,
-                                    struct s3c24xx_uart_clksrc *clk)
-{
-        unsigned long ucon = rd_regl(port, S3C2410_UCON);
-
-        switch (ucon & S3C2412_UCON_CLKMASK) {
-        case S3C2412_UCON_UCLK:
-                clk->divisor = 1;
-                clk->name = "uclk";
-                break;
-
-        case S3C2412_UCON_PCLK:
-        case S3C2412_UCON_PCLK2:
-                clk->divisor = 1;
-                clk->name = "pclk";
-                break;
-
-        case S3C2412_UCON_USYSCLK:
-                clk->divisor = 1;
-                clk->name = "usysclk";
-                break;
-        }
-
-        return 0;
-}
-
-static int s3c2412_serial_resetport(struct uart_port *port,
-                                    struct s3c2410_uartcfg *cfg)
-{
-        unsigned long ucon = rd_regl(port, S3C2410_UCON);
-
-        dbg("%s: port=%p (%08lx), cfg=%p\n",
-            __func__, port, port->mapbase, cfg);
-
-        /* ensure we don't change the clock settings... */
-
-        ucon &= S3C2412_UCON_CLKMASK;
-
-        wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
-        wr_regl(port, S3C2410_ULCON, cfg->ulcon);
-
-        /* reset both fifos */
-
-        wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
-        wr_regl(port, S3C2410_UFCON, cfg->ufcon);
-
-        return 0;
-}
-
-static struct s3c24xx_uart_info s3c2412_uart_inf = {
-        .name           = "Samsung S3C2412 UART",
-        .type           = PORT_S3C2412,
-        .fifosize       = 64,
-        .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
-        .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
-        .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
-        .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
-        .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
-        .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
-        .get_clksrc     = s3c2412_serial_getsource,
-        .set_clksrc     = s3c2412_serial_setsource,
-        .reset_port     = s3c2412_serial_resetport,
-};
-
-/* device management */
-
-static int s3c2412_serial_probe(struct platform_device *dev)
-{
-        dbg("s3c2440_serial_probe: dev=%p\n", dev);
-        return s3c24xx_serial_probe(dev, &s3c2412_uart_inf);
-}
-
-static struct platform_driver s3c2412_serial_drv = {
-        .probe          = s3c2412_serial_probe,
-        .remove         = s3c24xx_serial_remove,
-        .suspend        = s3c24xx_serial_suspend,
-        .resume         = s3c24xx_serial_resume,
-        .driver         = {
-                .name   = "s3c2412-uart",
-                .owner  = THIS_MODULE,
-        },
-};
-
-
-static inline int s3c2412_serial_init(void)
-{
-        return s3c24xx_serial_init(&s3c2412_serial_drv, &s3c2412_uart_inf);
-}
-
-static inline void s3c2412_serial_exit(void)
-{
-        platform_driver_unregister(&s3c2412_serial_drv);
-}
-
-#define s3c2412_uart_inf_at &s3c2412_uart_inf
-#else
-
-static inline int s3c2412_serial_init(void)
-{
-        return 0;
-}
-
-static inline void s3c2412_serial_exit(void)
-{
-}
-
-#define s3c2412_uart_inf_at NULL
-#endif /* CONFIG_CPU_S3C2440 */
-
-
-/* module initialisation code */
-
-static int __init s3c24xx_serial_modinit(void)
-{
-        int ret;
-
-        ret = uart_register_driver(&s3c24xx_uart_drv);
-        if (ret < 0) {
-                printk(KERN_ERR "failed to register UART driver\n");
-                return -1;
-        }
-
-        s3c2400_serial_init();
-        s3c2410_serial_init();
-        s3c2412_serial_init();
-        s3c2440_serial_init();
-
-        return 0;
-}
-
-static void __exit s3c24xx_serial_modexit(void)
-{
-        s3c2400_serial_exit();
-        s3c2410_serial_exit();
-        s3c2412_serial_exit();
-        s3c2440_serial_exit();
-
-        uart_unregister_driver(&s3c24xx_uart_drv);
-}
-
-
-module_init(s3c24xx_serial_modinit);
-module_exit(s3c24xx_serial_modexit);
-
-/* Console code */
-
-#ifdef CONFIG_SERIAL_S3C2410_CONSOLE
-
-static struct uart_port *cons_uart;
-
-static int
-s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
-{
-        struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
-        unsigned long ufstat, utrstat;
-
-        if (ufcon & S3C2410_UFCON_FIFOMODE) {
-                /* fifo mode - check ammount of data in fifo registers... */
-
-                ufstat = rd_regl(port, S3C2410_UFSTAT);
-                return (ufstat & info->tx_fifofull) ? 0 : 1;
-        }
-
-        /* in non-fifo mode, we go and use the tx buffer empty */
-
-        utrstat = rd_regl(port, S3C2410_UTRSTAT);
-        return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
-}
-
-static void
-s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
-{
-        unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
-        while (!s3c24xx_serial_console_txrdy(port, ufcon))
-                barrier();
-        wr_regb(cons_uart, S3C2410_UTXH, ch);
-}
-
-static void
-s3c24xx_serial_console_write(struct console *co, const char *s,
-                             unsigned int count)
-{
-        uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
-}
-
-static void __init
-s3c24xx_serial_get_options(struct uart_port *port, int *baud,
-                           int *parity, int *bits)
-{
-        struct s3c24xx_uart_clksrc clksrc;
-        struct clk *clk;
-        unsigned int ulcon;
-        unsigned int ucon;
-        unsigned int ubrdiv;
-        unsigned long rate;
-
-        ulcon  = rd_regl(port, S3C2410_ULCON);
-        ucon   = rd_regl(port, S3C2410_UCON);
-        ubrdiv = rd_regl(port, S3C2410_UBRDIV);
-
-        dbg("s3c24xx_serial_get_options: port=%p\n"
-            "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
-            port, ulcon, ucon, ubrdiv);
-
-        if ((ucon & 0xf) != 0) {
-                /* consider the serial port configured if the tx/rx mode set */
-
-                switch (ulcon & S3C2410_LCON_CSMASK) {
-                case S3C2410_LCON_CS5:
-                        *bits = 5;
-                        break;
-                case S3C2410_LCON_CS6:
-                        *bits = 6;
-                        break;
-                case S3C2410_LCON_CS7:
-                        *bits = 7;
-                        break;
-                default:
-                case S3C2410_LCON_CS8:
-                        *bits = 8;
-                        break;
-                }
-
-                switch (ulcon & S3C2410_LCON_PMASK) {
-                case S3C2410_LCON_PEVEN:
-                        *parity = 'e';
-                        break;
-
-                case S3C2410_LCON_PODD:
-                        *parity = 'o';
-                        break;
-
-                case S3C2410_LCON_PNONE:
-                default:
-                        *parity = 'n';
-                }
-
-                /* now calculate the baud rate */
-
-                s3c24xx_serial_getsource(port, &clksrc);
-
-                clk = clk_get(port->dev, clksrc.name);
-                if (!IS_ERR(clk) && clk != NULL)
-                        rate = clk_get_rate(clk) / clksrc.divisor;
-                else
-                        rate = 1;
-
-
-                *baud = rate / ( 16 * (ubrdiv + 1));
-                dbg("calculated baud %d\n", *baud);
-        }
-
-}
-
-/* s3c24xx_serial_init_ports
- *
- * initialise the serial ports from the machine provided initialisation
- * data.
-*/
-
-static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
-{
-        struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
-        struct platform_device **platdev_ptr;
-        int i;
-
-        dbg("s3c24xx_serial_init_ports: initialising ports...\n");
-
-        platdev_ptr = s3c24xx_uart_devs;
-
-        for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
-                s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
-        }
-
-        return 0;
-}
-
-static int __init
-s3c24xx_serial_console_setup(struct console *co, char *options)
-{
-        struct uart_port *port;
-        int baud = 9600;
-        int bits = 8;
-        int parity = 'n';
-        int flow = 'n';
-
-        dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
-            co, co->index, options);
-
-        /* is this a valid port */
-
-        if (co->index == -1 || co->index >= NR_PORTS)
-                co->index = 0;
-
-        port = &s3c24xx_serial_ports[co->index].port;
-
-        /* is the port configured? */
-
-        if (port->mapbase == 0x0) {
-                co->index = 0;
-                port = &s3c24xx_serial_ports[co->index].port;
-        }
-
-        cons_uart = port;
-
-        dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
-
-        /*
-         * Check whether an invalid uart number has been specified, and
-         * if so, search for the first available port that does have
-         * console support.
-         */
-        if (options)
-                uart_parse_options(options, &baud, &parity, &bits, &flow);
-        else
-                s3c24xx_serial_get_options(port, &baud, &parity, &bits);
-
-        dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
-
-        return uart_set_options(port, co, baud, parity, bits, flow);
-}
-
-/* s3c24xx_serial_initconsole
- *
- * initialise the console from one of the uart drivers
-*/
-
-static struct console s3c24xx_serial_console =
-{
-        .name           = S3C24XX_SERIAL_NAME,
-        .device         = uart_console_device,
-        .flags          = CON_PRINTBUFFER,
-        .index          = -1,
-        .write          = s3c24xx_serial_console_write,
-        .setup          = s3c24xx_serial_console_setup
-};
-
-static int s3c24xx_serial_initconsole(void)
-{
-        struct s3c24xx_uart_info *info;
-        struct platform_device *dev = s3c24xx_uart_devs[0];
-
-        dbg("s3c24xx_serial_initconsole\n");
-
-        /* select driver based on the cpu */
-
-        if (dev == NULL) {
-                printk(KERN_ERR "s3c24xx: no devices for console init\n");
-                return 0;
-        }
-
-        if (strcmp(dev->name, "s3c2400-uart") == 0) {
-                info = s3c2400_uart_inf_at;
-        } else if (strcmp(dev->name, "s3c2410-uart") == 0) {
-                info = s3c2410_uart_inf_at;
-        } else if (strcmp(dev->name, "s3c2440-uart") == 0) {
-                info = s3c2440_uart_inf_at;
-        } else if (strcmp(dev->name, "s3c2412-uart") == 0) {
-                info = s3c2412_uart_inf_at;
-        } else {
-                printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name);
-                return 0;
-        }
-
-        if (info == NULL) {
-                printk(KERN_ERR "s3c24xx: no driver for console\n");
-                return 0;
-        }
-
-        s3c24xx_serial_console.data = &s3c24xx_uart_drv;
-        s3c24xx_serial_init_ports(info);
-
-        register_console(&s3c24xx_serial_console);
-        return 0;
-}
-
-console_initcall(s3c24xx_serial_initconsole);
-
-#endif /* CONFIG_SERIAL_S3C2410_CONSOLE */
+module_init(s3c2410_serial_init);
+module_exit(s3c2410_serial_exit);
 
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
-MODULE_DESCRIPTION("Samsung S3C2410/S3C2440/S3C2412 Serial port driver");
-MODULE_ALIAS("platform:s3c2400-uart");
+MODULE_DESCRIPTION("Samsung S3C2410 SoC Serial port driver");
 MODULE_ALIAS("platform:s3c2410-uart");
-MODULE_ALIAS("platform:s3c2412-uart");
-MODULE_ALIAS("platform:s3c2440-uart");
diff --git a/drivers/serial/s3c2412.c b/drivers/serial/s3c2412.c
new file mode 100644
index 000000000000..ce0c220e3e92
--- /dev/null
+++ b/drivers/serial/s3c2412.c
@@ -0,0 +1,151 @@
+/* linux/drivers/serial/s3c2412.c
+ *
+ * Driver for Samsung S3C2412 and S3C2413 SoC onboard UARTs.
+ *
+ * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+
+#include <asm/irq.h>
+#include <asm/hardware.h>
+
+#include <asm/plat-s3c/regs-serial.h>
+#include <asm/arch/regs-gpio.h>
+
+#include "samsung.h"
+
+static int s3c2412_serial_setsource(struct uart_port *port,
+                                     struct s3c24xx_uart_clksrc *clk)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        ucon &= ~S3C2412_UCON_CLKMASK;
+
+        if (strcmp(clk->name, "uclk") == 0)
+                ucon |= S3C2440_UCON_UCLK;
+        else if (strcmp(clk->name, "pclk") == 0)
+                ucon |= S3C2440_UCON_PCLK;
+        else if (strcmp(clk->name, "usysclk") == 0)
+                ucon |= S3C2412_UCON_USYSCLK;
+        else {
+                printk(KERN_ERR "unknown clock source %s\n", clk->name);
+                return -EINVAL;
+        }
+
+        wr_regl(port, S3C2410_UCON, ucon);
+        return 0;
+}
+
+
+static int s3c2412_serial_getsource(struct uart_port *port,
+                                    struct s3c24xx_uart_clksrc *clk)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        switch (ucon & S3C2412_UCON_CLKMASK) {
+        case S3C2412_UCON_UCLK:
+                clk->divisor = 1;
+                clk->name = "uclk";
+                break;
+
+        case S3C2412_UCON_PCLK:
+        case S3C2412_UCON_PCLK2:
+                clk->divisor = 1;
+                clk->name = "pclk";
+                break;
+
+        case S3C2412_UCON_USYSCLK:
+                clk->divisor = 1;
+                clk->name = "usysclk";
+                break;
+        }
+
+        return 0;
+}
+
+static int s3c2412_serial_resetport(struct uart_port *port,
+                                    struct s3c2410_uartcfg *cfg)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        dbg("%s: port=%p (%08lx), cfg=%p\n",
+            __func__, port, port->mapbase, cfg);
+
+        /* ensure we don't change the clock settings... */
+
+        ucon &= S3C2412_UCON_CLKMASK;
+
+        wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
+        wr_regl(port, S3C2410_ULCON, cfg->ulcon);
+
+        /* reset both fifos */
+
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon);
+
+        return 0;
+}
+
+static struct s3c24xx_uart_info s3c2412_uart_inf = {
+        .name           = "Samsung S3C2412 UART",
+        .type           = PORT_S3C2412,
+        .fifosize       = 64,
+        .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
+        .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
+        .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
+        .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
+        .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
+        .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
+        .get_clksrc     = s3c2412_serial_getsource,
+        .set_clksrc     = s3c2412_serial_setsource,
+        .reset_port     = s3c2412_serial_resetport,
+};
+
+/* device management */
+
+static int s3c2412_serial_probe(struct platform_device *dev)
+{
+        dbg("s3c2440_serial_probe: dev=%p\n", dev);
+        return s3c24xx_serial_probe(dev, &s3c2412_uart_inf);
+}
+
+static struct platform_driver s3c2412_serial_drv = {
+        .probe          = s3c2412_serial_probe,
+        .remove         = s3c24xx_serial_remove,
+        .driver         = {
+                .name   = "s3c2412-uart",
+                .owner  = THIS_MODULE,
+        },
+};
+
+s3c24xx_console_init(&s3c2412_serial_drv, &s3c2412_uart_inf);
+
+static inline int s3c2412_serial_init(void)
+{
+        return s3c24xx_serial_init(&s3c2412_serial_drv, &s3c2412_uart_inf);
+}
+
+static inline void s3c2412_serial_exit(void)
+{
+        platform_driver_unregister(&s3c2412_serial_drv);
+}
+
+module_init(s3c2412_serial_init);
+module_exit(s3c2412_serial_exit);
+
+MODULE_DESCRIPTION("Samsung S3C2412,S3C2413 SoC Serial port driver");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:s3c2412-uart");
diff --git a/drivers/serial/s3c2440.c b/drivers/serial/s3c2440.c
new file mode 100644
index 000000000000..38f954bd39c6
--- /dev/null
+++ b/drivers/serial/s3c2440.c
@@ -0,0 +1,181 @@
+/* linux/drivers/serial/s3c2440.c
+ *
+ * Driver for Samsung S3C2440 and S3C2442 SoC onboard UARTs.
+ *
+ * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+
+#include <asm/irq.h>
+#include <asm/hardware.h>
+
+#include <asm/plat-s3c/regs-serial.h>
+#include <asm/arch/regs-gpio.h>
+
+#include "samsung.h"
+
+
+static int s3c2440_serial_setsource(struct uart_port *port,
+                                     struct s3c24xx_uart_clksrc *clk)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        /* todo - proper fclk<>nonfclk switch. */
+
+        ucon &= ~S3C2440_UCON_CLKMASK;
+
+        if (strcmp(clk->name, "uclk") == 0)
+                ucon |= S3C2440_UCON_UCLK;
+        else if (strcmp(clk->name, "pclk") == 0)
+                ucon |= S3C2440_UCON_PCLK;
+        else if (strcmp(clk->name, "fclk") == 0)
+                ucon |= S3C2440_UCON_FCLK;
+        else {
+                printk(KERN_ERR "unknown clock source %s\n", clk->name);
+                return -EINVAL;
+        }
+
+        wr_regl(port, S3C2410_UCON, ucon);
+        return 0;
+}
+
+
+static int s3c2440_serial_getsource(struct uart_port *port,
+                                    struct s3c24xx_uart_clksrc *clk)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+        unsigned long ucon0, ucon1, ucon2;
+
+        switch (ucon & S3C2440_UCON_CLKMASK) {
+        case S3C2440_UCON_UCLK:
+                clk->divisor = 1;
+                clk->name = "uclk";
+                break;
+
+        case S3C2440_UCON_PCLK:
+        case S3C2440_UCON_PCLK2:
+                clk->divisor = 1;
+                clk->name = "pclk";
+                break;
+
+        case S3C2440_UCON_FCLK:
+                /* the fun of calculating the uart divisors on
+                 * the s3c2440 */
+
+                ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
+                ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
+                ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
+
+                printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
+
+                ucon0 &= S3C2440_UCON0_DIVMASK;
+                ucon1 &= S3C2440_UCON1_DIVMASK;
+                ucon2 &= S3C2440_UCON2_DIVMASK;
+
+                if (ucon0 != 0) {
+                        clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
+                        clk->divisor += 6;
+                } else if (ucon1 != 0) {
+                        clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
+                        clk->divisor += 21;
+                } else if (ucon2 != 0) {
+                        clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
+                        clk->divisor += 36;
+                } else {
+                        /* manual calims 44, seems to be 9 */
+                        clk->divisor = 9;
+                }
+
+                clk->name = "fclk";
+                break;
+        }
+
+        return 0;
+}
+
+static int s3c2440_serial_resetport(struct uart_port *port,
+                                    struct s3c2410_uartcfg *cfg)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
+            port, port->mapbase, cfg);
+
+        /* ensure we don't change the clock settings... */
+
+        ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
+
+        wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
+        wr_regl(port, S3C2410_ULCON, cfg->ulcon);
+
+        /* reset both fifos */
+
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon);
+
+        return 0;
+}
+
+static struct s3c24xx_uart_info s3c2440_uart_inf = {
+        .name           = "Samsung S3C2440 UART",
+        .type           = PORT_S3C2440,
+        .fifosize       = 64,
+        .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
+        .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
+        .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
+        .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
+        .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
+        .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
+        .get_clksrc     = s3c2440_serial_getsource,
+        .set_clksrc     = s3c2440_serial_setsource,
+        .reset_port     = s3c2440_serial_resetport,
+};
+
+/* device management */
+
+static int s3c2440_serial_probe(struct platform_device *dev)
+{
+        dbg("s3c2440_serial_probe: dev=%p\n", dev);
+        return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
+}
+
+static struct platform_driver s3c2440_serial_drv = {
+        .probe          = s3c2440_serial_probe,
+        .remove         = s3c24xx_serial_remove,
+        .driver         = {
+                .name   = "s3c2440-uart",
+                .owner  = THIS_MODULE,
+        },
+};
+
+s3c24xx_console_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
+
+static int __init s3c2440_serial_init(void)
+{
+        return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
+}
+
+static void __exit s3c2440_serial_exit(void)
+{
+        platform_driver_unregister(&s3c2440_serial_drv);
+}
+
+module_init(s3c2440_serial_init);
+module_exit(s3c2440_serial_exit);
+
+MODULE_DESCRIPTION("Samsung S3C2440,S3C2442 SoC Serial port driver");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_LICENSE("GPLi v2");
+MODULE_ALIAS("platform:s3c2440-uart");
diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c
new file mode 100644
index 000000000000..4a3ecaa629e6
--- /dev/null
+++ b/drivers/serial/samsung.c
@@ -0,0 +1,1317 @@
+/* linux/drivers/serial/samsuing.c
+ *
+ * Driver core for Samsung SoC onboard UARTs.
+ *
+ * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Hote on 2410 error handling
+ *
+ * The s3c2410 manual has a love/hate affair with the contents of the
+ * UERSTAT register in the UART blocks, and keeps marking some of the
+ * error bits as reserved. Having checked with the s3c2410x01,
+ * it copes with BREAKs properly, so I am happy to ignore the RESERVED
+ * feature from the latter versions of the manual.
+ *
+ * If it becomes aparrent that latter versions of the 2410 remove these
+ * bits, then action will have to be taken to differentiate the versions
+ * and change the policy on BREAK
+ *
+ * BJD, 04-Nov-2004
+*/
+
+#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/sysrq.h>
+#include <linux/console.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+
+#include <asm/irq.h>
+
+#include <asm/hardware.h>
+
+#include <asm/plat-s3c/regs-serial.h>
+#include <asm/arch/regs-gpio.h>
+
+#include "samsung.h"
+
+/* UART name and device definitions */
+
+#define S3C24XX_SERIAL_NAME     "ttySAC"
+#define S3C24XX_SERIAL_MAJOR    204
+#define S3C24XX_SERIAL_MINOR    64
+
+/* we can support 3 uarts, but not always use them */
+
+#ifdef CONFIG_CPU_S3C2400
+#define NR_PORTS (2)
+#else
+#define NR_PORTS (3)
+#endif
+
+/* port irq numbers */
+
+#define TX_IRQ(port) ((port)->irq + 1)
+#define RX_IRQ(port) ((port)->irq)
+
+/* macros to change one thing to another */
+
+#define tx_enabled(port) ((port)->unused[0])
+#define rx_enabled(port) ((port)->unused[1])
+
+/* flag to ignore all characters comming in */
+#define RXSTAT_DUMMY_READ (0x10000000)
+
+static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
+{
+        return container_of(port, struct s3c24xx_uart_port, port);
+}
+
+/* translate a port to the device name */
+
+static inline const char *s3c24xx_serial_portname(struct uart_port *port)
+{
+        return to_platform_device(port->dev)->name;
+}
+
+static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
+{
+        return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
+}
+
+static void s3c24xx_serial_rx_enable(struct uart_port *port)
+{
+        unsigned long flags;
+        unsigned int ucon, ufcon;
+        int count = 10000;
+
+        spin_lock_irqsave(&port->lock, flags);
+
+        while (--count && !s3c24xx_serial_txempty_nofifo(port))
+                udelay(100);
+
+        ufcon = rd_regl(port, S3C2410_UFCON);
+        ufcon |= S3C2410_UFCON_RESETRX;
+        wr_regl(port, S3C2410_UFCON, ufcon);
+
+        ucon = rd_regl(port, S3C2410_UCON);
+        ucon |= S3C2410_UCON_RXIRQMODE;
+        wr_regl(port, S3C2410_UCON, ucon);
+
+        rx_enabled(port) = 1;
+        spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void s3c24xx_serial_rx_disable(struct uart_port *port)
+{
+        unsigned long flags;
+        unsigned int ucon;
+
+        spin_lock_irqsave(&port->lock, flags);
+
+        ucon = rd_regl(port, S3C2410_UCON);
+        ucon &= ~S3C2410_UCON_RXIRQMODE;
+        wr_regl(port, S3C2410_UCON, ucon);
+
+        rx_enabled(port) = 0;
+        spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void s3c24xx_serial_stop_tx(struct uart_port *port)
+{
+        if (tx_enabled(port)) {
+                disable_irq(TX_IRQ(port));
+                tx_enabled(port) = 0;
+                if (port->flags & UPF_CONS_FLOW)
+                        s3c24xx_serial_rx_enable(port);
+        }
+}
+
+static void s3c24xx_serial_start_tx(struct uart_port *port)
+{
+        if (!tx_enabled(port)) {
+                if (port->flags & UPF_CONS_FLOW)
+                        s3c24xx_serial_rx_disable(port);
+
+                enable_irq(TX_IRQ(port));
+                tx_enabled(port) = 1;
+        }
+}
+
+
+static void s3c24xx_serial_stop_rx(struct uart_port *port)
+{
+        if (rx_enabled(port)) {
+                dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
+                disable_irq(RX_IRQ(port));
+                rx_enabled(port) = 0;
+        }
+}
+
+static void s3c24xx_serial_enable_ms(struct uart_port *port)
+{
+}
+
+static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
+{
+        return to_ourport(port)->info;
+}
+
+static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
+{
+        if (port->dev == NULL)
+                return NULL;
+
+        return (struct s3c2410_uartcfg *)port->dev->platform_data;
+}
+
+static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
+                                     unsigned long ufstat)
+{
+        struct s3c24xx_uart_info *info = ourport->info;
+
+        if (ufstat & info->rx_fifofull)
+                return info->fifosize;
+
+        return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
+}
+
+
+/* ? - where has parity gone?? */
+#define S3C2410_UERSTAT_PARITY (0x1000)
+
+static irqreturn_t
+s3c24xx_serial_rx_chars(int irq, void *dev_id)
+{
+        struct s3c24xx_uart_port *ourport = dev_id;
+        struct uart_port *port = &ourport->port;
+        struct tty_struct *tty = port->info->tty;
+        unsigned int ufcon, ch, flag, ufstat, uerstat;
+        int max_count = 64;
+
+        while (max_count-- > 0) {
+                ufcon = rd_regl(port, S3C2410_UFCON);
+                ufstat = rd_regl(port, S3C2410_UFSTAT);
+
+                if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
+                        break;
+
+                uerstat = rd_regl(port, S3C2410_UERSTAT);
+                ch = rd_regb(port, S3C2410_URXH);
+
+                if (port->flags & UPF_CONS_FLOW) {
+                        int txe = s3c24xx_serial_txempty_nofifo(port);
+
+                        if (rx_enabled(port)) {
+                                if (!txe) {
+                                        rx_enabled(port) = 0;
+                                        continue;
+                                }
+                        } else {
+                                if (txe) {
+                                        ufcon |= S3C2410_UFCON_RESETRX;
+                                        wr_regl(port, S3C2410_UFCON, ufcon);
+                                        rx_enabled(port) = 1;
+                                        goto out;
+                                }
+                                continue;
+                        }
+                }
+
+                /* insert the character into the buffer */
+
+                flag = TTY_NORMAL;
+                port->icount.rx++;
+
+                if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
+                        dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
+                            ch, uerstat);
+
+                        /* check for break */
+                        if (uerstat & S3C2410_UERSTAT_BREAK) {
+                                dbg("break!\n");
+                                port->icount.brk++;
+                                if (uart_handle_break(port))
+                                    goto ignore_char;
+                        }
+
+                        if (uerstat & S3C2410_UERSTAT_FRAME)
+                                port->icount.frame++;
+                        if (uerstat & S3C2410_UERSTAT_OVERRUN)
+                                port->icount.overrun++;
+
+                        uerstat &= port->read_status_mask;
+
+                        if (uerstat & S3C2410_UERSTAT_BREAK)
+                                flag = TTY_BREAK;
+                        else if (uerstat & S3C2410_UERSTAT_PARITY)
+                                flag = TTY_PARITY;
+                        else if (uerstat & (S3C2410_UERSTAT_FRAME |
+                                            S3C2410_UERSTAT_OVERRUN))
+                                flag = TTY_FRAME;
+                }
+
+                if (uart_handle_sysrq_char(port, ch))
+                        goto ignore_char;
+
+                uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
+                                 ch, flag);
+
+ ignore_char:
+                continue;
+        }
+        tty_flip_buffer_push(tty);
+
+ out:
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
+{
+        struct s3c24xx_uart_port *ourport = id;
+        struct uart_port *port = &ourport->port;
+        struct circ_buf *xmit = &port->info->xmit;
+        int count = 256;
+
+        if (port->x_char) {
+                wr_regb(port, S3C2410_UTXH, port->x_char);
+                port->icount.tx++;
+                port->x_char = 0;
+                goto out;
+        }
+
+        /* if there isnt anything more to transmit, or the uart is now
+         * stopped, disable the uart and exit
+        */
+
+        if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
+                s3c24xx_serial_stop_tx(port);
+                goto out;
+        }
+
+        /* try and drain the buffer... */
+
+        while (!uart_circ_empty(xmit) && count-- > 0) {
+                if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
+                        break;
+
+                wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
+                xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+                port->icount.tx++;
+        }
+
+        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+                uart_write_wakeup(port);
+
+        if (uart_circ_empty(xmit))
+                s3c24xx_serial_stop_tx(port);
+
+ out:
+        return IRQ_HANDLED;
+}
+
+static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
+{
+        struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
+        unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
+        unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
+
+        if (ufcon & S3C2410_UFCON_FIFOMODE) {
+                if ((ufstat & info->tx_fifomask) != 0 ||
+                    (ufstat & info->tx_fifofull))
+                        return 0;
+
+                return 1;
+        }
+
+        return s3c24xx_serial_txempty_nofifo(port);
+}
+
+/* no modem control lines */
+static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
+{
+        unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
+
+        if (umstat & S3C2410_UMSTAT_CTS)
+                return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
+        else
+                return TIOCM_CAR | TIOCM_DSR;
+}
+
+static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+        /* todo - possibly remove AFC and do manual CTS */
+}
+
+static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
+{
+        unsigned long flags;
+        unsigned int ucon;
+
+        spin_lock_irqsave(&port->lock, flags);
+
+        ucon = rd_regl(port, S3C2410_UCON);
+
+        if (break_state)
+                ucon |= S3C2410_UCON_SBREAK;
+        else
+                ucon &= ~S3C2410_UCON_SBREAK;
+
+        wr_regl(port, S3C2410_UCON, ucon);
+
+        spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void s3c24xx_serial_shutdown(struct uart_port *port)
+{
+        struct s3c24xx_uart_port *ourport = to_ourport(port);
+
+        if (ourport->tx_claimed) {
+                free_irq(TX_IRQ(port), ourport);
+                tx_enabled(port) = 0;
+                ourport->tx_claimed = 0;
+        }
+
+        if (ourport->rx_claimed) {
+                free_irq(RX_IRQ(port), ourport);
+                ourport->rx_claimed = 0;
+                rx_enabled(port) = 0;
+        }
+}
+
+
+static int s3c24xx_serial_startup(struct uart_port *port)
+{
+        struct s3c24xx_uart_port *ourport = to_ourport(port);
+        int ret;
+
+        dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
+            port->mapbase, port->membase);
+
+        rx_enabled(port) = 1;
+
+        ret = request_irq(RX_IRQ(port),
+                          s3c24xx_serial_rx_chars, 0,
+                          s3c24xx_serial_portname(port), ourport);
+
+        if (ret != 0) {
+                printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
+                return ret;
+        }
+
+        ourport->rx_claimed = 1;
+
+        dbg("requesting tx irq...\n");
+
+        tx_enabled(port) = 1;
+
+        ret = request_irq(TX_IRQ(port),
+                          s3c24xx_serial_tx_chars, 0,
+                          s3c24xx_serial_portname(port), ourport);
+
+        if (ret) {
+                printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
+                goto err;
+        }
+
+        ourport->tx_claimed = 1;
+
+        dbg("s3c24xx_serial_startup ok\n");
+
+        /* the port reset code should have done the correct
+         * register setup for the port controls */
+
+        return ret;
+
+ err:
+        s3c24xx_serial_shutdown(port);
+        return ret;
+}
+
+/* power power management control */
+
+static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
+                              unsigned int old)
+{
+        struct s3c24xx_uart_port *ourport = to_ourport(port);
+
+        switch (level) {
+        case 3:
+                if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
+                        clk_disable(ourport->baudclk);
+
+                clk_disable(ourport->clk);
+                break;
+
+        case 0:
+                clk_enable(ourport->clk);
+
+                if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
+                        clk_enable(ourport->baudclk);
+
+                break;
+        default:
+                printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
+        }
+}
+
+/* baud rate calculation
+ *
+ * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
+ * of different sources, including the peripheral clock ("pclk") and an
+ * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
+ * with a programmable extra divisor.
+ *
+ * The following code goes through the clock sources, and calculates the
+ * baud clocks (and the resultant actual baud rates) and then tries to
+ * pick the closest one and select that.
+ *
+*/
+
+
+#define MAX_CLKS (8)
+
+static struct s3c24xx_uart_clksrc tmp_clksrc = {
+        .name           = "pclk",
+        .min_baud       = 0,
+        .max_baud       = 0,
+        .divisor        = 1,
+};
+
+static inline int
+s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
+{
+        struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
+
+        return (info->get_clksrc)(port, c);
+}
+
+static inline int
+s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
+{
+        struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
+
+        return (info->set_clksrc)(port, c);
+}
+
+struct baud_calc {
+        struct s3c24xx_uart_clksrc      *clksrc;
+        unsigned int                     calc;
+        unsigned int                     quot;
+        struct clk                      *src;
+};
+
+static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
+                                   struct uart_port *port,
+                                   struct s3c24xx_uart_clksrc *clksrc,
+                                   unsigned int baud)
+{
+        unsigned long rate;
+
+        calc->src = clk_get(port->dev, clksrc->name);
+        if (calc->src == NULL || IS_ERR(calc->src))
+                return 0;
+
+        rate = clk_get_rate(calc->src);
+        rate /= clksrc->divisor;
+
+        calc->clksrc = clksrc;
+        calc->quot = (rate + (8 * baud)) / (16 * baud);
+        calc->calc = (rate / (calc->quot * 16));
+
+        calc->quot--;
+        return 1;
+}
+
+static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
+                                          struct s3c24xx_uart_clksrc **clksrc,
+                                          struct clk **clk,
+                                          unsigned int baud)
+{
+        struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
+        struct s3c24xx_uart_clksrc *clkp;
+        struct baud_calc res[MAX_CLKS];
+        struct baud_calc *resptr, *best, *sptr;
+        int i;
+
+        clkp = cfg->clocks;
+        best = NULL;
+
+        if (cfg->clocks_size < 2) {
+                if (cfg->clocks_size == 0)
+                        clkp = &tmp_clksrc;
+
+                /* check to see if we're sourcing fclk, and if so we're
+                 * going to have to update the clock source
+                 */
+
+                if (strcmp(clkp->name, "fclk") == 0) {
+                        struct s3c24xx_uart_clksrc src;
+
+                        s3c24xx_serial_getsource(port, &src);
+
+                        /* check that the port already using fclk, and if
+                         * not, then re-select fclk
+                         */
+
+                        if (strcmp(src.name, clkp->name) == 0) {
+                                s3c24xx_serial_setsource(port, clkp);
+                                s3c24xx_serial_getsource(port, &src);
+                        }
+
+                        clkp->divisor = src.divisor;
+                }
+
+                s3c24xx_serial_calcbaud(res, port, clkp, baud);
+                best = res;
+                resptr = best + 1;
+        } else {
+                resptr = res;
+
+                for (i = 0; i < cfg->clocks_size; i++, clkp++) {
+                        if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
+                                resptr++;
+                }
+        }
+
+        /* ok, we now need to select the best clock we found */
+
+        if (!best) {
+                unsigned int deviation = (1<<30)|((1<<30)-1);
+                int calc_deviation;
+
+                for (sptr = res; sptr < resptr; sptr++) {
+                        calc_deviation = baud - sptr->calc;
+                        if (calc_deviation < 0)
+                                calc_deviation = -calc_deviation;
+
+                        if (calc_deviation < deviation) {
+                                best = sptr;
+                                deviation = calc_deviation;
+                        }
+                }
+        }
+
+        /* store results to pass back */
+
+        *clksrc = best->clksrc;
+        *clk    = best->src;
+
+        return best->quot;
+}
+
+static void s3c24xx_serial_set_termios(struct uart_port *port,
+                                       struct ktermios *termios,
+                                       struct ktermios *old)
+{
+        struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
+        struct s3c24xx_uart_port *ourport = to_ourport(port);
+        struct s3c24xx_uart_clksrc *clksrc = NULL;
+        struct clk *clk = NULL;
+        unsigned long flags;
+        unsigned int baud, quot;
+        unsigned int ulcon;
+        unsigned int umcon;
+
+        /*
+         * We don't support modem control lines.
+         */
+        termios->c_cflag &= ~(HUPCL | CMSPAR);
+        termios->c_cflag |= CLOCAL;
+
+        /*
+         * Ask the core to calculate the divisor for us.
+         */
+
+        baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
+
+        if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
+                quot = port->custom_divisor;
+        else
+                quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
+
+        /* check to see if we need  to change clock source */
+
+        if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
+                s3c24xx_serial_setsource(port, clksrc);
+
+                if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
+                        clk_disable(ourport->baudclk);
+                        ourport->baudclk  = NULL;
+                }
+
+                clk_enable(clk);
+
+                ourport->clksrc = clksrc;
+                ourport->baudclk = clk;
+        }
+
+        switch (termios->c_cflag & CSIZE) {
+        case CS5:
+                dbg("config: 5bits/char\n");
+                ulcon = S3C2410_LCON_CS5;
+                break;
+        case CS6:
+                dbg("config: 6bits/char\n");
+                ulcon = S3C2410_LCON_CS6;
+                break;
+        case CS7:
+                dbg("config: 7bits/char\n");
+                ulcon = S3C2410_LCON_CS7;
+                break;
+        case CS8:
+        default:
+                dbg("config: 8bits/char\n");
+                ulcon = S3C2410_LCON_CS8;
+                break;
+        }
+
+        /* preserve original lcon IR settings */
+        ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
+
+        if (termios->c_cflag & CSTOPB)
+                ulcon |= S3C2410_LCON_STOPB;
+
+        umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
+
+        if (termios->c_cflag & PARENB) {
+                if (termios->c_cflag & PARODD)
+                        ulcon |= S3C2410_LCON_PODD;
+                else
+                        ulcon |= S3C2410_LCON_PEVEN;
+        } else {
+                ulcon |= S3C2410_LCON_PNONE;
+        }
+
+        spin_lock_irqsave(&port->lock, flags);
+
+        dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
+
+        wr_regl(port, S3C2410_ULCON, ulcon);
+        wr_regl(port, S3C2410_UBRDIV, quot);
+        wr_regl(port, S3C2410_UMCON, umcon);
+
+        dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
+            rd_regl(port, S3C2410_ULCON),
+            rd_regl(port, S3C2410_UCON),
+            rd_regl(port, S3C2410_UFCON));
+
+        /*
+         * Update the per-port timeout.
+         */
+        uart_update_timeout(port, termios->c_cflag, baud);
+
+        /*
+         * Which character status flags are we interested in?
+         */
+        port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
+        if (termios->c_iflag & INPCK)
+                port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
+
+        /*
+         * Which character status flags should we ignore?
+         */
+        port->ignore_status_mask = 0;
+        if (termios->c_iflag & IGNPAR)
+                port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
+        if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
+                port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
+
+        /*
+         * Ignore all characters if CREAD is not set.
+         */
+        if ((termios->c_cflag & CREAD) == 0)
+                port->ignore_status_mask |= RXSTAT_DUMMY_READ;
+
+        spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *s3c24xx_serial_type(struct uart_port *port)
+{
+        switch (port->type) {
+        case PORT_S3C2410:
+                return "S3C2410";
+        case PORT_S3C2440:
+                return "S3C2440";
+        case PORT_S3C2412:
+                return "S3C2412";
+        default:
+                return NULL;
+        }
+}
+
+#define MAP_SIZE (0x100)
+
+static void s3c24xx_serial_release_port(struct uart_port *port)
+{
+        release_mem_region(port->mapbase, MAP_SIZE);
+}
+
+static int s3c24xx_serial_request_port(struct uart_port *port)
+{
+        const char *name = s3c24xx_serial_portname(port);
+        return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
+}
+
+static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
+{
+        struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
+
+        if (flags & UART_CONFIG_TYPE &&
+            s3c24xx_serial_request_port(port) == 0)
+                port->type = info->type;
+}
+
+/*
+ * verify the new serial_struct (for TIOCSSERIAL).
+ */
+static int
+s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+        struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
+
+        if (ser->type != PORT_UNKNOWN && ser->type != info->type)
+                return -EINVAL;
+
+        return 0;
+}
+
+
+#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
+
+static struct console s3c24xx_serial_console;
+
+#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
+#else
+#define S3C24XX_SERIAL_CONSOLE NULL
+#endif
+
+static struct uart_ops s3c24xx_serial_ops = {
+        .pm             = s3c24xx_serial_pm,
+        .tx_empty       = s3c24xx_serial_tx_empty,
+        .get_mctrl      = s3c24xx_serial_get_mctrl,
+        .set_mctrl      = s3c24xx_serial_set_mctrl,
+        .stop_tx        = s3c24xx_serial_stop_tx,
+        .start_tx       = s3c24xx_serial_start_tx,
+        .stop_rx        = s3c24xx_serial_stop_rx,
+        .enable_ms      = s3c24xx_serial_enable_ms,
+        .break_ctl      = s3c24xx_serial_break_ctl,
+        .startup        = s3c24xx_serial_startup,
+        .shutdown       = s3c24xx_serial_shutdown,
+        .set_termios    = s3c24xx_serial_set_termios,
+        .type           = s3c24xx_serial_type,
+        .release_port   = s3c24xx_serial_release_port,
+        .request_port   = s3c24xx_serial_request_port,
+        .config_port    = s3c24xx_serial_config_port,
+        .verify_port    = s3c24xx_serial_verify_port,
+};
+
+
+static struct uart_driver s3c24xx_uart_drv = {
+        .owner          = THIS_MODULE,
+        .dev_name       = "s3c2410_serial",
+        .nr             = 3,
+        .cons           = S3C24XX_SERIAL_CONSOLE,
+        .driver_name    = S3C24XX_SERIAL_NAME,
+        .major          = S3C24XX_SERIAL_MAJOR,
+        .minor          = S3C24XX_SERIAL_MINOR,
+};
+
+static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
+        [0] = {
+                .port = {
+                        .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
+                        .iotype         = UPIO_MEM,
+                        .irq            = IRQ_S3CUART_RX0,
+                        .uartclk        = 0,
+                        .fifosize       = 16,
+                        .ops            = &s3c24xx_serial_ops,
+                        .flags          = UPF_BOOT_AUTOCONF,
+                        .line           = 0,
+                }
+        },
+        [1] = {
+                .port = {
+                        .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
+                        .iotype         = UPIO_MEM,
+                        .irq            = IRQ_S3CUART_RX1,
+                        .uartclk        = 0,
+                        .fifosize       = 16,
+                        .ops            = &s3c24xx_serial_ops,
+                        .flags          = UPF_BOOT_AUTOCONF,
+                        .line           = 1,
+                }
+        },
+#if NR_PORTS > 2
+
+        [2] = {
+                .port = {
+                        .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
+                        .iotype         = UPIO_MEM,
+                        .irq            = IRQ_S3CUART_RX2,
+                        .uartclk        = 0,
+                        .fifosize       = 16,
+                        .ops            = &s3c24xx_serial_ops,
+                        .flags          = UPF_BOOT_AUTOCONF,
+                        .line           = 2,
+                }
+        }
+#endif
+};
+
+/* s3c24xx_serial_resetport
+ *
+ * wrapper to call the specific reset for this port (reset the fifos
+ * and the settings)
+*/
+
+static inline int s3c24xx_serial_resetport(struct uart_port *port,
+                                           struct s3c2410_uartcfg *cfg)
+{
+        struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
+
+        return (info->reset_port)(port, cfg);
+}
+
+/* s3c24xx_serial_init_port
+ *
+ * initialise a single serial port from the platform device given
+ */
+
+static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
+                                    struct s3c24xx_uart_info *info,
+                                    struct platform_device *platdev)
+{
+        struct uart_port *port = &ourport->port;
+        struct s3c2410_uartcfg *cfg;
+        struct resource *res;
+        int ret;
+
+        dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
+
+        if (platdev == NULL)
+                return -ENODEV;
+
+        cfg = s3c24xx_dev_to_cfg(&platdev->dev);
+
+        if (port->mapbase != 0)
+                return 0;
+
+        if (cfg->hwport > 3)
+                return -EINVAL;
+
+        /* setup info for port */
+        port->dev       = &platdev->dev;
+        ourport->info   = info;
+
+        /* copy the info in from provided structure */
+        ourport->port.fifosize = info->fifosize;
+
+        dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
+
+        port->uartclk = 1;
+
+        if (cfg->uart_flags & UPF_CONS_FLOW) {
+                dbg("s3c24xx_serial_init_port: enabling flow control\n");
+                port->flags |= UPF_CONS_FLOW;
+        }
+
+        /* sort our the physical and virtual addresses for each UART */
+
+        res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
+        if (res == NULL) {
+                printk(KERN_ERR "failed to find memory resource for uart\n");
+                return -EINVAL;
+        }
+
+        dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
+
+        port->mapbase   = res->start;
+        port->membase   = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART);
+        ret = platform_get_irq(platdev, 0);
+        if (ret < 0)
+                port->irq = 0;
+        else
+                port->irq = ret;
+
+        ourport->clk    = clk_get(&platdev->dev, "uart");
+
+        dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
+            port->mapbase, port->membase, port->irq, port->uartclk);
+
+        /* reset the fifos (and setup the uart) */
+        s3c24xx_serial_resetport(port, cfg);
+        return 0;
+}
+
+static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
+                                          struct device_attribute *attr,
+                                          char *buf)
+{
+        struct uart_port *port = s3c24xx_dev_to_port(dev);
+        struct s3c24xx_uart_port *ourport = to_ourport(port);
+
+        return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->clksrc->name);
+}
+
+static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
+
+/* Device driver serial port probe */
+
+static int probe_index;
+
+int s3c24xx_serial_probe(struct platform_device *dev,
+                         struct s3c24xx_uart_info *info)
+{
+        struct s3c24xx_uart_port *ourport;
+        int ret;
+
+        dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index);
+
+        ourport = &s3c24xx_serial_ports[probe_index];
+        probe_index++;
+
+        dbg("%s: initialising port %p...\n", __func__, ourport);
+
+        ret = s3c24xx_serial_init_port(ourport, info, dev);
+        if (ret < 0)
+                goto probe_err;
+
+        dbg("%s: adding port\n", __func__);
+        uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
+        platform_set_drvdata(dev, &ourport->port);
+
+        ret = device_create_file(&dev->dev, &dev_attr_clock_source);
+        if (ret < 0)
+                printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__);
+
+        return 0;
+
+ probe_err:
+        return ret;
+}
+
+EXPORT_SYMBOL_GPL(s3c24xx_serial_probe);
+
+int s3c24xx_serial_remove(struct platform_device *dev)
+{
+        struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
+
+        if (port) {
+                device_remove_file(&dev->dev, &dev_attr_clock_source);
+                uart_remove_one_port(&s3c24xx_uart_drv, port);
+        }
+
+        return 0;
+}
+
+EXPORT_SYMBOL_GPL(s3c24xx_serial_remove);
+
+/* UART power management code */
+
+#ifdef CONFIG_PM
+
+static int s3c24xx_serial_suspend(struct platform_device *dev, pm_message_t state)
+{
+        struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
+
+        if (port)
+                uart_suspend_port(&s3c24xx_uart_drv, port);
+
+        return 0;
+}
+
+static int s3c24xx_serial_resume(struct platform_device *dev)
+{
+        struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
+        struct s3c24xx_uart_port *ourport = to_ourport(port);
+
+        if (port) {
+                clk_enable(ourport->clk);
+                s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
+                clk_disable(ourport->clk);
+
+                uart_resume_port(&s3c24xx_uart_drv, port);
+        }
+
+        return 0;
+}
+#endif
+
+int s3c24xx_serial_init(struct platform_driver *drv,
+                        struct s3c24xx_uart_info *info)
+{
+        dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
+
+#ifdef CONFIG_PM
+        drv->suspend = s3c24xx_serial_suspend;
+        drv->resume = s3c24xx_serial_resume;
+#endif
+
+        return platform_driver_register(drv);
+}
+
+EXPORT_SYMBOL_GPL(s3c24xx_serial_init);
+
+/* module initialisation code */
+
+static int __init s3c24xx_serial_modinit(void)
+{
+        int ret;
+
+        ret = uart_register_driver(&s3c24xx_uart_drv);
+        if (ret < 0) {
+                printk(KERN_ERR "failed to register UART driver\n");
+                return -1;
+        }
+
+        return 0;
+}
+
+static void __exit s3c24xx_serial_modexit(void)
+{
+        uart_unregister_driver(&s3c24xx_uart_drv);
+}
+
+module_init(s3c24xx_serial_modinit);
+module_exit(s3c24xx_serial_modexit);
+
+/* Console code */
+
+#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
+
+static struct uart_port *cons_uart;
+
+static int
+s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
+{
+        struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
+        unsigned long ufstat, utrstat;
+
+        if (ufcon & S3C2410_UFCON_FIFOMODE) {
+                /* fifo mode - check ammount of data in fifo registers... */
+
+                ufstat = rd_regl(port, S3C2410_UFSTAT);
+                return (ufstat & info->tx_fifofull) ? 0 : 1;
+        }
+
+        /* in non-fifo mode, we go and use the tx buffer empty */
+
+        utrstat = rd_regl(port, S3C2410_UTRSTAT);
+        return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
+}
+
+static void
+s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
+{
+        unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
+        while (!s3c24xx_serial_console_txrdy(port, ufcon))
+                barrier();
+        wr_regb(cons_uart, S3C2410_UTXH, ch);
+}
+
+static void
+s3c24xx_serial_console_write(struct console *co, const char *s,
+                             unsigned int count)
+{
+        uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
+}
+
+static void __init
+s3c24xx_serial_get_options(struct uart_port *port, int *baud,
+                           int *parity, int *bits)
+{
+        struct s3c24xx_uart_clksrc clksrc;
+        struct clk *clk;
+        unsigned int ulcon;
+        unsigned int ucon;
+        unsigned int ubrdiv;
+        unsigned long rate;
+
+        ulcon  = rd_regl(port, S3C2410_ULCON);
+        ucon   = rd_regl(port, S3C2410_UCON);
+        ubrdiv = rd_regl(port, S3C2410_UBRDIV);
+
+        dbg("s3c24xx_serial_get_options: port=%p\n"
+            "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
+            port, ulcon, ucon, ubrdiv);
+
+        if ((ucon & 0xf) != 0) {
+                /* consider the serial port configured if the tx/rx mode set */
+
+                switch (ulcon & S3C2410_LCON_CSMASK) {
+                case S3C2410_LCON_CS5:
+                        *bits = 5;
+                        break;
+                case S3C2410_LCON_CS6:
+                        *bits = 6;
+                        break;
+                case S3C2410_LCON_CS7:
+                        *bits = 7;
+                        break;
+                default:
+                case S3C2410_LCON_CS8:
+                        *bits = 8;
+                        break;
+                }
+
+                switch (ulcon & S3C2410_LCON_PMASK) {
+                case S3C2410_LCON_PEVEN:
+                        *parity = 'e';
+                        break;
+
+                case S3C2410_LCON_PODD:
+                        *parity = 'o';
+                        break;
+
+                case S3C2410_LCON_PNONE:
+                default:
+                        *parity = 'n';
+                }
+
+                /* now calculate the baud rate */
+
+                s3c24xx_serial_getsource(port, &clksrc);
+
+                clk = clk_get(port->dev, clksrc.name);
+                if (!IS_ERR(clk) && clk != NULL)
+                        rate = clk_get_rate(clk) / clksrc.divisor;
+                else
+                        rate = 1;
+
+
+                *baud = rate / (16 * (ubrdiv + 1));
+                dbg("calculated baud %d\n", *baud);
+        }
+
+}
+
+/* s3c24xx_serial_init_ports
+ *
+ * initialise the serial ports from the machine provided initialisation
+ * data.
+*/
+
+static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
+{
+        struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
+        struct platform_device **platdev_ptr;
+        int i;
+
+        dbg("s3c24xx_serial_init_ports: initialising ports...\n");
+
+        platdev_ptr = s3c24xx_uart_devs;
+
+        for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
+                s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
+        }
+
+        return 0;
+}
+
+static int __init
+s3c24xx_serial_console_setup(struct console *co, char *options)
+{
+        struct uart_port *port;
+        int baud = 9600;
+        int bits = 8;
+        int parity = 'n';
+        int flow = 'n';
+
+        dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
+            co, co->index, options);
+
+        /* is this a valid port */
+
+        if (co->index == -1 || co->index >= NR_PORTS)
+                co->index = 0;
+
+        port = &s3c24xx_serial_ports[co->index].port;
+
+        /* is the port configured? */
+
+        if (port->mapbase == 0x0) {
+                co->index = 0;
+                port = &s3c24xx_serial_ports[co->index].port;
+        }
+
+        cons_uart = port;
+
+        dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
+
+        /*
+         * Check whether an invalid uart number has been specified, and
+         * if so, search for the first available port that does have
+         * console support.
+         */
+        if (options)
+                uart_parse_options(options, &baud, &parity, &bits, &flow);
+        else
+                s3c24xx_serial_get_options(port, &baud, &parity, &bits);
+
+        dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
+
+        return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+/* s3c24xx_serial_initconsole
+ *
+ * initialise the console from one of the uart drivers
+*/
+
+static struct console s3c24xx_serial_console = {
+        .name           = S3C24XX_SERIAL_NAME,
+        .device         = uart_console_device,
+        .flags          = CON_PRINTBUFFER,
+        .index          = -1,
+        .write          = s3c24xx_serial_console_write,
+        .setup          = s3c24xx_serial_console_setup
+};
+
+int s3c24xx_serial_initconsole(struct platform_driver *drv,
+                               struct s3c24xx_uart_info *info)
+
+{
+        struct platform_device *dev = s3c24xx_uart_devs[0];
+
+        dbg("s3c24xx_serial_initconsole\n");
+
+        /* select driver based on the cpu */
+
+        if (dev == NULL) {
+                printk(KERN_ERR "s3c24xx: no devices for console init\n");
+                return 0;
+        }
+
+        if (strcmp(dev->name, drv->driver.name) != 0)
+                return 0;
+
+        s3c24xx_serial_console.data = &s3c24xx_uart_drv;
+        s3c24xx_serial_init_ports(info);
+
+        register_console(&s3c24xx_serial_console);
+        return 0;
+}
+
+#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
+
+MODULE_DESCRIPTION("Samsung SoC Serial port driver");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/serial/samsung.h b/drivers/serial/samsung.h
new file mode 100644
index 000000000000..5c92ebbe7d9e
--- /dev/null
+++ b/drivers/serial/samsung.h
@@ -0,0 +1,102 @@
+/* linux/drivers/serial/samsung.h
+ *
+ * Driver for Samsung SoC onboard UARTs.
+ *
+ * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct s3c24xx_uart_info {
+        char                    *name;
+        unsigned int            type;
+        unsigned int            fifosize;
+        unsigned long           rx_fifomask;
+        unsigned long           rx_fifoshift;
+        unsigned long           rx_fifofull;
+        unsigned long           tx_fifomask;
+        unsigned long           tx_fifoshift;
+        unsigned long           tx_fifofull;
+
+        /* clock source control */
+
+        int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
+        int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
+
+        /* uart controls */
+        int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
+};
+
+struct s3c24xx_uart_port {
+        unsigned char                   rx_claimed;
+        unsigned char                   tx_claimed;
+
+        struct s3c24xx_uart_info        *info;
+        struct s3c24xx_uart_clksrc      *clksrc;
+        struct clk                      *clk;
+        struct clk                      *baudclk;
+        struct uart_port                port;
+};
+
+/* conversion functions */
+
+#define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
+#define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
+
+/* register access controls */
+
+#define portaddr(port, reg) ((port)->membase + (reg))
+
+#define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
+#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
+
+#define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
+#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
+
+extern int s3c24xx_serial_probe(struct platform_device *dev,
+                                struct s3c24xx_uart_info *uart);
+
+extern int s3c24xx_serial_remove(struct platform_device *dev);
+
+extern int s3c24xx_serial_initconsole(struct platform_driver *drv,
+                                      struct s3c24xx_uart_info *uart);
+
+extern int s3c24xx_serial_init(struct platform_driver *drv,
+                               struct s3c24xx_uart_info *info);
+
+#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
+
+#define s3c24xx_console_init(__drv, __inf)                      \
+static int __init s3c_serial_console_init(void)                 \
+{                                                               \
+        return s3c24xx_serial_initconsole(__drv, __inf);        \
+}                                                               \
+                                                                \
+console_initcall(s3c_serial_console_init)
+
+#else
+#define s3c24xx_console_init(drv, inf) extern void no_console(void)
+#endif
+
+#ifdef CONFIG_SERIAL_SAMSUNG_DEBUG
+
+extern void printascii(const char *);
+
+static void dbg(const char *fmt, ...)
+{
+        va_list va;
+        char buff[256];
+
+        va_start(va, fmt);
+        vsprintf(buff, fmt, va);
+        va_end(va);
+
+        printascii(buff);
+}
+
+#else
+#define dbg(x...) do { } while (0)
+#endif
diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
index c730d05bfeb6..54ac7bea5f8c 100644
--- a/drivers/spi/spi_imx.c
+++ b/drivers/spi/spi_imx.c
@@ -29,6 +29,7 @@
 #include <linux/spi/spi.h>
 #include <linux/workqueue.h>
 #include <linux/delay.h>
+#include <linux/clk.h>
 
 #include <asm/io.h>
 #include <asm/irq.h>
@@ -250,6 +251,8 @@ struct driver_data {
         int tx_dma_needs_unmap;
         size_t tx_map_len;
         u32 dummy_dma_buf ____cacheline_aligned;
+
+        struct clk *clk;
 };
 
 /* Runtime state */
@@ -855,15 +858,15 @@ static irqreturn_t spi_int(int irq, void *dev_id)
         return drv_data->transfer_handler(drv_data);
 }
 
-static inline u32 spi_speed_hz(u32 data_rate)
+static inline u32 spi_speed_hz(struct driver_data *drv_data, u32 data_rate)
 {
-        return imx_get_perclk2() / (4 << ((data_rate) >> 13));
+        return clk_get_rate(drv_data->clk) / (4 << ((data_rate) >> 13));
 }
 
-static u32 spi_data_rate(u32 speed_hz)
+static u32 spi_data_rate(struct driver_data *drv_data, u32 speed_hz)
 {
         u32 div;
-        u32 quantized_hz = imx_get_perclk2() >> 2;
+        u32 quantized_hz = clk_get_rate(drv_data->clk) >> 2;
 
         for (div = SPI_PERCLK2_DIV_MIN;
                 div <= SPI_PERCLK2_DIV_MAX;
@@ -947,7 +950,7 @@ static void pump_transfers(unsigned long data)
         tmp = transfer->speed_hz;
         if (tmp == 0)
                 tmp = chip->max_speed_hz;
-        tmp = spi_data_rate(tmp);
+        tmp = spi_data_rate(drv_data, tmp);
         u32_EDIT(control, SPI_CONTROL_DATARATE, tmp);
 
         writel(control, regs + SPI_CONTROL);
@@ -1109,7 +1112,7 @@ static int transfer(struct spi_device *spi, struct spi_message *msg)
         msg->actual_length = 0;
 
         /* Per transfer setup check */
-        min_speed_hz = spi_speed_hz(SPI_CONTROL_DATARATE_MIN);
+        min_speed_hz = spi_speed_hz(drv_data, SPI_CONTROL_DATARATE_MIN);
         max_speed_hz = spi->max_speed_hz;
         list_for_each_entry(trans, &msg->transfers, transfer_list) {
                 tmp = trans->bits_per_word;
@@ -1176,6 +1179,7 @@ msg_rejected:
    applied and notified to the calling driver. */
 static int setup(struct spi_device *spi)
 {
+        struct driver_data *drv_data = spi_master_get_devdata(spi->master);
         struct spi_imx_chip *chip_info;
         struct chip_data *chip;
         int first_setup = 0;
@@ -1304,14 +1308,14 @@ static int setup(struct spi_device *spi)
         chip->n_bytes = (tmp <= 8) ? 1 : 2;
 
         /* SPI datarate */
-        tmp = spi_data_rate(spi->max_speed_hz);
+        tmp = spi_data_rate(drv_data, spi->max_speed_hz);
         if (tmp == SPI_CONTROL_DATARATE_BAD) {
                 status = -EINVAL;
                 dev_err(&spi->dev,
                         "setup - "
                         "HW min speed (%d Hz) exceeds required "
                         "max speed (%d Hz)\n",
-                        spi_speed_hz(SPI_CONTROL_DATARATE_MIN),
+                        spi_speed_hz(drv_data, SPI_CONTROL_DATARATE_MIN),
                         spi->max_speed_hz);
                 if (first_setup)
                         goto err_first_setup;
@@ -1321,7 +1325,7 @@ static int setup(struct spi_device *spi)
         } else {
                 u32_EDIT(chip->control, SPI_CONTROL_DATARATE, tmp);
                 /* Actual rounded max_speed_hz */
-                tmp = spi_speed_hz(tmp);
+                tmp = spi_speed_hz(drv_data, tmp);
                 spi->max_speed_hz = tmp;
                 chip->max_speed_hz = tmp;
         }
@@ -1352,7 +1356,7 @@ static int setup(struct spi_device *spi)
                 chip->period & SPI_PERIOD_WAIT,
                 spi->mode,
                 spi->bits_per_word,
-                spi_speed_hz(SPI_CONTROL_DATARATE_MIN),
+                spi_speed_hz(drv_data, SPI_CONTROL_DATARATE_MIN),
                 spi->max_speed_hz);
         return status;
 
@@ -1465,6 +1469,14 @@ static int __init spi_imx_probe(struct platform_device *pdev)
                 goto err_no_pdata;
         }
 
+        drv_data->clk = clk_get(&pdev->dev, "perclk2");
+        if (IS_ERR(drv_data->clk)) {
+                dev_err(&pdev->dev, "probe - cannot get get\n");
+                status = PTR_ERR(drv_data->clk);
+                goto err_no_clk;
+        }
+        clk_enable(drv_data->clk);
+
         /* Allocate master with space for drv_data */
         master = spi_alloc_master(dev, sizeof(struct driver_data));
         if (!master) {
@@ -1526,24 +1538,24 @@ static int __init spi_imx_probe(struct platform_device *pdev)
         drv_data->rx_channel = -1;
         if (platform_info->enable_dma) {
                 /* Get rx DMA channel */
-                status = imx_dma_request_by_prio(&drv_data->rx_channel,
-                        "spi_imx_rx", DMA_PRIO_HIGH);
-                if (status < 0) {
+                drv_data->rx_channel = imx_dma_request_by_prio("spi_imx_rx",
+                                                               DMA_PRIO_HIGH);
+                if (drv_data->rx_channel < 0) {
                         dev_err(dev,
                                 "probe - problem (%d) requesting rx channel\n",
-                                status);
+                                drv_data->rx_channel);
                         goto err_no_rxdma;
                 } else
                         imx_dma_setup_handlers(drv_data->rx_channel, NULL,
                                                 dma_err_handler, drv_data);
 
                 /* Get tx DMA channel */
-                status = imx_dma_request_by_prio(&drv_data->tx_channel,
-                                                "spi_imx_tx", DMA_PRIO_MEDIUM);
-                if (status < 0) {
+                drv_data->tx_channel = imx_dma_request_by_prio("spi_imx_tx",
+                                                               DMA_PRIO_MEDIUM);
+                if (drv_data->tx_channel < 0) {
                         dev_err(dev,
                                 "probe - problem (%d) requesting tx channel\n",
-                                status);
+                                drv_data->tx_channel);
                         imx_dma_free(drv_data->rx_channel);
                         goto err_no_txdma;
                 } else
@@ -1623,6 +1635,9 @@ err_no_iores:
         spi_master_put(master);
 
 err_no_pdata:
+        clk_disable(drv_data->clk);
+        clk_put(drv_data->clk);
+err_no_clk:
 err_no_mem:
         return status;
 }
@@ -1662,6 +1677,9 @@ static int __exit spi_imx_remove(struct platform_device *pdev)
         if (irq >= 0)
                 free_irq(irq, drv_data);
 
+        clk_disable(drv_data->clk);
+        clk_put(drv_data->clk);
+
         /* Release map resources */
         iounmap(drv_data->regs);
         release_resource(drv_data->ioarea);
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 6e784d2db423..d6bab0d5f453 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -118,10 +118,10 @@ config USB_AMD5536UDC
 config USB_GADGET_ATMEL_USBA
         boolean "Atmel USBA"
         select USB_GADGET_DUALSPEED
-        depends on AVR32 || ARCH_AT91CAP9
+        depends on AVR32 || ARCH_AT91CAP9 || ARCH_AT91SAM9RL
         help
           USBA is the integrated high-speed USB Device controller on
-          the AT32AP700x and AT91CAP9 processors from Atmel.
+          the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel.
 
 config USB_ATMEL_USBA
         tristate
@@ -172,7 +172,7 @@ config USB_NET2280
         default USB_GADGET
         select USB_GADGET_SELECTED
 
-config USB_GADGET_PXA2XX
+config USB_GADGET_PXA25X
         boolean "PXA 25x or IXP 4xx"
         depends on (ARCH_PXA && PXA25x) || ARCH_IXP4XX
         help
@@ -184,19 +184,19 @@ config USB_GADGET_PXA2XX
            zero (for control transfers).
 
            Say "y" to link the driver statically, or "m" to build a
-           dynamically linked module called "pxa2xx_udc" and force all
+           dynamically linked module called "pxa25x_udc" and force all
            gadget drivers to also be dynamically linked.
 
-config USB_PXA2XX
+config USB_PXA25X
         tristate
-        depends on USB_GADGET_PXA2XX
+        depends on USB_GADGET_PXA25X
         default USB_GADGET
         select USB_GADGET_SELECTED
 
 # if there's only one gadget driver, using only two bulk endpoints,
 # don't waste memory for the other endpoints
-config USB_PXA2XX_SMALL
-        depends on USB_GADGET_PXA2XX
+config USB_PXA25X_SMALL
+        depends on USB_GADGET_PXA25X
         bool
         default n if USB_ETH_RNDIS
         default y if USB_ZERO
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 12357255d740..e258afd25faf 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -8,7 +8,7 @@ endif
 obj-$(CONFIG_USB_DUMMY_HCD)     += dummy_hcd.o
 obj-$(CONFIG_USB_NET2280)       += net2280.o
 obj-$(CONFIG_USB_AMD5536UDC)    += amd5536udc.o
-obj-$(CONFIG_USB_PXA2XX)        += pxa2xx_udc.o
+obj-$(CONFIG_USB_PXA25X)        += pxa25x_udc.o
 obj-$(CONFIG_USB_PXA27X)        += pxa27x_udc.o
 obj-$(CONFIG_USB_GOKU)          += goku_udc.o
 obj-$(CONFIG_USB_OMAP)          += omap_udc.o
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index 274c60a970cd..b6b2a0a5ba37 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -888,7 +888,7 @@ static void pullup(struct at91_udc *udc, int is_on)
                 at91_udp_write(udc, AT91_UDP_TXVC, 0);
                 if (cpu_is_at91rm9200())
                         gpio_set_value(udc->board.pullup_pin, active);
-                else if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) {
+                else if (cpu_is_at91sam9260() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
                         u32     txvc = at91_udp_read(udc, AT91_UDP_TXVC);
 
                         txvc |= AT91_UDP_TXVC_PUON;
@@ -906,7 +906,7 @@ static void pullup(struct at91_udc *udc, int is_on)
                 at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
                 if (cpu_is_at91rm9200())
                         gpio_set_value(udc->board.pullup_pin, !active);
-                else if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) {
+                else if (cpu_is_at91sam9260() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
                         u32     txvc = at91_udp_read(udc, AT91_UDP_TXVC);
 
                         txvc &= ~AT91_UDP_TXVC_PUON;
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index 8d61ea67a817..4ce3950b997f 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -262,7 +262,7 @@ MODULE_PARM_DESC(host_addr, "Host Ethernet Address");
 /* For CDC-incapable hardware, choose the simple cdc subset.
  * Anything that talks bulk (without notable bugs) can do this.
  */
-#ifdef CONFIG_USB_GADGET_PXA2XX
+#ifdef CONFIG_USB_GADGET_PXA25X
 #define DEV_CONFIG_SUBSET
 #endif
 
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index f7f159c1002b..ca5149ea7312 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -29,8 +29,8 @@
 #define gadget_is_dummy(g)      0
 #endif
 
-#ifdef CONFIG_USB_GADGET_PXA2XX
-#define gadget_is_pxa(g)        !strcmp("pxa2xx_udc", (g)->name)
+#ifdef CONFIG_USB_GADGET_PXA25X
+#define gadget_is_pxa(g)        !strcmp("pxa25x_udc", (g)->name)
 #else
 #define gadget_is_pxa(g)        0
 #endif
diff --git a/drivers/usb/gadget/inode.c b/drivers/usb/gadget/inode.c
index 69b0a2754f2a..f132a9219e11 100644
--- a/drivers/usb/gadget/inode.c
+++ b/drivers/usb/gadget/inode.c
@@ -1501,7 +1501,7 @@ gadgetfs_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
                 }
                 break;
 
-#ifndef CONFIG_USB_GADGET_PXA2XX
+#ifndef CONFIG_USB_GADGET_PXA25X
         /* PXA automagically handles this request too */
         case USB_REQ_GET_CONFIGURATION:
                 if (ctrl->bRequestType != 0x80)
diff --git a/drivers/usb/gadget/omap_udc.c b/drivers/usb/gadget/omap_udc.c
index 881d74c3d964..03a7f49d207d 100644
--- a/drivers/usb/gadget/omap_udc.c
+++ b/drivers/usb/gadget/omap_udc.c
@@ -135,13 +135,17 @@ static void use_ep(struct omap_ep *ep, u16 select)
 
         if (ep->bEndpointAddress & USB_DIR_IN)
                 num |= UDC_EP_DIR;
-        UDC_EP_NUM_REG = num | select;
+        omap_writew(num | select, UDC_EP_NUM);
         /* when select, MUST deselect later !! */
 }
 
 static inline void deselect_ep(void)
 {
-        UDC_EP_NUM_REG &= ~UDC_EP_SEL;
+        u16 w;
+
+        w = omap_readw(UDC_EP_NUM);
+        w &= ~UDC_EP_SEL;
+        omap_writew(w, UDC_EP_NUM);
         /* 6 wait states before TX will happen */
 }
 
@@ -216,7 +220,7 @@ static int omap_ep_enable(struct usb_ep *_ep,
         ep->has_dma = 0;
         ep->lch = -1;
         use_ep(ep, UDC_EP_SEL);
-        UDC_CTRL_REG = udc->clr_halt;
+        omap_writew(udc->clr_halt, UDC_CTRL);
         ep->ackwait = 0;
         deselect_ep();
 
@@ -232,7 +236,7 @@ static int omap_ep_enable(struct usb_ep *_ep,
         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
                         && !ep->has_dma
                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
-                UDC_CTRL_REG = UDC_SET_FIFO_EN;
+                omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
                 ep->ackwait = 1 + ep->double_buf;
         }
 
@@ -259,7 +263,7 @@ static int omap_ep_disable(struct usb_ep *_ep)
         nuke (ep, -ESHUTDOWN);
         ep->ep.maxpacket = ep->maxpacket;
         ep->has_dma = 0;
-        UDC_CTRL_REG = UDC_SET_HALT;
+        omap_writew(UDC_SET_HALT, UDC_CTRL);
         list_del_init(&ep->iso);
         del_timer(&ep->timer);
 
@@ -360,13 +364,13 @@ write_packet(u8 *buf, struct omap_req *req, unsigned max)
         if (likely((((int)buf) & 1) == 0)) {
                 wp = (u16 *)buf;
                 while (max >= 2) {
-                        UDC_DATA_REG = *wp++;
+                        omap_writew(*wp++, UDC_DATA);
                         max -= 2;
                 }
                 buf = (u8 *)wp;
         }
         while (max--)
-                *(volatile u8 *)&UDC_DATA_REG = *buf++;
+                omap_writeb(*buf++, UDC_DATA);
         return len;
 }
 
@@ -385,13 +389,13 @@ static int write_fifo(struct omap_ep *ep, struct omap_req *req)
         prefetch(buf);
 
         /* PIO-IN isn't double buffered except for iso */
-        ep_stat = UDC_STAT_FLG_REG;
+        ep_stat = omap_readw(UDC_STAT_FLG);
         if (ep_stat & UDC_FIFO_UNWRITABLE)
                 return 0;
 
         count = ep->ep.maxpacket;
         count = write_packet(buf, req, count);
-        UDC_CTRL_REG = UDC_SET_FIFO_EN;
+        omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
         ep->ackwait = 1;
 
         /* last packet is often short (sometimes a zlp) */
@@ -425,13 +429,13 @@ read_packet(u8 *buf, struct omap_req *req, unsigned avail)
         if (likely((((int)buf) & 1) == 0)) {
                 wp = (u16 *)buf;
                 while (avail >= 2) {
-                        *wp++ = UDC_DATA_REG;
+                        *wp++ = omap_readw(UDC_DATA);
                         avail -= 2;
                 }
                 buf = (u8 *)wp;
         }
         while (avail--)
-                *buf++ = *(volatile u8 *)&UDC_DATA_REG;
+                *buf++ = omap_readb(UDC_DATA);
         return len;
 }
 
@@ -446,7 +450,7 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req)
         prefetchw(buf);
 
         for (;;) {
-                u16     ep_stat = UDC_STAT_FLG_REG;
+                u16     ep_stat = omap_readw(UDC_STAT_FLG);
 
                 is_last = 0;
                 if (ep_stat & FIFO_EMPTY) {
@@ -460,7 +464,7 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req)
                 if (ep_stat & UDC_FIFO_FULL)
                         avail = ep->ep.maxpacket;
                 else  {
-                        avail = UDC_RXFSTAT_REG;
+                        avail = omap_readw(UDC_RXFSTAT);
                         ep->fnf = ep->double_buf;
                 }
                 count = read_packet(buf, req, avail);
@@ -473,7 +477,7 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req)
                                 req->req.status = -EOVERFLOW;
                                 avail -= count;
                                 while (avail--)
-                                        (void) *(volatile u8 *)&UDC_DATA_REG;
+                                        omap_readw(UDC_DATA);
                         }
                 } else if (req->req.length == req->req.actual)
                         is_last = 1;
@@ -491,32 +495,6 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 
 /*-------------------------------------------------------------------------*/
 
-static inline dma_addr_t dma_csac(unsigned lch)
-{
-        dma_addr_t      csac;
-
-        /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
-         * read before the DMA controller finished disabling the channel.
-         */
-        csac = OMAP_DMA_CSAC_REG(lch);
-        if (csac == 0)
-                csac = OMAP_DMA_CSAC_REG(lch);
-        return csac;
-}
-
-static inline dma_addr_t dma_cdac(unsigned lch)
-{
-        dma_addr_t      cdac;
-
-        /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
-         * read before the DMA controller finished disabling the channel.
-         */
-        cdac = OMAP_DMA_CDAC_REG(lch);
-        if (cdac == 0)
-                cdac = OMAP_DMA_CDAC_REG(lch);
-        return cdac;
-}
-
 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 {
         dma_addr_t      end;
@@ -527,7 +505,7 @@ static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
         if (cpu_is_omap15xx())
                 return 0;
 
-        end = dma_csac(ep->lch);
+        end = omap_get_dma_src_pos(ep->lch);
         if (end == ep->dma_counter)
                 return 0;
 
@@ -537,15 +515,11 @@ static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
         return end - start;
 }
 
-#define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
-                ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
-                : dma_cdac(x))
-
 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 {
         dma_addr_t      end;
 
-        end = DMA_DEST_LAST(ep->lch);
+        end = omap_get_dma_dst_pos(ep->lch);
         if (end == ep->dma_counter)
                 return 0;
 
@@ -565,7 +539,7 @@ static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 
 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 {
-        u16             txdma_ctrl;
+        u16             txdma_ctrl, w;
         unsigned        length = req->req.length - req->req.actual;
         const int       sync_mode = cpu_is_omap15xx()
                                 ? OMAP_DMA_SYNC_FRAME
@@ -596,14 +570,18 @@ static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
                 0, 0);
 
         omap_start_dma(ep->lch);
-        ep->dma_counter = dma_csac(ep->lch);
-        UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
-        UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
+        ep->dma_counter = omap_get_dma_src_pos(ep->lch);
+        w = omap_readw(UDC_DMA_IRQ_EN);
+        w |= UDC_TX_DONE_IE(ep->dma_channel);
+        omap_writew(w, UDC_DMA_IRQ_EN);
+        omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
         req->dma_bytes = length;
 }
 
 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 {
+        u16 w;
+
         if (status == 0) {
                 req->req.actual += req->dma_bytes;
 
@@ -620,7 +598,9 @@ static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 
         /* tx completion */
         omap_stop_dma(ep->lch);
-        UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
+        w = omap_readw(UDC_DMA_IRQ_EN);
+        w &= ~UDC_TX_DONE_IE(ep->dma_channel);
+        omap_writew(w, UDC_DMA_IRQ_EN);
         done(ep, req, status);
 }
 
@@ -628,6 +608,7 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 {
         unsigned packets = req->req.length - req->req.actual;
         int dma_trigger = 0;
+        u16 w;
 
         if (cpu_is_omap24xx())
                 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
@@ -654,12 +635,14 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
                 0, 0);
-        ep->dma_counter = DMA_DEST_LAST(ep->lch);
+        ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
 
-        UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
-        UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
-        UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
-        UDC_CTRL_REG = UDC_SET_FIFO_EN;
+        omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
+        w = omap_readw(UDC_DMA_IRQ_EN);
+        w |= UDC_RX_EOT_IE(ep->dma_channel);
+        omap_writew(w, UDC_DMA_IRQ_EN);
+        omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
+        omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 
         omap_start_dma(ep->lch);
 }
@@ -667,7 +650,7 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 static void
 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 {
-        u16     count;
+        u16     count, w;
 
         if (status == 0)
                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
@@ -686,13 +669,15 @@ finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
                 return;
 
         /* rx completion */
-        UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
+        w = omap_readw(UDC_DMA_IRQ_EN);
+        w &= ~UDC_RX_EOT_IE(ep->dma_channel);
+        omap_writew(w, UDC_DMA_IRQ_EN);
         done(ep, req, status);
 }
 
 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 {
-        u16             dman_stat = UDC_DMAN_STAT_REG;
+        u16             dman_stat = omap_readw(UDC_DMAN_STAT);
         struct omap_ep  *ep;
         struct omap_req *req;
 
@@ -706,7 +691,7 @@ static void dma_irq(struct omap_udc *udc, u16 irq_src)
                                                 struct omap_req, queue);
                         finish_in_dma(ep, req, 0);
                 }
-                UDC_IRQ_SRC_REG = UDC_TXN_DONE;
+                omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
 
                 if (!list_empty (&ep->queue)) {
                         req = container_of(ep->queue.next,
@@ -725,7 +710,7 @@ static void dma_irq(struct omap_udc *udc, u16 irq_src)
                                         struct omap_req, queue);
                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
                 }
-                UDC_IRQ_SRC_REG = UDC_RXN_EOT;
+                omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
 
                 if (!list_empty (&ep->queue)) {
                         req = container_of(ep->queue.next,
@@ -739,7 +724,7 @@ static void dma_irq(struct omap_udc *udc, u16 irq_src)
                 ep->irqs++;
                 /* omap15xx does this unasked... */
                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
-                UDC_IRQ_SRC_REG = UDC_RXN_CNT;
+                omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
         }
 }
 
@@ -762,9 +747,9 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 
         is_in = ep->bEndpointAddress & USB_DIR_IN;
         if (is_in)
-                reg = UDC_TXDMA_CFG_REG;
+                reg = omap_readw(UDC_TXDMA_CFG);
         else
-                reg = UDC_RXDMA_CFG_REG;
+                reg = omap_readw(UDC_RXDMA_CFG);
         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 
         ep->dma_channel = 0;
@@ -792,7 +777,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
                 status = omap_request_dma(dma_channel,
                         ep->ep.name, dma_error, ep, &ep->lch);
                 if (status == 0) {
-                        UDC_TXDMA_CFG_REG = reg;
+                        omap_writew(reg, UDC_TXDMA_CFG);
                         /* EMIFF or SDRC */
                         omap_set_dma_src_burst_mode(ep->lch,
                                                 OMAP_DMA_DATA_BURST_4);
@@ -801,7 +786,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
                         omap_set_dma_dest_params(ep->lch,
                                 OMAP_DMA_PORT_TIPB,
                                 OMAP_DMA_AMODE_CONSTANT,
-                                (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
+                                (unsigned long) io_v2p(UDC_DATA_DMA),
                                 0, 0);
                 }
         } else {
@@ -813,12 +798,12 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
                 status = omap_request_dma(dma_channel,
                         ep->ep.name, dma_error, ep, &ep->lch);
                 if (status == 0) {
-                        UDC_RXDMA_CFG_REG = reg;
+                        omap_writew(reg, UDC_RXDMA_CFG);
                         /* TIPB */
                         omap_set_dma_src_params(ep->lch,
                                 OMAP_DMA_PORT_TIPB,
                                 OMAP_DMA_AMODE_CONSTANT,
-                                (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
+                                (unsigned long) io_v2p(UDC_DATA_DMA),
                                 0, 0);
                         /* EMIFF or SDRC */
                         omap_set_dma_dest_burst_mode(ep->lch,
@@ -834,7 +819,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 
                 /* channel type P: hw synch (fifo) */
                 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
-                        OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
+                        omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
         }
 
 just_restart:
@@ -860,7 +845,7 @@ just_restart:
                         (is_in ? write_fifo : read_fifo)(ep, req);
                         deselect_ep();
                         if (!is_in) {
-                                UDC_CTRL_REG = UDC_SET_FIFO_EN;
+                                omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
                                 ep->ackwait = 1 + ep->double_buf;
                         }
                         /* IN: 6 wait states before it'll tx */
@@ -881,7 +866,7 @@ static void dma_channel_release(struct omap_ep *ep)
         else
                 req = NULL;
 
-        active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
+        active = omap_get_dma_active_status(ep->lch);
 
         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
                         active ? "active" : "idle",
@@ -894,23 +879,25 @@ static void dma_channel_release(struct omap_ep *ep)
 
         /* wait till current packet DMA finishes, and fifo empties */
         if (ep->bEndpointAddress & USB_DIR_IN) {
-                UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
+                omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
+                                        UDC_TXDMA_CFG);
 
                 if (req) {
                         finish_in_dma(ep, req, -ECONNRESET);
 
                         /* clear FIFO; hosts probably won't empty it */
                         use_ep(ep, UDC_EP_SEL);
-                        UDC_CTRL_REG = UDC_CLR_EP;
+                        omap_writew(UDC_CLR_EP, UDC_CTRL);
                         deselect_ep();
                 }
-                while (UDC_TXDMA_CFG_REG & mask)
+                while (omap_readw(UDC_TXDMA_CFG) & mask)
                         udelay(10);
         } else {
-                UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
+                omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
+                                        UDC_RXDMA_CFG);
 
                 /* dma empties the fifo */
-                while (UDC_RXDMA_CFG_REG & mask)
+                while (omap_readw(UDC_RXDMA_CFG) & mask)
                         udelay(10);
                 if (req)
                         finish_out_dma(ep, req, -ECONNRESET, 0);
@@ -997,9 +984,13 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
         req->req.actual = 0;
 
         /* maybe kickstart non-iso i/o queues */
-        if (is_iso)
-                UDC_IRQ_EN_REG |= UDC_SOF_IE;
-        else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
+        if (is_iso) {
+                u16 w;
+
+                w = omap_readw(UDC_IRQ_EN);
+                w |= UDC_SOF_IE;
+                omap_writew(w, UDC_IRQ_EN);
+        } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
                 int     is_in;
 
                 if (ep->bEndpointAddress == 0) {
@@ -1017,23 +1008,23 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
                                  * requests to non-control endpoints
                                  */
                                 if (udc->ep0_set_config) {
-                                        u16     irq_en = UDC_IRQ_EN_REG;
+                                        u16     irq_en = omap_readw(UDC_IRQ_EN);
 
                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
                                         if (!udc->ep0_reset_config)
                                                 irq_en |= UDC_EPN_RX_IE
                                                         | UDC_EPN_TX_IE;
-                                        UDC_IRQ_EN_REG = irq_en;
+                                        omap_writew(irq_en, UDC_IRQ_EN);
                                 }
 
                                 /* STATUS for zero length DATA stages is
                                  * always an IN ... even for IN transfers,
                                  * a weird case which seem to stall OMAP.
                                  */
-                                UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
-                                UDC_CTRL_REG = UDC_CLR_EP;
-                                UDC_CTRL_REG = UDC_SET_FIFO_EN;
-                                UDC_EP_NUM_REG = UDC_EP_DIR;
+                                omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
+                                omap_writew(UDC_CLR_EP, UDC_CTRL);
+                                omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
+                                omap_writew(UDC_EP_DIR, UDC_EP_NUM);
 
                                 /* cleanup */
                                 udc->ep0_pending = 0;
@@ -1042,11 +1033,11 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 
                         /* non-empty DATA stage */
                         } else if (is_in) {
-                                UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
+                                omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
                         } else {
                                 if (udc->ep0_setup)
                                         goto irq_wait;
-                                UDC_EP_NUM_REG = UDC_EP_SEL;
+                                omap_writew(UDC_EP_SEL, UDC_EP_NUM);
                         }
                 } else {
                         is_in = ep->bEndpointAddress & USB_DIR_IN;
@@ -1062,7 +1053,7 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
                                 req = NULL;
                         deselect_ep();
                         if (!is_in) {
-                                UDC_CTRL_REG = UDC_SET_FIFO_EN;
+                                omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
                                 ep->ackwait = 1 + ep->double_buf;
                         }
                         /* IN: 6 wait states before it'll tx */
@@ -1130,9 +1121,9 @@ static int omap_ep_set_halt(struct usb_ep *_ep, int value)
                 else if (value) {
                         if (ep->udc->ep0_set_config) {
                                 WARN("error changing config?\n");
-                                UDC_SYSCON2_REG = UDC_CLR_CFG;
+                                omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
                         }
-                        UDC_SYSCON2_REG = UDC_STALL_CMD;
+                        omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
                         ep->udc->ep0_pending = 0;
                         status = 0;
                 } else /* NOP */
@@ -1159,8 +1150,8 @@ static int omap_ep_set_halt(struct usb_ep *_ep, int value)
                                 channel = 0;
 
                         use_ep(ep, UDC_EP_SEL);
-                        if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
-                                UDC_CTRL_REG = UDC_SET_HALT;
+                        if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
+                                omap_writew(UDC_SET_HALT, UDC_CTRL);
                                 status = 0;
                         } else
                                 status = -EAGAIN;
@@ -1170,10 +1161,10 @@ static int omap_ep_set_halt(struct usb_ep *_ep, int value)
                                 dma_channel_claim(ep, channel);
                 } else {
                         use_ep(ep, 0);
-                        UDC_CTRL_REG = ep->udc->clr_halt;
+                        omap_writew(ep->udc->clr_halt, UDC_CTRL);
                         ep->ackwait = 0;
                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
-                                UDC_CTRL_REG = UDC_SET_FIFO_EN;
+                                omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
                                 ep->ackwait = 1 + ep->double_buf;
                         }
                 }
@@ -1205,7 +1196,7 @@ static struct usb_ep_ops omap_ep_ops = {
 
 static int omap_get_frame(struct usb_gadget *gadget)
 {
-        u16     sof = UDC_SOF_REG;
+        u16     sof = omap_readw(UDC_SOF);
         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
 }
 
@@ -1224,7 +1215,7 @@ static int omap_wakeup(struct usb_gadget *gadget)
                  */
                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
                         DBG("remote wakeup...\n");
-                        UDC_SYSCON2_REG = UDC_RMT_WKP;
+                        omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
                         retval = 0;
                 }
 
@@ -1247,12 +1238,12 @@ omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
 
         udc = container_of(gadget, struct omap_udc, gadget);
         spin_lock_irqsave(&udc->lock, flags);
-        syscon1 = UDC_SYSCON1_REG;
+        syscon1 = omap_readw(UDC_SYSCON1);
         if (is_selfpowered)
                 syscon1 |= UDC_SELF_PWR;
         else
                 syscon1 &= ~UDC_SELF_PWR;
-        UDC_SYSCON1_REG = syscon1;
+        omap_writew(syscon1, UDC_SYSCON1);
         spin_unlock_irqrestore(&udc->lock, flags);
 
         return 0;
@@ -1265,18 +1256,36 @@ static int can_pullup(struct omap_udc *udc)
 
 static void pullup_enable(struct omap_udc *udc)
 {
-        UDC_SYSCON1_REG |= UDC_PULLUP_EN;
-        if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
-                OTG_CTRL_REG |= OTG_BSESSVLD;
-        UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
+        u16 w;
+
+        w = omap_readw(UDC_SYSCON1);
+        w |= UDC_PULLUP_EN;
+        omap_writew(w, UDC_SYSCON1);
+        if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
+                u32 l;
+
+                l = omap_readl(OTG_CTRL);
+                l |= OTG_BSESSVLD;
+                omap_writel(l, OTG_CTRL);
+        }
+        omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
 }
 
 static void pullup_disable(struct omap_udc *udc)
 {
-        if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
-                OTG_CTRL_REG &= ~OTG_BSESSVLD;
-        UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
-        UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
+        u16 w;
+
+        if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
+                u32 l;
+
+                l = omap_readl(OTG_CTRL);
+                l &= ~OTG_BSESSVLD;
+                omap_writel(l, OTG_CTRL);
+        }
+        omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
+        w = omap_readw(UDC_SYSCON1);
+        w &= ~UDC_PULLUP_EN;
+        omap_writew(w, UDC_SYSCON1);
 }
 
 static struct omap_udc *udc;
@@ -1304,6 +1313,7 @@ static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
 {
         struct omap_udc *udc;
         unsigned long   flags;
+        u32 l;
 
         udc = container_of(gadget, struct omap_udc, gadget);
         spin_lock_irqsave(&udc->lock, flags);
@@ -1311,10 +1321,12 @@ static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
         udc->vbus_active = (is_active != 0);
         if (cpu_is_omap15xx()) {
                 /* "software" detect, ignored if !VBUS_MODE_1510 */
+                l = omap_readl(FUNC_MUX_CTRL_0);
                 if (is_active)
-                        FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
+                        l |= VBUS_CTRL_1510;
                 else
-                        FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
+                        l &= ~VBUS_CTRL_1510;
+                omap_writel(l, FUNC_MUX_CTRL_0);
         }
         if (udc->dc_clk != NULL && is_active) {
                 if (!udc->clk_requested) {
@@ -1384,9 +1396,9 @@ static void nuke(struct omap_ep *ep, int status)
                 dma_channel_release(ep);
 
         use_ep(ep, 0);
-        UDC_CTRL_REG = UDC_CLR_EP;
+        omap_writew(UDC_CLR_EP, UDC_CTRL);
         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
-                UDC_CTRL_REG = UDC_SET_HALT;
+                omap_writew(UDC_SET_HALT, UDC_CTRL);
 
         while (!list_empty(&ep->queue)) {
                 req = list_entry(ep->queue.next, struct omap_req, queue);
@@ -1414,8 +1426,8 @@ static void update_otg(struct omap_udc *udc)
         if (!gadget_is_otg(&udc->gadget))
                 return;
 
-        if (OTG_CTRL_REG & OTG_ID)
-                devstat = UDC_DEVSTAT_REG;
+        if (omap_readl(OTG_CTRL) & OTG_ID)
+                devstat = omap_readw(UDC_DEVSTAT);
         else
                 devstat = 0;
 
@@ -1426,9 +1438,14 @@ static void update_otg(struct omap_udc *udc)
         /* Enable HNP early, avoiding races on suspend irq path.
          * ASSUMES OTG state machine B_BUS_REQ input is true.
          */
-        if (udc->gadget.b_hnp_enable)
-                OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
-                                & ~OTG_PULLUP;
+        if (udc->gadget.b_hnp_enable) {
+                u32 l;
+
+                l = omap_readl(OTG_CTRL);
+                l |= OTG_B_HNPEN | OTG_B_BUSREQ;
+                l &= ~OTG_PULLUP;
+                omap_writel(l, OTG_CTRL);
+        }
 }
 
 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
@@ -1446,7 +1463,7 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
 
                 nuke(ep0, 0);
                 if (ack) {
-                        UDC_IRQ_SRC_REG = ack;
+                        omap_writew(ack, UDC_IRQ_SRC);
                         irq_src = UDC_SETUP;
                 }
         }
@@ -1466,9 +1483,9 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
         if (irq_src & UDC_EP0_TX) {
                 int     stat;
 
-                UDC_IRQ_SRC_REG = UDC_EP0_TX;
-                UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
-                stat = UDC_STAT_FLG_REG;
+                omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
+                omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
+                stat = omap_readw(UDC_STAT_FLG);
                 if (stat & UDC_ACK) {
                         if (udc->ep0_in) {
                                 /* write next IN packet from response,
@@ -1476,26 +1493,26 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
                                  */
                                 if (req)
                                         stat = write_fifo(ep0, req);
-                                UDC_EP_NUM_REG = UDC_EP_DIR;
+                                omap_writew(UDC_EP_DIR, UDC_EP_NUM);
                                 if (!req && udc->ep0_pending) {
-                                        UDC_EP_NUM_REG = UDC_EP_SEL;
-                                        UDC_CTRL_REG = UDC_CLR_EP;
-                                        UDC_CTRL_REG = UDC_SET_FIFO_EN;
-                                        UDC_EP_NUM_REG = 0;
+                                        omap_writew(UDC_EP_SEL, UDC_EP_NUM);
+                                        omap_writew(UDC_CLR_EP, UDC_CTRL);
+                                        omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
+                                        omap_writew(0, UDC_EP_NUM);
                                         udc->ep0_pending = 0;
                                 } /* else:  6 wait states before it'll tx */
                         } else {
                                 /* ack status stage of OUT transfer */
-                                UDC_EP_NUM_REG = UDC_EP_DIR;
+                                omap_writew(UDC_EP_DIR, UDC_EP_NUM);
                                 if (req)
                                         done(ep0, req, 0);
                         }
                         req = NULL;
                 } else if (stat & UDC_STALL) {
-                        UDC_CTRL_REG = UDC_CLR_HALT;
-                        UDC_EP_NUM_REG = UDC_EP_DIR;
+                        omap_writew(UDC_CLR_HALT, UDC_CTRL);
+                        omap_writew(UDC_EP_DIR, UDC_EP_NUM);
                 } else {
-                        UDC_EP_NUM_REG = UDC_EP_DIR;
+                        omap_writew(UDC_EP_DIR, UDC_EP_NUM);
                 }
         }
 
@@ -1503,9 +1520,9 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
         if (irq_src & UDC_EP0_RX) {
                 int     stat;
 
-                UDC_IRQ_SRC_REG = UDC_EP0_RX;
-                UDC_EP_NUM_REG = UDC_EP_SEL;
-                stat = UDC_STAT_FLG_REG;
+                omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
+                omap_writew(UDC_EP_SEL, UDC_EP_NUM);
+                stat = omap_readw(UDC_STAT_FLG);
                 if (stat & UDC_ACK) {
                         if (!udc->ep0_in) {
                                 stat = 0;
@@ -1513,34 +1530,35 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
                                  * reactiviting the fifo; stall on errors.
                                  */
                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
-                                        UDC_SYSCON2_REG = UDC_STALL_CMD;
+                                        omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
                                         udc->ep0_pending = 0;
                                         stat = 0;
                                 } else if (stat == 0)
-                                        UDC_CTRL_REG = UDC_SET_FIFO_EN;
-                                UDC_EP_NUM_REG = 0;
+                                        omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
+                                omap_writew(0, UDC_EP_NUM);
 
                                 /* activate status stage */
                                 if (stat == 1) {
                                         done(ep0, req, 0);
                                         /* that may have STALLed ep0... */
-                                        UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
-                                        UDC_CTRL_REG = UDC_CLR_EP;
-                                        UDC_CTRL_REG = UDC_SET_FIFO_EN;
-                                        UDC_EP_NUM_REG = UDC_EP_DIR;
+                                        omap_writew(UDC_EP_SEL | UDC_EP_DIR,
+                                                        UDC_EP_NUM);
+                                        omap_writew(UDC_CLR_EP, UDC_CTRL);
+                                        omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
+                                        omap_writew(UDC_EP_DIR, UDC_EP_NUM);
                                         udc->ep0_pending = 0;
                                 }
                         } else {
                                 /* ack status stage of IN transfer */
-                                UDC_EP_NUM_REG = 0;
+                                omap_writew(0, UDC_EP_NUM);
                                 if (req)
                                         done(ep0, req, 0);
                         }
                 } else if (stat & UDC_STALL) {
-                        UDC_CTRL_REG = UDC_CLR_HALT;
-                        UDC_EP_NUM_REG = 0;
+                        omap_writew(UDC_CLR_HALT, UDC_CTRL);
+                        omap_writew(0, UDC_EP_NUM);
                 } else {
-                        UDC_EP_NUM_REG = 0;
+                        omap_writew(0, UDC_EP_NUM);
                 }
         }
 
@@ -1555,14 +1573,14 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
 
                 /* read the (latest) SETUP message */
                 do {
-                        UDC_EP_NUM_REG = UDC_SETUP_SEL;
+                        omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
                         /* two bytes at a time */
-                        u.word[0] = UDC_DATA_REG;
-                        u.word[1] = UDC_DATA_REG;
-                        u.word[2] = UDC_DATA_REG;
-                        u.word[3] = UDC_DATA_REG;
-                        UDC_EP_NUM_REG = 0;
-                } while (UDC_IRQ_SRC_REG & UDC_SETUP);
+                        u.word[0] = omap_readw(UDC_DATA);
+                        u.word[1] = omap_readw(UDC_DATA);
+                        u.word[2] = omap_readw(UDC_DATA);
+                        u.word[3] = omap_readw(UDC_DATA);
+                        omap_writew(0, UDC_EP_NUM);
+                } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
 
 #define w_value         le16_to_cpu(u.r.wValue)
 #define w_index         le16_to_cpu(u.r.wIndex)
@@ -1593,9 +1611,9 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
                          * later if it fails the request.
                          */
                         if (udc->ep0_reset_config)
-                                UDC_SYSCON2_REG = UDC_CLR_CFG;
+                                omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
                         else
-                                UDC_SYSCON2_REG = UDC_DEV_CFG;
+                                omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
                         update_otg(udc);
                         goto delegate;
                 case USB_REQ_CLEAR_FEATURE:
@@ -1613,10 +1631,10 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
                                                 || !ep->desc)
                                         goto do_stall;
                                 use_ep(ep, 0);
-                                UDC_CTRL_REG = udc->clr_halt;
+                                omap_writew(udc->clr_halt, UDC_CTRL);
                                 ep->ackwait = 0;
                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
-                                        UDC_CTRL_REG = UDC_SET_FIFO_EN;
+                                        omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
                                         ep->ackwait = 1 + ep->double_buf;
                                 }
                                 /* NOTE:  assumes the host behaves sanely,
@@ -1649,15 +1667,15 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
                         }
                         use_ep(ep, 0);
                         /* can't halt if fifo isn't empty... */
-                        UDC_CTRL_REG = UDC_CLR_EP;
-                        UDC_CTRL_REG = UDC_SET_HALT;
+                        omap_writew(UDC_CLR_EP, UDC_CTRL);
+                        omap_writew(UDC_SET_HALT, UDC_CTRL);
                         VDBG("%s halted by host\n", ep->name);
 ep0out_status_stage:
                         status = 0;
-                        UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
-                        UDC_CTRL_REG = UDC_CLR_EP;
-                        UDC_CTRL_REG = UDC_SET_FIFO_EN;
-                        UDC_EP_NUM_REG = UDC_EP_DIR;
+                        omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
+                        omap_writew(UDC_CLR_EP, UDC_CTRL);
+                        omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
+                        omap_writew(UDC_EP_DIR, UDC_EP_NUM);
                         udc->ep0_pending = 0;
                         break;
                 case USB_REQ_GET_STATUS:
@@ -1694,10 +1712,10 @@ intf_status:
 
 zero_status:
                         /* return two zero bytes */
-                        UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
-                        UDC_DATA_REG = 0;
-                        UDC_CTRL_REG = UDC_SET_FIFO_EN;
-                        UDC_EP_NUM_REG = UDC_EP_DIR;
+                        omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
+                        omap_writew(0, UDC_DATA);
+                        omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
+                        omap_writew(UDC_EP_DIR, UDC_EP_NUM);
                         status = 0;
                         VDBG("GET_STATUS, interface %d\n", w_index);
                         /* next, status stage */
@@ -1706,8 +1724,8 @@ zero_status:
 delegate:
                         /* activate the ep0out fifo right away */
                         if (!udc->ep0_in && w_length) {
-                                UDC_EP_NUM_REG = 0;
-                                UDC_CTRL_REG = UDC_SET_FIFO_EN;
+                                omap_writew(0, UDC_EP_NUM);
+                                omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
                         }
 
                         /* gadget drivers see class/vendor specific requests,
@@ -1748,9 +1766,9 @@ do_stall:
                                 if (udc->ep0_reset_config)
                                         WARN("error resetting config?\n");
                                 else
-                                        UDC_SYSCON2_REG = UDC_CLR_CFG;
+                                        omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
                         }
-                        UDC_SYSCON2_REG = UDC_STALL_CMD;
+                        omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
                         udc->ep0_pending = 0;
                 }
         }
@@ -1764,7 +1782,7 @@ static void devstate_irq(struct omap_udc *udc, u16 irq_src)
 {
         u16     devstat, change;
 
-        devstat = UDC_DEVSTAT_REG;
+        devstat = omap_readw(UDC_DEVSTAT);
         change = devstat ^ udc->devstat;
         udc->devstat = devstat;
 
@@ -1804,7 +1822,8 @@ static void devstate_irq(struct omap_udc *udc, u16 irq_src)
                                 INFO("USB reset done, gadget %s\n",
                                         udc->driver->driver.name);
                                 /* ep0 traffic is legal from now on */
-                                UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
+                                omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
+                                                UDC_IRQ_EN);
                         }
                         change &= ~UDC_USB_RESET;
                 }
@@ -1848,7 +1867,7 @@ static void devstate_irq(struct omap_udc *udc, u16 irq_src)
                 VDBG("devstat %03x, ignore change %03x\n",
                         devstat,  change);
 
-        UDC_IRQ_SRC_REG = UDC_DS_CHG;
+        omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
 }
 
 static irqreturn_t omap_udc_irq(int irq, void *_udc)
@@ -1859,7 +1878,7 @@ static irqreturn_t omap_udc_irq(int irq, void *_udc)
         unsigned long   flags;
 
         spin_lock_irqsave(&udc->lock, flags);
-        irq_src = UDC_IRQ_SRC_REG;
+        irq_src = omap_readw(UDC_IRQ_SRC);
 
         /* Device state change (usb ch9 stuff) */
         if (irq_src & UDC_DS_CHG) {
@@ -1882,7 +1901,7 @@ static irqreturn_t omap_udc_irq(int irq, void *_udc)
                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
         }
 
-        irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
+        irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
         if (irq_src)
                 DBG("udc_irq, unhandled %03x\n", irq_src);
         spin_unlock_irqrestore(&udc->lock, flags);
@@ -1903,7 +1922,7 @@ static void pio_out_timer(unsigned long _ep)
         spin_lock_irqsave(&ep->udc->lock, flags);
         if (!list_empty(&ep->queue) && ep->ackwait) {
                 use_ep(ep, UDC_EP_SEL);
-                stat_flg = UDC_STAT_FLG_REG;
+                stat_flg = omap_readw(UDC_STAT_FLG);
 
                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
@@ -1913,8 +1932,8 @@ static void pio_out_timer(unsigned long _ep)
                         req = container_of(ep->queue.next,
                                         struct omap_req, queue);
                         (void) read_fifo(ep, req);
-                        UDC_EP_NUM_REG = ep->bEndpointAddress;
-                        UDC_CTRL_REG = UDC_SET_FIFO_EN;
+                        omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
+                        omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
                         ep->ackwait = 1 + ep->double_buf;
                 } else
                         deselect_ep();
@@ -1934,20 +1953,20 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
         unsigned long   flags;
 
         spin_lock_irqsave(&udc->lock, flags);
-        epn_stat = UDC_EPN_STAT_REG;
-        irq_src = UDC_IRQ_SRC_REG;
+        epn_stat = omap_readw(UDC_EPN_STAT);
+        irq_src = omap_readw(UDC_IRQ_SRC);
 
         /* handle OUT first, to avoid some wasteful NAKs */
         if (irq_src & UDC_EPN_RX) {
                 epnum = (epn_stat >> 8) & 0x0f;
-                UDC_IRQ_SRC_REG = UDC_EPN_RX;
+                omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
                 status = IRQ_HANDLED;
                 ep = &udc->ep[epnum];
                 ep->irqs++;
 
-                UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
+                omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
                 ep->fnf = 0;
-                if ((UDC_STAT_FLG_REG & UDC_ACK)) {
+                if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
                         ep->ackwait--;
                         if (!list_empty(&ep->queue)) {
                                 int stat;
@@ -1959,15 +1978,15 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
                         }
                 }
                 /* min 6 clock delay before clearing EP_SEL ... */
-                epn_stat = UDC_EPN_STAT_REG;
-                epn_stat = UDC_EPN_STAT_REG;
-                UDC_EP_NUM_REG = epnum;
+                epn_stat = omap_readw(UDC_EPN_STAT);
+                epn_stat = omap_readw(UDC_EPN_STAT);
+                omap_writew(epnum, UDC_EP_NUM);
 
                 /* enabling fifo _after_ clearing ACK, contrary to docs,
                  * reduces lossage; timer still needed though (sigh).
                  */
                 if (ep->fnf) {
-                        UDC_CTRL_REG = UDC_SET_FIFO_EN;
+                        omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
                         ep->ackwait = 1 + ep->double_buf;
                 }
                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
@@ -1976,13 +1995,13 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
         /* then IN transfers */
         else if (irq_src & UDC_EPN_TX) {
                 epnum = epn_stat & 0x0f;
-                UDC_IRQ_SRC_REG = UDC_EPN_TX;
+                omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
                 status = IRQ_HANDLED;
                 ep = &udc->ep[16 + epnum];
                 ep->irqs++;
 
-                UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
-                if ((UDC_STAT_FLG_REG & UDC_ACK)) {
+                omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
+                if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
                         ep->ackwait = 0;
                         if (!list_empty(&ep->queue)) {
                                 req = container_of(ep->queue.next,
@@ -1991,9 +2010,9 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
                         }
                 }
                 /* min 6 clock delay before clearing EP_SEL ... */
-                epn_stat = UDC_EPN_STAT_REG;
-                epn_stat = UDC_EPN_STAT_REG;
-                UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
+                epn_stat = omap_readw(UDC_EPN_STAT);
+                epn_stat = omap_readw(UDC_EPN_STAT);
+                omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
                 /* then 6 clocks before it'd tx */
         }
 
@@ -2021,7 +2040,7 @@ static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
                 req = list_entry(ep->queue.next, struct omap_req, queue);
 
                 use_ep(ep, UDC_EP_SEL);
-                stat = UDC_STAT_FLG_REG;
+                stat = omap_readw(UDC_STAT_FLG);
 
                 /* NOTE: like the other controller drivers, this isn't
                  * currently reporting lost or damaged frames.
@@ -2053,9 +2072,14 @@ static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
                 if (!list_empty(&ep->queue))
                         pending = 1;
         }
-        if (!pending)
-                UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
-        UDC_IRQ_SRC_REG = UDC_SOF;
+        if (!pending) {
+                u16 w;
+
+                w = omap_readw(UDC_IRQ_EN);
+                w &= ~UDC_SOF_IE;
+                omap_writew(w, UDC_IRQ_EN);
+        }
+        omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
 
         spin_unlock_irqrestore(&udc->lock, flags);
         return IRQ_HANDLED;
@@ -2104,7 +2128,7 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver)
                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
                         continue;
                 use_ep(ep, 0);
-                UDC_CTRL_REG = UDC_SET_HALT;
+                omap_writew(UDC_SET_HALT, UDC_CTRL);
         }
         udc->ep0_pending = 0;
         udc->ep[0].irqs = 0;
@@ -2128,7 +2152,7 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver)
         }
         DBG("bound to driver %s\n", driver->driver.name);
 
-        UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
+        omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
 
         /* connect to bus through transceiver */
         if (udc->transceiver) {
@@ -2225,7 +2249,7 @@ static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
         else
                 buf[0] = 0;
 
-        stat_flg = UDC_STAT_FLG_REG;
+        stat_flg = omap_readw(UDC_STAT_FLG);
         seq_printf(s,
                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
                 ep->name, buf,
@@ -2292,11 +2316,11 @@ static int proc_otg_show(struct seq_file *s)
                 trans = CONTROL_DEVCONF_REG;
         } else {
                 ctrl_name = "tranceiver_ctrl";
-                trans = USB_TRANSCEIVER_CTRL_REG;
+                trans = omap_readw(USB_TRANSCEIVER_CTRL);
         }
         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
-        tmp = OTG_SYSCON_1_REG;
+        tmp = omap_readw(OTG_SYSCON_1);
         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
                         FOURBITS "\n", tmp,
                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
@@ -2308,7 +2332,7 @@ static int proc_otg_show(struct seq_file *s)
                 (tmp & HST_IDLE_EN) ? " !host" : "",
                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
-        tmp = OTG_SYSCON_2_REG;
+        tmp = omap_readl(OTG_SYSCON_2);
         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
                         " b_ase_brst=%d hmc=%d\n", tmp,
                 (tmp & OTG_EN) ? " otg_en" : "",
@@ -2323,7 +2347,7 @@ static int proc_otg_show(struct seq_file *s)
                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
                 B_ASE_BRST(tmp),
                 OTG_HMC(tmp));
-        tmp = OTG_CTRL_REG;
+        tmp = omap_readl(OTG_CTRL);
         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
                 (tmp & OTG_ASESSVLD) ? " asess" : "",
                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
@@ -2343,13 +2367,13 @@ static int proc_otg_show(struct seq_file *s)
                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
                 (tmp & OTG_PU_ID) ? " pu_id" : ""
                 );
-        tmp = OTG_IRQ_EN_REG;
+        tmp = omap_readw(OTG_IRQ_EN);
         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
-        tmp = OTG_IRQ_SRC_REG;
+        tmp = omap_readw(OTG_IRQ_SRC);
         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
-        tmp = OTG_OUTCTRL_REG;
+        tmp = omap_readw(OTG_OUTCTRL);
         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
-        tmp = OTG_TEST_REG;
+        tmp = omap_readw(OTG_TEST);
         seq_printf(s, "otg_test    %04x" "\n", tmp);
         return 0;
 }
@@ -2370,7 +2394,7 @@ static int proc_udc_show(struct seq_file *s, void *_)
                 driver_desc,
                 use_dma ?  " (dma)" : "");
 
-        tmp = UDC_REV_REG & 0xff;
+        tmp = omap_readw(UDC_REV) & 0xff;
         seq_printf(s,
                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
                 "hmc %d, transceiver %s\n",
@@ -2384,16 +2408,16 @@ static int proc_udc_show(struct seq_file *s, void *_)
                                 ? "external" : "(none)"));
         if (cpu_class_is_omap1()) {
                 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
-                        __REG16(ULPD_CLOCK_CTRL),
-                        __REG16(ULPD_SOFT_REQ),
-                        __REG16(ULPD_STATUS_REQ));
+                        omap_readw(ULPD_CLOCK_CTRL),
+                        omap_readw(ULPD_SOFT_REQ),
+                        omap_readw(ULPD_STATUS_REQ));
         }
 
         /* OTG controller registers */
         if (!cpu_is_omap15xx())
                 proc_otg_show(s);
 
-        tmp = UDC_SYSCON1_REG;
+        tmp = omap_readw(UDC_SYSCON1);
         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
@@ -2412,7 +2436,7 @@ static int proc_udc_show(struct seq_file *s, void *_)
                 return 0;
         }
 
-        tmp = UDC_DEVSTAT_REG;
+        tmp = omap_readw(UDC_DEVSTAT);
         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
@@ -2424,20 +2448,20 @@ static int proc_udc_show(struct seq_file *s, void *_)
                 (tmp & UDC_ADD) ? " ADD" : "",
                 (tmp & UDC_DEF) ? " DEF" : "",
                 (tmp & UDC_ATT) ? " ATT" : "");
-        seq_printf(s, "sof         %04x\n", UDC_SOF_REG);
-        tmp = UDC_IRQ_EN_REG;
+        seq_printf(s, "sof         %04x\n", omap_readw(UDC_SOF));
+        tmp = omap_readw(UDC_IRQ_EN);
         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
                 (tmp & UDC_SOF_IE) ? " sof" : "",
                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
                 (tmp & UDC_EP0_IE) ? " ep0" : "");
-        tmp = UDC_IRQ_SRC_REG;
+        tmp = omap_readw(UDC_IRQ_SRC);
         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
-                (tmp & UDC_SOF) ? " sof" : "",
+                (tmp & UDC_IRQ_SOF) ? " sof" : "",
                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
@@ -2447,7 +2471,7 @@ static int proc_udc_show(struct seq_file *s, void *_)
         if (use_dma) {
                 unsigned i;
 
-                tmp = UDC_DMA_IRQ_EN_REG;
+                tmp = omap_readw(UDC_DMA_IRQ_EN);
                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
@@ -2461,29 +2485,29 @@ static int proc_udc_show(struct seq_file *s, void *_)
                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
 
-                tmp = UDC_RXDMA_CFG_REG;
+                tmp = omap_readw(UDC_RXDMA_CFG);
                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
                 if (tmp) {
                         for (i = 0; i < 3; i++) {
                                 if ((tmp & (0x0f << (i * 4))) == 0)
                                         continue;
                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
-                                                UDC_RXDMA_REG(i + 1));
+                                                omap_readw(UDC_RXDMA(i + 1)));
                         }
                 }
-                tmp = UDC_TXDMA_CFG_REG;
+                tmp = omap_readw(UDC_TXDMA_CFG);
                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
                 if (tmp) {
                         for (i = 0; i < 3; i++) {
                                 if (!(tmp & (0x0f << (i * 4))))
                                         continue;
                                 seq_printf(s, "txdma[%d]    %04x\n", i,
-                                                UDC_TXDMA_REG(i + 1));
+                                                omap_readw(UDC_TXDMA(i + 1)));
                         }
                 }
         }
 
-        tmp = UDC_DEVSTAT_REG;
+        tmp = omap_readw(UDC_DEVSTAT);
         if (tmp & UDC_ATT) {
                 proc_ep_show(s, &udc->ep[0]);
                 if (tmp & UDC_ADD) {
@@ -2535,7 +2559,7 @@ static inline void remove_proc_file(void) {}
  * buffer space among the endpoints we'll be operating.
  *
  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
- * UDC_SYSCON_1_REG.CFG_LOCK is set can now work.  We won't use that
+ * UDC_SYSCON_1.CFG_LOCK is set can now work.  We won't use that
  * capability yet though.
  */
 static unsigned __init
@@ -2597,9 +2621,9 @@ omap_ep_setup(char *name, u8 addr, u8 type,
                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
 
         if (addr & USB_DIR_IN)
-                UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
+                omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
         else
-                UDC_EP_RX_REG(addr) = epn_rxtx;
+                omap_writew(epn_rxtx, UDC_EP_RX(addr));
 
         /* next endpoint's buffer starts after this one's */
         buf += maxp;
@@ -2638,15 +2662,15 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
         unsigned        tmp, buf;
 
         /* abolish any previous hardware state */
-        UDC_SYSCON1_REG = 0;
-        UDC_IRQ_EN_REG = 0;
-        UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
-        UDC_DMA_IRQ_EN_REG = 0;
-        UDC_RXDMA_CFG_REG = 0;
-        UDC_TXDMA_CFG_REG = 0;
+        omap_writew(0, UDC_SYSCON1);
+        omap_writew(0, UDC_IRQ_EN);
+        omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
+        omap_writew(0, UDC_DMA_IRQ_EN);
+        omap_writew(0, UDC_RXDMA_CFG);
+        omap_writew(0, UDC_TXDMA_CFG);
 
         /* UDC_PULLUP_EN gates the chip clock */
-        // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
+        // OTG_SYSCON_1 |= DEV_IDLE_EN;
 
         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
         if (!udc)
@@ -2677,8 +2701,8 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
 
         /* initially disable all non-ep0 endpoints */
         for (tmp = 1; tmp < 15; tmp++) {
-                UDC_EP_RX_REG(tmp) = 0;
-                UDC_EP_TX_REG(tmp) = 0;
+                omap_writew(0, UDC_EP_RX(tmp));
+                omap_writew(0, UDC_EP_TX(tmp));
         }
 
 #define OMAP_BULK_EP(name,addr) \
@@ -2763,7 +2787,7 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
                 return -ENODEV;
         }
-        UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
+        omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
         return 0;
 }
@@ -2807,7 +2831,7 @@ static int __init omap_udc_probe(struct platform_device *pdev)
         }
 
         INFO("OMAP UDC rev %d.%d%s\n",
-                UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
+                omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
                 config->otg ? ", Mini-AB" : "");
 
         /* use the mode given to us by board init code */
@@ -2822,12 +2846,12 @@ static int __init omap_udc_probe(struct platform_device *pdev)
                          * know when to turn PULLUP_EN on/off; and that
                          * means we always "need" the 48MHz clock.
                          */
-                        u32 tmp = FUNC_MUX_CTRL_0_REG;
-
-                        FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
+                        u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
+                        tmp &= ~VBUS_CTRL_1510;
+                        omap_writel(tmp, FUNC_MUX_CTRL_0);
                         tmp |= VBUS_MODE_1510;
                         tmp &= ~VBUS_CTRL_1510;
-                        FUNC_MUX_CTRL_0_REG = tmp;
+                        omap_writel(tmp, FUNC_MUX_CTRL_0);
                 }
         } else {
                 /* The transceiver may package some GPIO logic or handle
@@ -2907,7 +2931,7 @@ known:
 #endif
 
         /* starting with omap1710 es2.0, clear toggle is a separate bit */
-        if (UDC_REV_REG >= 0x61)
+        if (omap_readw(UDC_REV) >= 0x61)
                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
         else
                 udc->clr_halt = UDC_RESET_EP;
@@ -3005,7 +3029,7 @@ static int __exit omap_udc_remove(struct platform_device *pdev)
                 put_device(udc->transceiver->dev);
                 udc->transceiver = NULL;
         }
-        UDC_SYSCON1_REG = 0;
+        omap_writew(0, UDC_SYSCON1);
 
         remove_proc_file();
 
@@ -3036,7 +3060,7 @@ static int __exit omap_udc_remove(struct platform_device *pdev)
  *
  * REVISIT we should probably reject suspend requests when there's a host
  * session active, rather than disconnecting, at least on boards that can
- * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT).  And in any case, we need to
+ * report VBUS irqs (UDC_DEVSTAT.UDC_ATT).  And in any case, we need to
  * make host resumes and VBUS detection trigger OMAP wakeup events; that
  * may involve talking to an external transceiver (e.g. isp1301).
  */
@@ -3045,7 +3069,7 @@ static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
 {
         u32     devstat;
 
-        devstat = UDC_DEVSTAT_REG;
+        devstat = omap_readw(UDC_DEVSTAT);
 
         /* we're requesting 48 MHz clock if the pullup is enabled
          * (== we're attached to the host) and we're not suspended,
diff --git a/drivers/usb/gadget/omap_udc.h b/drivers/usb/gadget/omap_udc.h
index c6b9cbc7230a..8522bbb12278 100644
--- a/drivers/usb/gadget/omap_udc.h
+++ b/drivers/usb/gadget/omap_udc.h
@@ -8,23 +8,22 @@
 /*
  * USB device/endpoint management registers
  */
-#define UDC_REG(offset)              __REG16(UDC_BASE + (offset))
 
-#define UDC_REV_REG                     UDC_REG(0x0)    /* Revision */
-#define UDC_EP_NUM_REG                  UDC_REG(0x4)    /* Which endpoint */
+#define UDC_REV                         (UDC_BASE + 0x0)        /* Revision */
+#define UDC_EP_NUM                      (UDC_BASE + 0x4)        /* Which endpoint */
 #       define  UDC_SETUP_SEL           (1 << 6)
 #       define  UDC_EP_SEL              (1 << 5)
 #       define  UDC_EP_DIR              (1 << 4)
         /* low 4 bits for endpoint number */
-#define UDC_DATA_REG                    UDC_REG(0x08)   /* Endpoint FIFO */
-#define UDC_CTRL_REG                    UDC_REG(0x0C)   /* Endpoint control */
+#define UDC_DATA                        (UDC_BASE + 0x08)       /* Endpoint FIFO */
+#define UDC_CTRL                        (UDC_BASE + 0x0C)       /* Endpoint control */
 #       define  UDC_CLR_HALT            (1 << 7)
 #       define  UDC_SET_HALT            (1 << 6)
 #       define  UDC_CLRDATA_TOGGLE      (1 << 3)
 #       define  UDC_SET_FIFO_EN         (1 << 2)
 #       define  UDC_CLR_EP              (1 << 1)
 #       define  UDC_RESET_EP            (1 << 0)
-#define UDC_STAT_FLG_REG                UDC_REG(0x10)   /* Endpoint status */
+#define UDC_STAT_FLG                    (UDC_BASE + 0x10)       /* Endpoint status */
 #       define  UDC_NO_RXPACKET         (1 << 15)
 #       define  UDC_MISS_IN             (1 << 14)
 #       define  UDC_DATA_FLUSH          (1 << 13)
@@ -38,8 +37,8 @@
 #       define  UDC_FIFO_EN             (1 << 2)
 #       define  UDC_NON_ISO_FIFO_EMPTY  (1 << 1)
 #       define  UDC_NON_ISO_FIFO_FULL   (1 << 0)
-#define UDC_RXFSTAT_REG                 UDC_REG(0x14)   /* OUT bytecount */
-#define UDC_SYSCON1_REG                 UDC_REG(0x18)   /* System config 1 */
+#define UDC_RXFSTAT                     (UDC_BASE + 0x14)       /* OUT bytecount */
+#define UDC_SYSCON1                     (UDC_BASE + 0x18)       /* System config 1 */
 #       define  UDC_CFG_LOCK            (1 << 8)
 #       define  UDC_DATA_ENDIAN         (1 << 7)
 #       define  UDC_DMA_ENDIAN          (1 << 6)
@@ -48,12 +47,12 @@
 #       define  UDC_SELF_PWR            (1 << 2)
 #       define  UDC_SOFF_DIS            (1 << 1)
 #       define  UDC_PULLUP_EN           (1 << 0)
-#define UDC_SYSCON2_REG                 UDC_REG(0x1C)   /* System config 2 */
+#define UDC_SYSCON2                     (UDC_BASE + 0x1C)       /* System config 2 */
 #       define  UDC_RMT_WKP             (1 << 6)
 #       define  UDC_STALL_CMD           (1 << 5)
 #       define  UDC_DEV_CFG             (1 << 3)
 #       define  UDC_CLR_CFG             (1 << 2)
-#define UDC_DEVSTAT_REG                 UDC_REG(0x20)   /* Device status */
+#define UDC_DEVSTAT                     (UDC_BASE + 0x20)       /* Device status */
 #       define  UDC_B_HNP_ENABLE        (1 << 9)
 #       define  UDC_A_HNP_SUPPORT       (1 << 8)
 #       define  UDC_A_ALT_HNP_SUPPORT   (1 << 7)
@@ -64,26 +63,26 @@
 #       define  UDC_ADD                 (1 << 2)
 #       define  UDC_DEF                 (1 << 1)
 #       define  UDC_ATT                 (1 << 0)
-#define UDC_SOF_REG                     UDC_REG(0x24)   /* Start of frame */
+#define UDC_SOF                         (UDC_BASE + 0x24)       /* Start of frame */
 #       define  UDC_FT_LOCK             (1 << 12)
 #       define  UDC_TS_OK               (1 << 11)
 #       define  UDC_TS                  0x03ff
-#define UDC_IRQ_EN_REG                  UDC_REG(0x28)   /* Interrupt enable */
+#define UDC_IRQ_EN                      (UDC_BASE + 0x28)       /* Interrupt enable */
 #       define  UDC_SOF_IE              (1 << 7)
 #       define  UDC_EPN_RX_IE           (1 << 5)
 #       define  UDC_EPN_TX_IE           (1 << 4)
 #       define  UDC_DS_CHG_IE           (1 << 3)
 #       define  UDC_EP0_IE              (1 << 0)
-#define UDC_DMA_IRQ_EN_REG              UDC_REG(0x2C)   /* DMA irq enable */
+#define UDC_DMA_IRQ_EN                  (UDC_BASE + 0x2C)       /* DMA irq enable */
         /* rx/tx dma channels numbered 1-3 not 0-2 */
 #       define  UDC_TX_DONE_IE(n)       (1 << (4 * (n) - 2))
 #       define  UDC_RX_CNT_IE(n)        (1 << (4 * (n) - 3))
 #       define  UDC_RX_EOT_IE(n)        (1 << (4 * (n) - 4))
-#define UDC_IRQ_SRC_REG                 UDC_REG(0x30)   /* Interrupt source */
+#define UDC_IRQ_SRC                     (UDC_BASE + 0x30)       /* Interrupt source */
 #       define  UDC_TXN_DONE            (1 << 10)
 #       define  UDC_RXN_CNT             (1 << 9)
 #       define  UDC_RXN_EOT             (1 << 8)
-#       define  UDC_SOF                 (1 << 7)
+#       define  UDC_IRQ_SOF             (1 << 7)
 #       define  UDC_EPN_RX              (1 << 5)
 #       define  UDC_EPN_TX              (1 << 4)
 #       define  UDC_DS_CHG              (1 << 3)
@@ -91,41 +90,41 @@
 #       define  UDC_EP0_RX              (1 << 1)
 #       define  UDC_EP0_TX              (1 << 0)
 #       define  UDC_IRQ_SRC_MASK        0x7bf
-#define UDC_EPN_STAT_REG                UDC_REG(0x34)   /* EP irq status */
-#define UDC_DMAN_STAT_REG               UDC_REG(0x38)   /* DMA irq status */
+#define UDC_EPN_STAT                    (UDC_BASE + 0x34)       /* EP irq status */
+#define UDC_DMAN_STAT                   (UDC_BASE + 0x38)       /* DMA irq status */
 #       define  UDC_DMA_RX_SB           (1 << 12)
 #       define  UDC_DMA_RX_SRC(x)       (((x)>>8) & 0xf)
 #       define  UDC_DMA_TX_SRC(x)       (((x)>>0) & 0xf)
 
 
 /* DMA configuration registers:  up to three channels in each direction.  */
-#define UDC_RXDMA_CFG_REG               UDC_REG(0x40)   /* 3 eps for RX DMA */
+#define UDC_RXDMA_CFG                   (UDC_BASE + 0x40)       /* 3 eps for RX DMA */
 #       define  UDC_DMA_REQ             (1 << 12)
-#define UDC_TXDMA_CFG_REG               UDC_REG(0x44)   /* 3 eps for TX DMA */
-#define UDC_DATA_DMA_REG                UDC_REG(0x48)   /* rx/tx fifo addr */
+#define UDC_TXDMA_CFG                   (UDC_BASE + 0x44)       /* 3 eps for TX DMA */
+#define UDC_DATA_DMA                    (UDC_BASE + 0x48)       /* rx/tx fifo addr */
 
 /* rx/tx dma control, numbering channels 1-3 not 0-2 */
-#define UDC_TXDMA_REG(chan)             UDC_REG(0x50 - 4 + 4 * (chan))
+#define UDC_TXDMA(chan)                 (UDC_BASE + 0x50 - 4 + 4 * (chan))
 #       define UDC_TXN_EOT              (1 << 15)       /* bytes vs packets */
 #       define UDC_TXN_START            (1 << 14)       /* start transfer */
 #       define UDC_TXN_TSC              0x03ff          /* units in xfer */
-#define UDC_RXDMA_REG(chan)             UDC_REG(0x60 - 4 + 4 * (chan))
+#define UDC_RXDMA(chan)                 (UDC_BASE + 0x60 - 4 + 4 * (chan))
 #       define UDC_RXN_STOP             (1 << 15)       /* enable EOT irq */
 #       define UDC_RXN_TC               0x00ff          /* packets in xfer */
 
 
 /*
  * Endpoint configuration registers (used before CFG_LOCK is set)
- * UDC_EP_TX_REG(0) is unused
+ * UDC_EP_TX(0) is unused
  */
-#define UDC_EP_RX_REG(endpoint)         UDC_REG(0x80 + (endpoint)*4)
+#define UDC_EP_RX(endpoint)             (UDC_BASE + 0x80 + (endpoint)*4)
 #       define  UDC_EPN_RX_VALID        (1 << 15)
 #       define  UDC_EPN_RX_DB           (1 << 14)
         /* buffer size in bits 13, 12 */
 #       define  UDC_EPN_RX_ISO          (1 << 11)
         /* buffer pointer in low 11 bits */
-#define UDC_EP_TX_REG(endpoint)         UDC_REG(0xc0 + (endpoint)*4)
-        /* same bitfields as in RX_REG */
+#define UDC_EP_TX(endpoint)             (UDC_BASE + 0xc0 + (endpoint)*4)
+        /* same bitfields as in RX */
 
 /*-------------------------------------------------------------------------*/
 
@@ -195,14 +194,14 @@ struct omap_udc {
 
 /*-------------------------------------------------------------------------*/
 
-#define MOD_CONF_CTRL_0_REG     __REG32(MOD_CONF_CTRL_0)
-#define VBUS_W2FC_1510          (1 << 17)       /* 0 gpio0, 1 dvdd2 pin */
+/* MOD_CONF_CTRL_0 */
+#define VBUS_W2FC_1510          (1 << 17)       /* 0 gpio0, 1 dvdd2 pin */
 
-#define FUNC_MUX_CTRL_0_REG     __REG32(FUNC_MUX_CTRL_0)
+/* FUNC_MUX_CTRL_0 */
 #define VBUS_CTRL_1510          (1 << 19)       /* 1 connected (software) */
 #define VBUS_MODE_1510          (1 << 18)       /* 0 hardware, 1 software */
 
-#define HMC_1510        ((MOD_CONF_CTRL_0_REG >> 1) & 0x3f)
-#define HMC_1610        (OTG_SYSCON_2_REG & 0x3f)
+#define HMC_1510        ((omap_readl(MOD_CONF_CTRL_0) >> 1) & 0x3f)
+#define HMC_1610        (omap_readl(OTG_SYSCON_2) & 0x3f)
 #define HMC             (cpu_is_omap15xx() ? HMC_1510 : HMC_1610)
 
diff --git a/drivers/usb/gadget/pxa2xx_udc.c b/drivers/usb/gadget/pxa25x_udc.c
index 08f699b1fc57..031dceb93023 100644
--- a/drivers/usb/gadget/pxa2xx_udc.c
+++ b/drivers/usb/gadget/pxa25x_udc.c
@@ -1,5 +1,4 @@
 /*
- * linux/drivers/usb/gadget/pxa2xx_udc.c
  * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
  *
  * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
@@ -46,19 +45,25 @@
 #include <linux/err.h>
 #include <linux/seq_file.h>
 #include <linux/debugfs.h>
+#include <linux/io.h>
 
 #include <asm/byteorder.h>
 #include <asm/dma.h>
 #include <asm/gpio.h>
-#include <asm/io.h>
 #include <asm/system.h>
 #include <asm/mach-types.h>
 #include <asm/unaligned.h>
-#include <asm/hardware.h>
 
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 
+/*
+ * This driver is PXA25x only.  Grab the right register definitions.
+ */
+#ifdef CONFIG_ARCH_PXA
+#include <asm/arch/pxa25x-udc.h>
+#endif
+
 #include <asm/mach/udc_pxa2xx.h>
 
 
@@ -91,7 +96,7 @@
 #define DRIVER_DESC     "PXA 25x USB Device Controller driver"
 
 
-static const char driver_name [] = "pxa2xx_udc";
+static const char driver_name [] = "pxa25x_udc";
 
 static const char ep0name [] = "ep0";
 
@@ -111,10 +116,10 @@ static const char ep0name [] = "ep0";
 
 #endif
 
-#include "pxa2xx_udc.h"
+#include "pxa25x_udc.h"
 
 
-#ifdef  CONFIG_USB_PXA2XX_SMALL
+#ifdef  CONFIG_USB_PXA25X_SMALL
 #define SIZE_STR        " (small)"
 #else
 #define SIZE_STR        ""
@@ -126,8 +131,8 @@ static const char ep0name [] = "ep0";
  * ---------------------------------------------------------------------------
  */
 
-static void pxa2xx_ep_fifo_flush (struct usb_ep *ep);
-static void nuke (struct pxa2xx_ep *, int status);
+static void pxa25x_ep_fifo_flush (struct usb_ep *ep);
+static void nuke (struct pxa25x_ep *, int status);
 
 /* one GPIO should be used to detect VBUS from the host */
 static int is_vbus_present(void)
@@ -212,24 +217,24 @@ static inline void udc_ack_int_UDCCR(int mask)
 /*
  * endpoint enable/disable
  *
- * we need to verify the descriptors used to enable endpoints.  since pxa2xx
+ * we need to verify the descriptors used to enable endpoints.  since pxa25x
  * endpoint configurations are fixed, and are pretty much always enabled,
  * there's not a lot to manage here.
  *
- * because pxa2xx can't selectively initialize bulk (or interrupt) endpoints,
+ * because pxa25x can't selectively initialize bulk (or interrupt) endpoints,
  * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
  * for a single interface (with only the default altsetting) and for gadget
  * drivers that don't halt endpoints (not reset by set_interface).  that also
  * means that if you use ISO, you must violate the USB spec rule that all
  * iso endpoints must be in non-default altsettings.
  */
-static int pxa2xx_ep_enable (struct usb_ep *_ep,
+static int pxa25x_ep_enable (struct usb_ep *_ep,
                 const struct usb_endpoint_descriptor *desc)
 {
-        struct pxa2xx_ep        *ep;
-        struct pxa2xx_udc       *dev;
+        struct pxa25x_ep        *ep;
+        struct pxa25x_udc       *dev;
 
-        ep = container_of (_ep, struct pxa2xx_ep, ep);
+        ep = container_of (_ep, struct pxa25x_ep, ep);
         if (!_ep || !desc || ep->desc || _ep->name == ep0name
                         || desc->bDescriptorType != USB_DT_ENDPOINT
                         || ep->bEndpointAddress != desc->bEndpointAddress
@@ -268,7 +273,7 @@ static int pxa2xx_ep_enable (struct usb_ep *_ep,
         ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize);
 
         /* flush fifo (mostly for OUT buffers) */
-        pxa2xx_ep_fifo_flush (_ep);
+        pxa25x_ep_fifo_flush (_ep);
 
         /* ... reset halt state too, if we could ... */
 
@@ -276,12 +281,12 @@ static int pxa2xx_ep_enable (struct usb_ep *_ep,
         return 0;
 }
 
-static int pxa2xx_ep_disable (struct usb_ep *_ep)
+static int pxa25x_ep_disable (struct usb_ep *_ep)
 {
-        struct pxa2xx_ep        *ep;
+        struct pxa25x_ep        *ep;
         unsigned long           flags;
 
-        ep = container_of (_ep, struct pxa2xx_ep, ep);
+        ep = container_of (_ep, struct pxa25x_ep, ep);
         if (!_ep || !ep->desc) {
                 DMSG("%s, %s not enabled\n", __func__,
                         _ep ? ep->ep.name : NULL);
@@ -292,7 +297,7 @@ static int pxa2xx_ep_disable (struct usb_ep *_ep)
         nuke (ep, -ESHUTDOWN);
 
         /* flush fifo (mostly for IN buffers) */
-        pxa2xx_ep_fifo_flush (_ep);
+        pxa25x_ep_fifo_flush (_ep);
 
         ep->desc = NULL;
         ep->stopped = 1;
@@ -304,18 +309,18 @@ static int pxa2xx_ep_disable (struct usb_ep *_ep)
 
 /*-------------------------------------------------------------------------*/
 
-/* for the pxa2xx, these can just wrap kmalloc/kfree.  gadget drivers
+/* for the pxa25x, these can just wrap kmalloc/kfree.  gadget drivers
  * must still pass correctly initialized endpoints, since other controller
  * drivers may care about how it's currently set up (dma issues etc).
  */
 
 /*
- *      pxa2xx_ep_alloc_request - allocate a request data structure
+ *      pxa25x_ep_alloc_request - allocate a request data structure
  */
 static struct usb_request *
-pxa2xx_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags)
+pxa25x_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags)
 {
-        struct pxa2xx_request *req;
+        struct pxa25x_request *req;
 
         req = kzalloc(sizeof(*req), gfp_flags);
         if (!req)
@@ -327,14 +332,14 @@ pxa2xx_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags)
 
 
 /*
- *      pxa2xx_ep_free_request - deallocate a request data structure
+ *      pxa25x_ep_free_request - deallocate a request data structure
  */
 static void
-pxa2xx_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
+pxa25x_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
 {
-        struct pxa2xx_request   *req;
+        struct pxa25x_request   *req;
 
-        req = container_of (_req, struct pxa2xx_request, req);
+        req = container_of (_req, struct pxa25x_request, req);
         WARN_ON (!list_empty (&req->queue));
         kfree(req);
 }
@@ -344,7 +349,7 @@ pxa2xx_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
 /*
  *      done - retire a request; caller blocked irqs
  */
-static void done(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int status)
+static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status)
 {
         unsigned                stopped = ep->stopped;
 
@@ -367,13 +372,13 @@ static void done(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int status)
 }
 
 
-static inline void ep0_idle (struct pxa2xx_udc *dev)
+static inline void ep0_idle (struct pxa25x_udc *dev)
 {
         dev->ep0state = EP0_IDLE;
 }
 
 static int
-write_packet(volatile u32 *uddr, struct pxa2xx_request *req, unsigned max)
+write_packet(volatile u32 *uddr, struct pxa25x_request *req, unsigned max)
 {
         u8              *buf;
         unsigned        length, count;
@@ -398,7 +403,7 @@ write_packet(volatile u32 *uddr, struct pxa2xx_request *req, unsigned max)
  * caller guarantees at least one packet buffer is ready (or a zlp).
  */
 static int
-write_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
+write_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
 {
         unsigned                max;
 
@@ -455,7 +460,7 @@ write_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
  * ep0 data stage.  these chips want very simple state transitions.
  */
 static inline
-void ep0start(struct pxa2xx_udc *dev, u32 flags, const char *tag)
+void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag)
 {
         UDCCS0 = flags|UDCCS0_SA|UDCCS0_OPR;
         USIR0 = USIR0_IR0;
@@ -465,7 +470,7 @@ void ep0start(struct pxa2xx_udc *dev, u32 flags, const char *tag)
 }
 
 static int
-write_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
+write_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
 {
         unsigned        count;
         int             is_short;
@@ -525,7 +530,7 @@ write_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
  * request buffer having filled (and maybe overran till end-of-packet).
  */
 static int
-read_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
+read_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
 {
         for (;;) {
                 u32             udccs;
@@ -602,7 +607,7 @@ read_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
  * protocols do use them.
  */
 static int
-read_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
+read_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
 {
         u8              *buf, byte;
         unsigned        bufferspace;
@@ -641,21 +646,21 @@ read_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 /*-------------------------------------------------------------------------*/
 
 static int
-pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
+pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 {
-        struct pxa2xx_request   *req;
-        struct pxa2xx_ep        *ep;
-        struct pxa2xx_udc       *dev;
+        struct pxa25x_request   *req;
+        struct pxa25x_ep        *ep;
+        struct pxa25x_udc       *dev;
         unsigned long           flags;
 
-        req = container_of(_req, struct pxa2xx_request, req);
+        req = container_of(_req, struct pxa25x_request, req);
         if (unlikely (!_req || !_req->complete || !_req->buf
                         || !list_empty(&req->queue))) {
                 DMSG("%s, bad params\n", __func__);
                 return -EINVAL;
         }
 
-        ep = container_of(_ep, struct pxa2xx_ep, ep);
+        ep = container_of(_ep, struct pxa25x_ep, ep);
         if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
                 DMSG("%s, bad ep\n", __func__);
                 return -EINVAL;
@@ -751,14 +756,14 @@ pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 /*
  *      nuke - dequeue ALL requests
  */
-static void nuke(struct pxa2xx_ep *ep, int status)
+static void nuke(struct pxa25x_ep *ep, int status)
 {
-        struct pxa2xx_request *req;
+        struct pxa25x_request *req;
 
         /* called with irqs blocked */
         while (!list_empty(&ep->queue)) {
                 req = list_entry(ep->queue.next,
-                                struct pxa2xx_request,
+                                struct pxa25x_request,
                                 queue);
                 done(ep, req, status);
         }
@@ -768,13 +773,13 @@ static void nuke(struct pxa2xx_ep *ep, int status)
 
 
 /* dequeue JUST ONE request */
-static int pxa2xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 {
-        struct pxa2xx_ep        *ep;
-        struct pxa2xx_request   *req;
+        struct pxa25x_ep        *ep;
+        struct pxa25x_request   *req;
         unsigned long           flags;
 
-        ep = container_of(_ep, struct pxa2xx_ep, ep);
+        ep = container_of(_ep, struct pxa25x_ep, ep);
         if (!_ep || ep->ep.name == ep0name)
                 return -EINVAL;
 
@@ -798,12 +803,12 @@ static int pxa2xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 
 /*-------------------------------------------------------------------------*/
 
-static int pxa2xx_ep_set_halt(struct usb_ep *_ep, int value)
+static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value)
 {
-        struct pxa2xx_ep        *ep;
+        struct pxa25x_ep        *ep;
         unsigned long           flags;
 
-        ep = container_of(_ep, struct pxa2xx_ep, ep);
+        ep = container_of(_ep, struct pxa25x_ep, ep);
         if (unlikely (!_ep
                         || (!ep->desc && ep->ep.name != ep0name))
                         || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
@@ -853,11 +858,11 @@ static int pxa2xx_ep_set_halt(struct usb_ep *_ep, int value)
         return 0;
 }
 
-static int pxa2xx_ep_fifo_status(struct usb_ep *_ep)
+static int pxa25x_ep_fifo_status(struct usb_ep *_ep)
 {
-        struct pxa2xx_ep        *ep;
+        struct pxa25x_ep        *ep;
 
-        ep = container_of(_ep, struct pxa2xx_ep, ep);
+        ep = container_of(_ep, struct pxa25x_ep, ep);
         if (!_ep) {
                 DMSG("%s, bad ep\n", __func__);
                 return -ENODEV;
@@ -872,11 +877,11 @@ static int pxa2xx_ep_fifo_status(struct usb_ep *_ep)
                 return (*ep->reg_ubcr & 0xfff) + 1;
 }
 
-static void pxa2xx_ep_fifo_flush(struct usb_ep *_ep)
+static void pxa25x_ep_fifo_flush(struct usb_ep *_ep)
 {
-        struct pxa2xx_ep        *ep;
+        struct pxa25x_ep        *ep;
 
-        ep = container_of(_ep, struct pxa2xx_ep, ep);
+        ep = container_of(_ep, struct pxa25x_ep, ep);
         if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
                 DMSG("%s, bad ep\n", __func__);
                 return;
@@ -898,19 +903,19 @@ static void pxa2xx_ep_fifo_flush(struct usb_ep *_ep)
 }
 
 
-static struct usb_ep_ops pxa2xx_ep_ops = {
-        .enable         = pxa2xx_ep_enable,
-        .disable        = pxa2xx_ep_disable,
+static struct usb_ep_ops pxa25x_ep_ops = {
+        .enable         = pxa25x_ep_enable,
+        .disable        = pxa25x_ep_disable,
 
-        .alloc_request  = pxa2xx_ep_alloc_request,
-        .free_request   = pxa2xx_ep_free_request,
+        .alloc_request  = pxa25x_ep_alloc_request,
+        .free_request   = pxa25x_ep_free_request,
 
-        .queue          = pxa2xx_ep_queue,
-        .dequeue        = pxa2xx_ep_dequeue,
+        .queue          = pxa25x_ep_queue,
+        .dequeue        = pxa25x_ep_dequeue,
 
-        .set_halt       = pxa2xx_ep_set_halt,
-        .fifo_status    = pxa2xx_ep_fifo_status,
-        .fifo_flush     = pxa2xx_ep_fifo_flush,
+        .set_halt       = pxa25x_ep_set_halt,
+        .fifo_status    = pxa25x_ep_fifo_status,
+        .fifo_flush     = pxa25x_ep_fifo_flush,
 };
 
 
@@ -919,12 +924,12 @@ static struct usb_ep_ops pxa2xx_ep_ops = {
  * ---------------------------------------------------------------------------
  */
 
-static int pxa2xx_udc_get_frame(struct usb_gadget *_gadget)
+static int pxa25x_udc_get_frame(struct usb_gadget *_gadget)
 {
         return ((UFNRH & 0x07) << 8) | (UFNRL & 0xff);
 }
 
-static int pxa2xx_udc_wakeup(struct usb_gadget *_gadget)
+static int pxa25x_udc_wakeup(struct usb_gadget *_gadget)
 {
         /* host may not have enabled remote wakeup */
         if ((UDCCS0 & UDCCS0_DRWF) == 0)
@@ -933,14 +938,14 @@ static int pxa2xx_udc_wakeup(struct usb_gadget *_gadget)
         return 0;
 }
 
-static void stop_activity(struct pxa2xx_udc *, struct usb_gadget_driver *);
-static void udc_enable (struct pxa2xx_udc *);
-static void udc_disable(struct pxa2xx_udc *);
+static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *);
+static void udc_enable (struct pxa25x_udc *);
+static void udc_disable(struct pxa25x_udc *);
 
 /* We disable the UDC -- and its 48 MHz clock -- whenever it's not
  * in active use.
  */
-static int pullup(struct pxa2xx_udc *udc)
+static int pullup(struct pxa25x_udc *udc)
 {
         int is_active = udc->vbus && udc->pullup && !udc->suspended;
         DMSG("%s\n", is_active ? "active" : "inactive");
@@ -970,11 +975,11 @@ static int pullup(struct pxa2xx_udc *udc)
 }
 
 /* VBUS reporting logically comes from a transceiver */
-static int pxa2xx_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
+static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
 {
-        struct pxa2xx_udc       *udc;
+        struct pxa25x_udc       *udc;
 
-        udc = container_of(_gadget, struct pxa2xx_udc, gadget);
+        udc = container_of(_gadget, struct pxa25x_udc, gadget);
         udc->vbus = (is_active != 0);
         DMSG("vbus %s\n", is_active ? "supplied" : "inactive");
         pullup(udc);
@@ -982,11 +987,11 @@ static int pxa2xx_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
 }
 
 /* drivers may have software control over D+ pullup */
-static int pxa2xx_udc_pullup(struct usb_gadget *_gadget, int is_active)
+static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active)
 {
-        struct pxa2xx_udc       *udc;
+        struct pxa25x_udc       *udc;
 
-        udc = container_of(_gadget, struct pxa2xx_udc, gadget);
+        udc = container_of(_gadget, struct pxa25x_udc, gadget);
 
         /* not all boards support pullup control */
         if (!udc->mach->gpio_pullup && !udc->mach->udc_command)
@@ -997,11 +1002,11 @@ static int pxa2xx_udc_pullup(struct usb_gadget *_gadget, int is_active)
         return 0;
 }
 
-static const struct usb_gadget_ops pxa2xx_udc_ops = {
-        .get_frame      = pxa2xx_udc_get_frame,
-        .wakeup         = pxa2xx_udc_wakeup,
-        .vbus_session   = pxa2xx_udc_vbus_session,
-        .pullup         = pxa2xx_udc_pullup,
+static const struct usb_gadget_ops pxa25x_udc_ops = {
+        .get_frame      = pxa25x_udc_get_frame,
+        .wakeup         = pxa25x_udc_wakeup,
+        .vbus_session   = pxa25x_udc_vbus_session,
+        .pullup         = pxa25x_udc_pullup,
 
         // .vbus_draw ... boards may consume current from VBUS, up to
         // 100-500mA based on config.  the 500uA suspend ceiling means
@@ -1015,7 +1020,7 @@ static const struct usb_gadget_ops pxa2xx_udc_ops = {
 static int
 udc_seq_show(struct seq_file *m, void *_d)
 {
-        struct pxa2xx_udc       *dev = m->private;
+        struct pxa25x_udc       *dev = m->private;
         unsigned long           flags;
         int                     i;
         u32                     tmp;
@@ -1076,8 +1081,8 @@ udc_seq_show(struct seq_file *m, void *_d)
 
         /* dump endpoint queues */
         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
-                struct pxa2xx_ep        *ep = &dev->ep [i];
-                struct pxa2xx_request   *req;
+                struct pxa25x_ep        *ep = &dev->ep [i];
+                struct pxa25x_request   *req;
 
                 if (i != 0) {
                         const struct usb_endpoint_descriptor    *desc;
@@ -1150,7 +1155,7 @@ static const struct file_operations debug_fops = {
 /*
  *      udc_disable - disable USB device controller
  */
-static void udc_disable(struct pxa2xx_udc *dev)
+static void udc_disable(struct pxa25x_udc *dev)
 {
         /* block all irqs */
         udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
@@ -1170,7 +1175,7 @@ static void udc_disable(struct pxa2xx_udc *dev)
 /*
  *      udc_reinit - initialize software state
  */
-static void udc_reinit(struct pxa2xx_udc *dev)
+static void udc_reinit(struct pxa25x_udc *dev)
 {
         u32     i;
 
@@ -1181,7 +1186,7 @@ static void udc_reinit(struct pxa2xx_udc *dev)
 
         /* basic endpoint records init */
         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
-                struct pxa2xx_ep *ep = &dev->ep[i];
+                struct pxa25x_ep *ep = &dev->ep[i];
 
                 if (i != 0)
                         list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
@@ -1198,7 +1203,7 @@ static void udc_reinit(struct pxa2xx_udc *dev)
 /* until it's enabled, this UDC should be completely invisible
  * to any USB host.
  */
-static void udc_enable (struct pxa2xx_udc *dev)
+static void udc_enable (struct pxa25x_udc *dev)
 {
         udc_clear_mask_UDCCR(UDCCR_UDE);
 
@@ -1254,7 +1259,7 @@ static void udc_enable (struct pxa2xx_udc *dev)
  */
 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
 {
-        struct pxa2xx_udc       *dev = the_controller;
+        struct pxa25x_udc       *dev = the_controller;
         int                     retval;
 
         if (!driver
@@ -1299,7 +1304,7 @@ fail:
 EXPORT_SYMBOL(usb_gadget_register_driver);
 
 static void
-stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver)
+stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
 {
         int i;
 
@@ -1310,7 +1315,7 @@ stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver)
 
         /* prevent new request submissions, kill any outstanding requests  */
         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
-                struct pxa2xx_ep *ep = &dev->ep[i];
+                struct pxa25x_ep *ep = &dev->ep[i];
 
                 ep->stopped = 1;
                 nuke(ep, -ESHUTDOWN);
@@ -1327,7 +1332,7 @@ stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver)
 
 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
 {
-        struct pxa2xx_udc       *dev = the_controller;
+        struct pxa25x_udc       *dev = the_controller;
 
         if (!dev)
                 return -ENODEV;
@@ -1364,7 +1369,7 @@ EXPORT_SYMBOL(usb_gadget_unregister_driver);
 static irqreturn_t
 lubbock_vbus_irq(int irq, void *_dev)
 {
-        struct pxa2xx_udc       *dev = _dev;
+        struct pxa25x_udc       *dev = _dev;
         int                     vbus;
 
         dev->stats.irqs++;
@@ -1383,7 +1388,7 @@ lubbock_vbus_irq(int irq, void *_dev)
                 return IRQ_NONE;
         }
 
-        pxa2xx_udc_vbus_session(&dev->gadget, vbus);
+        pxa25x_udc_vbus_session(&dev->gadget, vbus);
         return IRQ_HANDLED;
 }
 
@@ -1391,20 +1396,20 @@ lubbock_vbus_irq(int irq, void *_dev)
 
 static irqreturn_t udc_vbus_irq(int irq, void *_dev)
 {
-        struct pxa2xx_udc       *dev = _dev;
+        struct pxa25x_udc       *dev = _dev;
         int                     vbus = gpio_get_value(dev->mach->gpio_vbus);
 
         if (dev->mach->gpio_vbus_inverted)
                 vbus = !vbus;
 
-        pxa2xx_udc_vbus_session(&dev->gadget, vbus);
+        pxa25x_udc_vbus_session(&dev->gadget, vbus);
         return IRQ_HANDLED;
 }
 
 
 /*-------------------------------------------------------------------------*/
 
-static inline void clear_ep_state (struct pxa2xx_udc *dev)
+static inline void clear_ep_state (struct pxa25x_udc *dev)
 {
         unsigned i;
 
@@ -1417,7 +1422,7 @@ static inline void clear_ep_state (struct pxa2xx_udc *dev)
 
 static void udc_watchdog(unsigned long _dev)
 {
-        struct pxa2xx_udc       *dev = (void *)_dev;
+        struct pxa25x_udc       *dev = (void *)_dev;
 
         local_irq_disable();
         if (dev->ep0state == EP0_STALL
@@ -1430,11 +1435,11 @@ static void udc_watchdog(unsigned long _dev)
         local_irq_enable();
 }
 
-static void handle_ep0 (struct pxa2xx_udc *dev)
+static void handle_ep0 (struct pxa25x_udc *dev)
 {
         u32                     udccs0 = UDCCS0;
-        struct pxa2xx_ep        *ep = &dev->ep [0];
-        struct pxa2xx_request   *req;
+        struct pxa25x_ep        *ep = &dev->ep [0];
+        struct pxa25x_request   *req;
         union {
                 struct usb_ctrlrequest  r;
                 u8                      raw [8];
@@ -1444,7 +1449,7 @@ static void handle_ep0 (struct pxa2xx_udc *dev)
         if (list_empty(&ep->queue))
                 req = NULL;
         else
-                req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
+                req = list_entry(ep->queue.next, struct pxa25x_request, queue);
 
         /* clear stall status */
         if (udccs0 & UDCCS0_SST) {
@@ -1654,9 +1659,9 @@ stall:
         USIR0 = USIR0_IR0;
 }
 
-static void handle_ep(struct pxa2xx_ep *ep)
+static void handle_ep(struct pxa25x_ep *ep)
 {
-        struct pxa2xx_request   *req;
+        struct pxa25x_request   *req;
         int                     is_in = ep->bEndpointAddress & USB_DIR_IN;
         int                     completed;
         u32                     udccs, tmp;
@@ -1665,7 +1670,7 @@ static void handle_ep(struct pxa2xx_ep *ep)
                 completed = 0;
                 if (likely (!list_empty(&ep->queue)))
                         req = list_entry(ep->queue.next,
-                                        struct pxa2xx_request, queue);
+                                        struct pxa25x_request, queue);
                 else
                         req = NULL;
 
@@ -1702,16 +1707,16 @@ static void handle_ep(struct pxa2xx_ep *ep)
 }
 
 /*
- *      pxa2xx_udc_irq - interrupt handler
+ *      pxa25x_udc_irq - interrupt handler
  *
  * avoid delays in ep0 processing. the control handshaking isn't always
  * under software control (pxa250c0 and the pxa255 are better), and delays
  * could cause usb protocol errors.
  */
 static irqreturn_t
-pxa2xx_udc_irq(int irq, void *_dev)
+pxa25x_udc_irq(int irq, void *_dev)
 {
-        struct pxa2xx_udc       *dev = _dev;
+        struct pxa25x_udc       *dev = _dev;
         int                     handled;
 
         dev->stats.irqs++;
@@ -1820,9 +1825,9 @@ static void nop_release (struct device *dev)
  * doing it at run-time) to save code, eliminate fault paths, and
  * be more obviously correct.
  */
-static struct pxa2xx_udc memory = {
+static struct pxa25x_udc memory = {
         .gadget = {
-                .ops            = &pxa2xx_udc_ops,
+                .ops            = &pxa25x_udc_ops,
                 .ep0            = &memory.ep[0].ep,
                 .name           = driver_name,
                 .dev = {
@@ -1835,7 +1840,7 @@ static struct pxa2xx_udc memory = {
         .ep[0] = {
                 .ep = {
                         .name           = ep0name,
-                        .ops            = &pxa2xx_ep_ops,
+                        .ops            = &pxa25x_ep_ops,
                         .maxpacket      = EP0_FIFO_SIZE,
                 },
                 .dev            = &memory,
@@ -1847,7 +1852,7 @@ static struct pxa2xx_udc memory = {
         .ep[1] = {
                 .ep = {
                         .name           = "ep1in-bulk",
-                        .ops            = &pxa2xx_ep_ops,
+                        .ops            = &pxa25x_ep_ops,
                         .maxpacket      = BULK_FIFO_SIZE,
                 },
                 .dev            = &memory,
@@ -1860,7 +1865,7 @@ static struct pxa2xx_udc memory = {
         .ep[2] = {
                 .ep = {
                         .name           = "ep2out-bulk",
-                        .ops            = &pxa2xx_ep_ops,
+                        .ops            = &pxa25x_ep_ops,
                         .maxpacket      = BULK_FIFO_SIZE,
                 },
                 .dev            = &memory,
@@ -1871,11 +1876,11 @@ static struct pxa2xx_udc memory = {
                 .reg_ubcr       = &UBCR2,
                 .reg_uddr       = &UDDR2,
         },
-#ifndef CONFIG_USB_PXA2XX_SMALL
+#ifndef CONFIG_USB_PXA25X_SMALL
         .ep[3] = {
                 .ep = {
                         .name           = "ep3in-iso",
-                        .ops            = &pxa2xx_ep_ops,
+                        .ops            = &pxa25x_ep_ops,
                         .maxpacket      = ISO_FIFO_SIZE,
                 },
                 .dev            = &memory,
@@ -1888,7 +1893,7 @@ static struct pxa2xx_udc memory = {
         .ep[4] = {
                 .ep = {
                         .name           = "ep4out-iso",
-                        .ops            = &pxa2xx_ep_ops,
+                        .ops            = &pxa25x_ep_ops,
                         .maxpacket      = ISO_FIFO_SIZE,
                 },
                 .dev            = &memory,
@@ -1902,7 +1907,7 @@ static struct pxa2xx_udc memory = {
         .ep[5] = {
                 .ep = {
                         .name           = "ep5in-int",
-                        .ops            = &pxa2xx_ep_ops,
+                        .ops            = &pxa25x_ep_ops,
                         .maxpacket      = INT_FIFO_SIZE,
                 },
                 .dev            = &memory,
@@ -1917,7 +1922,7 @@ static struct pxa2xx_udc memory = {
         .ep[6] = {
                 .ep = {
                         .name           = "ep6in-bulk",
-                        .ops            = &pxa2xx_ep_ops,
+                        .ops            = &pxa25x_ep_ops,
                         .maxpacket      = BULK_FIFO_SIZE,
                 },
                 .dev            = &memory,
@@ -1930,7 +1935,7 @@ static struct pxa2xx_udc memory = {
         .ep[7] = {
                 .ep = {
                         .name           = "ep7out-bulk",
-                        .ops            = &pxa2xx_ep_ops,
+                        .ops            = &pxa25x_ep_ops,
                         .maxpacket      = BULK_FIFO_SIZE,
                 },
                 .dev            = &memory,
@@ -1944,7 +1949,7 @@ static struct pxa2xx_udc memory = {
         .ep[8] = {
                 .ep = {
                         .name           = "ep8in-iso",
-                        .ops            = &pxa2xx_ep_ops,
+                        .ops            = &pxa25x_ep_ops,
                         .maxpacket      = ISO_FIFO_SIZE,
                 },
                 .dev            = &memory,
@@ -1957,7 +1962,7 @@ static struct pxa2xx_udc memory = {
         .ep[9] = {
                 .ep = {
                         .name           = "ep9out-iso",
-                        .ops            = &pxa2xx_ep_ops,
+                        .ops            = &pxa25x_ep_ops,
                         .maxpacket      = ISO_FIFO_SIZE,
                 },
                 .dev            = &memory,
@@ -1971,7 +1976,7 @@ static struct pxa2xx_udc memory = {
         .ep[10] = {
                 .ep = {
                         .name           = "ep10in-int",
-                        .ops            = &pxa2xx_ep_ops,
+                        .ops            = &pxa25x_ep_ops,
                         .maxpacket      = INT_FIFO_SIZE,
                 },
                 .dev            = &memory,
@@ -1986,7 +1991,7 @@ static struct pxa2xx_udc memory = {
         .ep[11] = {
                 .ep = {
                         .name           = "ep11in-bulk",
-                        .ops            = &pxa2xx_ep_ops,
+                        .ops            = &pxa25x_ep_ops,
                         .maxpacket      = BULK_FIFO_SIZE,
                 },
                 .dev            = &memory,
@@ -1999,7 +2004,7 @@ static struct pxa2xx_udc memory = {
         .ep[12] = {
                 .ep = {
                         .name           = "ep12out-bulk",
-                        .ops            = &pxa2xx_ep_ops,
+                        .ops            = &pxa25x_ep_ops,
                         .maxpacket      = BULK_FIFO_SIZE,
                 },
                 .dev            = &memory,
@@ -2013,7 +2018,7 @@ static struct pxa2xx_udc memory = {
         .ep[13] = {
                 .ep = {
                         .name           = "ep13in-iso",
-                        .ops            = &pxa2xx_ep_ops,
+                        .ops            = &pxa25x_ep_ops,
                         .maxpacket      = ISO_FIFO_SIZE,
                 },
                 .dev            = &memory,
@@ -2026,7 +2031,7 @@ static struct pxa2xx_udc memory = {
         .ep[14] = {
                 .ep = {
                         .name           = "ep14out-iso",
-                        .ops            = &pxa2xx_ep_ops,
+                        .ops            = &pxa25x_ep_ops,
                         .maxpacket      = ISO_FIFO_SIZE,
                 },
                 .dev            = &memory,
@@ -2040,7 +2045,7 @@ static struct pxa2xx_udc memory = {
         .ep[15] = {
                 .ep = {
                         .name           = "ep15in-int",
-                        .ops            = &pxa2xx_ep_ops,
+                        .ops            = &pxa25x_ep_ops,
                         .maxpacket      = INT_FIFO_SIZE,
                 },
                 .dev            = &memory,
@@ -2050,7 +2055,7 @@ static struct pxa2xx_udc memory = {
                 .reg_udccs      = &UDCCS15,
                 .reg_uddr       = &UDDR15,
         },
-#endif /* !CONFIG_USB_PXA2XX_SMALL */
+#endif /* !CONFIG_USB_PXA25X_SMALL */
 };
 
 #define CP15R0_VENDOR_MASK      0xffffe000
@@ -2090,9 +2095,9 @@ static struct pxa2xx_udc memory = {
 /*
  *      probe - binds to the platform device
  */
-static int __init pxa2xx_udc_probe(struct platform_device *pdev)
+static int __init pxa25x_udc_probe(struct platform_device *pdev)
 {
-        struct pxa2xx_udc *dev = &memory;
+        struct pxa25x_udc *dev = &memory;
         int retval, vbus_irq, irq;
         u32 chiprev;
 
@@ -2155,7 +2160,7 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev)
 
         if (dev->mach->gpio_vbus) {
                 if ((retval = gpio_request(dev->mach->gpio_vbus,
-                                "pxa2xx_udc GPIO VBUS"))) {
+                                "pxa25x_udc GPIO VBUS"))) {
                         dev_dbg(&pdev->dev,
                                 "can't get vbus gpio %d, err: %d\n",
                                 dev->mach->gpio_vbus, retval);
@@ -2168,7 +2173,7 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev)
 
         if (dev->mach->gpio_pullup) {
                 if ((retval = gpio_request(dev->mach->gpio_pullup,
-                                "pca2xx_udc GPIO PULLUP"))) {
+                                "pca25x_udc GPIO PULLUP"))) {
                         dev_dbg(&pdev->dev,
                                 "can't get pullup gpio %d, err: %d\n",
                                 dev->mach->gpio_pullup, retval);
@@ -2194,7 +2199,7 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev)
         dev->vbus = is_vbus_present();
 
         /* irq setup after old hardware state is cleaned up */
-        retval = request_irq(irq, pxa2xx_udc_irq,
+        retval = request_irq(irq, pxa25x_udc_irq,
                         IRQF_DISABLED, driver_name, dev);
         if (retval != 0) {
                 pr_err("%s: can't get irq %d, err %d\n",
@@ -2260,14 +2265,14 @@ lubbock_fail0:
         return retval;
 }
 
-static void pxa2xx_udc_shutdown(struct platform_device *_dev)
+static void pxa25x_udc_shutdown(struct platform_device *_dev)
 {
         pullup_off();
 }
 
-static int __exit pxa2xx_udc_remove(struct platform_device *pdev)
+static int __exit pxa25x_udc_remove(struct platform_device *pdev)
 {
-        struct pxa2xx_udc *dev = platform_get_drvdata(pdev);
+        struct pxa25x_udc *dev = platform_get_drvdata(pdev);
 
         if (dev->driver)
                 return -EBUSY;
@@ -2317,9 +2322,9 @@ static int __exit pxa2xx_udc_remove(struct platform_device *pdev)
  * VBUS IRQs should probably be ignored so that the PXA device just acts
  * "dead" to USB hosts until system resume.
  */
-static int pxa2xx_udc_suspend(struct platform_device *dev, pm_message_t state)
+static int pxa25x_udc_suspend(struct platform_device *dev, pm_message_t state)
 {
-        struct pxa2xx_udc       *udc = platform_get_drvdata(dev);
+        struct pxa25x_udc       *udc = platform_get_drvdata(dev);
         unsigned long flags;
 
         if (!udc->mach->gpio_pullup && !udc->mach->udc_command)
@@ -2333,9 +2338,9 @@ static int pxa2xx_udc_suspend(struct platform_device *dev, pm_message_t state)
         return 0;
 }
 
-static int pxa2xx_udc_resume(struct platform_device *dev)
+static int pxa25x_udc_resume(struct platform_device *dev)
 {
-        struct pxa2xx_udc       *udc = platform_get_drvdata(dev);
+        struct pxa25x_udc       *udc = platform_get_drvdata(dev);
         unsigned long flags;
 
         udc->suspended = 0;
@@ -2347,27 +2352,27 @@ static int pxa2xx_udc_resume(struct platform_device *dev)
 }
 
 #else
-#define pxa2xx_udc_suspend      NULL
-#define pxa2xx_udc_resume       NULL
+#define pxa25x_udc_suspend      NULL
+#define pxa25x_udc_resume       NULL
 #endif
 
 /*-------------------------------------------------------------------------*/
 
 static struct platform_driver udc_driver = {
-        .shutdown       = pxa2xx_udc_shutdown,
-        .remove         = __exit_p(pxa2xx_udc_remove),
-        .suspend        = pxa2xx_udc_suspend,
-        .resume         = pxa2xx_udc_resume,
+        .shutdown       = pxa25x_udc_shutdown,
+        .remove         = __exit_p(pxa25x_udc_remove),
+        .suspend        = pxa25x_udc_suspend,
+        .resume         = pxa25x_udc_resume,
         .driver         = {
                 .owner  = THIS_MODULE,
-                .name   = "pxa2xx-udc",
+                .name   = "pxa25x-udc",
         },
 };
 
 static int __init udc_init(void)
 {
         pr_info("%s: version %s\n", driver_name, DRIVER_VERSION);
-        return platform_driver_probe(&udc_driver, pxa2xx_udc_probe);
+        return platform_driver_probe(&udc_driver, pxa25x_udc_probe);
 }
 module_init(udc_init);
 
@@ -2380,4 +2385,4 @@ module_exit(udc_exit);
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
 MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:pxa2xx-udc");
+MODULE_ALIAS("platform:pxa25x-udc");
diff --git a/drivers/usb/gadget/pxa2xx_udc.h b/drivers/usb/gadget/pxa25x_udc.h
index e2c19e88c875..4d11ece7c95f 100644
--- a/drivers/usb/gadget/pxa2xx_udc.h
+++ b/drivers/usb/gadget/pxa25x_udc.h
@@ -1,6 +1,5 @@
 /*
- * linux/drivers/usb/gadget/pxa2xx_udc.h
- * Intel PXA2xx on-chip full speed USB device controller
+ * Intel PXA25x on-chip full speed USB device controller
  *
  * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
  * Copyright (C) 2003 David Brownell
@@ -21,14 +20,14 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#ifndef __LINUX_USB_GADGET_PXA2XX_H
-#define __LINUX_USB_GADGET_PXA2XX_H
+#ifndef __LINUX_USB_GADGET_PXA25X_H
+#define __LINUX_USB_GADGET_PXA25X_H
 
 #include <linux/types.h>
 
 /*-------------------------------------------------------------------------*/
 
-/* pxa2xx has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */
+/* pxa25x has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */
 #define UFNRH_SIR       (1 << 7)        /* SOF interrupt request */
 #define UFNRH_SIM       (1 << 6)        /* SOF interrupt mask */
 #define UFNRH_IPE14     (1 << 5)        /* ISO packet error, ep14 */
@@ -45,11 +44,11 @@
 
 /*-------------------------------------------------------------------------*/
 
-struct pxa2xx_udc;
+struct pxa25x_udc;
 
-struct pxa2xx_ep {
+struct pxa25x_ep {
         struct usb_ep                           ep;
-        struct pxa2xx_udc                       *dev;
+        struct pxa25x_udc                       *dev;
 
         const struct usb_endpoint_descriptor    *desc;
         struct list_head                        queue;
@@ -72,7 +71,7 @@ struct pxa2xx_ep {
         volatile u32                            *reg_uddr;
 };
 
-struct pxa2xx_request {
+struct pxa25x_request {
         struct usb_request                      req;
         struct list_head                        queue;
 };
@@ -98,7 +97,7 @@ struct udc_stats {
         unsigned long                   irqs;
 };
 
-#ifdef CONFIG_USB_PXA2XX_SMALL
+#ifdef CONFIG_USB_PXA25X_SMALL
 /* when memory's tight, SMALL config saves code+data.  */
 #define PXA_UDC_NUM_ENDPOINTS   3
 #endif
@@ -107,7 +106,7 @@ struct udc_stats {
 #define PXA_UDC_NUM_ENDPOINTS   16
 #endif
 
-struct pxa2xx_udc {
+struct pxa25x_udc {
         struct usb_gadget                       gadget;
         struct usb_gadget_driver                *driver;
 
@@ -130,7 +129,7 @@ struct pxa2xx_udc {
         struct clk                              *clk;
         struct pxa2xx_udc_mach_info             *mach;
         u64                                     dma_mask;
-        struct pxa2xx_ep                        ep [PXA_UDC_NUM_ENDPOINTS];
+        struct pxa25x_ep                        ep [PXA_UDC_NUM_ENDPOINTS];
 
 #ifdef CONFIG_USB_GADGET_DEBUG_FS
         struct dentry                           *debugfs_udc;
@@ -144,7 +143,7 @@ struct pxa2xx_udc {
 /* lubbock can also report usb connect/disconnect irqs */
 #endif
 
-static struct pxa2xx_udc *the_controller;
+static struct pxa25x_udc *the_controller;
 
 /*-------------------------------------------------------------------------*/
 
@@ -209,7 +208,7 @@ dump_udccs0(const char *label)
 }
 
 static void __maybe_unused
-dump_state(struct pxa2xx_udc *dev)
+dump_state(struct pxa25x_udc *dev)
 {
         u32             tmp;
         unsigned        i;
@@ -264,4 +263,4 @@ dump_state(struct pxa2xx_udc *dev)
 #define INFO(stuff...)          pr_info("udc: " stuff)
 
 
-#endif /* __LINUX_USB_GADGET_PXA2XX_H */
+#endif /* __LINUX_USB_GADGET_PXA25X_H */
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index e02bfd4df3a6..9c0e82ec5c43 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -38,7 +38,7 @@
 #include <linux/usb.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
-
+#include <asm/arch/pxa2xx-regs.h> /* FIXME: for PSSR */
 #include <asm/arch/udc.h>
 
 #include "pxa27x_udc.h"
@@ -2360,18 +2360,19 @@ static int pxa_udc_resume(struct platform_device *_dev)
          * Software must configure the USB OTG pad, UDC, and UHC
          * to the state they were in before entering sleep mode.
          */
-        PSSR |= PSSR_OTGPH;
+        if (cpu_is_pxa27x())
+                PSSR |= PSSR_OTGPH;
 
         return 0;
 }
 #endif
 
 /* work with hotplug and coldplug */
-MODULE_ALIAS("platform:pxa2xx-udc");
+MODULE_ALIAS("platform:pxa27x-udc");
 
 static struct platform_driver udc_driver = {
         .driver         = {
-                .name   = "pxa2xx-udc",
+                .name   = "pxa27x-udc",
                 .owner  = THIS_MODULE,
         },
         .remove         = __exit_p(pxa_udc_remove),
diff --git a/drivers/usb/gadget/pxa27x_udc.h b/drivers/usb/gadget/pxa27x_udc.h
index 97453db924ff..1d1b7936ee11 100644
--- a/drivers/usb/gadget/pxa27x_udc.h
+++ b/drivers/usb/gadget/pxa27x_udc.h
@@ -484,12 +484,4 @@ static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget)
 #define ep_warn(ep, fmt, arg...) \
         dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg)
 
-/*
- * Cannot include pxa-regs.h, as register names are similar.
- * So PSSR is redefined here. This should be removed once UDC registers will
- * be gone from pxa-regs.h.
- */
-#define PSSR            __REG(0x40F00004)       /* Power Manager Sleep Status */
-#define PSSR_OTGPH      (1 << 6)                /* OTG Peripheral Hold */
-
 #endif /* __LINUX_USB_GADGET_PXA27X_H */
diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c
index 3a7c24c03671..a19a4f80a6e1 100644
--- a/drivers/usb/host/ohci-omap.c
+++ b/drivers/usb/host/ohci-omap.c
@@ -169,13 +169,16 @@ static void start_hnp(struct ohci_hcd *ohci)
 {
         const unsigned  port = ohci_to_hcd(ohci)->self.otg_port - 1;
         unsigned long   flags;
+        u32 l;
 
         otg_start_hnp(ohci->transceiver);
 
         local_irq_save(flags);
         ohci->transceiver->state = OTG_STATE_A_SUSPEND;
         writel (RH_PS_PSS, &ohci->regs->roothub.portstatus [port]);
-        OTG_CTRL_REG &= ~OTG_A_BUSREQ;
+        l = omap_readl(OTG_CTRL);
+        l &= ~OTG_A_BUSREQ;
+        omap_writel(l, OTG_CTRL);
         local_irq_restore(flags);
 }
 
diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c
index d4ee27d92be8..127b15799024 100644
--- a/drivers/usb/host/ohci-pxa27x.c
+++ b/drivers/usb/host/ohci-pxa27x.c
@@ -27,6 +27,7 @@
 #include <asm/mach-types.h>
 #include <asm/hardware.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h> /* FIXME: for PSSR */
 #include <asm/arch/ohci.h>
 
 #define PXA_UHC_MAX_PORTNUM    3
@@ -104,7 +105,7 @@ static int pxa27x_start_hc(struct device *dev)
         UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
 
         /* Clear any OTG Pin Hold */
-        if (PSSR & PSSR_OTGPH)
+        if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
                 PSSR |= PSSR_OTGPH;
 
         return 0;
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
index dcd8073c2369..30bf7f2f1635 100644
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -112,3 +112,10 @@ config BACKLIGHT_CARILLO_RANCH
         help
           If you have a Intel LE80578 (Carillo Ranch) say Y to enable the
           backlight driver.
+
+config BACKLIGHT_PWM
+        tristate "Generic PWM based Backlight Driver"
+        depends on BACKLIGHT_CLASS_DEVICE && HAVE_PWM
+        help
+          If you have a LCD backlight adjustable by PWM, say Y to enable
+          this driver.
diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
index 33f6c7cecc73..b51a7cd12500 100644
--- a/drivers/video/backlight/Makefile
+++ b/drivers/video/backlight/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_BACKLIGHT_LOCOMO)	+= locomolcd.o
 obj-$(CONFIG_BACKLIGHT_OMAP1)   += omap1_bl.o
 obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o
 obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o
+obj-$(CONFIG_BACKLIGHT_PWM)     += pwm_bl.o
diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
new file mode 100644
index 000000000000..6338d0e2fe07
--- /dev/null
+++ b/drivers/video/backlight/pwm_bl.c
@@ -0,0 +1,185 @@
+/*
+ * linux/drivers/video/backlight/pwm_bl.c
+ *
+ * simple PWM based backlight control, board code has to setup
+ * 1) pin configuration so PWM waveforms can output
+ * 2) platform_data casts to the PWM id (0/1/2/3 on PXA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/fb.h>
+#include <linux/backlight.h>
+#include <linux/err.h>
+#include <linux/pwm.h>
+#include <linux/pwm_backlight.h>
+
+struct pwm_bl_data {
+        struct pwm_device       *pwm;
+        unsigned int            period;
+        int                     (*notify)(int brightness);
+};
+
+static int pwm_backlight_update_status(struct backlight_device *bl)
+{
+        struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
+        int brightness = bl->props.brightness;
+        int max = bl->props.max_brightness;
+
+        if (bl->props.power != FB_BLANK_UNBLANK)
+                brightness = 0;
+
+        if (bl->props.fb_blank != FB_BLANK_UNBLANK)
+                brightness = 0;
+
+        if (pb->notify)
+                brightness = pb->notify(brightness);
+
+        if (brightness == 0) {
+                pwm_config(pb->pwm, 0, pb->period);
+                pwm_disable(pb->pwm);
+        } else {
+                pwm_config(pb->pwm, brightness * pb->period / max, pb->period);
+                pwm_enable(pb->pwm);
+        }
+        return 0;
+}
+
+static int pwm_backlight_get_brightness(struct backlight_device *bl)
+{
+        return bl->props.brightness;
+}
+
+static struct backlight_ops pwm_backlight_ops = {
+        .update_status  = pwm_backlight_update_status,
+        .get_brightness = pwm_backlight_get_brightness,
+};
+
+static int pwm_backlight_probe(struct platform_device *pdev)
+{
+        struct platform_pwm_backlight_data *data = pdev->dev.platform_data;
+        struct backlight_device *bl;
+        struct pwm_bl_data *pb;
+        int ret;
+
+        if (!data)
+                return -EINVAL;
+
+        if (data->init) {
+                ret = data->init(&pdev->dev);
+                if (ret < 0)
+                        return ret;
+        }
+
+        pb = kzalloc(sizeof(*pb), GFP_KERNEL);
+        if (!pb) {
+                ret = -ENOMEM;
+                goto err_alloc;
+        }
+
+        pb->period = data->pwm_period_ns;
+        pb->notify = data->notify;
+
+        pb->pwm = pwm_request(data->pwm_id, "backlight");
+        if (IS_ERR(pb->pwm)) {
+                dev_err(&pdev->dev, "unable to request PWM for backlight\n");
+                ret = PTR_ERR(pb->pwm);
+                goto err_pwm;
+        }
+
+        bl = backlight_device_register(pdev->name, &pdev->dev,
+                        pb, &pwm_backlight_ops);
+        if (IS_ERR(bl)) {
+                dev_err(&pdev->dev, "failed to register backlight\n");
+                ret = PTR_ERR(bl);
+                goto err_bl;
+        }
+
+        bl->props.max_brightness = data->max_brightness;
+        bl->props.brightness = data->dft_brightness;
+        backlight_update_status(bl);
+
+        platform_set_drvdata(pdev, bl);
+        return 0;
+
+err_bl:
+        pwm_free(pb->pwm);
+err_pwm:
+        kfree(pb);
+err_alloc:
+        if (data->exit)
+                data->exit(&pdev->dev);
+        return ret;
+}
+
+static int pwm_backlight_remove(struct platform_device *pdev)
+{
+        struct platform_pwm_backlight_data *data = pdev->dev.platform_data;
+        struct backlight_device *bl = platform_get_drvdata(pdev);
+        struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
+
+        backlight_device_unregister(bl);
+        pwm_config(pb->pwm, 0, pb->period);
+        pwm_disable(pb->pwm);
+        pwm_free(pb->pwm);
+        kfree(pb);
+        if (data->exit)
+                data->exit(&pdev->dev);
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int pwm_backlight_suspend(struct platform_device *pdev,
+                                 pm_message_t state)
+{
+        struct backlight_device *bl = platform_get_drvdata(pdev);
+        struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
+
+        pwm_config(pb->pwm, 0, pb->period);
+        pwm_disable(pb->pwm);
+        return 0;
+}
+
+static int pwm_backlight_resume(struct platform_device *pdev)
+{
+        struct backlight_device *bl = platform_get_drvdata(pdev);
+
+        backlight_update_status(bl);
+        return 0;
+}
+#else
+#define pwm_backlight_suspend   NULL
+#define pwm_backlight_resume    NULL
+#endif
+
+static struct platform_driver pwm_backlight_driver = {
+        .driver         = {
+                .name   = "pwm-backlight",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = pwm_backlight_probe,
+        .remove         = pwm_backlight_remove,
+        .suspend        = pwm_backlight_suspend,
+        .resume         = pwm_backlight_resume,
+};
+
+static int __init pwm_backlight_init(void)
+{
+        return platform_driver_register(&pwm_backlight_driver);
+}
+module_init(pwm_backlight_init);
+
+static void __exit pwm_backlight_exit(void)
+{
+        platform_driver_unregister(&pwm_backlight_driver);
+}
+module_exit(pwm_backlight_exit);
+
+MODULE_DESCRIPTION("PWM based Backlight Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index fafe7db20d6d..d0746261c957 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -1792,11 +1792,49 @@ failed:
         return ret;
 }
 
+static int __devexit pxafb_remove(struct platform_device *dev)
+{
+        struct pxafb_info *fbi = platform_get_drvdata(dev);
+        struct resource *r;
+        int irq;
+        struct fb_info *info;
+
+        if (!fbi)
+                return 0;
+
+        info = &fbi->fb;
+
+        unregister_framebuffer(info);
+
+        pxafb_disable_controller(fbi);
+
+        if (fbi->fb.cmap.len)
+                fb_dealloc_cmap(&fbi->fb.cmap);
+
+        irq = platform_get_irq(dev, 0);
+        free_irq(irq, fbi);
+
+        dma_free_writecombine(&dev->dev, fbi->map_size,
+                                        fbi->map_cpu, fbi->map_dma);
+
+        iounmap(fbi->mmio_base);
+
+        r = platform_get_resource(dev, IORESOURCE_MEM, 0);
+        release_mem_region(r->start, r->end - r->start + 1);
+
+        clk_put(fbi->clk);
+        kfree(fbi);
+
+        return 0;
+}
+
 static struct platform_driver pxafb_driver = {
         .probe          = pxafb_probe,
+        .remove         = pxafb_remove,
         .suspend        = pxafb_suspend,
         .resume         = pxafb_resume,
         .driver         = {
+                .owner  = THIS_MODULE,
                 .name   = "pxa2xx-fb",
         },
 };
@@ -1809,7 +1847,13 @@ static int __init pxafb_init(void)
         return platform_driver_register(&pxafb_driver);
 }
 
+static void __exit pxafb_exit(void)
+{
+        platform_driver_unregister(&pxafb_driver);
+}
+
 module_init(pxafb_init);
+module_exit(pxafb_exit);
 
 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
 MODULE_LICENSE("GPL");
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index c2b13c280155..2001e81f2267 100644
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -39,10 +39,14 @@
 #define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
 
 #define AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [SAM9RL, CAP9] */
+#define         AT91_PMC_UPLLEN         (1   << 16)             /* UTMI PLL Enable */
+#define         AT91_PMC_UPLLCOUNT      (0xf << 20)             /* UTMI PLL Start-up Time */
+#define         AT91_PMC_BIASEN         (1   << 24)             /* UTMI BIAS Enable */
+#define         AT91_PMC_BIASCOUNT      (0xf << 28)             /* UTMI PLL Start-up Time */
 
 #define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register [not on SAM9RL] */
 #define         AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
-#define         AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [AT91SAM926x only] */
+#define         AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [SAM9x, CAP9] */
 #define         AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
 
 #define AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
@@ -97,6 +101,7 @@
 #define         AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
 #define         AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
 #define         AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
+#define         AT91_PMC_LOCKU          (1 <<  6)               /* UPLL Lock [AT91CAP9 only] */
 #define         AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
 #define         AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
 #define         AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h
index bac83adb5050..6f14d9053ac7 100644
--- a/include/asm-arm/arch-at91/at91cap9.h
+++ b/include/asm-arm/arch-at91/at91cap9.h
@@ -118,7 +118,7 @@
 #define AT91CAP9_ROM_SIZE       (32 * SZ_1K)    /* Internal ROM size (32Kb) */
 
 #define AT91CAP9_LCDC_BASE      0x00500000      /* LCD Controller */
-#define AT91CAP9_UDPHS_BASE     0x00600000      /* USB High Speed Device Port */
+#define AT91CAP9_UDPHS_FIFO     0x00600000      /* USB High Speed Device Port */
 #define AT91CAP9_UHP_BASE       0x00700000      /* USB Host controller */
 
 #define CONFIG_DRAM_BASE        AT91_CHIPSELECT_6
diff --git a/include/asm-arm/arch-at91/at91cap9_matrix.h b/include/asm-arm/arch-at91/at91cap9_matrix.h
index a641686b6c3d..ddbd4873c842 100644
--- a/include/asm-arm/arch-at91/at91cap9_matrix.h
+++ b/include/asm-arm/arch-at91/at91cap9_matrix.h
@@ -106,6 +106,11 @@
 #define AT91_MPBS0_SFR          (AT91_MATRIX + 0x114)   /* MPBlock Slave 0 Special Function Register */
 #define AT91_MPBS1_SFR          (AT91_MATRIX + 0x11C)   /* MPBlock Slave 1 Special Function Register */
 
+#define AT91_MATRIX_UDPHS       (AT91_MATRIX + 0x118)   /* USBHS Special Function Register [AT91CAP9 only] */
+#define         AT91_MATRIX_SELECT_UDPHS        (0 << 31)       /* select High Speed UDP */
+#define         AT91_MATRIX_SELECT_UDP          (1 << 31)       /* select standard UDP */
+#define         AT91_MATRIX_UDPHS_BYPASS_LOCK   (1 << 30)       /* bypass lock bit */
+
 #define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI Chip Select Assignment Register */
 #define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h
index c8934fe34dc5..889872a3f2a9 100644
--- a/include/asm-arm/arch-at91/at91sam9260.h
+++ b/include/asm-arm/arch-at91/at91sam9260.h
@@ -6,6 +6,8 @@
  * Common definitions.
  * Based on AT91SAM9260 datasheet revision A (Preliminary).
  *
+ * Includes also definitions for AT91SAM9XE and AT91SAM9G families
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -123,5 +125,14 @@
 #define AT91SAM9XE_FLASH_BASE   0x00200000      /* Internal FLASH base address */
 #define AT91SAM9XE_SRAM_BASE    0x00300000      /* Internal SRAM base address */
 
+#define AT91SAM9G20_ROM_BASE    0x00100000      /* Internal ROM base address */
+#define AT91SAM9G20_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
+
+#define AT91SAM9G20_SRAM0_BASE  0x00200000      /* Internal SRAM 0 base address */
+#define AT91SAM9G20_SRAM0_SIZE  SZ_16K          /* Internal SRAM 0 size (16Kb) */
+#define AT91SAM9G20_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
+#define AT91SAM9G20_SRAM1_SIZE  SZ_16K          /* Internal SRAM 1 size (16Kb) */
+
+#define AT91SAM9G20_UHP_BASE    0x00500000      /* USB Host controller */
 
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h
index 16d2832f6c0a..622e56f81d42 100644
--- a/include/asm-arm/arch-at91/at91sam9rl.h
+++ b/include/asm-arm/arch-at91/at91sam9rl.h
@@ -110,6 +110,6 @@
 #define AT91SAM9RL_ROM_SIZE     (2 * SZ_16K)    /* Internal ROM size (32Kb) */
 
 #define AT91SAM9RL_LCDC_BASE    0x00500000      /* LCD Controller */
-#define AT91SAM9RL_UDPHS_BASE   0x00600000      /* USB Device HS controller */
+#define AT91SAM9RL_UDPHS_FIFO   0x00600000      /* USB Device HS controller */
 
 #endif
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index dc189f01c5b3..94de788da76e 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -36,6 +36,7 @@
 #include <linux/i2c.h>
 #include <linux/leds.h>
 #include <linux/spi/spi.h>
+#include <linux/usb/atmel_usba_udc.h>
 
  /* USB Device */
 struct at91_udc_data {
@@ -45,6 +46,9 @@ struct at91_udc_data {
 };
 extern void __init at91_add_device_udc(struct at91_udc_data *data);
 
+ /* USB High Speed Device */
+extern void __init at91_add_device_usba(struct usba_platform_data *data);
+
  /* Compact Flash */
 struct at91_cf_data {
         u8      irq_pin;                /* I/O IRQ */
@@ -73,7 +77,7 @@ struct at91_eth_data {
 };
 extern void __init at91_add_device_eth(struct at91_eth_data *data);
 
-#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9)
+#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9)
 #define eth_platform_data       at91_eth_data
 #endif
 
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index 7145166826a2..52df794205cb 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -21,6 +21,7 @@
 #define ARCH_ID_AT91SAM9260     0x019803a0
 #define ARCH_ID_AT91SAM9261     0x019703a0
 #define ARCH_ID_AT91SAM9263     0x019607a0
+#define ARCH_ID_AT91SAM9G20     0x019905a0
 #define ARCH_ID_AT91SAM9RL64    0x019b03a0
 #define ARCH_ID_AT91CAP9        0x039A03A0
 
@@ -63,6 +64,12 @@ static inline unsigned long at91_arch_identify(void)
 #define cpu_is_at91sam9260()    (0)
 #endif
 
+#ifdef CONFIG_ARCH_AT91SAM9G20
+#define cpu_is_at91sam9g20()    (at91_cpu_identify() == ARCH_ID_AT91SAM9G20)
+#else
+#define cpu_is_at91sam9g20()    (0)
+#endif
+
 #ifdef CONFIG_ARCH_AT91SAM9261
 #define cpu_is_at91sam9261()    (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
 #else
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 2c826d8247a3..016a3a3f6633 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -18,7 +18,7 @@
 
 #if defined(CONFIG_ARCH_AT91RM9200)
 #include <asm/arch/at91rm9200.h>
-#elif defined(CONFIG_ARCH_AT91SAM9260)
+#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
 #include <asm/arch/at91sam9260.h>
 #elif defined(CONFIG_ARCH_AT91SAM9261)
 #include <asm/arch/at91sam9261.h>
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
index f1933b0fa43f..298d8313cdac 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -27,14 +27,29 @@
 
 #define CLOCK_TICK_RATE         (AT91_SLOW_CLOCK)
 
-#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261)
+#elif defined(CONFIG_ARCH_AT91SAM9260)
+
+#if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260)
+#define AT91SAM9_MASTER_CLOCK   90000000
+#else
+#define AT91SAM9_MASTER_CLOCK   99300000
+#endif
+
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+
+#elif defined(CONFIG_ARCH_AT91SAM9261)
 
 #define AT91SAM9_MASTER_CLOCK   99300000
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
 
 #elif defined(CONFIG_ARCH_AT91SAM9263)
 
+#if defined(CONFIG_MACH_USB_A9263)
+#define AT91SAM9_MASTER_CLOCK   90000000
+#else
 #define AT91SAM9_MASTER_CLOCK   99959500
+#endif
+
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
 
 #elif defined(CONFIG_ARCH_AT91SAM9RL)
@@ -42,6 +57,11 @@
 #define AT91SAM9_MASTER_CLOCK   100000000
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
 
+#elif defined(CONFIG_ARCH_AT91SAM9G20)
+
+#define AT91SAM9_MASTER_CLOCK   132096000
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+
 #elif defined(CONFIG_ARCH_AT91CAP9)
 
 #define AT91CAP9_MASTER_CLOCK   100000000
diff --git a/include/asm-arm/arch-ebsa285/hardware.h b/include/asm-arm/arch-ebsa285/hardware.h
index daad8ee2d194..74610c2c63d4 100644
--- a/include/asm-arm/arch-ebsa285/hardware.h
+++ b/include/asm-arm/arch-ebsa285/hardware.h
@@ -14,7 +14,6 @@
 
 #include <asm/arch/memory.h>
 
-#ifdef CONFIG_ARCH_FOOTBRIDGE
 /*   Virtual      Physical      Size
  * 0xff800000   0x40000000      1MB     X-Bus
  * 0xff000000   0x7c000000      1MB     PCI I/O space
@@ -50,31 +49,6 @@
 #define PCIMEM_SIZE             0x01000000
 #define PCIMEM_BASE             0xf0000000
 
-#elif defined(CONFIG_ARCH_CO285)
-/*
- * This is the COEBSA285 cut-down mapping
- */
-#define PCIMEM_SIZE             0x80000000
-#define PCIMEM_BASE             0x80000000
-
-#define WFLUSH_SIZE             0x01000000
-#define WFLUSH_BASE             0x7d000000
-
-#define ARMCSR_SIZE             0x00100000
-#define ARMCSR_BASE             0x7cf00000
-
-#define XBUS_SIZE               0x00020000
-#define XBUS_BASE               0x7cee0000
-
-#define PCIO_SIZE               0x00010000
-#define PCIO_BASE               0x7ced0000
-
-#else
-
-#error "Undefined footbridge architecture"
-
-#endif
-
 #define XBUS_LEDS               ((volatile unsigned char *)(XBUS_BASE + 0x12000))
 #define XBUS_LED_AMBER          (1 << 0)
 #define XBUS_LED_GREEN          (1 << 1)
diff --git a/include/asm-arm/arch-ebsa285/memory.h b/include/asm-arm/arch-ebsa285/memory.h
index cbd7ae64bcc9..9019a3bf5ab9 100644
--- a/include/asm-arm/arch-ebsa285/memory.h
+++ b/include/asm-arm/arch-ebsa285/memory.h
@@ -42,8 +42,6 @@ extern unsigned long __bus_to_virt(unsigned long);
 
 #endif
 
-#if defined(CONFIG_ARCH_FOOTBRIDGE)
-
 /* Task size and page offset at 3GB */
 #define TASK_SIZE               UL(0xbf000000)
 #define PAGE_OFFSET             UL(0xc0000000)
@@ -53,23 +51,6 @@ extern unsigned long __bus_to_virt(unsigned long);
  */
 #define FLUSH_BASE              0xf9000000
 
-#elif defined(CONFIG_ARCH_CO285)
-
-/* Task size and page offset at 1.5GB */
-#define TASK_SIZE               UL(0x5f000000)
-#define PAGE_OFFSET             UL(0x60000000)
-
-/*
- * Cache flushing area.
- */
-#define FLUSH_BASE              0x7e000000
-
-#else
-
-#error "Undefined footbridge architecture"
-
-#endif
-
 /*
  * Physical DRAM offset.
  */
diff --git a/include/asm-arm/arch-ebsa285/vmalloc.h b/include/asm-arm/arch-ebsa285/vmalloc.h
index 02598200997d..e487d7e8c8a6 100644
--- a/include/asm-arm/arch-ebsa285/vmalloc.h
+++ b/include/asm-arm/arch-ebsa285/vmalloc.h
@@ -7,8 +7,4 @@
  */
 
 
-#ifdef CONFIG_ARCH_FOOTBRIDGE
 #define VMALLOC_END       (PAGE_OFFSET + 0x30000000)
-#else
-#define VMALLOC_END       (PAGE_OFFSET + 0x20000000)
-#endif
diff --git a/include/asm-arm/arch-imx/hardware.h b/include/asm-arm/arch-imx/hardware.h
index adffb6acf42a..6542ca5e8c33 100644
--- a/include/asm-arm/arch-imx/hardware.h
+++ b/include/asm-arm/arch-imx/hardware.h
@@ -73,14 +73,6 @@
  */
 extern void imx_gpio_mode( int gpio_mode );
 
-/* get frequencies in Hz */
-extern unsigned int imx_get_system_clk(void);
-extern unsigned int imx_get_mcu_clk(void);
-extern unsigned int imx_get_perclk1(void); /* UART[12], Timer[12], PWM */
-extern unsigned int imx_get_perclk2(void); /* LCD, SD, SPI[12]         */
-extern unsigned int imx_get_perclk3(void); /* SSI                      */
-extern unsigned int imx_get_hclk(void);    /* SDRAM, CSI, Memory Stick,*/
-                                           /* I2C, DMA                 */
 #endif
 
 #define MAXIRQNUM                       62
diff --git a/include/asm-arm/arch-imx/imx-dma.h b/include/asm-arm/arch-imx/imx-dma.h
index 5b1066da4e1f..44d89c35539a 100644
--- a/include/asm-arm/arch-imx/imx-dma.h
+++ b/include/asm-arm/arch-imx/imx-dma.h
@@ -88,7 +88,7 @@ int imx_dma_request(imx_dmach_t dma_ch, const char *name);
 
 void imx_dma_free(imx_dmach_t dma_ch);
 
-int imx_dma_request_by_prio(imx_dmach_t *pdma_ch, const char *name, imx_dma_prio prio);
+imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio);
 
 
 #endif  /* _ASM_ARCH_IMX_DMA_H */
diff --git a/include/asm-arm/arch-imx/imx-uart.h b/include/asm-arm/arch-imx/imx-uart.h
index 3a685e1780ea..d54eb1d48026 100644
--- a/include/asm-arm/arch-imx/imx-uart.h
+++ b/include/asm-arm/arch-imx/imx-uart.h
@@ -4,6 +4,8 @@
 #define IMXUART_HAVE_RTSCTS (1<<0)
 
 struct imxuart_platform_data {
+        int (*init)(struct platform_device *pdev);
+        void (*exit)(struct platform_device *pdev);
         unsigned int flags;
 };
 
diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h
index 2e15da53ff79..d79846fbb394 100644
--- a/include/asm-arm/arch-iop13xx/dma.h
+++ b/include/asm-arm/arch-iop13xx/dma.h
@@ -1,3 +1,3 @@
 #ifndef _IOP13XX_DMA_H
-#define _IOP13XX_DMA_H_
+#define _IOP13XX_DMA_H
 #endif
diff --git a/include/asm-arm/arch-iop32x/gpio.h b/include/asm-arm/arch-iop32x/gpio.h
new file mode 100644
index 000000000000..708f4ec9db1d
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/gpio.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_IOP32X_GPIO_H
+#define __ASM_ARCH_IOP32X_GPIO_H
+
+#include <asm/hardware/iop3xx-gpio.h>
+
+#endif
diff --git a/include/asm-arm/arch-iop33x/gpio.h b/include/asm-arm/arch-iop33x/gpio.h
new file mode 100644
index 000000000000..ddd55bba9bb9
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/gpio.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_IOP33X_GPIO_H
+#define __ASM_ARCH_IOP33X_GPIO_H
+
+#include <asm/hardware/iop3xx-gpio.h>
+
+#endif
diff --git a/include/asm-arm/arch-ixp4xx/fsg.h b/include/asm-arm/arch-ixp4xx/fsg.h
new file mode 100644
index 000000000000..c0100cc7981c
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/fsg.h
@@ -0,0 +1,50 @@
+/*
+ * include/asm-arm/arch-ixp4xx/fsg.h
+ *
+ * Freecom FSG-3 platform specific definitions
+ *
+ * Author: Rod Whitby <rod@whitby.id.au>
+ * Author: Tomasz Chmielewski <mangoo@wpkg.org>
+ * Maintainers: http://www.nslu2-linux.org
+ *
+ * Based on coyote.h by
+ * Copyright 2004 (c) MontaVista, Software, Inc.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <asm/hardware.h>"
+#endif
+
+#define FSG_SDA_PIN             12
+#define FSG_SCL_PIN             13
+
+/*
+ * FSG PCI IRQs
+ */
+#define FSG_PCI_MAX_DEV         3
+#define FSG_PCI_IRQ_LINES       3
+
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define FSG_PCI_INTA_PIN        6
+#define FSG_PCI_INTB_PIN        7
+#define FSG_PCI_INTC_PIN        5
+
+/* Buttons */
+
+#define FSG_SB_GPIO             4       /* sync button */
+#define FSG_RB_GPIO             9       /* reset button */
+#define FSG_UB_GPIO             10      /* usb button */
+
+/* LEDs */
+
+#define FSG_LED_WLAN_BIT        0
+#define FSG_LED_WAN_BIT         1
+#define FSG_LED_SATA_BIT        2
+#define FSG_LED_USB_BIT         4
+#define FSG_LED_RING_BIT        5
+#define FSG_LED_SYNC_BIT        7
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
index 73e8dc36f6a4..fa723a627854 100644
--- a/include/asm-arm/arch-ixp4xx/hardware.h
+++ b/include/asm-arm/arch-ixp4xx/hardware.h
@@ -45,5 +45,6 @@
 #include "nslu2.h"
 #include "nas100d.h"
 #include "dsmg600.h"
+#include "fsg.h"
 
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h
index 11801605047b..674af4a84147 100644
--- a/include/asm-arm/arch-ixp4xx/irqs.h
+++ b/include/asm-arm/arch-ixp4xx/irqs.h
@@ -128,4 +128,11 @@
 #define        IRQ_DSMG600_PCI_INTE    IRQ_IXP4XX_GPIO7
 #define        IRQ_DSMG600_PCI_INTF    IRQ_IXP4XX_GPIO6
 
+/*
+ * Freecom FSG-3 Board IRQs
+ */
+#define        IRQ_FSG_PCI_INTA        IRQ_IXP4XX_GPIO6
+#define        IRQ_FSG_PCI_INTB        IRQ_IXP4XX_GPIO7
+#define        IRQ_FSG_PCI_INTC        IRQ_IXP4XX_GPIO5
+
 #endif
diff --git a/include/asm-arm/arch-kirkwood/debug-macro.S b/include/asm-arm/arch-kirkwood/debug-macro.S
new file mode 100644
index 000000000000..f55fb8ad9ee4
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * include/asm-arm/arch-kirkwood/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <asm/arch/kirkwood.h>
+
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =KIRKWOOD_REGS_PHYS_BASE
+        ldrne   \rx, =KIRKWOOD_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-kirkwood/dma.h b/include/asm-arm/arch-kirkwood/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/dma.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/include/asm-arm/arch-kirkwood/entry-macro.S b/include/asm-arm/arch-kirkwood/entry-macro.S
new file mode 100644
index 000000000000..fc6a43d9355c
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/entry-macro.S
@@ -0,0 +1,40 @@
+/*
+ * include/asm-arm/arch-kirkwood/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Marvell Kirkwood platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/arch/kirkwood.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IRQ_VIRT_BASE
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ check low interrupts
+        ldr     \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
+        mov     \irqnr, #31
+        ands    \irqstat, \irqstat, \tmp
+        bne     1001f
+
+        @ if no low interrupts set, check high interrupts
+        ldr     \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_HIGH_OFF]
+        mov     \irqnr, #63
+        ands    \irqstat, \irqstat, \tmp
+
+        @ find first active interrupt source
+1001:   clzne   \irqstat, \irqstat
+        subne   \irqnr, \irqnr, \irqstat
+        .endm
diff --git a/include/asm-arm/arch-kirkwood/hardware.h b/include/asm-arm/arch-kirkwood/hardware.h
new file mode 100644
index 000000000000..e695719771a5
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/hardware.h
@@ -0,0 +1,21 @@
+/*
+ * include/asm-arm/arch-kirkwood/hardware.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include "kirkwood.h"
+
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO                  0x00001000
+#define PCIBIOS_MIN_MEM                 0x01000000
+#define PCIMEM_BASE                     KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */
+
+
+#endif
diff --git a/include/asm-arm/arch-kirkwood/io.h b/include/asm-arm/arch-kirkwood/io.h
new file mode 100644
index 000000000000..0ef6e95f5d5b
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/io.h
@@ -0,0 +1,26 @@
+/*
+ * include/asm-arm/arch-kirkwood/io.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include "kirkwood.h"
+
+#define IO_SPACE_LIMIT          0xffffffff
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_PHYS_BASE)
+                                        + KIRKWOOD_PCIE_IO_VIRT_BASE);
+}
+
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+
+
+#endif
diff --git a/include/asm-arm/arch-kirkwood/irqs.h b/include/asm-arm/arch-kirkwood/irqs.h
new file mode 100644
index 000000000000..2e7b5da6335c
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/irqs.h
@@ -0,0 +1,63 @@
+/*
+ * include/asm-arm/arch-kirkwood/irqs.h
+ *
+ * IRQ definitions for Marvell Kirkwood SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include "kirkwood.h"   /* need GPIO_MAX */
+
+/*
+ * Low Interrupt Controller
+ */
+#define IRQ_KIRKWOOD_HIGH_SUM   0
+#define IRQ_KIRKWOOD_BRIDGE     1
+#define IRQ_KIRKWOOD_HOST2CPU   2
+#define IRQ_KIRKWOOD_CPU2HOST   3
+#define IRQ_KIRKWOOD_XOR_00     5
+#define IRQ_KIRKWOOD_XOR_01     6
+#define IRQ_KIRKWOOD_XOR_10     7
+#define IRQ_KIRKWOOD_XOR_11     8
+#define IRQ_KIRKWOOD_PCIE       9
+#define IRQ_KIRKWOOD_GE00_SUM   11
+#define IRQ_KIRKWOOD_GE01_SUM   15
+#define IRQ_KIRKWOOD_USB        19
+#define IRQ_KIRKWOOD_SATA       21
+#define IRQ_KIRKWOOD_CRYPTO     22
+#define IRQ_KIRKWOOD_SPI        23
+#define IRQ_KIRKWOOD_I2S        24
+#define IRQ_KIRKWOOD_TS_0       26
+#define IRQ_KIRKWOOD_SDIO       28
+#define IRQ_KIRKWOOD_TWSI       29
+#define IRQ_KIRKWOOD_AVB        30
+#define IRQ_KIRKWOOD_TDMI       31
+
+/*
+ * High Interrupt Controller
+ */
+#define IRQ_KIRKWOOD_UART_0     33
+#define IRQ_KIRKWOOD_UART_1     34
+#define IRQ_KIRKWOOD_GPIO_LOW_0_7       35
+#define IRQ_KIRKWOOD_GPIO_LOW_8_15      36
+#define IRQ_KIRKWOOD_GPIO_LOW_16_23     37
+#define IRQ_KIRKWOOD_GPIO_LOW_24_31     38
+#define IRQ_KIRKWOOD_GPIO_HIGH_0_7      39
+#define IRQ_KIRKWOOD_GPIO_HIGH_8_15     40
+#define IRQ_KIRKWOOD_GPIO_HIGH_16_23    41
+
+/*
+ * KIRKWOOD General Purpose Pins
+ */
+#define IRQ_KIRKWOOD_GPIO_START 64
+#define NR_GPIO_IRQS            GPIO_MAX
+
+#define NR_IRQS                 (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS)
+
+
+#endif
diff --git a/include/asm-arm/arch-kirkwood/kirkwood.h b/include/asm-arm/arch-kirkwood/kirkwood.h
new file mode 100644
index 000000000000..bb31b315c350
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/kirkwood.h
@@ -0,0 +1,100 @@
+/*
+ * include/asm-arm/arch-kirkwood/kirkwood.h
+ *
+ * Generic definitions for Marvell Kirkwood SoC flavors:
+ *  88F6180, 88F6192 and 88F6281.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_KIRKWOOD_H
+#define __ASM_ARCH_KIRKWOOD_H
+
+/*
+ * Marvell Kirkwood address maps.
+ *
+ * phys
+ * e0000000     PCIe Memory space
+ * f1000000     on-chip peripheral registers
+ * f2000000     PCIe I/O space
+ * f3000000     NAND controller address window
+ *
+ * virt         phys            size
+ * fee00000     f1000000        1M      on-chip peripheral registers
+ * fef00000     f2000000        1M      PCIe I/O space
+ */
+
+#define KIRKWOOD_NAND_MEM_PHYS_BASE     0xf3000000
+#define KIRKWOOD_NAND_MEM_SIZE          SZ_64K /* 1K is sufficient, but 64K
+                                                * is the minimal window size
+                                                */
+
+#define KIRKWOOD_PCIE_IO_PHYS_BASE      0xf2000000
+#define KIRKWOOD_PCIE_IO_VIRT_BASE      0xfef00000
+#define KIRKWOOD_PCIE_IO_BUS_BASE       0x00000000
+#define KIRKWOOD_PCIE_IO_SIZE           SZ_1M
+
+#define KIRKWOOD_REGS_PHYS_BASE         0xf1000000
+#define KIRKWOOD_REGS_VIRT_BASE         0xfee00000
+#define KIRKWOOD_REGS_SIZE              SZ_1M
+
+#define KIRKWOOD_PCIE_MEM_PHYS_BASE     0xe0000000
+#define KIRKWOOD_PCIE_MEM_SIZE          SZ_128M
+
+/*
+ * MBUS bridge registers.
+ */
+#define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
+#define  CPU_CONTROL            (BRIDGE_VIRT_BASE | 0x0104)
+#define   CPU_RESET             0x00000002
+#define  RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
+#define   SOFT_RESET_OUT_EN     0x00000004
+#define  SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
+#define   SOFT_RESET            0x00000001
+#define  BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
+#define  BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
+#define   BRIDGE_INT_TIMER0     0x0002
+#define   BRIDGE_INT_TIMER1     0x0004
+#define   BRIDGE_INT_TIMER1_CLR (~0x0004)
+#define  IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define   IRQ_CAUSE_LOW_OFF     0x0000
+#define   IRQ_MASK_LOW_OFF      0x0004
+#define   IRQ_CAUSE_HIGH_OFF    0x0010
+#define   IRQ_MASK_HIGH_OFF     0x0014
+#define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
+#define  L2_CONFIG_REG          (BRIDGE_VIRT_BASE | 0x0128)
+#define   L2_WRITETHROUGH       0x00000010
+
+/*
+ * Register Map
+ */
+#define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
+#define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE | 0x1500)
+
+#define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
+#define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
+#define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE | 0x0030)
+#define  DEVICE_ID              (DEV_BUS_VIRT_BASE | 0x0034)
+#define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0300)
+#define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0600)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
+
+#define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
+
+#define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
+
+#define GE00_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
+#define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
+
+#define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
+
+
+#define GPIO_MAX                50
+
+
+#endif
diff --git a/include/asm-arm/arch-kirkwood/memory.h b/include/asm-arm/arch-kirkwood/memory.h
new file mode 100644
index 000000000000..e5108f408ce6
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/memory.h
@@ -0,0 +1,14 @@
+/*
+ * include/asm-arm/arch-kirkwood/memory.h
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET             UL(0x00000000)
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+
+#endif
diff --git a/include/asm-arm/arch-kirkwood/system.h b/include/asm-arm/arch-kirkwood/system.h
new file mode 100644
index 000000000000..8dde7e379855
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/system.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm-arm/arch-kirkwood/system.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/kirkwood.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+
+        while (1)
+                ;
+}
+
+
+#endif
diff --git a/include/asm-arm/arch-kirkwood/timex.h b/include/asm-arm/arch-kirkwood/timex.h
new file mode 100644
index 000000000000..82122e134e3c
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/timex.h
@@ -0,0 +1,11 @@
+/*
+ * include/asm-arm/arch-kirkwood/timex.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE         (100 * HZ)
+
+#define KIRKWOOD_TCLK           166666667
diff --git a/include/asm-arm/arch-kirkwood/uncompress.h b/include/asm-arm/arch-kirkwood/uncompress.h
new file mode 100644
index 000000000000..a9062b6d7680
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/uncompress.h
@@ -0,0 +1,47 @@
+/*
+ * include/asm-arm/arch-kirkwood/uncompress.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/serial_reg.h>
+#include <asm/arch/kirkwood.h>
+
+#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
+
+static void putc(const char c)
+{
+        unsigned char *base = SERIAL_BASE;
+        int i;
+
+        for (i = 0; i < 0x1000; i++) {
+                if (base[UART_LSR << 2] & UART_LSR_THRE)
+                        break;
+                barrier();
+        }
+
+        base[UART_TX << 2] = c;
+}
+
+static void flush(void)
+{
+        unsigned char *base = SERIAL_BASE;
+        unsigned char mask;
+        int i;
+
+        mask = UART_LSR_TEMT | UART_LSR_THRE;
+
+        for (i = 0; i < 0x1000; i++) {
+                if ((base[UART_LSR << 2] & mask) == mask)
+                        break;
+                barrier();
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-kirkwood/vmalloc.h b/include/asm-arm/arch-kirkwood/vmalloc.h
new file mode 100644
index 000000000000..41852c6e77f3
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * include/asm-arm/arch-kirkwood/vmalloc.h
+ */
+
+#define VMALLOC_END     0xfe800000
diff --git a/include/asm-arm/arch-loki/debug-macro.S b/include/asm-arm/arch-loki/debug-macro.S
new file mode 100644
index 000000000000..585502e96513
--- /dev/null
+++ b/include/asm-arm/arch-loki/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * include/asm-arm/arch-loki/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <asm/arch/loki.h>
+
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =LOKI_REGS_PHYS_BASE
+        ldrne   \rx, =LOKI_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-loki/dma.h b/include/asm-arm/arch-loki/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-loki/dma.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/include/asm-arm/arch-loki/entry-macro.S b/include/asm-arm/arch-loki/entry-macro.S
new file mode 100644
index 000000000000..693257cdbeb8
--- /dev/null
+++ b/include/asm-arm/arch-loki/entry-macro.S
@@ -0,0 +1,30 @@
+/*
+ * include/asm-arm/arch-loki/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/arch/loki.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IRQ_VIRT_BASE
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \irqstat, [\base, #IRQ_CAUSE_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_OFF]
+        mov     \irqnr, #0
+        ands    \irqstat, \irqstat, \tmp
+        clzne   \irqnr, \irqstat
+        rsbne   \irqnr, \irqnr, #31
+        .endm
diff --git a/include/asm-arm/arch-loki/hardware.h b/include/asm-arm/arch-loki/hardware.h
new file mode 100644
index 000000000000..f65b01c733b6
--- /dev/null
+++ b/include/asm-arm/arch-loki/hardware.h
@@ -0,0 +1,15 @@
+/*
+ * include/asm-arm/arch-loki/hardware.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include "loki.h"
+
+
+#endif
diff --git a/include/asm-arm/arch-loki/io.h b/include/asm-arm/arch-loki/io.h
new file mode 100644
index 000000000000..e7418a915e75
--- /dev/null
+++ b/include/asm-arm/arch-loki/io.h
@@ -0,0 +1,26 @@
+/*
+ * include/asm-arm/arch-loki/io.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include "loki.h"
+
+#define IO_SPACE_LIMIT          0xffffffff
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE)
+                                        + LOKI_PCIE0_IO_VIRT_BASE);
+}
+
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+
+
+#endif
diff --git a/include/asm-arm/arch-loki/irqs.h b/include/asm-arm/arch-loki/irqs.h
new file mode 100644
index 000000000000..7e4971438072
--- /dev/null
+++ b/include/asm-arm/arch-loki/irqs.h
@@ -0,0 +1,58 @@
+/*
+ * include/asm-arm/arch-loki/irqs.h
+ *
+ * IRQ definitions for Marvell Loki (88RC8480) SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include "loki.h"       /* need GPIO_MAX */
+
+/*
+ * Interrupt Controller
+ */
+#define IRQ_LOKI_PCIE_A_CPU_DRBL        0
+#define IRQ_LOKI_CPU_PCIE_A_DRBL        1
+#define IRQ_LOKI_PCIE_B_CPU_DRBL        2
+#define IRQ_LOKI_CPU_PCIE_B_DRBL        3
+#define IRQ_LOKI_COM_A_ERR              6
+#define IRQ_LOKI_COM_A_IN               7
+#define IRQ_LOKI_COM_A_OUT              8
+#define IRQ_LOKI_COM_B_ERR              9
+#define IRQ_LOKI_COM_B_IN               10
+#define IRQ_LOKI_COM_B_OUT              11
+#define IRQ_LOKI_DMA_A                  12
+#define IRQ_LOKI_DMA_B                  13
+#define IRQ_LOKI_SAS_A                  14
+#define IRQ_LOKI_SAS_B                  15
+#define IRQ_LOKI_DDR                    16
+#define IRQ_LOKI_XOR                    17
+#define IRQ_LOKI_BRIDGE                 18
+#define IRQ_LOKI_PCIE_A_ERR             20
+#define IRQ_LOKI_PCIE_A_INT             21
+#define IRQ_LOKI_PCIE_B_ERR             22
+#define IRQ_LOKI_PCIE_B_INT             23
+#define IRQ_LOKI_GBE_A_INT              24
+#define IRQ_LOKI_GBE_B_INT              25
+#define IRQ_LOKI_DEV_ERR                26
+#define IRQ_LOKI_UART0                  27
+#define IRQ_LOKI_UART1                  28
+#define IRQ_LOKI_TWSI                   29
+#define IRQ_LOKI_GPIO_23_0              30
+#define IRQ_LOKI_GPIO_25_24             31
+
+/*
+ * Loki General Purpose Pins
+ */
+#define IRQ_LOKI_GPIO_START     32
+#define NR_GPIO_IRQS            GPIO_MAX
+
+#define NR_IRQS                 (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS)
+
+
+#endif
diff --git a/include/asm-arm/arch-loki/loki.h b/include/asm-arm/arch-loki/loki.h
new file mode 100644
index 000000000000..5dd05ee0a4e6
--- /dev/null
+++ b/include/asm-arm/arch-loki/loki.h
@@ -0,0 +1,97 @@
+/*
+ * include/asm-arm/arch-loki/loki.h
+ *
+ * Generic definitions for Marvell Loki (88RC8480) SoC flavors
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_LOKI_H
+#define __ASM_ARCH_LOKI_H
+
+/*
+ * Marvell Loki (88RC8480) address maps.
+ *
+ * phys
+ * d0000000     on-chip peripheral registers
+ * e0000000     PCIe 0 Memory space
+ * e8000000     PCIe 1 Memory space
+ * f0000000     PCIe 0 I/O space
+ * f0100000     PCIe 1 I/O space
+ *
+ * virt         phys            size
+ * fed00000     d0000000        1M      on-chip peripheral registers
+ * fee00000     f0000000        64K     PCIe 0 I/O space
+ * fef00000     f0100000        64K     PCIe 1 I/O space
+ */
+
+#define LOKI_REGS_PHYS_BASE             0xd0000000
+#define LOKI_REGS_VIRT_BASE             0xfed00000
+#define LOKI_REGS_SIZE                  SZ_1M
+
+#define LOKI_PCIE0_IO_PHYS_BASE         0xf0000000
+#define LOKI_PCIE0_IO_VIRT_BASE         0xfee00000
+#define LOKI_PCIE0_IO_BUS_BASE          0x00000000
+#define LOKI_PCIE0_IO_SIZE              SZ_64K
+
+#define LOKI_PCIE1_IO_PHYS_BASE         0xf0100000
+#define LOKI_PCIE1_IO_VIRT_BASE         0xfef00000
+#define LOKI_PCIE1_IO_BUS_BASE          0x00000000
+#define LOKI_PCIE1_IO_SIZE              SZ_64K
+
+#define LOKI_PCIE0_MEM_PHYS_BASE        0xe0000000
+#define LOKI_PCIE0_MEM_SIZE             SZ_128M
+
+#define LOKI_PCIE1_MEM_PHYS_BASE        0xe8000000
+#define LOKI_PCIE1_MEM_SIZE             SZ_128M
+
+/*
+ * Register Map
+ */
+#define DEV_BUS_PHYS_BASE       (LOKI_REGS_PHYS_BASE | 0x10000)
+#define DEV_BUS_VIRT_BASE       (LOKI_REGS_VIRT_BASE | 0x10000)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
+
+#define BRIDGE_VIRT_BASE        (LOKI_REGS_VIRT_BASE | 0x20000)
+#define  BRIDGE_REG(x)          (BRIDGE_VIRT_BASE | (x))
+#define  RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
+#define   SOFT_RESET_OUT_EN     0x00000004
+#define  SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
+#define   SOFT_RESET            0x00000001
+#define  BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
+#define  BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
+#define   BRIDGE_INT_TIMER0     0x0002
+#define   BRIDGE_INT_TIMER1     0x0004
+#define   BRIDGE_INT_TIMER1_CLR 0x0004
+#define  IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define   IRQ_CAUSE_OFF         0x0000
+#define   IRQ_MASK_OFF          0x0004
+#define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
+
+#define PCIE0_VIRT_BASE         (LOKI_REGS_VIRT_BASE | 0x30000)
+
+#define PCIE1_VIRT_BASE         (LOKI_REGS_VIRT_BASE | 0x40000)
+
+#define SAS0_PHYS_BASE          (LOKI_REGS_PHYS_BASE | 0x80000)
+
+#define SAS1_PHYS_BASE          (LOKI_REGS_PHYS_BASE | 0x90000)
+
+#define GE0_PHYS_BASE           (LOKI_REGS_PHYS_BASE | 0xa0000)
+#define GE0_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xa0000)
+
+#define GE1_PHYS_BASE           (LOKI_REGS_PHYS_BASE | 0xb0000)
+#define GE1_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xb0000)
+
+#define DDR_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xf0000)
+#define DDR_REG(x)              (DDR_VIRT_BASE | (x))
+
+
+#define GPIO_MAX                8
+
+
+#endif
diff --git a/include/asm-arm/arch-loki/memory.h b/include/asm-arm/arch-loki/memory.h
new file mode 100644
index 000000000000..835101e49875
--- /dev/null
+++ b/include/asm-arm/arch-loki/memory.h
@@ -0,0 +1,14 @@
+/*
+ * include/asm-arm/arch-loki/memory.h
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET             UL(0x00000000)
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+
+#endif
diff --git a/include/asm-arm/arch-loki/system.h b/include/asm-arm/arch-loki/system.h
new file mode 100644
index 000000000000..a3568ac8ec35
--- /dev/null
+++ b/include/asm-arm/arch-loki/system.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm-arm/arch-loki/system.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/loki.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+
+        while (1)
+                ;
+}
+
+
+#endif
diff --git a/include/asm-arm/arch-loki/timex.h b/include/asm-arm/arch-loki/timex.h
new file mode 100644
index 000000000000..940014f97cae
--- /dev/null
+++ b/include/asm-arm/arch-loki/timex.h
@@ -0,0 +1,11 @@
+/*
+ * include/asm-arm/arch-loki/timex.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE         (100 * HZ)
+
+#define LOKI_TCLK               180000000
diff --git a/include/asm-arm/arch-loki/uncompress.h b/include/asm-arm/arch-loki/uncompress.h
new file mode 100644
index 000000000000..89a0cf88d3a5
--- /dev/null
+++ b/include/asm-arm/arch-loki/uncompress.h
@@ -0,0 +1,47 @@
+/*
+ * include/asm-arm/arch-loki/uncompress.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/serial_reg.h>
+#include <asm/arch/loki.h>
+
+#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
+
+static void putc(const char c)
+{
+        unsigned char *base = SERIAL_BASE;
+        int i;
+
+        for (i = 0; i < 0x1000; i++) {
+                if (base[UART_LSR << 2] & UART_LSR_THRE)
+                        break;
+                barrier();
+        }
+
+        base[UART_TX << 2] = c;
+}
+
+static void flush(void)
+{
+        unsigned char *base = SERIAL_BASE;
+        unsigned char mask;
+        int i;
+
+        mask = UART_LSR_TEMT | UART_LSR_THRE;
+
+        for (i = 0; i < 0x1000; i++) {
+                if ((base[UART_LSR << 2] & mask) == mask)
+                        break;
+                barrier();
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-loki/vmalloc.h b/include/asm-arm/arch-loki/vmalloc.h
new file mode 100644
index 000000000000..f5be06220491
--- /dev/null
+++ b/include/asm-arm/arch-loki/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * include/asm-arm/arch-loki/vmalloc.h
+ */
+
+#define VMALLOC_END     0xfe800000
diff --git a/include/asm-arm/arch-msm/irqs.h b/include/asm-arm/arch-msm/irqs.h
index 565430cfaa7e..e62a108b1857 100644
--- a/include/asm-arm/arch-msm/irqs.h
+++ b/include/asm-arm/arch-msm/irqs.h
@@ -15,6 +15,7 @@
  */
 
 #ifndef __ASM_ARCH_MSM_IRQS_H
+#define __ASM_ARCH_MSM_IRQS_H
 
 /* MSM ARM11 Interrupt Numbers */
 /* See 80-VE113-1 A, pp219-221     */
diff --git a/include/asm-arm/arch-msm/timex.h b/include/asm-arm/arch-msm/timex.h
index 154b23fb3599..8724487ab4c9 100644
--- a/include/asm-arm/arch-msm/timex.h
+++ b/include/asm-arm/arch-msm/timex.h
@@ -14,6 +14,7 @@
  */
 
 #ifndef __ASM_ARCH_MSM_TIMEX_H
+#define __ASM_ARCH_MSM_TIMEX_H
 
 #define CLOCK_TICK_RATE         1000000
 
diff --git a/include/asm-arm/arch-mv78xx0/debug-macro.S b/include/asm-arm/arch-mv78xx0/debug-macro.S
new file mode 100644
index 000000000000..d0595bd645e5
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * include/asm-arm/arch-mv78xx0/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <asm/arch/mv78xx0.h>
+
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =MV78XX0_REGS_PHYS_BASE
+        ldrne   \rx, =MV78XX0_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-mv78xx0/dma.h b/include/asm-arm/arch-mv78xx0/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/dma.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/include/asm-arm/arch-mv78xx0/entry-macro.S b/include/asm-arm/arch-mv78xx0/entry-macro.S
new file mode 100644
index 000000000000..e9a606b12669
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/entry-macro.S
@@ -0,0 +1,39 @@
+/*
+ * include/asm-arm/arch-mv78xx0/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Marvell MV78xx0 platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/arch/mv78xx0.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IRQ_VIRT_BASE
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ check low interrupts
+        ldr     \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
+        mov     \irqnr, #31
+        ands    \irqstat, \irqstat, \tmp
+
+        @ if no low interrupts set, check high interrupts
+        ldreq   \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
+        ldreq   \tmp, [\base, #IRQ_MASK_HIGH_OFF]
+        moveq   \irqnr, #63
+        andeqs  \irqstat, \irqstat, \tmp
+
+        @ find first active interrupt source
+        clzne   \irqstat, \irqstat
+        subne   \irqnr, \irqnr, \irqstat
+        .endm
diff --git a/include/asm-arm/arch-mv78xx0/hardware.h b/include/asm-arm/arch-mv78xx0/hardware.h
new file mode 100644
index 000000000000..8e17926086c6
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/hardware.h
@@ -0,0 +1,21 @@
+/*
+ * include/asm-arm/arch-mv78xx0/hardware.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include "mv78xx0.h"
+
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO                  0x00001000
+#define PCIBIOS_MIN_MEM                 0x01000000
+#define PCIMEM_BASE                     MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */
+
+
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/io.h b/include/asm-arm/arch-mv78xx0/io.h
new file mode 100644
index 000000000000..415d4c98e3d1
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/io.h
@@ -0,0 +1,26 @@
+/*
+ * include/asm-arm/arch-mv78xx0/io.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include "mv78xx0.h"
+
+#define IO_SPACE_LIMIT          0xffffffff
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
+                                        + MV78XX0_PCIE_IO_VIRT_BASE(0));
+}
+
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+
+
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/irqs.h b/include/asm-arm/arch-mv78xx0/irqs.h
new file mode 100644
index 000000000000..75930450cd65
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/irqs.h
@@ -0,0 +1,91 @@
+/*
+ * include/asm-arm/arch-mv78xx0/irqs.h
+ *
+ * IRQ definitions for Marvell MV78xx0 SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include "mv78xx0.h"    /* need GPIO_MAX */
+
+/*
+ * MV78xx0 Low Interrupt Controller
+ */
+#define IRQ_MV78XX0_ERR         0
+#define IRQ_MV78XX0_SPI         1
+#define IRQ_MV78XX0_I2C_0       2
+#define IRQ_MV78XX0_I2C_1       3
+#define IRQ_MV78XX0_IDMA_0      4
+#define IRQ_MV78XX0_IDMA_1      5
+#define IRQ_MV78XX0_IDMA_2      6
+#define IRQ_MV78XX0_IDMA_3      7
+#define IRQ_MV78XX0_TIMER_0     8
+#define IRQ_MV78XX0_TIMER_1     9
+#define IRQ_MV78XX0_TIMER_2     10
+#define IRQ_MV78XX0_TIMER_3     11
+#define IRQ_MV78XX0_UART_0      12
+#define IRQ_MV78XX0_UART_1      13
+#define IRQ_MV78XX0_UART_2      14
+#define IRQ_MV78XX0_UART_3      15
+#define IRQ_MV78XX0_USB_0       16
+#define IRQ_MV78XX0_USB_1       17
+#define IRQ_MV78XX0_USB_2       18
+#define IRQ_MV78XX0_CRYPTO      19
+#define IRQ_MV78XX0_SDIO_0      20
+#define IRQ_MV78XX0_SDIO_1      21
+#define IRQ_MV78XX0_XOR_0       22
+#define IRQ_MV78XX0_XOR_1       23
+#define IRQ_MV78XX0_I2S_0       24
+#define IRQ_MV78XX0_I2S_1       25
+#define IRQ_MV78XX0_SATA        26
+#define IRQ_MV78XX0_TDMI        27
+
+/*
+ * MV78xx0 High Interrupt Controller
+ */
+#define IRQ_MV78XX0_PCIE_00     32
+#define IRQ_MV78XX0_PCIE_01     33
+#define IRQ_MV78XX0_PCIE_02     34
+#define IRQ_MV78XX0_PCIE_03     35
+#define IRQ_MV78XX0_PCIE_10     36
+#define IRQ_MV78XX0_PCIE_11     37
+#define IRQ_MV78XX0_PCIE_12     38
+#define IRQ_MV78XX0_PCIE_13     39
+#define IRQ_MV78XX0_GE00_SUM    40
+#define IRQ_MV78XX0_GE00_RX     41
+#define IRQ_MV78XX0_GE00_TX     42
+#define IRQ_MV78XX0_GE00_MISC   43
+#define IRQ_MV78XX0_GE01_SUM    44
+#define IRQ_MV78XX0_GE01_RX     45
+#define IRQ_MV78XX0_GE01_TX     46
+#define IRQ_MV78XX0_GE01_MISC   47
+#define IRQ_MV78XX0_GE10_SUM    48
+#define IRQ_MV78XX0_GE10_RX     49
+#define IRQ_MV78XX0_GE10_TX     50
+#define IRQ_MV78XX0_GE10_MISC   51
+#define IRQ_MV78XX0_GE11_SUM    52
+#define IRQ_MV78XX0_GE11_RX     53
+#define IRQ_MV78XX0_GE11_TX     54
+#define IRQ_MV78XX0_GE11_MISC   55
+#define IRQ_MV78XX0_GPIO_0_7    56
+#define IRQ_MV78XX0_GPIO_8_15   57
+#define IRQ_MV78XX0_GPIO_16_23  58
+#define IRQ_MV78XX0_GPIO_24_31  59
+#define IRQ_MV78XX0_DB_IN       60
+#define IRQ_MV78XX0_DB_OUT      61
+
+/*
+ * MV78XX0 General Purpose Pins
+ */
+#define IRQ_MV78XX0_GPIO_START  64
+#define NR_GPIO_IRQS            GPIO_MAX
+
+#define NR_IRQS                 (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
+
+
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/memory.h b/include/asm-arm/arch-mv78xx0/memory.h
new file mode 100644
index 000000000000..721a6b185b91
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/memory.h
@@ -0,0 +1,14 @@
+/*
+ * include/asm-arm/arch-mv78xx0/memory.h
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET             UL(0x00000000)
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/mv78xx0.h b/include/asm-arm/arch-mv78xx0/mv78xx0.h
new file mode 100644
index 000000000000..9f5d83c73faa
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/mv78xx0.h
@@ -0,0 +1,126 @@
+/*
+ * include/asm-arm/arch-mv78xx0/mv78xx0.h
+ *
+ * Generic definitions for Marvell MV78xx0 SoC flavors:
+ *  MV781x0 and MV782x0.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_MV78XX0_H
+#define __ASM_ARCH_MV78XX0_H
+
+/*
+ * Marvell MV78xx0 address maps.
+ *
+ * phys
+ * c0000000     PCIe Memory space
+ * f0800000     PCIe #0 I/O space
+ * f0900000     PCIe #1 I/O space
+ * f0a00000     PCIe #2 I/O space
+ * f0b00000     PCIe #3 I/O space
+ * f0c00000     PCIe #4 I/O space
+ * f0d00000     PCIe #5 I/O space
+ * f0e00000     PCIe #6 I/O space
+ * f0f00000     PCIe #7 I/O space
+ * f1000000     on-chip peripheral registers
+ *
+ * virt         phys            size
+ * fe400000     f102x000        16K     core-specific peripheral registers
+ * fe700000     f0800000        1M      PCIe #0 I/O space
+ * fe800000     f0900000        1M      PCIe #1 I/O space
+ * fe900000     f0a00000        1M      PCIe #2 I/O space
+ * fea00000     f0b00000        1M      PCIe #3 I/O space
+ * feb00000     f0c00000        1M      PCIe #4 I/O space
+ * fec00000     f0d00000        1M      PCIe #5 I/O space
+ * fed00000     f0e00000        1M      PCIe #6 I/O space
+ * fee00000     f0f00000        1M      PCIe #7 I/O space
+ * fef00000     f1000000        1M      on-chip peripheral registers
+ */
+#define MV78XX0_CORE0_REGS_PHYS_BASE    0xf1020000
+#define MV78XX0_CORE1_REGS_PHYS_BASE    0xf1024000
+#define MV78XX0_CORE_REGS_VIRT_BASE     0xfe400000
+#define MV78XX0_CORE_REGS_SIZE          SZ_16K
+
+#define MV78XX0_PCIE_IO_PHYS_BASE(i)    (0xf0800000 + ((i) << 20))
+#define MV78XX0_PCIE_IO_VIRT_BASE(i)    (0xfe700000 + ((i) << 20))
+#define MV78XX0_PCIE_IO_SIZE            SZ_1M
+
+#define MV78XX0_REGS_PHYS_BASE          0xf1000000
+#define MV78XX0_REGS_VIRT_BASE          0xfef00000
+#define MV78XX0_REGS_SIZE               SZ_1M
+
+#define MV78XX0_PCIE_MEM_PHYS_BASE      0xc0000000
+#define MV78XX0_PCIE_MEM_SIZE           0x30000000
+
+/*
+ * Core-specific peripheral registers.
+ */
+#define BRIDGE_VIRT_BASE        (MV78XX0_CORE_REGS_VIRT_BASE)
+#define  CPU_CONTROL            (BRIDGE_VIRT_BASE | 0x0104)
+#define   L2_WRITETHROUGH       0x00020000
+#define  RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
+#define   SOFT_RESET_OUT_EN     0x00000004
+#define  SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
+#define   SOFT_RESET            0x00000001
+#define  BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
+#define  BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
+#define   BRIDGE_INT_TIMER0     0x0002
+#define   BRIDGE_INT_TIMER1     0x0004
+#define   BRIDGE_INT_TIMER1_CLR (~0x0004)
+#define  IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define   IRQ_CAUSE_LOW_OFF     0x0004
+#define   IRQ_CAUSE_HIGH_OFF    0x0008
+#define   IRQ_MASK_LOW_OFF      0x0010
+#define   IRQ_MASK_HIGH_OFF     0x0014
+#define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
+
+/*
+ * Register Map
+ */
+#define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE | 0x00000)
+#define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE | 0x1500)
+#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE | 0x1700)
+
+#define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE | 0x10000)
+#define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x10000)
+#define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE | 0x0030)
+#define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE | 0x0034)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
+#define  UART2_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2200)
+#define  UART2_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2200)
+#define  UART3_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2300)
+#define  UART3_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2300)
+
+#define GE10_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x30000)
+#define GE11_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x34000)
+
+#define PCIE00_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x40000)
+#define PCIE01_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x44000)
+#define PCIE02_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x48000)
+#define PCIE03_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x4c000)
+
+#define USB0_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x50000)
+#define USB1_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x51000)
+#define USB2_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x52000)
+
+#define GE00_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x70000)
+#define GE01_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x74000)
+
+#define PCIE10_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x80000)
+#define PCIE11_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x84000)
+#define PCIE12_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x88000)
+#define PCIE13_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x8c000)
+
+#define SATA_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0xa0000)
+
+
+#define GPIO_MAX                32
+
+
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/system.h b/include/asm-arm/arch-mv78xx0/system.h
new file mode 100644
index 000000000000..7eb47d376db9
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/system.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm-arm/arch-mv78xx0/system.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/mv78xx0.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+
+        while (1)
+                ;
+}
+
+
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/timex.h b/include/asm-arm/arch-mv78xx0/timex.h
new file mode 100644
index 000000000000..a854b1ccbd01
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/timex.h
@@ -0,0 +1,9 @@
+/*
+ * include/asm-arm/arch-mv78xx0/timex.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/include/asm-arm/arch-mv78xx0/uncompress.h b/include/asm-arm/arch-mv78xx0/uncompress.h
new file mode 100644
index 000000000000..3bfe0a293ef7
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/uncompress.h
@@ -0,0 +1,47 @@
+/*
+ * include/asm-arm/arch-mv78xx0/uncompress.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/serial_reg.h>
+#include <asm/arch/mv78xx0.h>
+
+#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
+
+static void putc(const char c)
+{
+        unsigned char *base = SERIAL_BASE;
+        int i;
+
+        for (i = 0; i < 0x1000; i++) {
+                if (base[UART_LSR << 2] & UART_LSR_THRE)
+                        break;
+                barrier();
+        }
+
+        base[UART_TX << 2] = c;
+}
+
+static void flush(void)
+{
+        unsigned char *base = SERIAL_BASE;
+        unsigned char mask;
+        int i;
+
+        mask = UART_LSR_TEMT | UART_LSR_THRE;
+
+        for (i = 0; i < 0x1000; i++) {
+                if ((base[UART_LSR << 2] & mask) == mask)
+                        break;
+                barrier();
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-mv78xx0/vmalloc.h b/include/asm-arm/arch-mv78xx0/vmalloc.h
new file mode 100644
index 000000000000..f2c512197579
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * include/asm-arm/arch-mv78xx0/vmalloc.h
+ */
+
+#define VMALLOC_END     0xfe000000
diff --git a/include/asm-arm/arch-mxc/board-mx27ads.h b/include/asm-arm/arch-mxc/board-mx27ads.h
new file mode 100644
index 000000000000..61e66dac90ef
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx27ads.h
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
+#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
+
+/* external interrupt multiplexer */
+#define MXC_EXP_IO_BASE         (MXC_GPIO_BASE + MXC_MAX_GPIO_LINES)
+
+#define MXC_VIRTUAL_INTS_BASE   (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
+#define MXC_SDIO1_CARD_IRQ      MXC_VIRTUAL_INTS_BASE
+#define MXC_SDIO2_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 1)
+#define MXC_SDIO3_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 2)
+
+#define MXC_MAX_BOARD_INTS      (MXC_MAX_EXP_IO_LINES + \
+                                MXC_MAX_VIRTUAL_INTS)
+
+/*
+ * MXC UART EVB board level configurations
+ */
+
+#define MXC_LL_EXTUART_PADDR    (CS4_BASE_ADDR + 0x20000)
+#define MXC_LL_EXTUART_VADDR    (CS4_BASE_ADDR_VIRT + 0x20000)
+#define MXC_LL_EXTUART_16BIT_BUS
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPI_IO_ADDRESS(UART1_BASE_ADDR)
+
+/*
+ * @name Memory Size parameters
+ */
+
+/*
+ * Size of SDRAM memory
+ */
+#define SDRAM_MEM_SIZE          SZ_128M
+
+/*
+ * PBC Controller parameters
+ */
+
+/*
+ * Base address of PBC controller, CS4
+ */
+#define PBC_BASE_ADDRESS        0xEB000000
+#define PBC_REG_ADDR(offset)    (PBC_BASE_ADDRESS + (offset))
+
+/*
+ * PBC Interupt name definitions
+ */
+#define PBC_GPIO1_0  0
+#define PBC_GPIO1_1  1
+#define PBC_GPIO1_2  2
+#define PBC_GPIO1_3  3
+#define PBC_GPIO1_4  4
+#define PBC_GPIO1_5  5
+
+#define PBC_INTR_MAX_NUM 6
+#define PBC_INTR_SHARED_MAX_NUM 8
+
+/* When the PBC address connection is fixed in h/w, defined as 1 */
+#define PBC_ADDR_SH             0
+
+/* Offsets for the PBC Controller register */
+/*
+ * PBC Board version register offset
+ */
+#define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 set address.
+ */
+#define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 clear address.
+ */
+#define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 2 set address.
+ */
+#define PBC_BCTRL2_SET_REG      PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 2 clear address.
+ */
+#define PBC_BCTRL2_CLEAR_REG    PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 3 set address.
+ */
+#define PBC_BCTRL3_SET_REG      PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 3 clear address.
+ */
+#define PBC_BCTRL3_CLEAR_REG    PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 3 set address.
+ */
+#define PBC_BCTRL4_SET_REG      PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 4 clear address.
+ */
+#define PBC_BCTRL4_CLEAR_REG    PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
+/*PBC_ADDR_SH
+ * PBC Board status register 1.
+ */
+#define PBC_BSTAT1_REG          PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
+/*
+ * PBC Board interrupt status register.
+ */
+#define PBC_INTSTATUS_REG       PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
+/*
+ * PBC Board interrupt current status register.
+ */
+#define PBC_INTCURR_STATUS_REG  PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
+/*
+ * PBC Interrupt mask register set address.
+ */
+#define PBC_INTMASK_SET_REG     PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
+/*
+ * PBC Interrupt mask register clear address.
+ */
+#define PBC_INTMASK_CLEAR_REG   PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
+/*
+ * External UART A.
+ */
+#define PBC_SC16C652_UARTA_REG  PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
+/*
+ * UART 4 Expanding Signal Status.
+ */
+#define PBC_UART_STATUS_REG     PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
+/*
+ * UART 4 Expanding Signal Control Set.
+ */
+#define PBC_UCTRL_SET_REG       PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
+/*
+ * UART 4 Expanding Signal Control Clear.
+ */
+#define PBC_UCTRL_CLR_REG       PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
+/*
+ * Ethernet Controller IO base address.
+ */
+#define PBC_CS8900A_IOBASE_REG  PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
+/*
+ * Ethernet Controller Memory base address.
+ */
+#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
+/*
+ * Ethernet Controller DMA base address.
+ */
+#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
+
+/* PBC Board Version Register bit definition */
+#define PBC_VERSION_ADS         0x8000  /* Bit15=1 means version for ads */
+#define PBC_VERSION_EVB_REVB    0x4000  /* BIT14=1 means version for evb revb */
+
+/* PBC Board Control Register 1 bit definitions */
+#define PBC_BCTRL1_ERST         0x0001  /* Ethernet Reset */
+#define PBC_BCTRL1_URST         0x0002  /* Reset External UART controller */
+#define PBC_BCTRL1_FRST         0x0004  /* FEC Reset */
+#define PBC_BCTRL1_ESLEEP       0x0010  /* Enable ethernet Sleep */
+#define PBC_BCTRL1_LCDON        0x0800  /* Enable the LCD */
+
+/* PBC Board Control Register 2 bit definitions */
+#define PBC_BCTRL2_VCC_EN       0x0004  /*   Enable VCC */
+#define PBC_BCTRL2_VPP_EN       0x0008  /*   Enable Vpp */
+#define PBC_BCTRL2_ATAFEC_EN    0X0010
+#define PBC_BCTRL2_ATAFEC_SEL   0X0020
+#define PBC_BCTRL2_ATA_EN       0X0040
+#define PBC_BCTRL2_IRDA_SD      0X0080
+#define PBC_BCTRL2_IRDA_EN      0X0100
+#define PBC_BCTRL2_CCTL10       0X0200
+#define PBC_BCTRL2_CCTL11       0X0400
+
+/* PBC Board Control Register 3 bit definitions */
+#define PBC_BCTRL3_HSH_EN       0X0020
+#define PBC_BCTRL3_FSH_MOD      0X0040
+#define PBC_BCTRL3_OTG_HS_EN    0X0080
+#define PBC_BCTRL3_OTG_VBUS_EN  0X0100
+#define PBC_BCTRL3_FSH_VBUS_EN  0X0200
+#define PBC_BCTRL3_USB_OTG_ON   0X0800
+#define PBC_BCTRL3_USB_FSH_ON   0X1000
+
+/* PBC Board Control Register 4 bit definitions */
+#define PBC_BCTRL4_REGEN_SEL    0X0001
+#define PBC_BCTRL4_USER_OFF     0X0002
+#define PBC_BCTRL4_VIB_EN       0X0004
+#define PBC_BCTRL4_PWRGT1_EN    0X0008
+#define PBC_BCTRL4_PWRGT2_EN    0X0010
+#define PBC_BCTRL4_STDBY_PRI    0X0020
+
+#ifndef __ASSEMBLY__
+/*
+ * Enumerations for SD cards and memory stick card. This corresponds to
+ * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
+ */
+enum mxc_card_no {
+        MXC_CARD_SD2 = 0,
+        MXC_CARD_SD3,
+        MXC_CARD_MS,
+        MXC_CARD_SD1,
+        MXC_CARD_MIN = MXC_CARD_SD2,
+        MXC_CARD_MAX = MXC_CARD_SD1,
+};
+#endif
+
+#define MXC_CPLD_VER_1_50       0x01
+
+/*
+ * PBC BSTAT Register bit definitions
+ */
+#define PBC_BSTAT_PRI_INT       0X0001
+#define PBC_BSTAT_USB_BYP       0X0002
+#define PBC_BSTAT_ATA_IOCS16    0X0004
+#define PBC_BSTAT_ATA_CBLID     0X0008
+#define PBC_BSTAT_ATA_DASP      0X0010
+#define PBC_BSTAT_PWR_RDY       0X0020
+#define PBC_BSTAT_SD3_WP        0X0100
+#define PBC_BSTAT_SD2_WP        0X0200
+#define PBC_BSTAT_SD1_WP        0X0400
+#define PBC_BSTAT_SD3_DET       0X0800
+#define PBC_BSTAT_SD2_DET       0X1000
+#define PBC_BSTAT_SD1_DET       0X2000
+#define PBC_BSTAT_MS_DET        0X4000
+#define PBC_BSTAT_SD3_DET_BIT   11
+#define PBC_BSTAT_SD2_DET_BIT   12
+#define PBC_BSTAT_SD1_DET_BIT   13
+#define PBC_BSTAT_MS_DET_BIT    14
+#define MXC_BSTAT_BIT(n)        ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
+                                 ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
+                                 ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
+                                 ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
+                                        0x0))))
+
+/*
+ * PBC UART Control Register bit definitions
+ */
+#define PBC_UCTRL_DCE_DCD       0X0001
+#define PBC_UCTRL_DCE_DSR       0X0002
+#define PBC_UCTRL_DCE_RI        0X0004
+#define PBC_UCTRL_DTE_DTR       0X0100
+
+/*
+ * PBC UART Status Register bit definitions
+ */
+#define PBC_USTAT_DTE_DCD       0X0001
+#define PBC_USTAT_DTE_DSR       0X0002
+#define PBC_USTAT_DTE_RI        0X0004
+#define PBC_USTAT_DCE_DTR       0X0100
+
+/*
+ * PBC Interupt mask register bit definitions
+ */
+#define PBC_INTR_SD3_R_EN_BIT   4
+#define PBC_INTR_SD2_R_EN_BIT   0
+#define PBC_INTR_SD1_R_EN_BIT   6
+#define PBC_INTR_MS_R_EN_BIT    5
+#define PBC_INTR_SD3_EN_BIT     13
+#define PBC_INTR_SD2_EN_BIT     12
+#define PBC_INTR_MS_EN_BIT      14
+#define PBC_INTR_SD1_EN_BIT     15
+
+#define PBC_INTR_SD2_R_EN       0x0001
+#define PBC_INTR_LOW_BAT        0X0002
+#define PBC_INTR_OTG_FSOVER     0X0004
+#define PBC_INTR_FSH_OVER       0X0008
+#define PBC_INTR_SD3_R_EN       0x0010
+#define PBC_INTR_MS_R_EN        0x0020
+#define PBC_INTR_SD1_R_EN       0x0040
+#define PBC_INTR_FEC_INT        0X0080
+#define PBC_INTR_ENET_INT       0X0100
+#define PBC_INTR_OTGFS_INT      0X0200
+#define PBC_INTR_XUART_INT      0X0400
+#define PBC_INTR_CCTL12         0X0800
+#define PBC_INTR_SD2_EN         0x1000
+#define PBC_INTR_SD3_EN         0x2000
+#define PBC_INTR_MS_EN          0x4000
+#define PBC_INTR_SD1_EN         0x8000
+
+
+
+/* For interrupts like xuart, enet etc */
+#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX27_PIN_TIN)
+#define MXC_MAX_EXP_IO_LINES    16
+
+/*
+ * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
+ *
+ */
+#define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 1)
+#define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
+#define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
+#define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
+#define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
+#define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
+#define EXPIO_INT_FEC           (MXC_EXP_IO_BASE + 7)
+#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
+#define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
+#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_CCTL12_INT    (MXC_EXP_IO_BASE + 11)
+#define EXPIO_INT_SD2_EN        (MXC_EXP_IO_BASE + 12)
+#define EXPIO_INT_SD3_EN        (MXC_EXP_IO_BASE + 13)
+#define EXPIO_INT_MS_EN         (MXC_EXP_IO_BASE + 14)
+#define EXPIO_INT_SD1_EN        (MXC_EXP_IO_BASE + 15)
+
+/*
+ * This is System IRQ used by CS8900A for interrupt generation
+ * taken from platform.h
+ */
+#define CS8900AIRQ              EXPIO_INT_ENET_INT
+/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
+#define CS8900A_BASE_ADDRESS    (PBC_CS8900A_IOBASE_REG + 0x300)
+
+#define MXC_PMIC_INT_LINE       IOMUX_TO_IRQ(MX27_PIN_TOUT)
+
+/*
+* This is used to detect if the CPLD version is for mx27 evb board rev-a
+*/
+#define PBC_CPLD_VERSION_IS_REVA() \
+        ((__raw_readw(PBC_VERSION_REG) & \
+        (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
+        == 0)
+
+/* This is used to active or inactive ata signal in CPLD .
+ *  It is dependent with hardware
+ */
+#define PBC_ATA_SIGNAL_ACTIVE() \
+        __raw_writew(           \
+                PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
+                PBC_BCTRL2_CLEAR_REG)
+
+#define PBC_ATA_SIGNAL_INACTIVE() \
+        __raw_writew(  \
+                PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
+                PBC_BCTRL2_SET_REG)
+
+#define MXC_BD_LED1             (1 << 5)
+#define MXC_BD_LED2             (1 << 6)
+#define MXC_BD_LED_ON(led) \
+        __raw_writew(led, PBC_BCTRL1_SET_REG)
+#define MXC_BD_LED_OFF(led) \
+        __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
+
+/* to determine the correct external crystal reference */
+#define CKIH_27MHZ_BIT_SET      (1 << 3)
+
+#endif                          /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h
index 8590127760a8..1bc6fb0f9a83 100644
--- a/include/asm-arm/arch-mxc/board-mx31ads.h
+++ b/include/asm-arm/arch-mxc/board-mx31ads.h
@@ -109,4 +109,9 @@
 
 #define MXC_MAX_EXP_IO_LINES    16
 
+/* mandatory for CONFIG_LL_DEBUG */
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+
 #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/board-mx31lite.h b/include/asm-arm/arch-mxc/board-mx31lite.h
new file mode 100644
index 000000000000..e4e5cf5ad7db
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx31lite.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
+#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
+
+#define MXC_MAX_EXP_IO_LINES    16
+
+
+/*
+ * Memory Size parameters
+ */
+
+/*
+ * Size of SDRAM memory
+ */
+#define SDRAM_MEM_SIZE          SZ_128M
+/*
+ * Size of MBX buffer memory
+ */
+#define MXC_MBX_MEM_SIZE        SZ_16M
+/*
+ * Size of memory available to kernel
+ */
+#define MEM_SIZE                (SDRAM_MEM_SIZE - MXC_MBX_MEM_SIZE)
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+
+#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
+
diff --git a/include/asm-arm/arch-mxc/board-pcm037.h b/include/asm-arm/arch-mxc/board-pcm037.h
new file mode 100644
index 000000000000..82232ba3c8fc
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-pcm037.h
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2008 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
+#define __ASM_ARCH_MXC_BOARD_PCM037_H__
+
+/* mandatory for CONFIG_LL_DEBUG */
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+
+#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
diff --git a/include/asm-arm/arch-mxc/board-pcm038.h b/include/asm-arm/arch-mxc/board-pcm038.h
new file mode 100644
index 000000000000..750c62afd90f
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-pcm038.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
+#define __ASM_ARCH_MXC_BOARD_PCM038_H__
+
+/* mandatory for CONFIG_LL_DEBUG */
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
+
+#ifndef __ASSEMBLY__
+/*
+ * This CPU module needs a baseboard to work. After basic initializing
+ * its own devices, it calls baseboard's init function.
+ * TODO: Add your own baseboard init function and call it from
+ * inside pcm038_init().
+ *
+ * This example here is for the development board. Refer pcm970-baseboard.c
+ */
+
+extern void pcm970_baseboard_init(void);
+
+#endif
+
+#endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */
diff --git a/include/asm-arm/arch-mxc/clock.h b/include/asm-arm/arch-mxc/clock.h
new file mode 100644
index 000000000000..24caa2b7c91d
--- /dev/null
+++ b/include/asm-arm/arch-mxc/clock.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_CLOCK_H__
+#define __ASM_ARCH_MXC_CLOCK_H__
+
+#ifndef __ASSEMBLY__
+#include <linux/list.h>
+
+struct module;
+
+struct clk {
+        struct list_head node;
+        struct module *owner;
+        const char *name;
+        int id;
+        /* Source clock this clk depends on */
+        struct clk *parent;
+        /* Secondary clock to enable/disable with this clock */
+        struct clk *secondary;
+        /* Reference count of clock enable/disable */
+        __s8 usecount;
+        /* Register bit position for clock's enable/disable control. */
+        u8 enable_shift;
+        /* Register address for clock's enable/disable control. */
+        u32 enable_reg;
+        u32 flags;
+        /* get the current clock rate (always a fresh value) */
+        unsigned long (*get_rate) (struct clk *);
+        /* Function ptr to set the clock to a new rate. The rate must match a
+           supported rate returned from round_rate. Leave blank if clock is not
+           programmable */
+        int (*set_rate) (struct clk *, unsigned long);
+        /* Function ptr to round the requested clock rate to the nearest
+           supported rate that is less than or equal to the requested rate. */
+        unsigned long (*round_rate) (struct clk *, unsigned long);
+        /* Function ptr to enable the clock. Leave blank if clock can not
+           be gated. */
+        int (*enable) (struct clk *);
+        /* Function ptr to disable the clock. Leave blank if clock can not
+           be gated. */
+        void (*disable) (struct clk *);
+        /* Function ptr to set the parent clock of the clock. */
+        int (*set_parent) (struct clk *, struct clk *);
+};
+
+int clk_register(struct clk *clk);
+void clk_unregister(struct clk *clk);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/include/asm-arm/arch-mxc/common.h b/include/asm-arm/arch-mxc/common.h
index 23b4350edbd6..a6d2e24aab15 100644
--- a/include/asm-arm/arch-mxc/common.h
+++ b/include/asm-arm/arch-mxc/common.h
@@ -11,10 +11,10 @@
 #ifndef __ASM_ARCH_MXC_COMMON_H__
 #define __ASM_ARCH_MXC_COMMON_H__
 
-struct sys_timer;
-
 extern void mxc_map_io(void);
 extern void mxc_init_irq(void);
-extern struct sys_timer mxc_timer;
+extern void mxc_timer_init(const char *clk_timer);
+extern int mxc_clocks_init(unsigned long fref);
+extern int mxc_register_gpios(void);
 
 #endif
diff --git a/include/asm-arm/arch-mxc/debug-macro.S b/include/asm-arm/arch-mxc/debug-macro.S
new file mode 100644
index 000000000000..575087f8561a
--- /dev/null
+++ b/include/asm-arm/arch-mxc/debug-macro.S
@@ -0,0 +1,49 @@
+/* linux/include/asm-arm/arch-imx/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <asm/arch/hardware.h>
+
+#ifdef CONFIG_MACH_MX31ADS
+#include <asm/arch/board-mx31ads.h>
+#endif
+#ifdef CONFIG_MACH_PCM037
+#include <asm/arch/board-pcm037.h>
+#endif
+#ifdef CONFIG_MACH_MX31LITE
+#include <asm/arch/board-mx31lite.h>
+#endif
+#ifdef CONFIG_MACH_MX27ADS
+#include <asm/arch/board-mx27ads.h>
+#endif
+#ifdef CONFIG_MACH_PCM038
+#include <asm/arch/board-pcm038.h>
+#endif
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                ldreq   \rx, =MXC_LL_UART_PADDR @ physical
+                ldrne   \rx, =MXC_LL_UART_VADDR @ virtual
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x40]       @ TXDATA
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
+
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #0x98]       @ SR2
+                tst     \rd, #1 << 3            @ TXDC
+                beq     1002b                   @ wait until transmit done
+                .endm
diff --git a/include/asm-arm/arch-mxc/gpio.h b/include/asm-arm/arch-mxc/gpio.h
new file mode 100644
index 000000000000..d393e15f5a6b
--- /dev/null
+++ b/include/asm-arm/arch-mxc/gpio.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_GPIO_H__
+#define __ASM_ARCH_MXC_GPIO_H__
+
+#include <asm/hardware.h>
+#include <asm-generic/gpio.h>
+
+/* use gpiolib dispatchers */
+#define gpio_get_value          __gpio_get_value
+#define gpio_set_value          __gpio_set_value
+#define gpio_cansleep           __gpio_cansleep
+
+#define gpio_to_irq(gpio)       (MXC_MAX_INT_LINES + (gpio))
+#define irq_to_gpio(irq)        ((irq) - MXC_MAX_INT_LINES)
+
+struct mxc_gpio_port {
+        void __iomem *base;
+        int irq;
+        int virtual_irq_start;
+        struct gpio_chip chip;
+};
+
+int mxc_gpio_init(struct mxc_gpio_port*, int);
+
+#endif
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h
index e87ff0679d5e..37cddbaaade7 100644
--- a/include/asm-arm/arch-mxc/hardware.h
+++ b/include/asm-arm/arch-mxc/hardware.h
@@ -1,11 +1,20 @@
 /*
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
  */
 
 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
@@ -17,15 +26,12 @@
 # include <asm/arch/mx31.h>
 #endif
 
-#include <asm/arch/mxc.h>
-
-/*
- * ---------------------------------------------------------------------------
- * Board specific defines
- * ---------------------------------------------------------------------------
- */
-#ifdef CONFIG_MACH_MX31ADS
-# include <asm/arch/board-mx31ads.h>
+#ifdef CONFIG_ARCH_MX2
+# ifdef CONFIG_MACH_MX27
+#  include <asm/arch/mx27.h>
+# endif
 #endif
 
+#include <asm/arch/mxc.h>
+
 #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/iim.h b/include/asm-arm/arch-mxc/iim.h
new file mode 100644
index 000000000000..315bffadafda
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iim.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_IIM_H__
+#define __ASM_ARCH_MXC_IIM_H__
+
+/* Register offsets */
+#define MXC_IIMSTAT             0x0000
+#define MXC_IIMSTATM            0x0004
+#define MXC_IIMERR              0x0008
+#define MXC_IIMEMASK            0x000C
+#define MXC_IIMFCTL             0x0010
+#define MXC_IIMUA               0x0014
+#define MXC_IIMLA               0x0018
+#define MXC_IIMSDAT             0x001C
+#define MXC_IIMPREV             0x0020
+#define MXC_IIMSREV             0x0024
+#define MXC_IIMPRG_P            0x0028
+#define MXC_IIMSCS0             0x002C
+#define MXC_IIMSCS1             0x0030
+#define MXC_IIMSCS2             0x0034
+#define MXC_IIMSCS3             0x0038
+#define MXC_IIMFBAC0            0x0800
+#define MXC_IIMJAC              0x0804
+#define MXC_IIMHWV1             0x0808
+#define MXC_IIMHWV2             0x080C
+#define MXC_IIMHAB0             0x0810
+#define MXC_IIMHAB1             0x0814
+/* Definitions for i.MX27 TO2 */
+#define MXC_IIMMAC              0x0814
+#define MXC_IIMPREV_FUSE        0x0818
+#define MXC_IIMSREV_FUSE        0x081C
+#define MXC_IIMSJC_CHALL_0      0x0820
+#define MXC_IIMSJC_CHALL_7      0x083C
+#define MXC_IIMFB0UC17          0x0840
+#define MXC_IIMFB0UC255         0x0BFC
+#define MXC_IIMFBAC1            0x0C00
+/* Definitions for i.MX27 TO2 */
+#define MXC_IIMSUID             0x0C04
+#define MXC_IIMKEY0             0x0C04
+#define MXC_IIMKEY20            0x0C54
+#define MXC_IIMSJC_RESP_0       0x0C58
+#define MXC_IIMSJC_RESP_7       0x0C74
+#define MXC_IIMFB1UC30          0x0C78
+#define MXC_IIMFB1UC255         0x0FFC
+
+/* Bit definitions */
+
+#define MXC_IIMHWV1_WLOCK               (0x1 << 7)
+#define MXC_IIMHWV1_MCU_ENDIAN          (0x1 << 6)
+#define MXC_IIMHWV1_DSP_ENDIAN          (0x1 << 5)
+#define MXC_IIMHWV1_BOOT_INT            (0x1 << 4)
+#define MXC_IIMHWV1_SCC_DISABLE         (0x1 << 3)
+#define MXC_IIMHWV1_HANTRO_DISABLE      (0x1 << 2)
+#define MXC_IIMHWV1_MEMSTICK_DIS        (0x1 << 1)
+
+#define MXC_IIMHWV2_WLOCK               (0x1 << 7)
+#define MXC_IIMHWV2_BP_SDMA             (0x1 << 6)
+#define MXC_IIMHWV2_SCM_DCM             (0x1 << 5)
+
+#endif /* __ASM_ARCH_MXC_IIM_H__ */
diff --git a/include/asm-arm/arch-mxc/imx-uart.h b/include/asm-arm/arch-mxc/imx-uart.h
new file mode 100644
index 000000000000..83fb72c4048a
--- /dev/null
+++ b/include/asm-arm/arch-mxc/imx-uart.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef ASMARM_ARCH_UART_H
+#define ASMARM_ARCH_UART_H
+
+#define IMXUART_HAVE_RTSCTS (1<<0)
+
+struct imxuart_platform_data {
+        int (*init)(struct platform_device *pdev);
+        int (*exit)(struct platform_device *pdev);
+        unsigned int flags;
+};
+
+int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata);
+
+#endif
diff --git a/include/asm-arm/arch-mxc/iomux-mx1-mx2.h b/include/asm-arm/arch-mxc/iomux-mx1-mx2.h
new file mode 100644
index 000000000000..076d37b38eb2
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iomux-mx1-mx2.h
@@ -0,0 +1,372 @@
+/*
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef _MXC_GPIO_MX1_MX2_H
+#define _MXC_GPIO_MX1_MX2_H
+
+#include <linux/io.h>
+
+#define MXC_GPIO_ALLOC_MODE_NORMAL      0
+#define MXC_GPIO_ALLOC_MODE_NO_ALLOC    1
+#define MXC_GPIO_ALLOC_MODE_TRY_ALLOC   2
+#define MXC_GPIO_ALLOC_MODE_ALLOC_ONLY  4
+#define MXC_GPIO_ALLOC_MODE_RELEASE     8
+
+/*
+ *  GPIO Module and I/O Multiplexer
+ *  x = 0..3 for reg_A, reg_B, reg_C, reg_D
+ */
+#define VA_GPIO_BASE    IO_ADDRESS(GPIO_BASE_ADDR)
+#define MXC_DDIR(x)    (0x00 + ((x) << 8))
+#define MXC_OCR1(x)    (0x04 + ((x) << 8))
+#define MXC_OCR2(x)    (0x08 + ((x) << 8))
+#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
+#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
+#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
+#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
+#define MXC_DR(x)      (0x1c + ((x) << 8))
+#define MXC_GIUS(x)    (0x20 + ((x) << 8))
+#define MXC_SSR(x)     (0x24 + ((x) << 8))
+#define MXC_ICR1(x)    (0x28 + ((x) << 8))
+#define MXC_ICR2(x)    (0x2c + ((x) << 8))
+#define MXC_IMR(x)     (0x30 + ((x) << 8))
+#define MXC_ISR(x)     (0x34 + ((x) << 8))
+#define MXC_GPR(x)     (0x38 + ((x) << 8))
+#define MXC_SWR(x)     (0x3c + ((x) << 8))
+#define MXC_PUEN(x)    (0x40 + ((x) << 8))
+
+#ifdef CONFIG_ARCH_MX1
+# define GPIO_PORT_MAX  3
+#endif
+#ifdef CONFIG_ARCH_MX2
+# define GPIO_PORT_MAX  5
+#endif
+
+#ifndef GPIO_PORT_MAX
+# error "GPIO config port count unknown!"
+#endif
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
+
+#define GPIO_OUT   (1 << 8)
+#define GPIO_IN    (0 << 8)
+#define GPIO_PUEN  (1 << 9)
+
+#define GPIO_PF    (1 << 10)
+#define GPIO_AF    (1 << 11)
+
+#define GPIO_OCR_SHIFT 12
+#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
+#define GPIO_AIN   (0 << GPIO_OCR_SHIFT)
+#define GPIO_BIN   (1 << GPIO_OCR_SHIFT)
+#define GPIO_CIN   (2 << GPIO_OCR_SHIFT)
+#define GPIO_GPIO  (3 << GPIO_OCR_SHIFT)
+
+#define GPIO_AOUT_SHIFT 14
+#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT     (0 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_0   (2 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_1   (3 << GPIO_AOUT_SHIFT)
+
+#define GPIO_BOUT_SHIFT 16
+#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT      (0 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_ISR  (1 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_0    (2 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_1    (3 << GPIO_BOUT_SHIFT)
+
+extern void mxc_gpio_mode(int gpio_mode);
+extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
+                                        int alloc_mode, const char *label);
+
+/*-------------------------------------------------------------------------*/
+
+/* assignements for GPIO alternate/primary functions */
+
+/* FIXME: This list is not completed. The correct directions are
+ * missing on some (many) pins
+ */
+#ifdef CONFIG_ARCH_MX1
+#define PA0_AIN_SPI2_CLK     (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0)
+#define PA0_AF_ETMTRACESYNC  (GPIO_PORTA | GPIO_AF | 0)
+#define PA1_AOUT_SPI2_RXD    (GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1)
+#define PA1_PF_TIN           (GPIO_PORTA | GPIO_PF | 1)
+#define PA2_PF_PWM0          (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2)
+#define PA3_PF_CSI_MCLK      (GPIO_PORTA | GPIO_PF | 3)
+#define PA4_PF_CSI_D0        (GPIO_PORTA | GPIO_PF | 4)
+#define PA5_PF_CSI_D1        (GPIO_PORTA | GPIO_PF | 5)
+#define PA6_PF_CSI_D2        (GPIO_PORTA | GPIO_PF | 6)
+#define PA7_PF_CSI_D3        (GPIO_PORTA | GPIO_PF | 7)
+#define PA8_PF_CSI_D4        (GPIO_PORTA | GPIO_PF | 8)
+#define PA9_PF_CSI_D5        (GPIO_PORTA | GPIO_PF | 9)
+#define PA10_PF_CSI_D6       (GPIO_PORTA | GPIO_PF | 10)
+#define PA11_PF_CSI_D7       (GPIO_PORTA | GPIO_PF | 11)
+#define PA12_PF_CSI_VSYNC    (GPIO_PORTA | GPIO_PF | 12)
+#define PA13_PF_CSI_HSYNC    (GPIO_PORTA | GPIO_PF | 13)
+#define PA14_PF_CSI_PIXCLK   (GPIO_PORTA | GPIO_PF | 14)
+#define PA15_PF_I2C_SDA      (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
+#define PA16_PF_I2C_SCL      (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
+#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
+#define PA17_AIN_SPI2_SS     (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17)
+#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
+#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
+#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
+#define PA21_PF_A0           (GPIO_PORTA | GPIO_PF | 21)
+#define PA22_PF_CS4          (GPIO_PORTA | GPIO_PF | 22)
+#define PA23_PF_CS5          (GPIO_PORTA | GPIO_PF | 23)
+#define PA24_PF_A16          (GPIO_PORTA | GPIO_PF | 24)
+#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
+#define PA25_PF_A17          (GPIO_PORTA | GPIO_PF | 25)
+#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
+#define PA26_PF_A18          (GPIO_PORTA | GPIO_PF | 26)
+#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
+#define PA27_PF_A19          (GPIO_PORTA | GPIO_PF | 27)
+#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
+#define PA28_PF_A20          (GPIO_PORTA | GPIO_PF | 28)
+#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
+#define PA29_PF_A21          (GPIO_PORTA | GPIO_PF | 29)
+#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
+#define PA30_PF_A22          (GPIO_PORTA | GPIO_PF | 30)
+#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
+#define PA31_PF_A23          (GPIO_PORTA | GPIO_PF | 31)
+#define PA31_AF_ETMTRACECLK  (GPIO_PORTA | GPIO_AF | 31)
+#define PB8_PF_SD_DAT0       (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
+#define PB8_AF_MS_PIO        (GPIO_PORTB | GPIO_AF | 8)
+#define PB9_PF_SD_DAT1       (GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 9)
+#define PB9_AF_MS_PI1        (GPIO_PORTB | GPIO_AF | 9)
+#define PB10_PF_SD_DAT2      (GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 10)
+#define PB10_AF_MS_SCLKI     (GPIO_PORTB | GPIO_AF | 10)
+#define PB11_PF_SD_DAT3      (GPIO_PORTB | GPIO_PF | 11)
+#define PB11_AF_MS_SDIO      (GPIO_PORTB | GPIO_AF | 11)
+#define PB12_PF_SD_CLK       (GPIO_PORTB | GPIO_PF | 12)
+#define PB12_AF_MS_SCLK0     (GPIO_PORTB | GPIO_AF | 12)
+#define PB13_PF_SD_CMD       (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
+#define PB13_AF_MS_BS        (GPIO_PORTB | GPIO_AF | 13)
+#define PB14_AF_SSI_RXFS     (GPIO_PORTB | GPIO_AF | 14)
+#define PB15_AF_SSI_RXCLK    (GPIO_PORTB | GPIO_AF | 15)
+#define PB16_AF_SSI_RXDAT    (GPIO_PORTB | GPIO_IN | GPIO_AF | 16)
+#define PB17_AF_SSI_TXDAT    (GPIO_PORTB | GPIO_OUT | GPIO_AF | 17)
+#define PB18_AF_SSI_TXFS     (GPIO_PORTB | GPIO_AF | 18)
+#define PB19_AF_SSI_TXCLK    (GPIO_PORTB | GPIO_AF | 19)
+#define PB20_PF_USBD_AFE     (GPIO_PORTB | GPIO_PF | 20)
+#define PB21_PF_USBD_OE      (GPIO_PORTB | GPIO_PF | 21)
+#define PB22_PFUSBD_RCV      (GPIO_PORTB | GPIO_PF | 22)
+#define PB23_PF_USBD_SUSPND  (GPIO_PORTB | GPIO_PF | 23)
+#define PB24_PF_USBD_VP      (GPIO_PORTB | GPIO_PF | 24)
+#define PB25_PF_USBD_VM      (GPIO_PORTB | GPIO_PF | 25)
+#define PB26_PF_USBD_VPO     (GPIO_PORTB | GPIO_PF | 26)
+#define PB27_PF_USBD_VMO     (GPIO_PORTB | GPIO_PF | 27)
+#define PB28_PF_UART2_CTS    (GPIO_PORTB | GPIO_OUT | GPIO_PF | 28)
+#define PB29_PF_UART2_RTS    (GPIO_PORTB | GPIO_IN | GPIO_PF | 29)
+#define PB30_PF_UART2_TXD    (GPIO_PORTB | GPIO_OUT | GPIO_PF | 30)
+#define PB31_PF_UART2_RXD    (GPIO_PORTB | GPIO_IN | GPIO_PF | 31)
+#define PC3_PF_SSI_RXFS      (GPIO_PORTC | GPIO_PF | 3)
+#define PC4_PF_SSI_RXCLK     (GPIO_PORTC | GPIO_PF | 4)
+#define PC5_PF_SSI_RXDAT     (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
+#define PC6_PF_SSI_TXDAT     (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
+#define PC7_PF_SSI_TXFS      (GPIO_PORTC | GPIO_PF | 7)
+#define PC8_PF_SSI_TXCLK     (GPIO_PORTC | GPIO_PF | 8)
+#define PC9_PF_UART1_CTS     (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
+#define PC10_PF_UART1_RTS    (GPIO_PORTC | GPIO_IN | GPIO_PF | 10)
+#define PC11_PF_UART1_TXD    (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
+#define PC12_PF_UART1_RXD    (GPIO_PORTC | GPIO_IN | GPIO_PF | 12)
+#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
+#define PC14_PF_SPI1_SCLK    (GPIO_PORTC | GPIO_PF | 14)
+#define PC15_PF_SPI1_SS      (GPIO_PORTC | GPIO_PF | 15)
+#define PC16_PF_SPI1_MISO    (GPIO_PORTC | GPIO_PF | 16)
+#define PC17_PF_SPI1_MOSI    (GPIO_PORTC | GPIO_PF | 17)
+#define PC24_BIN_UART3_RI    (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24)
+#define PC25_BIN_UART3_DSR   (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25)
+#define PC26_AOUT_UART3_DTR  (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26)
+#define PC27_BIN_UART3_DCD   (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27)
+#define PC28_BIN_UART3_CTS   (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28)
+#define PC29_AOUT_UART3_RTS  (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29)
+#define PC30_BIN_UART3_TX    (GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30)
+#define PC31_AOUT_UART3_RX   (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
+#define PD6_PF_LSCLK         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6)
+#define PD7_PF_REV           (GPIO_PORTD | GPIO_PF | 7)
+#define PD7_AF_UART2_DTR     (GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7)
+#define PD7_AIN_SPI2_SCLK    (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7)
+#define PD8_PF_CLS           (GPIO_PORTD | GPIO_PF | 8)
+#define PD8_AF_UART2_DCD     (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8)
+#define PD8_AIN_SPI2_SS      (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8)
+#define PD9_PF_PS            (GPIO_PORTD | GPIO_PF | 9)
+#define PD9_AF_UART2_RI      (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9)
+#define PD9_AOUT_SPI2_RXD    (GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9)
+#define PD10_PF_SPL_SPR      (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10)
+#define PD10_AF_UART2_DSR    (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10)
+#define PD10_AIN_SPI2_TXD    (GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10)
+#define PD11_PF_CONTRAST     (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11)
+#define PD12_PF_ACD_OE       (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12)
+#define PD13_PF_LP_HSYNC     (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13)
+#define PD14_PF_FLM_VSYNC    (GPIO_PORTD | GPIO_OUT | GPIO_PF | 14)
+#define PD15_PF_LD0          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 15)
+#define PD16_PF_LD1          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 16)
+#define PD17_PF_LD2          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
+#define PD18_PF_LD3          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
+#define PD19_PF_LD4          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 19)
+#define PD20_PF_LD5          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 20)
+#define PD21_PF_LD6          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 21)
+#define PD22_PF_LD7          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 22)
+#define PD23_PF_LD8          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 23)
+#define PD24_PF_LD9          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 24)
+#define PD25_PF_LD10         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
+#define PD26_PF_LD11         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
+#define PD27_PF_LD12         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
+#define PD28_PF_LD13         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
+#define PD29_PF_LD14         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
+#define PD30_PF_LD15         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30)
+#define PD31_PF_TMR2OUT      (GPIO_PORTD | GPIO_PF | 31)
+#define PD31_BIN_SPI2_TXD    (GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31)
+#endif
+
+#ifdef CONFIG_ARCH_MX2
+#define PA5_PF_LSCLK            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5)
+#define PA6_PF_LD0              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6)
+#define PA7_PF_LD1              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7)
+#define PA8_PF_LD2              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 8)
+#define PA9_PF_LD3              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 9)
+#define PA10_PF_LD4             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 10)
+#define PA11_PF_LD5             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 11)
+#define PA12_PF_LD6             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 12)
+#define PA13_PF_LD7             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 13)
+#define PA14_PF_LD8             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 14)
+#define PA15_PF_LD9             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
+#define PA16_PF_LD10            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
+#define PA17_PF_LD11            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 17)
+#define PA18_PF_LD12            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 18)
+#define PA19_PF_LD13            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 19)
+#define PA20_PF_LD14            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 20)
+#define PA21_PF_LD15            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 21)
+#define PA22_PF_LD16            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 22)
+#define PA23_PF_LD17            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 23)
+#define PA24_PF_REV             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 24)
+#define PA25_PF_CLS             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 25)
+#define PA26_PF_PS              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 26)
+#define PA27_PF_SPL_SPR         (GPIO_PORTA | GPIO_OUT | GPIO_PF | 27)
+#define PA28_PF_HSYNC           (GPIO_PORTA | GPIO_OUT | GPIO_PF | 28)
+#define PA29_PF_VSYNC           (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29)
+#define PA30_PF_CONTRAST        (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30)
+#define PA31_PF_OE_ACD          (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31)
+#define PB10_PF_CSI_D0          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10)
+#define PB10_AF_UART6_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10)
+#define PB11_PF_CSI_D1          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11)
+#define PB11_AF_UART6_RXD       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 11)
+#define PB12_PF_CSI_D2          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 12)
+#define PB12_AF_UART6_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 12)
+#define PB13_PF_CSI_D3          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 13)
+#define PB13_AF_UART6_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 13)
+#define PB14_PF_CSI_D4          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 14)
+#define PB15_PF_CSI_MCLK        (GPIO_PORTB | GPIO_OUT | GPIO_PF | 15)
+#define PB16_PF_CSI_PIXCLK      (GPIO_PORTB | GPIO_OUT | GPIO_PF | 16)
+#define PB17_PF_CSI_D5          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 17)
+#define PB18_PF_CSI_D6          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 18)
+#define PB18_AF_UART5_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 18)
+#define PB19_PF_CSI_D7          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 19)
+#define PB19_AF_UART5_RXD       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 19)
+#define PB20_PF_CSI_VSYNC       (GPIO_PORTB | GPIO_OUT | GPIO_PF | 20)
+#define PB20_AF_UART5_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20)
+#define PB21_PF_CSI_HSYNC       (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21)
+#define PB21_AF_UART5_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 21)
+#define PB26_AF_UART4_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_PF | 26)
+#define PB28_AF_UART4_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28)
+#define PB29_AF_UART4_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29)
+#define PB31_AF_UART4_RXD       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 31)
+#define PC5_PF_I2C2_SDA         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 5)
+#define PC6_PF_I2C2_SCL         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 6)
+#define PC16_PF_SSI4_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 16)
+#define PC17_PF_SSI4_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 17)
+#define PC18_PF_SSI4_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 18)
+#define PC19_PF_SSI4_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 19)
+#define PC20_PF_SSI1_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 20)
+#define PC21_PF_SSI1_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 21)
+#define PC22_PF_SSI1_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 22)
+#define PC23_PF_SSI1_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 23)
+#define PC24_PF_SSI2_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 24)
+#define PC25_PF_SSI2_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 25)
+#define PC26_PF_SSI2_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 26)
+#define PC27_PF_SSI2_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 27)
+#define PC28_PF_SSI3_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 28)
+#define PC29_PF_SSI3_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 29)
+#define PC30_PF_SSI3_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 30)
+#define PC31_PF_SSI3_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 31)
+#define PD0_AIN_FEC_TXD0        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
+#define PD1_AIN_FEC_TXD1        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
+#define PD2_AIN_FEC_TXD2        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
+#define PD3_AIN_FEC_TXD3        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
+#define PD4_AOUT_FEC_RX_ER      (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
+#define PD5_AOUT_FEC_RXD1       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
+#define PD6_AOUT_FEC_RXD2       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
+#define PD7_AOUT_FEC_RXD3       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
+#define PD8_AF_FEC_MDIO         (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
+#define PD9_AIN_FEC_MDC         (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
+#define PD10_AOUT_FEC_CRS       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
+#define PD11_AOUT_FEC_TX_CLK    (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
+#define PD12_AOUT_FEC_RXD0      (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
+#define PD13_AOUT_FEC_RX_DV     (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
+#define PD14_AOUT_FEC_CLR       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
+#define PD15_AOUT_FEC_COL       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
+#define PD16_AIN_FEC_TX_ER      (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
+#define PD17_PF_I2C_DATA        (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
+#define PD18_PF_I2C_CLK         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
+#define PD25_PF_CSPI1_RDY       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 25)
+#define PD26_PF_CSPI1_SS2       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 26)
+#define PD27_PF_CSPI1_SS1       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 27)
+#define PD28_PF_CSPI1_SS0       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 28)
+#define PD29_PF_CSPI1_SCLK      (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 29)
+#define PD30_PF_CSPI1_MISO      (GPIO_PORTD | GPIO_IN | GPIO_PF  | 30)
+#define PD31_PF_CSPI1_MOSI      (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 31)
+#define PF23_AIN_FEC_TX_EN      (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
+#define PE3_PF_UART2_CTS        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
+#define PE4_PF_UART2_RTS        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 4)
+#define PE6_PF_UART2_TXD        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
+#define PE7_PF_UART2_RXD        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 7)
+#define PE8_PF_UART3_TXD        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
+#define PE9_PF_UART3_RXD        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 9)
+#define PE10_PF_UART3_CTS       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
+#define PE11_PF_UART3_RTS       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 11)
+#define PE12_PF_UART1_TXD       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
+#define PE13_PF_UART1_RXD       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 13)
+#define PE14_PF_UART1_CTS       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
+#define PE15_PF_UART1_RTS       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 15)
+#define PE18_AF_CSPI3_MISO      (GPIO_PORTE | GPIO_IN  | GPIO_AF | 18)
+#define PE21_AF_CSPI3_SS        (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21)
+#define PE22_AF_CSPI3_MOSI      (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22)
+#define PE23_AF_CSPI3_SCLK      (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23)
+#endif
+
+/* decode irq number to use with IMR(x), ISR(x) and friends */
+#define IRQ_TO_REG(irq) ((irq - MXC_MAX_INT_LINES) >> 5)
+
+#define IRQ_GPIOA(x)  (MXC_MAX_INT_LINES + x)
+#define IRQ_GPIOB(x)  (IRQ_GPIOA(32) + x)
+#define IRQ_GPIOC(x)  (IRQ_GPIOB(32) + x)
+#define IRQ_GPIOD(x)  (IRQ_GPIOC(32) + x)
+
+#endif /* _MXC_GPIO_MX1_MX2_H */
diff --git a/include/asm-arm/arch-mxc/iomux-mx3.h b/include/asm-arm/arch-mxc/iomux-mx3.h
new file mode 100644
index 000000000000..7509e7692f08
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iomux-mx3.h
@@ -0,0 +1,501 @@
+/*
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __MACH_MX31_IOMUX_H__
+#define __MACH_MX31_IOMUX_H__
+
+#include <linux/types.h>
+
+/*
+ * various IOMUX output functions
+ */
+
+#define IOMUX_OCONFIG_GPIO (0 << 4)     /* used as GPIO */
+#define IOMUX_OCONFIG_FUNC (1 << 4)     /* used as function */
+#define IOMUX_OCONFIG_ALT1 (2 << 4)     /* used as alternate function 1 */
+#define IOMUX_OCONFIG_ALT2 (3 << 4)     /* used as alternate function 2 */
+#define IOMUX_OCONFIG_ALT3 (4 << 4)     /* used as alternate function 3 */
+#define IOMUX_OCONFIG_ALT4 (5 << 4)     /* used as alternate function 4 */
+#define IOMUX_OCONFIG_ALT5 (6 << 4)     /* used as alternate function 5 */
+#define IOMUX_OCONFIG_ALT6 (7 << 4)     /* used as alternate function 6 */
+#define IOMUX_ICONFIG_NONE  0           /* not configured for input */
+#define IOMUX_ICONFIG_GPIO  1           /* used as GPIO */
+#define IOMUX_ICONFIG_FUNC  2           /* used as function */
+#define IOMUX_ICONFIG_ALT1  4           /* used as alternate function 1 */
+#define IOMUX_ICONFIG_ALT2  8           /* used as alternate function 2 */
+
+#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
+#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
+#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
+#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
+
+/*
+ * various IOMUX pad functions
+ */
+enum iomux_pad_config {
+        PAD_CTL_NOLOOPBACK      = 0x0 << 9,
+        PAD_CTL_LOOPBACK        = 0x1 << 9,
+        PAD_CTL_PKE_NONE        = 0x0 << 8,
+        PAD_CTL_PKE_ENABLE      = 0x1 << 8,
+        PAD_CTL_PUE_KEEPER      = 0x0 << 7,
+        PAD_CTL_PUE_PUD         = 0x1 << 7,
+        PAD_CTL_100K_PD         = 0x0 << 5,
+        PAD_CTL_100K_PU         = 0x1 << 5,
+        PAD_CTL_47K_PU          = 0x2 << 5,
+        PAD_CTL_22K_PU          = 0x3 << 5,
+        PAD_CTL_HYS_CMOS        = 0x0 << 4,
+        PAD_CTL_HYS_SCHMITZ     = 0x1 << 4,
+        PAD_CTL_ODE_CMOS        = 0x0 << 3,
+        PAD_CTL_ODE_OpenDrain   = 0x1 << 3,
+        PAD_CTL_DRV_NORMAL      = 0x0 << 1,
+        PAD_CTL_DRV_HIGH        = 0x1 << 1,
+        PAD_CTL_DRV_MAX         = 0x2 << 1,
+        PAD_CTL_SRE_SLOW        = 0x0 << 0,
+        PAD_CTL_SRE_FAST        = 0x1 << 0
+};
+
+/*
+ * various IOMUX general purpose functions
+ */
+enum iomux_gp_func {
+        MUX_PGP_FIRI                    = 1 << 0,
+        MUX_DDR_MODE                    = 1 << 1,
+        MUX_PGP_CSPI_BB                 = 1 << 2,
+        MUX_PGP_ATA_1                   = 1 << 3,
+        MUX_PGP_ATA_2                   = 1 << 4,
+        MUX_PGP_ATA_3                   = 1 << 5,
+        MUX_PGP_ATA_4                   = 1 << 6,
+        MUX_PGP_ATA_5                   = 1 << 7,
+        MUX_PGP_ATA_6                   = 1 << 8,
+        MUX_PGP_ATA_7                   = 1 << 9,
+        MUX_PGP_ATA_8                   = 1 << 10,
+        MUX_PGP_UH2                     = 1 << 11,
+        MUX_SDCTL_CSD0_SEL              = 1 << 12,
+        MUX_SDCTL_CSD1_SEL              = 1 << 13,
+        MUX_CSPI1_UART3                 = 1 << 14,
+        MUX_EXTDMAREQ2_MBX_SEL          = 1 << 15,
+        MUX_TAMPER_DETECT_EN            = 1 << 16,
+        MUX_PGP_USB_4WIRE               = 1 << 17,
+        MUX_PGB_USB_COMMON              = 1 << 18,
+        MUX_SDHC_MEMSTICK1              = 1 << 19,
+        MUX_SDHC_MEMSTICK2              = 1 << 20,
+        MUX_PGP_SPLL_BYP                = 1 << 21,
+        MUX_PGP_UPLL_BYP                = 1 << 22,
+        MUX_PGP_MSHC1_CLK_SEL           = 1 << 23,
+        MUX_PGP_MSHC2_CLK_SEL           = 1 << 24,
+        MUX_CSPI3_UART5_SEL             = 1 << 25,
+        MUX_PGP_ATA_9                   = 1 << 26,
+        MUX_PGP_USB_SUSPEND             = 1 << 27,
+        MUX_PGP_USB_OTG_LOOPBACK        = 1 << 28,
+        MUX_PGP_USB_HS1_LOOPBACK        = 1 << 29,
+        MUX_PGP_USB_HS2_LOOPBACK        = 1 << 30,
+        MUX_CLKO_DDR_MODE               = 1 << 31,
+};
+
+/*
+ * This function enables/disables the general purpose function for a particular
+ * signal.
+ */
+void iomux_config_gpr(enum iomux_gp_func , bool);
+
+/*
+ * set the mode for a IOMUX pin.
+ */
+int mxc_iomux_mode(unsigned int);
+
+/*
+ * This function enables/disables the general purpose function for a particular
+ * signal.
+ */
+void mxc_iomux_set_gpr(enum iomux_gp_func, bool);
+
+#define IOMUX_PADNUM_MASK       0x1ff
+#define IOMUX_GPIONUM_SHIFT     9
+#define IOMUX_GPIONUM_MASK      (0xff << IOMUX_GPIONUM_SHIFT)
+#define IOMUX_MODE_SHIFT        17
+#define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT)
+
+#define IOMUX_PIN(gpionum, padnum) \
+        (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \
+         (padnum & IOMUX_PADNUM_MASK))
+
+#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT)
+
+#define IOMUX_TO_GPIO(iomux_pin) \
+        ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
+#define IOMUX_TO_IRQ(iomux_pin) \
+        (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
+        MXC_GPIO_INT_BASE)
+
+/*
+ * This enumeration is constructed based on the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
+ * value is constructed based on the rules described above.
+ */
+
+enum iomux_pins {
+        MX31_PIN_TTM_PAD        = IOMUX_PIN(0xff,   0),
+        MX31_PIN_CSPI3_SPI_RDY  = IOMUX_PIN(0xff,   1),
+        MX31_PIN_CSPI3_SCLK     = IOMUX_PIN(0xff,   2),
+        MX31_PIN_CSPI3_MISO     = IOMUX_PIN(0xff,   3),
+        MX31_PIN_CSPI3_MOSI     = IOMUX_PIN(0xff,   4),
+        MX31_PIN_CLKSS          = IOMUX_PIN(0xff,   5),
+        MX31_PIN_CE_CONTROL     = IOMUX_PIN(0xff,   6),
+        MX31_PIN_ATA_RESET_B    = IOMUX_PIN(95,     7),
+        MX31_PIN_ATA_DMACK      = IOMUX_PIN(94,     8),
+        MX31_PIN_ATA_DIOW       = IOMUX_PIN(93,     9),
+        MX31_PIN_ATA_DIOR       = IOMUX_PIN(92,    10),
+        MX31_PIN_ATA_CS1        = IOMUX_PIN(91,    11),
+        MX31_PIN_ATA_CS0        = IOMUX_PIN(90,    12),
+        MX31_PIN_SD1_DATA3      = IOMUX_PIN(63,    13),
+        MX31_PIN_SD1_DATA2      = IOMUX_PIN(62,    14),
+        MX31_PIN_SD1_DATA1      = IOMUX_PIN(61,    15),
+        MX31_PIN_SD1_DATA0      = IOMUX_PIN(60,    16),
+        MX31_PIN_SD1_CLK        = IOMUX_PIN(59,    17),
+        MX31_PIN_SD1_CMD        = IOMUX_PIN(58,    18),
+        MX31_PIN_D3_SPL         = IOMUX_PIN(0xff,  19),
+        MX31_PIN_D3_CLS         = IOMUX_PIN(0xff,  20),
+        MX31_PIN_D3_REV         = IOMUX_PIN(0xff,  21),
+        MX31_PIN_CONTRAST       = IOMUX_PIN(0xff,  22),
+        MX31_PIN_VSYNC3         = IOMUX_PIN(0xff,  23),
+        MX31_PIN_READ           = IOMUX_PIN(0xff,  24),
+        MX31_PIN_WRITE          = IOMUX_PIN(0xff,  25),
+        MX31_PIN_PAR_RS         = IOMUX_PIN(0xff,  26),
+        MX31_PIN_SER_RS         = IOMUX_PIN(89,    27),
+        MX31_PIN_LCS1           = IOMUX_PIN(88,    28),
+        MX31_PIN_LCS0           = IOMUX_PIN(87,    29),
+        MX31_PIN_SD_D_CLK       = IOMUX_PIN(86,    30),
+        MX31_PIN_SD_D_IO        = IOMUX_PIN(85,    31),
+        MX31_PIN_SD_D_I         = IOMUX_PIN(84,    32),
+        MX31_PIN_DRDY0          = IOMUX_PIN(0xff,  33),
+        MX31_PIN_FPSHIFT        = IOMUX_PIN(0xff,  34),
+        MX31_PIN_HSYNC          = IOMUX_PIN(0xff,  35),
+        MX31_PIN_VSYNC0         = IOMUX_PIN(0xff,  36),
+        MX31_PIN_LD17           = IOMUX_PIN(0xff,  37),
+        MX31_PIN_LD16           = IOMUX_PIN(0xff,  38),
+        MX31_PIN_LD15           = IOMUX_PIN(0xff,  39),
+        MX31_PIN_LD14           = IOMUX_PIN(0xff,  40),
+        MX31_PIN_LD13           = IOMUX_PIN(0xff,  41),
+        MX31_PIN_LD12           = IOMUX_PIN(0xff,  42),
+        MX31_PIN_LD11           = IOMUX_PIN(0xff,  43),
+        MX31_PIN_LD10           = IOMUX_PIN(0xff,  44),
+        MX31_PIN_LD9            = IOMUX_PIN(0xff,  45),
+        MX31_PIN_LD8            = IOMUX_PIN(0xff,  46),
+        MX31_PIN_LD7            = IOMUX_PIN(0xff,  47),
+        MX31_PIN_LD6            = IOMUX_PIN(0xff,  48),
+        MX31_PIN_LD5            = IOMUX_PIN(0xff,  49),
+        MX31_PIN_LD4            = IOMUX_PIN(0xff,  50),
+        MX31_PIN_LD3            = IOMUX_PIN(0xff,  51),
+        MX31_PIN_LD2            = IOMUX_PIN(0xff,  52),
+        MX31_PIN_LD1            = IOMUX_PIN(0xff,  53),
+        MX31_PIN_LD0            = IOMUX_PIN(0xff,  54),
+        MX31_PIN_USBH2_DATA1    = IOMUX_PIN(0xff,  55),
+        MX31_PIN_USBH2_DATA0    = IOMUX_PIN(0xff,  56),
+        MX31_PIN_USBH2_NXT      = IOMUX_PIN(0xff,  57),
+        MX31_PIN_USBH2_STP      = IOMUX_PIN(0xff,  58),
+        MX31_PIN_USBH2_DIR      = IOMUX_PIN(0xff,  59),
+        MX31_PIN_USBH2_CLK      = IOMUX_PIN(0xff,  60),
+        MX31_PIN_USBOTG_DATA7   = IOMUX_PIN(0xff,  61),
+        MX31_PIN_USBOTG_DATA6   = IOMUX_PIN(0xff,  62),
+        MX31_PIN_USBOTG_DATA5   = IOMUX_PIN(0xff,  63),
+        MX31_PIN_USBOTG_DATA4   = IOMUX_PIN(0xff,  64),
+        MX31_PIN_USBOTG_DATA3   = IOMUX_PIN(0xff,  65),
+        MX31_PIN_USBOTG_DATA2   = IOMUX_PIN(0xff,  66),
+        MX31_PIN_USBOTG_DATA1   = IOMUX_PIN(0xff,  67),
+        MX31_PIN_USBOTG_DATA0   = IOMUX_PIN(0xff,  68),
+        MX31_PIN_USBOTG_NXT     = IOMUX_PIN(0xff,  69),
+        MX31_PIN_USBOTG_STP     = IOMUX_PIN(0xff,  70),
+        MX31_PIN_USBOTG_DIR     = IOMUX_PIN(0xff,  71),
+        MX31_PIN_USBOTG_CLK     = IOMUX_PIN(0xff,  72),
+        MX31_PIN_USB_BYP        = IOMUX_PIN(31,    73),
+        MX31_PIN_USB_OC         = IOMUX_PIN(30,    74),
+        MX31_PIN_USB_PWR        = IOMUX_PIN(29,    75),
+        MX31_PIN_SJC_MOD        = IOMUX_PIN(0xff,  76),
+        MX31_PIN_DE_B           = IOMUX_PIN(0xff,  77),
+        MX31_PIN_TRSTB          = IOMUX_PIN(0xff,  78),
+        MX31_PIN_TDO            = IOMUX_PIN(0xff,  79),
+        MX31_PIN_TDI            = IOMUX_PIN(0xff,  80),
+        MX31_PIN_TMS            = IOMUX_PIN(0xff,  81),
+        MX31_PIN_TCK            = IOMUX_PIN(0xff,  82),
+        MX31_PIN_RTCK           = IOMUX_PIN(0xff,  83),
+        MX31_PIN_KEY_COL7       = IOMUX_PIN(57,    84),
+        MX31_PIN_KEY_COL6       = IOMUX_PIN(56,    85),
+        MX31_PIN_KEY_COL5       = IOMUX_PIN(55,    86),
+        MX31_PIN_KEY_COL4       = IOMUX_PIN(54,    87),
+        MX31_PIN_KEY_COL3       = IOMUX_PIN(0xff,  88),
+        MX31_PIN_KEY_COL2       = IOMUX_PIN(0xff,  89),
+        MX31_PIN_KEY_COL1       = IOMUX_PIN(0xff,  90),
+        MX31_PIN_KEY_COL0       = IOMUX_PIN(0xff,  91),
+        MX31_PIN_KEY_ROW7       = IOMUX_PIN(53,    92),
+        MX31_PIN_KEY_ROW6       = IOMUX_PIN(52,    93),
+        MX31_PIN_KEY_ROW5       = IOMUX_PIN(51,    94),
+        MX31_PIN_KEY_ROW4       = IOMUX_PIN(50,    95),
+        MX31_PIN_KEY_ROW3       = IOMUX_PIN(0xff,  96),
+        MX31_PIN_KEY_ROW2       = IOMUX_PIN(0xff,  97),
+        MX31_PIN_KEY_ROW1       = IOMUX_PIN(0xff,  98),
+        MX31_PIN_KEY_ROW0       = IOMUX_PIN(0xff,  99),
+        MX31_PIN_BATT_LINE      = IOMUX_PIN(49,   100),
+        MX31_PIN_CTS2           = IOMUX_PIN(0xff, 101),
+        MX31_PIN_RTS2           = IOMUX_PIN(0xff, 102),
+        MX31_PIN_TXD2           = IOMUX_PIN(28,   103),
+        MX31_PIN_RXD2           = IOMUX_PIN(27,   104),
+        MX31_PIN_DTR_DCE2       = IOMUX_PIN(48,   105),
+        MX31_PIN_DCD_DTE1       = IOMUX_PIN(47,   106),
+        MX31_PIN_RI_DTE1        = IOMUX_PIN(46,   107),
+        MX31_PIN_DSR_DTE1       = IOMUX_PIN(45,   108),
+        MX31_PIN_DTR_DTE1       = IOMUX_PIN(44,   109),
+        MX31_PIN_DCD_DCE1       = IOMUX_PIN(43,   110),
+        MX31_PIN_RI_DCE1        = IOMUX_PIN(42,   111),
+        MX31_PIN_DSR_DCE1       = IOMUX_PIN(41,   112),
+        MX31_PIN_DTR_DCE1       = IOMUX_PIN(40,   113),
+        MX31_PIN_CTS1           = IOMUX_PIN(39,   114),
+        MX31_PIN_RTS1           = IOMUX_PIN(38,   115),
+        MX31_PIN_TXD1           = IOMUX_PIN(37,   116),
+        MX31_PIN_RXD1           = IOMUX_PIN(36,   117),
+        MX31_PIN_CSPI2_SPI_RDY  = IOMUX_PIN(0xff, 118),
+        MX31_PIN_CSPI2_SCLK     = IOMUX_PIN(0xff, 119),
+        MX31_PIN_CSPI2_SS2      = IOMUX_PIN(0xff, 120),
+        MX31_PIN_CSPI2_SS1      = IOMUX_PIN(0xff, 121),
+        MX31_PIN_CSPI2_SS0      = IOMUX_PIN(0xff, 122),
+        MX31_PIN_CSPI2_MISO     = IOMUX_PIN(0xff, 123),
+        MX31_PIN_CSPI2_MOSI     = IOMUX_PIN(0xff, 124),
+        MX31_PIN_CSPI1_SPI_RDY  = IOMUX_PIN(0xff, 125),
+        MX31_PIN_CSPI1_SCLK     = IOMUX_PIN(0xff, 126),
+        MX31_PIN_CSPI1_SS2      = IOMUX_PIN(0xff, 127),
+        MX31_PIN_CSPI1_SS1      = IOMUX_PIN(0xff, 128),
+        MX31_PIN_CSPI1_SS0      = IOMUX_PIN(0xff, 129),
+        MX31_PIN_CSPI1_MISO     = IOMUX_PIN(0xff, 130),
+        MX31_PIN_CSPI1_MOSI     = IOMUX_PIN(0xff, 131),
+        MX31_PIN_SFS6           = IOMUX_PIN(26,   132),
+        MX31_PIN_SCK6           = IOMUX_PIN(25,   133),
+        MX31_PIN_SRXD6          = IOMUX_PIN(24,   134),
+        MX31_PIN_STXD6          = IOMUX_PIN(23,   135),
+        MX31_PIN_SFS5           = IOMUX_PIN(0xff, 136),
+        MX31_PIN_SCK5           = IOMUX_PIN(0xff, 137),
+        MX31_PIN_SRXD5          = IOMUX_PIN(22,   138),
+        MX31_PIN_STXD5          = IOMUX_PIN(21,   139),
+        MX31_PIN_SFS4           = IOMUX_PIN(0xff, 140),
+        MX31_PIN_SCK4           = IOMUX_PIN(0xff, 141),
+        MX31_PIN_SRXD4          = IOMUX_PIN(20,   142),
+        MX31_PIN_STXD4          = IOMUX_PIN(19,   143),
+        MX31_PIN_SFS3           = IOMUX_PIN(0xff, 144),
+        MX31_PIN_SCK3           = IOMUX_PIN(0xff, 145),
+        MX31_PIN_SRXD3          = IOMUX_PIN(18,   146),
+        MX31_PIN_STXD3          = IOMUX_PIN(17,   147),
+        MX31_PIN_I2C_DAT        = IOMUX_PIN(0xff, 148),
+        MX31_PIN_I2C_CLK        = IOMUX_PIN(0xff, 149),
+        MX31_PIN_CSI_PIXCLK     = IOMUX_PIN(83,   150),
+        MX31_PIN_CSI_HSYNC      = IOMUX_PIN(82,   151),
+        MX31_PIN_CSI_VSYNC      = IOMUX_PIN(81,   152),
+        MX31_PIN_CSI_MCLK       = IOMUX_PIN(80,   153),
+        MX31_PIN_CSI_D15        = IOMUX_PIN(79,   154),
+        MX31_PIN_CSI_D14        = IOMUX_PIN(78,   155),
+        MX31_PIN_CSI_D13        = IOMUX_PIN(77,   156),
+        MX31_PIN_CSI_D12        = IOMUX_PIN(76,   157),
+        MX31_PIN_CSI_D11        = IOMUX_PIN(75,   158),
+        MX31_PIN_CSI_D10        = IOMUX_PIN(74,   159),
+        MX31_PIN_CSI_D9         = IOMUX_PIN(73,   160),
+        MX31_PIN_CSI_D8         = IOMUX_PIN(72,   161),
+        MX31_PIN_CSI_D7         = IOMUX_PIN(71,   162),
+        MX31_PIN_CSI_D6         = IOMUX_PIN(70,   163),
+        MX31_PIN_CSI_D5         = IOMUX_PIN(69,   164),
+        MX31_PIN_CSI_D4         = IOMUX_PIN(68,   165),
+        MX31_PIN_M_GRANT        = IOMUX_PIN(0xff, 166),
+        MX31_PIN_M_REQUEST      = IOMUX_PIN(0xff, 167),
+        MX31_PIN_PC_POE         = IOMUX_PIN(0xff, 168),
+        MX31_PIN_PC_RW_B        = IOMUX_PIN(0xff, 169),
+        MX31_PIN_IOIS16         = IOMUX_PIN(0xff, 170),
+        MX31_PIN_PC_RST         = IOMUX_PIN(0xff, 171),
+        MX31_PIN_PC_BVD2        = IOMUX_PIN(0xff, 172),
+        MX31_PIN_PC_BVD1        = IOMUX_PIN(0xff, 173),
+        MX31_PIN_PC_VS2         = IOMUX_PIN(0xff, 174),
+        MX31_PIN_PC_VS1         = IOMUX_PIN(0xff, 175),
+        MX31_PIN_PC_PWRON       = IOMUX_PIN(0xff, 176),
+        MX31_PIN_PC_READY       = IOMUX_PIN(0xff, 177),
+        MX31_PIN_PC_WAIT_B      = IOMUX_PIN(0xff, 178),
+        MX31_PIN_PC_CD2_B       = IOMUX_PIN(0xff, 179),
+        MX31_PIN_PC_CD1_B       = IOMUX_PIN(0xff, 180),
+        MX31_PIN_D0             = IOMUX_PIN(0xff, 181),
+        MX31_PIN_D1             = IOMUX_PIN(0xff, 182),
+        MX31_PIN_D2             = IOMUX_PIN(0xff, 183),
+        MX31_PIN_D3             = IOMUX_PIN(0xff, 184),
+        MX31_PIN_D4             = IOMUX_PIN(0xff, 185),
+        MX31_PIN_D5             = IOMUX_PIN(0xff, 186),
+        MX31_PIN_D6             = IOMUX_PIN(0xff, 187),
+        MX31_PIN_D7             = IOMUX_PIN(0xff, 188),
+        MX31_PIN_D8             = IOMUX_PIN(0xff, 189),
+        MX31_PIN_D9             = IOMUX_PIN(0xff, 190),
+        MX31_PIN_D10            = IOMUX_PIN(0xff, 191),
+        MX31_PIN_D11            = IOMUX_PIN(0xff, 192),
+        MX31_PIN_D12            = IOMUX_PIN(0xff, 193),
+        MX31_PIN_D13            = IOMUX_PIN(0xff, 194),
+        MX31_PIN_D14            = IOMUX_PIN(0xff, 195),
+        MX31_PIN_D15            = IOMUX_PIN(0xff, 196),
+        MX31_PIN_NFRB           = IOMUX_PIN(16,   197),
+        MX31_PIN_NFCE_B         = IOMUX_PIN(15,   198),
+        MX31_PIN_NFWP_B         = IOMUX_PIN(14,   199),
+        MX31_PIN_NFCLE          = IOMUX_PIN(13,   200),
+        MX31_PIN_NFALE          = IOMUX_PIN(12,   201),
+        MX31_PIN_NFRE_B         = IOMUX_PIN(11,   202),
+        MX31_PIN_NFWE_B         = IOMUX_PIN(10,   203),
+        MX31_PIN_SDQS3          = IOMUX_PIN(0xff, 204),
+        MX31_PIN_SDQS2          = IOMUX_PIN(0xff, 205),
+        MX31_PIN_SDQS1          = IOMUX_PIN(0xff, 206),
+        MX31_PIN_SDQS0          = IOMUX_PIN(0xff, 207),
+        MX31_PIN_SDCLK_B        = IOMUX_PIN(0xff, 208),
+        MX31_PIN_SDCLK          = IOMUX_PIN(0xff, 209),
+        MX31_PIN_SDCKE1         = IOMUX_PIN(0xff, 210),
+        MX31_PIN_SDCKE0         = IOMUX_PIN(0xff, 211),
+        MX31_PIN_SDWE           = IOMUX_PIN(0xff, 212),
+        MX31_PIN_CAS            = IOMUX_PIN(0xff, 213),
+        MX31_PIN_RAS            = IOMUX_PIN(0xff, 214),
+        MX31_PIN_RW             = IOMUX_PIN(0xff, 215),
+        MX31_PIN_BCLK           = IOMUX_PIN(0xff, 216),
+        MX31_PIN_LBA            = IOMUX_PIN(0xff, 217),
+        MX31_PIN_ECB            = IOMUX_PIN(0xff, 218),
+        MX31_PIN_CS5            = IOMUX_PIN(0xff, 219),
+        MX31_PIN_CS4            = IOMUX_PIN(0xff, 220),
+        MX31_PIN_CS3            = IOMUX_PIN(0xff, 221),
+        MX31_PIN_CS2            = IOMUX_PIN(0xff, 222),
+        MX31_PIN_CS1            = IOMUX_PIN(0xff, 223),
+        MX31_PIN_CS0            = IOMUX_PIN(0xff, 224),
+        MX31_PIN_OE             = IOMUX_PIN(0xff, 225),
+        MX31_PIN_EB1            = IOMUX_PIN(0xff, 226),
+        MX31_PIN_EB0            = IOMUX_PIN(0xff, 227),
+        MX31_PIN_DQM3           = IOMUX_PIN(0xff, 228),
+        MX31_PIN_DQM2           = IOMUX_PIN(0xff, 229),
+        MX31_PIN_DQM1           = IOMUX_PIN(0xff, 230),
+        MX31_PIN_DQM0           = IOMUX_PIN(0xff, 231),
+        MX31_PIN_SD31           = IOMUX_PIN(0xff, 232),
+        MX31_PIN_SD30           = IOMUX_PIN(0xff, 233),
+        MX31_PIN_SD29           = IOMUX_PIN(0xff, 234),
+        MX31_PIN_SD28           = IOMUX_PIN(0xff, 235),
+        MX31_PIN_SD27           = IOMUX_PIN(0xff, 236),
+        MX31_PIN_SD26           = IOMUX_PIN(0xff, 237),
+        MX31_PIN_SD25           = IOMUX_PIN(0xff, 238),
+        MX31_PIN_SD24           = IOMUX_PIN(0xff, 239),
+        MX31_PIN_SD23           = IOMUX_PIN(0xff, 240),
+        MX31_PIN_SD22           = IOMUX_PIN(0xff, 241),
+        MX31_PIN_SD21           = IOMUX_PIN(0xff, 242),
+        MX31_PIN_SD20           = IOMUX_PIN(0xff, 243),
+        MX31_PIN_SD19           = IOMUX_PIN(0xff, 244),
+        MX31_PIN_SD18           = IOMUX_PIN(0xff, 245),
+        MX31_PIN_SD17           = IOMUX_PIN(0xff, 246),
+        MX31_PIN_SD16           = IOMUX_PIN(0xff, 247),
+        MX31_PIN_SD15           = IOMUX_PIN(0xff, 248),
+        MX31_PIN_SD14           = IOMUX_PIN(0xff, 249),
+        MX31_PIN_SD13           = IOMUX_PIN(0xff, 250),
+        MX31_PIN_SD12           = IOMUX_PIN(0xff, 251),
+        MX31_PIN_SD11           = IOMUX_PIN(0xff, 252),
+        MX31_PIN_SD10           = IOMUX_PIN(0xff, 253),
+        MX31_PIN_SD9            = IOMUX_PIN(0xff, 254),
+        MX31_PIN_SD8            = IOMUX_PIN(0xff, 255),
+        MX31_PIN_SD7            = IOMUX_PIN(0xff, 256),
+        MX31_PIN_SD6            = IOMUX_PIN(0xff, 257),
+        MX31_PIN_SD5            = IOMUX_PIN(0xff, 258),
+        MX31_PIN_SD4            = IOMUX_PIN(0xff, 259),
+        MX31_PIN_SD3            = IOMUX_PIN(0xff, 260),
+        MX31_PIN_SD2            = IOMUX_PIN(0xff, 261),
+        MX31_PIN_SD1            = IOMUX_PIN(0xff, 262),
+        MX31_PIN_SD0            = IOMUX_PIN(0xff, 263),
+        MX31_PIN_SDBA0          = IOMUX_PIN(0xff, 264),
+        MX31_PIN_SDBA1          = IOMUX_PIN(0xff, 265),
+        MX31_PIN_A25            = IOMUX_PIN(0xff, 266),
+        MX31_PIN_A24            = IOMUX_PIN(0xff, 267),
+        MX31_PIN_A23            = IOMUX_PIN(0xff, 268),
+        MX31_PIN_A22            = IOMUX_PIN(0xff, 269),
+        MX31_PIN_A21            = IOMUX_PIN(0xff, 270),
+        MX31_PIN_A20            = IOMUX_PIN(0xff, 271),
+        MX31_PIN_A19            = IOMUX_PIN(0xff, 272),
+        MX31_PIN_A18            = IOMUX_PIN(0xff, 273),
+        MX31_PIN_A17            = IOMUX_PIN(0xff, 274),
+        MX31_PIN_A16            = IOMUX_PIN(0xff, 275),
+        MX31_PIN_A14            = IOMUX_PIN(0xff, 276),
+        MX31_PIN_A15            = IOMUX_PIN(0xff, 277),
+        MX31_PIN_A13            = IOMUX_PIN(0xff, 278),
+        MX31_PIN_A12            = IOMUX_PIN(0xff, 279),
+        MX31_PIN_A11            = IOMUX_PIN(0xff, 280),
+        MX31_PIN_MA10           = IOMUX_PIN(0xff, 281),
+        MX31_PIN_A10            = IOMUX_PIN(0xff, 282),
+        MX31_PIN_A9             = IOMUX_PIN(0xff, 283),
+        MX31_PIN_A8             = IOMUX_PIN(0xff, 284),
+        MX31_PIN_A7             = IOMUX_PIN(0xff, 285),
+        MX31_PIN_A6             = IOMUX_PIN(0xff, 286),
+        MX31_PIN_A5             = IOMUX_PIN(0xff, 287),
+        MX31_PIN_A4             = IOMUX_PIN(0xff, 288),
+        MX31_PIN_A3             = IOMUX_PIN(0xff, 289),
+        MX31_PIN_A2             = IOMUX_PIN(0xff, 290),
+        MX31_PIN_A1             = IOMUX_PIN(0xff, 291),
+        MX31_PIN_A0             = IOMUX_PIN(0xff, 292),
+        MX31_PIN_VPG1           = IOMUX_PIN(0xff, 293),
+        MX31_PIN_VPG0           = IOMUX_PIN(0xff, 294),
+        MX31_PIN_DVFS1          = IOMUX_PIN(0xff, 295),
+        MX31_PIN_DVFS0          = IOMUX_PIN(0xff, 296),
+        MX31_PIN_VSTBY          = IOMUX_PIN(0xff, 297),
+        MX31_PIN_POWER_FAIL     = IOMUX_PIN(0xff, 298),
+        MX31_PIN_CKIL           = IOMUX_PIN(0xff, 299),
+        MX31_PIN_BOOT_MODE4     = IOMUX_PIN(0xff, 300),
+        MX31_PIN_BOOT_MODE3     = IOMUX_PIN(0xff, 301),
+        MX31_PIN_BOOT_MODE2     = IOMUX_PIN(0xff, 302),
+        MX31_PIN_BOOT_MODE1     = IOMUX_PIN(0xff, 303),
+        MX31_PIN_BOOT_MODE0     = IOMUX_PIN(0xff, 304),
+        MX31_PIN_CLKO           = IOMUX_PIN(0xff, 305),
+        MX31_PIN_POR_B          = IOMUX_PIN(0xff, 306),
+        MX31_PIN_RESET_IN_B     = IOMUX_PIN(0xff, 307),
+        MX31_PIN_CKIH           = IOMUX_PIN(0xff, 308),
+        MX31_PIN_SIMPD0         = IOMUX_PIN(35,   309),
+        MX31_PIN_SRX0           = IOMUX_PIN(34,   310),
+        MX31_PIN_STX0           = IOMUX_PIN(33,   311),
+        MX31_PIN_SVEN0          = IOMUX_PIN(32,   312),
+        MX31_PIN_SRST0          = IOMUX_PIN(67,   313),
+        MX31_PIN_SCLK0          = IOMUX_PIN(66,   314),
+        MX31_PIN_GPIO3_1        = IOMUX_PIN(65,   315),
+        MX31_PIN_GPIO3_0        = IOMUX_PIN(64,   316),
+        MX31_PIN_GPIO1_6        = IOMUX_PIN( 6,   317),
+        MX31_PIN_GPIO1_5        = IOMUX_PIN( 5,   318),
+        MX31_PIN_GPIO1_4        = IOMUX_PIN( 4,   319),
+        MX31_PIN_GPIO1_3        = IOMUX_PIN( 3,   320),
+        MX31_PIN_GPIO1_2        = IOMUX_PIN( 2,   321),
+        MX31_PIN_GPIO1_1        = IOMUX_PIN( 1,   322),
+        MX31_PIN_GPIO1_0        = IOMUX_PIN( 0,   323),
+        MX31_PIN_PWMO           = IOMUX_PIN( 9,   324),
+        MX31_PIN_WATCHDOG_RST   = IOMUX_PIN(0xff, 325),
+        MX31_PIN_COMPARE        = IOMUX_PIN( 8,   326),
+        MX31_PIN_CAPTURE        = IOMUX_PIN( 7,   327),
+};
+
+/*
+ * Convenience values for use with mxc_iomux_mode()
+ *
+ * Format here is MX31_PIN_(pin name)__(function)
+ */
+#define MX31_PIN_CSPI3_MOSI__RXD3       IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI3_MISO__TXD3       IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CTS1__CTS1             IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RTS1__RTS1             IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_TXD1__TXD1             IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RXD1__RXD1             IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
+
+/*
+ * This function configures the pad value for a IOMUX pin.
+ */
+void mxc_iomux_set_pad(enum iomux_pins, u32);
+
+#endif
+
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
index b2c5205e1962..f416130718cf 100644
--- a/include/asm-arm/arch-mxc/irqs.h
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -13,17 +13,4 @@
 
 #include <asm/hardware.h>
 
-#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
-
-#define MXC_IRQ_TO_GPIO(irq)    ((irq) - MXC_GPIO_INT_BASE)
-#define MXC_GPIO_TO_IRQ(x)      (MXC_GPIO_INT_BASE + x)
-
-/* Number of normal interrupts */
-#define NR_IRQS         (MXC_MAX_INT_LINES + \
-                        MXC_MAX_GPIO_LINES + \
-                        MXC_MAX_VIRTUAL_INTS)
-
-/* Number of fast interrupts */
-#define NR_FIQS         MXC_MAX_INTS
-
 #endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/mx27.h b/include/asm-arm/arch-mxc/mx27.h
new file mode 100644
index 000000000000..212ecc246626
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mx27.h
@@ -0,0 +1,302 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_MX27_H__
+#define __ASM_ARCH_MXC_MX27_H__
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+
+/* IRAM */
+#define IRAM_BASE_ADDR          0xFFFF4C00      /* internal ram */
+
+/* Register offests */
+#define AIPI_BASE_ADDR          0x10000000
+#define AIPI_BASE_ADDR_VIRT     0xF4000000
+#define AIPI_SIZE               SZ_1M
+
+#define DMA_BASE_ADDR           (AIPI_BASE_ADDR + 0x01000)
+#define WDOG_BASE_ADDR          (AIPI_BASE_ADDR + 0x02000)
+#define GPT1_BASE_ADDR          (AIPI_BASE_ADDR + 0x03000)
+#define GPT2_BASE_ADDR          (AIPI_BASE_ADDR + 0x04000)
+#define GPT3_BASE_ADDR          (AIPI_BASE_ADDR + 0x05000)
+#define PWM_BASE_ADDR           (AIPI_BASE_ADDR + 0x06000)
+#define RTC_BASE_ADDR           (AIPI_BASE_ADDR + 0x07000)
+#define KPP_BASE_ADDR           (AIPI_BASE_ADDR + 0x08000)
+#define OWIRE_BASE_ADDR         (AIPI_BASE_ADDR + 0x09000)
+#define UART1_BASE_ADDR         (AIPI_BASE_ADDR + 0x0A000)
+#define UART2_BASE_ADDR         (AIPI_BASE_ADDR + 0x0B000)
+#define UART3_BASE_ADDR         (AIPI_BASE_ADDR + 0x0C000)
+#define UART4_BASE_ADDR         (AIPI_BASE_ADDR + 0x0D000)
+#define CSPI1_BASE_ADDR         (AIPI_BASE_ADDR + 0x0E000)
+#define CSPI2_BASE_ADDR         (AIPI_BASE_ADDR + 0x0F000)
+#define SSI1_BASE_ADDR          (AIPI_BASE_ADDR + 0x10000)
+#define SSI2_BASE_ADDR          (AIPI_BASE_ADDR + 0x11000)
+#define I2C_BASE_ADDR           (AIPI_BASE_ADDR + 0x12000)
+#define SDHC1_BASE_ADDR         (AIPI_BASE_ADDR + 0x13000)
+#define SDHC2_BASE_ADDR         (AIPI_BASE_ADDR + 0x14000)
+#define GPIO_BASE_ADDR          (AIPI_BASE_ADDR + 0x15000)
+#define AUDMUX_BASE_ADDR        (AIPI_BASE_ADDR + 0x16000)
+
+#define CSPI3_BASE_ADDR         (AIPI_BASE_ADDR + 0x17000)
+#define MSHC_BASE_ADDR          (AIPI_BASE_ADDR + 0x18000)
+#define GPT5_BASE_ADDR          (AIPI_BASE_ADDR + 0x19000)
+#define GPT4_BASE_ADDR          (AIPI_BASE_ADDR + 0x1A000)
+#define UART5_BASE_ADDR         (AIPI_BASE_ADDR + 0x1B000)
+#define UART6_BASE_ADDR         (AIPI_BASE_ADDR + 0x1C000)
+#define I2C2_BASE_ADDR          (AIPI_BASE_ADDR + 0x1D000)
+#define SDHC3_BASE_ADDR         (AIPI_BASE_ADDR + 0x1E000)
+#define GPT6_BASE_ADDR          (AIPI_BASE_ADDR + 0x1F000)
+
+#define LCDC_BASE_ADDR          (AIPI_BASE_ADDR + 0x21000)
+#define SLCDC_BASE_ADDR         (AIPI_BASE_ADDR + 0x22000)
+#define VPU_BASE_ADDR           (AIPI_BASE_ADDR + 0x23000)
+#define USBOTG_BASE_ADDR        (AIPI_BASE_ADDR + 0x24000)
+/* for mx27*/
+#define OTG_BASE_ADDR           USBOTG_BASE_ADDR
+#define SAHARA_BASE_ADDR        (AIPI_BASE_ADDR + 0x25000)
+#define EMMA_BASE_ADDR          (AIPI_BASE_ADDR + 0x26400)
+#define CCM_BASE_ADDR           (AIPI_BASE_ADDR + 0x27000)
+#define SYSCTRL_BASE_ADDR       (AIPI_BASE_ADDR + 0x27800)
+#define IIM_BASE_ADDR           (AIPI_BASE_ADDR + 0x28000)
+
+#define RTIC_BASE_ADDR          (AIPI_BASE_ADDR + 0x2A000)
+#define FEC_BASE_ADDR           (AIPI_BASE_ADDR + 0x2B000)
+#define SCC_BASE_ADDR           (AIPI_BASE_ADDR + 0x2C000)
+#define ETB_BASE_ADDR           (AIPI_BASE_ADDR + 0x3B000)
+#define ETB_RAM_BASE_ADDR       (AIPI_BASE_ADDR + 0x3C000)
+
+#define JAM_BASE_ADDR           (AIPI_BASE_ADDR + 0x3E000)
+#define MAX_BASE_ADDR           (AIPI_BASE_ADDR + 0x3F000)
+
+/* ROMP and AVIC */
+#define ROMP_BASE_ADDR          0x10041000
+
+#define AVIC_BASE_ADDR          0x10040000
+
+#define SAHB1_BASE_ADDR         0x80000000
+#define SAHB1_BASE_ADDR_VIRT    0xF4100000
+#define SAHB1_SIZE              SZ_1M
+
+#define CSI_BASE_ADDR           (SAHB1_BASE_ADDR + 0x0000)
+#define ATA_BASE_ADDR           (SAHB1_BASE_ADDR + 0x1000)
+
+/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
+#define X_MEMC_BASE_ADDR        0xD8000000
+#define X_MEMC_BASE_ADDR_VIRT   0xF4200000
+#define X_MEMC_SIZE             SZ_1M
+
+#define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR)
+#define SDRAMC_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
+#define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
+#define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
+#define PCMCIA_CTL_BASE_ADDR    (X_MEMC_BASE_ADDR + 0x4000)
+
+/* Memory regions and CS */
+#define SDRAM_BASE_ADDR         0xA0000000
+#define CSD1_BASE_ADDR          0xB0000000
+
+#define CS0_BASE_ADDR           0xC0000000
+#define CS1_BASE_ADDR           0xC8000000
+#define CS2_BASE_ADDR           0xD0000000
+#define CS3_BASE_ADDR           0xD2000000
+#define CS4_BASE_ADDR           0xD4000000
+#define CS5_BASE_ADDR           0xD6000000
+#define PCMCIA_MEM_BASE_ADDR    0xDC000000
+
+/*
+ * This macro defines the physical to virtual address mapping for all the
+ * peripheral modules. It is used by passing in the physical address as x
+ * and returning the virtual address. If the physical address is not mapped,
+ * it returns 0xDEADBEEF
+ */
+#define IO_ADDRESS(x)   \
+        (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
+                AIPI_IO_ADDRESS(x) : \
+        ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
+                SAHB1_IO_ADDRESS(x) : \
+        ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
+                X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
+
+/* define the address mapping macros: in physical address order */
+#define AIPI_IO_ADDRESS(x)  \
+        (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
+
+#define AVIC_IO_ADDRESS(x)      AIPI_IO_ADDRESS(x)
+
+#define SAHB1_IO_ADDRESS(x)  \
+        (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
+
+#define CS4_IO_ADDRESS(x)  \
+        (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
+
+#define X_MEMC_IO_ADDRESS(x)  \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+#define PCMCIA_IO_ADDRESS(x) \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+/* fixed interrput numbers */
+#define MXC_INT_CCM             63
+#define MXC_INT_IIM             62
+#define MXC_INT_LCDC            61
+#define MXC_INT_SLCDC           60
+#define MXC_INT_SAHARA          59
+#define MXC_INT_SCC_SCM         58
+#define MXC_INT_SCC_SMN         57
+#define MXC_INT_USB3            56
+#define MXC_INT_USB2            55
+#define MXC_INT_USB1            54
+#define MXC_INT_VPU             53
+#define MXC_INT_EMMAPP          52
+#define MXC_INT_EMMAPRP         51
+#define MXC_INT_FEC             50
+#define MXC_INT_UART5           49
+#define MXC_INT_UART6           48
+#define MXC_INT_DMACH15         47
+#define MXC_INT_DMACH14         46
+#define MXC_INT_DMACH13         45
+#define MXC_INT_DMACH12         44
+#define MXC_INT_DMACH11         43
+#define MXC_INT_DMACH10         42
+#define MXC_INT_DMACH9          41
+#define MXC_INT_DMACH8          40
+#define MXC_INT_DMACH7          39
+#define MXC_INT_DMACH6          38
+#define MXC_INT_DMACH5          37
+#define MXC_INT_DMACH4          36
+#define MXC_INT_DMACH3          35
+#define MXC_INT_DMACH2          34
+#define MXC_INT_DMACH1          33
+#define MXC_INT_DMACH0          32
+#define MXC_INT_CSI             31
+#define MXC_INT_ATA             30
+#define MXC_INT_NANDFC          29
+#define MXC_INT_PCMCIA          28
+#define MXC_INT_WDOG            27
+#define MXC_INT_GPT1            26
+#define MXC_INT_GPT2            25
+#define MXC_INT_GPT3            24
+#define MXC_INT_GPT             INT_GPT1
+#define MXC_INT_PWM             23
+#define MXC_INT_RTC             22
+#define MXC_INT_KPP             21
+#define MXC_INT_UART1           20
+#define MXC_INT_UART2           19
+#define MXC_INT_UART3           18
+#define MXC_INT_UART4           17
+#define MXC_INT_CSPI1           16
+#define MXC_INT_CSPI2           15
+#define MXC_INT_SSI1            14
+#define MXC_INT_SSI2            13
+#define MXC_INT_I2C             12
+#define MXC_INT_SDHC1           11
+#define MXC_INT_SDHC2           10
+#define MXC_INT_SDHC3           9
+#define MXC_INT_GPIO            8
+#define MXC_INT_SDHC            7
+#define MXC_INT_CSPI3           6
+#define MXC_INT_RTIC            5
+#define MXC_INT_GPT4            4
+#define MXC_INT_GPT5            3
+#define MXC_INT_GPT6            2
+#define MXC_INT_I2C2            1
+
+/* fixed DMA request numbers */
+#define DMA_REQ_NFC             37
+#define DMA_REQ_SDHC3           36
+#define DMA_REQ_UART6_RX        35
+#define DMA_REQ_UART6_TX        34
+#define DMA_REQ_UART5_RX        33
+#define DMA_REQ_UART5_TX        32
+#define DMA_REQ_CSI_RX          31
+#define DMA_REQ_CSI_STAT        30
+#define DMA_REQ_ATA_RCV         29
+#define DMA_REQ_ATA_TX          28
+#define DMA_REQ_UART1_TX        27
+#define DMA_REQ_UART1_RX        26
+#define DMA_REQ_UART2_TX        25
+#define DMA_REQ_UART2_RX        24
+#define DMA_REQ_UART3_TX        23
+#define DMA_REQ_UART3_RX        22
+#define DMA_REQ_UART4_TX        21
+#define DMA_REQ_UART4_RX        20
+#define DMA_REQ_CSPI1_TX        19
+#define DMA_REQ_CSPI1_RX        18
+#define DMA_REQ_CSPI2_TX        17
+#define DMA_REQ_CSPI2_RX        16
+#define DMA_REQ_SSI1_TX1        15
+#define DMA_REQ_SSI1_RX1        14
+#define DMA_REQ_SSI1_TX0        13
+#define DMA_REQ_SSI1_RX0        12
+#define DMA_REQ_SSI2_TX1        11
+#define DMA_REQ_SSI2_RX1        10
+#define DMA_REQ_SSI2_TX0        9
+#define DMA_REQ_SSI2_RX0        8
+#define DMA_REQ_SDHC1           7
+#define DMA_REQ_SDHC2           6
+#define DMA_REQ_MSHC            4
+#define DMA_REQ_EXT             3
+#define DMA_REQ_CSPI3_TX        2
+#define DMA_REQ_CSPI3_RX        1
+
+/* silicon revisions specific to i.MX27 */
+#define CHIP_REV_1_0            0x00
+#define CHIP_REV_2_0            0x01
+
+#ifndef __ASSEMBLY__
+extern int mx27_revision(void);
+#endif
+
+/* gpio and gpio based interrupt handling */
+#define GPIO_DR                 0x1C
+#define GPIO_GDIR               0x00
+#define GPIO_PSR                0x24
+#define GPIO_ICR1               0x28
+#define GPIO_ICR2               0x2C
+#define GPIO_IMR                0x30
+#define GPIO_ISR                0x34
+#define GPIO_INT_LOW_LEV        0x3
+#define GPIO_INT_HIGH_LEV       0x2
+#define GPIO_INT_RISE_EDGE      0x0
+#define GPIO_INT_FALL_EDGE      0x1
+#define GPIO_INT_NONE           0x4
+
+/* Mandatory defines used globally */
+
+/* this is an i.MX27 CPU */
+#define cpu_is_mx27()           (1)
+
+/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
+#define ARCH_NR_GPIOS           (192 + 16)
+
+/* OS clock tick rate */
+#define CLOCK_TICK_RATE         13300000
+
+/* Start of RAM */
+#define PHYS_OFFSET             SDRAM_BASE_ADDR
+
+/* max interrupt lines count */
+#define NR_IRQS                 256
+
+/* count of internal interrupt sources */
+#define MXC_MAX_INT_LINES       64
+
+#endif /* __ASM_ARCH_MXC_MX27_H__ */
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
index 36a1af495bb3..a7373e4a56cb 100644
--- a/include/asm-arm/arch-mxc/mx31.h
+++ b/include/asm-arm/arch-mxc/mx31.h
@@ -320,6 +320,8 @@
 #define MXC_MAX_GPIO_LINES      (GPIO_NUM_PIN * GPIO_PORT_NUM)
 #define MXC_MAX_VIRTUAL_INTS    16
 
+#define NR_IRQS (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES + MXC_MAX_VIRTUAL_INTS)
+
 /*!
  * Number of GPIO port as defined in the IC Spec
  */
@@ -347,6 +349,25 @@
 #define SYSTEM_REV_MIN          CHIP_REV_1_0
 #define SYSTEM_REV_NUM          3
 
+/* gpio and gpio based interrupt handling */
+#define GPIO_DR                 0x00
+#define GPIO_GDIR               0x04
+#define GPIO_PSR                0x08
+#define GPIO_ICR1               0x0C
+#define GPIO_ICR2               0x10
+#define GPIO_IMR                0x14
+#define GPIO_ISR                0x18
+#define GPIO_INT_LOW_LEV        0x0
+#define GPIO_INT_HIGH_LEV       0x1
+#define GPIO_INT_RISE_EDGE      0x2
+#define GPIO_INT_FALL_EDGE      0x3
+#define GPIO_INT_NONE           0x4
+
+/* Mandatory defines used globally */
+
+/* this CPU supports up to 96 GPIOs */
+#define ARCH_NR_GPIOS           96
+
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 
 /* this is a i.MX31 CPU */
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
index 146d3f60951a..332eda4dbd3b 100644
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -1,11 +1,20 @@
 /*
  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
  */
 
 #ifndef __ASM_ARCH_MXC_H__
@@ -20,133 +29,8 @@
 # define cpu_is_mx31() (0)
 #endif
 
-/*
- *****************************************
- * GPT  Register definitions             *
- *****************************************
- */
-#define MXC_GPT_GPTCR           IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
-#define MXC_GPT_GPTPR           IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
-#define MXC_GPT_GPTSR           IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
-#define MXC_GPT_GPTIR           IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
-#define MXC_GPT_GPTOCR1         IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
-#define MXC_GPT_GPTOCR2         IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
-#define MXC_GPT_GPTOCR3         IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
-#define MXC_GPT_GPTICR1         IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
-#define MXC_GPT_GPTICR2         IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
-#define MXC_GPT_GPTCNT          IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
-
-/* GPT Control register bit definitions */
-#define GPTCR_FO3                       (1 << 31)
-#define GPTCR_FO2                       (1 << 30)
-#define GPTCR_FO1                       (1 << 29)
-
-#define GPTCR_OM3_SHIFT                 26
-#define GPTCR_OM3_MASK                  (7 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_DISCONNECTED          (0 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_TOGGLE                (1 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_CLEAR                 (2 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_SET                   (3 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_GENERATE_LOW          (7 << GPTCR_OM3_SHIFT)
-
-#define GPTCR_OM2_SHIFT                 23
-#define GPTCR_OM2_MASK                  (7 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_DISCONNECTED          (0 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_TOGGLE                (1 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_CLEAR                 (2 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_SET                   (3 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_GENERATE_LOW          (7 << GPTCR_OM2_SHIFT)
-
-#define GPTCR_OM1_SHIFT                 20
-#define GPTCR_OM1_MASK                  (7 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_DISCONNECTED          (0 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_TOGGLE                (1 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_CLEAR                 (2 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_SET                   (3 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_GENERATE_LOW          (7 << GPTCR_OM1_SHIFT)
-
-#define GPTCR_IM2_SHIFT                 18
-#define GPTCR_IM2_MASK                  (3 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM2_CAPTURE_DISABLE       (0 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM2_CAPTURE_RISING        (1 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM2_CAPTURE_FALLING       (2 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM2_CAPTURE_BOTH          (3 << GPTCR_IM2_SHIFT)
-
-#define GPTCR_IM1_SHIFT                 16
-#define GPTCR_IM1_MASK                  (3 << GPTCR_IM1_SHIFT)
-#define GPTCR_IM1_CAPTURE_DISABLE       (0 << GPTCR_IM1_SHIFT)
-#define GPTCR_IM1_CAPTURE_RISING        (1 << GPTCR_IM1_SHIFT)
-#define GPTCR_IM1_CAPTURE_FALLING       (2 << GPTCR_IM1_SHIFT)
-#define GPTCR_IM1_CAPTURE_BOTH          (3 << GPTCR_IM1_SHIFT)
-
-#define GPTCR_SWR                       (1 << 15)
-#define GPTCR_FRR                       (1 << 9)
-
-#define GPTCR_CLKSRC_SHIFT              6
-#define GPTCR_CLKSRC_MASK               (7 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_CLKSRC_NOCLOCK            (0 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_CLKSRC_HIGHFREQ           (2 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_CLKSRC_CLKIN              (3 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_CLKSRC_CLK32K             (7 << GPTCR_CLKSRC_SHIFT)
-
-#define GPTCR_STOPEN                    (1 << 5)
-#define GPTCR_DOZEN                     (1 << 4)
-#define GPTCR_WAITEN                    (1 << 3)
-#define GPTCR_DBGEN                     (1 << 2)
-
-#define GPTCR_ENMOD                     (1 << 1)
-#define GPTCR_ENABLE                    (1 << 0)
-
-#define GPTSR_OF1                       (1 << 0)
-#define GPTSR_OF2                       (1 << 1)
-#define GPTSR_OF3                       (1 << 2)
-#define GPTSR_IF1                       (1 << 3)
-#define GPTSR_IF2                       (1 << 4)
-#define GPTSR_ROV                       (1 << 5)
-
-#define GPTIR_OF1IE                     GPTSR_OF1
-#define GPTIR_OF2IE                     GPTSR_OF2
-#define GPTIR_OF3IE                     GPTSR_OF3
-#define GPTIR_IF1IE                     GPTSR_IF1
-#define GPTIR_IF2IE                     GPTSR_IF2
-#define GPTIR_ROVIE                     GPTSR_ROV
-
-/*
- *****************************************
- * AVIC Registers                        *
- *****************************************
- */
-#define AVIC_BASE               IO_ADDRESS(AVIC_BASE_ADDR)
-#define AVIC_INTCNTL            (AVIC_BASE + 0x00)      /* int control reg */
-#define AVIC_NIMASK             (AVIC_BASE + 0x04)      /* int mask reg */
-#define AVIC_INTENNUM           (AVIC_BASE + 0x08)      /* int enable number reg */
-#define AVIC_INTDISNUM          (AVIC_BASE + 0x0C)      /* int disable number reg */
-#define AVIC_INTENABLEH         (AVIC_BASE + 0x10)      /* int enable reg high */
-#define AVIC_INTENABLEL         (AVIC_BASE + 0x14)      /* int enable reg low */
-#define AVIC_INTTYPEH           (AVIC_BASE + 0x18)      /* int type reg high */
-#define AVIC_INTTYPEL           (AVIC_BASE + 0x1C)      /* int type reg low */
-#define AVIC_NIPRIORITY7        (AVIC_BASE + 0x20)      /* norm int priority lvl7 */
-#define AVIC_NIPRIORITY6        (AVIC_BASE + 0x24)      /* norm int priority lvl6 */
-#define AVIC_NIPRIORITY5        (AVIC_BASE + 0x28)      /* norm int priority lvl5 */
-#define AVIC_NIPRIORITY4        (AVIC_BASE + 0x2C)      /* norm int priority lvl4 */
-#define AVIC_NIPRIORITY3        (AVIC_BASE + 0x30)      /* norm int priority lvl3 */
-#define AVIC_NIPRIORITY2        (AVIC_BASE + 0x34)      /* norm int priority lvl2 */
-#define AVIC_NIPRIORITY1        (AVIC_BASE + 0x38)      /* norm int priority lvl1 */
-#define AVIC_NIPRIORITY0        (AVIC_BASE + 0x3C)      /* norm int priority lvl0 */
-#define AVIC_NIVECSR            (AVIC_BASE + 0x40)      /* norm int vector/status */
-#define AVIC_FIVECSR            (AVIC_BASE + 0x44)      /* fast int vector/status */
-#define AVIC_INTSRCH            (AVIC_BASE + 0x48)      /* int source reg high */
-#define AVIC_INTSRCL            (AVIC_BASE + 0x4C)      /* int source reg low */
-#define AVIC_INTFRCH            (AVIC_BASE + 0x50)      /* int force reg high */
-#define AVIC_INTFRCL            (AVIC_BASE + 0x54)      /* int force reg low */
-#define AVIC_NIPNDH             (AVIC_BASE + 0x58)      /* norm int pending high */
-#define AVIC_NIPNDL             (AVIC_BASE + 0x5C)      /* norm int pending low */
-#define AVIC_FIPNDH             (AVIC_BASE + 0x60)      /* fast int pending high */
-#define AVIC_FIPNDL             (AVIC_BASE + 0x64)      /* fast int pending low */
-
-#define SYSTEM_PREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x20)
-#define SYSTEM_SREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x24)
-#define IIM_PROD_REV_SH         3
-#define IIM_PROD_REV_LEN        5
+#ifndef CONFIG_MACH_MX27
+# define cpu_is_mx27() (0)
+#endif
 
 #endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc_timer.h b/include/asm-arm/arch-mxc/mxc_timer.h
new file mode 100644
index 000000000000..6cb11f4f1a06
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mxc_timer.h
@@ -0,0 +1,158 @@
+/*
+ * mxc_timer.h
+ *
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __PLAT_MXC_TIMER_H
+#define __PLAT_MXC_TIMER_H
+
+#include <linux/clk.h>
+#include <asm/hardware.h>
+
+#ifdef CONFIG_ARCH_IMX
+#define TIMER_BASE              IO_ADDRESS(TIM1_BASE_ADDR)
+#define TIMER_INTERRUPT         TIM1_INT
+
+#define TCTL_VAL                TCTL_CLK_PCLK1
+#define TCTL_IRQEN              (1<<4)
+#define TCTL_FRR                (1<<8)
+#define TCTL_CLK_PCLK1          (1<<1)
+#define TCTL_CLK_PCLK1_4        (2<<1)
+#define TCTL_CLK_TIN            (3<<1)
+#define TCTL_CLK_32             (4<<1)
+
+#define MXC_TCTL   0x00
+#define MXC_TPRER  0x04
+#define MXC_TCMP   0x08
+#define MXC_TCR    0x0c
+#define MXC_TCN    0x10
+#define MXC_TSTAT  0x14
+#define TSTAT_CAPT              (1<<1)
+#define TSTAT_COMP              (1<<0)
+
+static inline void gpt_irq_disable(void)
+{
+        unsigned int tmp;
+
+        tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
+        __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
+}
+
+static inline void gpt_irq_enable(void)
+{
+        __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
+                                TIMER_BASE + MXC_TCTL);
+}
+
+static void gpt_irq_acknowledge(void)
+{
+        __raw_writel(0, TIMER_BASE + MXC_TSTAT);
+}
+#endif /* CONFIG_ARCH_IMX */
+
+#ifdef CONFIG_ARCH_MX2
+#define TIMER_BASE              IO_ADDRESS(GPT1_BASE_ADDR)
+#define TIMER_INTERRUPT         MXC_INT_GPT1
+
+#define MXC_TCTL   0x00
+#define TCTL_VAL                TCTL_CLK_PCLK1
+#define TCTL_CLK_PCLK1          (1<<1)
+#define TCTL_CLK_PCLK1_4        (2<<1)
+#define TCTL_IRQEN              (1<<4)
+#define TCTL_FRR                (1<<8)
+#define MXC_TPRER  0x04
+#define MXC_TCMP   0x08
+#define MXC_TCR    0x0c
+#define MXC_TCN    0x10
+#define MXC_TSTAT  0x14
+#define TSTAT_CAPT              (1<<1)
+#define TSTAT_COMP              (1<<0)
+
+static inline void gpt_irq_disable(void)
+{
+        unsigned int tmp;
+
+        tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
+        __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
+}
+
+static inline void gpt_irq_enable(void)
+{
+        __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
+                                TIMER_BASE + MXC_TCTL);
+}
+
+static void gpt_irq_acknowledge(void)
+{
+        __raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT);
+}
+#endif /* CONFIG_ARCH_MX2 */
+
+#ifdef CONFIG_ARCH_MX3
+#define TIMER_BASE              IO_ADDRESS(GPT1_BASE_ADDR)
+#define TIMER_INTERRUPT         MXC_INT_GPT
+
+#define MXC_TCTL   0x00
+#define TCTL_VAL                (TCTL_CLK_IPG | TCTL_WAITEN)
+#define TCTL_CLK_IPG            (1<<6)
+#define TCTL_FRR                (1<<9)
+#define TCTL_WAITEN             (1<<3)
+
+#define MXC_TPRER  0x04
+#define MXC_TSTAT  0x08
+#define TSTAT_OF1               (1<<0)
+#define TSTAT_OF2               (1<<1)
+#define TSTAT_OF3               (1<<2)
+#define TSTAT_IF1               (1<<3)
+#define TSTAT_IF2               (1<<4)
+#define TSTAT_ROV               (1<<5)
+#define MXC_IR     0x0c
+#define MXC_TCMP   0x10
+#define MXC_TCMP2  0x14
+#define MXC_TCMP3  0x18
+#define MXC_TCR    0x1c
+#define MXC_TCN    0x24
+
+static inline void gpt_irq_disable(void)
+{
+        __raw_writel(0, TIMER_BASE + MXC_IR);
+}
+
+static inline void gpt_irq_enable(void)
+{
+        __raw_writel(1<<0, TIMER_BASE + MXC_IR);
+}
+
+static inline void gpt_irq_acknowledge(void)
+{
+        __raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT);
+}
+#endif /* CONFIG_ARCH_MX3 */
+
+#define TCTL_SWR                (1<<15)
+#define TCTL_CC                 (1<<10)
+#define TCTL_OM                 (1<<9)
+#define TCTL_CAP_RIS            (1<<6)
+#define TCTL_CAP_FAL            (2<<6)
+#define TCTL_CAP_RIS_FAL        (3<<6)
+#define TCTL_CAP_ENA            (1<<5)
+#define TCTL_TEN                (1<<0)
+
+#endif
diff --git a/include/asm-arm/arch-ns9xxx/hardware.h b/include/asm-arm/arch-ns9xxx/hardware.h
index 0b7b34603f1c..0dca11ce21fc 100644
--- a/include/asm-arm/arch-ns9xxx/hardware.h
+++ b/include/asm-arm/arch-ns9xxx/hardware.h
@@ -66,13 +66,13 @@
          __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field)
 
 #  define REGGETIM_IDX(var, reg, field, idx)                            \
-         __REGGET(var, reg ## _ ## field((idx))) /                      \
+         __REGGET(var, reg ## _ ## field((idx))) /                      \
          __REGSHIFT(reg ## _ ## field((idx)))
 
 #else
 
 #  define __REG(x)      io_p2v(x)
-#  define __REG2(x, y)  io_p2v((x) + (y))
+#  define __REG2(x, y)  io_p2v((x) + 4 * (y))
 
 #endif
 
diff --git a/include/asm-arm/arch-omap/board-2430sdp.h b/include/asm-arm/arch-omap/board-2430sdp.h
index e9c65ce3cb12..c7db9004ec31 100644
--- a/include/asm-arm/arch-omap/board-2430sdp.h
+++ b/include/asm-arm/arch-omap/board-2430sdp.h
@@ -36,9 +36,4 @@
 
 #define TWL4030_IRQNUM                  INT_24XX_SYS_NIRQ
 
-/* TWL4030 Primary Interrupt Handler (PIH) interrupts */
-#define IH_TWL4030_BASE                 IH_BOARD_BASE
-#define IH_TWL4030_END                  (IH_TWL4030_BASE+8)
-#define NR_IRQS                         (IH_TWL4030_END)
-
 #endif /* __ASM_ARCH_OMAP_2430SDP_H */
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
index 0f6404435ea8..c5d0f32a40ac 100644
--- a/include/asm-arm/arch-omap/board-h3.h
+++ b/include/asm-arm/arch-omap/board-h3.h
@@ -30,12 +30,6 @@
 /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
 #define OMAP1710_ETHR_START             0x04000300
 
-#define MAXIRQNUM                       (IH_BOARD_BASE)
-#define MAXFIQNUM                       MAXIRQNUM
-#define MAXSWINUM                       MAXIRQNUM
-
-#define NR_IRQS                         (MAXIRQNUM + 1)
-
 extern void h3_mmc_init(void);
 extern void h3_mmc_slot_cover_handler(void *arg, int state);
 
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h
index 56d2c98e143c..9ca03dec9d36 100644
--- a/include/asm-arm/arch-omap/board-innovator.h
+++ b/include/asm-arm/arch-omap/board-innovator.h
@@ -36,9 +36,6 @@
 #define OMAP1510P1_EMIFS_PRI_VALUE              0x00
 #define OMAP1510P1_EMIFF_PRI_VALUE              0x00
 
-#define NR_FPGA_IRQS            24
-#define NR_IRQS                 (IH_BOARD_BASE + NR_FPGA_IRQS)
-
 #ifndef __ASSEMBLY__
 void fpga_write(unsigned char val, int reg);
 unsigned char fpga_read(int reg);
diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h
index eb74420cb439..d7429cb0f726 100644
--- a/include/asm-arm/arch-omap/board-perseus2.h
+++ b/include/asm-arm/arch-omap/board-perseus2.h
@@ -36,10 +36,4 @@
 #define OMAP_SDRAM_DEVICE               D256M_1X16_4B
 #endif
 
-#define MAXIRQNUM               IH_BOARD_BASE
-#define MAXFIQNUM               MAXIRQNUM
-#define MAXSWINUM               MAXIRQNUM
-
-#define NR_IRQS                 (MAXIRQNUM + 1)
-
 #endif
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h
index 12a5e4de9518..4c7b3514f71a 100644
--- a/include/asm-arm/arch-omap/clock.h
+++ b/include/asm-arm/arch-omap/clock.h
@@ -33,12 +33,24 @@ struct dpll_data {
         void __iomem            *mult_div1_reg;
         u32                     mult_mask;
         u32                     div1_mask;
+        u16                     last_rounded_m;
+        u8                      last_rounded_n;
+        unsigned long           last_rounded_rate;
+        unsigned int            rate_tolerance;
+        u16                     max_multiplier;
+        u8                      max_divider;
+        u32                     max_tolerance;
 #  if defined(CONFIG_ARCH_OMAP3)
+        u8                      modes;
         void __iomem            *control_reg;
         u32                     enable_mask;
         u8                      auto_recal_bit;
         u8                      recal_en_bit;
         u8                      recal_st_bit;
+        void __iomem            *autoidle_reg;
+        u32                     autoidle_mask;
+        void __iomem            *idlest_reg;
+        u8                      idlest_bit;
 #  endif
 };
 
@@ -66,11 +78,14 @@ struct clk {
         void __iomem            *clksel_reg;
         u32                     clksel_mask;
         const struct clksel     *clksel;
-        const struct dpll_data  *dpll_data;
+        struct dpll_data        *dpll_data;
 #else
         __u8                    rate_offset;
         __u8                    src_offset;
 #endif
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+        struct dentry           *dent;  /* For visible tree hierarchy */
+#endif
 };
 
 struct cpufreq_frequency_table;
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
index 36a3b62d4d8d..8ac03071f60c 100644
--- a/include/asm-arm/arch-omap/common.h
+++ b/include/asm-arm/arch-omap/common.h
@@ -47,8 +47,23 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
 }
 #endif
 
+/* IO bases for various OMAP processors */
+struct omap_globals {
+        void __iomem    *tap;           /* Control module ID code */
+        void __iomem    *sdrc;          /* SDRAM Controller */
+        void __iomem    *sms;           /* SDRAM Memory Scheduler */
+        void __iomem    *ctrl;          /* System Control Module */
+        void __iomem    *prm;           /* Power and Reset Management */
+        void __iomem    *cm;            /* Clock Management */
+};
+
 void omap2_set_globals_242x(void);
 void omap2_set_globals_243x(void);
 void omap2_set_globals_343x(void);
 
+/* These get called from omap2_set_globals_xxxx(), do not call these */
+void omap2_set_globals_memory(struct omap_globals *);
+void omap2_set_globals_control(struct omap_globals *);
+void omap2_set_globals_prcm(struct omap_globals *);
+
 #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
index 59c0686f8be7..987553e3eeb9 100644
--- a/include/asm-arm/arch-omap/control.h
+++ b/include/asm-arm/arch-omap/control.h
@@ -167,8 +167,7 @@
 
 #ifndef __ASSEMBLY__
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-extern void omap_ctrl_base_set(u32 base);
-extern u32 omap_ctrl_base_get(void);
+extern void __iomem *omap_ctrl_base_get(void);
 extern u8 omap_ctrl_readb(u16 offset);
 extern u16 omap_ctrl_readw(u16 offset);
 extern u32 omap_ctrl_readl(u16 offset);
@@ -176,7 +175,6 @@ extern void omap_ctrl_writeb(u8 val, u16 offset);
 extern void omap_ctrl_writew(u16 val, u16 offset);
 extern void omap_ctrl_writel(u32 val, u16 offset);
 #else
-#define omap_ctrl_base_set(x)           WARN_ON(1)
 #define omap_ctrl_base_get()            0
 #define omap_ctrl_readb(x)              0
 #define omap_ctrl_readw(x)              0
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
index e8a4cf52778b..52db09f83281 100644
--- a/include/asm-arm/arch-omap/cpu.h
+++ b/include/asm-arm/arch-omap/cpu.h
@@ -3,7 +3,7 @@
  *
  * OMAP cpu type detection
  *
- * Copyright (C) 2004 Nokia Corporation
+ * Copyright (C) 2004, 2008 Nokia Corporation
  *
  * Written by Tony Lindgren <tony.lindgren@nokia.com>
  *
@@ -26,6 +26,12 @@
 #ifndef __ASM_ARCH_OMAP_CPU_H
 #define __ASM_ARCH_OMAP_CPU_H
 
+struct omap_chip_id {
+        u8 oc;
+};
+
+#define OMAP_CHIP_INIT(x)       { .oc = x }
+
 extern unsigned int system_rev;
 
 #define omap2_cpu_rev()         ((system_rev >> 12) & 0x0f)
@@ -345,6 +351,33 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define OMAP2430_REV_ES1_0      0x24300000
 #define OMAP3430_REV_ES1_0      0x34300000
 #define OMAP3430_REV_ES2_0      0x34301000
+#define OMAP3430_REV_ES2_1      0x34302000
+#define OMAP3430_REV_ES2_2      0x34303000
+
+/*
+ * omap_chip bits
+ *
+ * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
+ * valid on all chips of that type.  CHIP_IS_OMAP3430ES{1,2} indicates
+ * something that is only valid on that particular ES revision.
+ *
+ * These bits may be ORed together to indicate structures that are
+ * available on multiple chip types.
+ *
+ * To test whether a particular structure matches the current OMAP chip type,
+ * use omap_chip_is().
+ *
+ */
+#define CHIP_IS_OMAP2420       (1 << 0)
+#define CHIP_IS_OMAP2430       (1 << 1)
+#define CHIP_IS_OMAP3430       (1 << 2)
+#define CHIP_IS_OMAP3430ES1    (1 << 3)
+#define CHIP_IS_OMAP3430ES2    (1 << 4)
+
+#define CHIP_IS_OMAP24XX       (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
+
+int omap_chip_is(struct omap_chip_id oci);
+
 
 /*
  * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
@@ -362,6 +395,8 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define is_device_type_gp()     (get_device_type() == DEVICE_TYPE_GP)
 #define is_device_type_bad()    (get_device_type() == DEVICE_TYPE_BAD)
 
-#endif
+void omap2_check_revision(void);
+
+#endif    /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
 
 #endif
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index 24acf090030d..f4dcb9587869 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -22,108 +22,128 @@
 #define __ASM_ARCH_DMA_H
 
 /* Hardware registers for omap1 */
-#define OMAP_DMA_BASE                   (0xfffed800)
-#define OMAP_DMA_GCR                    (OMAP_DMA_BASE + 0x400)
-#define OMAP_DMA_GSCR                   (OMAP_DMA_BASE + 0x404)
-#define OMAP_DMA_GRST                   (OMAP_DMA_BASE + 0x408)
-#define OMAP_DMA_HW_ID                  (OMAP_DMA_BASE + 0x442)
-#define OMAP_DMA_PCH2_ID                (OMAP_DMA_BASE + 0x444)
-#define OMAP_DMA_PCH0_ID                (OMAP_DMA_BASE + 0x446)
-#define OMAP_DMA_PCH1_ID                (OMAP_DMA_BASE + 0x448)
-#define OMAP_DMA_PCHG_ID                (OMAP_DMA_BASE + 0x44a)
-#define OMAP_DMA_PCHD_ID                (OMAP_DMA_BASE + 0x44c)
-#define OMAP_DMA_CAPS_0_U               (OMAP_DMA_BASE + 0x44e)
-#define OMAP_DMA_CAPS_0_L               (OMAP_DMA_BASE + 0x450)
-#define OMAP_DMA_CAPS_1_U               (OMAP_DMA_BASE + 0x452)
-#define OMAP_DMA_CAPS_1_L               (OMAP_DMA_BASE + 0x454)
-#define OMAP_DMA_CAPS_2                 (OMAP_DMA_BASE + 0x456)
-#define OMAP_DMA_CAPS_3                 (OMAP_DMA_BASE + 0x458)
-#define OMAP_DMA_CAPS_4                 (OMAP_DMA_BASE + 0x45a)
-#define OMAP_DMA_PCH2_SR                (OMAP_DMA_BASE + 0x460)
-#define OMAP_DMA_PCH0_SR                (OMAP_DMA_BASE + 0x480)
-#define OMAP_DMA_PCH1_SR                (OMAP_DMA_BASE + 0x482)
-#define OMAP_DMA_PCHD_SR                (OMAP_DMA_BASE + 0x4c0)
-
-/* Hardware registers for omap2 */
-#if defined(CONFIG_ARCH_OMAP3)
-#define OMAP_DMA4_BASE                  (L4_34XX_BASE + 0x56000)
-#else   /* CONFIG_ARCH_OMAP2 */
-#define OMAP_DMA4_BASE                  (L4_24XX_BASE + 0x56000)
-#endif
-
-#define OMAP_DMA4_REVISION              (OMAP_DMA4_BASE + 0x00)
-#define OMAP_DMA4_GCR_REG               (OMAP_DMA4_BASE + 0x78)
-#define OMAP_DMA4_IRQSTATUS_L0          (OMAP_DMA4_BASE + 0x08)
-#define OMAP_DMA4_IRQSTATUS_L1          (OMAP_DMA4_BASE + 0x0c)
-#define OMAP_DMA4_IRQSTATUS_L2          (OMAP_DMA4_BASE + 0x10)
-#define OMAP_DMA4_IRQSTATUS_L3          (OMAP_DMA4_BASE + 0x14)
-#define OMAP_DMA4_IRQENABLE_L0          (OMAP_DMA4_BASE + 0x18)
-#define OMAP_DMA4_IRQENABLE_L1          (OMAP_DMA4_BASE + 0x1c)
-#define OMAP_DMA4_IRQENABLE_L2          (OMAP_DMA4_BASE + 0x20)
-#define OMAP_DMA4_IRQENABLE_L3          (OMAP_DMA4_BASE + 0x24)
-#define OMAP_DMA4_SYSSTATUS             (OMAP_DMA4_BASE + 0x28)
-#define OMAP_DMA4_OCP_SYSCONFIG         (OMAP_DMA4_BASE + 0x2c)
-#define OMAP_DMA4_CAPS_0                (OMAP_DMA4_BASE + 0x64)
-#define OMAP_DMA4_CAPS_2                (OMAP_DMA4_BASE + 0x6c)
-#define OMAP_DMA4_CAPS_3                (OMAP_DMA4_BASE + 0x70)
-#define OMAP_DMA4_CAPS_4                (OMAP_DMA4_BASE + 0x74)
-
-#ifdef CONFIG_ARCH_OMAP1
-
-#define OMAP_LOGICAL_DMA_CH_COUNT       17
+#define OMAP1_DMA_BASE                  (0xfffed800)
+
+#define OMAP1_DMA_GCR                   0x400
+#define OMAP1_DMA_GSCR                  0x404
+#define OMAP1_DMA_GRST                  0x408
+#define OMAP1_DMA_HW_ID                 0x442
+#define OMAP1_DMA_PCH2_ID               0x444
+#define OMAP1_DMA_PCH0_ID               0x446
+#define OMAP1_DMA_PCH1_ID               0x448
+#define OMAP1_DMA_PCHG_ID               0x44a
+#define OMAP1_DMA_PCHD_ID               0x44c
+#define OMAP1_DMA_CAPS_0_U              0x44e
+#define OMAP1_DMA_CAPS_0_L              0x450
+#define OMAP1_DMA_CAPS_1_U              0x452
+#define OMAP1_DMA_CAPS_1_L              0x454
+#define OMAP1_DMA_CAPS_2                0x456
+#define OMAP1_DMA_CAPS_3                0x458
+#define OMAP1_DMA_CAPS_4                0x45a
+#define OMAP1_DMA_PCH2_SR               0x460
+#define OMAP1_DMA_PCH0_SR               0x480
+#define OMAP1_DMA_PCH1_SR               0x482
+#define OMAP1_DMA_PCHD_SR               0x4c0
+
+/* Hardware registers for omap2 and omap3 */
+#define OMAP24XX_DMA4_BASE              (L4_24XX_BASE + 0x56000)
+#define OMAP34XX_DMA4_BASE              (L4_34XX_BASE + 0x56000)
+
+#define OMAP_DMA4_REVISION              0x00
+#define OMAP_DMA4_GCR                   0x78
+#define OMAP_DMA4_IRQSTATUS_L0          0x08
+#define OMAP_DMA4_IRQSTATUS_L1          0x0c
+#define OMAP_DMA4_IRQSTATUS_L2          0x10
+#define OMAP_DMA4_IRQSTATUS_L3          0x14
+#define OMAP_DMA4_IRQENABLE_L0          0x18
+#define OMAP_DMA4_IRQENABLE_L1          0x1c
+#define OMAP_DMA4_IRQENABLE_L2          0x20
+#define OMAP_DMA4_IRQENABLE_L3          0x24
+#define OMAP_DMA4_SYSSTATUS             0x28
+#define OMAP_DMA4_OCP_SYSCONFIG         0x2c
+#define OMAP_DMA4_CAPS_0                0x64
+#define OMAP_DMA4_CAPS_2                0x6c
+#define OMAP_DMA4_CAPS_3                0x70
+#define OMAP_DMA4_CAPS_4                0x74
+
+#define OMAP1_LOGICAL_DMA_CH_COUNT      17
+#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT  32      /* REVISIT: Is this 32 + 2? */
 
 /* Common channel specific registers for omap1 */
-#define OMAP_DMA_CSDP_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00)
-#define OMAP_DMA_CCR_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02)
-#define OMAP_DMA_CICR_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04)
-#define OMAP_DMA_CSR_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06)
-#define OMAP_DMA_CEN_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10)
-#define OMAP_DMA_CFN_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12)
-#define OMAP_DMA_CSFI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14)
-#define OMAP_DMA_CSEI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16)
-#define OMAP_DMA_CSAC_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18)
-#define OMAP_DMA_CDAC_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
-#define OMAP_DMA_CDEI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
-#define OMAP_DMA_CDFI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
-#define OMAP_DMA_CLNK_CTRL_REG(n)       __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28)
-
-#else
-
-#define OMAP_LOGICAL_DMA_CH_COUNT       32      /* REVISIT: Is this 32 + 2? */
+#define OMAP1_DMA_CH_BASE(n)            (0x40 * (n) + 0x00)
+#define OMAP1_DMA_CSDP(n)               (0x40 * (n) + 0x00)
+#define OMAP1_DMA_CCR(n)                (0x40 * (n) + 0x02)
+#define OMAP1_DMA_CICR(n)               (0x40 * (n) + 0x04)
+#define OMAP1_DMA_CSR(n)                (0x40 * (n) + 0x06)
+#define OMAP1_DMA_CEN(n)                (0x40 * (n) + 0x10)
+#define OMAP1_DMA_CFN(n)                (0x40 * (n) + 0x12)
+#define OMAP1_DMA_CSFI(n)               (0x40 * (n) + 0x14)
+#define OMAP1_DMA_CSEI(n)               (0x40 * (n) + 0x16)
+#define OMAP1_DMA_CPC(n)                (0x40 * (n) + 0x18)     /* 15xx only */
+#define OMAP1_DMA_CSAC(n)               (0x40 * (n) + 0x18)
+#define OMAP1_DMA_CDAC(n)               (0x40 * (n) + 0x1a)
+#define OMAP1_DMA_CDEI(n)               (0x40 * (n) + 0x1c)
+#define OMAP1_DMA_CDFI(n)               (0x40 * (n) + 0x1e)
+#define OMAP1_DMA_CLNK_CTRL(n)          (0x40 * (n) + 0x28)
 
 /* Common channel specific registers for omap2 */
-#define OMAP_DMA_CCR_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80)
-#define OMAP_DMA_CLNK_CTRL_REG(n)       __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84)
-#define OMAP_DMA_CICR_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88)
-#define OMAP_DMA_CSR_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c)
-#define OMAP_DMA_CSDP_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90)
-#define OMAP_DMA_CEN_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94)
-#define OMAP_DMA_CFN_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98)
-#define OMAP_DMA_CSEI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4)
-#define OMAP_DMA_CSFI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8)
-#define OMAP_DMA_CDEI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac)
-#define OMAP_DMA_CDFI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0)
-#define OMAP_DMA_CSAC_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4)
-#define OMAP_DMA_CDAC_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8)
-
-#endif
+#define OMAP_DMA4_CH_BASE(n)            (0x60 * (n) + 0x80)
+#define OMAP_DMA4_CCR(n)                (0x60 * (n) + 0x80)
+#define OMAP_DMA4_CLNK_CTRL(n)          (0x60 * (n) + 0x84)
+#define OMAP_DMA4_CICR(n)               (0x60 * (n) + 0x88)
+#define OMAP_DMA4_CSR(n)                (0x60 * (n) + 0x8c)
+#define OMAP_DMA4_CSDP(n)               (0x60 * (n) + 0x90)
+#define OMAP_DMA4_CEN(n)                (0x60 * (n) + 0x94)
+#define OMAP_DMA4_CFN(n)                (0x60 * (n) + 0x98)
+#define OMAP_DMA4_CSEI(n)               (0x60 * (n) + 0xa4)
+#define OMAP_DMA4_CSFI(n)               (0x60 * (n) + 0xa8)
+#define OMAP_DMA4_CDEI(n)               (0x60 * (n) + 0xac)
+#define OMAP_DMA4_CDFI(n)               (0x60 * (n) + 0xb0)
+#define OMAP_DMA4_CSAC(n)               (0x60 * (n) + 0xb4)
+#define OMAP_DMA4_CDAC(n)               (0x60 * (n) + 0xb8)
 
 /* Channel specific registers only on omap1 */
-#define OMAP1_DMA_CSSA_L_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
-#define OMAP1_DMA_CSSA_U_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
-#define OMAP1_DMA_CDSA_L_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
-#define OMAP1_DMA_CDSA_U_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
-#define OMAP1_DMA_COLOR_L_REG(n)        __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
-#define OMAP1_DMA_CCR2_REG(n)           __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
-#define OMAP1_DMA_COLOR_U_REG(n)        __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
-#define OMAP1_DMA_LCH_CTRL_REG(n)       __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
+#define OMAP1_DMA_CSSA_L(n)             (0x40 * (n) + 0x08)
+#define OMAP1_DMA_CSSA_U(n)             (0x40 * (n) + 0x0a)
+#define OMAP1_DMA_CDSA_L(n)             (0x40 * (n) + 0x0c)
+#define OMAP1_DMA_CDSA_U(n)             (0x40 * (n) + 0x0e)
+#define OMAP1_DMA_COLOR_L(n)            (0x40 * (n) + 0x20)
+#define OMAP1_DMA_COLOR_U(n)            (0x40 * (n) + 0x22)
+#define OMAP1_DMA_CCR2(n)               (0x40 * (n) + 0x24)
+#define OMAP1_DMA_LCH_CTRL(n)           (0x40 * (n) + 0x2a)     /* not on 15xx */
+#define OMAP1_DMA_CCEN(n)               0
+#define OMAP1_DMA_CCFN(n)               0
 
 /* Channel specific registers only on omap2 */
-#define OMAP2_DMA_CSSA_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c)
-#define OMAP2_DMA_CDSA_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0)
-#define OMAP2_DMA_CCEN_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc)
-#define OMAP2_DMA_CCFN_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0)
-#define OMAP2_DMA_COLOR_REG(n)          __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4)
+#define OMAP_DMA4_CSSA(n)               (0x60 * (n) + 0x9c)
+#define OMAP_DMA4_CDSA(n)               (0x60 * (n) + 0xa0)
+#define OMAP_DMA4_CCEN(n)               (0x60 * (n) + 0xbc)
+#define OMAP_DMA4_CCFN(n)               (0x60 * (n) + 0xc0)
+#define OMAP_DMA4_COLOR(n)              (0x60 * (n) + 0xc4)
+
+/* Dummy defines to keep multi-omap compiles happy */
+#define OMAP1_DMA_REVISION              0
+#define OMAP1_DMA_IRQSTATUS_L0          0
+#define OMAP1_DMA_IRQENABLE_L0          0
+#define OMAP1_DMA_OCP_SYSCONFIG         0
+#define OMAP_DMA4_HW_ID                 0
+#define OMAP_DMA4_CAPS_0_L              0
+#define OMAP_DMA4_CAPS_0_U              0
+#define OMAP_DMA4_CAPS_1_L              0
+#define OMAP_DMA4_CAPS_1_U              0
+#define OMAP_DMA4_GSCR                  0
+#define OMAP_DMA4_CPC(n)                0
+
+#define OMAP_DMA4_LCH_CTRL(n)           0
+#define OMAP_DMA4_COLOR_L(n)            0
+#define OMAP_DMA4_COLOR_U(n)            0
+#define OMAP_DMA4_CCR2(n)               0
+#define OMAP1_DMA_CSSA(n)               0
+#define OMAP1_DMA_CDSA(n)               0
+#define OMAP_DMA4_CSSA_L(n)             0
+#define OMAP_DMA4_CSSA_U(n)             0
+#define OMAP_DMA4_CDSA_L(n)             0
+#define OMAP_DMA4_CDSA_U(n)             0
 
 /*----------------------------------------------------------------------------*/
 
@@ -196,63 +216,98 @@
 #define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
 #define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
 #define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
-#define OMAP24XX_DMA_VLYNQ_TX           7       /* S_DMA_6 */
+#define OMAP242X_DMA_VLYNQ_TX           7       /* S_DMA_6 */
+#define OMAP24XX_DMA_EXT_DMAREQ2        7       /* S_DMA_6 */
 #define OMAP24XX_DMA_CWT                8       /* S_DMA_7 */
 #define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
 #define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
 #define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
 #define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
 #define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
-#define OMAP24XX_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
-#define OMAP24XX_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
-#define OMAP24XX_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
-#define OMAP24XX_DMA_EAC_AC_RD          17      /* S_DMA_16 */
-#define OMAP24XX_DMA_EAC_AC_WR          18      /* S_DMA_17 */
-#define OMAP24XX_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
-#define OMAP24XX_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
-#define OMAP24XX_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
-#define OMAP24XX_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
-#define OMAP24XX_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
-#define OMAP24XX_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
-#define OMAP24XX_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
-#define OMAP24XX_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
+#define OMAP34XX_DMA_SHA2MD5_RX         13      /* S_DMA_12 */
+#define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
+#define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
+#define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
+#define OMAP242X_DMA_EAC_AC_RD          17      /* S_DMA_16 */
+#define OMAP242X_DMA_EAC_AC_WR          18      /* S_DMA_17 */
+#define OMAP242X_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
+#define OMAP242X_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
+#define OMAP242X_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
+#define OMAP242X_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
+#define OMAP242X_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
+#define OMAP242X_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
+#define OMAP242X_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
+#define OMAP242X_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
+#define OMAP243X_DMA_EXT_DMAREQ3        14      /* S_DMA_13 */
+#define OMAP24XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
+#define OMAP24XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
+#define OMAP24XX_DMA_MCBSP3_TX          17      /* S_DMA_16 */
+#define OMAP24XX_DMA_MCBSP3_RX          18      /* S_DMA_17 */
+#define OMAP24XX_DMA_MCBSP4_TX          19      /* S_DMA_18 */
+#define OMAP24XX_DMA_MCBSP4_RX          20      /* S_DMA_19 */
+#define OMAP24XX_DMA_MCBSP5_TX          21      /* S_DMA_20 */
+#define OMAP24XX_DMA_MCBSP5_RX          22      /* S_DMA_21 */
+#define OMAP24XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
+#define OMAP24XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
+#define OMAP243X_DMA_EXT_DMAREQ4        25      /* S_DMA_24 */
+#define OMAP243X_DMA_EXT_DMAREQ5        26      /* S_DMA_25 */
+#define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */
+#define OMAP34XX_DMA_I2C3_RX            26      /* S_DMA_25 */
 #define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
 #define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
 #define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
 #define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
-#define OMAP24XX_DMA_MCBSP1_TX          31      /* SDMA_30 */
-#define OMAP24XX_DMA_MCBSP1_RX          32      /* SDMA_31 */
-#define OMAP24XX_DMA_MCBSP2_TX          33      /* SDMA_32 */
-#define OMAP24XX_DMA_MCBSP2_RX          34      /* SDMA_33 */
-#define OMAP24XX_DMA_SPI1_TX0           35      /* SDMA_34 */
-#define OMAP24XX_DMA_SPI1_RX0           36      /* SDMA_35 */
-#define OMAP24XX_DMA_SPI1_TX1           37      /* SDMA_36 */
-#define OMAP24XX_DMA_SPI1_RX1           38      /* SDMA_37 */
-#define OMAP24XX_DMA_SPI1_TX2           39      /* SDMA_38 */
-#define OMAP24XX_DMA_SPI1_RX2           40      /* SDMA_39 */
-#define OMAP24XX_DMA_SPI1_TX3           41      /* SDMA_40 */
-#define OMAP24XX_DMA_SPI1_RX3           42      /* SDMA_41 */
-#define OMAP24XX_DMA_SPI2_TX0           43      /* SDMA_42 */
-#define OMAP24XX_DMA_SPI2_RX0           44      /* SDMA_43 */
-#define OMAP24XX_DMA_SPI2_TX1           45      /* SDMA_44 */
-#define OMAP24XX_DMA_SPI2_RX1           46      /* SDMA_45 */
-
-#define OMAP24XX_DMA_UART1_TX           49      /* SDMA_48 */
-#define OMAP24XX_DMA_UART1_RX           50      /* SDMA_49 */
-#define OMAP24XX_DMA_UART2_TX           51      /* SDMA_50 */
-#define OMAP24XX_DMA_UART2_RX           52      /* SDMA_51 */
-#define OMAP24XX_DMA_UART3_TX           53      /* SDMA_52 */
-#define OMAP24XX_DMA_UART3_RX           54      /* SDMA_53 */
-#define OMAP24XX_DMA_USB_W2FC_TX0       55      /* SDMA_54 */
-#define OMAP24XX_DMA_USB_W2FC_RX0       56      /* SDMA_55 */
-#define OMAP24XX_DMA_USB_W2FC_TX1       57      /* SDMA_56 */
-#define OMAP24XX_DMA_USB_W2FC_RX1       58      /* SDMA_57 */
-#define OMAP24XX_DMA_USB_W2FC_TX2       59      /* SDMA_58 */
-#define OMAP24XX_DMA_USB_W2FC_RX2       60      /* SDMA_59 */
-#define OMAP24XX_DMA_MMC1_TX            61      /* SDMA_60 */
-#define OMAP24XX_DMA_MMC1_RX            62      /* SDMA_61 */
-#define OMAP24XX_DMA_MS                 63      /* SDMA_62 */
-#define OMAP24XX_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
+#define OMAP24XX_DMA_MCBSP1_TX          31      /* S_DMA_30 */
+#define OMAP24XX_DMA_MCBSP1_RX          32      /* S_DMA_31 */
+#define OMAP24XX_DMA_MCBSP2_TX          33      /* S_DMA_32 */
+#define OMAP24XX_DMA_MCBSP2_RX          34      /* S_DMA_33 */
+#define OMAP24XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
+#define OMAP24XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
+#define OMAP24XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
+#define OMAP24XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
+#define OMAP24XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
+#define OMAP24XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
+#define OMAP24XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
+#define OMAP24XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
+#define OMAP24XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
+#define OMAP24XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
+#define OMAP24XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
+#define OMAP24XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
+#define OMAP24XX_DMA_MMC2_TX            47      /* S_DMA_46 */
+#define OMAP24XX_DMA_MMC2_RX            48      /* S_DMA_47 */
+#define OMAP24XX_DMA_UART1_TX           49      /* S_DMA_48 */
+#define OMAP24XX_DMA_UART1_RX           50      /* S_DMA_49 */
+#define OMAP24XX_DMA_UART2_TX           51      /* S_DMA_50 */
+#define OMAP24XX_DMA_UART2_RX           52      /* S_DMA_51 */
+#define OMAP24XX_DMA_UART3_TX           53      /* S_DMA_52 */
+#define OMAP24XX_DMA_UART3_RX           54      /* S_DMA_53 */
+#define OMAP24XX_DMA_USB_W2FC_TX0       55      /* S_DMA_54 */
+#define OMAP24XX_DMA_USB_W2FC_RX0       56      /* S_DMA_55 */
+#define OMAP24XX_DMA_USB_W2FC_TX1       57      /* S_DMA_56 */
+#define OMAP24XX_DMA_USB_W2FC_RX1       58      /* S_DMA_57 */
+#define OMAP24XX_DMA_USB_W2FC_TX2       59      /* S_DMA_58 */
+#define OMAP24XX_DMA_USB_W2FC_RX2       60      /* S_DMA_59 */
+#define OMAP24XX_DMA_MMC1_TX            61      /* S_DMA_60 */
+#define OMAP24XX_DMA_MMC1_RX            62      /* S_DMA_61 */
+#define OMAP24XX_DMA_MS                 63      /* S_DMA_62 */
+#define OMAP242X_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
+#define OMAP243X_DMA_EXT_DMAREQ6        64      /* S_DMA_63 */
+#define OMAP34XX_DMA_EXT_DMAREQ3        64      /* S_DMA_63 */
+#define OMAP34XX_DMA_AES2_TX            65      /* S_DMA_64 */
+#define OMAP34XX_DMA_AES2_RX            66      /* S_DMA_65 */
+#define OMAP34XX_DMA_DES2_TX            67      /* S_DMA_66 */
+#define OMAP34XX_DMA_DES2_RX            68      /* S_DMA_67 */
+#define OMAP34XX_DMA_SHA1MD5_RX         69      /* S_DMA_68 */
+#define OMAP34XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
+#define OMAP34XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
+#define OMAP34XX_DSS_DMA0               72      /* S_DMA_71 */
+#define OMAP34XX_DSS_DMA1               73      /* S_DMA_72 */
+#define OMAP34XX_DSS_DMA2               74      /* S_DMA_73 */
+#define OMAP34XX_DSS_DMA3               75      /* S_DMA_74 */
+#define OMAP34XX_DMA_MMC3_TX            77      /* S_DMA_76 */
+#define OMAP34XX_DMA_MMC3_RX            78      /* S_DMA_77 */
+#define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
+#define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
 
 /*----------------------------------------------------------------------------*/
 
@@ -358,6 +413,11 @@ enum omap_dma_burst_mode {
         OMAP_DMA_DATA_BURST_16,
 };
 
+enum end_type {
+        OMAP_DMA_LITTLE_ENDIAN = 0,
+        OMAP_DMA_BIG_ENDIAN
+};
+
 enum omap_dma_color_mode {
         OMAP_DMA_COLOR_DIS = 0,
         OMAP_DMA_CONSTANT_FILL,
@@ -370,24 +430,34 @@ enum omap_dma_write_mode {
         OMAP_DMA_WRITE_LAST_NON_POSTED
 };
 
+enum omap_dma_channel_mode {
+        OMAP_DMA_LCH_2D = 0,
+        OMAP_DMA_LCH_G,
+        OMAP_DMA_LCH_P,
+        OMAP_DMA_LCH_PD
+};
+
 struct omap_dma_channel_params {
         int data_type;          /* data type 8,16,32 */
         int elem_count;         /* number of elements in a frame */
         int frame_count;        /* number of frames in a element */
 
         int src_port;           /* Only on OMAP1 REVISIT: Is this needed? */
-        int src_amode;          /* constant , post increment, indexed , double indexed */
+        int src_amode;          /* constant, post increment, indexed,
+                                        double indexed */
         unsigned long src_start;        /* source address : physical */
         int src_ei;             /* source element index */
         int src_fi;             /* source frame index */
 
         int dst_port;           /* Only on OMAP1 REVISIT: Is this needed? */
-        int dst_amode;          /* constant , post increment, indexed , double indexed */
+        int dst_amode;          /* constant, post increment, indexed,
+                                        double indexed */
         unsigned long dst_start;        /* source address : physical */
         int dst_ei;             /* source element index */
         int dst_fi;             /* source frame index */
 
-        int trigger;            /* trigger attached if the channel is synchronized */
+        int trigger;            /* trigger attached if the channel is
+                                        synchronized */
         int sync_mode;          /* sycn on element, frame , block or packet */
         int src_or_dst_synch;   /* source synch(1) or destination synch(0) */
 
@@ -404,8 +474,8 @@ struct omap_dma_channel_params {
 
 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
 extern int omap_request_dma(int dev_id, const char *dev_name,
-                            void (* callback)(int lch, u16 ch_status, void *data),
-                            void *data, int *dma_ch);
+                        void (*callback)(int lch, u16 ch_status, void *data),
+                        void *data, int *dma_ch);
 extern void omap_enable_dma_irq(int ch, u16 irq_bits);
 extern void omap_disable_dma_irq(int ch, u16 irq_bits);
 extern void omap_free_dma(int ch);
@@ -418,6 +488,7 @@ extern void omap_set_dma_transfer_params(int lch, int data_type,
 extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
                                     u32 color);
 extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
+extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
 
 extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
                                     unsigned long src_start,
@@ -436,23 +507,26 @@ extern void omap_set_dma_dest_burst_mode(int lch,
                                          enum omap_dma_burst_mode burst_mode);
 
 extern void omap_set_dma_params(int lch,
-                                struct omap_dma_channel_params * params);
+                                struct omap_dma_channel_params *params);
 
-extern void omap_dma_link_lch (int lch_head, int lch_queue);
-extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
+extern void omap_dma_link_lch(int lch_head, int lch_queue);
+extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
 
 extern int omap_set_dma_callback(int lch,
-                        void (* callback)(int lch, u16 ch_status, void *data),
+                        void (*callback)(int lch, u16 ch_status, void *data),
                         void *data);
 extern dma_addr_t omap_get_dma_src_pos(int lch);
 extern dma_addr_t omap_get_dma_dst_pos(int lch);
-extern int omap_get_dma_src_addr_counter(int lch);
 extern void omap_clear_dma(int lch);
+extern int omap_get_dma_active_status(int lch);
 extern int omap_dma_running(void);
 extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
                                        int tparams);
 extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
                                  unsigned char write_prio);
+extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
+extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
+extern int omap_get_dma_index(int lch, int *ei, int *fi);
 
 /* Chaining APIs */
 #ifndef CONFIG_ARCH_OMAP1
@@ -478,7 +552,7 @@ extern int omap_dma_chain_status(int chain_id);
 #endif
 
 /* LCD DMA functions */
-extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
+extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
                                 void *data);
 extern void omap_free_lcd_dma(void);
 extern void omap_setup_lcd_dma(void);
diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h
index fefb276ed402..02b29e8437ae 100644
--- a/include/asm-arm/arch-omap/dmtimer.h
+++ b/include/asm-arm/arch-omap/dmtimer.h
@@ -66,6 +66,7 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer);
 
 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
+void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
diff --git a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h
index 6a883e0bdbb8..f420881d2a3b 100644
--- a/include/asm-arm/arch-omap/fpga.h
+++ b/include/asm-arm/arch-omap/fpga.h
@@ -169,30 +169,29 @@ struct h2p2_dbg_fpga {
 #define OMAP1510_INT_FPGA               (IH_GPIO_BASE + 13)
 
 /* IRQ Numbers for interrupts muxed through the FPGA */
-#define OMAP1510_IH_FPGA_BASE           IH_BOARD_BASE
-#define OMAP1510_INT_FPGA_ATN           (OMAP1510_IH_FPGA_BASE + 0)
-#define OMAP1510_INT_FPGA_ACK           (OMAP1510_IH_FPGA_BASE + 1)
-#define OMAP1510_INT_FPGA2              (OMAP1510_IH_FPGA_BASE + 2)
-#define OMAP1510_INT_FPGA3              (OMAP1510_IH_FPGA_BASE + 3)
-#define OMAP1510_INT_FPGA4              (OMAP1510_IH_FPGA_BASE + 4)
-#define OMAP1510_INT_FPGA5              (OMAP1510_IH_FPGA_BASE + 5)
-#define OMAP1510_INT_FPGA6              (OMAP1510_IH_FPGA_BASE + 6)
-#define OMAP1510_INT_FPGA7              (OMAP1510_IH_FPGA_BASE + 7)
-#define OMAP1510_INT_FPGA8              (OMAP1510_IH_FPGA_BASE + 8)
-#define OMAP1510_INT_FPGA9              (OMAP1510_IH_FPGA_BASE + 9)
-#define OMAP1510_INT_FPGA10             (OMAP1510_IH_FPGA_BASE + 10)
-#define OMAP1510_INT_FPGA11             (OMAP1510_IH_FPGA_BASE + 11)
-#define OMAP1510_INT_FPGA12             (OMAP1510_IH_FPGA_BASE + 12)
-#define OMAP1510_INT_ETHER              (OMAP1510_IH_FPGA_BASE + 13)
-#define OMAP1510_INT_FPGAUART1          (OMAP1510_IH_FPGA_BASE + 14)
-#define OMAP1510_INT_FPGAUART2          (OMAP1510_IH_FPGA_BASE + 15)
-#define OMAP1510_INT_FPGA_TS            (OMAP1510_IH_FPGA_BASE + 16)
-#define OMAP1510_INT_FPGA17             (OMAP1510_IH_FPGA_BASE + 17)
-#define OMAP1510_INT_FPGA_CAM           (OMAP1510_IH_FPGA_BASE + 18)
-#define OMAP1510_INT_FPGA_RTC_A         (OMAP1510_IH_FPGA_BASE + 19)
-#define OMAP1510_INT_FPGA_RTC_B         (OMAP1510_IH_FPGA_BASE + 20)
-#define OMAP1510_INT_FPGA_CD            (OMAP1510_IH_FPGA_BASE + 21)
-#define OMAP1510_INT_FPGA22             (OMAP1510_IH_FPGA_BASE + 22)
-#define OMAP1510_INT_FPGA23             (OMAP1510_IH_FPGA_BASE + 23)
+#define OMAP1510_INT_FPGA_ATN           (OMAP_FPGA_IRQ_BASE + 0)
+#define OMAP1510_INT_FPGA_ACK           (OMAP_FPGA_IRQ_BASE + 1)
+#define OMAP1510_INT_FPGA2              (OMAP_FPGA_IRQ_BASE + 2)
+#define OMAP1510_INT_FPGA3              (OMAP_FPGA_IRQ_BASE + 3)
+#define OMAP1510_INT_FPGA4              (OMAP_FPGA_IRQ_BASE + 4)
+#define OMAP1510_INT_FPGA5              (OMAP_FPGA_IRQ_BASE + 5)
+#define OMAP1510_INT_FPGA6              (OMAP_FPGA_IRQ_BASE + 6)
+#define OMAP1510_INT_FPGA7              (OMAP_FPGA_IRQ_BASE + 7)
+#define OMAP1510_INT_FPGA8              (OMAP_FPGA_IRQ_BASE + 8)
+#define OMAP1510_INT_FPGA9              (OMAP_FPGA_IRQ_BASE + 9)
+#define OMAP1510_INT_FPGA10             (OMAP_FPGA_IRQ_BASE + 10)
+#define OMAP1510_INT_FPGA11             (OMAP_FPGA_IRQ_BASE + 11)
+#define OMAP1510_INT_FPGA12             (OMAP_FPGA_IRQ_BASE + 12)
+#define OMAP1510_INT_ETHER              (OMAP_FPGA_IRQ_BASE + 13)
+#define OMAP1510_INT_FPGAUART1          (OMAP_FPGA_IRQ_BASE + 14)
+#define OMAP1510_INT_FPGAUART2          (OMAP_FPGA_IRQ_BASE + 15)
+#define OMAP1510_INT_FPGA_TS            (OMAP_FPGA_IRQ_BASE + 16)
+#define OMAP1510_INT_FPGA17             (OMAP_FPGA_IRQ_BASE + 17)
+#define OMAP1510_INT_FPGA_CAM           (OMAP_FPGA_IRQ_BASE + 18)
+#define OMAP1510_INT_FPGA_RTC_A         (OMAP_FPGA_IRQ_BASE + 19)
+#define OMAP1510_INT_FPGA_RTC_B         (OMAP_FPGA_IRQ_BASE + 20)
+#define OMAP1510_INT_FPGA_CD            (OMAP_FPGA_IRQ_BASE + 21)
+#define OMAP1510_INT_FPGA22             (OMAP_FPGA_IRQ_BASE + 22)
+#define OMAP1510_INT_FPGA23             (OMAP_FPGA_IRQ_BASE + 23)
 
 #endif
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index 91d85b3417b7..45fdfccbd5d4 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -284,6 +284,7 @@
 #include "omap1510.h"
 #include "omap24xx.h"
 #include "omap16xx.h"
+#include "omap34xx.h"
 
 #ifndef __ASSEMBLER__
 
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 160578e1f557..0b13557fd30b 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -60,6 +60,7 @@
 #define IO_SIZE         0x40000
 #define IO_VIRT         (IO_PHYS - IO_OFFSET)
 #define IO_ADDRESS(pa)  ((pa) - IO_OFFSET)
+#define OMAP1_IO_ADDRESS(pa)    ((pa) - IO_OFFSET)
 #define io_p2v(pa)      ((pa) - IO_OFFSET)
 #define io_v2p(va)      ((va) + IO_OFFSET)
 
@@ -91,6 +92,7 @@
 
 #define IO_OFFSET       0x90000000
 #define IO_ADDRESS(pa)  ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
+#define OMAP2_IO_ADDRESS(pa)    ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
 #define io_p2v(pa)      ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
 #define io_v2p(va)      ((va) - IO_OFFSET)      /* Works for L3 and L4 */
 
@@ -148,6 +150,7 @@
 
 #define IO_OFFSET               0x90000000
 #define IO_ADDRESS(pa)          ((pa) + IO_OFFSET)/* Works for L3 and L4 */
+#define OMAP2_IO_ADDRESS(pa)    ((pa) + IO_OFFSET)/* Works for L3 and L4 */
 #define io_p2v(pa)              ((pa) + IO_OFFSET)/* Works for L3 and L4 */
 #define io_v2p(va)              ((va) - IO_OFFSET)/* Works for L3 and L4 */
 
@@ -183,35 +186,12 @@
 #define omap_writew(v,a)        (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
 #define omap_writel(v,a)        (*(volatile unsigned int   *)IO_ADDRESS(a) = (v))
 
-/* 16 bit uses LDRH/STRH, base +/- offset_8 */
-typedef struct { volatile u16 offset[256]; } __regbase16;
-#define __REGV16(vaddr)         ((__regbase16 *)((vaddr)&~0xff)) \
-                                        ->offset[((vaddr)&0xff)>>1]
-#define __REG16(paddr)          __REGV16(io_p2v(paddr))
-
-/* 8/32 bit uses LDR/STR, base +/- offset_12 */
-typedef struct { volatile u8 offset[4096]; } __regbase8;
-#define __REGV8(vaddr)          ((__regbase8  *)((vaddr)&~4095)) \
-                                        ->offset[((vaddr)&4095)>>0]
-#define __REG8(paddr)           __REGV8(io_p2v(paddr))
-
-typedef struct { volatile u32 offset[4096]; } __regbase32;
-#define __REGV32(vaddr)         ((__regbase32 *)((vaddr)&~4095)) \
-                                        ->offset[((vaddr)&4095)>>2]
-#define __REG32(paddr)          __REGV32(io_p2v(paddr))
-
 extern void omap1_map_common_io(void);
 extern void omap1_init_common_hw(void);
 
 extern void omap2_map_common_io(void);
 extern void omap2_init_common_hw(void);
 
-#else
-
-#define __REG8(paddr)           io_p2v(paddr)
-#define __REG16(paddr)          io_p2v(paddr)
-#define __REG32(paddr)          io_p2v(paddr)
-
 #endif
 
 #endif
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 87973654e625..7464c694859b 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -285,7 +285,41 @@
 #define OMAP_MAX_GPIO_LINES     192
 #define IH_GPIO_BASE            (128 + IH2_BASE)
 #define IH_MPUIO_BASE           (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
-#define IH_BOARD_BASE           (16 + IH_MPUIO_BASE)
+#define OMAP_IRQ_END            (IH_MPUIO_BASE + 16)
+
+/* External FPGA handles interrupts on Innovator boards */
+#define OMAP_FPGA_IRQ_BASE      (OMAP_IRQ_END)
+#ifdef  CONFIG_MACH_OMAP_INNOVATOR
+#define OMAP_FPGA_NR_IRQS       24
+#else
+#define OMAP_FPGA_NR_IRQS       0
+#endif
+#define OMAP_FPGA_IRQ_END       (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
+
+/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
+#define TWL4030_IRQ_BASE        (OMAP_FPGA_IRQ_END)
+#ifdef  CONFIG_TWL4030_CORE
+#define TWL4030_BASE_NR_IRQS    8
+#define TWL4030_PWR_NR_IRQS     8
+#else
+#define TWL4030_BASE_NR_IRQS    0
+#define TWL4030_PWR_NR_IRQS     0
+#endif
+#define TWL4030_IRQ_END         (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
+#define TWL4030_PWR_IRQ_BASE    TWL4030_IRQ_END
+#define TWL4030_PWR_IRQ_END     (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
+
+/* External TWL4030 gpio interrupts are optional */
+#define TWL4030_GPIO_IRQ_BASE   TWL4030_PWR_IRQ_END
+#ifdef  CONFIG_TWL4030_GPIO
+#define TWL4030_GPIO_NR_IRQS    18
+#else
+#define TWL4030_GPIO_NR_IRQS    0
+#endif
+#define TWL4030_GPIO_IRQ_END    (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
+
+/* Total number of interrupts depends on the enabled blocks above */
+#define NR_IRQS                 TWL4030_GPIO_IRQ_END
 
 #define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
 
@@ -293,14 +327,6 @@
 extern void omap_init_irq(void);
 #endif
 
-/*
- * The definition of NR_IRQS is in board-specific header file, which is
- * included via hardware.h
- */
 #include <asm/hardware.h>
 
-#ifndef NR_IRQS
-#define NR_IRQS                 IH_BOARD_BASE
-#endif
-
 #endif
diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h
index c7a0cc1c4e93..26c78f67dc8e 100644
--- a/include/asm-arm/arch-omap/mcbsp.h
+++ b/include/asm-arm/arch-omap/mcbsp.h
@@ -24,7 +24,11 @@
 #ifndef __ASM_ARCH_OMAP_MCBSP_H
 #define __ASM_ARCH_OMAP_MCBSP_H
 
+#include <linux/completion.h>
+#include <linux/spinlock.h>
+
 #include <asm/hardware.h>
+#include <asm/arch/clock.h>
 
 #define OMAP730_MCBSP1_BASE     0xfffb1000
 #define OMAP730_MCBSP2_BASE     0xfffb1800
@@ -40,6 +44,9 @@
 #define OMAP24XX_MCBSP1_BASE    0x48074000
 #define OMAP24XX_MCBSP2_BASE    0x48076000
 
+#define OMAP34XX_MCBSP1_BASE    0x48074000
+#define OMAP34XX_MCBSP2_BASE    0x49022000
+
 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
 
 #define OMAP_MCBSP_REG_DRR2     0x00
@@ -74,7 +81,8 @@
 #define OMAP_MCBSP_REG_XCERG    0x3A
 #define OMAP_MCBSP_REG_XCERH    0x3C
 
-#define OMAP_MAX_MCBSP_COUNT 3
+#define OMAP_MAX_MCBSP_COUNT    3
+#define MAX_MCBSP_CLOCKS        3
 
 #define AUDIO_MCBSP_DATAWRITE   (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
 #define AUDIO_MCBSP_DATAREAD    (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
@@ -117,7 +125,8 @@
 #define OMAP_MCBSP_REG_XCERG    0x74
 #define OMAP_MCBSP_REG_XCERH    0x78
 
-#define OMAP_MAX_MCBSP_COUNT 2
+#define OMAP_MAX_MCBSP_COUNT    2
+#define MAX_MCBSP_CLOCKS        2
 
 #define AUDIO_MCBSP_DATAWRITE   (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
 #define AUDIO_MCBSP_DATAREAD    (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
@@ -298,6 +307,55 @@ struct omap_mcbsp_spi_cfg {
         omap_mcbsp_word_length          word_length;
 };
 
+/* Platform specific configuration */
+struct omap_mcbsp_ops {
+        void (*request)(unsigned int);
+        void (*free)(unsigned int);
+        int (*check)(unsigned int);
+};
+
+struct omap_mcbsp_platform_data {
+        u32 virt_base;
+        u8 dma_rx_sync, dma_tx_sync;
+        u16 rx_irq, tx_irq;
+        struct omap_mcbsp_ops *ops;
+        char const *clk_name;
+};
+
+struct omap_mcbsp {
+        struct device *dev;
+        u32 io_base;
+        u8 id;
+        u8 free;
+        omap_mcbsp_word_length rx_word_length;
+        omap_mcbsp_word_length tx_word_length;
+
+        omap_mcbsp_io_type_t io_type; /* IRQ or poll */
+        /* IRQ based TX/RX */
+        int rx_irq;
+        int tx_irq;
+
+        /* DMA stuff */
+        u8 dma_rx_sync;
+        short dma_rx_lch;
+        u8 dma_tx_sync;
+        short dma_tx_lch;
+
+        /* Completion queues */
+        struct completion tx_irq_completion;
+        struct completion rx_irq_completion;
+        struct completion tx_dma_completion;
+        struct completion rx_dma_completion;
+
+        /* Protect the field .free, while checking if the mcbsp is in use */
+        spinlock_t lock;
+        struct omap_mcbsp_platform_data *pdata;
+        struct clk *clk;
+};
+
+int omap_mcbsp_init(void);
+void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
+                                        int size);
 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
 int omap_mcbsp_request(unsigned int id);
 void omap_mcbsp_free(unsigned int id);
diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h
new file mode 100644
index 000000000000..aa30c6d10abd
--- /dev/null
+++ b/include/asm-arm/arch-omap/omap34xx.h
@@ -0,0 +1,72 @@
+/*
+ * include/asm-arm/arch-omap/omap34xx.h
+ *
+ * This file contains the processor specific definitions of the TI OMAP34XX.
+ *
+ * Copyright (C) 2007 Texas Instruments.
+ * Copyright (C) 2007 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_OMAP34XX_H
+#define __ASM_ARCH_OMAP34XX_H
+
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers.
+ */
+
+#define L4_34XX_BASE            0x48000000
+#define L4_WK_34XX_BASE         0x48300000
+#define L4_WK_OMAP_BASE         L4_WK_34XX_BASE
+#define L4_PER_34XX_BASE        0x49000000
+#define L4_PER_OMAP_BASE        L4_PER_34XX_BASE
+#define L4_EMU_34XX_BASE        0x54000000
+#define L4_EMU_BASE             L4_EMU_34XX_BASE
+#define L3_34XX_BASE            0x68000000
+#define L3_OMAP_BASE            L3_34XX_BASE
+
+#define OMAP3430_32KSYNCT_BASE  0x48320000
+#define OMAP3430_CM_BASE        0x48004800
+#define OMAP3430_PRM_BASE       0x48306800
+#define OMAP343X_SMS_BASE       0x6C000000
+#define OMAP343X_SDRC_BASE      0x6D000000
+#define OMAP34XX_GPMC_BASE      0x6E000000
+#define OMAP343X_SCM_BASE       0x48002000
+#define OMAP343X_CTRL_BASE      OMAP343X_SCM_BASE
+
+#define OMAP34XX_IC_BASE        0x48200000
+#define OMAP34XX_IVA_INTC_BASE  0x40000000
+#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
+#define OMAP34XX_HSUSB_HOST_BASE        (L4_34XX_BASE + 0x64000)
+#define OMAP34XX_USBTLL_BASE    (L4_34XX_BASE + 0x62000)
+
+
+#if defined(CONFIG_ARCH_OMAP3430)
+
+#define OMAP2_32KSYNCT_BASE             OMAP3430_32KSYNCT_BASE
+#define OMAP2_CM_BASE                   OMAP3430_CM_BASE
+#define OMAP2_PRM_BASE                  OMAP3430_PRM_BASE
+#define OMAP2_VA_IC_BASE                IO_ADDRESS(OMAP34XX_IC_BASE)
+
+#endif
+
+#define OMAP34XX_DSP_BASE       0x58000000
+#define OMAP34XX_DSP_MEM_BASE   (OMAP34XX_DSP_BASE + 0x0)
+#define OMAP34XX_DSP_IPI_BASE   (OMAP34XX_DSP_BASE + 0x1000000)
+#define OMAP34XX_DSP_MMU_BASE   (OMAP34XX_DSP_BASE + 0x2000000)
+#endif /* __ASM_ARCH_OMAP34XX_H */
+
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h
index bb9bb3fd532f..be59f4a9828b 100644
--- a/include/asm-arm/arch-omap/sram.h
+++ b/include/asm-arm/arch-omap/sram.h
@@ -11,6 +11,7 @@
 #ifndef __ARCH_ARM_OMAP_SRAM_H
 #define __ARCH_ARM_OMAP_SRAM_H
 
+extern int __init omap_sram_init(void);
 extern void * omap_sram_push(void * start, unsigned long size);
 extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
 
@@ -21,17 +22,35 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 
 /* Do not use these */
-extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl);
-extern unsigned long sram_reprogram_clock_sz;
+extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+extern unsigned long omap1_sram_reprogram_clock_sz;
 
-extern void sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-                          u32 base_cs, u32 force_unlock);
-extern unsigned long sram_ddr_init_sz;
+extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+extern unsigned long omap24xx_sram_reprogram_clock_sz;
 
-extern u32 sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
-extern unsigned long sram_set_prcm_sz;
+extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                                u32 base_cs, u32 force_unlock);
+extern unsigned long omap242x_sram_ddr_init_sz;
 
-extern void sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type);
-extern unsigned long sram_reprogram_sdrc_sz;
+extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
+                                                int bypass);
+extern unsigned long omap242x_sram_set_prcm_sz;
+
+extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                                u32 mem_type);
+extern unsigned long omap242x_sram_reprogram_sdrc_sz;
+
+
+extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                                u32 base_cs, u32 force_unlock);
+extern unsigned long omap243x_sram_ddr_init_sz;
+
+extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
+                                                int bypass);
+extern unsigned long omap243x_sram_set_prcm_sz;
+
+extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                                u32 mem_type);
+extern unsigned long omap243x_sram_reprogram_sdrc_sz;
 
 #endif
diff --git a/include/asm-arm/arch-omap/tc.h b/include/asm-arm/arch-omap/tc.h
index 8ded218cbea5..65a9c82d3bf7 100644
--- a/include/asm-arm/arch-omap/tc.h
+++ b/include/asm-arm/arch-omap/tc.h
@@ -75,16 +75,14 @@
 #ifndef __ASSEMBLER__
 
 /* EMIF Slow Interface Configuration Register */
-#define OMAP_EMIFS_CONFIG_REG   __REG32(EMIFS_CONFIG)
-
 #define OMAP_EMIFS_CONFIG_FR            (1 << 4)
 #define OMAP_EMIFS_CONFIG_PDE           (1 << 3)
 #define OMAP_EMIFS_CONFIG_PWD_EN        (1 << 2)
 #define OMAP_EMIFS_CONFIG_BM            (1 << 1)
 #define OMAP_EMIFS_CONFIG_WP            (1 << 0)
 
-#define EMIFS_CCS(n)            __REG32(EMIFS_CS0_CONFIG + (4 * (n)))
-#define EMIFS_ACS(n)            __REG32(EMIFS_ACS0 + (4 * (n)))
+#define EMIFS_CCS(n)            (EMIFS_CS0_CONFIG + (4 * (n)))
+#define EMIFS_ACS(n)            (EMIFS_ACS0 + (4 * (n)))
 
 /* Almost all documentation for chip and board memory maps assumes
  * BM is clear.  Most devel boards have a switch to control booting
@@ -93,13 +91,13 @@
  */
 static inline u32 omap_cs0_phys(void)
 {
-        return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM)
+        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
                         ?  OMAP_CS3_PHYS : 0;
 }
 
 static inline u32 omap_cs3_phys(void)
 {
-        return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM)
+        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
                         ? 0 : OMAP_CS3_PHYS;
 }
 
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
index 2147d18aaeae..ddf1861e6df9 100644
--- a/include/asm-arm/arch-omap/usb.h
+++ b/include/asm-arm/arch-omap/usb.h
@@ -34,11 +34,8 @@
 /*
  * OTG and transceiver registers, for OMAPs starting with ARM926
  */
-#define OTG_REG32(offset)               __REG32(OTG_BASE + (offset))
-#define OTG_REG16(offset)               __REG16(OTG_BASE + (offset))
-
-#define OTG_REV_REG                     OTG_REG32(0x00)
-#define OTG_SYSCON_1_REG                OTG_REG32(0x04)
+#define OTG_REV                         (OTG_BASE + 0x00)
+#define OTG_SYSCON_1                    (OTG_BASE + 0x04)
 #       define   USB2_TRX_MODE(w)       (((w)>>24)&0x07)
 #       define   USB1_TRX_MODE(w)       (((w)>>20)&0x07)
 #       define   USB0_TRX_MODE(w)       (((w)>>16)&0x07)
@@ -47,7 +44,7 @@
 #       define   DEV_IDLE_EN            (1 << 13)
 #       define   OTG_RESET_DONE         (1 << 2)
 #       define   OTG_SOFT_RESET         (1 << 1)
-#define OTG_SYSCON_2_REG                OTG_REG32(0x08)
+#define OTG_SYSCON_2                    (OTG_BASE + 0x08)
 #       define   OTG_EN                 (1 << 31)
 #       define   USBX_SYNCHRO           (1 << 30)
 #       define   OTG_MST16              (1 << 29)
@@ -65,7 +62,7 @@
 #       define   HMC_TLLSPEED           (1 << 7)
 #       define   HMC_TLLATTACH          (1 << 6)
 #       define   OTG_HMC(w)             (((w)>>0)&0x3f)
-#define OTG_CTRL_REG                    OTG_REG32(0x0c)
+#define OTG_CTRL                        (OTG_BASE + 0x0c)
 #       define   OTG_USB2_EN            (1 << 29)
 #       define   OTG_USB2_DP            (1 << 28)
 #       define   OTG_USB2_DM            (1 << 27)
@@ -92,7 +89,7 @@
 #       define   OTG_PD_VBUS            (1 << 2)
 #       define   OTG_PU_VBUS            (1 << 1)
 #       define   OTG_PU_ID              (1 << 0)
-#define OTG_IRQ_EN_REG                  OTG_REG16(0x10)
+#define OTG_IRQ_EN                      (OTG_BASE + 0x10)       /* 16-bit */
 #       define   DRIVER_SWITCH          (1 << 15)
 #       define   A_VBUS_ERR             (1 << 13)
 #       define   A_REQ_TMROUT           (1 << 12)
@@ -102,9 +99,9 @@
 #       define   B_SRP_DONE             (1 << 8)
 #       define   B_SRP_STARTED          (1 << 7)
 #       define   OPRT_CHG               (1 << 0)
-#define OTG_IRQ_SRC_REG                 OTG_REG16(0x14)
+#define OTG_IRQ_SRC                     (OTG_BASE + 0x14)       /* 16-bit */
         // same bits as in IRQ_EN
-#define OTG_OUTCTRL_REG                 OTG_REG16(0x18)
+#define OTG_OUTCTRL                     (OTG_BASE + 0x18)       /* 16-bit */
 #       define   OTGVPD                 (1 << 14)
 #       define   OTGVPU                 (1 << 13)
 #       define   OTGPUID                (1 << 12)
@@ -117,13 +114,13 @@
 #       define   USB0VDR                (1 << 2)
 #       define   USB0PDEN               (1 << 1)
 #       define   USB0PUEN               (1 << 0)
-#define OTG_TEST_REG                    OTG_REG16(0x20)
-#define OTG_VENDOR_CODE_REG             OTG_REG32(0xfc)
+#define OTG_TEST                        (OTG_BASE + 0x20)       /* 16-bit */
+#define OTG_VENDOR_CODE                 (OTG_BASE + 0xfc)       /* 16-bit */
 
 /*-------------------------------------------------------------------------*/
 
 /* OMAP1 */
-#define USB_TRANSCEIVER_CTRL_REG        __REG32(0xfffe1000 + 0x0064)
+#define USB_TRANSCEIVER_CTRL            (0xfffe1000 + 0x0064)
 #       define  CONF_USB2_UNI_R         (1 << 8)
 #       define  CONF_USB1_UNI_R         (1 << 7)
 #       define  CONF_USB_PORT0_R(x)     (((x)>>4)&0x7)
diff --git a/include/asm-arm/arch-orion5x/io.h b/include/asm-arm/arch-orion5x/io.h
index 50f8c8802206..59f1bc96a23b 100644
--- a/include/asm-arm/arch-orion5x/io.h
+++ b/include/asm-arm/arch-orion5x/io.h
@@ -14,7 +14,6 @@
 #include "orion5x.h"
 
 #define IO_SPACE_LIMIT          0xffffffff
-#define IO_SPACE_REMAP          ORION5X_PCI_SYS_IO_BASE
 
 static inline void __iomem *
 __arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
@@ -53,15 +52,12 @@ static inline void __iomem *__io(unsigned long addr)
 /*****************************************************************************
  * Helpers to access Orion registers
  ****************************************************************************/
-#define orion5x_read(r)         __raw_readl(r)
-#define orion5x_write(r, val)   __raw_writel(val, r)
-
 /*
  * These are not preempt-safe.  Locks, if needed, must be taken
  * care of by the caller.
  */
-#define orion5x_setbits(r, mask)        orion5x_write((r), orion5x_read(r) | (mask))
-#define orion5x_clrbits(r, mask)        orion5x_write((r), orion5x_read(r) & ~(mask))
+#define orion5x_setbits(r, mask)        writel(readl(r) | (mask), (r))
+#define orion5x_clrbits(r, mask)        writel(readl(r) & ~(mask), (r))
 
 
 #endif
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h
index 206ddd71e193..10257f5c5e9e 100644
--- a/include/asm-arm/arch-orion5x/orion5x.h
+++ b/include/asm-arm/arch-orion5x/orion5x.h
@@ -2,7 +2,7 @@
  * include/asm-arm/arch-orion5x/orion5x.h
  *
  * Generic definitions of Orion SoC flavors:
- *  Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
+ *  Orion-1, Orion-VoIP, Orion-NAS, and Orion-2.
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
  *
@@ -63,9 +63,11 @@
 /*******************************************************************************
  * Supported Devices & Revisions
  ******************************************************************************/
-/* Orion-1 (88F5181) */
+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
 #define MV88F5181_DEV_ID        0x5181
 #define MV88F5181_REV_B1        3
+#define MV88F5181L_REV_A0       8
+#define MV88F5181L_REV_A1       9
 /* Orion-NAS (88F5182) */
 #define MV88F5182_DEV_ID        0x5182
 #define MV88F5182_REV_A2        2
@@ -152,6 +154,7 @@
 #define BRIDGE_MASK             ORION5X_BRIDGE_REG(0x114)
 #define  BRIDGE_INT_TIMER0      0x0002
 #define  BRIDGE_INT_TIMER1      0x0004
+#define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
 #define MAIN_IRQ_CAUSE          ORION5X_BRIDGE_REG(0x200)
 #define MAIN_IRQ_MASK           ORION5X_BRIDGE_REG(0x204)
 
diff --git a/include/asm-arm/arch-orion5x/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h
index 5c13d4fafb4e..7548cedf2d76 100644
--- a/include/asm-arm/arch-orion5x/uncompress.h
+++ b/include/asm-arm/arch-orion5x/uncompress.h
@@ -8,23 +8,38 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/serial_reg.h>
 #include <asm/arch/orion5x.h>
 
-#define MV_UART_THR     ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
-#define MV_UART_LSR     ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
-
-#define LSR_THRE        0x20
+#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
 
 static void putc(const char c)
 {
-        int j = 0x1000;
-        while (--j && !(*MV_UART_LSR & LSR_THRE))
+        unsigned char *base = SERIAL_BASE;
+        int i;
+
+        for (i = 0; i < 0x1000; i++) {
+                if (base[UART_LSR << 2] & UART_LSR_THRE)
+                        break;
                 barrier();
-        *MV_UART_THR = c;
+        }
+
+        base[UART_TX << 2] = c;
 }
 
 static void flush(void)
 {
+        unsigned char *base = SERIAL_BASE;
+        unsigned char mask;
+        int i;
+
+        mask = UART_LSR_TEMT | UART_LSR_THRE;
+
+        for (i = 0; i < 0x1000; i++) {
+                if ((base[UART_LSR << 2] & mask) == mask)
+                        break;
+                barrier();
+        }
 }
 
 /*
diff --git a/include/asm-arm/arch-pxa/audio.h b/include/asm-arm/arch-pxa/audio.h
index 52bbe3bc25e1..f82f96dd1053 100644
--- a/include/asm-arm/arch-pxa/audio.h
+++ b/include/asm-arm/arch-pxa/audio.h
@@ -12,4 +12,6 @@ typedef struct {
         void *priv;
 } pxa2xx_audio_ops_t;
 
+extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops);
+
 #endif
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index e25558faa5a4..d9af6dabc899 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -192,15 +192,6 @@ extern int pxa_gpio_get_value(unsigned gpio);
 extern void pxa_gpio_set_value(unsigned gpio, int value);
 
 /*
- * Routine to enable or disable CKEN
- */
-static inline void __deprecated pxa_set_cken(int clock, int enable)
-{
-        extern void __pxa_set_cken(int clock, int enable);
-        __pxa_set_cken(clock, enable);
-}
-
-/*
  * return current memory and LCD clock frequency in units of 10kHz
  */
 extern unsigned int get_memclk_frequency_10khz(void);
diff --git a/include/asm-arm/arch-pxa/irda.h b/include/asm-arm/arch-pxa/irda.h
index 99f4f423a8e1..0a50c3c763df 100644
--- a/include/asm-arm/arch-pxa/irda.h
+++ b/include/asm-arm/arch-pxa/irda.h
@@ -16,4 +16,8 @@ struct pxaficp_platform_data {
 
 extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
 
+#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
+void pxa2xx_transceiver_mode(struct device *dev, int mode);
+#endif
+
 #endif
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 4b2ea1e95c57..dce9308626b7 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -600,418 +600,6 @@
 
 
 /*
- * USB Device Controller
- * PXA25x and PXA27x USB device controller registers are different.
- */
-#if defined(CONFIG_PXA25x)
-
-#define UDC_RES1        __REG(0x40600004)  /* UDC Undocumented - Reserved1 */
-#define UDC_RES2        __REG(0x40600008)  /* UDC Undocumented - Reserved2 */
-#define UDC_RES3        __REG(0x4060000C)  /* UDC Undocumented - Reserved3 */
-
-#define UDCCR           __REG(0x40600000)  /* UDC Control Register */
-#define UDCCR_UDE       (1 << 0)        /* UDC enable */
-#define UDCCR_UDA       (1 << 1)        /* UDC active */
-#define UDCCR_RSM       (1 << 2)        /* Device resume */
-#define UDCCR_RESIR     (1 << 3)        /* Resume interrupt request */
-#define UDCCR_SUSIR     (1 << 4)        /* Suspend interrupt request */
-#define UDCCR_SRM       (1 << 5)        /* Suspend/resume interrupt mask */
-#define UDCCR_RSTIR     (1 << 6)        /* Reset interrupt request */
-#define UDCCR_REM       (1 << 7)        /* Reset interrupt mask */
-
-#define UDCCS0          __REG(0x40600010)  /* UDC Endpoint 0 Control/Status Register */
-#define UDCCS0_OPR      (1 << 0)        /* OUT packet ready */
-#define UDCCS0_IPR      (1 << 1)        /* IN packet ready */
-#define UDCCS0_FTF      (1 << 2)        /* Flush Tx FIFO */
-#define UDCCS0_DRWF     (1 << 3)        /* Device remote wakeup feature */
-#define UDCCS0_SST      (1 << 4)        /* Sent stall */
-#define UDCCS0_FST      (1 << 5)        /* Force stall */
-#define UDCCS0_RNE      (1 << 6)        /* Receive FIFO no empty */
-#define UDCCS0_SA       (1 << 7)        /* Setup active */
-
-/* Bulk IN - Endpoint 1,6,11 */
-#define UDCCS1          __REG(0x40600014)  /* UDC Endpoint 1 (IN) Control/Status Register */
-#define UDCCS6          __REG(0x40600028)  /* UDC Endpoint 6 (IN) Control/Status Register */
-#define UDCCS11         __REG(0x4060003C)  /* UDC Endpoint 11 (IN) Control/Status Register */
-
-#define UDCCS_BI_TFS    (1 << 0)        /* Transmit FIFO service */
-#define UDCCS_BI_TPC    (1 << 1)        /* Transmit packet complete */
-#define UDCCS_BI_FTF    (1 << 2)        /* Flush Tx FIFO */
-#define UDCCS_BI_TUR    (1 << 3)        /* Transmit FIFO underrun */
-#define UDCCS_BI_SST    (1 << 4)        /* Sent stall */
-#define UDCCS_BI_FST    (1 << 5)        /* Force stall */
-#define UDCCS_BI_TSP    (1 << 7)        /* Transmit short packet */
-
-/* Bulk OUT - Endpoint 2,7,12 */
-#define UDCCS2          __REG(0x40600018)  /* UDC Endpoint 2 (OUT) Control/Status Register */
-#define UDCCS7          __REG(0x4060002C)  /* UDC Endpoint 7 (OUT) Control/Status Register */
-#define UDCCS12         __REG(0x40600040)  /* UDC Endpoint 12 (OUT) Control/Status Register */
-
-#define UDCCS_BO_RFS    (1 << 0)        /* Receive FIFO service */
-#define UDCCS_BO_RPC    (1 << 1)        /* Receive packet complete */
-#define UDCCS_BO_DME    (1 << 3)        /* DMA enable */
-#define UDCCS_BO_SST    (1 << 4)        /* Sent stall */
-#define UDCCS_BO_FST    (1 << 5)        /* Force stall */
-#define UDCCS_BO_RNE    (1 << 6)        /* Receive FIFO not empty */
-#define UDCCS_BO_RSP    (1 << 7)        /* Receive short packet */
-
-/* Isochronous IN - Endpoint 3,8,13 */
-#define UDCCS3          __REG(0x4060001C)  /* UDC Endpoint 3 (IN) Control/Status Register */
-#define UDCCS8          __REG(0x40600030)  /* UDC Endpoint 8 (IN) Control/Status Register */
-#define UDCCS13         __REG(0x40600044)  /* UDC Endpoint 13 (IN) Control/Status Register */
-
-#define UDCCS_II_TFS    (1 << 0)        /* Transmit FIFO service */
-#define UDCCS_II_TPC    (1 << 1)        /* Transmit packet complete */
-#define UDCCS_II_FTF    (1 << 2)        /* Flush Tx FIFO */
-#define UDCCS_II_TUR    (1 << 3)        /* Transmit FIFO underrun */
-#define UDCCS_II_TSP    (1 << 7)        /* Transmit short packet */
-
-/* Isochronous OUT - Endpoint 4,9,14 */
-#define UDCCS4          __REG(0x40600020)  /* UDC Endpoint 4 (OUT) Control/Status Register */
-#define UDCCS9          __REG(0x40600034)  /* UDC Endpoint 9 (OUT) Control/Status Register */
-#define UDCCS14         __REG(0x40600048)  /* UDC Endpoint 14 (OUT) Control/Status Register */
-
-#define UDCCS_IO_RFS    (1 << 0)        /* Receive FIFO service */
-#define UDCCS_IO_RPC    (1 << 1)        /* Receive packet complete */
-#define UDCCS_IO_ROF    (1 << 2)        /* Receive overflow */
-#define UDCCS_IO_DME    (1 << 3)        /* DMA enable */
-#define UDCCS_IO_RNE    (1 << 6)        /* Receive FIFO not empty */
-#define UDCCS_IO_RSP    (1 << 7)        /* Receive short packet */
-
-/* Interrupt IN - Endpoint 5,10,15 */
-#define UDCCS5          __REG(0x40600024)  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
-#define UDCCS10         __REG(0x40600038)  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
-#define UDCCS15         __REG(0x4060004C)  /* UDC Endpoint 15 (Interrupt) Control/Status Register */
-
-#define UDCCS_INT_TFS   (1 << 0)        /* Transmit FIFO service */
-#define UDCCS_INT_TPC   (1 << 1)        /* Transmit packet complete */
-#define UDCCS_INT_FTF   (1 << 2)        /* Flush Tx FIFO */
-#define UDCCS_INT_TUR   (1 << 3)        /* Transmit FIFO underrun */
-#define UDCCS_INT_SST   (1 << 4)        /* Sent stall */
-#define UDCCS_INT_FST   (1 << 5)        /* Force stall */
-#define UDCCS_INT_TSP   (1 << 7)        /* Transmit short packet */
-
-#define UFNRH           __REG(0x40600060)  /* UDC Frame Number Register High */
-#define UFNRL           __REG(0x40600064)  /* UDC Frame Number Register Low */
-#define UBCR2           __REG(0x40600068)  /* UDC Byte Count Reg 2 */
-#define UBCR4           __REG(0x4060006c)  /* UDC Byte Count Reg 4 */
-#define UBCR7           __REG(0x40600070)  /* UDC Byte Count Reg 7 */
-#define UBCR9           __REG(0x40600074)  /* UDC Byte Count Reg 9 */
-#define UBCR12          __REG(0x40600078)  /* UDC Byte Count Reg 12 */
-#define UBCR14          __REG(0x4060007c)  /* UDC Byte Count Reg 14 */
-#define UDDR0           __REG(0x40600080)  /* UDC Endpoint 0 Data Register */
-#define UDDR1           __REG(0x40600100)  /* UDC Endpoint 1 Data Register */
-#define UDDR2           __REG(0x40600180)  /* UDC Endpoint 2 Data Register */
-#define UDDR3           __REG(0x40600200)  /* UDC Endpoint 3 Data Register */
-#define UDDR4           __REG(0x40600400)  /* UDC Endpoint 4 Data Register */
-#define UDDR5           __REG(0x406000A0)  /* UDC Endpoint 5 Data Register */
-#define UDDR6           __REG(0x40600600)  /* UDC Endpoint 6 Data Register */
-#define UDDR7           __REG(0x40600680)  /* UDC Endpoint 7 Data Register */
-#define UDDR8           __REG(0x40600700)  /* UDC Endpoint 8 Data Register */
-#define UDDR9           __REG(0x40600900)  /* UDC Endpoint 9 Data Register */
-#define UDDR10          __REG(0x406000C0)  /* UDC Endpoint 10 Data Register */
-#define UDDR11          __REG(0x40600B00)  /* UDC Endpoint 11 Data Register */
-#define UDDR12          __REG(0x40600B80)  /* UDC Endpoint 12 Data Register */
-#define UDDR13          __REG(0x40600C00)  /* UDC Endpoint 13 Data Register */
-#define UDDR14          __REG(0x40600E00)  /* UDC Endpoint 14 Data Register */
-#define UDDR15          __REG(0x406000E0)  /* UDC Endpoint 15 Data Register */
-
-#define UICR0           __REG(0x40600050)  /* UDC Interrupt Control Register 0 */
-
-#define UICR0_IM0       (1 << 0)        /* Interrupt mask ep 0 */
-#define UICR0_IM1       (1 << 1)        /* Interrupt mask ep 1 */
-#define UICR0_IM2       (1 << 2)        /* Interrupt mask ep 2 */
-#define UICR0_IM3       (1 << 3)        /* Interrupt mask ep 3 */
-#define UICR0_IM4       (1 << 4)        /* Interrupt mask ep 4 */
-#define UICR0_IM5       (1 << 5)        /* Interrupt mask ep 5 */
-#define UICR0_IM6       (1 << 6)        /* Interrupt mask ep 6 */
-#define UICR0_IM7       (1 << 7)        /* Interrupt mask ep 7 */
-
-#define UICR1           __REG(0x40600054)  /* UDC Interrupt Control Register 1 */
-
-#define UICR1_IM8       (1 << 0)        /* Interrupt mask ep 8 */
-#define UICR1_IM9       (1 << 1)        /* Interrupt mask ep 9 */
-#define UICR1_IM10      (1 << 2)        /* Interrupt mask ep 10 */
-#define UICR1_IM11      (1 << 3)        /* Interrupt mask ep 11 */
-#define UICR1_IM12      (1 << 4)        /* Interrupt mask ep 12 */
-#define UICR1_IM13      (1 << 5)        /* Interrupt mask ep 13 */
-#define UICR1_IM14      (1 << 6)        /* Interrupt mask ep 14 */
-#define UICR1_IM15      (1 << 7)        /* Interrupt mask ep 15 */
-
-#define USIR0           __REG(0x40600058)  /* UDC Status Interrupt Register 0 */
-
-#define USIR0_IR0       (1 << 0)        /* Interrupt request ep 0 */
-#define USIR0_IR1       (1 << 1)        /* Interrupt request ep 1 */
-#define USIR0_IR2       (1 << 2)        /* Interrupt request ep 2 */
-#define USIR0_IR3       (1 << 3)        /* Interrupt request ep 3 */
-#define USIR0_IR4       (1 << 4)        /* Interrupt request ep 4 */
-#define USIR0_IR5       (1 << 5)        /* Interrupt request ep 5 */
-#define USIR0_IR6       (1 << 6)        /* Interrupt request ep 6 */
-#define USIR0_IR7       (1 << 7)        /* Interrupt request ep 7 */
-
-#define USIR1           __REG(0x4060005C)  /* UDC Status Interrupt Register 1 */
-
-#define USIR1_IR8       (1 << 0)        /* Interrupt request ep 8 */
-#define USIR1_IR9       (1 << 1)        /* Interrupt request ep 9 */
-#define USIR1_IR10      (1 << 2)        /* Interrupt request ep 10 */
-#define USIR1_IR11      (1 << 3)        /* Interrupt request ep 11 */
-#define USIR1_IR12      (1 << 4)        /* Interrupt request ep 12 */
-#define USIR1_IR13      (1 << 5)        /* Interrupt request ep 13 */
-#define USIR1_IR14      (1 << 6)        /* Interrupt request ep 14 */
-#define USIR1_IR15      (1 << 7)        /* Interrupt request ep 15 */
-
-#elif defined(CONFIG_PXA27x)
-
-#define UDCCR           __REG(0x40600000) /* UDC Control Register */
-#define UDCCR_OEN       (1 << 31)       /* On-the-Go Enable */
-#define UDCCR_AALTHNP   (1 << 30)       /* A-device Alternate Host Negotiation
-                                           Protocol Port Support */
-#define UDCCR_AHNP      (1 << 29)       /* A-device Host Negotiation Protocol
-                                           Support */
-#define UDCCR_BHNP      (1 << 28)       /* B-device Host Negotiation Protocol
-                                           Enable */
-#define UDCCR_DWRE      (1 << 16)       /* Device Remote Wake-up Enable */
-#define UDCCR_ACN       (0x03 << 11)    /* Active UDC configuration Number */
-#define UDCCR_ACN_S     11
-#define UDCCR_AIN       (0x07 << 8)     /* Active UDC interface Number */
-#define UDCCR_AIN_S     8
-#define UDCCR_AAISN     (0x07 << 5)     /* Active UDC Alternate Interface
-                                           Setting Number */
-#define UDCCR_AAISN_S   5
-#define UDCCR_SMAC      (1 << 4)        /* Switch Endpoint Memory to Active
-                                           Configuration */
-#define UDCCR_EMCE      (1 << 3)        /* Endpoint Memory Configuration
-                                           Error */
-#define UDCCR_UDR       (1 << 2)        /* UDC Resume */
-#define UDCCR_UDA       (1 << 1)        /* UDC Active */
-#define UDCCR_UDE       (1 << 0)        /* UDC Enable */
-
-#define UDCICR0         __REG(0x40600004) /* UDC Interrupt Control Register0 */
-#define UDCICR1         __REG(0x40600008) /* UDC Interrupt Control Register1 */
-#define UDCICR_FIFOERR  (1 << 1)        /* FIFO Error interrupt for EP */
-#define UDCICR_PKTCOMPL (1 << 0)        /* Packet Complete interrupt for EP */
-
-#define UDC_INT_FIFOERROR  (0x2)
-#define UDC_INT_PACKETCMP  (0x1)
-
-#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
-#define UDCICR1_IECC    (1 << 31)       /* IntEn - Configuration Change */
-#define UDCICR1_IESOF   (1 << 30)       /* IntEn - Start of Frame */
-#define UDCICR1_IERU    (1 << 29)       /* IntEn - Resume */
-#define UDCICR1_IESU    (1 << 28)       /* IntEn - Suspend */
-#define UDCICR1_IERS    (1 << 27)       /* IntEn - Reset */
-
-#define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
-#define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
-#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
-#define UDCISR1_IRCC    (1 << 31)       /* IntReq - Configuration Change */
-#define UDCISR1_IRSOF   (1 << 30)       /* IntReq - Start of Frame */
-#define UDCISR1_IRRU    (1 << 29)       /* IntReq - Resume */
-#define UDCISR1_IRSU    (1 << 28)       /* IntReq - Suspend */
-#define UDCISR1_IRRS    (1 << 27)       /* IntReq - Reset */
-
-#define UDCFNR          __REG(0x40600014) /* UDC Frame Number Register */
-#define UDCOTGICR       __REG(0x40600018) /* UDC On-The-Go interrupt control */
-#define UDCOTGICR_IESF  (1 << 24)       /* OTG SET_FEATURE command recvd */
-#define UDCOTGICR_IEXR  (1 << 17)       /* Extra Transciever Interrupt
-                                           Rising Edge Interrupt Enable */
-#define UDCOTGICR_IEXF  (1 << 16)       /* Extra Transciever Interrupt
-                                           Falling Edge Interrupt Enable */
-#define UDCOTGICR_IEVV40R (1 << 9)      /* OTG Vbus Valid 4.0V Rising Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IEVV40F (1 << 8)      /* OTG Vbus Valid 4.0V Falling Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IEVV44R (1 << 7)      /* OTG Vbus Valid 4.4V Rising Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IEVV44F (1 << 6)      /* OTG Vbus Valid 4.4V Falling Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IESVR (1 << 5)        /* OTG Session Valid Rising Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IESVF (1 << 4)        /* OTG Session Valid Falling Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IESDR (1 << 3)        /* OTG A-Device SRP Detect Rising
-                                           Edge Interrupt Enable */
-#define UDCOTGICR_IESDF (1 << 2)        /* OTG A-Device SRP Detect Falling
-                                           Edge Interrupt Enable */
-#define UDCOTGICR_IEIDR (1 << 1)        /* OTG ID Change Rising Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IEIDF (1 << 0)        /* OTG ID Change Falling Edge
-                                           Interrupt Enable */
-
-#define UP2OCR            __REG(0x40600020)  /* USB Port 2 Output Control register */
-
-#define UP2OCR_CPVEN    (1 << 0)        /* Charge Pump Vbus Enable */
-#define UP2OCR_CPVPE    (1 << 1)        /* Charge Pump Vbus Pulse Enable */
-#define UP2OCR_DPPDE    (1 << 2)        /* Host Port 2 Transceiver D+ Pull Down Enable */
-#define UP2OCR_DMPDE    (1 << 3)        /* Host Port 2 Transceiver D- Pull Down Enable */
-#define UP2OCR_DPPUE    (1 << 4)        /* Host Port 2 Transceiver D+ Pull Up Enable */
-#define UP2OCR_DMPUE    (1 << 5)        /* Host Port 2 Transceiver D- Pull Up Enable */
-#define UP2OCR_DPPUBE   (1 << 6)        /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
-#define UP2OCR_DMPUBE   (1 << 7)        /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
-#define UP2OCR_EXSP             (1 << 8)        /* External Transceiver Speed Control */
-#define UP2OCR_EXSUS    (1 << 9)        /* External Transceiver Speed Enable */
-#define UP2OCR_IDON             (1 << 10)       /* OTG ID Read Enable */
-#define UP2OCR_HXS              (1 << 16)       /* Host Port 2 Transceiver Output Select */
-#define UP2OCR_HXOE             (1 << 17)       /* Host Port 2 Transceiver Output Enable */
-#define UP2OCR_SEOS             (1 << 24)       /* Single-Ended Output Select */
-
-#define UDCCSN(x)       __REG2(0x40600100, (x) << 2)
-#define UDCCSR0         __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
-#define UDCCSR0_SA      (1 << 7)        /* Setup Active */
-#define UDCCSR0_RNE     (1 << 6)        /* Receive FIFO Not Empty */
-#define UDCCSR0_FST     (1 << 5)        /* Force Stall */
-#define UDCCSR0_SST     (1 << 4)        /* Sent Stall */
-#define UDCCSR0_DME     (1 << 3)        /* DMA Enable */
-#define UDCCSR0_FTF     (1 << 2)        /* Flush Transmit FIFO */
-#define UDCCSR0_IPR     (1 << 1)        /* IN Packet Ready */
-#define UDCCSR0_OPC     (1 << 0)        /* OUT Packet Complete */
-
-#define UDCCSRA         __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
-#define UDCCSRB         __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
-#define UDCCSRC         __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
-#define UDCCSRD         __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
-#define UDCCSRE         __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
-#define UDCCSRF         __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
-#define UDCCSRG         __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
-#define UDCCSRH         __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
-#define UDCCSRI         __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
-#define UDCCSRJ         __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
-#define UDCCSRK         __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
-#define UDCCSRL         __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
-#define UDCCSRM         __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
-#define UDCCSRN         __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
-#define UDCCSRP         __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
-#define UDCCSRQ         __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
-#define UDCCSRR         __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
-#define UDCCSRS         __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
-#define UDCCSRT         __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
-#define UDCCSRU         __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
-#define UDCCSRV         __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
-#define UDCCSRW         __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
-#define UDCCSRX         __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
-
-#define UDCCSR_DPE      (1 << 9)        /* Data Packet Error */
-#define UDCCSR_FEF      (1 << 8)        /* Flush Endpoint FIFO */
-#define UDCCSR_SP       (1 << 7)        /* Short Packet Control/Status */
-#define UDCCSR_BNE      (1 << 6)        /* Buffer Not Empty (IN endpoints) */
-#define UDCCSR_BNF      (1 << 6)        /* Buffer Not Full (OUT endpoints) */
-#define UDCCSR_FST      (1 << 5)        /* Force STALL */
-#define UDCCSR_SST      (1 << 4)        /* Sent STALL */
-#define UDCCSR_DME      (1 << 3)        /* DMA Enable */
-#define UDCCSR_TRN      (1 << 2)        /* Tx/Rx NAK */
-#define UDCCSR_PC       (1 << 1)        /* Packet Complete */
-#define UDCCSR_FS       (1 << 0)        /* FIFO needs service */
-
-#define UDCBCN(x)       __REG2(0x40600200, (x)<<2)
-#define UDCBCR0         __REG(0x40600200) /* Byte Count Register - EP0 */
-#define UDCBCRA         __REG(0x40600204) /* Byte Count Register - EPA */
-#define UDCBCRB         __REG(0x40600208) /* Byte Count Register - EPB */
-#define UDCBCRC         __REG(0x4060020C) /* Byte Count Register - EPC */
-#define UDCBCRD         __REG(0x40600210) /* Byte Count Register - EPD */
-#define UDCBCRE         __REG(0x40600214) /* Byte Count Register - EPE */
-#define UDCBCRF         __REG(0x40600218) /* Byte Count Register - EPF */
-#define UDCBCRG         __REG(0x4060021C) /* Byte Count Register - EPG */
-#define UDCBCRH         __REG(0x40600220) /* Byte Count Register - EPH */
-#define UDCBCRI         __REG(0x40600224) /* Byte Count Register - EPI */
-#define UDCBCRJ         __REG(0x40600228) /* Byte Count Register - EPJ */
-#define UDCBCRK         __REG(0x4060022C) /* Byte Count Register - EPK */
-#define UDCBCRL         __REG(0x40600230) /* Byte Count Register - EPL */
-#define UDCBCRM         __REG(0x40600234) /* Byte Count Register - EPM */
-#define UDCBCRN         __REG(0x40600238) /* Byte Count Register - EPN */
-#define UDCBCRP         __REG(0x4060023C) /* Byte Count Register - EPP */
-#define UDCBCRQ         __REG(0x40600240) /* Byte Count Register - EPQ */
-#define UDCBCRR         __REG(0x40600244) /* Byte Count Register - EPR */
-#define UDCBCRS         __REG(0x40600248) /* Byte Count Register - EPS */
-#define UDCBCRT         __REG(0x4060024C) /* Byte Count Register - EPT */
-#define UDCBCRU         __REG(0x40600250) /* Byte Count Register - EPU */
-#define UDCBCRV         __REG(0x40600254) /* Byte Count Register - EPV */
-#define UDCBCRW         __REG(0x40600258) /* Byte Count Register - EPW */
-#define UDCBCRX         __REG(0x4060025C) /* Byte Count Register - EPX */
-
-#define UDCDN(x)        __REG2(0x40600300, (x)<<2)
-#define PHYS_UDCDN(x)   (0x40600300 + ((x)<<2))
-#define PUDCDN(x)       (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
-#define UDCDR0          __REG(0x40600300) /* Data Register - EP0 */
-#define UDCDRA          __REG(0x40600304) /* Data Register - EPA */
-#define UDCDRB          __REG(0x40600308) /* Data Register - EPB */
-#define UDCDRC          __REG(0x4060030C) /* Data Register - EPC */
-#define UDCDRD          __REG(0x40600310) /* Data Register - EPD */
-#define UDCDRE          __REG(0x40600314) /* Data Register - EPE */
-#define UDCDRF          __REG(0x40600318) /* Data Register - EPF */
-#define UDCDRG          __REG(0x4060031C) /* Data Register - EPG */
-#define UDCDRH          __REG(0x40600320) /* Data Register - EPH */
-#define UDCDRI          __REG(0x40600324) /* Data Register - EPI */
-#define UDCDRJ          __REG(0x40600328) /* Data Register - EPJ */
-#define UDCDRK          __REG(0x4060032C) /* Data Register - EPK */
-#define UDCDRL          __REG(0x40600330) /* Data Register - EPL */
-#define UDCDRM          __REG(0x40600334) /* Data Register - EPM */
-#define UDCDRN          __REG(0x40600338) /* Data Register - EPN */
-#define UDCDRP          __REG(0x4060033C) /* Data Register - EPP */
-#define UDCDRQ          __REG(0x40600340) /* Data Register - EPQ */
-#define UDCDRR          __REG(0x40600344) /* Data Register - EPR */
-#define UDCDRS          __REG(0x40600348) /* Data Register - EPS */
-#define UDCDRT          __REG(0x4060034C) /* Data Register - EPT */
-#define UDCDRU          __REG(0x40600350) /* Data Register - EPU */
-#define UDCDRV          __REG(0x40600354) /* Data Register - EPV */
-#define UDCDRW          __REG(0x40600358) /* Data Register - EPW */
-#define UDCDRX          __REG(0x4060035C) /* Data Register - EPX */
-
-#define UDCCN(x)       __REG2(0x40600400, (x)<<2)
-#define UDCCRA          __REG(0x40600404) /* Configuration register EPA */
-#define UDCCRB          __REG(0x40600408) /* Configuration register EPB */
-#define UDCCRC          __REG(0x4060040C) /* Configuration register EPC */
-#define UDCCRD          __REG(0x40600410) /* Configuration register EPD */
-#define UDCCRE          __REG(0x40600414) /* Configuration register EPE */
-#define UDCCRF          __REG(0x40600418) /* Configuration register EPF */
-#define UDCCRG          __REG(0x4060041C) /* Configuration register EPG */
-#define UDCCRH          __REG(0x40600420) /* Configuration register EPH */
-#define UDCCRI          __REG(0x40600424) /* Configuration register EPI */
-#define UDCCRJ          __REG(0x40600428) /* Configuration register EPJ */
-#define UDCCRK          __REG(0x4060042C) /* Configuration register EPK */
-#define UDCCRL          __REG(0x40600430) /* Configuration register EPL */
-#define UDCCRM          __REG(0x40600434) /* Configuration register EPM */
-#define UDCCRN          __REG(0x40600438) /* Configuration register EPN */
-#define UDCCRP          __REG(0x4060043C) /* Configuration register EPP */
-#define UDCCRQ          __REG(0x40600440) /* Configuration register EPQ */
-#define UDCCRR          __REG(0x40600444) /* Configuration register EPR */
-#define UDCCRS          __REG(0x40600448) /* Configuration register EPS */
-#define UDCCRT          __REG(0x4060044C) /* Configuration register EPT */
-#define UDCCRU          __REG(0x40600450) /* Configuration register EPU */
-#define UDCCRV          __REG(0x40600454) /* Configuration register EPV */
-#define UDCCRW          __REG(0x40600458) /* Configuration register EPW */
-#define UDCCRX          __REG(0x4060045C) /* Configuration register EPX */
-
-#define UDCCONR_CN      (0x03 << 25)    /* Configuration Number */
-#define UDCCONR_CN_S    (25)
-#define UDCCONR_IN      (0x07 << 22)    /* Interface Number */
-#define UDCCONR_IN_S    (22)
-#define UDCCONR_AISN    (0x07 << 19)    /* Alternate Interface Number */
-#define UDCCONR_AISN_S  (19)
-#define UDCCONR_EN      (0x0f << 15)    /* Endpoint Number */
-#define UDCCONR_EN_S    (15)
-#define UDCCONR_ET      (0x03 << 13)    /* Endpoint Type: */
-#define UDCCONR_ET_S    (13)
-#define UDCCONR_ET_INT  (0x03 << 13)    /*   Interrupt */
-#define UDCCONR_ET_BULK (0x02 << 13)    /*   Bulk */
-#define UDCCONR_ET_ISO  (0x01 << 13)    /*   Isochronous */
-#define UDCCONR_ET_NU   (0x00 << 13)    /*   Not used */
-#define UDCCONR_ED      (1 << 12)       /* Endpoint Direction */
-#define UDCCONR_MPS     (0x3ff << 2)    /* Maximum Packet Size */
-#define UDCCONR_MPS_S   (2)
-#define UDCCONR_DE      (1 << 1)        /* Double Buffering Enable */
-#define UDCCONR_EE      (1 << 0)        /* Endpoint Enable */
-
-
-#define UDC_INT_FIFOERROR  (0x2)
-#define UDC_INT_PACKETCMP  (0x1)
-
-#define UDC_FNR_MASK     (0x7ff)
-
-#define UDCCSR_WR_MASK   (UDCCSR_DME|UDCCSR_FST)
-#define UDC_BCR_MASK    (0x3ff)
-#endif
-
-/*
  * Fast Infrared Communication Port
  */
 
@@ -1237,120 +825,9 @@
 #endif
 
 /*
- * Power Manager
+ * Power Manager - see pxa2xx-regs.h
  */
 
-#define PMCR            __REG(0x40F00000)  /* Power Manager Control Register */
-#define PSSR            __REG(0x40F00004)  /* Power Manager Sleep Status Register */
-#define PSPR            __REG(0x40F00008)  /* Power Manager Scratch Pad Register */
-#define PWER            __REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */
-#define PRER            __REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
-#define PFER            __REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
-#define PEDR            __REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
-#define PCFR            __REG(0x40F0001C)  /* Power Manager General Configuration Register */
-#define PGSR0           __REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
-#define PGSR1           __REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
-#define PGSR2           __REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
-#define PGSR3           __REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
-#define RCSR            __REG(0x40F00030)  /* Reset Controller Status Register */
-
-#define PSLR            __REG(0x40F00034)       /* Power Manager Sleep Config Register */
-#define PSTR            __REG(0x40F00038)       /*Power Manager Standby Config Register */
-#define PSNR            __REG(0x40F0003C)       /*Power Manager Sense Config Register */
-#define PVCR            __REG(0x40F00040)       /*Power Manager VoltageControl Register */
-#define PKWR            __REG(0x40F00050)       /* Power Manager KB Wake-up Enable Reg */
-#define PKSR            __REG(0x40F00054)       /* Power Manager KB Level-Detect Register */
-#define PCMD(x) __REG2(0x40F00080, (x)<<2)
-#define PCMD0   __REG(0x40F00080 + 0 * 4)
-#define PCMD1   __REG(0x40F00080 + 1 * 4)
-#define PCMD2   __REG(0x40F00080 + 2 * 4)
-#define PCMD3   __REG(0x40F00080 + 3 * 4)
-#define PCMD4   __REG(0x40F00080 + 4 * 4)
-#define PCMD5   __REG(0x40F00080 + 5 * 4)
-#define PCMD6   __REG(0x40F00080 + 6 * 4)
-#define PCMD7   __REG(0x40F00080 + 7 * 4)
-#define PCMD8   __REG(0x40F00080 + 8 * 4)
-#define PCMD9   __REG(0x40F00080 + 9 * 4)
-#define PCMD10  __REG(0x40F00080 + 10 * 4)
-#define PCMD11  __REG(0x40F00080 + 11 * 4)
-#define PCMD12  __REG(0x40F00080 + 12 * 4)
-#define PCMD13  __REG(0x40F00080 + 13 * 4)
-#define PCMD14  __REG(0x40F00080 + 14 * 4)
-#define PCMD15  __REG(0x40F00080 + 15 * 4)
-#define PCMD16  __REG(0x40F00080 + 16 * 4)
-#define PCMD17  __REG(0x40F00080 + 17 * 4)
-#define PCMD18  __REG(0x40F00080 + 18 * 4)
-#define PCMD19  __REG(0x40F00080 + 19 * 4)
-#define PCMD20  __REG(0x40F00080 + 20 * 4)
-#define PCMD21  __REG(0x40F00080 + 21 * 4)
-#define PCMD22  __REG(0x40F00080 + 22 * 4)
-#define PCMD23  __REG(0x40F00080 + 23 * 4)
-#define PCMD24  __REG(0x40F00080 + 24 * 4)
-#define PCMD25  __REG(0x40F00080 + 25 * 4)
-#define PCMD26  __REG(0x40F00080 + 26 * 4)
-#define PCMD27  __REG(0x40F00080 + 27 * 4)
-#define PCMD28  __REG(0x40F00080 + 28 * 4)
-#define PCMD29  __REG(0x40F00080 + 29 * 4)
-#define PCMD30  __REG(0x40F00080 + 30 * 4)
-#define PCMD31  __REG(0x40F00080 + 31 * 4)
-
-#define PCMD_MBC        (1<<12)
-#define PCMD_DCE        (1<<11)
-#define PCMD_LC (1<<10)
-/* FIXME:  PCMD_SQC need be checked.   */
-#define PCMD_SQC        (3<<8)  /* currently only bit 8 is changeable,
-                                   bit 9 should be 0 all day. */
-#define PVCR_VCSA       (0x1<<14)
-#define PVCR_CommandDelay (0xf80)
-#define PCFR_PI2C_EN    (0x1 << 6)
-
-#define PSSR_OTGPH      (1 << 6)        /* OTG Peripheral control Hold */
-#define PSSR_RDH        (1 << 5)        /* Read Disable Hold */
-#define PSSR_PH         (1 << 4)        /* Peripheral Control Hold */
-#define PSSR_STS        (1 << 3)        /* Standby Mode Status */
-#define PSSR_VFS        (1 << 2)        /* VDD Fault Status */
-#define PSSR_BFS        (1 << 1)        /* Battery Fault Status */
-#define PSSR_SSS        (1 << 0)        /* Software Sleep Status */
-
-#define PSLR_SL_ROD     (1 << 20)       /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
-
-#define PCFR_RO         (1 << 15)       /* RDH Override */
-#define PCFR_PO         (1 << 14)       /* PH Override */
-#define PCFR_GPROD      (1 << 12)       /* GPIO nRESET_OUT Disable */
-#define PCFR_L1_EN      (1 << 11)       /* Sleep Mode L1 converter Enable */
-#define PCFR_FVC        (1 << 10)       /* Frequency/Voltage Change */
-#define PCFR_DC_EN      (1 << 7)        /* Sleep/deep-sleep DC-DC Converter Enable */
-#define PCFR_PI2CEN     (1 << 6)        /* Enable PI2C controller */
-#define PCFR_GPR_EN     (1 << 4)        /* nRESET_GPIO Pin Enable */
-#define PCFR_DS         (1 << 3)        /* Deep Sleep Mode */
-#define PCFR_FS         (1 << 2)        /* Float Static Chip Selects */
-#define PCFR_FP         (1 << 1)        /* Float PCMCIA controls */
-#define PCFR_OPDE       (1 << 0)        /* 3.6864 MHz oscillator power-down enable */
-
-#define RCSR_GPR        (1 << 3)        /* GPIO Reset */
-#define RCSR_SMR        (1 << 2)        /* Sleep Mode */
-#define RCSR_WDR        (1 << 1)        /* Watchdog Reset */
-#define RCSR_HWR        (1 << 0)        /* Hardware Reset */
-
-#define PWER_GPIO(Nb)   (1 << Nb)       /* GPIO [0..15] wake-up enable     */
-#define PWER_GPIO0      PWER_GPIO (0)   /* GPIO  [0] wake-up enable        */
-#define PWER_GPIO1      PWER_GPIO (1)   /* GPIO  [1] wake-up enable        */
-#define PWER_GPIO2      PWER_GPIO (2)   /* GPIO  [2] wake-up enable        */
-#define PWER_GPIO3      PWER_GPIO (3)   /* GPIO  [3] wake-up enable        */
-#define PWER_GPIO4      PWER_GPIO (4)   /* GPIO  [4] wake-up enable        */
-#define PWER_GPIO5      PWER_GPIO (5)   /* GPIO  [5] wake-up enable        */
-#define PWER_GPIO6      PWER_GPIO (6)   /* GPIO  [6] wake-up enable        */
-#define PWER_GPIO7      PWER_GPIO (7)   /* GPIO  [7] wake-up enable        */
-#define PWER_GPIO8      PWER_GPIO (8)   /* GPIO  [8] wake-up enable        */
-#define PWER_GPIO9      PWER_GPIO (9)   /* GPIO  [9] wake-up enable        */
-#define PWER_GPIO10     PWER_GPIO (10)  /* GPIO [10] wake-up enable        */
-#define PWER_GPIO11     PWER_GPIO (11)  /* GPIO [11] wake-up enable        */
-#define PWER_GPIO12     PWER_GPIO (12)  /* GPIO [12] wake-up enable        */
-#define PWER_GPIO13     PWER_GPIO (13)  /* GPIO [13] wake-up enable        */
-#define PWER_GPIO14     PWER_GPIO (14)  /* GPIO [14] wake-up enable        */
-#define PWER_GPIO15     PWER_GPIO (15)  /* GPIO [15] wake-up enable        */
-#define PWER_RTC        0x80000000      /* RTC alarm wake-up enable        */
-
 /*
  * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
  */
@@ -1360,52 +837,9 @@
  */
 
 /*
- * Core Clock
+ * Core Clock - see include/asm-arm/arch-pxa/pxa2xx-regs.h
  */
 
-#define CCCR            __REG(0x41300000)  /* Core Clock Configuration Register */
-#define CKEN            __REG(0x41300004)  /* Clock Enable Register */
-#define OSCC            __REG(0x41300008)  /* Oscillator Configuration Register */
-#define CCSR            __REG(0x4130000C)  /* Core Clock Status Register */
-
-#define CCCR_N_MASK     0x0380          /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#define CCCR_M_MASK     0x0060          /* Memory Frequency to Run Mode Frequency Multiplier */
-#define CCCR_L_MASK     0x001f          /* Crystal Frequency to Memory Frequency Multiplier */
-
-#define CKEN_AC97CONF   (31)    /* AC97 Controller Configuration */
-#define CKEN_CAMERA     (24)    /* Camera Interface Clock Enable */
-#define CKEN_SSP1       (23)    /* SSP1 Unit Clock Enable */
-#define CKEN_MEMC       (22)    /* Memory Controller Clock Enable */
-#define CKEN_MEMSTK     (21)    /* Memory Stick Host Controller */
-#define CKEN_IM         (20)    /* Internal Memory Clock Enable */
-#define CKEN_KEYPAD     (19)    /* Keypad Interface Clock Enable */
-#define CKEN_USIM       (18)    /* USIM Unit Clock Enable */
-#define CKEN_MSL        (17)    /* MSL Unit Clock Enable */
-#define CKEN_LCD        (16)    /* LCD Unit Clock Enable */
-#define CKEN_PWRI2C     (15)    /* PWR I2C Unit Clock Enable */
-#define CKEN_I2C        (14)    /* I2C Unit Clock Enable */
-#define CKEN_FICP       (13)    /* FICP Unit Clock Enable */
-#define CKEN_MMC        (12)    /* MMC Unit Clock Enable */
-#define CKEN_USB        (11)    /* USB Unit Clock Enable */
-#define CKEN_ASSP       (10)    /* ASSP (SSP3) Clock Enable */
-#define CKEN_USBHOST    (10)    /* USB Host Unit Clock Enable */
-#define CKEN_OSTIMER    (9)     /* OS Timer Unit Clock Enable */
-#define CKEN_NSSP       (9)     /* NSSP (SSP2) Clock Enable */
-#define CKEN_I2S        (8)     /* I2S Unit Clock Enable */
-#define CKEN_BTUART     (7)     /* BTUART Unit Clock Enable */
-#define CKEN_FFUART     (6)     /* FFUART Unit Clock Enable */
-#define CKEN_STUART     (5)     /* STUART Unit Clock Enable */
-#define CKEN_HWUART     (4)     /* HWUART Unit Clock Enable */
-#define CKEN_SSP3       (4)     /* SSP3 Unit Clock Enable */
-#define CKEN_SSP        (3)     /* SSP Unit Clock Enable */
-#define CKEN_SSP2       (3)     /* SSP2 Unit Clock Enable */
-#define CKEN_AC97       (2)     /* AC97 Unit Clock Enable */
-#define CKEN_PWM1       (1)     /* PWM1 Clock Enable */
-#define CKEN_PWM0       (0)     /* PWM0 Clock Enable */
-
-#define OSCC_OON        (1 << 1)        /* 32.768kHz OON (write-once only bit) */
-#define OSCC_OOK        (1 << 0)        /* 32.768kHz OOK (read-only bit) */
-
 #ifdef CONFIG_PXA27x
 
 /* Camera Interface */
diff --git a/include/asm-arm/arch-pxa/pxa25x-udc.h b/include/asm-arm/arch-pxa/pxa25x-udc.h
new file mode 100644
index 000000000000..840305916b6d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa25x-udc.h
@@ -0,0 +1,163 @@
+#ifndef _ASM_ARCH_PXA25X_UDC_H
+#define _ASM_ARCH_PXA25X_UDC_H
+
+#ifdef _ASM_ARCH_PXA27X_UDC_H
+#error You can't include both PXA25x and PXA27x UDC support
+#endif
+
+#define UDC_RES1        __REG(0x40600004)  /* UDC Undocumented - Reserved1 */
+#define UDC_RES2        __REG(0x40600008)  /* UDC Undocumented - Reserved2 */
+#define UDC_RES3        __REG(0x4060000C)  /* UDC Undocumented - Reserved3 */
+
+#define UDCCR           __REG(0x40600000)  /* UDC Control Register */
+#define UDCCR_UDE       (1 << 0)        /* UDC enable */
+#define UDCCR_UDA       (1 << 1)        /* UDC active */
+#define UDCCR_RSM       (1 << 2)        /* Device resume */
+#define UDCCR_RESIR     (1 << 3)        /* Resume interrupt request */
+#define UDCCR_SUSIR     (1 << 4)        /* Suspend interrupt request */
+#define UDCCR_SRM       (1 << 5)        /* Suspend/resume interrupt mask */
+#define UDCCR_RSTIR     (1 << 6)        /* Reset interrupt request */
+#define UDCCR_REM       (1 << 7)        /* Reset interrupt mask */
+
+#define UDCCS0          __REG(0x40600010)  /* UDC Endpoint 0 Control/Status Register */
+#define UDCCS0_OPR      (1 << 0)        /* OUT packet ready */
+#define UDCCS0_IPR      (1 << 1)        /* IN packet ready */
+#define UDCCS0_FTF      (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS0_DRWF     (1 << 3)        /* Device remote wakeup feature */
+#define UDCCS0_SST      (1 << 4)        /* Sent stall */
+#define UDCCS0_FST      (1 << 5)        /* Force stall */
+#define UDCCS0_RNE      (1 << 6)        /* Receive FIFO no empty */
+#define UDCCS0_SA       (1 << 7)        /* Setup active */
+
+/* Bulk IN - Endpoint 1,6,11 */
+#define UDCCS1          __REG(0x40600014)  /* UDC Endpoint 1 (IN) Control/Status Register */
+#define UDCCS6          __REG(0x40600028)  /* UDC Endpoint 6 (IN) Control/Status Register */
+#define UDCCS11         __REG(0x4060003C)  /* UDC Endpoint 11 (IN) Control/Status Register */
+
+#define UDCCS_BI_TFS    (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_BI_TPC    (1 << 1)        /* Transmit packet complete */
+#define UDCCS_BI_FTF    (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_BI_TUR    (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_BI_SST    (1 << 4)        /* Sent stall */
+#define UDCCS_BI_FST    (1 << 5)        /* Force stall */
+#define UDCCS_BI_TSP    (1 << 7)        /* Transmit short packet */
+
+/* Bulk OUT - Endpoint 2,7,12 */
+#define UDCCS2          __REG(0x40600018)  /* UDC Endpoint 2 (OUT) Control/Status Register */
+#define UDCCS7          __REG(0x4060002C)  /* UDC Endpoint 7 (OUT) Control/Status Register */
+#define UDCCS12         __REG(0x40600040)  /* UDC Endpoint 12 (OUT) Control/Status Register */
+
+#define UDCCS_BO_RFS    (1 << 0)        /* Receive FIFO service */
+#define UDCCS_BO_RPC    (1 << 1)        /* Receive packet complete */
+#define UDCCS_BO_DME    (1 << 3)        /* DMA enable */
+#define UDCCS_BO_SST    (1 << 4)        /* Sent stall */
+#define UDCCS_BO_FST    (1 << 5)        /* Force stall */
+#define UDCCS_BO_RNE    (1 << 6)        /* Receive FIFO not empty */
+#define UDCCS_BO_RSP    (1 << 7)        /* Receive short packet */
+
+/* Isochronous IN - Endpoint 3,8,13 */
+#define UDCCS3          __REG(0x4060001C)  /* UDC Endpoint 3 (IN) Control/Status Register */
+#define UDCCS8          __REG(0x40600030)  /* UDC Endpoint 8 (IN) Control/Status Register */
+#define UDCCS13         __REG(0x40600044)  /* UDC Endpoint 13 (IN) Control/Status Register */
+
+#define UDCCS_II_TFS    (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_II_TPC    (1 << 1)        /* Transmit packet complete */
+#define UDCCS_II_FTF    (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_II_TUR    (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_II_TSP    (1 << 7)        /* Transmit short packet */
+
+/* Isochronous OUT - Endpoint 4,9,14 */
+#define UDCCS4          __REG(0x40600020)  /* UDC Endpoint 4 (OUT) Control/Status Register */
+#define UDCCS9          __REG(0x40600034)  /* UDC Endpoint 9 (OUT) Control/Status Register */
+#define UDCCS14         __REG(0x40600048)  /* UDC Endpoint 14 (OUT) Control/Status Register */
+
+#define UDCCS_IO_RFS    (1 << 0)        /* Receive FIFO service */
+#define UDCCS_IO_RPC    (1 << 1)        /* Receive packet complete */
+#define UDCCS_IO_ROF    (1 << 2)        /* Receive overflow */
+#define UDCCS_IO_DME    (1 << 3)        /* DMA enable */
+#define UDCCS_IO_RNE    (1 << 6)        /* Receive FIFO not empty */
+#define UDCCS_IO_RSP    (1 << 7)        /* Receive short packet */
+
+/* Interrupt IN - Endpoint 5,10,15 */
+#define UDCCS5          __REG(0x40600024)  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
+#define UDCCS10         __REG(0x40600038)  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
+#define UDCCS15         __REG(0x4060004C)  /* UDC Endpoint 15 (Interrupt) Control/Status Register */
+
+#define UDCCS_INT_TFS   (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_INT_TPC   (1 << 1)        /* Transmit packet complete */
+#define UDCCS_INT_FTF   (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_INT_TUR   (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_INT_SST   (1 << 4)        /* Sent stall */
+#define UDCCS_INT_FST   (1 << 5)        /* Force stall */
+#define UDCCS_INT_TSP   (1 << 7)        /* Transmit short packet */
+
+#define UFNRH           __REG(0x40600060)  /* UDC Frame Number Register High */
+#define UFNRL           __REG(0x40600064)  /* UDC Frame Number Register Low */
+#define UBCR2           __REG(0x40600068)  /* UDC Byte Count Reg 2 */
+#define UBCR4           __REG(0x4060006c)  /* UDC Byte Count Reg 4 */
+#define UBCR7           __REG(0x40600070)  /* UDC Byte Count Reg 7 */
+#define UBCR9           __REG(0x40600074)  /* UDC Byte Count Reg 9 */
+#define UBCR12          __REG(0x40600078)  /* UDC Byte Count Reg 12 */
+#define UBCR14          __REG(0x4060007c)  /* UDC Byte Count Reg 14 */
+#define UDDR0           __REG(0x40600080)  /* UDC Endpoint 0 Data Register */
+#define UDDR1           __REG(0x40600100)  /* UDC Endpoint 1 Data Register */
+#define UDDR2           __REG(0x40600180)  /* UDC Endpoint 2 Data Register */
+#define UDDR3           __REG(0x40600200)  /* UDC Endpoint 3 Data Register */
+#define UDDR4           __REG(0x40600400)  /* UDC Endpoint 4 Data Register */
+#define UDDR5           __REG(0x406000A0)  /* UDC Endpoint 5 Data Register */
+#define UDDR6           __REG(0x40600600)  /* UDC Endpoint 6 Data Register */
+#define UDDR7           __REG(0x40600680)  /* UDC Endpoint 7 Data Register */
+#define UDDR8           __REG(0x40600700)  /* UDC Endpoint 8 Data Register */
+#define UDDR9           __REG(0x40600900)  /* UDC Endpoint 9 Data Register */
+#define UDDR10          __REG(0x406000C0)  /* UDC Endpoint 10 Data Register */
+#define UDDR11          __REG(0x40600B00)  /* UDC Endpoint 11 Data Register */
+#define UDDR12          __REG(0x40600B80)  /* UDC Endpoint 12 Data Register */
+#define UDDR13          __REG(0x40600C00)  /* UDC Endpoint 13 Data Register */
+#define UDDR14          __REG(0x40600E00)  /* UDC Endpoint 14 Data Register */
+#define UDDR15          __REG(0x406000E0)  /* UDC Endpoint 15 Data Register */
+
+#define UICR0           __REG(0x40600050)  /* UDC Interrupt Control Register 0 */
+
+#define UICR0_IM0       (1 << 0)        /* Interrupt mask ep 0 */
+#define UICR0_IM1       (1 << 1)        /* Interrupt mask ep 1 */
+#define UICR0_IM2       (1 << 2)        /* Interrupt mask ep 2 */
+#define UICR0_IM3       (1 << 3)        /* Interrupt mask ep 3 */
+#define UICR0_IM4       (1 << 4)        /* Interrupt mask ep 4 */
+#define UICR0_IM5       (1 << 5)        /* Interrupt mask ep 5 */
+#define UICR0_IM6       (1 << 6)        /* Interrupt mask ep 6 */
+#define UICR0_IM7       (1 << 7)        /* Interrupt mask ep 7 */
+
+#define UICR1           __REG(0x40600054)  /* UDC Interrupt Control Register 1 */
+
+#define UICR1_IM8       (1 << 0)        /* Interrupt mask ep 8 */
+#define UICR1_IM9       (1 << 1)        /* Interrupt mask ep 9 */
+#define UICR1_IM10      (1 << 2)        /* Interrupt mask ep 10 */
+#define UICR1_IM11      (1 << 3)        /* Interrupt mask ep 11 */
+#define UICR1_IM12      (1 << 4)        /* Interrupt mask ep 12 */
+#define UICR1_IM13      (1 << 5)        /* Interrupt mask ep 13 */
+#define UICR1_IM14      (1 << 6)        /* Interrupt mask ep 14 */
+#define UICR1_IM15      (1 << 7)        /* Interrupt mask ep 15 */
+
+#define USIR0           __REG(0x40600058)  /* UDC Status Interrupt Register 0 */
+
+#define USIR0_IR0       (1 << 0)        /* Interrupt request ep 0 */
+#define USIR0_IR1       (1 << 1)        /* Interrupt request ep 1 */
+#define USIR0_IR2       (1 << 2)        /* Interrupt request ep 2 */
+#define USIR0_IR3       (1 << 3)        /* Interrupt request ep 3 */
+#define USIR0_IR4       (1 << 4)        /* Interrupt request ep 4 */
+#define USIR0_IR5       (1 << 5)        /* Interrupt request ep 5 */
+#define USIR0_IR6       (1 << 6)        /* Interrupt request ep 6 */
+#define USIR0_IR7       (1 << 7)        /* Interrupt request ep 7 */
+
+#define USIR1           __REG(0x4060005C)  /* UDC Status Interrupt Register 1 */
+
+#define USIR1_IR8       (1 << 0)        /* Interrupt request ep 8 */
+#define USIR1_IR9       (1 << 1)        /* Interrupt request ep 9 */
+#define USIR1_IR10      (1 << 2)        /* Interrupt request ep 10 */
+#define USIR1_IR11      (1 << 3)        /* Interrupt request ep 11 */
+#define USIR1_IR12      (1 << 4)        /* Interrupt request ep 12 */
+#define USIR1_IR13      (1 << 5)        /* Interrupt request ep 13 */
+#define USIR1_IR14      (1 << 6)        /* Interrupt request ep 14 */
+#define USIR1_IR15      (1 << 7)        /* Interrupt request ep 15 */
+
+#endif
diff --git a/include/asm-arm/arch-pxa/pxa27x-udc.h b/include/asm-arm/arch-pxa/pxa27x-udc.h
new file mode 100644
index 000000000000..bc1cf7d0773a
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa27x-udc.h
@@ -0,0 +1,257 @@
+#ifndef _ASM_ARCH_PXA27X_UDC_H
+#define _ASM_ARCH_PXA27X_UDC_H
+
+#ifdef _ASM_ARCH_PXA25X_UDC_H
+#error You cannot include both PXA25x and PXA27x UDC support
+#endif
+
+#define UDCCR           __REG(0x40600000) /* UDC Control Register */
+#define UDCCR_OEN       (1 << 31)       /* On-the-Go Enable */
+#define UDCCR_AALTHNP   (1 << 30)       /* A-device Alternate Host Negotiation
+                                           Protocol Port Support */
+#define UDCCR_AHNP      (1 << 29)       /* A-device Host Negotiation Protocol
+                                           Support */
+#define UDCCR_BHNP      (1 << 28)       /* B-device Host Negotiation Protocol
+                                           Enable */
+#define UDCCR_DWRE      (1 << 16)       /* Device Remote Wake-up Enable */
+#define UDCCR_ACN       (0x03 << 11)    /* Active UDC configuration Number */
+#define UDCCR_ACN_S     11
+#define UDCCR_AIN       (0x07 << 8)     /* Active UDC interface Number */
+#define UDCCR_AIN_S     8
+#define UDCCR_AAISN     (0x07 << 5)     /* Active UDC Alternate Interface
+                                           Setting Number */
+#define UDCCR_AAISN_S   5
+#define UDCCR_SMAC      (1 << 4)        /* Switch Endpoint Memory to Active
+                                           Configuration */
+#define UDCCR_EMCE      (1 << 3)        /* Endpoint Memory Configuration
+                                           Error */
+#define UDCCR_UDR       (1 << 2)        /* UDC Resume */
+#define UDCCR_UDA       (1 << 1)        /* UDC Active */
+#define UDCCR_UDE       (1 << 0)        /* UDC Enable */
+
+#define UDCICR0         __REG(0x40600004) /* UDC Interrupt Control Register0 */
+#define UDCICR1         __REG(0x40600008) /* UDC Interrupt Control Register1 */
+#define UDCICR_FIFOERR  (1 << 1)        /* FIFO Error interrupt for EP */
+#define UDCICR_PKTCOMPL (1 << 0)        /* Packet Complete interrupt for EP */
+
+#define UDC_INT_FIFOERROR  (0x2)
+#define UDC_INT_PACKETCMP  (0x1)
+
+#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
+#define UDCICR1_IECC    (1 << 31)       /* IntEn - Configuration Change */
+#define UDCICR1_IESOF   (1 << 30)       /* IntEn - Start of Frame */
+#define UDCICR1_IERU    (1 << 29)       /* IntEn - Resume */
+#define UDCICR1_IESU    (1 << 28)       /* IntEn - Suspend */
+#define UDCICR1_IERS    (1 << 27)       /* IntEn - Reset */
+
+#define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
+#define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
+#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
+#define UDCISR1_IRCC    (1 << 31)       /* IntReq - Configuration Change */
+#define UDCISR1_IRSOF   (1 << 30)       /* IntReq - Start of Frame */
+#define UDCISR1_IRRU    (1 << 29)       /* IntReq - Resume */
+#define UDCISR1_IRSU    (1 << 28)       /* IntReq - Suspend */
+#define UDCISR1_IRRS    (1 << 27)       /* IntReq - Reset */
+
+#define UDCFNR          __REG(0x40600014) /* UDC Frame Number Register */
+#define UDCOTGICR       __REG(0x40600018) /* UDC On-The-Go interrupt control */
+#define UDCOTGICR_IESF  (1 << 24)       /* OTG SET_FEATURE command recvd */
+#define UDCOTGICR_IEXR  (1 << 17)       /* Extra Transciever Interrupt
+                                           Rising Edge Interrupt Enable */
+#define UDCOTGICR_IEXF  (1 << 16)       /* Extra Transciever Interrupt
+                                           Falling Edge Interrupt Enable */
+#define UDCOTGICR_IEVV40R (1 << 9)      /* OTG Vbus Valid 4.0V Rising Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IEVV40F (1 << 8)      /* OTG Vbus Valid 4.0V Falling Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IEVV44R (1 << 7)      /* OTG Vbus Valid 4.4V Rising Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IEVV44F (1 << 6)      /* OTG Vbus Valid 4.4V Falling Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IESVR (1 << 5)        /* OTG Session Valid Rising Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IESVF (1 << 4)        /* OTG Session Valid Falling Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IESDR (1 << 3)        /* OTG A-Device SRP Detect Rising
+                                           Edge Interrupt Enable */
+#define UDCOTGICR_IESDF (1 << 2)        /* OTG A-Device SRP Detect Falling
+                                           Edge Interrupt Enable */
+#define UDCOTGICR_IEIDR (1 << 1)        /* OTG ID Change Rising Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IEIDF (1 << 0)        /* OTG ID Change Falling Edge
+                                           Interrupt Enable */
+
+#define UP2OCR            __REG(0x40600020)  /* USB Port 2 Output Control register */
+#define UP3OCR            __REG(0x40600024)  /* USB Port 2 Output Control register */
+
+#define UP2OCR_CPVEN    (1 << 0)        /* Charge Pump Vbus Enable */
+#define UP2OCR_CPVPE    (1 << 1)        /* Charge Pump Vbus Pulse Enable */
+#define UP2OCR_DPPDE    (1 << 2)        /* Host Port 2 Transceiver D+ Pull Down Enable */
+#define UP2OCR_DMPDE    (1 << 3)        /* Host Port 2 Transceiver D- Pull Down Enable */
+#define UP2OCR_DPPUE    (1 << 4)        /* Host Port 2 Transceiver D+ Pull Up Enable */
+#define UP2OCR_DMPUE    (1 << 5)        /* Host Port 2 Transceiver D- Pull Up Enable */
+#define UP2OCR_DPPUBE   (1 << 6)        /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
+#define UP2OCR_DMPUBE   (1 << 7)        /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
+#define UP2OCR_EXSP             (1 << 8)        /* External Transceiver Speed Control */
+#define UP2OCR_EXSUS    (1 << 9)        /* External Transceiver Speed Enable */
+#define UP2OCR_IDON             (1 << 10)       /* OTG ID Read Enable */
+#define UP2OCR_HXS              (1 << 16)       /* Host Port 2 Transceiver Output Select */
+#define UP2OCR_HXOE             (1 << 17)       /* Host Port 2 Transceiver Output Enable */
+#define UP2OCR_SEOS             (1 << 24)       /* Single-Ended Output Select */
+
+#define UDCCSN(x)       __REG2(0x40600100, (x) << 2)
+#define UDCCSR0         __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
+#define UDCCSR0_SA      (1 << 7)        /* Setup Active */
+#define UDCCSR0_RNE     (1 << 6)        /* Receive FIFO Not Empty */
+#define UDCCSR0_FST     (1 << 5)        /* Force Stall */
+#define UDCCSR0_SST     (1 << 4)        /* Sent Stall */
+#define UDCCSR0_DME     (1 << 3)        /* DMA Enable */
+#define UDCCSR0_FTF     (1 << 2)        /* Flush Transmit FIFO */
+#define UDCCSR0_IPR     (1 << 1)        /* IN Packet Ready */
+#define UDCCSR0_OPC     (1 << 0)        /* OUT Packet Complete */
+
+#define UDCCSRA         __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
+#define UDCCSRB         __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
+#define UDCCSRC         __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
+#define UDCCSRD         __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
+#define UDCCSRE         __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
+#define UDCCSRF         __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
+#define UDCCSRG         __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
+#define UDCCSRH         __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
+#define UDCCSRI         __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
+#define UDCCSRJ         __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
+#define UDCCSRK         __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
+#define UDCCSRL         __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
+#define UDCCSRM         __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
+#define UDCCSRN         __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
+#define UDCCSRP         __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
+#define UDCCSRQ         __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
+#define UDCCSRR         __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
+#define UDCCSRS         __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
+#define UDCCSRT         __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
+#define UDCCSRU         __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
+#define UDCCSRV         __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
+#define UDCCSRW         __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
+#define UDCCSRX         __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
+
+#define UDCCSR_DPE      (1 << 9)        /* Data Packet Error */
+#define UDCCSR_FEF      (1 << 8)        /* Flush Endpoint FIFO */
+#define UDCCSR_SP       (1 << 7)        /* Short Packet Control/Status */
+#define UDCCSR_BNE      (1 << 6)        /* Buffer Not Empty (IN endpoints) */
+#define UDCCSR_BNF      (1 << 6)        /* Buffer Not Full (OUT endpoints) */
+#define UDCCSR_FST      (1 << 5)        /* Force STALL */
+#define UDCCSR_SST      (1 << 4)        /* Sent STALL */
+#define UDCCSR_DME      (1 << 3)        /* DMA Enable */
+#define UDCCSR_TRN      (1 << 2)        /* Tx/Rx NAK */
+#define UDCCSR_PC       (1 << 1)        /* Packet Complete */
+#define UDCCSR_FS       (1 << 0)        /* FIFO needs service */
+
+#define UDCBCN(x)       __REG2(0x40600200, (x)<<2)
+#define UDCBCR0         __REG(0x40600200) /* Byte Count Register - EP0 */
+#define UDCBCRA         __REG(0x40600204) /* Byte Count Register - EPA */
+#define UDCBCRB         __REG(0x40600208) /* Byte Count Register - EPB */
+#define UDCBCRC         __REG(0x4060020C) /* Byte Count Register - EPC */
+#define UDCBCRD         __REG(0x40600210) /* Byte Count Register - EPD */
+#define UDCBCRE         __REG(0x40600214) /* Byte Count Register - EPE */
+#define UDCBCRF         __REG(0x40600218) /* Byte Count Register - EPF */
+#define UDCBCRG         __REG(0x4060021C) /* Byte Count Register - EPG */
+#define UDCBCRH         __REG(0x40600220) /* Byte Count Register - EPH */
+#define UDCBCRI         __REG(0x40600224) /* Byte Count Register - EPI */
+#define UDCBCRJ         __REG(0x40600228) /* Byte Count Register - EPJ */
+#define UDCBCRK         __REG(0x4060022C) /* Byte Count Register - EPK */
+#define UDCBCRL         __REG(0x40600230) /* Byte Count Register - EPL */
+#define UDCBCRM         __REG(0x40600234) /* Byte Count Register - EPM */
+#define UDCBCRN         __REG(0x40600238) /* Byte Count Register - EPN */
+#define UDCBCRP         __REG(0x4060023C) /* Byte Count Register - EPP */
+#define UDCBCRQ         __REG(0x40600240) /* Byte Count Register - EPQ */
+#define UDCBCRR         __REG(0x40600244) /* Byte Count Register - EPR */
+#define UDCBCRS         __REG(0x40600248) /* Byte Count Register - EPS */
+#define UDCBCRT         __REG(0x4060024C) /* Byte Count Register - EPT */
+#define UDCBCRU         __REG(0x40600250) /* Byte Count Register - EPU */
+#define UDCBCRV         __REG(0x40600254) /* Byte Count Register - EPV */
+#define UDCBCRW         __REG(0x40600258) /* Byte Count Register - EPW */
+#define UDCBCRX         __REG(0x4060025C) /* Byte Count Register - EPX */
+
+#define UDCDN(x)        __REG2(0x40600300, (x)<<2)
+#define PHYS_UDCDN(x)   (0x40600300 + ((x)<<2))
+#define PUDCDN(x)       (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
+#define UDCDR0          __REG(0x40600300) /* Data Register - EP0 */
+#define UDCDRA          __REG(0x40600304) /* Data Register - EPA */
+#define UDCDRB          __REG(0x40600308) /* Data Register - EPB */
+#define UDCDRC          __REG(0x4060030C) /* Data Register - EPC */
+#define UDCDRD          __REG(0x40600310) /* Data Register - EPD */
+#define UDCDRE          __REG(0x40600314) /* Data Register - EPE */
+#define UDCDRF          __REG(0x40600318) /* Data Register - EPF */
+#define UDCDRG          __REG(0x4060031C) /* Data Register - EPG */
+#define UDCDRH          __REG(0x40600320) /* Data Register - EPH */
+#define UDCDRI          __REG(0x40600324) /* Data Register - EPI */
+#define UDCDRJ          __REG(0x40600328) /* Data Register - EPJ */
+#define UDCDRK          __REG(0x4060032C) /* Data Register - EPK */
+#define UDCDRL          __REG(0x40600330) /* Data Register - EPL */
+#define UDCDRM          __REG(0x40600334) /* Data Register - EPM */
+#define UDCDRN          __REG(0x40600338) /* Data Register - EPN */
+#define UDCDRP          __REG(0x4060033C) /* Data Register - EPP */
+#define UDCDRQ          __REG(0x40600340) /* Data Register - EPQ */
+#define UDCDRR          __REG(0x40600344) /* Data Register - EPR */
+#define UDCDRS          __REG(0x40600348) /* Data Register - EPS */
+#define UDCDRT          __REG(0x4060034C) /* Data Register - EPT */
+#define UDCDRU          __REG(0x40600350) /* Data Register - EPU */
+#define UDCDRV          __REG(0x40600354) /* Data Register - EPV */
+#define UDCDRW          __REG(0x40600358) /* Data Register - EPW */
+#define UDCDRX          __REG(0x4060035C) /* Data Register - EPX */
+
+#define UDCCN(x)       __REG2(0x40600400, (x)<<2)
+#define UDCCRA          __REG(0x40600404) /* Configuration register EPA */
+#define UDCCRB          __REG(0x40600408) /* Configuration register EPB */
+#define UDCCRC          __REG(0x4060040C) /* Configuration register EPC */
+#define UDCCRD          __REG(0x40600410) /* Configuration register EPD */
+#define UDCCRE          __REG(0x40600414) /* Configuration register EPE */
+#define UDCCRF          __REG(0x40600418) /* Configuration register EPF */
+#define UDCCRG          __REG(0x4060041C) /* Configuration register EPG */
+#define UDCCRH          __REG(0x40600420) /* Configuration register EPH */
+#define UDCCRI          __REG(0x40600424) /* Configuration register EPI */
+#define UDCCRJ          __REG(0x40600428) /* Configuration register EPJ */
+#define UDCCRK          __REG(0x4060042C) /* Configuration register EPK */
+#define UDCCRL          __REG(0x40600430) /* Configuration register EPL */
+#define UDCCRM          __REG(0x40600434) /* Configuration register EPM */
+#define UDCCRN          __REG(0x40600438) /* Configuration register EPN */
+#define UDCCRP          __REG(0x4060043C) /* Configuration register EPP */
+#define UDCCRQ          __REG(0x40600440) /* Configuration register EPQ */
+#define UDCCRR          __REG(0x40600444) /* Configuration register EPR */
+#define UDCCRS          __REG(0x40600448) /* Configuration register EPS */
+#define UDCCRT          __REG(0x4060044C) /* Configuration register EPT */
+#define UDCCRU          __REG(0x40600450) /* Configuration register EPU */
+#define UDCCRV          __REG(0x40600454) /* Configuration register EPV */
+#define UDCCRW          __REG(0x40600458) /* Configuration register EPW */
+#define UDCCRX          __REG(0x4060045C) /* Configuration register EPX */
+
+#define UDCCONR_CN      (0x03 << 25)    /* Configuration Number */
+#define UDCCONR_CN_S    (25)
+#define UDCCONR_IN      (0x07 << 22)    /* Interface Number */
+#define UDCCONR_IN_S    (22)
+#define UDCCONR_AISN    (0x07 << 19)    /* Alternate Interface Number */
+#define UDCCONR_AISN_S  (19)
+#define UDCCONR_EN      (0x0f << 15)    /* Endpoint Number */
+#define UDCCONR_EN_S    (15)
+#define UDCCONR_ET      (0x03 << 13)    /* Endpoint Type: */
+#define UDCCONR_ET_S    (13)
+#define UDCCONR_ET_INT  (0x03 << 13)    /*   Interrupt */
+#define UDCCONR_ET_BULK (0x02 << 13)    /*   Bulk */
+#define UDCCONR_ET_ISO  (0x01 << 13)    /*   Isochronous */
+#define UDCCONR_ET_NU   (0x00 << 13)    /*   Not used */
+#define UDCCONR_ED      (1 << 12)       /* Endpoint Direction */
+#define UDCCONR_MPS     (0x3ff << 2)    /* Maximum Packet Size */
+#define UDCCONR_MPS_S   (2)
+#define UDCCONR_DE      (1 << 1)        /* Double Buffering Enable */
+#define UDCCONR_EE      (1 << 0)        /* Endpoint Enable */
+
+
+#define UDC_INT_FIFOERROR  (0x2)
+#define UDC_INT_PACKETCMP  (0x1)
+
+#define UDC_FNR_MASK     (0x7ff)
+
+#define UDCCSR_WR_MASK   (UDCCSR_DME|UDCCSR_FST)
+#define UDC_BCR_MASK    (0x3ff)
+
+#endif
diff --git a/include/asm-arm/arch-pxa/pxa2xx-gpio.h b/include/asm-arm/arch-pxa/pxa2xx-gpio.h
index b81cd63cb2eb..6ef1dd09970b 100644
--- a/include/asm-arm/arch-pxa/pxa2xx-gpio.h
+++ b/include/asm-arm/arch-pxa/pxa2xx-gpio.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_ARCH_PXA2XX_GPIO_H
 #define __ASM_ARCH_PXA2XX_GPIO_H
 
+#warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h
+
 /* GPIO alternate function assignments */
 
 #define GPIO1_RST               1       /* reset */
diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h
index 9553b54fa5bc..73e0a329cf7f 100644
--- a/include/asm-arm/arch-pxa/pxa2xx-regs.h
+++ b/include/asm-arm/arch-pxa/pxa2xx-regs.h
@@ -81,4 +81,166 @@
 
 #endif
 
+
+/*
+ * Power Manager
+ */
+
+#define PMCR            __REG(0x40F00000)  /* Power Manager Control Register */
+#define PSSR            __REG(0x40F00004)  /* Power Manager Sleep Status Register */
+#define PSPR            __REG(0x40F00008)  /* Power Manager Scratch Pad Register */
+#define PWER            __REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */
+#define PRER            __REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
+#define PFER            __REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
+#define PEDR            __REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
+#define PCFR            __REG(0x40F0001C)  /* Power Manager General Configuration Register */
+#define PGSR0           __REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
+#define PGSR1           __REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
+#define PGSR2           __REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
+#define PGSR3           __REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
+#define RCSR            __REG(0x40F00030)  /* Reset Controller Status Register */
+
+#define PSLR            __REG(0x40F00034)       /* Power Manager Sleep Config Register */
+#define PSTR            __REG(0x40F00038)       /* Power Manager Standby Config Register */
+#define PSNR            __REG(0x40F0003C)       /* Power Manager Sense Config Register */
+#define PVCR            __REG(0x40F00040)       /* Power Manager VoltageControl Register */
+#define PKWR            __REG(0x40F00050)       /* Power Manager KB Wake-up Enable Reg */
+#define PKSR            __REG(0x40F00054)       /* Power Manager KB Level-Detect Register */
+#define PCMD(x) __REG2(0x40F00080, (x)<<2)
+#define PCMD0   __REG(0x40F00080 + 0 * 4)
+#define PCMD1   __REG(0x40F00080 + 1 * 4)
+#define PCMD2   __REG(0x40F00080 + 2 * 4)
+#define PCMD3   __REG(0x40F00080 + 3 * 4)
+#define PCMD4   __REG(0x40F00080 + 4 * 4)
+#define PCMD5   __REG(0x40F00080 + 5 * 4)
+#define PCMD6   __REG(0x40F00080 + 6 * 4)
+#define PCMD7   __REG(0x40F00080 + 7 * 4)
+#define PCMD8   __REG(0x40F00080 + 8 * 4)
+#define PCMD9   __REG(0x40F00080 + 9 * 4)
+#define PCMD10  __REG(0x40F00080 + 10 * 4)
+#define PCMD11  __REG(0x40F00080 + 11 * 4)
+#define PCMD12  __REG(0x40F00080 + 12 * 4)
+#define PCMD13  __REG(0x40F00080 + 13 * 4)
+#define PCMD14  __REG(0x40F00080 + 14 * 4)
+#define PCMD15  __REG(0x40F00080 + 15 * 4)
+#define PCMD16  __REG(0x40F00080 + 16 * 4)
+#define PCMD17  __REG(0x40F00080 + 17 * 4)
+#define PCMD18  __REG(0x40F00080 + 18 * 4)
+#define PCMD19  __REG(0x40F00080 + 19 * 4)
+#define PCMD20  __REG(0x40F00080 + 20 * 4)
+#define PCMD21  __REG(0x40F00080 + 21 * 4)
+#define PCMD22  __REG(0x40F00080 + 22 * 4)
+#define PCMD23  __REG(0x40F00080 + 23 * 4)
+#define PCMD24  __REG(0x40F00080 + 24 * 4)
+#define PCMD25  __REG(0x40F00080 + 25 * 4)
+#define PCMD26  __REG(0x40F00080 + 26 * 4)
+#define PCMD27  __REG(0x40F00080 + 27 * 4)
+#define PCMD28  __REG(0x40F00080 + 28 * 4)
+#define PCMD29  __REG(0x40F00080 + 29 * 4)
+#define PCMD30  __REG(0x40F00080 + 30 * 4)
+#define PCMD31  __REG(0x40F00080 + 31 * 4)
+
+#define PCMD_MBC        (1<<12)
+#define PCMD_DCE        (1<<11)
+#define PCMD_LC (1<<10)
+/* FIXME:  PCMD_SQC need be checked.   */
+#define PCMD_SQC        (3<<8)  /* currently only bit 8 is changeable,
+                                   bit 9 should be 0 all day. */
+#define PVCR_VCSA       (0x1<<14)
+#define PVCR_CommandDelay (0xf80)
+#define PCFR_PI2C_EN    (0x1 << 6)
+
+#define PSSR_OTGPH      (1 << 6)        /* OTG Peripheral control Hold */
+#define PSSR_RDH        (1 << 5)        /* Read Disable Hold */
+#define PSSR_PH         (1 << 4)        /* Peripheral Control Hold */
+#define PSSR_STS        (1 << 3)        /* Standby Mode Status */
+#define PSSR_VFS        (1 << 2)        /* VDD Fault Status */
+#define PSSR_BFS        (1 << 1)        /* Battery Fault Status */
+#define PSSR_SSS        (1 << 0)        /* Software Sleep Status */
+
+#define PSLR_SL_ROD     (1 << 20)       /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
+
+#define PCFR_RO         (1 << 15)       /* RDH Override */
+#define PCFR_PO         (1 << 14)       /* PH Override */
+#define PCFR_GPROD      (1 << 12)       /* GPIO nRESET_OUT Disable */
+#define PCFR_L1_EN      (1 << 11)       /* Sleep Mode L1 converter Enable */
+#define PCFR_FVC        (1 << 10)       /* Frequency/Voltage Change */
+#define PCFR_DC_EN      (1 << 7)        /* Sleep/deep-sleep DC-DC Converter Enable */
+#define PCFR_PI2CEN     (1 << 6)        /* Enable PI2C controller */
+#define PCFR_GPR_EN     (1 << 4)        /* nRESET_GPIO Pin Enable */
+#define PCFR_DS         (1 << 3)        /* Deep Sleep Mode */
+#define PCFR_FS         (1 << 2)        /* Float Static Chip Selects */
+#define PCFR_FP         (1 << 1)        /* Float PCMCIA controls */
+#define PCFR_OPDE       (1 << 0)        /* 3.6864 MHz oscillator power-down enable */
+
+#define RCSR_GPR        (1 << 3)        /* GPIO Reset */
+#define RCSR_SMR        (1 << 2)        /* Sleep Mode */
+#define RCSR_WDR        (1 << 1)        /* Watchdog Reset */
+#define RCSR_HWR        (1 << 0)        /* Hardware Reset */
+
+#define PWER_GPIO(Nb)   (1 << Nb)       /* GPIO [0..15] wake-up enable     */
+#define PWER_GPIO0      PWER_GPIO (0)   /* GPIO  [0] wake-up enable        */
+#define PWER_GPIO1      PWER_GPIO (1)   /* GPIO  [1] wake-up enable        */
+#define PWER_GPIO2      PWER_GPIO (2)   /* GPIO  [2] wake-up enable        */
+#define PWER_GPIO3      PWER_GPIO (3)   /* GPIO  [3] wake-up enable        */
+#define PWER_GPIO4      PWER_GPIO (4)   /* GPIO  [4] wake-up enable        */
+#define PWER_GPIO5      PWER_GPIO (5)   /* GPIO  [5] wake-up enable        */
+#define PWER_GPIO6      PWER_GPIO (6)   /* GPIO  [6] wake-up enable        */
+#define PWER_GPIO7      PWER_GPIO (7)   /* GPIO  [7] wake-up enable        */
+#define PWER_GPIO8      PWER_GPIO (8)   /* GPIO  [8] wake-up enable        */
+#define PWER_GPIO9      PWER_GPIO (9)   /* GPIO  [9] wake-up enable        */
+#define PWER_GPIO10     PWER_GPIO (10)  /* GPIO [10] wake-up enable        */
+#define PWER_GPIO11     PWER_GPIO (11)  /* GPIO [11] wake-up enable        */
+#define PWER_GPIO12     PWER_GPIO (12)  /* GPIO [12] wake-up enable        */
+#define PWER_GPIO13     PWER_GPIO (13)  /* GPIO [13] wake-up enable        */
+#define PWER_GPIO14     PWER_GPIO (14)  /* GPIO [14] wake-up enable        */
+#define PWER_GPIO15     PWER_GPIO (15)  /* GPIO [15] wake-up enable        */
+#define PWER_RTC        0x80000000      /* RTC alarm wake-up enable        */
+
+/*
+ * PXA2xx specific Core clock definitions
+ */
+#define CCCR            __REG(0x41300000)  /* Core Clock Configuration Register */
+#define CCSR            __REG(0x4130000C)  /* Core Clock Status Register */
+#define CKEN            __REG(0x41300004)  /* Clock Enable Register */
+#define OSCC            __REG(0x41300008)  /* Oscillator Configuration Register */
+
+#define CCCR_N_MASK     0x0380  /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#define CCCR_M_MASK     0x0060  /* Memory Frequency to Run Mode Frequency Multiplier */
+#define CCCR_L_MASK     0x001f  /* Crystal Frequency to Memory Frequency Multiplier */
+
+#define CKEN_AC97CONF   (31)    /* AC97 Controller Configuration */
+#define CKEN_CAMERA     (24)    /* Camera Interface Clock Enable */
+#define CKEN_SSP1       (23)    /* SSP1 Unit Clock Enable */
+#define CKEN_MEMC       (22)    /* Memory Controller Clock Enable */
+#define CKEN_MEMSTK     (21)    /* Memory Stick Host Controller */
+#define CKEN_IM         (20)    /* Internal Memory Clock Enable */
+#define CKEN_KEYPAD     (19)    /* Keypad Interface Clock Enable */
+#define CKEN_USIM       (18)    /* USIM Unit Clock Enable */
+#define CKEN_MSL        (17)    /* MSL Unit Clock Enable */
+#define CKEN_LCD        (16)    /* LCD Unit Clock Enable */
+#define CKEN_PWRI2C     (15)    /* PWR I2C Unit Clock Enable */
+#define CKEN_I2C        (14)    /* I2C Unit Clock Enable */
+#define CKEN_FICP       (13)    /* FICP Unit Clock Enable */
+#define CKEN_MMC        (12)    /* MMC Unit Clock Enable */
+#define CKEN_USB        (11)    /* USB Unit Clock Enable */
+#define CKEN_ASSP       (10)    /* ASSP (SSP3) Clock Enable */
+#define CKEN_USBHOST    (10)    /* USB Host Unit Clock Enable */
+#define CKEN_OSTIMER    (9)     /* OS Timer Unit Clock Enable */
+#define CKEN_NSSP       (9)     /* NSSP (SSP2) Clock Enable */
+#define CKEN_I2S        (8)     /* I2S Unit Clock Enable */
+#define CKEN_BTUART     (7)     /* BTUART Unit Clock Enable */
+#define CKEN_FFUART     (6)     /* FFUART Unit Clock Enable */
+#define CKEN_STUART     (5)     /* STUART Unit Clock Enable */
+#define CKEN_HWUART     (4)     /* HWUART Unit Clock Enable */
+#define CKEN_SSP3       (4)     /* SSP3 Unit Clock Enable */
+#define CKEN_SSP        (3)     /* SSP Unit Clock Enable */
+#define CKEN_SSP2       (3)     /* SSP2 Unit Clock Enable */
+#define CKEN_AC97       (2)     /* AC97 Unit Clock Enable */
+#define CKEN_PWM1       (1)     /* PWM1 Clock Enable */
+#define CKEN_PWM0       (0)     /* PWM0 Clock Enable */
+
+#define OSCC_OON        (1 << 1)        /* 32.768kHz OON (write-once only bit) */
+#define OSCC_OOK        (1 << 0)        /* 32.768kHz OOK (read-only bit) */
+
 #endif
diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h
index 9aa6c2e939e8..ba7e132de1b3 100644
--- a/include/asm-arm/arch-pxa/system.h
+++ b/include/asm-arm/arch-pxa/system.h
@@ -12,6 +12,7 @@
 
 #include <asm/proc-fns.h>
 #include "hardware.h"
+#include "pxa2xx-regs.h"
 #include "pxa-regs.h"
 
 static inline void arch_idle(void)
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
index 4881b80f0f90..de577de8d18c 100644
--- a/include/asm-arm/arch-pxa/zylonite.h
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -15,7 +15,6 @@ struct platform_mmc_slot {
 
 extern struct platform_mmc_slot zylonite_mmc_slot[];
 
-extern int gpio_backlight;
 extern int gpio_eth_irq;
 
 extern int wm9713_irq;
diff --git a/include/asm-arm/arch-rpc/io.h b/include/asm-arm/arch-rpc/io.h
index b4da08d7a336..6bd2295c0e01 100644
--- a/include/asm-arm/arch-rpc/io.h
+++ b/include/asm-arm/arch-rpc/io.h
@@ -126,7 +126,7 @@ static inline unsigned sz __in##fnsuffix (unsigned int port)		\
         return (unsigned sz)value;                                              \
 }
 
-static inline void __iomem *__ioaddr(unsigned int port)
+static inline void __iomem *__deprecated __ioaddr(unsigned int port)
 {
         void __iomem *ret;
         if (__PORT_PCIO(port))
@@ -232,8 +232,7 @@ DECLARE_IO(int,l,"")
         result;                                                                 \
 })
 
-#define __ioaddrc(port)         \
-        ((__PORT_PCIO(port) ? PCIO_BASE : IO_BASE) + ((port) << 2))
+#define __ioaddrc(port)         __ioaddr(port)
 
 #define inb(p)          (__builtin_constant_p((p)) ? __inbc(p)    : __inb(p))
 #define inw(p)          (__builtin_constant_p((p)) ? __inwc(p)    : __inw(p))
diff --git a/include/asm-arm/arch-s3c2410/gpio.h b/include/asm-arm/arch-s3c2410/gpio.h
index 7583895fd336..18e10d2c35ea 100644
--- a/include/asm-arm/arch-s3c2410/gpio.h
+++ b/include/asm-arm/arch-s3c2410/gpio.h
@@ -1,68 +1,18 @@
-/*
- * linux/include/asm-arm/arch-s3c2410/gpio.h
+/* linux/include/asm-arm/arch-s3c2410/gpio.h
  *
- * S3C2410 GPIO wrappers for arch-neutral GPIO calls
+ * Copyright (c) 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
  *
- * Written by Philipp Zabel <philipp.zabel@gmail.com>
+ * S3C2410 - GPIO lib support
  *
  * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARCH_S3C2410_GPIO_H
-#define __ASM_ARCH_S3C2410_GPIO_H
-
-#include <asm/irq.h>
-#include <asm/hardware.h>
-#include <asm/arch/regs-gpio.h>
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-        return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
-        return;
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
-        s3c2410_gpio_cfgpin(gpio, S3C2410_GPIO_INPUT);
-        return 0;
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
-        s3c2410_gpio_cfgpin(gpio, S3C2410_GPIO_OUTPUT);
-        /* REVISIT can we write the value first, to avoid glitching? */
-        s3c2410_gpio_setpin(gpio, value);
-        return 0;
-}
-
-#define gpio_get_value(gpio)            s3c2410_gpio_getpin(gpio)
-#define gpio_set_value(gpio,value)      s3c2410_gpio_setpin(gpio, value)
-
-#include <asm-generic/gpio.h>                   /* cansleep wrappers */
-
-#ifdef CONFIG_CPU_S3C2400
-#define gpio_to_irq(gpio)               s3c2400_gpio_getirq(gpio)
-#else
-#define gpio_to_irq(gpio)               s3c2410_gpio_getirq(gpio)
-#endif
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
 
-/* FIXME implement irq_to_gpio() */
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
 
-#endif
+#include <asm-generic/gpio.h>
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index ecae9e7f5e45..37661358b42b 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -189,6 +189,8 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
 #define S3C2412_CLKSRC_I2SCLK_MPLL              (1<<9)
 #define S3C2412_CLKSRC_USBCLK_HCLK              (1<<10)
 #define S3C2412_CLKSRC_CAMCLK_HCLK              (1<<11)
+#define S3C2412_CLKSRC_UREFCLK_EXTCLK   (1<<12)
+#define S3C2412_CLKSRC_EREFCLK_EXTCLK   (1<<14)
 
 #endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
 
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index fce832820825..911393b2c6f0 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -56,6 +56,21 @@
 #endif
 
 /*
+ * This can be used to enable code to cacheline align the destination
+ * pointer when bulk writing to memory.  Experiments on StrongARM and
+ * XScale didn't show this a worthwhile thing to do when the cache is not
+ * set to write-allocate (this would need further testing on XScale when WA
+ * is used).
+ *
+ * On Feroceon there is much to gain however, regardless of cache mode.
+ */
+#ifdef CONFIG_CPU_FEROCEON
+#define CALGN(code...) code
+#else
+#define CALGN(code...)
+#endif
+
+/*
  * Enable and disable interrupts
  */
 #if __LINUX_ARM_ARCH__ >= 6
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 759a97b56eed..70b0fe724b62 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -95,11 +95,7 @@
 #endif
 
 #if defined(CONFIG_CPU_FEROCEON)
-# ifdef _CACHE
-#  define MULTI_CACHE 1
-# else
-#  define _CACHE feroceon
-# endif
+# define MULTI_CACHE 1
 #endif
 
 #if defined(CONFIG_CPU_V6)
@@ -410,6 +406,13 @@ extern void flush_dcache_page(struct page *);
 
 extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
 
+static inline void __flush_icache_all(void)
+{
+        asm("mcr        p15, 0, %0, c7, c5, 0   @ invalidate I-cache\n"
+            :
+            : "r" (0));
+}
+
 #define ARCH_HAS_FLUSH_ANON_PAGE
 static inline void flush_anon_page(struct vm_area_struct *vma,
                          struct page *page, unsigned long vmaddr)
diff --git a/include/asm-arm/dyntick.h b/include/asm-arm/dyntick.h
deleted file mode 100644
index 19fab2d2b760..000000000000
--- a/include/asm-arm/dyntick.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASMARM_DYNTICK_H
-#define _ASMARM_DYNTICK_H
-
-#include <asm/mach/time.h>
-
-#endif /* _ASMARM_DYNTICK_H */
diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h
index 684fe0645239..5e22881a630d 100644
--- a/include/asm-arm/ecard.h
+++ b/include/asm-arm/ecard.h
@@ -85,19 +85,6 @@
 
 #define MAX_ECARDS      9
 
-typedef enum {                          /* Cards address space          */
-        ECARD_IOC,
-        ECARD_MEMC,
-        ECARD_EASI
-} card_type_t;
-
-typedef enum {                          /* Speed for ECARD_IOC space    */
-        ECARD_SLOW       = 0,
-        ECARD_MEDIUM     = 1,
-        ECARD_FAST       = 2,
-        ECARD_SYNC       = 3
-} card_speed_t;
-
 struct ecard_id {                       /* Card ID structure            */
         unsigned short  manufacturer;
         unsigned short  product;
@@ -190,16 +177,6 @@ struct in_chunk_dir {
 };
 
 /*
- * ecard_claim: claim an expansion card entry
- */
-#define ecard_claim(ec) ((ec)->claimed = 1)
-
-/*
- * ecard_release: release an expansion card entry
- */
-#define ecard_release(ec) ((ec)->claimed = 0)
-
-/*
  * Read a chunk from an expansion card
  * cd : where to put read data
  * ec : expansion card info struct
@@ -209,18 +186,6 @@ struct in_chunk_dir {
 extern int ecard_readchunk (struct in_chunk_dir *cd, struct expansion_card *ec, int id, int num);
 
 /*
- * Obtain the address of a card.  This returns the "old style" address
- * and should no longer be used.
- */
-static inline unsigned int __deprecated
-ecard_address(struct expansion_card *ec, card_type_t type, card_speed_t speed)
-{
-        extern unsigned int __ecard_address(struct expansion_card *,
-                                            card_type_t, card_speed_t);
-        return __ecard_address(ec, type, speed);
-}
-
-/*
  * Request and release ecard resources
  */
 extern int ecard_request_resources(struct expansion_card *ec);
diff --git a/include/asm-arm/hardware/iop3xx-gpio.h b/include/asm-arm/hardware/iop3xx-gpio.h
new file mode 100644
index 000000000000..0c9331f9ac24
--- /dev/null
+++ b/include/asm-arm/hardware/iop3xx-gpio.h
@@ -0,0 +1,73 @@
+/*
+ * linux/include/asm-arm/hardware/iop3xx-gpio.h
+ *
+ * IOP3xx GPIO wrappers
+ *
+ * Copyright (c) 2008 Arnaud Patard <arnaud.patard@rtp-net.org>
+ * Based on IXP4XX gpio.h file
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_HARDWARE_IOP3XX_GPIO_H
+#define __ASM_ARM_HARDWARE_IOP3XX_GPIO_H
+
+#include <asm/hardware.h>
+#include <asm-generic/gpio.h>
+
+#define IOP3XX_N_GPIOS  8
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        if (gpio > IOP3XX_N_GPIOS)
+                return __gpio_get_value(gpio);
+
+        return gpio_line_get(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        if (gpio > IOP3XX_N_GPIOS) {
+                __gpio_set_value(gpio, value);
+                return;
+        }
+        gpio_line_set(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned gpio)
+{
+        if (gpio < IOP3XX_N_GPIOS)
+                return 0;
+        else
+                return __gpio_cansleep(gpio);
+}
+
+/*
+ * The GPIOs are not generating any interrupt
+ * Note : manuals are not clear about this
+ */
+static inline int gpio_to_irq(int gpio)
+{
+        return -EINVAL;
+}
+
+static inline int irq_to_gpio(int gpio)
+{
+        return -EINVAL;
+}
+
+#endif
+
diff --git a/include/asm-arm/hw_irq.h b/include/asm-arm/hw_irq.h
index 98d594a973d6..f1a08a500604 100644
--- a/include/asm-arm/hw_irq.h
+++ b/include/asm-arm/hw_irq.h
@@ -6,15 +6,4 @@
 
 #include <asm/mach/irq.h>
 
-#if defined(CONFIG_NO_IDLE_HZ)
-# include <asm/dyntick.h>
-# define handle_dynamic_tick(action)                                    \
-        if (!(action->flags & IRQF_TIMER) && system_timer->dyn_tick) {  \
-                write_seqlock(&xtime_lock);                             \
-                if (system_timer->dyn_tick->state & DYN_TICK_ENABLED)   \
-                        system_timer->dyn_tick->handler(irq, NULL);     \
-                write_sequnlock(&xtime_lock);                           \
-        }
-#endif
-
 #endif
diff --git a/include/asm-arm/kexec.h b/include/asm-arm/kexec.h
index 47fe34d692da..c8986bb99ed5 100644
--- a/include/asm-arm/kexec.h
+++ b/include/asm-arm/kexec.h
@@ -14,8 +14,6 @@
 
 #define KEXEC_ARCH KEXEC_ARCH_ARM
 
-#define KEXEC_BOOT_PARAMS_SIZE 1536
-
 #define KEXEC_ARM_ATAGS_OFFSET  0x1000
 #define KEXEC_ARM_ZIMAGE_OFFSET 0x8000
 
diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h
index 5dc357013b79..2fd36ea0130d 100644
--- a/include/asm-arm/mach/time.h
+++ b/include/asm-arm/mach/time.h
@@ -41,30 +41,8 @@ struct sys_timer {
 #ifndef CONFIG_GENERIC_TIME
         unsigned long           (*offset)(void);
 #endif
-
-#ifdef CONFIG_NO_IDLE_HZ
-        struct dyn_tick_timer   *dyn_tick;
-#endif
-};
-
-#ifdef CONFIG_NO_IDLE_HZ
-
-#define DYN_TICK_ENABLED        (1 << 1)
-
-struct dyn_tick_timer {
-        spinlock_t      lock;
-        unsigned int    state;                  /* Current state */
-        int             (*enable)(void);        /* Enables dynamic tick */
-        int             (*disable)(void);       /* Disables dynamic tick */
-        void            (*reprogram)(unsigned long); /* Reprograms the timer */
-        int             (*handler)(int, void *);
 };
 
-void timer_dyn_reprogram(void);
-#else
-#define timer_dyn_reprogram()   do { } while (0)
-#endif
-
 extern struct sys_timer *system_timer;
 extern void timer_tick(void);
 
diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h
index 6913d02ca5d6..91b9dfdfed52 100644
--- a/include/asm-arm/mmu_context.h
+++ b/include/asm-arm/mmu_context.h
@@ -97,6 +97,11 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 #ifdef CONFIG_MMU
         unsigned int cpu = smp_processor_id();
 
+#ifdef CONFIG_SMP
+        /* check for possible thread migration */
+        if (!cpus_empty(next->cpu_vm_mask) && !cpu_isset(cpu, next->cpu_vm_mask))
+                __flush_icache_all();
+#endif
         if (!cpu_test_and_set(cpu, next->cpu_vm_mask) || prev != next) {
                 check_context(next);
                 cpu_switch_mm(next->pgd, next);
diff --git a/include/asm-arm/plat-orion/cache-feroceon-l2.h b/include/asm-arm/plat-orion/cache-feroceon-l2.h
new file mode 100644
index 000000000000..ba4e016d3ec0
--- /dev/null
+++ b/include/asm-arm/plat-orion/cache-feroceon-l2.h
@@ -0,0 +1,11 @@
+/*
+ * include/asm-arm/plat-orion/cache-feroceon-l2.h
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+extern void __init feroceon_l2_init(int l2_wt_override);
diff --git a/include/asm-arm/plat-orion/orion_nand.h b/include/asm-arm/plat-orion/orion_nand.h
index ffd3852a0dd7..ad4ce94c1998 100644
--- a/include/asm-arm/plat-orion/orion_nand.h
+++ b/include/asm-arm/plat-orion/orion_nand.h
@@ -18,6 +18,7 @@ struct orion_nand_data {
         u8 ale;         /* address line number connected to ALE */
         u8 cle;         /* address line number connected to CLE */
         u8 width;       /* buswidth */
+        u8 chip_delay;
 };
 
 
diff --git a/include/asm-arm/plat-orion/pcie.h b/include/asm-arm/plat-orion/pcie.h
index 6434ac685d21..e61b7bd97af5 100644
--- a/include/asm-arm/plat-orion/pcie.h
+++ b/include/asm-arm/plat-orion/pcie.h
@@ -14,6 +14,7 @@
 u32 orion_pcie_dev_id(void __iomem *base);
 u32 orion_pcie_rev(void __iomem *base);
 int orion_pcie_link_up(void __iomem *base);
+int orion_pcie_x4_mode(void __iomem *base);
 int orion_pcie_get_local_bus_nr(void __iomem *base);
 void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
 void orion_pcie_setup(void __iomem *base,
diff --git a/include/asm-arm/plat-s3c/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h
index 8b0d594397b1..b5bc692f3489 100644
--- a/include/asm-arm/plat-s3c/regs-timer.h
+++ b/include/asm-arm/plat-s3c/regs-timer.h
@@ -65,6 +65,15 @@
 #define S3C2410_TCFG1_MUX0_TCLK0  (4<<0)
 #define S3C2410_TCFG1_MUX0_MASK   (15<<0)
 
+#define S3C2410_TCFG1_MUX_DIV2    (0<<0)
+#define S3C2410_TCFG1_MUX_DIV4    (1<<0)
+#define S3C2410_TCFG1_MUX_DIV8    (2<<0)
+#define S3C2410_TCFG1_MUX_DIV16   (3<<0)
+#define S3C2410_TCFG1_MUX_TCLK    (4<<0)
+#define S3C2410_TCFG1_MUX_MASK    (15<<0)
+
+#define S3C2410_TCFG1_SHIFT(x)    ((x) * 4)
+
 /* for each timer, we have an count buffer, an compare buffer and
  * an observation buffer
 */
diff --git a/include/asm-arm/plat-s3c24xx/devs.h b/include/asm-arm/plat-s3c24xx/devs.h
index f9d6f0317bc1..badaac9d64a8 100644
--- a/include/asm-arm/plat-s3c24xx/devs.h
+++ b/include/asm-arm/plat-s3c24xx/devs.h
@@ -21,6 +21,8 @@ extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
 extern struct platform_device *s3c24xx_uart_devs[];
 extern struct platform_device *s3c24xx_uart_src[];
 
+extern struct platform_device s3c_device_timer[];
+
 extern struct platform_device s3c_device_usb;
 extern struct platform_device s3c_device_lcd;
 extern struct platform_device s3c_device_wdt;
@@ -36,11 +38,6 @@ extern struct platform_device s3c_device_spi1;
 
 extern struct platform_device s3c_device_nand;
 
-extern struct platform_device s3c_device_timer0;
-extern struct platform_device s3c_device_timer1;
-extern struct platform_device s3c_device_timer2;
-extern struct platform_device s3c_device_timer3;
-
 extern struct platform_device s3c_device_usbgadget;
 
 /* s3c2440 specific devices */
diff --git a/include/asm-arm/rtc.h b/include/asm-arm/rtc.h
deleted file mode 100644
index 1a5c9232a91e..000000000000
--- a/include/asm-arm/rtc.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- *  linux/include/asm-arm/rtc.h
- *
- *  Copyright (C) 2003 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_RTC_H
-#define ASMARM_RTC_H
-
-struct module;
-
-struct rtc_ops {
-        struct module   *owner;
-        int             (*open)(void);
-        void            (*release)(void);
-        int             (*ioctl)(unsigned int, unsigned long);
-
-        int             (*read_time)(struct rtc_time *);
-        int             (*set_time)(struct rtc_time *);
-        int             (*read_alarm)(struct rtc_wkalrm *);
-        int             (*set_alarm)(struct rtc_wkalrm *);
-        int             (*proc)(char *buf);
-};
-
-void rtc_next_alarm_time(struct rtc_time *, struct rtc_time *, struct rtc_time *);
-void rtc_update(unsigned long, unsigned long);
-int register_rtc(struct rtc_ops *);
-void unregister_rtc(struct rtc_ops *);
-
-static inline int rtc_periodic_alarm(struct rtc_time *tm)
-{
-        return  (tm->tm_year == -1) ||
-                ((unsigned)tm->tm_mon >= 12) ||
-                ((unsigned)(tm->tm_mday - 1) >= 31) ||
-                ((unsigned)tm->tm_hour > 23) ||
-                ((unsigned)tm->tm_min > 59) ||
-                ((unsigned)tm->tm_sec > 59);
-}
-
-#endif
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 8c6bc1bb9d1a..909656c747ef 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -39,6 +39,7 @@
 #define TLB_V6_D_ASID   (1 << 17)
 #define TLB_V6_I_ASID   (1 << 18)
 
+#define TLB_L2CLEAN_FR  (1 << 29)               /* Feroceon */
 #define TLB_DCLEAN      (1 << 30)
 #define TLB_WB          (1 << 31)
 
@@ -51,6 +52,7 @@
  *        v4    - ARMv4 without write buffer
  *        v4wb  - ARMv4 with write buffer without I TLB flush entry instruction
  *        v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
+ *        fr    - Feroceon (v4wbi with non-outer-cacheable page table walks)
  *        v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
  */
 #undef _TLB
@@ -103,6 +105,23 @@
 # define v4wbi_always_flags     (-1UL)
 #endif
 
+#define fr_tlb_flags    (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \
+                         TLB_V4_I_FULL | TLB_V4_D_FULL | \
+                         TLB_V4_I_PAGE | TLB_V4_D_PAGE)
+
+#ifdef CONFIG_CPU_TLB_FEROCEON
+# define fr_possible_flags      fr_tlb_flags
+# define fr_always_flags        fr_tlb_flags
+# ifdef _TLB
+#  define MULTI_TLB 1
+# else
+#  define _TLB v4wbi
+# endif
+#else
+# define fr_possible_flags      0
+# define fr_always_flags        (-1UL)
+#endif
+
 #define v4wb_tlb_flags  (TLB_WB | TLB_DCLEAN | \
                          TLB_V4_I_FULL | TLB_V4_D_FULL | \
                          TLB_V4_D_PAGE)
@@ -245,12 +264,14 @@ extern struct cpu_tlb_fns cpu_tlb;
 #define possible_tlb_flags      (v3_possible_flags | \
                                  v4_possible_flags | \
                                  v4wbi_possible_flags | \
+                                 fr_possible_flags | \
                                  v4wb_possible_flags | \
                                  v6wbi_possible_flags)
 
 #define always_tlb_flags        (v3_always_flags & \
                                  v4_always_flags & \
                                  v4wbi_always_flags & \
+                                 fr_always_flags & \
                                  v4wb_always_flags & \
                                  v6wbi_always_flags)
 
@@ -417,6 +438,11 @@ static inline void flush_pmd_entry(pmd_t *pmd)
         if (tlb_flag(TLB_DCLEAN))
                 asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
                         : : "r" (pmd) : "cc");
+
+        if (tlb_flag(TLB_L2CLEAN_FR))
+                asm("mcr        p15, 1, %0, c15, c9, 1  @ L2 flush_pmd"
+                        : : "r" (pmd) : "cc");
+
         if (tlb_flag(TLB_WB))
                 dsb();
 }
@@ -428,6 +454,10 @@ static inline void clean_pmd_entry(pmd_t *pmd)
         if (tlb_flag(TLB_DCLEAN))
                 asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
                         : : "r" (pmd) : "cc");
+
+        if (tlb_flag(TLB_L2CLEAN_FR))
+                asm("mcr        p15, 1, %0, c15, c9, 1  @ L2 flush_pmd"
+                        : : "r" (pmd) : "cc");
 }
 
 #undef tlb_flag
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
new file mode 100644
index 000000000000..3945f803d514
--- /dev/null
+++ b/include/linux/pwm.h
@@ -0,0 +1,31 @@
+#ifndef __LINUX_PWM_H
+#define __LINUX_PWM_H
+
+struct pwm_device;
+
+/*
+ * pwm_request - request a PWM device
+ */
+struct pwm_device *pwm_request(int pwm_id, const char *label);
+
+/*
+ * pwm_free - free a PWM device
+ */
+void pwm_free(struct pwm_device *pwm);
+
+/*
+ * pwm_config - change a PWM device configuration
+ */
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns);
+
+/*
+ * pwm_enable - start a PWM output toggling
+ */
+int pwm_enable(struct pwm_device *pwm);
+
+/*
+ * pwm_disable - stop a PWM output toggling
+ */
+void pwm_disable(struct pwm_device *pwm);
+
+#endif /* __ASM_ARCH_PWM_H */
diff --git a/include/linux/pwm_backlight.h b/include/linux/pwm_backlight.h
new file mode 100644
index 000000000000..7a9754c96775
--- /dev/null
+++ b/include/linux/pwm_backlight.h
@@ -0,0 +1,17 @@
+/*
+ * Generic PWM backlight driver data - see drivers/video/backlight/pwm_bl.c
+ */
+#ifndef __LINUX_PWM_BACKLIGHT_H
+#define __LINUX_PWM_BACKLIGHT_H
+
+struct platform_pwm_backlight_data {
+        int pwm_id;
+        unsigned int max_brightness;
+        unsigned int dft_brightness;
+        unsigned int pwm_period_ns;
+        int (*init)(struct device *dev);
+        int (*notify)(int brightness);
+        void (*exit)(struct device *dev);
+};
+
+#endif
diff --git a/kernel/hrtimer.c b/kernel/hrtimer.c
index e0da4fc9f931..27a83ee41443 100644
--- a/kernel/hrtimer.c
+++ b/kernel/hrtimer.c
@@ -1086,7 +1086,7 @@ ktime_t hrtimer_get_remaining(const struct hrtimer *timer)
 }
 EXPORT_SYMBOL_GPL(hrtimer_get_remaining);
 
-#if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
+#ifdef CONFIG_NO_HZ
 /**
  * hrtimer_get_next_event - get the time until next expiry event
  *
diff --git a/kernel/sysctl.c b/kernel/sysctl.c
index 18943985ddee..0d562d6531eb 100644
--- a/kernel/sysctl.c
+++ b/kernel/sysctl.c
@@ -133,8 +133,6 @@ extern int sysctl_userprocess_debug;
 extern int spin_retry;
 #endif
 
-extern int sysctl_hz_timer;
-
 #ifdef CONFIG_BSD_PROCESS_ACCT
 extern int acct_parm[];
 #endif
@@ -582,16 +580,6 @@ static struct ctl_table kern_table[] = {
                 .proc_handler   = &proc_dointvec,
         },
 #endif
-#ifdef CONFIG_NO_IDLE_HZ
-        {
-                .ctl_name       = KERN_HZ_TIMER,
-                .procname       = "hz_timer",
-                .data           = &sysctl_hz_timer,
-                .maxlen         = sizeof(int),
-                .mode           = 0644,
-                .proc_handler   = &proc_dointvec,
-        },
-#endif
         {
                 .ctl_name       = KERN_S390_USER_DEBUG_LOGGING,
                 .procname       = "userprocess_debug",
diff --git a/kernel/timer.c b/kernel/timer.c
index b4da888497fa..03bc7f1f1593 100644
--- a/kernel/timer.c
+++ b/kernel/timer.c
@@ -812,7 +812,7 @@ static inline void __run_timers(struct tvec_base *base)
         spin_unlock_irq(&base->lock);
 }
 
-#if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
+#ifdef CONFIG_NO_HZ
 /*
  * Find out when the next timer event is due to happen. This
  * is used on S/390 to stop all activity when a cpus is idle.
@@ -947,14 +947,6 @@ unsigned long get_next_timer_interrupt(unsigned long now)
 
         return cmp_next_hrtimer_event(now, expires);
 }
-
-#ifdef CONFIG_NO_IDLE_HZ
-unsigned long next_timer_interrupt(void)
-{
-        return get_next_timer_interrupt(jiffies);
-}
-#endif
-
 #endif
 
 #ifndef CONFIG_VIRT_CPU_ACCOUNTING
diff --git a/sound/soc/at91/at91-ssc.c b/sound/soc/at91/at91-ssc.c
index c3625b665c5a..090e607f8692 100644
--- a/sound/soc/at91/at91-ssc.c
+++ b/sound/soc/at91/at91-ssc.c
@@ -41,7 +41,7 @@
 #define DBG(x...)
 #endif
 
-#if defined(CONFIG_ARCH_AT91SAM9260)
+#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
 #define NUM_SSC_DEVICES         1
 #else
 #define NUM_SSC_DEVICES         3
diff --git a/sound/soc/pxa/pxa2xx-i2s.c b/sound/soc/pxa/pxa2xx-i2s.c
index 9c06553b9267..8f96d87f7b4b 100644
--- a/sound/soc/pxa/pxa2xx-i2s.c
+++ b/sound/soc/pxa/pxa2xx-i2s.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/device.h>
 #include <linux/delay.h>
+#include <linux/clk.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/initval.h>
@@ -37,6 +38,7 @@ struct pxa_i2s_port {
         u32 fmt;
 };
 static struct pxa_i2s_port pxa_i2s;
+static struct clk *clk_i2s;
 
 static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
         .name                   = "I2S PCM Stereo out",
@@ -79,6 +81,10 @@ static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream)
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 
+        clk_i2s = clk_get(NULL, "I2SCLK");
+        if (IS_ERR(clk_i2s))
+                return PTR_ERR(clk_i2s);
+
         if (!cpu_dai->active) {
                 SACR0 |= SACR0_RST;
                 SACR0 = 0;
@@ -146,7 +152,7 @@ static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
         pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx);
         pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm);
         pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk);
-        pxa_set_cken(CKEN_I2S, 1);
+        clk_enable(clk_i2s);
         pxa_i2s_wait();
 
         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
@@ -231,8 +237,10 @@ static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream)
         if (SACR1 & (SACR1_DREC | SACR1_DRPL)) {
                 SACR0 &= ~SACR0_ENB;
                 pxa_i2s_wait();
-                pxa_set_cken(CKEN_I2S, 0);
+                clk_disable(clk_i2s);
         }
+
+        clk_put(clk_i2s);
 }
 
 #ifdef CONFIG_PM